├── .cproject
├── .gitignore
├── .project
├── .settings
├── com.atollic.truestudio.debug.hardware_device.prefs
├── language.settings.xml
├── org.eclipse.cdt.codan.core.prefs
└── org.eclipse.cdt.managedbuilder.core.prefs
├── LIN_Example_F103.elf.launch
├── Libraries
├── CMSIS
│ └── Include
│ │ ├── arm_common_tables.h
│ │ ├── arm_math.h
│ │ ├── core_cm3.h
│ │ ├── core_cmFunc.h
│ │ └── core_cmInstr.h
└── System_stm32f10x
│ ├── inc
│ ├── stm32f10x.h
│ ├── stm32f1xx_it.h
│ └── system_stm32f10x.h
│ └── src
│ ├── startup_stm32f10x_md.s
│ ├── stm32f1xx_it.c
│ └── system_stm32f10x.c
├── Transceiver Design
└── Transceiver.jpeg
├── ff.txt
├── src
├── inc
│ ├── DS18B20.h
│ ├── LIN_Slave.h
│ ├── SysTick.h
│ ├── dma.h
│ ├── exti.h
│ ├── gpio.h
│ ├── itm.h
│ ├── memcpy.h
│ ├── nvic.h
│ └── usart.h
├── main.c
└── src
│ ├── DS18B20.c
│ ├── LIN_Slave.c
│ ├── SysTick.c
│ ├── dma.c
│ ├── exti.c
│ ├── gpio.c
│ ├── itm.c
│ ├── memcpy.c
│ ├── nvic.c
│ └── usart.c
└── stm32_flash.ld
/.gitignore:
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1 | /Debug/
2 |
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/.project:
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1 |
2 |
3 | LIN_Example_F103
4 |
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9 | org.eclipse.cdt.managedbuilder.core.genmakebuilder
10 | clean,full,incremental,
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15 | org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder
16 | full,incremental,
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22 | org.eclipse.cdt.core.cnature
23 | org.eclipse.cdt.managedbuilder.core.managedBuildNature
24 | org.eclipse.cdt.managedbuilder.core.ScannerConfigNature
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27 |
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/.settings/com.atollic.truestudio.debug.hardware_device.prefs:
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1 | BOARD=None
2 | CODE_LOCATION=FLASH
3 | ENDIAN=Little-endian
4 | MCU=STM32F103C8
5 | MCU_VENDOR=STMicroelectronics
6 | MODEL=Pro
7 | PROBE=ST-LINK
8 | PROJECT_FORMAT_VERSION=2
9 | TARGET=STM32
10 | VERSION=9.0.0
11 | eclipse.preferences.version=1
12 |
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/.settings/language.settings.xml:
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/.settings/org.eclipse.cdt.codan.core.prefs:
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/.settings/org.eclipse.cdt.managedbuilder.core.prefs:
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1 | eclipse.preferences.version=1
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11 | environment/buildEnvironmentLibrary/com.atollic.truestudio.exe.debug.1536710142/appendContributed=true
12 |
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/LIN_Example_F103.elf.launch:
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/Libraries/CMSIS/Include/arm_common_tables.h:
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1 | /* ----------------------------------------------------------------------
2 | * Copyright (C) 2010 ARM Limited. All rights reserved.
3 | *
4 | * $Date: 11. November 2010
5 | * $Revision: V1.0.2
6 | *
7 | * Project: CMSIS DSP Library
8 | * Title: arm_common_tables.h
9 | *
10 | * Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions
11 | *
12 | * Target Processor: Cortex-M4/Cortex-M3
13 | *
14 | * Version 1.0.2 2010/11/11
15 | * Documentation updated.
16 | *
17 | * Version 1.0.1 2010/10/05
18 | * Production release and review comments incorporated.
19 | *
20 | * Version 1.0.0 2010/09/20
21 | * Production release and review comments incorporated.
22 | * -------------------------------------------------------------------- */
23 |
24 | #ifndef _ARM_COMMON_TABLES_H
25 | #define _ARM_COMMON_TABLES_H
26 |
27 | #include "arm_math.h"
28 |
29 | extern uint16_t armBitRevTable[256];
30 | extern q15_t armRecipTableQ15[64];
31 | extern q31_t armRecipTableQ31[64];
32 | extern const q31_t realCoefAQ31[1024];
33 | extern const q31_t realCoefBQ31[1024];
34 |
35 | #endif /* ARM_COMMON_TABLES_H */
36 |
--------------------------------------------------------------------------------
/Libraries/CMSIS/Include/core_cmFunc.h:
--------------------------------------------------------------------------------
1 | /**************************************************************************//**
2 | * @file core_cmFunc.h
3 | * @brief CMSIS Cortex-M Core Function Access Header File
4 | * @version V2.10
5 | * @date 26. July 2011
6 | *
7 | * @note
8 | * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
9 | *
10 | * @par
11 | * ARM Limited (ARM) is supplying this software for use with Cortex-M
12 | * processor based microcontrollers. This file can be freely distributed
13 | * within development tools that are supporting such ARM based processors.
14 | *
15 | * @par
16 | * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
17 | * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
18 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
19 | * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
20 | * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
21 | *
22 | ******************************************************************************/
23 |
24 | #ifndef __CORE_CMFUNC_H
25 | #define __CORE_CMFUNC_H
26 |
27 |
28 | /* ########################### Core Function Access ########################### */
29 | /** \ingroup CMSIS_Core_FunctionInterface
30 | \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
31 | @{
32 | */
33 |
34 | #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
35 | /* ARM armcc specific functions */
36 |
37 | #if (__ARMCC_VERSION < 400677)
38 | #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
39 | #endif
40 |
41 | /* intrinsic void __enable_irq(); */
42 | /* intrinsic void __disable_irq(); */
43 |
44 | /** \brief Get Control Register
45 |
46 | This function returns the content of the Control Register.
47 |
48 | \return Control Register value
49 | */
50 | static __INLINE uint32_t __get_CONTROL(void)
51 | {
52 | register uint32_t __regControl __ASM("control");
53 | return(__regControl);
54 | }
55 |
56 |
57 | /** \brief Set Control Register
58 |
59 | This function writes the given value to the Control Register.
60 |
61 | \param [in] control Control Register value to set
62 | */
63 | static __INLINE void __set_CONTROL(uint32_t control)
64 | {
65 | register uint32_t __regControl __ASM("control");
66 | __regControl = control;
67 | }
68 |
69 |
70 | /** \brief Get ISPR Register
71 |
72 | This function returns the content of the ISPR Register.
73 |
74 | \return ISPR Register value
75 | */
76 | static __INLINE uint32_t __get_IPSR(void)
77 | {
78 | register uint32_t __regIPSR __ASM("ipsr");
79 | return(__regIPSR);
80 | }
81 |
82 |
83 | /** \brief Get APSR Register
84 |
85 | This function returns the content of the APSR Register.
86 |
87 | \return APSR Register value
88 | */
89 | static __INLINE uint32_t __get_APSR(void)
90 | {
91 | register uint32_t __regAPSR __ASM("apsr");
92 | return(__regAPSR);
93 | }
94 |
95 |
96 | /** \brief Get xPSR Register
97 |
98 | This function returns the content of the xPSR Register.
99 |
100 | \return xPSR Register value
101 | */
102 | static __INLINE uint32_t __get_xPSR(void)
103 | {
104 | register uint32_t __regXPSR __ASM("xpsr");
105 | return(__regXPSR);
106 | }
107 |
108 |
109 | /** \brief Get Process Stack Pointer
110 |
111 | This function returns the current value of the Process Stack Pointer (PSP).
112 |
113 | \return PSP Register value
114 | */
115 | static __INLINE uint32_t __get_PSP(void)
116 | {
117 | register uint32_t __regProcessStackPointer __ASM("psp");
118 | return(__regProcessStackPointer);
119 | }
120 |
121 |
122 | /** \brief Set Process Stack Pointer
123 |
124 | This function assigns the given value to the Process Stack Pointer (PSP).
125 |
126 | \param [in] topOfProcStack Process Stack Pointer value to set
127 | */
128 | static __INLINE void __set_PSP(uint32_t topOfProcStack)
129 | {
130 | register uint32_t __regProcessStackPointer __ASM("psp");
131 | __regProcessStackPointer = topOfProcStack;
132 | }
133 |
134 |
135 | /** \brief Get Main Stack Pointer
136 |
137 | This function returns the current value of the Main Stack Pointer (MSP).
138 |
139 | \return MSP Register value
140 | */
141 | static __INLINE uint32_t __get_MSP(void)
142 | {
143 | register uint32_t __regMainStackPointer __ASM("msp");
144 | return(__regMainStackPointer);
145 | }
146 |
147 |
148 | /** \brief Set Main Stack Pointer
149 |
150 | This function assigns the given value to the Main Stack Pointer (MSP).
151 |
152 | \param [in] topOfMainStack Main Stack Pointer value to set
153 | */
154 | static __INLINE void __set_MSP(uint32_t topOfMainStack)
155 | {
156 | register uint32_t __regMainStackPointer __ASM("msp");
157 | __regMainStackPointer = topOfMainStack;
158 | }
159 |
160 |
161 | /** \brief Get Priority Mask
162 |
163 | This function returns the current state of the priority mask bit from the Priority Mask Register.
164 |
165 | \return Priority Mask value
166 | */
167 | static __INLINE uint32_t __get_PRIMASK(void)
168 | {
169 | register uint32_t __regPriMask __ASM("primask");
170 | return(__regPriMask);
171 | }
172 |
173 |
174 | /** \brief Set Priority Mask
175 |
176 | This function assigns the given value to the Priority Mask Register.
177 |
178 | \param [in] priMask Priority Mask
179 | */
180 | static __INLINE void __set_PRIMASK(uint32_t priMask)
181 | {
182 | register uint32_t __regPriMask __ASM("primask");
183 | __regPriMask = (priMask);
184 | }
185 |
186 |
187 | #if (__CORTEX_M >= 0x03)
188 |
189 | /** \brief Enable FIQ
190 |
191 | This function enables FIQ interrupts by clearing the F-bit in the CPSR.
192 | Can only be executed in Privileged modes.
193 | */
194 | #define __enable_fault_irq __enable_fiq
195 |
196 |
197 | /** \brief Disable FIQ
198 |
199 | This function disables FIQ interrupts by setting the F-bit in the CPSR.
200 | Can only be executed in Privileged modes.
201 | */
202 | #define __disable_fault_irq __disable_fiq
203 |
204 |
205 | /** \brief Get Base Priority
206 |
207 | This function returns the current value of the Base Priority register.
208 |
209 | \return Base Priority register value
210 | */
211 | static __INLINE uint32_t __get_BASEPRI(void)
212 | {
213 | register uint32_t __regBasePri __ASM("basepri");
214 | return(__regBasePri);
215 | }
216 |
217 |
218 | /** \brief Set Base Priority
219 |
220 | This function assigns the given value to the Base Priority register.
221 |
222 | \param [in] basePri Base Priority value to set
223 | */
224 | static __INLINE void __set_BASEPRI(uint32_t basePri)
225 | {
226 | register uint32_t __regBasePri __ASM("basepri");
227 | __regBasePri = (basePri & 0xff);
228 | }
229 |
230 |
231 | /** \brief Get Fault Mask
232 |
233 | This function returns the current value of the Fault Mask register.
234 |
235 | \return Fault Mask register value
236 | */
237 | static __INLINE uint32_t __get_FAULTMASK(void)
238 | {
239 | register uint32_t __regFaultMask __ASM("faultmask");
240 | return(__regFaultMask);
241 | }
242 |
243 |
244 | /** \brief Set Fault Mask
245 |
246 | This function assigns the given value to the Fault Mask register.
247 |
248 | \param [in] faultMask Fault Mask value to set
249 | */
250 | static __INLINE void __set_FAULTMASK(uint32_t faultMask)
251 | {
252 | register uint32_t __regFaultMask __ASM("faultmask");
253 | __regFaultMask = (faultMask & (uint32_t)1);
254 | }
255 |
256 | #endif /* (__CORTEX_M >= 0x03) */
257 |
258 |
259 | #if (__CORTEX_M == 0x04)
260 |
261 | /** \brief Get FPSCR
262 |
263 | This function returns the current value of the Floating Point Status/Control register.
264 |
265 | \return Floating Point Status/Control register value
266 | */
267 | static __INLINE uint32_t __get_FPSCR(void)
268 | {
269 | #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
270 | register uint32_t __regfpscr __ASM("fpscr");
271 | return(__regfpscr);
272 | #else
273 | return(0);
274 | #endif
275 | }
276 |
277 |
278 | /** \brief Set FPSCR
279 |
280 | This function assigns the given value to the Floating Point Status/Control register.
281 |
282 | \param [in] fpscr Floating Point Status/Control value to set
283 | */
284 | static __INLINE void __set_FPSCR(uint32_t fpscr)
285 | {
286 | #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
287 | register uint32_t __regfpscr __ASM("fpscr");
288 | __regfpscr = (fpscr);
289 | #endif
290 | }
291 |
292 | #endif /* (__CORTEX_M == 0x04) */
293 |
294 |
295 | #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
296 | /* IAR iccarm specific functions */
297 |
298 | #include
299 |
300 | #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
301 | /* GNU gcc specific functions */
302 |
303 | /** \brief Enable IRQ Interrupts
304 |
305 | This function enables IRQ interrupts by clearing the I-bit in the CPSR.
306 | Can only be executed in Privileged modes.
307 | */
308 | __attribute__( ( always_inline ) ) static __INLINE void __enable_irq(void)
309 | {
310 | __ASM volatile ("cpsie i");
311 | }
312 |
313 |
314 | /** \brief Disable IRQ Interrupts
315 |
316 | This function disables IRQ interrupts by setting the I-bit in the CPSR.
317 | Can only be executed in Privileged modes.
318 | */
319 | __attribute__( ( always_inline ) ) static __INLINE void __disable_irq(void)
320 | {
321 | __ASM volatile ("cpsid i");
322 | }
323 |
324 |
325 | /** \brief Get Control Register
326 |
327 | This function returns the content of the Control Register.
328 |
329 | \return Control Register value
330 | */
331 | __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_CONTROL(void)
332 | {
333 | uint32_t result;
334 |
335 | __ASM volatile ("MRS %0, control" : "=r" (result) );
336 | return(result);
337 | }
338 |
339 |
340 | /** \brief Set Control Register
341 |
342 | This function writes the given value to the Control Register.
343 |
344 | \param [in] control Control Register value to set
345 | */
346 | __attribute__( ( always_inline ) ) static __INLINE void __set_CONTROL(uint32_t control)
347 | {
348 | __ASM volatile ("MSR control, %0" : : "r" (control) );
349 | }
350 |
351 |
352 | /** \brief Get ISPR Register
353 |
354 | This function returns the content of the ISPR Register.
355 |
356 | \return ISPR Register value
357 | */
358 | __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_IPSR(void)
359 | {
360 | uint32_t result;
361 |
362 | __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
363 | return(result);
364 | }
365 |
366 |
367 | /** \brief Get APSR Register
368 |
369 | This function returns the content of the APSR Register.
370 |
371 | \return APSR Register value
372 | */
373 | __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_APSR(void)
374 | {
375 | uint32_t result;
376 |
377 | __ASM volatile ("MRS %0, apsr" : "=r" (result) );
378 | return(result);
379 | }
380 |
381 |
382 | /** \brief Get xPSR Register
383 |
384 | This function returns the content of the xPSR Register.
385 |
386 | \return xPSR Register value
387 | */
388 | __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_xPSR(void)
389 | {
390 | uint32_t result;
391 |
392 | __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
393 | return(result);
394 | }
395 |
396 |
397 | /** \brief Get Process Stack Pointer
398 |
399 | This function returns the current value of the Process Stack Pointer (PSP).
400 |
401 | \return PSP Register value
402 | */
403 | __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PSP(void)
404 | {
405 | register uint32_t result;
406 |
407 | __ASM volatile ("MRS %0, psp\n" : "=r" (result) );
408 | return(result);
409 | }
410 |
411 |
412 | /** \brief Set Process Stack Pointer
413 |
414 | This function assigns the given value to the Process Stack Pointer (PSP).
415 |
416 | \param [in] topOfProcStack Process Stack Pointer value to set
417 | */
418 | __attribute__( ( always_inline ) ) static __INLINE void __set_PSP(uint32_t topOfProcStack)
419 | {
420 | __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) );
421 | }
422 |
423 |
424 | /** \brief Get Main Stack Pointer
425 |
426 | This function returns the current value of the Main Stack Pointer (MSP).
427 |
428 | \return MSP Register value
429 | */
430 | __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_MSP(void)
431 | {
432 | register uint32_t result;
433 |
434 | __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
435 | return(result);
436 | }
437 |
438 |
439 | /** \brief Set Main Stack Pointer
440 |
441 | This function assigns the given value to the Main Stack Pointer (MSP).
442 |
443 | \param [in] topOfMainStack Main Stack Pointer value to set
444 | */
445 | __attribute__( ( always_inline ) ) static __INLINE void __set_MSP(uint32_t topOfMainStack)
446 | {
447 | __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) );
448 | }
449 |
450 |
451 | /** \brief Get Priority Mask
452 |
453 | This function returns the current state of the priority mask bit from the Priority Mask Register.
454 |
455 | \return Priority Mask value
456 | */
457 | __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PRIMASK(void)
458 | {
459 | uint32_t result;
460 |
461 | __ASM volatile ("MRS %0, primask" : "=r" (result) );
462 | return(result);
463 | }
464 |
465 |
466 | /** \brief Set Priority Mask
467 |
468 | This function assigns the given value to the Priority Mask Register.
469 |
470 | \param [in] priMask Priority Mask
471 | */
472 | __attribute__( ( always_inline ) ) static __INLINE void __set_PRIMASK(uint32_t priMask)
473 | {
474 | __ASM volatile ("MSR primask, %0" : : "r" (priMask) );
475 | }
476 |
477 |
478 | #if (__CORTEX_M >= 0x03)
479 |
480 | /** \brief Enable FIQ
481 |
482 | This function enables FIQ interrupts by clearing the F-bit in the CPSR.
483 | Can only be executed in Privileged modes.
484 | */
485 | __attribute__( ( always_inline ) ) static __INLINE void __enable_fault_irq(void)
486 | {
487 | __ASM volatile ("cpsie f");
488 | }
489 |
490 |
491 | /** \brief Disable FIQ
492 |
493 | This function disables FIQ interrupts by setting the F-bit in the CPSR.
494 | Can only be executed in Privileged modes.
495 | */
496 | __attribute__( ( always_inline ) ) static __INLINE void __disable_fault_irq(void)
497 | {
498 | __ASM volatile ("cpsid f");
499 | }
500 |
501 |
502 | /** \brief Get Base Priority
503 |
504 | This function returns the current value of the Base Priority register.
505 |
506 | \return Base Priority register value
507 | */
508 | __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_BASEPRI(void)
509 | {
510 | uint32_t result;
511 |
512 | __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
513 | return(result);
514 | }
515 |
516 |
517 | /** \brief Set Base Priority
518 |
519 | This function assigns the given value to the Base Priority register.
520 |
521 | \param [in] basePri Base Priority value to set
522 | */
523 | __attribute__( ( always_inline ) ) static __INLINE void __set_BASEPRI(uint32_t value)
524 | {
525 | __ASM volatile ("MSR basepri, %0" : : "r" (value) );
526 | }
527 |
528 |
529 | /** \brief Get Fault Mask
530 |
531 | This function returns the current value of the Fault Mask register.
532 |
533 | \return Fault Mask register value
534 | */
535 | __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FAULTMASK(void)
536 | {
537 | uint32_t result;
538 |
539 | __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
540 | return(result);
541 | }
542 |
543 |
544 | /** \brief Set Fault Mask
545 |
546 | This function assigns the given value to the Fault Mask register.
547 |
548 | \param [in] faultMask Fault Mask value to set
549 | */
550 | __attribute__( ( always_inline ) ) static __INLINE void __set_FAULTMASK(uint32_t faultMask)
551 | {
552 | __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );
553 | }
554 |
555 | #endif /* (__CORTEX_M >= 0x03) */
556 |
557 |
558 | #if (__CORTEX_M == 0x04)
559 |
560 | /** \brief Get FPSCR
561 |
562 | This function returns the current value of the Floating Point Status/Control register.
563 |
564 | \return Floating Point Status/Control register value
565 | */
566 | __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FPSCR(void)
567 | {
568 | #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
569 | uint32_t result;
570 |
571 | __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
572 | return(result);
573 | #else
574 | return(0);
575 | #endif
576 | }
577 |
578 |
579 | /** \brief Set FPSCR
580 |
581 | This function assigns the given value to the Floating Point Status/Control register.
582 |
583 | \param [in] fpscr Floating Point Status/Control value to set
584 | */
585 | __attribute__( ( always_inline ) ) static __INLINE void __set_FPSCR(uint32_t fpscr)
586 | {
587 | #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
588 | __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) );
589 | #endif
590 | }
591 |
592 | #endif /* (__CORTEX_M == 0x04) */
593 |
594 |
595 | #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
596 | /* TASKING carm specific functions */
597 |
598 | /*
599 | * The CMSIS functions have been implemented as intrinsics in the compiler.
600 | * Please use "carm -?i" to get an up to date list of all instrinsics,
601 | * Including the CMSIS ones.
602 | */
603 |
604 | #endif
605 |
606 | /*@} end of CMSIS_Core_RegAccFunctions */
607 |
608 |
609 | #endif /* __CORE_CMFUNC_H */
610 |
--------------------------------------------------------------------------------
/Libraries/CMSIS/Include/core_cmInstr.h:
--------------------------------------------------------------------------------
1 | /**************************************************************************//**
2 | * @file core_cmInstr.h
3 | * @brief CMSIS Cortex-M Core Instruction Access Header File
4 | * @version V2.10
5 | * @date 19. July 2011
6 | *
7 | * @note
8 | * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
9 | *
10 | * @par
11 | * ARM Limited (ARM) is supplying this software for use with Cortex-M
12 | * processor based microcontrollers. This file can be freely distributed
13 | * within development tools that are supporting such ARM based processors.
14 | *
15 | * @par
16 | * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
17 | * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
18 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
19 | * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
20 | * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
21 | *
22 | ******************************************************************************/
23 |
24 | #ifndef __CORE_CMINSTR_H
25 | #define __CORE_CMINSTR_H
26 |
27 |
28 | /* ########################## Core Instruction Access ######################### */
29 | /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
30 | Access to dedicated instructions
31 | @{
32 | */
33 |
34 | #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
35 | /* ARM armcc specific functions */
36 |
37 | #if (__ARMCC_VERSION < 400677)
38 | #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
39 | #endif
40 |
41 |
42 | /** \brief No Operation
43 |
44 | No Operation does nothing. This instruction can be used for code alignment purposes.
45 | */
46 | #define __NOP __nop
47 |
48 |
49 | /** \brief Wait For Interrupt
50 |
51 | Wait For Interrupt is a hint instruction that suspends execution
52 | until one of a number of events occurs.
53 | */
54 | #define __WFI __wfi
55 |
56 |
57 | /** \brief Wait For Event
58 |
59 | Wait For Event is a hint instruction that permits the processor to enter
60 | a low-power state until one of a number of events occurs.
61 | */
62 | #define __WFE __wfe
63 |
64 |
65 | /** \brief Send Event
66 |
67 | Send Event is a hint instruction. It causes an event to be signaled to the CPU.
68 | */
69 | #define __SEV __sev
70 |
71 |
72 | /** \brief Instruction Synchronization Barrier
73 |
74 | Instruction Synchronization Barrier flushes the pipeline in the processor,
75 | so that all instructions following the ISB are fetched from cache or
76 | memory, after the instruction has been completed.
77 | */
78 | #define __ISB() __isb(0xF)
79 |
80 |
81 | /** \brief Data Synchronization Barrier
82 |
83 | This function acts as a special kind of Data Memory Barrier.
84 | It completes when all explicit memory accesses before this instruction complete.
85 | */
86 | #define __DSB() __dsb(0xF)
87 |
88 |
89 | /** \brief Data Memory Barrier
90 |
91 | This function ensures the apparent order of the explicit memory operations before
92 | and after the instruction, without ensuring their completion.
93 | */
94 | #define __DMB() __dmb(0xF)
95 |
96 |
97 | /** \brief Reverse byte order (32 bit)
98 |
99 | This function reverses the byte order in integer value.
100 |
101 | \param [in] value Value to reverse
102 | \return Reversed value
103 | */
104 | #define __REV __rev
105 |
106 |
107 | /** \brief Reverse byte order (16 bit)
108 |
109 | This function reverses the byte order in two unsigned short values.
110 |
111 | \param [in] value Value to reverse
112 | \return Reversed value
113 | */
114 | static __INLINE __ASM uint32_t __REV16(uint32_t value)
115 | {
116 | rev16 r0, r0
117 | bx lr
118 | }
119 |
120 |
121 | /** \brief Reverse byte order in signed short value
122 |
123 | This function reverses the byte order in a signed short value with sign extension to integer.
124 |
125 | \param [in] value Value to reverse
126 | \return Reversed value
127 | */
128 | static __INLINE __ASM int32_t __REVSH(int32_t value)
129 | {
130 | revsh r0, r0
131 | bx lr
132 | }
133 |
134 |
135 | #if (__CORTEX_M >= 0x03)
136 |
137 | /** \brief Reverse bit order of value
138 |
139 | This function reverses the bit order of the given value.
140 |
141 | \param [in] value Value to reverse
142 | \return Reversed value
143 | */
144 | #define __RBIT __rbit
145 |
146 |
147 | /** \brief LDR Exclusive (8 bit)
148 |
149 | This function performs a exclusive LDR command for 8 bit value.
150 |
151 | \param [in] ptr Pointer to data
152 | \return value of type uint8_t at (*ptr)
153 | */
154 | #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
155 |
156 |
157 | /** \brief LDR Exclusive (16 bit)
158 |
159 | This function performs a exclusive LDR command for 16 bit values.
160 |
161 | \param [in] ptr Pointer to data
162 | \return value of type uint16_t at (*ptr)
163 | */
164 | #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
165 |
166 |
167 | /** \brief LDR Exclusive (32 bit)
168 |
169 | This function performs a exclusive LDR command for 32 bit values.
170 |
171 | \param [in] ptr Pointer to data
172 | \return value of type uint32_t at (*ptr)
173 | */
174 | #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
175 |
176 |
177 | /** \brief STR Exclusive (8 bit)
178 |
179 | This function performs a exclusive STR command for 8 bit values.
180 |
181 | \param [in] value Value to store
182 | \param [in] ptr Pointer to location
183 | \return 0 Function succeeded
184 | \return 1 Function failed
185 | */
186 | #define __STREXB(value, ptr) __strex(value, ptr)
187 |
188 |
189 | /** \brief STR Exclusive (16 bit)
190 |
191 | This function performs a exclusive STR command for 16 bit values.
192 |
193 | \param [in] value Value to store
194 | \param [in] ptr Pointer to location
195 | \return 0 Function succeeded
196 | \return 1 Function failed
197 | */
198 | #define __STREXH(value, ptr) __strex(value, ptr)
199 |
200 |
201 | /** \brief STR Exclusive (32 bit)
202 |
203 | This function performs a exclusive STR command for 32 bit values.
204 |
205 | \param [in] value Value to store
206 | \param [in] ptr Pointer to location
207 | \return 0 Function succeeded
208 | \return 1 Function failed
209 | */
210 | #define __STREXW(value, ptr) __strex(value, ptr)
211 |
212 |
213 | /** \brief Remove the exclusive lock
214 |
215 | This function removes the exclusive lock which is created by LDREX.
216 |
217 | */
218 | #define __CLREX __clrex
219 |
220 |
221 | /** \brief Signed Saturate
222 |
223 | This function saturates a signed value.
224 |
225 | \param [in] value Value to be saturated
226 | \param [in] sat Bit position to saturate to (1..32)
227 | \return Saturated value
228 | */
229 | #define __SSAT __ssat
230 |
231 |
232 | /** \brief Unsigned Saturate
233 |
234 | This function saturates an unsigned value.
235 |
236 | \param [in] value Value to be saturated
237 | \param [in] sat Bit position to saturate to (0..31)
238 | \return Saturated value
239 | */
240 | #define __USAT __usat
241 |
242 |
243 | /** \brief Count leading zeros
244 |
245 | This function counts the number of leading zeros of a data value.
246 |
247 | \param [in] value Value to count the leading zeros
248 | \return number of leading zeros in value
249 | */
250 | #define __CLZ __clz
251 |
252 | #endif /* (__CORTEX_M >= 0x03) */
253 |
254 |
255 |
256 | #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
257 | /* IAR iccarm specific functions */
258 |
259 | #include
260 |
261 |
262 | #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
263 | /* GNU gcc specific functions */
264 |
265 | /** \brief No Operation
266 |
267 | No Operation does nothing. This instruction can be used for code alignment purposes.
268 | */
269 | __attribute__( ( always_inline ) ) static __INLINE void __NOP(void)
270 | {
271 | __ASM volatile ("nop");
272 | }
273 |
274 |
275 | /** \brief Wait For Interrupt
276 |
277 | Wait For Interrupt is a hint instruction that suspends execution
278 | until one of a number of events occurs.
279 | */
280 | __attribute__( ( always_inline ) ) static __INLINE void __WFI(void)
281 | {
282 | __ASM volatile ("wfi");
283 | }
284 |
285 |
286 | /** \brief Wait For Event
287 |
288 | Wait For Event is a hint instruction that permits the processor to enter
289 | a low-power state until one of a number of events occurs.
290 | */
291 | __attribute__( ( always_inline ) ) static __INLINE void __WFE(void)
292 | {
293 | __ASM volatile ("wfe");
294 | }
295 |
296 |
297 | /** \brief Send Event
298 |
299 | Send Event is a hint instruction. It causes an event to be signaled to the CPU.
300 | */
301 | __attribute__( ( always_inline ) ) static __INLINE void __SEV(void)
302 | {
303 | __ASM volatile ("sev");
304 | }
305 |
306 |
307 | /** \brief Instruction Synchronization Barrier
308 |
309 | Instruction Synchronization Barrier flushes the pipeline in the processor,
310 | so that all instructions following the ISB are fetched from cache or
311 | memory, after the instruction has been completed.
312 | */
313 | __attribute__( ( always_inline ) ) static __INLINE void __ISB(void)
314 | {
315 | __ASM volatile ("isb");
316 | }
317 |
318 |
319 | /** \brief Data Synchronization Barrier
320 |
321 | This function acts as a special kind of Data Memory Barrier.
322 | It completes when all explicit memory accesses before this instruction complete.
323 | */
324 | __attribute__( ( always_inline ) ) static __INLINE void __DSB(void)
325 | {
326 | __ASM volatile ("dsb");
327 | }
328 |
329 |
330 | /** \brief Data Memory Barrier
331 |
332 | This function ensures the apparent order of the explicit memory operations before
333 | and after the instruction, without ensuring their completion.
334 | */
335 | __attribute__( ( always_inline ) ) static __INLINE void __DMB(void)
336 | {
337 | __ASM volatile ("dmb");
338 | }
339 |
340 |
341 | /** \brief Reverse byte order (32 bit)
342 |
343 | This function reverses the byte order in integer value.
344 |
345 | \param [in] value Value to reverse
346 | \return Reversed value
347 | */
348 | __attribute__( ( always_inline ) ) static __INLINE uint32_t __REV(uint32_t value)
349 | {
350 | uint32_t result;
351 |
352 | __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );
353 | return(result);
354 | }
355 |
356 |
357 | /** \brief Reverse byte order (16 bit)
358 |
359 | This function reverses the byte order in two unsigned short values.
360 |
361 | \param [in] value Value to reverse
362 | \return Reversed value
363 | */
364 | __attribute__( ( always_inline ) ) static __INLINE uint32_t __REV16(uint32_t value)
365 | {
366 | uint32_t result;
367 |
368 | __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );
369 | return(result);
370 | }
371 |
372 |
373 | /** \brief Reverse byte order in signed short value
374 |
375 | This function reverses the byte order in a signed short value with sign extension to integer.
376 |
377 | \param [in] value Value to reverse
378 | \return Reversed value
379 | */
380 | __attribute__( ( always_inline ) ) static __INLINE int32_t __REVSH(int32_t value)
381 | {
382 | uint32_t result;
383 |
384 | __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );
385 | return(result);
386 | }
387 |
388 |
389 | #if (__CORTEX_M >= 0x03)
390 |
391 | /** \brief Reverse bit order of value
392 |
393 | This function reverses the bit order of the given value.
394 |
395 | \param [in] value Value to reverse
396 | \return Reversed value
397 | */
398 | __attribute__( ( always_inline ) ) static __INLINE uint32_t __RBIT(uint32_t value)
399 | {
400 | uint32_t result;
401 |
402 | __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
403 | return(result);
404 | }
405 |
406 |
407 | /** \brief LDR Exclusive (8 bit)
408 |
409 | This function performs a exclusive LDR command for 8 bit value.
410 |
411 | \param [in] ptr Pointer to data
412 | \return value of type uint8_t at (*ptr)
413 | */
414 | __attribute__( ( always_inline ) ) static __INLINE uint8_t __LDREXB(volatile uint8_t *addr)
415 | {
416 | uint8_t result;
417 |
418 | __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );
419 | return(result);
420 | }
421 |
422 |
423 | /** \brief LDR Exclusive (16 bit)
424 |
425 | This function performs a exclusive LDR command for 16 bit values.
426 |
427 | \param [in] ptr Pointer to data
428 | \return value of type uint16_t at (*ptr)
429 | */
430 | __attribute__( ( always_inline ) ) static __INLINE uint16_t __LDREXH(volatile uint16_t *addr)
431 | {
432 | uint16_t result;
433 |
434 | __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );
435 | return(result);
436 | }
437 |
438 |
439 | /** \brief LDR Exclusive (32 bit)
440 |
441 | This function performs a exclusive LDR command for 32 bit values.
442 |
443 | \param [in] ptr Pointer to data
444 | \return value of type uint32_t at (*ptr)
445 | */
446 | __attribute__( ( always_inline ) ) static __INLINE uint32_t __LDREXW(volatile uint32_t *addr)
447 | {
448 | uint32_t result;
449 |
450 | __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );
451 | return(result);
452 | }
453 |
454 |
455 | /** \brief STR Exclusive (8 bit)
456 |
457 | This function performs a exclusive STR command for 8 bit values.
458 |
459 | \param [in] value Value to store
460 | \param [in] ptr Pointer to location
461 | \return 0 Function succeeded
462 | \return 1 Function failed
463 | */
464 | __attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
465 | {
466 | uint32_t result;
467 |
468 | __ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
469 | return(result);
470 | }
471 |
472 |
473 | /** \brief STR Exclusive (16 bit)
474 |
475 | This function performs a exclusive STR command for 16 bit values.
476 |
477 | \param [in] value Value to store
478 | \param [in] ptr Pointer to location
479 | \return 0 Function succeeded
480 | \return 1 Function failed
481 | */
482 | __attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
483 | {
484 | uint32_t result;
485 |
486 | __ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
487 | return(result);
488 | }
489 |
490 |
491 | /** \brief STR Exclusive (32 bit)
492 |
493 | This function performs a exclusive STR command for 32 bit values.
494 |
495 | \param [in] value Value to store
496 | \param [in] ptr Pointer to location
497 | \return 0 Function succeeded
498 | \return 1 Function failed
499 | */
500 | __attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
501 | {
502 | uint32_t result;
503 |
504 | __ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
505 | return(result);
506 | }
507 |
508 |
509 | /** \brief Remove the exclusive lock
510 |
511 | This function removes the exclusive lock which is created by LDREX.
512 |
513 | */
514 | __attribute__( ( always_inline ) ) static __INLINE void __CLREX(void)
515 | {
516 | __ASM volatile ("clrex");
517 | }
518 |
519 |
520 | /** \brief Signed Saturate
521 |
522 | This function saturates a signed value.
523 |
524 | \param [in] value Value to be saturated
525 | \param [in] sat Bit position to saturate to (1..32)
526 | \return Saturated value
527 | */
528 | #define __SSAT(ARG1,ARG2) \
529 | ({ \
530 | uint32_t __RES, __ARG1 = (ARG1); \
531 | __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
532 | __RES; \
533 | })
534 |
535 |
536 | /** \brief Unsigned Saturate
537 |
538 | This function saturates an unsigned value.
539 |
540 | \param [in] value Value to be saturated
541 | \param [in] sat Bit position to saturate to (0..31)
542 | \return Saturated value
543 | */
544 | #define __USAT(ARG1,ARG2) \
545 | ({ \
546 | uint32_t __RES, __ARG1 = (ARG1); \
547 | __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
548 | __RES; \
549 | })
550 |
551 |
552 | /** \brief Count leading zeros
553 |
554 | This function counts the number of leading zeros of a data value.
555 |
556 | \param [in] value Value to count the leading zeros
557 | \return number of leading zeros in value
558 | */
559 | __attribute__( ( always_inline ) ) static __INLINE uint8_t __CLZ(uint32_t value)
560 | {
561 | uint8_t result;
562 |
563 | __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
564 | return(result);
565 | }
566 |
567 | #endif /* (__CORTEX_M >= 0x03) */
568 |
569 |
570 |
571 |
572 | #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
573 | /* TASKING carm specific functions */
574 |
575 | /*
576 | * The CMSIS functions have been implemented as intrinsics in the compiler.
577 | * Please use "carm -?i" to get an up to date list of all intrinsics,
578 | * Including the CMSIS ones.
579 | */
580 |
581 | #endif
582 |
583 | /*@}*/ /* end of group CMSIS_Core_InstructionInterface */
584 |
585 | #endif /* __CORE_CMINSTR_H */
586 |
--------------------------------------------------------------------------------
/Libraries/System_stm32f10x/inc/stm32f1xx_it.h:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32f1xx_it.h
4 | * @author MCD Application Team
5 | * @version V1.0.0
6 | * @date 11-February-2014
7 | * @brief This file contains the headers of the interrupt handlers.
8 | ******************************************************************************
9 | * @attention
10 | *
11 | * © COPYRIGHT 2014 STMicroelectronics
12 | *
13 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
14 | * You may not use this file except in compliance with the License.
15 | * You may obtain a copy of the License at:
16 | *
17 | * http://www.st.com/software_license_agreement_liberty_v2
18 | *
19 | * Unless required by applicable law or agreed to in writing, software
20 | * distributed under the License is distributed on an "AS IS" BASIS,
21 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
22 | * See the License for the specific language governing permissions and
23 | * limitations under the License.
24 | *
25 | ******************************************************************************
26 | */
27 |
28 | /* Define to prevent recursive inclusion -------------------------------------*/
29 | #ifndef __STM32F1XX_IT_H
30 | #define __STM32F1XX_IT_H
31 |
32 | #ifdef __cplusplus
33 | extern "C" {
34 | #endif
35 |
36 | /* Includes ------------------------------------------------------------------*/
37 | #include "stm32f10x.h"
38 |
39 | /* Exported types ------------------------------------------------------------*/
40 | /* Exported constants --------------------------------------------------------*/
41 | /* Exported macro ------------------------------------------------------------*/
42 | /* Exported functions ------------------------------------------------------- */
43 |
44 | void NMI_Handler(void);
45 | void HardFault_Handler(void);
46 | void MemManage_Handler(void);
47 | void BusFault_Handler(void);
48 | void UsageFault_Handler(void);
49 | void SVC_Handler(void);
50 | void DebugMon_Handler(void);
51 | void PendSV_Handler(void);
52 | void SysTick_Handler(void);
53 | void EXTI15_10_IRQHandler(void);
54 |
55 | /* STM32F10x Peripherals Interrupt Handlers */
56 | void EXTI0_IRQHandler(void);
57 | void EXTI1_IRQHandler(void);
58 | void EXTI2_IRQHandler(void);
59 | void EXTI3_IRQHandler(void);
60 | void DMA1_Channel4_IRQHandler(void);
61 | void DMA1_Channel5_IRQHandler(void);
62 | void DMA1_Channel2_IRQHandler(void);
63 | void DMA1_Channel3_IRQHandler(void);
64 | void USART1_IRQHandler(void);
65 | void USART3_IRQHandler(void);
66 |
67 | #ifdef __cplusplus
68 | }
69 | #endif
70 |
71 | #endif /* __STM32F1XX_IT_H */
72 |
73 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
74 |
--------------------------------------------------------------------------------
/Libraries/System_stm32f10x/inc/system_stm32f10x.h:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file system_stm32f10x.h
4 | * @author MCD Application Team
5 | * @version V3.6.1
6 | * @date 09-March-2012
7 | * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Header File.
8 | ******************************************************************************
9 | * @attention
10 | *
11 | * © COPYRIGHT 2012 STMicroelectronics
12 | *
13 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
14 | * You may not use this file except in compliance with the License.
15 | * You may obtain a copy of the License at:
16 | *
17 | * http://www.st.com/software_license_agreement_liberty_v2
18 | *
19 | * Unless required by applicable law or agreed to in writing, software
20 | * distributed under the License is distributed on an "AS IS" BASIS,
21 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
22 | * See the License for the specific language governing permissions and
23 | * limitations under the License.
24 | *
25 | ******************************************************************************
26 | */
27 |
28 | /** @addtogroup CMSIS
29 | * @{
30 | */
31 |
32 | /** @addtogroup stm32f10x_system
33 | * @{
34 | */
35 |
36 | /**
37 | * @brief Define to prevent recursive inclusion
38 | */
39 | #ifndef __SYSTEM_STM32F10X_H
40 | #define __SYSTEM_STM32F10X_H
41 |
42 | #ifdef __cplusplus
43 | extern "C" {
44 | #endif
45 |
46 | /** @addtogroup STM32F10x_System_Includes
47 | * @{
48 | */
49 |
50 | /**
51 | * @}
52 | */
53 |
54 |
55 | /** @addtogroup STM32F10x_System_Exported_types
56 | * @{
57 | */
58 |
59 | extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
60 |
61 | /**
62 | * @}
63 | */
64 |
65 | /** @addtogroup STM32F10x_System_Exported_Constants
66 | * @{
67 | */
68 |
69 | /**
70 | * @}
71 | */
72 |
73 | /** @addtogroup STM32F10x_System_Exported_Macros
74 | * @{
75 | */
76 |
77 | /**
78 | * @}
79 | */
80 |
81 | /** @addtogroup STM32F10x_System_Exported_Functions
82 | * @{
83 | */
84 |
85 | extern void SystemInit(void);
86 | extern void SystemCoreClockUpdate(void);
87 | /**
88 | * @}
89 | */
90 |
91 | #ifdef __cplusplus
92 | }
93 | #endif
94 |
95 | #endif /*__SYSTEM_STM32F10X_H */
96 |
97 | /**
98 | * @}
99 | */
100 |
101 | /**
102 | * @}
103 | */
104 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
105 |
--------------------------------------------------------------------------------
/Libraries/System_stm32f10x/src/startup_stm32f10x_md.s:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file startup_stm32f10x_md.s
4 | * @author MCD Application Team
5 | * @version V3.6.1
6 | * @date 09-March-2012
7 | * @brief STM32F10x Medium Density Devices vector table for Atollic toolchain.
8 | * This module performs:
9 | * - Set the initial SP
10 | * - Set the initial PC == Reset_Handler,
11 | * - Set the vector table entries with the exceptions ISR address
12 | * - Configure the clock system
13 | * - Branches to main in the C library (which eventually
14 | * calls main()).
15 | * After Reset the Cortex-M3 processor is in Thread mode,
16 | * priority is Privileged, and the Stack is set to Main.
17 | ******************************************************************************
18 | * @attention
19 | *
20 | * © COPYRIGHT 2012 STMicroelectronics
21 | *
22 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
23 | * You may not use this file except in compliance with the License.
24 | * You may obtain a copy of the License at:
25 | *
26 | * http://www.st.com/software_license_agreement_liberty_v2
27 | *
28 | * Unless required by applicable law or agreed to in writing, software
29 | * distributed under the License is distributed on an "AS IS" BASIS,
30 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
31 | * See the License for the specific language governing permissions and
32 | * limitations under the License.
33 | *
34 | ******************************************************************************
35 | */
36 |
37 | .syntax unified
38 | .cpu cortex-m3
39 | .fpu softvfp
40 | .thumb
41 |
42 | .global g_pfnVectors
43 | .global Default_Handler
44 |
45 | /* start address for the initialization values of the .data section.
46 | defined in linker script */
47 | .word _sidata
48 | /* start address for the .data section. defined in linker script */
49 | .word _sdata
50 | /* end address for the .data section. defined in linker script */
51 | .word _edata
52 | /* start address for the .bss section. defined in linker script */
53 | .word _sbss
54 | /* end address for the .bss section. defined in linker script */
55 | .word _ebss
56 |
57 | .equ BootRAM, 0xF108F85F
58 | /**
59 | * @brief This is the code that gets called when the processor first
60 | * starts execution following a reset event. Only the absolutely
61 | * necessary set is performed, after which the application
62 | * supplied main() routine is called.
63 | * @param None
64 | * @retval : None
65 | */
66 |
67 | .section .text.Reset_Handler
68 | .weak Reset_Handler
69 | .type Reset_Handler, %function
70 | Reset_Handler:
71 | ldr sp, =_estack /* Atollic update: set stack pointer */
72 |
73 | /* Disable interrupt (set PRIMASK) */
74 | CPSID i
75 |
76 | /* Copy the data segment initializers from flash to SRAM */
77 | movs r1, #0
78 | b LoopCopyDataInit
79 |
80 | CopyDataInit:
81 | ldr r3, =_sidata
82 | ldr r3, [r3, r1]
83 | str r3, [r0, r1]
84 | adds r1, r1, #4
85 |
86 | LoopCopyDataInit:
87 | ldr r0, =_sdata
88 | ldr r3, =_edata
89 | adds r2, r0, r1
90 | cmp r2, r3
91 | bcc CopyDataInit
92 | ldr r2, =_sbss
93 | b LoopFillZerobss
94 | /* Zero fill the bss segment. */
95 | FillZerobss:
96 | movs r3, #0
97 | str r3, [r2], #4
98 |
99 | LoopFillZerobss:
100 | ldr r3, = _ebss
101 | cmp r2, r3
102 | bcc FillZerobss
103 |
104 | /* Call the clock system intitialization function.*/
105 | bl SystemInit
106 | /* Call static constructors */
107 | bl __libc_init_array
108 | /* Call the application's entry point.*/
109 | bl main
110 | bx lr
111 | .size Reset_Handler, .-Reset_Handler
112 |
113 | /**
114 | * @brief This is the code that gets called when the processor receives an
115 | * unexpected interrupt. This simply enters an infinite loop, preserving
116 | * the system state for examination by a debugger.
117 | *
118 | * @param None
119 | * @retval : None
120 | */
121 | .section .text.Default_Handler,"ax",%progbits
122 | Default_Handler:
123 | Infinite_Loop:
124 | b Infinite_Loop
125 | .size Default_Handler, .-Default_Handler
126 | /******************************************************************************
127 | *
128 | * The minimal vector table for a Cortex M3. Note that the proper constructs
129 | * must be placed on this to ensure that it ends up at physical address
130 | * 0x0000.0000.
131 | *
132 | ******************************************************************************/
133 | .section .isr_vector,"a",%progbits
134 | .type g_pfnVectors, %object
135 | .size g_pfnVectors, .-g_pfnVectors
136 |
137 |
138 | g_pfnVectors:
139 | .word _estack
140 | .word Reset_Handler
141 | .word NMI_Handler
142 | .word HardFault_Handler
143 | .word MemManage_Handler
144 | .word BusFault_Handler
145 | .word UsageFault_Handler
146 | .word 0
147 | .word 0
148 | .word 0
149 | .word 0
150 | .word SVC_Handler
151 | .word DebugMon_Handler
152 | .word 0
153 | .word PendSV_Handler
154 | .word SysTick_Handler
155 | .word WWDG_IRQHandler
156 | .word PVD_IRQHandler
157 | .word TAMPER_IRQHandler
158 | .word RTC_IRQHandler
159 | .word FLASH_IRQHandler
160 | .word RCC_IRQHandler
161 | .word EXTI0_IRQHandler
162 | .word EXTI1_IRQHandler
163 | .word EXTI2_IRQHandler
164 | .word EXTI3_IRQHandler
165 | .word EXTI4_IRQHandler
166 | .word DMA1_Channel1_IRQHandler
167 | .word DMA1_Channel2_IRQHandler
168 | .word DMA1_Channel3_IRQHandler
169 | .word DMA1_Channel4_IRQHandler
170 | .word DMA1_Channel5_IRQHandler
171 | .word DMA1_Channel6_IRQHandler
172 | .word DMA1_Channel7_IRQHandler
173 | .word ADC1_2_IRQHandler
174 | .word USB_HP_CAN1_TX_IRQHandler
175 | .word USB_LP_CAN1_RX0_IRQHandler
176 | .word CAN1_RX1_IRQHandler
177 | .word CAN1_SCE_IRQHandler
178 | .word EXTI9_5_IRQHandler
179 | .word TIM1_BRK_IRQHandler
180 | .word TIM1_UP_IRQHandler
181 | .word TIM1_TRG_COM_IRQHandler
182 | .word TIM1_CC_IRQHandler
183 | .word TIM2_IRQHandler
184 | .word TIM3_IRQHandler
185 | .word TIM4_IRQHandler
186 | .word I2C1_EV_IRQHandler
187 | .word I2C1_ER_IRQHandler
188 | .word I2C2_EV_IRQHandler
189 | .word I2C2_ER_IRQHandler
190 | .word SPI1_IRQHandler
191 | .word SPI2_IRQHandler
192 | .word USART1_IRQHandler
193 | .word USART2_IRQHandler
194 | .word USART3_IRQHandler
195 | .word EXTI15_10_IRQHandler
196 | .word RTCAlarm_IRQHandler
197 | .word USBWakeUp_IRQHandler
198 | .word 0
199 | .word 0
200 | .word 0
201 | .word 0
202 | .word 0
203 | .word 0
204 | .word 0
205 | .word BootRAM /* @0x108. This is for boot in RAM mode for
206 | STM32F10x Medium Density devices. */
207 |
208 | /*******************************************************************************
209 | *
210 | * Provide weak aliases for each Exception handler to the Default_Handler.
211 | * As they are weak aliases, any function with the same name will override
212 | * this definition.
213 | *
214 | *******************************************************************************/
215 |
216 | .weak NMI_Handler
217 | .thumb_set NMI_Handler,Default_Handler
218 |
219 | .weak HardFault_Handler
220 | .thumb_set HardFault_Handler,Default_Handler
221 |
222 | .weak MemManage_Handler
223 | .thumb_set MemManage_Handler,Default_Handler
224 |
225 | .weak BusFault_Handler
226 | .thumb_set BusFault_Handler,Default_Handler
227 |
228 | .weak UsageFault_Handler
229 | .thumb_set UsageFault_Handler,Default_Handler
230 |
231 | .weak SVC_Handler
232 | .thumb_set SVC_Handler,Default_Handler
233 |
234 | .weak DebugMon_Handler
235 | .thumb_set DebugMon_Handler,Default_Handler
236 |
237 | .weak PendSV_Handler
238 | .thumb_set PendSV_Handler,Default_Handler
239 |
240 | .weak SysTick_Handler
241 | .thumb_set SysTick_Handler,Default_Handler
242 |
243 | .weak WWDG_IRQHandler
244 | .thumb_set WWDG_IRQHandler,Default_Handler
245 |
246 | .weak PVD_IRQHandler
247 | .thumb_set PVD_IRQHandler,Default_Handler
248 |
249 | .weak TAMPER_IRQHandler
250 | .thumb_set TAMPER_IRQHandler,Default_Handler
251 |
252 | .weak RTC_IRQHandler
253 | .thumb_set RTC_IRQHandler,Default_Handler
254 |
255 | .weak FLASH_IRQHandler
256 | .thumb_set FLASH_IRQHandler,Default_Handler
257 |
258 | .weak RCC_IRQHandler
259 | .thumb_set RCC_IRQHandler,Default_Handler
260 |
261 | .weak EXTI0_IRQHandler
262 | .thumb_set EXTI0_IRQHandler,Default_Handler
263 |
264 | .weak EXTI1_IRQHandler
265 | .thumb_set EXTI1_IRQHandler,Default_Handler
266 |
267 | .weak EXTI2_IRQHandler
268 | .thumb_set EXTI2_IRQHandler,Default_Handler
269 |
270 | .weak EXTI3_IRQHandler
271 | .thumb_set EXTI3_IRQHandler,Default_Handler
272 |
273 | .weak EXTI4_IRQHandler
274 | .thumb_set EXTI4_IRQHandler,Default_Handler
275 |
276 | .weak DMA1_Channel1_IRQHandler
277 | .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
278 |
279 | .weak DMA1_Channel2_IRQHandler
280 | .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
281 |
282 | .weak DMA1_Channel3_IRQHandler
283 | .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
284 |
285 | .weak DMA1_Channel4_IRQHandler
286 | .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
287 |
288 | .weak DMA1_Channel5_IRQHandler
289 | .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
290 |
291 | .weak DMA1_Channel6_IRQHandler
292 | .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
293 |
294 | .weak DMA1_Channel7_IRQHandler
295 | .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
296 |
297 | .weak ADC1_2_IRQHandler
298 | .thumb_set ADC1_2_IRQHandler,Default_Handler
299 |
300 | .weak USB_HP_CAN1_TX_IRQHandler
301 | .thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler
302 |
303 | .weak USB_LP_CAN1_RX0_IRQHandler
304 | .thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler
305 |
306 | .weak CAN1_RX1_IRQHandler
307 | .thumb_set CAN1_RX1_IRQHandler,Default_Handler
308 |
309 | .weak CAN1_SCE_IRQHandler
310 | .thumb_set CAN1_SCE_IRQHandler,Default_Handler
311 |
312 | .weak EXTI9_5_IRQHandler
313 | .thumb_set EXTI9_5_IRQHandler,Default_Handler
314 |
315 | .weak TIM1_BRK_IRQHandler
316 | .thumb_set TIM1_BRK_IRQHandler,Default_Handler
317 |
318 | .weak TIM1_UP_IRQHandler
319 | .thumb_set TIM1_UP_IRQHandler,Default_Handler
320 |
321 | .weak TIM1_TRG_COM_IRQHandler
322 | .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
323 |
324 | .weak TIM1_CC_IRQHandler
325 | .thumb_set TIM1_CC_IRQHandler,Default_Handler
326 |
327 | .weak TIM2_IRQHandler
328 | .thumb_set TIM2_IRQHandler,Default_Handler
329 |
330 | .weak TIM3_IRQHandler
331 | .thumb_set TIM3_IRQHandler,Default_Handler
332 |
333 | .weak TIM4_IRQHandler
334 | .thumb_set TIM4_IRQHandler,Default_Handler
335 |
336 | .weak I2C1_EV_IRQHandler
337 | .thumb_set I2C1_EV_IRQHandler,Default_Handler
338 |
339 | .weak I2C1_ER_IRQHandler
340 | .thumb_set I2C1_ER_IRQHandler,Default_Handler
341 |
342 | .weak I2C2_EV_IRQHandler
343 | .thumb_set I2C2_EV_IRQHandler,Default_Handler
344 |
345 | .weak I2C2_ER_IRQHandler
346 | .thumb_set I2C2_ER_IRQHandler,Default_Handler
347 |
348 | .weak SPI1_IRQHandler
349 | .thumb_set SPI1_IRQHandler,Default_Handler
350 |
351 | .weak SPI2_IRQHandler
352 | .thumb_set SPI2_IRQHandler,Default_Handler
353 |
354 | .weak USART1_IRQHandler
355 | .thumb_set USART1_IRQHandler,Default_Handler
356 |
357 | .weak USART2_IRQHandler
358 | .thumb_set USART2_IRQHandler,Default_Handler
359 |
360 | .weak USART3_IRQHandler
361 | .thumb_set USART3_IRQHandler,Default_Handler
362 |
363 | .weak EXTI15_10_IRQHandler
364 | .thumb_set EXTI15_10_IRQHandler,Default_Handler
365 |
366 | .weak RTCAlarm_IRQHandler
367 | .thumb_set RTCAlarm_IRQHandler,Default_Handler
368 |
369 | .weak USBWakeUp_IRQHandler
370 | .thumb_set USBWakeUp_IRQHandler,Default_Handler
371 |
372 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
373 |
374 |
--------------------------------------------------------------------------------
/Libraries/System_stm32f10x/src/stm32f1xx_it.c:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32f1xx_it.c
4 | * @author MCD Application Team
5 | * @version V1.0.0
6 | * @date 11-February-2014
7 | * @brief Main Interrupt Service Routines.
8 | * This file provides template for all exceptions handler and
9 | * peripherals interrupt service routine.
10 | ******************************************************************************
11 | * @attention
12 | *
13 | * © COPYRIGHT 2014 STMicroelectronics
14 | *
15 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
16 | * You may not use this file except in compliance with the License.
17 | * You may obtain a copy of the License at:
18 | *
19 | * http://www.st.com/software_license_agreement_liberty_v2
20 | *
21 | * Unless required by applicable law or agreed to in writing, software
22 | * distributed under the License is distributed on an "AS IS" BASIS,
23 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
24 | * See the License for the specific language governing permissions and
25 | * limitations under the License.
26 | *
27 | ******************************************************************************
28 | */
29 |
30 | /* Includes ------------------------------------------------------------------*/
31 | #include "gpio.h"
32 | #include "stm32f1xx_it.h"
33 | #include "SysTick.h"
34 | #include "usart.h"
35 | #include "dma.h"
36 | #include "DS18B20.h"
37 | #include "LIN_Slave.h"
38 |
39 | /* Private typedef -----------------------------------------------------------*/
40 | /* Private define ------------------------------------------------------------*/
41 | /* Private macro -------------------------------------------------------------*/
42 | /* Private variables ---------------------------------------------------------*/
43 | /* Private function prototypes -----------------------------------------------*/
44 | /* Private functions ---------------------------------------------------------*/
45 |
46 | /******************************************************************************/
47 | /* Cortex-M Processor Exceptions Handlers */
48 | /******************************************************************************/
49 |
50 | /**
51 | * @brief This function handles NMI exception.
52 | * @param None
53 | * @retval None
54 | */
55 | void NMI_Handler(void)
56 | {
57 | }
58 |
59 | /**
60 | * @brief This function handles Hard Fault exception.
61 | * @param None
62 | * @retval None
63 | */
64 | void HardFault_Handler(void)
65 | {
66 | /* Go to infinite loop when Hard Fault exception occurs */
67 | while (1)
68 | {
69 | }
70 | }
71 |
72 | /**
73 | * @brief This function handles Memory Manage exception.
74 | * @param None
75 | * @retval None
76 | */
77 | void MemManage_Handler(void)
78 | {
79 | /* Go to infinite loop when Memory Manage exception occurs */
80 | while (1)
81 | {
82 | }
83 | }
84 |
85 | /**
86 | * @brief This function handles Bus Fault exception.
87 | * @param None
88 | * @retval None
89 | */
90 | void BusFault_Handler(void)
91 | {
92 | /* Go to infinite loop when Bus Fault exception occurs */
93 | while (1)
94 | {
95 | }
96 | }
97 |
98 | /**
99 | * @brief This function handles Usage Fault exception.
100 | * @param None
101 | * @retval None
102 | */
103 | void UsageFault_Handler(void)
104 | {
105 | /* Go to infinite loop when Usage Fault exception occurs */
106 | while (1)
107 | {
108 | }
109 | }
110 |
111 | /**
112 | * @brief This function handles SVCall exception.
113 | * @param None
114 | * @retval None
115 | */
116 | void SVC_Handler(void)
117 | {
118 | }
119 |
120 | /**
121 | * @brief This function handles Debug Monitor exception.
122 | * @param None
123 | * @retval None
124 | */
125 | void DebugMon_Handler(void)
126 | {
127 | }
128 |
129 | /**
130 | * @brief This function handles PendSVC exception.
131 | * @param None
132 | * @retval None
133 | */
134 | void PendSV_Handler(void)
135 | {
136 | }
137 |
138 | /**
139 | * @brief This function handles SysTick Handler.
140 | * @param None
141 | * @retval None
142 | */
143 | void SysTick_Handler(void)
144 | {
145 | ++SysTickCounter;
146 | }
147 |
148 | /******************************************************************************/
149 | /* STM32F1xx Peripherals Interrupt Handlers */
150 | /* Add here the Interrupt Handler for the used peripheral(s) (PPP), for the */
151 | /* available peripheral interrupt handler's name please refer to the startup */
152 | /* file (startup_stm32f10x_md.s). */
153 | /******************************************************************************/
154 |
155 | /**
156 | * @brief This function handles PPP interrupt request.
157 | * @param None
158 | * @retval None
159 | */
160 | /*void PPP_IRQHandler(void)
161 | {
162 | }*/
163 |
164 | /**
165 | * @brief This function handles EXTI0 interrupt request.
166 | * @note None
167 | * @param None
168 | * @retval None
169 | */
170 | void EXTI0_IRQHandler(void)
171 | {
172 |
173 | /* Turn on Yellow LED */
174 | Yellow_LED_BITBAND = 0;
175 |
176 | /* Wait one second */
177 | SysTick_Delay(1000);
178 |
179 | /* Turn OFF Yellow LED */
180 | Yellow_LED_BITBAND = 1;
181 |
182 | /* Wait one second */
183 | SysTick_Delay(1000);
184 |
185 | /* Clear pending bit */
186 | EXTI->PR |= EXTI_PR_PR0;
187 | }
188 |
189 | /**
190 | * @brief This function handles EXTI1 interrupt request.
191 | * @note None
192 | * @param None
193 | * @retval None
194 | */
195 | void EXTI1_IRQHandler(void)
196 | {
197 |
198 | }
199 |
200 | /**
201 | * @brief This function handles EXTI2 interrupt request.
202 | * @note None
203 | * @param None
204 | * @retval None
205 | */
206 | void EXTI2_IRQHandler(void)
207 | {
208 |
209 | }
210 |
211 | /**
212 | * @brief This function handles EXTI3 interrupt request.
213 | * @note None
214 | * @param None
215 | * @retval None
216 | */
217 | void EXTI3_IRQHandler(void)
218 | {
219 |
220 | }
221 |
222 |
223 |
224 | /**
225 | * @brief This function handles DMA1 Channel4 interrupt request.
226 | * @param None
227 | * @retval None
228 | */
229 | void DMA1_Channel4_IRQHandler(void)
230 | {
231 | USART1_TX_DMA_IRQ_Callback();
232 | }
233 |
234 | /**
235 | * @brief This function handles DMA1 Channel5 interrupt request.
236 | * @param None
237 | * @retval None
238 | */
239 | void DMA1_Channel5_IRQHandler(void)
240 | {
241 | USART1_RX_DMA_IRQ_Callback();
242 | }
243 | /**
244 | * @brief This function handles DMA1 Channel2 interrupt request.
245 | * @param None
246 | * @retval None
247 | */
248 | void DMA1_Channel2_IRQHandler(void)
249 | {
250 | LIN_Slave_TX_DMA_IRQ_Callback();
251 | }
252 |
253 | /**
254 | * @brief This function handles DMA1 Channel3 interrupt request.
255 | * @param None
256 | * @retval None
257 | */
258 | void DMA1_Channel3_IRQHandler(void)
259 | {
260 | LIN_Slave_RX_DMA_IRQ_Callback();
261 | }
262 |
263 | /**
264 | * @brief This function handles USART1 interrupt request.
265 | * @param None
266 | * @retval None
267 | */
268 | void USART1_IRQHandler(void)
269 | {
270 | USART1_IRQ_Callback();
271 | }
272 | /**
273 | * @brief This function handles USART3 interrupt request.
274 | * @param None
275 | * @retval None
276 | */
277 | void USART3_IRQHandler(void)
278 | {
279 | LIN_Slave_USART3_IRQ_Callback();
280 | }
281 | /**
282 | * @}
283 | */
284 |
285 |
286 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
287 |
--------------------------------------------------------------------------------
/Transceiver Design/Transceiver.jpeg:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/RashadShubita/STM32F103_LIN-bus_Example/c06eefd8dc90c1cb3b3d2a4b2243d6b06053f46a/Transceiver Design/Transceiver.jpeg
--------------------------------------------------------------------------------
/ff.txt:
--------------------------------------------------------------------------------
1 | /*
2 | * dma.c
3 | *
4 | * Created on: Dec 11, 2018
5 | * Author: shubi
6 | */
7 |
8 | #include "dma.h"
9 |
10 | /**
11 | * @brief DMA initialization function
12 | * @note Basic initialization
13 | *
14 | * @param DMA_Num: 1 or 2
15 | * DMA_Channel: DMAx_Channely where: x= 1 or 2 , y= 1 ..7 for DMA1 and 1 ..5 for DMA2
16 | * Peripheral_Adr: peripheral address
17 | * Memory_Adr: memory address
18 | * Size: Buffer size(no. of data to transfer)
19 | * Psize: DMA_PERIPHERAL_DATA_8BIT
20 | * DMA_PERIPHERAL_DATA_16BIT
21 | * DMA_PERIPHERAL_DATA_32BIT
22 | * Msize: DMA_MEMORY_DATA_8BIT
23 | * DMA_MEMORY_DATA_16BIT
24 | * DMA_MEMORY_DATA_32BIT
25 | * Prio: DMA_PRIORITY_LOW
26 | * DMA_PRIORITY_MEDIUM
27 | * DMA_PRIORITY_HIGH
28 | * DMA_PRIORITY_VERY_HIGH
29 | * P_inc: DMA_PERIPHERAL_INCREMENT_E
30 | * DMA_PERIPHERAL_INCREMENT_D
31 | * M_inc: DMA_MEMORY_INCREMENT_E
32 | * DMA_MEMORY_INCREMENT_D
33 | * Circular_M: DMA_CIRCULAR_MODE_E
34 | * DMA_CIRCULAR_MODE_D
35 | * M2M: DMA_M2M_E
36 | * DMA_M2M_D
37 | *
38 | * @retval None
39 | */
40 | void DMA_Init(uint8_t DMA_Num, DMA_Channel_TypeDef * DMA_Channel, const uint32_t * Peripheral_Adr, const uint32_t * Memory_Adr,const uint32_t Size,
41 | const uint8_t Psize,const uint8_t Msize,const uint8_t Prio,const uint8_t P_inc,const uint8_t M_inc,const uint8_t Circular_M,const uint8_t M2M)
42 | {
43 | /* Enable clock for DMA1 or DM2 */
44 | if(DMA_Num == 1)
45 | RCC ->AHBENR |= RCC_AHBENR_DMA1EN;
46 | else if(DMA_Num == 2)
47 | RCC ->AHBENR |= RCC_AHBENR_DMA1EN;
48 | /* disable channel, since this registers must not be written when the channel is enabled */
49 | DMA_ChannelDisable(DMA_Channel);
50 |
51 | /* Set address for peripheral */
52 | DMA_Channel ->CPAR = (uint32_t)Peripheral_Adr;
53 |
54 | /* Set address for memory */
55 | DMA_Channel ->CMAR = (uint32_t)Memory_Adr;
56 |
57 | /* Set no. of data to transfer */
58 | DMA_Channel ->CNDTR = Size;
59 |
60 | /* Set Peripheral size, 00: 8-bits & 01: 16-bits & 10: 32-bits & 11: Reserved */
61 | DMA_Channel ->CCR &= ~DMA_CCR1_PSIZE;
62 | if(Psize != 0)DMA_Channel ->CCR |= Psize;
63 |
64 | /* Set Memory size, 00: 8-bits & 01: 16-bits & 10: 32-bits & 11: Reserved*/
65 | DMA_Channel ->CCR &= ~DMA_CCR1_MSIZE;
66 | if(Msize != 0)DMA_Channel ->CCR |= Msize;
67 |
68 | /* Set Channel priority, 00: Low & 01: Medium & 10: High & 11: Very high */
69 | DMA_Channel ->CCR &= ~DMA_CCR1_PL;
70 | if(Prio != 0)DMA_Channel ->CCR |= Prio;
71 |
72 | /* 1:Enable/0:Disable Peripheral increment mode */
73 | if(P_inc == 0)DMA_Channel ->CCR &= ~DMA_CCR1_PINC;
74 | else DMA_Channel ->CCR |= DMA_CCR1_PINC;
75 |
76 | /* 1:Enable/0:Disable memory increment mode */
77 | if(M_inc == 0)DMA_Channel ->CCR &= ~DMA_CCR1_MINC;
78 | else DMA_Channel ->CCR |= DMA_CCR1_MINC;
79 |
80 | if(M2M == 0)
81 | {
82 | /* Disable M2M Mode */
83 | DMA_Channel ->CCR &= ~DMA_CCR1_MEM2MEM;
84 | /* 1:Enable/0:Disable Circular mode*/
85 | if(Circular_M == 0)DMA_Channel ->CCR &= ~DMA_CCR1_CIRC;
86 | else DMA_Channel ->CCR |= DMA_CCR1_CIRC;
87 | }
88 | else
89 | {
90 | /* Enable M2M Mode */
91 | DMA_Channel ->CCR |= DMA_CCR1_MEM2MEM;
92 | }
93 | /* Data transfer direction, 0: Read from peripheral , 1: Read from memory*/
94 | if(Circular_M == 0)DMA_Channel ->CCR &= ~DMA_CCR1_DIR;
95 | else DMA_Channel ->CCR |= DMA_CCR1_DIR;
96 |
97 | DMA_ChannelEnable(DMA_Channel);
98 |
99 | __ASM("NOP");
100 | __ASM("NOP");
101 | __ASM("NOP");
102 | __ASM("NOP");
103 | __ASM("NOP");
104 | __ASM("NOP");
105 | __ASM("NOP");
106 | __ASM("NOP");
107 | }
108 |
109 | /**
110 | * @brief Enable DMA
111 | * @note
112 | * @param DMAx_Channely where: x= 1 or 2 , y= 1 ..7 for DMA1 and 1 ..5 for DMA2
113 | * @retval None
114 | */
115 | void DMA_ChannelEnable(DMA_Channel_TypeDef *DMA_Channel){
116 | DMA_Channel->CCR |= DMA_CCR1_EN;
117 | }
118 |
119 | /**
120 | * @brief Disable DMA
121 | * @note
122 | * @param DMAx_Channely where: x= 1 or 2 , y= 1 ..7 for DMA1 and 1 ..5 for DMA2
123 | * @retval None
124 | */
125 | void DMA_ChannelDisable(DMA_Channel_TypeDef *DMA_Channel){
126 | DMA_Channel->CCR &= ~DMA_CCR1_EN;
127 | }
128 |
129 |
130 |
131 |
132 |
133 |
134 |
135 |
136 |
137 |
138 |
139 |
140 |
141 |
142 |
143 |
144 | /*
145 | * dma.h
146 | *
147 | * Created on: Dec 11, 2018
148 | * Author: shubi
149 | */
150 |
151 | /* Define to prevent recursive inclusion */
152 | #ifndef INC_DMA_H_
153 | #define INC_DMA_H_
154 |
155 | #include "stm32f10x.h"
156 |
157 | #define DMA_PERIPHERAL_DATA_8BIT 0
158 | #define DMA_PERIPHERAL_DATA_16BIT (0x0100)
159 | #define DMA_PERIPHERAL_DATA_32BIT (0x0200)
160 | #define DMA_MEMORY_DATA_8BIT 0
161 | #define DMA_MEMORY_DATA_16BIT DMA_CCR1_MSIZE_0
162 | #define DMA_MEMORY_DATA_32BIT ((uint16_t)0x0800)
163 | #define DMA_PRIORITY_LOW 0
164 | #define DMA_PRIORITY_MEDIUM DMA_CCR1_PL_0
165 | #define DMA_PRIORITY_HIGH DMA_CCR1_PL_1
166 | #define DMA_PRIORITY_VERY_HIGH DMA_CCR1_PL
167 | #define DMA_PERIPHERAL_INCREMENT_E 1
168 | #define DMA_PERIPHERAL_INCREMENT_D 0
169 | #define DMA_MEMORY_INCREMENT_E 1
170 | #define DMA_MEMORY_INCREMENT_D 0
171 | #define DMA_CIRCULAR_MODE_E 1
172 | #define DMA_CIRCULAR_MODE_D 0
173 | #define DMA_READ_FROM_PERIPHERAL 0
174 | #define DMA_READ_FROM_MEMORY 1
175 | #define DMA_M2M_D 0
176 | #define DMA_M2M_E 1
177 |
178 |
179 | /**
180 | * @brief DMA initialization function
181 | * @note Basic initialization
182 | *
183 | * @param DMA_Num: 1 or 2
184 | * DMA_Channel: DMAx_Channely where: x= 1 or 2 , y= 1 ..7 for DMA1 and 1 ..5 for DMA2
185 | * Peripheral_Adr: peripheral address
186 | * Memory_Adr: memory address
187 | * Size: Buffer size(no. of data to transfer)
188 | * Psize: DMA_PERIPHERAL_DATA_8BIT
189 | * DMA_PERIPHERAL_DATA_16BIT
190 | * DMA_PERIPHERAL_DATA_32BIT
191 | * Msize: DMA_MEMORY_DATA_8BIT
192 | * DMA_MEMORY_DATA_16BIT
193 | * DMA_MEMORY_DATA_32BIT
194 | * Prio: DMA_PRIORITY_LOW
195 | * DMA_PRIORITY_MEDIUM
196 | * DMA_PRIORITY_HIGH
197 | * DMA_PRIORITY_VERY_HIGH
198 | * P_inc: DMA_PERIPHERAL_INCREMENT_E
199 | * DMA_PERIPHERAL_INCREMENT_D
200 | * M_inc: DMA_MEMORY_INCREMENT_E
201 | * DMA_MEMORY_INCREMENT_D
202 | * Circular_M: DMA_CIRCULAR_MODE_E
203 | * DMA_CIRCULAR_MODE_D
204 | * M2M: DMA_M2M_E
205 | * DMA_M2M_D
206 | * @retval None
207 | */
208 | void DMA_Init(uint8_t DMA_Num, DMA_Channel_TypeDef * DMA_Channel, const uint32_t * Peripheral_Adr, const uint32_t * Memory_Adr,const uint32_t Size,
209 | const uint8_t Psize, const uint8_t Msize,const uint8_t Prio,const uint8_t P_inc,const uint8_t M_inc,const uint8_t Circular_M,const uint8_t M2M);
210 |
211 | /**
212 | * @brief Enable DMA
213 | * @note
214 | * @param DMAx_Channely where: x= 1 or 2 , y= 1 ..7 for DMA1 and 1 ..5 for DMA2
215 | * @retval None
216 | */
217 | void DMA_ChannelEnable(DMA_Channel_TypeDef *DMA_Channel);
218 |
219 | /**
220 | * @brief Disable DMA
221 | * @note
222 | * @param DMAx_Channely where: x= 1 or 2 , y= 1 ..7 for DMA1 and 1 ..5 for DMA2
223 | * @retval None
224 | */
225 | void DMA_ChannelDisable(DMA_Channel_TypeDef *DMA_Channel);
226 |
227 |
228 | #endif /* INC_DMA_H_ */
229 |
230 |
231 |
232 |
233 |
234 |
235 |
236 |
237 |
238 |
239 |
240 |
241 |
242 |
243 |
244 |
245 |
246 |
247 |
248 |
249 | /*
250 | ******************************************************************************
251 | File: main.c
252 | Info: Generated by Atollic TrueSTUDIO(R) 9.0.0 2018-06-29
253 |
254 | The MIT License (MIT)
255 | Copyright (c) 2018 STMicroelectronics
256 |
257 | Permission is hereby granted, free of charge, to any person obtaining a copy
258 | of this software and associated documentation files (the "Software"), to deal
259 | in the Software without restriction, including without limitation the rights
260 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
261 | copies of the Software, and to permit persons to whom the Software is
262 | furnished to do so, subject to the following conditions:
263 |
264 | The above copyright notice and this permission notice shall be included in all
265 | copies or substantial portions of the Software.
266 |
267 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
268 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
269 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
270 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
271 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
272 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
273 | SOFTWARE.
274 |
275 | ******************************************************************************
276 | */
277 |
278 | /* Includes ------------------------------------------------------------------*/
279 | #include "nvic.h"
280 | #include "SysTick.h"
281 | #include "exti.h"
282 | #include "gpio.h"
283 | #include "dma.h"
284 | #include "memcpy.h"
285 |
286 | /* Private typedef */
287 | /* Private define ------------------------------------------------------------*/
288 | /**
289 | * @brief Buffer array size
290 | */
291 | #define BUFFER_SIZE ((uint32_t) 500)
292 |
293 | /**
294 | * @brief use #define USE_MEMCPY or USE_DMA
295 | */
296 | #define USE_MEMCPY
297 |
298 | /* Private macro */
299 |
300 | /* Private variables ---------------------------------------------------------*/
301 | /**
302 | * @brief Source and destination buffers
303 | */
304 | static uint32_t srcBuffer[BUFFER_SIZE];
305 | static uint32_t dstBuffer[BUFFER_SIZE];
306 |
307 | /* Private function prototypes */
308 | /* Private functions */
309 |
310 | /**
311 | **===========================================================================
312 | **
313 | ** Abstract: main program
314 | **
315 | **===========================================================================
316 | */
317 | int main(void)
318 | {
319 | SysTick_Init();
320 | GPIO_OnBoard_Init_LED();
321 |
322 | GPIO_Init_PB();
323 | EXTI_Init_PB();
324 | NVIC_Init();
325 |
326 | DMA_Init(1, DMA1_Channel3, dstBuffer, srcBuffer, BUFFER_SIZE, DMA_PERIPHERAL_DATA_32BIT, DMA_MEMORY_DATA_32BIT,
327 | DMA_PRIORITY_VERY_HIGH, DMA_PERIPHERAL_INCREMENT_E, DMA_MEMORY_INCREMENT_E,DMA_CIRCULAR_MODE_D,DMA_M2M_E);
328 |
329 | /* Clear PRIMASK, enable IRQs */
330 | __enable_irq();
331 |
332 | /* Infinite loop */
333 | while (1)
334 | {
335 |
336 | }
337 | }
338 |
339 |
340 |
--------------------------------------------------------------------------------
/src/inc/DS18B20.h:
--------------------------------------------------------------------------------
1 | /*******************************************************************************
2 | * @file DS18B20.h
3 | * @author Rashad Shubita
4 | * @email shubitarashad@gmail.com
5 | * @date 20.01.2019
6 | *
7 | * @brief Interfacing temperature sensor DS18B20 using UART over one-wire
8 | * @note
9 | *
10 | @verbatim
11 | Copyright (C) 2019, Rashad Shubita
12 |
13 | This program is free software: you can redistribute it and/or modify it under
14 | the terms of the GNU General Public License as published by the Free Software
15 | Foundation, either version 3 of the License, or any later version.
16 |
17 | This program is distributed in the hope that it will be useful, but WITHOUT
18 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
19 | FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
20 |
21 | You should have received a copy of the GNU General Public License along with
22 | this program. If not, see .
23 | @endverbatim
24 | *******************************************************************************/
25 |
26 | #ifndef INC_DS18B20_H_
27 | #define INC_DS18B20_H_
28 |
29 | /* Includes */
30 | #include "stm32f10x.h"
31 |
32 | /**
33 | * @brief Configure GPIO
34 | * @note UART3_TX -> PB10, UART3_RX -> PB11 (Not Used) from "Datasheet rev17 page:30"
35 | * GPIO configuration from "Reference manual [Table 24. USARTs]
36 | * UART3 connected to APB1 with 36MHz max clock
37 | * @param None
38 | * @retval None
39 | */
40 | void DS18B20_GPIO_Init(void);
41 |
42 | /**
43 | * @brief Configure DMA for USART TX
44 | * @note USART3_TX -> DMA1_Channel2
45 | * @param None
46 | * @retval None
47 | */
48 | void DS18B20_TX_DMA_Init(void);
49 |
50 | /**
51 | * @brief Configure DMA for UART RX
52 | * @note USART3_RX -> DMA1_Channel3
53 | * @param None
54 | * @retval None
55 | */
56 | void DS18B20_RX_DMA_Init(void);
57 |
58 | /**
59 | * @brief Configure USART3 for DS18B20
60 | * @note
61 | * @param None
62 | * @retval None
63 | */
64 | void DS18B20_USART3_Init(void);
65 |
66 | /**
67 | * @brief Enable communications with DS18B20
68 | * @note
69 | * @param None
70 | * @retval None
71 | */
72 | void DS18B20_USART3_Enable(void);
73 |
74 | /**
75 | * @brief DS18B20 process function
76 | * @note
77 | * @param None
78 | * @retval None
79 | */
80 | void DS18B20_Process(void);
81 |
82 | /**
83 | * @brief IRQ callback function
84 | * @note
85 | * @param None
86 | * @retval None
87 | */
88 | void USART3_TX_DMA_IRQ_Callback(void);
89 |
90 | /**
91 | * @brief IRQ callback function
92 | * @note
93 | * @param None
94 | * @retval None
95 | */
96 | void USART3_RX_DMA_IRQ_Callback(void);
97 |
98 |
99 | #endif /* INC_DS18B20_H_ */
100 |
--------------------------------------------------------------------------------
/src/inc/LIN_Slave.h:
--------------------------------------------------------------------------------
1 | /*******************************************************************************
2 | * @file LIN_Slave.h
3 | * @author Rashad Shubita
4 | * @email shubitarashad@gmail.com
5 | * @date 23.01.2019
6 | *
7 | * @brief LIN slave node driver
8 | * @note
9 | *
10 | @verbatim
11 | Copyright (C) 2019, Rashad Shubita
12 |
13 | This program is free software: you can redistribute it and/or modify it under
14 | the terms of the GNU General Public License as published by the Free Software
15 | Foundation, either version 3 of the License, or any later version.
16 |
17 | This program is distributed in the hope that it will be useful, but WITHOUT
18 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
19 | FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
20 |
21 | You should have received a copy of the GNU General Public License along with
22 | this program. If not, see .
23 | @endverbatim
24 | *******************************************************************************/
25 |
26 | /* Define to prevent recursive inclusion */
27 | #ifndef __INC_LIN_SLAVE_H_
28 | #define __INC_LIN_SLAVE_H_
29 |
30 | /* C++ detection */
31 | #ifdef __cplusplus
32 | extern "C" {
33 | #endif
34 |
35 | /* Includes */
36 | #include "stm32f10x.h"
37 |
38 | /**
39 | * @addtogroup stm32_examples
40 | * @{
41 | */
42 |
43 | /**
44 | * @addtogroup LIN_Slave
45 | * @{
46 | */
47 |
48 | /**
49 | * @defgroup LIN_Slave_exported_typedefs
50 | * @{
51 | */
52 |
53 | /**
54 | * @}
55 | */
56 |
57 | /**
58 | * @defgroup LIN_Slave_exported_defines
59 | * @{
60 | */
61 |
62 | /**
63 | * @}
64 | */
65 |
66 | /**
67 | * @defgroup LIN_Slave_exported_macros
68 | * @{
69 | */
70 |
71 | /**
72 | * @}
73 | */
74 |
75 | /**
76 | * @defgroup LIN_Slave_exported_constants
77 | * @{
78 | */
79 |
80 | /**
81 | * @}
82 | */
83 |
84 | /**
85 | * @defgroup LIN_Slave_exported_functions
86 | * @{
87 | */
88 |
89 | void LIN_Slave_GPIO_Init(void);
90 | void LIN_Slave_USART3_Init(void);
91 | void LIN_Slave_TX_DMA_Init(void);
92 | void LIN_Slave_RX_DMA_Init(void);
93 | void LIN_Slave_Enable(void);
94 | void LIN_Slave_RX_DMA_IRQ_Callback(void);
95 | void LIN_Slave_TX_DMA_IRQ_Callback(void);
96 | void LIN_Slave_USART3_IRQ_Callback(void);
97 | void LIN_Slave_Process(void);
98 | void LIN_Send_Break_Field(void);
99 | void LIN_Master_Process(uint8_t data0, uint8_t data1, uint8_t CheckSum);
100 |
101 | /**
102 | * @}
103 | */
104 | /**
105 | * @}
106 | */
107 | /**
108 | * @}
109 | */
110 |
111 | /* C++ detection */
112 | #ifdef __cplusplus
113 | }
114 | #endif
115 |
116 | #endif /*__INC_LIN_SLAVE_H_ */
117 |
--------------------------------------------------------------------------------
/src/inc/SysTick.h:
--------------------------------------------------------------------------------
1 | /*******************************************************************************
2 | * @file SysTick.h
3 | * @author Rashad Shubita
4 | * @email shubitarashad@gmail.com
5 | * @date 15.01.2019
6 | *
7 | * @brief SysTick configuration header file
8 | * @note
9 | *
10 | @verbatim
11 | Copyright (C) 2019, Rashad Shubita
12 |
13 | This program is free software: you can redistribute it and/or modify it under
14 | the terms of the GNU General Public License as published by the Free Software
15 | Foundation, either version 3 of the License, or any later version.
16 |
17 | This program is distributed in the hope that it will be useful, but WITHOUT
18 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
19 | FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
20 |
21 | You should have received a copy of the GNU General Public License along with
22 | this program. If not, see .
23 | @endverbatim
24 | *******************************************************************************/
25 |
26 |
27 | #ifndef INC_SYSTICK_H_
28 | #define INC_SYSTICK_H_
29 |
30 | /* Includes */
31 | #include "stm32f10x.h"
32 |
33 |
34 | extern volatile uint32_t SysTickCounter;
35 |
36 | /**
37 | * @brief Return current SysTick counter
38 | * @note
39 | * @param None
40 | * @retval SysTickCounter
41 | */
42 | uint32_t SysTick_GetCurrentTick(void);
43 |
44 | /**
45 | * @brief Delay function based on SysTick
46 | * @note SysTick will be update with IRQ callback
47 | * @param Waiting time in milliseconds
48 | * @retval None
49 | */
50 | void SysTick_Delay(uint32_t wait_time_ms);
51 |
52 | /**
53 | * @brief SysTick initial configuration
54 | * @note
55 | * @param None
56 | * @retval None
57 | */
58 | void SysTick_Init(void);
59 |
60 | #endif /* INC_SYSTICK_H_ */
61 |
--------------------------------------------------------------------------------
/src/inc/dma.h:
--------------------------------------------------------------------------------
1 | /*******************************************************************************
2 | * @file dma.h
3 | * @author Rashad Shubita
4 | * @email shubitarashad@gmail.com
5 | * @date 15.02.2019
6 | *
7 | * @brief DMA configuration header file
8 | * @note
9 | *
10 | @verbatim
11 | Copyright (C) 2019, Rashad Shubita
12 |
13 | This program is free software: you can redistribute it and/or modify it under
14 | the terms of the GNU General Public License as published by the Free Software
15 | Foundation, either version 3 of the License, or any later version.
16 |
17 | This program is distributed in the hope that it will be useful, but WITHOUT
18 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
19 | FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
20 |
21 | You should have received a copy of the GNU General Public License along with
22 | this program. If not, see .
23 | @endverbatim
24 | *******************************************************************************/
25 |
26 | /* Define to prevent recursive inclusion */
27 | #ifndef INC_DMA_H_
28 | #define INC_DMA_H_
29 |
30 | #include "stm32f10x.h"
31 |
32 | /**
33 | * @brief DMA1 Channel3 initialization function
34 | * @note Used for data transfer between two memory buffers
35 | * @param None
36 | * @retval None
37 | */
38 | void DMA1_Channel3_Init(void);
39 |
40 | /**
41 | * @brief Enable DMA
42 | * @note
43 | * @param DMAx_Channely where: x= 1 or 2 , y= 1 ..7 for DMA1 and 1 ..5 for DMA2
44 | * @retval None
45 | */
46 | void DMA_ChannelEnable(DMA_Channel_TypeDef *DMA_Channel,uint8_t DMA_Num, uint8_t Ch_Num);
47 |
48 | /**
49 | * @brief Disable DMA
50 | * @note
51 | * @param DMAx_Channely where: x= 1 or 2 , y= 1 ..7 for DMA1 and 1 ..5 for DMA2
52 | * @retval None
53 | */
54 | void DMA_ChannelDisable(DMA_Channel_TypeDef *DMA_Channel);
55 |
56 |
57 | #endif /* INC_DMA_H_ */
58 |
--------------------------------------------------------------------------------
/src/inc/exti.h:
--------------------------------------------------------------------------------
1 | /*******************************************************************************
2 | * @file exti.h
3 | * @author Rashad Shubita
4 | * @email shubitarashad@gmail.com
5 | * @date 08.02.2019
6 | *
7 | * @brief EXTI configuration header file
8 | * @note
9 | *
10 | @verbatim
11 | Copyright (C) 2019, Rashad Shubita
12 |
13 | This program is free software: you can redistribute it and/or modify it under
14 | the terms of the GNU General Public License as published by the Free Software
15 | Foundation, either version 3 of the License, or any later version.
16 |
17 | This program is distributed in the hope that it will be useful, but WITHOUT
18 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
19 | FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
20 |
21 | You should have received a copy of the GNU General Public License along with
22 | this program. If not, see .
23 | @endverbatim
24 | *******************************************************************************/
25 |
26 | /* Define to prevent recursive inclusion */
27 | #ifndef EXTI_H_
28 | #define EXTI_H_
29 |
30 | void EXTI_Init_PB(void);
31 |
32 | #endif /* EXTI_H_ */
33 |
--------------------------------------------------------------------------------
/src/inc/gpio.h:
--------------------------------------------------------------------------------
1 | /*******************************************************************************
2 | * @file gpio.h
3 | * @author Rashad Shubita
4 | * @email shubitarashad@gmail.com
5 | * @date 15.01.2019
6 | *
7 | * @brief Some examples on how to use STM32 GPIOs
8 | *
9 | * @note Example: calculate the bit band address of the Yellow LED
10 | * connected to PC13
11 | *
12 | * General equation:
13 | * bit_word_addr = bit_band_base + (byte_offset * 32) + (bit_number * 4)
14 | * ->bit_word_addr : is the address of the word in the alias memory region that maps to the targeted bit.
15 | * ->bit_band_base : is the starting address of the alias region
16 | * ->byte_offset : is the number of the byte in the bit-band region that contains the targeted bit
17 | * peripheral_base_address = 0x40000000 (Fixed for all ARM Cortex-M3)
18 | * bit_band_base(alias) = 0x42000000 (Fixed for all ARM Cortex-M3)
19 | * port_C_address = 0x40011000 (From STM32F1 datasheet page 34)
20 | * register_ODR_offset = 0x0C (From STM32F1 reference manual page 172)
21 | *
22 | * byte_offset = (port_C_address + register_ODR_offset) - peripheral_base_address
23 | * = (0x40011000 + 0x0C) - 0x40000000
24 | * = 0x0001100C
25 | *
26 | * bit_number = 13 (Yellow LED connected to PC13)
27 | *
28 | * bit_word_addr = 0x42000000 + (0x0001100C * 32) + (13 * 4)
29 | * = 0x42000000 + 0x220180 + 0x34
30 | * = 0x422201B4
31 | @verbatim
32 | Copyright (C) 2019, Rashad Shubita
33 |
34 | This program is free software: you can redistribute it and/or modify it under
35 | the terms of the GNU General Public License as published by the Free Software
36 | Foundation, either version 3 of the License, or any later version.
37 |
38 | This program is distributed in the hope that it will be useful, but WITHOUT
39 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
40 | FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
41 |
42 | You should have received a copy of the GNU General Public License along with
43 | this program. If not, see .
44 | @endverbatim
45 | *******************************************************************************/
46 |
47 |
48 | #ifndef INC_GPIO_H_
49 | #define INC_GPIO_H_
50 |
51 | /* Includes */
52 | #include "stm32f10x.h"
53 | #include
54 |
55 | #define GPIO_Pin_Set(GPIOx, GPIO_PIN) ( GPIOx ->BSRR = (1<BRR = (1<BSRR = (uint32_t)(1<IDR & (1<ODR ^= (1< PC13
89 | * @param None
90 | * @retval None
91 | */
92 | void GPIO_OnBoard_Init_LED();
93 |
94 | /**
95 | * @brief Push button initialization function
96 | * @note Push button connected to PA0
97 | * @param None
98 | * @retval None
99 | */
100 | void GPIO_Init_PB(void);
101 |
102 | /**
103 | * @brief USART2 GPIO initialization function
104 | * @note PB10 -> USART1_TX, PB11 -> USART1_RX
105 | * @param None
106 | * @retval None
107 | */
108 | void GPIO_USART2_Init(void);
109 |
110 | #endif /* INC_GPIO_H_ */
111 |
--------------------------------------------------------------------------------
/src/inc/itm.h:
--------------------------------------------------------------------------------
1 | /*******************************************************************************
2 | * @file itm.h
3 | * @author Rashad Shubita
4 | * @email shubitarashad@gmail.com
5 | * @date 20.01.2019
6 | *
7 | * @brief Basic functionality of ITM
8 | * @note
9 | *
10 | @verbatim
11 | Copyright (C) 2019, Rashad Shubita
12 |
13 | This program is free software: you can redistribute it and/or modify it under
14 | the terms of the GNU General Public License as published by the Free Software
15 | Foundation, either version 3 of the License, or any later version.
16 |
17 | This program is distributed in the hope that it will be useful, but WITHOUT
18 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
19 | FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
20 |
21 | You should have received a copy of the GNU General Public License along with
22 | this program. If not, see .
23 | @endverbatim
24 | *******************************************************************************/
25 |
26 | /* Define to prevent recursive inclusion */
27 | #ifndef __INC_ITM_H_
28 | #define __INC_ITM_H_
29 |
30 | /* C++ detection */
31 | #ifdef __cplusplus
32 | extern "C" {
33 | #endif
34 |
35 | /* Includes */
36 | #include "stm32f10x.h"
37 |
38 | /**
39 | * @addtogroup stm32_examples
40 | * @{
41 | */
42 |
43 | /**
44 | * @addtogroup itm
45 | * @{
46 | */
47 |
48 | /**
49 | * @defgroup itm_exported_typedefs
50 | * @{
51 | */
52 |
53 | /**
54 | * @}
55 | */
56 |
57 | /**
58 | * @defgroup itm_exported_defines
59 | * @{
60 | */
61 |
62 | /**
63 | * @}
64 | */
65 |
66 | /**
67 | * @defgroup itm_exported_macros
68 | * @{
69 | */
70 |
71 | /**
72 | * @}
73 | */
74 |
75 | /**
76 | * @defgroup itm_exported_constants
77 | * @{
78 | */
79 |
80 | /**
81 | * @}
82 | */
83 |
84 | /**
85 | * @defgroup itm_exported_functions
86 | * @{
87 | */
88 | /**
89 | * @brief ITM_Printf
90 | * @note
91 | * @param str, length
92 | * @retval None
93 | */
94 | void ITM_Printf(char *str, int length);
95 |
96 | /**
97 | * @brief SendChar
98 | * @note
99 | * @param port, ch
100 | * @retval
101 | */
102 | void ITM_SendChar_Port(uint8_t port, uint8_t ch);
103 |
104 | /**
105 | * @brief ITM_Printf_Port
106 | * @note
107 | * @param port, str, length
108 | * @retval None
109 | */
110 | void ITM_Printf_Port(uint8_t port, char *str, int length);
111 |
112 | /**
113 | * @}
114 | */
115 | /**
116 | * @}
117 | */
118 | /**
119 | * @}
120 | */
121 |
122 | /* C++ detection */
123 | #ifdef __cplusplus
124 | }
125 | #endif
126 |
127 | #endif /*__INC_ITM_H_ */
128 |
--------------------------------------------------------------------------------
/src/inc/memcpy.h:
--------------------------------------------------------------------------------
1 | /*******************************************************************************
2 | * @file memcpy.h
3 | * @author Rashad Shubita
4 | * @email shubitarashad@gmail.com
5 | * @date 15.02.2019
6 | *
7 | * @brief Copy data between two memory buffers
8 | * @note
9 | *
10 | @verbatim
11 | Copyright (C) 2019, Rashad Shubita
12 |
13 | This program is free software: you can redistribute it and/or modify it under
14 | the terms of the GNU General Public License as published by the Free Software
15 | Foundation, either version 3 of the License, or any later version.
16 |
17 | This program is distributed in the hope that it will be useful, but WITHOUT
18 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
19 | FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
20 |
21 | You should have received a copy of the GNU General Public License along with
22 | this program. If not, see .
23 | @endverbatim
24 | *******************************************************************************/
25 |
26 | /* Define to prevent recursive inclusion */
27 | #ifndef __INC_MEMCPY_H_
28 | #define __INC_MEMCPY_H_
29 |
30 | /* C++ detection */
31 | #ifdef __cplusplus
32 | extern "C" {
33 | #endif
34 |
35 | /* Includes */
36 | #include "stm32f10x.h"
37 |
38 | /**
39 | * @addtogroup stm32_examples
40 | * @{
41 | */
42 |
43 | /**
44 | * @addtogroup memcpy
45 | * @{
46 | */
47 |
48 | /**
49 | * @defgroup memcpy_exported_typedefs
50 | * @{
51 | */
52 |
53 | /**
54 | * @brief Return type
55 | */
56 | typedef enum
57 | {
58 | RETURN_STATUS_OK = 0u,
59 | RETURN_STATUS_NOT_OK = 1u
60 | } ReturnStatus_Type;
61 |
62 | /**
63 | * @}
64 | */
65 |
66 | /**
67 | * @defgroup memcpy_exported_defines
68 | * @{
69 | */
70 |
71 | /**
72 | * @}
73 | */
74 |
75 | /**
76 | * @defgroup memcpy_exported_macros
77 | * @{
78 | */
79 |
80 | /**
81 | * @}
82 | */
83 |
84 | /**
85 | * @defgroup memcpy_exported_constants
86 | * @{
87 | */
88 |
89 | /**
90 | * @}
91 | */
92 |
93 | /**
94 | * @defgroup memcpy_exported_functions
95 | * @{
96 | */
97 |
98 | /**
99 | * @brief Copy data between two memory buffers
100 | * @note
101 | * @param src, dst, size
102 | * @retval RETURN_STATUS_OK, RETURN_STATUS_NOT_OK
103 | */
104 | ReturnStatus_Type memcpy32(const uint32_t * src,
105 | uint32_t * dst, const uint32_t size);
106 |
107 | /**
108 | * @}
109 | */
110 | /**
111 | * @}
112 | */
113 | /**
114 | * @}
115 | */
116 |
117 | /* C++ detection */
118 | #ifdef __cplusplus
119 | }
120 | #endif
121 |
122 | #endif /*__INC_MEMCPY_H_ */
123 |
--------------------------------------------------------------------------------
/src/inc/nvic.h:
--------------------------------------------------------------------------------
1 | /*******************************************************************************
2 | * @file nvic.h
3 | * @author Rashad Shubita
4 | * @email shubitarashad@gmail.com
5 | * @date 08.02.2019
6 | *
7 | * @brief NVIC configuration header file
8 | * @note
9 | *
10 | @verbatim
11 | Copyright (C) 2019, Rashad Shubita
12 |
13 | This program is free software: you can redistribute it and/or modify it under
14 | the terms of the GNU General Public License as published by the Free Software
15 | Foundation, either version 3 of the License, or any later version.
16 |
17 | This program is distributed in the hope that it will be useful, but WITHOUT
18 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
19 | FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
20 |
21 | You should have received a copy of the GNU General Public License along with
22 | this program. If not, see .
23 | @endverbatim
24 | *******************************************************************************/
25 |
26 |
27 | #ifndef INC_NVIC_H_
28 | #define INC_NVIC_H_
29 |
30 |
31 | /* Includes */
32 | #include "stm32f10x.h"
33 |
34 | /**
35 | * @brief NVIC IRQs initialization function
36 | * @note
37 | * @param None
38 | * @retval None
39 | */
40 | void NVIC_Init(void);
41 |
42 |
43 | #endif /* INC_NVIC_H_ */
44 |
--------------------------------------------------------------------------------
/src/inc/usart.h:
--------------------------------------------------------------------------------
1 | /*******************************************************************************
2 | * @file usart.h
3 | * @author Rashad Shubita
4 | * @email shubitarashad@gmail.com
5 | * @date 23.02.2019
6 | *
7 | * @brief USART configuration header file
8 | * @note
9 | *
10 | @verbatim
11 | Copyright (C) 2019, Rashad Shubita
12 |
13 | This program is free software: you can redistribute it and/or modify it under
14 | the terms of the GNU General Public License as published by the Free Software
15 | Foundation, either version 3 of the License, or any later version.
16 |
17 | This program is distributed in the hope that it will be useful, but WITHOUT
18 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
19 | FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
20 |
21 | You should have received a copy of the GNU General Public License along with
22 | this program. If not, see .
23 | @endverbatim
24 | *******************************************************************************/
25 |
26 |
27 | #ifndef INC_USART_H_
28 | #define INC_USART_H_
29 |
30 | #include "stm32f10x.h"
31 | #include "gpio.h"
32 | #include
33 | #include "dma.h"
34 |
35 | #define Yes 1
36 | #define No 0
37 |
38 |
39 | /**
40 | * @brief USART1 GPIO initialization function
41 | * @note PA9 -> USART1_TX
42 | * PA10 -> USART1_RX
43 | * PA11 -> USART1_CTS
44 | * PA12 -> USART1_RTS
45 | * "Table 5. Medium-density STM32F103xx pin definitions" in Datasheet
46 | * "Table 24. USARTs" in Reference manual
47 | * @param HFC if = 1 -> Init. CTS & RTS pins
48 | * @retval None
49 | */
50 | void USART1_GPIO_Init(uint8_t HFC);
51 |
52 | /**
53 | * @brief USART BRR value calculation
54 | * @note F_CK Input clock to the peripheral(PCLK1[APB1] for USART2, 3, 4, 5 or PCLK2[APB2] for USART1) & always over-sampling by 16
55 | * @param Baud_Rate: Desired Baud Rate value
56 | * F_CK: Input clock to the peripheral in Hz
57 | * @retval Value of BRR
58 | */
59 | uint16_t Cal_USART_BRR_Val(uint32_t Baud_Rate, uint32_t F_CK);
60 |
61 | /**
62 | * @brief USART initialization function
63 | * @note None
64 | * @param BRR_Val: Can be calculated using Cal_USART_BRR_Val function
65 | * @retval None
66 | */
67 | void USART1_Init(uint16_t BRR_Val);
68 |
69 | /**
70 | * @brief Enable USART transmitter and receiver
71 | * @note
72 | * @param USARTx ,where x=1 ..3
73 | * @retval None
74 | */
75 | void USART_Enable(USART_TypeDef *USARTx);
76 |
77 |
78 | /**
79 | * @brief String transmit
80 | * @note
81 | * @param USARTX, str
82 | * @retval None
83 | */
84 | void USART_Send_String(USART_TypeDef *USARTx,const char *str);
85 |
86 | /**
87 | * @brief DMA1 Channel4 initialization function
88 | * @note Used for data transfer between two memory buffers
89 | * @param None
90 | * @retval None
91 | */
92 | void USART1_TX_DMA_Config(void);
93 |
94 | /**
95 | * @brief DMA1 Channel5 initialization function
96 | * @note Used for data transfer between two memory buffers
97 | * @param None
98 | * @retval None
99 | */
100 | void USART1_RX_DMA_Config(void);
101 |
102 | /**
103 | * @brief IRQ callback function
104 | * @note
105 | * @param None
106 | * @retval None
107 | */
108 | void USART1_RX_DMA_IRQ_Callback(void);
109 |
110 | /**
111 | * @brief IRQ callback function
112 | * @note
113 | * @param None
114 | * @retval None
115 | */
116 | void USART1_TX_DMA_IRQ_Callback(void);
117 |
118 | /**
119 | * @brief IRQ callback function
120 | * @note
121 | * @param None
122 | * @retval None
123 | */
124 | void USART1_IRQ_Callback(void);
125 |
126 | /**
127 | * @brief USART1 transmit and receive data
128 | * @note
129 | * @param None
130 | * @retval None
131 | */
132 | void USART1_Process(void);
133 |
134 | #endif /* INC_USART_H_ */
135 |
--------------------------------------------------------------------------------
/src/main.c:
--------------------------------------------------------------------------------
1 | /*******************************************************************************
2 | * @file main.c
3 | * @author Rashad Shubita
4 | * @email shubitarashad@gmail.com
5 | * @date 20.01.2019
6 | *
7 | * @brief main application called after startup
8 | * @note
9 | *
10 | @verbatim
11 | Copyright (C) 2019, Rashad Shubita
12 |
13 | This program is free software: you can redistribute it and/or modify it under
14 | the terms of the GNU General Public License as published by the Free Software
15 | Foundation, either version 3 of the License, or any later version.
16 |
17 | This program is distributed in the hope that it will be useful, but WITHOUT
18 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
19 | FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
20 |
21 | You should have received a copy of the GNU General Public License along with
22 | this program. If not, see .
23 | @endverbatim
24 | *******************************************************************************/
25 |
26 |
27 |
28 | /* Includes ------------------------------------------------------------------*/
29 | #include "nvic.h"
30 | #include "SysTick.h"
31 | #include "gpio.h"
32 | #include "LIN_Slave.h"
33 | #include "itm.h"
34 |
35 | /* Private typedef -----------------------------------------------------------*/
36 | /* Private define ------------------------------------------------------------*/
37 | /* Private macro -------------------------------------------------------------*/
38 | /* Private variables ---------------------------------------------------------*/
39 | /* Private function prototypes -----------------------------------------------*/
40 | /* Private functions ---------------------------------------------------------*/
41 |
42 | /**
43 | **===========================================================================
44 | **
45 | ** Abstract: main program
46 | **
47 | **===========================================================================
48 | */
49 | int main(void)
50 | {
51 | uint32_t x= 0;
52 |
53 | SysTick_Init();
54 | GPIO_OnBoard_Init_LED();
55 | NVIC_Init();
56 |
57 | LIN_Slave_GPIO_Init();
58 | LIN_Slave_USART3_Init();
59 | LIN_Slave_TX_DMA_Init();
60 | LIN_Slave_RX_DMA_Init();
61 |
62 | /* Clear PRIMASK, enable IRQs */
63 | __enable_irq();
64 | /* Send 10 to ITM port 2 */
65 |
66 | LIN_Slave_Enable();
67 | SysTick_Delay(400);
68 |
69 | /* Infinite loop */
70 | while(1)
71 | {
72 | LIN_Master_Process(0x1A, 0x1B, 0xCA);
73 | SysTick_Delay(200);
74 | LIN_Master_Process(0x0A, 0x0B, 0xEA);
75 | SysTick_Delay(200);
76 | }
77 |
78 | }
79 |
80 |
81 |
--------------------------------------------------------------------------------
/src/src/DS18B20.c:
--------------------------------------------------------------------------------
1 | /*******************************************************************************
2 | * @file DS18B20.c
3 | * @author Rashad Shubita
4 | * @email shubitarashad@gmail.com
5 | * @date 20.01.2019
6 | *
7 | * @brief Interfacing temperature sensor DS18B20 using UART over one-wire
8 | * @note
9 | *
10 | @verbatim
11 | Copyright (C) 2019, Rashad Shubita
12 |
13 | This program is free software: you can redistribute it and/or modify it under
14 | the terms of the GNU General Public License as published by the Free Software
15 | Foundation, either version 3 of the License, or any later version.
16 |
17 | This program is distributed in the hope that it will be useful, but WITHOUT
18 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
19 | FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
20 |
21 | You should have received a copy of the GNU General Public License along with
22 | this program. If not, see .
23 | @endverbatim
24 | *******************************************************************************/
25 |
26 |
27 | /* Includes */
28 | #include
29 | #include "SysTick.h"
30 | #include "gpio.h"
31 | #include "DS18B20.h"
32 | #include "usart.h"
33 |
34 | /* Private typedef -----------------------------------------------------------*/
35 | /* Private define ------------------------------------------------------------*/
36 |
37 | /**
38 | * @brief Reset command
39 | */
40 | #define DS18B20_RESET_CMD ((uint8_t) 0xF0)
41 |
42 | /**
43 | * @brief Logical bit values
44 | */
45 | #define BIT_0 ((uint8_t) 0x00)
46 | #define BIT_1 ((uint8_t) 0xFF)
47 |
48 | /**
49 | * @brief Conversion time in ms, from DS18B20 datasheet
50 | */
51 | #define MAX_CONVERSION_TIME ((uint32_t) 750)
52 |
53 | /* Private macro -------------------------------------------------------------*/
54 | /* Private constants ---------------------------------------------------------*/
55 | /**
56 | * @brief Temperature convert, {Skip ROM = 0xCC, Convert = 0x44}
57 | */
58 | static const uint8_t temp_convert[] =
59 | {
60 | BIT_0, BIT_0, BIT_1, BIT_1, BIT_0, BIT_0, BIT_1, BIT_1,
61 | BIT_0, BIT_0, BIT_1, BIT_0, BIT_0, BIT_0, BIT_1, BIT_0
62 | };
63 |
64 | /**
65 | * @brief Temperature data read, {Skip ROM = 0xCC, Scratch read = 0xBE}
66 | */
67 | static const uint8_t temp_read[] =
68 | {
69 | BIT_0, BIT_0, BIT_1, BIT_1, BIT_0, BIT_0, BIT_1, BIT_1,
70 | BIT_0, BIT_1, BIT_1, BIT_1, BIT_1, BIT_1, BIT_0, BIT_1,
71 | BIT_1, BIT_1, BIT_1, BIT_1, BIT_1, BIT_1, BIT_1, BIT_1,
72 | BIT_1, BIT_1, BIT_1, BIT_1, BIT_1, BIT_1, BIT_1, BIT_1
73 | };
74 |
75 | /* Private variables ---------------------------------------------------------*/
76 | /**
77 | * @brief Received temperature data using DMA
78 | */
79 | static uint8_t temperatureData[sizeof(temp_read)];
80 |
81 | /**
82 | * @brief Temperature data received flag
83 | */
84 | static uint8_t temperatureDataReceived = 0;
85 |
86 | /**
87 | * @brief Current temperature value in degree celsius
88 | */
89 | static float currentTemperature = 0;
90 |
91 | /* Private function prototypes -----------------------------------------------*/
92 | /**
93 | * @brief DMA command transmit
94 | * @note
95 | * @param cmd, size
96 | * @retval None
97 | */
98 | static void cmdTransmit(const uint8_t * cmd, uint8_t size);
99 |
100 | /**
101 | * @brief DMA command receive
102 | * @note
103 | * @param cmd, size
104 | * @retval None
105 | */
106 | static void cmdReceive(const uint8_t * cmd, uint8_t size);
107 |
108 | /**
109 | * @brief Send reset pulse to DS18B20
110 | * @note
111 | * @param None
112 | * @retval None
113 | */
114 | static uint8_t cmdReset(void);
115 |
116 | /* Private functions ---------------------------------------------------------*/
117 |
118 | /**
119 | * @brief DMA string transmit
120 | * @note IMPORTANT: Since we send and receive the reset pulse without DMA,
121 | * its necessary to clear any pending DMA requests before
122 | * enable transmission DMA stream.
123 | * @param cmd, size
124 | * @retval None
125 | */
126 | static void cmdTransmit(const uint8_t * cmd, uint8_t size)
127 | {
128 | /* Check null pointers */
129 | if(NULL != cmd)
130 | {
131 | /* disable channel, since this registers must not be written when the channel is enabled */
132 | if(DMA_CCR1_EN == (DMA_CCR1_EN & DMA1_Channel2->CCR))
133 | {
134 | /* DMA 1 channel 2 is enabled, shall be disabled first */
135 | DMA1_Channel2->CCR &= ~DMA_CCR1_EN;
136 |
137 | /* Wait until EN bit is cleared */
138 | while(DMA_CCR1_EN == (DMA_CCR1_EN & DMA1_Channel2->CCR))
139 | {
140 | /* Do nothing until EN bit is cleared */
141 | }
142 | }
143 | else
144 | {
145 | /* Do nothing, channel 2 is not enabled */
146 | }
147 |
148 | /* Set address for memory */
149 | DMA1_Channel2 ->CMAR = (uint32_t)cmd;
150 |
151 | /* Set number of data items */
152 | DMA1_Channel2 ->CNDTR = size;
153 |
154 | /* Clear transfer complete flag */
155 | DMA1->IFCR |= DMA_IFCR_CTCIF2;
156 |
157 | /* Clears the GIF, TEIF, HTIF and TCIF flags in the DMA_ISR register */
158 | DMA1->IFCR |= DMA_IFCR_CGIF2;
159 |
160 | /* Clear any USART pending DMA requests */
161 | USART3->CR3 &= ~USART_CR3_DMAT;
162 |
163 | /* Enable DMA mode for transmitter */
164 | USART3->CR3 |= USART_CR3_DMAT;
165 |
166 | /* Enable DMA 1 channel 2 */
167 | DMA1_Channel2->CCR |= DMA_CCR1_EN;
168 | }
169 | else
170 | {
171 | /* Null pointers, do nothing */
172 | }
173 |
174 | }
175 |
176 | /**
177 | * @brief DMA string receive
178 | * @note IMPORTANT: Since we send and receive the reset pulse without DMA,
179 | * its necessary to clear any pending DMA requests before
180 | * enable reception DMA stream.
181 | * @param cmd, size
182 | * @retval None
183 | */
184 | static void cmdReceive(const uint8_t * cmd, uint8_t size)
185 | {
186 | /* Check null pointers */
187 | if(NULL != cmd)
188 | {
189 |
190 | /* Set address for memory */
191 | DMA1_Channel3 ->CMAR = (uint32_t)cmd;
192 |
193 | /* Set number of data items */
194 | DMA1_Channel3 ->CNDTR = size;
195 |
196 | /* Clear transfer complete flag */
197 | DMA1->IFCR |= DMA_IFCR_CTCIF3;
198 |
199 | /* Clears the GIF, TEIF, HTIF and TCIF flags in the DMA_ISR register */
200 | DMA1->IFCR |= DMA_IFCR_CGIF3;
201 |
202 | /* Clear any USART pending DMA requests */
203 | USART3->CR3 &= ~USART_CR3_DMAR;
204 |
205 | /* Enable DMA mode for reception */
206 | USART3->CR3 |= USART_CR3_DMAR;
207 |
208 | /* Enable DMA 1 channel 3 */
209 | DMA1_Channel3->CCR |= DMA_CCR1_EN;
210 | }
211 | else
212 | {
213 | /* Null pointers, do nothing */
214 | }
215 | }
216 |
217 | /**
218 | * @brief Send reset pulse to DS18B20
219 | * @note
220 | * @param None
221 | * @retval None
222 | */
223 | static uint8_t cmdReset(void)
224 | {
225 | uint8_t isSensorDetected = 0;
226 |
227 | /* Disable USART3 prescaler and outputs */
228 | USART3->CR1 &= ~USART_CR1_UE;
229 |
230 | /* Set baud rate = 9600 Bps */
231 | USART3->BRR = Cal_USART_BRR_Val(9600,8000000);
232 |
233 | /* Enable USART3 prescaler and outputs */
234 | USART3->CR1 |= USART_CR1_UE;
235 |
236 | /* Check USART status register */
237 | while(!(USART3->SR & USART_SR_TXE))
238 | {
239 | /* Wait for transmission buffer empty flag */
240 | }
241 |
242 | /* Write reset command */
243 | USART3->DR = DS18B20_RESET_CMD;
244 |
245 | /* Check USART status register */
246 | while(!(USART3->SR & USART_SR_TC))
247 | {
248 | /* Wait for transmission complete flag */
249 | }
250 |
251 | /* Read Rx Data */
252 | uint16_t Rx = USART3->DR;
253 |
254 | /* Check sensor presence */
255 | if((DS18B20_RESET_CMD != Rx) && ( BIT_0 != Rx))
256 | {
257 | /* Temp sensor was detected */
258 | isSensorDetected = 1;
259 | }
260 | else
261 | {
262 | /* Do nothing, No sensor was detected */
263 | }
264 |
265 | /* Disable USART3 prescaler and outputs */
266 | USART3->CR1 &= ~USART_CR1_UE;
267 |
268 | /* Set baud rate = 115200 Bps */
269 | USART3->BRR = Cal_USART_BRR_Val(115200, 8000000);
270 |
271 | /* Enable USART3 prescaler and outputs */
272 | USART3->CR1 |= USART_CR1_UE;
273 |
274 | return isSensorDetected;
275 | }
276 |
277 | /**
278 | * @}
279 | */
280 |
281 | /**
282 | * @defgroup DS18B20_exported_functions
283 | * @{
284 | */
285 |
286 | /**
287 | * @brief Configure GPIO
288 | * @note UART3_TX -> PB10, UART3_RX -> PB11 from "Datasheet rev17 page:30"
289 | * GPIO configuration from "Reference manual [Table 24. USARTs]
290 | * UART3 connected to APB1 with 36MHz max clock
291 | * @param None
292 | * @retval None
293 | */
294 | void DS18B20_GPIO_Init(void)
295 | {
296 | /* GPIOB clock enable */
297 | RCC ->APB2ENR |= RCC_APB2ENR_IOPBEN;
298 |
299 | /* PB10 TX: Output mode, max speed 2 MHz. */
300 | GPIOB ->CRH &= ~GPIO_CRH_MODE10;
301 | GPIOB ->CRH |= GPIO_CRH_MODE10_1;
302 |
303 | /* PB10 TX: Alternate function output Push-pull */
304 | GPIOB ->CRH &= ~GPIO_CRH_CNF10;
305 | GPIOB ->CRH |= GPIO_CRH_CNF10_1;
306 | }
307 |
308 | /**
309 | * @brief Configure DMA for USART TX
310 | * @note USART3_TX -> DMA1_Channel2
311 | * @param None
312 | * @retval None
313 | */
314 | void DS18B20_TX_DMA_Init(void)
315 | {
316 | /* Enable clock for DMA1*/
317 | RCC ->AHBENR |= RCC_AHBENR_DMA1EN;
318 |
319 | /* disable channel, since this registers must not be written when the channel is enabled */
320 | if(DMA_CCR1_EN == (DMA_CCR1_EN & DMA1_Channel2->CCR))
321 | {
322 | /* DMA 1 channel 2 is enabled, shall be disabled first */
323 | DMA1_Channel2->CCR &= ~DMA_CCR1_EN;
324 |
325 | /* Wait until EN bit is cleared */
326 | while(DMA_CCR1_EN == (DMA_CCR1_EN & DMA1_Channel2->CCR))
327 | {
328 | /* Do nothing until EN bit is cleared */
329 | }
330 | }
331 | else
332 | {
333 | /* Do nothing, channel 2 is not enabled */
334 | }
335 |
336 | /* Set Peripheral size 8-bits (00)*/
337 | DMA1_Channel2 ->CCR &= ~DMA_CCR1_PSIZE;
338 |
339 | /* Set Memory size 8-bits (00)*/
340 | DMA1_Channel2 ->CCR &= ~DMA_CCR1_MSIZE;
341 |
342 | /* Set Channel priority Very high (11)*/
343 | DMA1_Channel2 ->CCR |= DMA_CCR1_PL;
344 |
345 | /* Disable Peripheral increment mode (0) */
346 | DMA1_Channel2 ->CCR &= ~DMA_CCR1_PINC;
347 |
348 | /* Enable memory increment mode (1)*/
349 | DMA1_Channel2 ->CCR |= DMA_CCR1_MINC;
350 |
351 | /* Disable Circular mode (0)*/
352 | DMA1_Channel2 ->CCR &= ~DMA_CCR1_CIRC;
353 |
354 | /* Diable M2M Mode (0) */
355 | DMA1_Channel2 ->CCR &= ~DMA_CCR1_MEM2MEM;
356 |
357 | /* Data transfer direction Read from memory(memory-to-peripheral) (1)*/
358 | DMA1_Channel2 ->CCR |= DMA_CCR1_DIR;
359 |
360 | /* Enable Transfer complete interrupt */
361 | DMA1_Channel2 ->CCR |= DMA_CCR1_TCIE;
362 |
363 | /* Set address for peripheral */
364 | DMA1_Channel2 ->CPAR = (uint32_t)&USART3->DR;
365 |
366 | __ASM("NOP");
367 | __ASM("NOP");
368 | __ASM("NOP");
369 | __ASM("NOP");
370 |
371 | }
372 |
373 | /**
374 | * @brief Configure DMA for UART RX
375 | * @note USART3_RX -> DMA1_Channel3
376 | * @param None
377 | * @retval None
378 | */
379 | void DS18B20_RX_DMA_Init(void)
380 | {
381 | /* Enable clock for DMA1*/
382 | RCC ->AHBENR |= RCC_AHBENR_DMA1EN;
383 |
384 | /* disable channel, since this registers must not be written when the channel is enabled */
385 | if(DMA_CCR1_EN == (DMA_CCR1_EN & DMA1_Channel3->CCR))
386 | {
387 | /* DMA 1 channel 3 is enabled, shall be disabled first */
388 | DMA_ChannelDisable(DMA1_Channel3);
389 |
390 | /* Wait until EN bit is cleared */
391 | while(DMA_CCR1_EN == (DMA_CCR1_EN & DMA1_Channel3->CCR))
392 | {
393 | /* Do nothing until EN bit is cleared */
394 | }
395 | }
396 | else
397 | {
398 | /* Do nothing, channel 3 is not enabled */
399 | }
400 |
401 | /* Set Peripheral size 8-bits (00)*/
402 | DMA1_Channel3 ->CCR &= ~DMA_CCR1_PSIZE;
403 |
404 | /* Set Memory size 8-bits (00)*/
405 | DMA1_Channel3 ->CCR &= ~DMA_CCR1_MSIZE;
406 |
407 | /* Set Channel priority Very high (11)*/
408 | DMA1_Channel3 ->CCR |= DMA_CCR1_PL;
409 |
410 | /* Disable Peripheral increment mode (0) */
411 | DMA1_Channel3 ->CCR &= ~DMA_CCR1_PINC;
412 |
413 | /* Enable memory increment mode (1)*/
414 | DMA1_Channel3 ->CCR |= DMA_CCR1_MINC;
415 |
416 | /* Disable Circular mode (0)*/
417 | DMA1_Channel3 ->CCR &= ~DMA_CCR1_CIRC;
418 |
419 | /* Diable M2M Mode (0) */
420 | DMA1_Channel3 ->CCR &= ~DMA_CCR1_MEM2MEM;
421 |
422 | /* Data transfer direction Read from peripheral (0)*/
423 | DMA1_Channel3 ->CCR &= ~DMA_CCR1_DIR;
424 |
425 | /* Enable Transfer complete interrupt */
426 | DMA1_Channel3 ->CCR |= DMA_CCR1_TCIE;
427 |
428 | /* Set address for peripheral */
429 | DMA1_Channel3 ->CPAR = (uint32_t)&USART3->DR;
430 |
431 | __ASM("NOP");
432 | __ASM("NOP");
433 | __ASM("NOP");
434 | __ASM("NOP");
435 |
436 | }
437 |
438 | /**
439 | * @brief Configure USART3 for DS18B20
440 | * @note
441 | * @param None
442 | * @retval None
443 | */
444 | void DS18B20_USART3_Init(void)
445 | {
446 | /* Enable USART3 clock */
447 | RCC-> APB1ENR |= RCC_APB1ENR_USART3EN;
448 |
449 | /* select 1 Start bit, 8 Data bits, n Stop bit */
450 | USART3 ->CR1 &= ~USART_CR1_M;
451 |
452 | /* STOP bits, 00: 1 Stop bit */
453 | USART3->CR2 &= ~USART_CR2_STOP;
454 |
455 | /* Select Single-wire Half-duplex mode */
456 | USART3->CR3 |= USART_CR3_HDSEL;
457 | }
458 |
459 | /**
460 | * @brief Enable communications with DS18B20
461 | * @note
462 | * @param None
463 | * @retval None
464 | */
465 | void DS18B20_USART3_Enable(void)
466 | {
467 | /* Enable USART3 */
468 | USART3->CR1 |= USART_CR1_UE;
469 |
470 | /* Enable transmitter */
471 | USART3->CR1 |= USART_CR1_TE;
472 |
473 | /* Enable receiver */
474 | USART3->CR1 |= USART_CR1_RE;
475 | }
476 |
477 | /**
478 | * @brief DS18B20 process function
479 | * @note
480 | * @param None
481 | * @retval None
482 | */
483 | void DS18B20_Process(void)
484 | {
485 | /* Sensor detected flag */
486 | uint8_t isSensorDetected = 0;
487 |
488 | /* Send reset pulse */
489 | isSensorDetected = cmdReset();
490 |
491 | /* Check if the sensor was detected */
492 | if(1 == isSensorDetected)
493 | {
494 | /* Turn on green LED */
495 | //GPIO_TurnON_LED(EVAL_GREEN_LED);
496 |
497 | /* Send temperature conversion command */
498 | cmdTransmit(temp_convert, sizeof(temp_convert));
499 |
500 | /* Wait conversion time */
501 | SysTick_Delay(MAX_CONVERSION_TIME);
502 |
503 | /* Send reset pulse */
504 | cmdReset();
505 |
506 | /* Enable temperature data reception with DMA */
507 | cmdReceive(temperatureData, sizeof(temperatureData));
508 |
509 | /* Send temperature read command */
510 | cmdTransmit(temp_read, sizeof(temp_read));
511 |
512 | /* Check temperature data received flag */
513 | while (temperatureDataReceived == 0)
514 | {
515 | /* Wait until DMA receive temperature data */
516 | }
517 |
518 | /* Reset temperature data received flag */
519 | temperatureDataReceived = 0;
520 |
521 | /* Temporarily variable for extracting temperature data */
522 | uint16_t temperature = 0;
523 |
524 | /* Extract new temperature data */
525 | for (int idx = 16; idx < 32; idx++)
526 | {
527 | if (BIT_1 == temperatureData[idx])
528 | {
529 | /* Bit value is 1 */
530 | temperature = (temperature >> 1) | 0x8000;
531 | }
532 | else
533 | {
534 | /* Bit value is 0 */
535 | temperature = temperature >> 1;
536 | }
537 | }
538 |
539 | /* Copying new temperature data and divide by 16 for fraction part */
540 | currentTemperature = (float) temperature / (float) 16;
541 |
542 | }
543 | else
544 | {
545 | /* Turn on red LED, indicates sensor detection failed */
546 | //GPIO_TurnON_LED(EVAL_RED_LED);
547 |
548 | /* Temperature data not valid */
549 | currentTemperature = 0;
550 | }
551 | }
552 |
553 | /**
554 | * @brief IRQ callback function
555 | * @note
556 | * @param None
557 | * @retval None
558 | */
559 | void USART3_TX_DMA_IRQ_Callback(void)
560 | {
561 | /* Check transfer complete flag */
562 | if((DMA1->ISR & DMA_ISR_TCIF2) == DMA_ISR_TCIF2)
563 | {
564 | /* DMA transfer is complete */
565 |
566 | /* Clear transfer complete flag */
567 | DMA1->IFCR |= DMA_IFCR_CTCIF2;
568 |
569 | /* Clears the GIF, TEIF, HTIF and TCIF flags in the DMA_ISR register */
570 | DMA1->IFCR |= DMA_IFCR_CGIF2;
571 | }
572 |
573 | else
574 | {
575 | /* Do nothing, this interrupt is not handled */
576 | }
577 |
578 | }
579 |
580 | /**
581 | * @brief IRQ callback function
582 | * @note
583 | * @param None
584 | * @retval None
585 | */
586 | void USART3_RX_DMA_IRQ_Callback(void)
587 | {
588 |
589 | /* Check transfer complete flag */
590 | if((DMA1->ISR & DMA_ISR_TCIF3) == DMA_ISR_TCIF3)
591 | {
592 | /* DMA transfer is complete */
593 |
594 | /* Clear transfer complete flag */
595 | DMA1->IFCR |= DMA_IFCR_CTCIF3;
596 |
597 | /* Clears the GIF, TEIF, HTIF and TCIF flags in the DMA_ISR register */
598 | DMA1->IFCR |= DMA_IFCR_CGIF3;
599 | /* Set transfer complete flag */
600 | temperatureDataReceived = 1;
601 | }
602 |
603 | else
604 | {
605 | /* Do nothing, this interrupt is not handled */
606 | }
607 |
608 | }
609 |
610 |
611 |
612 |
613 |
--------------------------------------------------------------------------------
/src/src/LIN_Slave.c:
--------------------------------------------------------------------------------
1 | /*******************************************************************************
2 | * @file LIN_Slave.c
3 | * @author Rashad Shubita
4 | * @email shubitarashad@gmail.com
5 | * @date 23.01.2019
6 | *
7 | * @brief LIN slave node driver
8 | * @note
9 | *
10 | @verbatim
11 | Copyright (C) 2019, Rashad Shubita
12 |
13 | This program is free software: you can redistribute it and/or modify it under
14 | the terms of the GNU General Public License as published by the Free Software
15 | Foundation, either version 3 of the License, or any later version.
16 |
17 | This program is distributed in the hope that it will be useful, but WITHOUT
18 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
19 | FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
20 |
21 | You should have received a copy of the GNU General Public License along with
22 | this program. If not, see .
23 | @endverbatim
24 | *******************************************************************************/
25 |
26 | /* Includes */
27 | #include
28 | #include "gpio.h"
29 | #include "LIN_Slave.h"
30 | #include "usart.h"
31 | #include "itm.h"
32 |
33 | /* Private typedef -----------------------------------------------------------*/
34 |
35 | /**
36 | * @brief LIN slave states definition
37 | */
38 | typedef enum
39 | {
40 | LINS_IDLE,
41 | LINS_BREAK_RECEIVED,
42 | LINS_WAIT_FOR_HEADER,
43 | LINS_HEADER_RECEIVED,
44 | LINS_RX_DATA,
45 | LINS_WAIT_FOR_RX_DATA,
46 | LINS_RX_DATA_RECEIVED,
47 | LINS_TX_DATA
48 | } LIN_Slave_StateType;
49 |
50 | /**
51 | * @brief LIN slave error status definition
52 | */
53 | typedef enum
54 | {
55 | LINS_NO_ERROR,
56 | LINS_SYNC_ERROR,
57 | LINS_CHECKSUM_INVALID_ERROR
58 | } LIN_Slave_ErrorStatusType;
59 |
60 | /* Private define ------------------------------------------------------------*/
61 |
62 | /**
63 | * @brief LIN Header Length
64 | */
65 | #define LIN_HEADER_LENGTH ((uint8_t) 2u)
66 |
67 | /**
68 | * @brief LIN data length including the checksum
69 | */
70 | #define LIN_DATA_LENGTH ((uint8_t) 3u)
71 |
72 | /* Private macro -------------------------------------------------------------*/
73 | /* Private constants ---------------------------------------------------------*/
74 |
75 | /* Private variables ---------------------------------------------------------*/
76 |
77 | /**
78 | * @brief LIN slave current state
79 | */
80 | static LIN_Slave_StateType currentState = LINS_IDLE;
81 |
82 | /**
83 | * @brief LIN slave current error status
84 | */
85 | static LIN_Slave_ErrorStatusType currentErrorStatus = LINS_NO_ERROR;
86 |
87 | /**
88 | * @brief LIN Header, 2 bytes
89 | */
90 | static uint8_t linHeader[LIN_HEADER_LENGTH];
91 |
92 | /**
93 | * @brief LIN Header For TX, 2 bytes
94 | */
95 | static uint8_t linHeader_TX[LIN_HEADER_LENGTH];
96 |
97 | /**
98 | * @brief LIN Data, 3 bytes
99 | */
100 | static uint8_t linData[LIN_DATA_LENGTH];
101 |
102 | /**
103 | * @brief DMA received flag
104 | */
105 | static uint8_t RxDMAReceived = 0;
106 |
107 | /* Private function prototypes -----------------------------------------------*/
108 |
109 | /**
110 | * @brief DMA receive
111 | * @note
112 | * @param data, size
113 | * @retval None
114 | */
115 | static void DMAReceive(const uint8_t * data, uint8_t size);
116 |
117 | /**
118 | * @}
119 | */
120 |
121 | /**
122 | * @defgroup LIN_Slave_private_functions
123 | * @{
124 | */
125 |
126 | /**
127 | * @brief DMA receive
128 | * @note
129 | * @param data, size
130 | * @retval None
131 | */
132 | static void DMAReceive(const uint8_t * data, uint8_t size)
133 | {
134 | /* Check null pointers */
135 | if(NULL != data)
136 | {
137 | /* disable channel, since this registers must not be written when the channel is enabled */
138 | if(DMA_CCR1_EN == (DMA_CCR1_EN & DMA1_Channel3->CCR))
139 | {
140 | /* DMA 1 channel 3 is enabled, shall be disabled first */
141 | DMA_ChannelDisable(DMA1_Channel3);
142 |
143 | /* Wait until EN bit is cleared */
144 | while(DMA_CCR1_EN == (DMA_CCR1_EN & DMA1_Channel3->CCR))
145 | {
146 | /* Do nothing until EN bit is cleared */
147 | }
148 | }
149 | else
150 | {
151 | /* Do nothing, channel 3 is not enabled */
152 | }
153 |
154 | /* Set address for memory */
155 | DMA1_Channel3 ->CMAR = (uint32_t)data;
156 |
157 | /* Set number of data items */
158 | DMA1_Channel3 ->CNDTR = size;
159 |
160 | /* Clear transfer complete flag */
161 | DMA1->IFCR |= DMA_IFCR_CTCIF3;
162 |
163 | /* Clears the GIF, TEIF, HTIF and TCIF flags in the DMA_ISR register */
164 | DMA1->IFCR |= DMA_IFCR_CGIF3;
165 |
166 | /* Clear any USART pending DMA requests */
167 | USART3->CR3 &= ~USART_CR3_DMAR;
168 |
169 | /* Enable DMA mode for reception */
170 | USART3->CR3 |= USART_CR3_DMAR;
171 | /* Finally, I find the error after 2 days of debugging xD */
172 | int temp = USART3->DR;
173 |
174 | /* Enable DMA 1 channel 3 */
175 | DMA1_Channel3->CCR |= DMA_CCR1_EN;
176 |
177 | }
178 | else
179 | {
180 | /* Null pointers, do nothing */
181 | }
182 | }
183 |
184 | /**
185 | * @brief DMA transmit
186 | * @note
187 | * @param data, size
188 | * @retval None
189 | */
190 | static void DMATransmit(const uint8_t * data, uint8_t size)
191 | {
192 | /* Check null pointers */
193 | if(NULL != data)
194 | {
195 | /* disable channel, since this registers must not be written when the channel is enabled */
196 | if(DMA_CCR1_EN == (DMA_CCR1_EN & DMA1_Channel2->CCR))
197 | {
198 | /* DMA 1 channel 2 is enabled, shall be disabled first */
199 | DMA1_Channel2->CCR &= ~DMA_CCR1_EN;
200 |
201 | /* Wait until EN bit is cleared */
202 | while(DMA_CCR1_EN == (DMA_CCR1_EN & DMA1_Channel2->CCR))
203 | {
204 | /* Do nothing until EN bit is cleared */
205 | }
206 | }
207 | else
208 | {
209 | /* Do nothing, channel 2 is not enabled */
210 | }
211 |
212 | /* Set address for memory */
213 | DMA1_Channel2 ->CMAR = (uint32_t)data;
214 |
215 | /* Set number of data items */
216 | DMA1_Channel2 ->CNDTR = size;
217 |
218 | /* Clear transfer complete flag */
219 | DMA1->IFCR |= DMA_IFCR_CTCIF2;
220 |
221 | /* Clears the GIF, TEIF, HTIF and TCIF flags in the DMA_ISR register */
222 | DMA1->IFCR |= DMA_IFCR_CGIF2;
223 |
224 | /* Clear any USART pending DMA requests */
225 | USART3->CR3 &= ~USART_CR3_DMAT;
226 |
227 | /* Enable DMA mode for transmitter */
228 | USART3->CR3 |= USART_CR3_DMAT;
229 |
230 | while(USART_SR_TC != (USART_SR_TC & USART3->SR)){}
231 |
232 | /* */
233 | USART3->SR &= ~USART_SR_TC;
234 | NVIC_ClearPendingIRQ(DMA1_Channel2_IRQn);
235 | /* Enable DMA 1 channel 2 */
236 | DMA1_Channel2->CCR |= DMA_CCR1_EN;
237 | }
238 | else
239 | {
240 | /* Null pointers, do nothing */
241 | }
242 |
243 | }
244 |
245 | /**
246 | * @}
247 | */
248 |
249 | /**
250 | * @defgroup LIN_Slave_exported_functions
251 | * @{
252 | */
253 |
254 | /**
255 | * @brief Configure GPIO
256 | * @note UART3_TX -> PB10, UART3_RX -> PB11 from "Datasheet rev17 page:30"
257 | * GPIO configuration from "Reference manual [Table 24. USARTs]
258 | * UART3 connected to APB1 with 36MHz max clock
259 | * @param None
260 | * @retval None
261 | */
262 | void LIN_Slave_GPIO_Init(void)
263 | {
264 | /* GPIOB clock enable */
265 | RCC ->APB2ENR |= RCC_APB2ENR_IOPBEN;
266 |
267 | /* PB10 TX: Output mode, max speed 2 MHz. */
268 | GPIOB ->CRH &= ~GPIO_CRH_MODE10;
269 | GPIOB ->CRH |= GPIO_CRH_MODE10_1;
270 |
271 | /* PB10 TX: Alternate function output Push-pull */
272 | GPIOB ->CRH &= ~GPIO_CRH_CNF10;
273 | GPIOB ->CRH |= GPIO_CRH_CNF10_1;
274 |
275 | /* PB11 RX: Floating input */
276 | GPIOB ->CRH &= ~GPIO_CRH_CNF11;
277 | GPIOB ->CRH |= GPIO_CRH_CNF11_0;
278 |
279 | /* PB11 RX: Input mode */
280 | GPIOB ->CRH &= ~GPIO_CRH_MODE11;
281 |
282 | }
283 |
284 | /**
285 | * @brief Configure UART5
286 | * @note
287 | * @param None
288 | * @retval None
289 | */
290 | void LIN_Slave_USART3_Init(void)
291 | {
292 | /* Enable USART3 clock */
293 | RCC-> APB1ENR |= RCC_APB1ENR_USART3EN;
294 |
295 | /* select 1 Start bit, 8 Data bits, n Stop bit */
296 | USART3 ->CR1 &= ~USART_CR1_M;
297 |
298 | /* STOP bits, 00: 1 Stop bit */
299 | USART3->CR2 &= ~USART_CR2_STOP;
300 |
301 | /* Select LIN mode */
302 | USART3->CR2 |= USART_CR2_LINEN;
303 |
304 | /* Select LIN break detection length 11 bits */
305 | USART3->CR2 |= USART_CR2_LBDL;
306 |
307 | /* Enable LIN break detection interrupt */
308 | USART3->CR2 |= USART_CR2_LBDIE;
309 |
310 | /* Set baud rate = 9600 Bps */
311 | USART3->BRR = Cal_USART_BRR_Val(9600,8000000);
312 | }
313 |
314 | /**
315 | * @brief Configure DMA for USART TX
316 | * @note USART3_TX -> DMA1_Channel2
317 | * @param None
318 | * @retval None
319 | */
320 | void LIN_Slave_TX_DMA_Init(void)
321 | {
322 | /* Enable clock for DMA1*/
323 | RCC ->AHBENR |= RCC_AHBENR_DMA1EN;
324 |
325 | /* disable channel, since this registers must not be written when the channel is enabled */
326 | if(DMA_CCR1_EN == (DMA_CCR1_EN & DMA1_Channel2->CCR))
327 | {
328 | /* DMA 1 channel 2 is enabled, shall be disabled first */
329 | DMA1_Channel2->CCR &= ~DMA_CCR1_EN;
330 |
331 | /* Wait until EN bit is cleared */
332 | while(DMA_CCR1_EN == (DMA_CCR1_EN & DMA1_Channel2->CCR))
333 | {
334 | /* Do nothing until EN bit is cleared */
335 | }
336 | }
337 | else
338 | {
339 | /* Do nothing, channel 2 is not enabled */
340 | }
341 |
342 | /* Set Peripheral size 8-bits (00)*/
343 | DMA1_Channel2 ->CCR &= ~DMA_CCR1_PSIZE;
344 |
345 | /* Set Memory size 8-bits (00)*/
346 | DMA1_Channel2 ->CCR &= ~DMA_CCR1_MSIZE;
347 |
348 | /* Set Channel priority Very high (11)*/
349 | DMA1_Channel2 ->CCR |= DMA_CCR1_PL;
350 |
351 | /* Disable Peripheral increment mode (0) */
352 | DMA1_Channel2 ->CCR &= ~DMA_CCR1_PINC;
353 |
354 | /* Enable memory increment mode (1)*/
355 | DMA1_Channel2 ->CCR |= DMA_CCR1_MINC;
356 |
357 | /* Disable Circular mode (0)*/
358 | DMA1_Channel2 ->CCR &= ~DMA_CCR1_CIRC;
359 |
360 | /* Diable M2M Mode (0) */
361 | DMA1_Channel2 ->CCR &= ~DMA_CCR1_MEM2MEM;
362 |
363 | /* Data transfer direction Read from memory(memory-to-peripheral) (1)*/
364 | DMA1_Channel2 ->CCR |= DMA_CCR1_DIR;
365 |
366 | /* Enable Transfer complete interrupt */
367 | DMA1_Channel2 ->CCR |= DMA_CCR1_TCIE;
368 |
369 | /* Set address for peripheral */
370 | DMA1_Channel2 ->CPAR = (uint32_t)&USART3->DR;
371 |
372 | __ASM("NOP");
373 | __ASM("NOP");
374 | __ASM("NOP");
375 | __ASM("NOP");
376 |
377 | }
378 |
379 | /**
380 | * @brief Configure DMA for UART RX
381 | * @note USART3_RX -> DMA1_Channel3
382 | * @param None
383 | * @retval None
384 | */
385 | void LIN_Slave_RX_DMA_Init(void)
386 | {
387 | /* Enable clock for DMA1*/
388 | RCC ->AHBENR |= RCC_AHBENR_DMA1EN;
389 |
390 | /* disable channel, since this registers must not be written when the channel is enabled */
391 | if(DMA_CCR1_EN == (DMA_CCR1_EN & DMA1_Channel3->CCR))
392 | {
393 | /* DMA 1 channel 3 is enabled, shall be disabled first */
394 | DMA_ChannelDisable(DMA1_Channel3);
395 |
396 | /* Wait until EN bit is cleared */
397 | while(DMA_CCR1_EN == (DMA_CCR1_EN & DMA1_Channel3->CCR))
398 | {
399 | /* Do nothing until EN bit is cleared */
400 | }
401 | }
402 | else
403 | {
404 | /* Do nothing, channel 3 is not enabled */
405 | }
406 |
407 | /* Set Peripheral size 8-bits (00)*/
408 | DMA1_Channel3 ->CCR &= ~DMA_CCR1_PSIZE;
409 |
410 | /* Set Memory size 8-bits (00)*/
411 | DMA1_Channel3 ->CCR &= ~DMA_CCR1_MSIZE;
412 |
413 | /* Set Channel priority Very high (11)*/
414 | DMA1_Channel3 ->CCR |= DMA_CCR1_PL;
415 |
416 | /* Disable Peripheral increment mode (0) */
417 | DMA1_Channel3 ->CCR &= ~DMA_CCR1_PINC;
418 |
419 | /* Enable memory increment mode (1)*/
420 | DMA1_Channel3 ->CCR |= DMA_CCR1_MINC;
421 |
422 | /* Disable Circular mode (0)*/
423 | DMA1_Channel3 ->CCR &= ~DMA_CCR1_CIRC;
424 |
425 | /* Diable M2M Mode (0) */
426 | DMA1_Channel3 ->CCR &= ~DMA_CCR1_MEM2MEM;
427 |
428 | /* Data transfer direction Read from peripheral (0)*/
429 | DMA1_Channel3 ->CCR &= ~DMA_CCR1_DIR;
430 |
431 | /* Enable Transfer complete interrupt */
432 | DMA1_Channel3 ->CCR |= DMA_CCR1_TCIE;
433 |
434 | /* Set address for peripheral */
435 | DMA1_Channel3 ->CPAR = (uint32_t)&USART3->DR;
436 |
437 | __ASM("NOP");
438 | __ASM("NOP");
439 | __ASM("NOP");
440 | __ASM("NOP");
441 |
442 | }
443 |
444 | /**
445 | * @brief Enable LIN slave node communications
446 | * @note
447 | * @param None
448 | * @retval None
449 | */
450 | void LIN_Slave_Enable(void)
451 | {
452 | /* Enable USART3 */
453 | USART3->CR1 |= USART_CR1_UE;
454 |
455 | /* Enable transmitter */
456 | USART3->CR1 |= USART_CR1_TE;
457 |
458 | /* Enable receiver */
459 | USART3->CR1 |= USART_CR1_RE;
460 | }
461 |
462 | /**
463 | * @brief IRQ callback function
464 | * @note
465 | * @param None
466 | * @retval None
467 | */
468 | void LIN_Slave_RX_DMA_IRQ_Callback(void)
469 | {
470 | //ITM_SendChar_Port(2, 60);
471 | /* Check transfer complete flag */
472 | if((DMA1->ISR & DMA_ISR_TCIF3) == DMA_ISR_TCIF3)
473 | {
474 | /* DMA transfer is complete */
475 |
476 | /* Clear transfer complete flag */
477 | DMA1->IFCR |= DMA_IFCR_CTCIF3;
478 |
479 | /* Clears the GIF, TEIF, HTIF and TCIF flags in the DMA_ISR register */
480 | DMA1->IFCR |= DMA_IFCR_CGIF3;
481 | /* Set transfer complete flag */
482 | RxDMAReceived = 1;
483 |
484 | }
485 |
486 | else
487 | {
488 | /* Do nothing, this interrupt is not handled */
489 |
490 | }
491 |
492 |
493 | }
494 |
495 | /**
496 | * @brief IRQ callback function
497 | * @note
498 | * @param None
499 | * @retval None
500 | */
501 | void LIN_Slave_TX_DMA_IRQ_Callback(void)
502 | {
503 | //ITM_SendChar_Port(2, 55);
504 | /* Check transfer complete flag */
505 | if((DMA1->ISR & DMA_ISR_TCIF2) == DMA_ISR_TCIF2)
506 | {
507 | /* DMA transfer is complete */
508 |
509 | /* Clear transfer complete flag */
510 | DMA1->IFCR |= DMA_IFCR_CTCIF2;
511 |
512 | /* Clears the GIF, TEIF, HTIF and TCIF flags in the DMA_ISR register */
513 | DMA1->IFCR |= DMA_IFCR_CGIF2;
514 | }
515 |
516 | else
517 | {
518 | /* Do nothing, this interrupt is not handled */
519 | }
520 |
521 | }
522 |
523 | /**
524 | * @brief IRQ callback function
525 | * @note
526 | * @param None
527 | * @retval None
528 | */
529 | void LIN_Slave_USART3_IRQ_Callback(void)
530 | {
531 | //ITM_SendChar_Port(2, 50);
532 | /* Check if LIN break detected */
533 | if((USART3->SR & USART_SR_LBD) == USART_SR_LBD)
534 | {
535 | /* Clear LIN break detection flag */
536 | USART3->SR &= ~(USART_SR_LBD);
537 |
538 | /* Clear read data register not empty */
539 | USART3->SR &= ~(USART_SR_RXNE);
540 |
541 | /* Set LIN break detected */
542 | currentState = LINS_BREAK_RECEIVED;
543 | }
544 | else
545 | {
546 | /* No new LIN Frame received */
547 | }
548 |
549 | }
550 |
551 | /**
552 | * @brief LIN slave node task
553 | * @note This function shall be called periodically.
554 | * @param None
555 | * @retval None
556 | */
557 | void LIN_Slave_Process(void)
558 | {
559 | /* Check current LIN slave state */
560 | switch (currentState)
561 | {
562 | case LINS_IDLE:
563 | /* Wait for LIN break */
564 | break;
565 |
566 | case LINS_BREAK_RECEIVED:
567 | /* Start DMA for LIN header reception */
568 | //DMAReceive(linHeader, LIN_HEADER_LENGTH);
569 |
570 | /* Wait for LIN header */
571 | currentState = LINS_WAIT_FOR_HEADER;
572 | break;
573 |
574 | case LINS_WAIT_FOR_HEADER:
575 | /* Wait for LIN header */
576 | if(1 == RxDMAReceived)
577 | {
578 | /* New DMA data was received, reset DMA flag */
579 | RxDMAReceived = 0;
580 |
581 | /* Go to next state */
582 | currentState = LINS_HEADER_RECEIVED;
583 | }
584 | else
585 | {
586 | /* Do nothing */
587 | }
588 | break;
589 |
590 | case LINS_HEADER_RECEIVED:
591 | /* Check sync field */
592 | if(0x55 == linHeader[0])
593 | {
594 | /* Sync is OK, Check PID */
595 | /* We expecting only one frame with PID = 0xEC */
596 | if(0xEC == linHeader[1])
597 | {
598 | /* PID is OK, go to TX data */
599 | currentState = LINS_TX_DATA;
600 | }
601 | else
602 | {
603 | /* PID is unknown, go to idle */
604 | currentState = LINS_IDLE;
605 | }
606 | }
607 | else
608 | {
609 | /* Sync field not OK, go to idle */
610 | currentErrorStatus = LINS_SYNC_ERROR;
611 | currentState = LINS_IDLE;
612 | }
613 | break;
614 |
615 | case LINS_TX_DATA:
616 | /* Start sending the Response */
617 | DMATransmit(linData, LIN_DATA_LENGTH );
618 | currentState = LINS_IDLE;
619 |
620 | break;
621 |
622 | case LINS_RX_DATA:
623 | /* Start DMA for LIN header reception */
624 | DMAReceive(linData, LIN_DATA_LENGTH);
625 |
626 | /* Wait for LIN Data reception */
627 | currentState = LINS_WAIT_FOR_RX_DATA;
628 | break;
629 |
630 | case LINS_WAIT_FOR_RX_DATA:
631 | /* Wait for LIN data */
632 | if(1 == RxDMAReceived)
633 | {
634 | /* New DMA data was received, reset DMA flag */
635 | RxDMAReceived = 0;
636 |
637 | /* Go to next state */
638 | currentState = LINS_RX_DATA_RECEIVED;
639 | }
640 | else
641 | {
642 | /* Do nothing */
643 | }
644 | break;
645 |
646 | case LINS_RX_DATA_RECEIVED:
647 | /* Check the received checksum, shall be calculated based
648 | * on the received data */
649 | if((0xCA == linData[2]) || (0xEA == linData[2]))
650 | {
651 | /* Checksum is OK, check required command for the green LED */
652 | if(0x0A == linData[0])
653 | {
654 | /* Turn off green LED */
655 |
656 | }
657 | else if(0x1A == linData[0])
658 | {
659 | /* Turn on green LED */
660 |
661 | }
662 | else
663 | {
664 | /* Do nothing */
665 | }
666 |
667 | /* Command for the red LED */
668 | if(0x0B == linData[1])
669 | {
670 | /* Turn off red LED */
671 |
672 | }
673 | else if(0x1B == linData[1])
674 | {
675 | /* Turn on red LED */
676 |
677 | }
678 | else
679 | {
680 | /* Do nothing */
681 | }
682 |
683 | /* Reset error state and go to idle */
684 | currentState = LINS_IDLE;
685 | currentErrorStatus = LINS_NO_ERROR;
686 | }
687 | else
688 | {
689 | /* Checksum error, go to idle */
690 | currentState = LINS_IDLE;
691 | currentErrorStatus = LINS_CHECKSUM_INVALID_ERROR;
692 | }
693 | break;
694 |
695 | default:
696 | break;
697 |
698 | }
699 |
700 | }
701 | void LIN_Send_Break_Field(void)
702 | {
703 | /* Send break character */
704 | USART3->CR1 |= USART_CR1_SBK;
705 | }
706 | void LIN_Master_Process(uint8_t data0, uint8_t data1, uint8_t CheckSum)
707 | {
708 | /* Set Sync field */
709 | linHeader_TX[0]=0x55;
710 |
711 | /* Set PID = 0xEC as Master PID for Transmission */
712 | linHeader_TX[1]=0xEC;
713 |
714 | /* Set Response to transmit */
715 | linData[0] = data0;
716 | linData[1] = data1;
717 | linData[2] = CheckSum;
718 |
719 | /* Rest Header Frame */
720 | linHeader[0] = 0;
721 | linHeader[1] = 0;
722 |
723 | LIN_Send_Break_Field();
724 |
725 | /* Wait for Break Field to be sent */
726 | while(currentState != LINS_BREAK_RECEIVED){}
727 |
728 | DMAReceive(linHeader, LIN_HEADER_LENGTH);
729 | DMATransmit(linHeader_TX, LIN_HEADER_LENGTH);
730 |
731 | do{
732 | LIN_Slave_Process();
733 | }while(currentState != LINS_IDLE);
734 |
735 |
736 | }
737 |
738 |
739 |
740 |
--------------------------------------------------------------------------------
/src/src/SysTick.c:
--------------------------------------------------------------------------------
1 | /*******************************************************************************
2 | * @file SysTick.c
3 | * @author Rashad Shubita
4 | * @email shubitarashad@gmail.com
5 | * @date 15.01.2019
6 | *
7 | * @brief SysTick configuration source file
8 | * @note
9 | *
10 | @verbatim
11 | Copyright (C) 2019, Rashad Shubita
12 |
13 | This program is free software: you can redistribute it and/or modify it under
14 | the terms of the GNU General Public License as published by the Free Software
15 | Foundation, either version 3 of the License, or any later version.
16 |
17 | This program is distributed in the hope that it will be useful, but WITHOUT
18 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
19 | FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
20 |
21 | You should have received a copy of the GNU General Public License along with
22 | this program. If not, see .
23 | @endverbatim
24 | *******************************************************************************/
25 |
26 | /* Includes */
27 | #include "SysTick.h"
28 |
29 | volatile uint32_t SysTickCounter = 0;
30 |
31 | /**
32 | * @brief Return current SysTick counter
33 | * @note
34 | * @param None
35 | * @retval SysTickCounter
36 | */
37 | uint32_t SysTick_GetCurrentTick(void)
38 | {
39 | return(SysTickCounter);
40 | }
41 |
42 | /**
43 | * @brief Delay function based on SysTick
44 | * @note SysTick will be update with IRQ callback
45 | * @param Waiting time in milliseconds
46 | * @retval None
47 | */
48 | void SysTick_Delay(uint32_t wait_time_ms)
49 | {
50 | /* Store start tick */
51 | uint32_t startTick = SysTickCounter;
52 |
53 | /* Loop until timeout */
54 | while((SysTickCounter - startTick) < wait_time_ms)
55 | {
56 |
57 | }
58 | }
59 |
60 | /**
61 | * @brief SysTick initial configuration
62 | * @note
63 | * @param None
64 | * @retval None
65 | */
66 | void SysTick_Init(void)
67 | {
68 | uint32_t returnCode;
69 |
70 | /* Update clock configuration */
71 | SystemCoreClockUpdate();
72 |
73 | /* Check clock configuration */
74 | if(SystemCoreClock != (uint32_t) 8000000)
75 | {
76 | /* Clock configuration is not OK */
77 | while(1)
78 | {
79 |
80 | }
81 | }
82 | else
83 | {
84 | /* Clock configuration is OK */
85 | }
86 |
87 | /* Configure SysTick to generate an interrupt every millisecond */
88 | returnCode = SysTick_Config(SystemCoreClock / 1000);
89 |
90 | /* Check return code for errors */
91 | if (returnCode != 0)
92 | {
93 | /* SysTick configuration failed */
94 | while(1)
95 | {
96 |
97 | }
98 | }
99 | else
100 | {
101 | /* Do nothing, SysTick configuration OK */
102 | }
103 | NVIC_SetPriority(SysTick_IRQn, 0);
104 | }
105 |
106 |
--------------------------------------------------------------------------------
/src/src/dma.c:
--------------------------------------------------------------------------------
1 | /*******************************************************************************
2 | * @file dma.c
3 | * @author Rashad Shubita
4 | * @email shubitarashad@gmail.com
5 | * @date 15.02.2019
6 | *
7 | * @brief DMA configuration source file
8 | * @note
9 | *
10 | @verbatim
11 | Copyright (C) 2019, Rashad Shubita
12 |
13 | This program is free software: you can redistribute it and/or modify it under
14 | the terms of the GNU General Public License as published by the Free Software
15 | Foundation, either version 3 of the License, or any later version.
16 |
17 | This program is distributed in the hope that it will be useful, but WITHOUT
18 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
19 | FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
20 |
21 | You should have received a copy of the GNU General Public License along with
22 | this program. If not, see .
23 | @endverbatim
24 | *******************************************************************************/
25 |
26 |
27 | #include "dma.h"
28 |
29 | /**
30 | * @brief DMA1 Channel3 initialization function
31 | * @note Used for data transfer between two memory buffers
32 | * @param None
33 | * @retval None
34 | */
35 | void DMA1_Channel3_Init(void)
36 | {
37 | /* Enable clock for DMA1*/
38 | RCC ->AHBENR |= RCC_AHBENR_DMA1EN;
39 |
40 | /* disable channel, since this registers must not be written when the channel is enabled */
41 | DMA_ChannelDisable(DMA1_Channel3);
42 |
43 | /* Set Peripheral size 32-bits (10)*/
44 | DMA1_Channel3 ->CCR &= ~DMA_CCR1_PSIZE;
45 | DMA1_Channel3 ->CCR |= DMA_CCR1_PSIZE_1;
46 |
47 | /* Set Memory size 32-bits (10)*/
48 | DMA1_Channel3 ->CCR &= ~DMA_CCR1_MSIZE;
49 | DMA1_Channel3 ->CCR |= DMA_CCR1_MSIZE_1;
50 |
51 | /* Set Channel priority Very high (11)*/
52 | DMA1_Channel3 ->CCR |= DMA_CCR1_PL;
53 |
54 | /* Enable Peripheral increment mode (1) */
55 | DMA1_Channel3 ->CCR |= DMA_CCR1_PINC;
56 |
57 | /* Enable memory increment mode (1)*/
58 | DMA1_Channel3 ->CCR |= DMA_CCR1_MINC;
59 |
60 | /* Enable M2M Mode (1) */
61 | DMA1_Channel3 ->CCR |= DMA_CCR1_MEM2MEM;
62 |
63 | /* Data transfer direction Read from memory (1)*/
64 | DMA1_Channel3 ->CCR |= DMA_CCR1_DIR;
65 |
66 | /* Enable Transfer complete interrupt */
67 | DMA1_Channel3 ->CCR |= DMA_CCR1_TCIE;
68 |
69 | __ASM("NOP");
70 | __ASM("NOP");
71 | __ASM("NOP");
72 | __ASM("NOP");
73 | }
74 |
75 |
76 | /*
77 | * @brief DMA Channel set addresses function
78 | * @note Sets the addresses of the memory and peripheral ports,
79 | * and number of data items to be transfered in a specific channel
80 | * @param DMA_Channel, Peripheral_Adr, Memory_Adr, size
81 | * @retval None
82 | */
83 | void DMA_Channel_Set_Addresses(DMA_Channel_TypeDef *DMA_Channel, const uint32_t * Peripheral_Adr,
84 | uint32_t * Memory_Adr, const uint32_t size)
85 | {
86 | /* Set address for peripheral */
87 | DMA_Channel ->CPAR = (uint32_t)Peripheral_Adr;
88 |
89 | /* Set address for memory */
90 | DMA_Channel ->CMAR = (uint32_t)Memory_Adr;
91 |
92 | /* Set no. of data to transfer */
93 | DMA_Channel ->CNDTR = size;
94 | }
95 |
96 | /**
97 | * @brief Enable DMA
98 | * @note
99 | * @param DMAx_Channely where: x= 1 or 2 , y= 1 ..7 for DMA1 and 1 ..5 for DMA2
100 | * @retval None
101 | */
102 | void DMA_ChannelEnable(DMA_Channel_TypeDef *DMA_Channel,uint8_t DMA_Num, uint8_t Ch_Num)
103 | {
104 | /*Clears the GIF, TEIF, HTIF and TCIF flags in the DMA_ISR register */
105 | if(DMA_Num == 1)DMA1->IFCR |= (1 << (4*(Ch_Num-1)) );
106 | else DMA2->IFCR |= (1 << (4*(Ch_Num-1)) );
107 | /* Channel enable */
108 | DMA_Channel->CCR |= DMA_CCR1_EN;
109 | }
110 |
111 | /**
112 | * @brief Disable DMA
113 | * @note
114 | * @param DMAx_Channely where: x= 1 or 2 , y= 1 ..7 for DMA1 and 1 ..5 for DMA2
115 | * @retval None
116 | */
117 | void DMA_ChannelDisable(DMA_Channel_TypeDef *DMA_Channel){
118 | DMA_Channel->CCR &= ~DMA_CCR1_EN;
119 | }
120 |
--------------------------------------------------------------------------------
/src/src/exti.c:
--------------------------------------------------------------------------------
1 | /*******************************************************************************
2 | * @file exti.c
3 | * @author Rashad Shubita
4 | * @email shubitarashad@gmail.com
5 | * @date 08.02.2019
6 | *
7 | * @brief EXTI configuration source file
8 | * @note
9 | *
10 | @verbatim
11 | Copyright (C) 2019, Rashad Shubita
12 |
13 | This program is free software: you can redistribute it and/or modify it under
14 | the terms of the GNU General Public License as published by the Free Software
15 | Foundation, either version 3 of the License, or any later version.
16 |
17 | This program is distributed in the hope that it will be useful, but WITHOUT
18 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
19 | FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
20 |
21 | You should have received a copy of the GNU General Public License along with
22 | this program. If not, see .
23 | @endverbatim
24 | *******************************************************************************/
25 |
26 |
27 | #include "exti.h"
28 | #include "stm32f10x.h"
29 |
30 | void EXTI_Init_PB(void)
31 | {
32 |
33 | /* --------------- EXTI initialization and connect the External line to the GPIO --------------- */
34 | /* Enable AFIO_EXTICR clock */
35 | RCC-> APB2ENR |= RCC_APB2ENR_AFIOEN;
36 |
37 | /* MAP the PA0 to EXTI0 */
38 | AFIO-> EXTICR[0] |= AFIO_EXTICR1_EXTI0_PA ;
39 |
40 | /* Rising trigger selection ( 1 = trigger enable) */
41 | EXTI-> RTSR |= EXTI_RTSR_TR0 ;
42 |
43 | /* Falling trigger selection ( 0 = trigger disable) */
44 | EXTI-> FTSR &= ~EXTI_FTSR_TR0 ;
45 |
46 | /* Interrupt Mask Register ( 1 = not masked [enable], 0=masked) */
47 | EXTI-> IMR |= EXTI_IMR_MR0 ;
48 |
49 | /* Enable event line */
50 | EXTI -> EMR |= EXTI_EMR_MR0;
51 |
52 | /* Clear pending if any */
53 | EXTI->PR |= EXTI_PR_PR0;
54 |
55 | }
56 |
--------------------------------------------------------------------------------
/src/src/gpio.c:
--------------------------------------------------------------------------------
1 | /*******************************************************************************
2 | * @file gpio.c
3 | * @author Rashad Shubita
4 | * @email shubitarashad@gmail.com
5 | * @date 15.01.2019
6 | *
7 | * @brief Some examples on how to use STM32 GPIOs
8 | * @note
9 | *
10 | @verbatim
11 | Copyright (C) 2019, Rashad Shubita
12 |
13 | This program is free software: you can redistribute it and/or modify it under
14 | the terms of the GNU General Public License as published by the Free Software
15 | Foundation, either version 3 of the License, or any later version.
16 |
17 | This program is distributed in the hope that it will be useful, but WITHOUT
18 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
19 | FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
20 |
21 | You should have received a copy of the GNU General Public License along with
22 | this program. If not, see .
23 | @endverbatim
24 | *******************************************************************************/
25 |
26 | /* Includes */
27 | #include "gpio.h"
28 |
29 | /**
30 | * @brief LED initialization function
31 | * @note Yellow_LED -> PC13
32 | * @param None
33 | * @retval None
34 | */
35 | void GPIO_OnBoard_Init_LED(void)
36 | {
37 | /* Enable clock for GPIOC */
38 | RCC ->APB2ENR |= RCC_APB2ENR_IOPCEN;
39 | /* Configure PC.13 in output mode, max speed 2 MHz. */
40 | GPIOC ->CRH &= ~GPIO_CRH_MODE13;
41 | GPIOC ->CRH |= GPIO_CRH_MODE13_1;
42 | /* Configure PC.13 as general purpose output push-pull */
43 | GPIOC ->CRH &= ~GPIO_CRH_CNF13;
44 | /* Led OFF */
45 | GPIOC ->ODR |= GPIO_ODR_ODR13;
46 |
47 | }
48 |
49 | /**
50 | * @brief Push button initialization function
51 | * @note Push button connected to PA0
52 | * @param None
53 | * @retval None
54 | */
55 | void GPIO_Init_PB(void)
56 | {
57 | RCC -> APB2ENR |= RCC_APB2ENR_IOPAEN; //Enable Clock for GPIOA
58 | GPIOA -> CRL &= ~GPIO_CRL_MODE0; //Input mode (reset state)
59 | GPIOA -> CRL &= ~GPIO_CRL_CNF0_0; //Input with pull-up / pull-down
60 | GPIOA -> CRL |= GPIO_CRL_CNF0_1; //
61 | GPIOA ->ODR &= ~GPIO_ODR_ODR0; //active pull-down resistor
62 | }
63 |
64 |
65 |
66 | /**
67 | * @brief USART2 GPIO initialization function
68 | * @note PB10 -> USART1_TX, PB11 -> USART1_RX
69 | * @param None
70 | * @retval None
71 | */
72 | void GPIO_USART2_Init(void)
73 | {
74 | /* GPIOA clock enable */
75 | RCC ->APB2ENR |= RCC_APB2ENR_IOPBEN;
76 |
77 | /* PB10 TX: Output mode, max speed 2 MHz. */
78 | GPIOB ->CRH &= ~GPIO_CRH_MODE10;
79 | GPIOB ->CRH |= GPIO_CRH_MODE10_1;
80 |
81 | /* PB10 TX: Alternate function output Push-pull */
82 | GPIOB ->CRH &= ~GPIO_CRH_CNF10;
83 | GPIOB ->CRH |= GPIO_CRH_CNF10_1;
84 |
85 | /* PB11 RX: Floating input */
86 | GPIOB ->CRH &= ~GPIO_CRH_CNF11;
87 | GPIOB ->CRH |= GPIO_CRH_CNF11_0;
88 |
89 | /* PB11 RX: Input mode */
90 | GPIOB ->CRH &= ~GPIO_CRH_MODE11;
91 |
92 | }
93 |
94 |
--------------------------------------------------------------------------------
/src/src/itm.c:
--------------------------------------------------------------------------------
1 | /*******************************************************************************
2 | * @file itm.c
3 | * @author Rashad Shubita
4 | * @email shubitarashad@gmail.com
5 | * @date 20.01.2019
6 | *
7 | * @brief Basic functionality of ITM
8 | * @note
9 | *
10 | @verbatim
11 | Copyright (C) 2019, Rashad Shubita
12 |
13 | This program is free software: you can redistribute it and/or modify it under
14 | the terms of the GNU General Public License as published by the Free Software
15 | Foundation, either version 3 of the License, or any later version.
16 |
17 | This program is distributed in the hope that it will be useful, but WITHOUT
18 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
19 | FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
20 |
21 | You should have received a copy of the GNU General Public License along with
22 | this program. If not, see .
23 | @endverbatim
24 | *******************************************************************************/
25 |
26 |
27 | /* Includes */
28 | #include
29 | #include "itm.h"
30 |
31 | /**
32 | * @addtogroup stm32_examples
33 | * @{
34 | */
35 |
36 | /**
37 | * @defgroup itm
38 | * @brief
39 | * @{
40 | */
41 |
42 | /**
43 | * @defgroup itm_private_typedefs
44 | * @{
45 | */
46 |
47 | /**
48 | * @}
49 | */
50 |
51 | /**
52 | * @defgroup itm_private_defines
53 | * @{
54 | */
55 |
56 | /**
57 | * @}
58 | */
59 |
60 | /**
61 | * @defgroup itm_private_macros
62 | * @{
63 | */
64 |
65 | /**
66 | * @}
67 | */
68 |
69 | /**
70 | * @defgroup itm_private_constants
71 | * @{
72 | */
73 |
74 | /**
75 | * @}
76 | */
77 |
78 | /**
79 | * @defgroup itm_private_variables
80 | * @{
81 | */
82 |
83 | /**
84 | * @}
85 | */
86 |
87 | /**
88 | * @defgroup itm_private_function_prototypes
89 | * @{
90 | */
91 |
92 | /**
93 | * @}
94 | */
95 |
96 | /**
97 | * @defgroup itm_private_functions
98 | * @{
99 | */
100 |
101 | /**
102 | * @}
103 | */
104 |
105 | /**
106 | * @defgroup itm_exported_functions
107 | * @{
108 | */
109 |
110 | /**
111 | * @brief ITM_Printf
112 | * @note
113 | * @param str, length
114 | * @retval None
115 | */
116 | void ITM_Printf(char *str, int length)
117 | {
118 | /* Check null pointers */
119 | if(NULL != str)
120 | {
121 | /* Start transmission to ITM port 0 */
122 | for(int idx = 0; idx < (length - 1); idx++)
123 | {
124 | /* Send a char */
125 | ITM_SendChar(*str);
126 |
127 | /* Increment to the next char */
128 | str++;
129 | }
130 | }
131 | }
132 |
133 | /**
134 | * @brief SendChar
135 | * @note
136 | * @param port, ch
137 | * @retval
138 | */
139 | void ITM_SendChar_Port(uint8_t port, uint8_t ch)
140 | {
141 | if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */
142 | (ITM->TER & (1UL << port) ) ) /* ITM Port #0 enabled */
143 | {
144 | while (ITM->PORT[port].u32 == 0);
145 | ITM->PORT[port].u8 = ch;
146 | }
147 | }
148 |
149 | /**
150 | * @brief ITM_Printf_Port
151 | * @note
152 | * @param port, str, length
153 | * @retval None
154 | */
155 | void ITM_Printf_Port(uint8_t port, char *str, int length)
156 | {
157 | /* Check null pointers */
158 | if(NULL != str)
159 | {
160 | /* Start transmission to ITM port 0 */
161 | for(int idx = 0; idx < (length - 1); idx++)
162 | {
163 | /* Send a char */
164 | ITM_SendChar_Port(port, *str);
165 |
166 | /* Increment to the next char */
167 | str++;
168 | }
169 | }
170 | }
171 |
172 | /**
173 | * @}
174 | */
175 | /**
176 | * @}
177 | */
178 | /**
179 | * @}
180 | */
181 |
--------------------------------------------------------------------------------
/src/src/memcpy.c:
--------------------------------------------------------------------------------
1 | /*******************************************************************************
2 | * @file memcpy.c
3 | * @author Rashad Shubita
4 | * @email shubitarashad@gmail.com
5 | * @date 15.02.2019
6 | *
7 | * @brief Copy data between two memory buffers
8 | * @note
9 | *
10 | @verbatim
11 | Copyright (C) 2019, Rashad Shubita
12 |
13 | This program is free software: you can redistribute it and/or modify it under
14 | the terms of the GNU General Public License as published by the Free Software
15 | Foundation, either version 3 of the License, or any later version.
16 |
17 | This program is distributed in the hope that it will be useful, but WITHOUT
18 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
19 | FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
20 |
21 | You should have received a copy of the GNU General Public License along with
22 | this program. If not, see .
23 | @endverbatim
24 | *******************************************************************************/
25 |
26 | /* Includes */
27 | #include
28 | #include "memcpy.h"
29 |
30 | /**
31 | * @addtogroup stm32_examples
32 | * @{
33 | */
34 |
35 | /**
36 | * @defgroup memcpy
37 | * @brief
38 | * @{
39 | */
40 |
41 | /**
42 | * @defgroup memcpy_private_typedefs
43 | * @{
44 | */
45 |
46 | /**
47 | * @}
48 | */
49 |
50 | /**
51 | * @defgroup memcpy_private_defines
52 | * @{
53 | */
54 | // use #define USE_INDEX_BY_INDEX or USE_POINTER
55 | #define USE_POINTER
56 |
57 | /**
58 | * @}
59 | */
60 |
61 | /**
62 | * @defgroup memcpy_private_macros
63 | * @{
64 | */
65 |
66 | /**
67 | * @}
68 | */
69 |
70 | /**
71 | * @defgroup memcpy_private_constants
72 | * @{
73 | */
74 |
75 | /**
76 | * @}
77 | */
78 |
79 | /**
80 | * @defgroup memcpy_private_variables
81 | * @{
82 | */
83 |
84 | /**
85 | * @}
86 | */
87 |
88 | /**
89 | * @defgroup memcpy_private_function_prototypes
90 | * @{
91 | */
92 |
93 | /**
94 | * @}
95 | */
96 |
97 | /**
98 | * @defgroup memcpy_private_functions
99 | * @{
100 | */
101 |
102 | /**
103 | * @}
104 | */
105 |
106 | /**
107 | * @defgroup memcpy_exported_functions
108 | * @{
109 | */
110 |
111 | /**
112 | * @brief Copy data between two memory buffers
113 | * @note
114 | * @param src, dst, size
115 | * @retval RETURN_STATUS_OK, RETURN_STATUS_NOT_OK
116 | */
117 | ReturnStatus_Type memcpy32(const uint32_t * src,
118 | uint32_t * dst, const uint32_t size)
119 | {
120 | /* Return status */
121 | ReturnStatus_Type returnStatus = RETURN_STATUS_NOT_OK;
122 |
123 | /* Check for null pointer */
124 | if((NULL != src) && (NULL != dst))
125 | {
126 | /* Pointers are OK, start copying */
127 | #ifdef USE_INDEX_BY_INDEX
128 | for (uint32_t idx = 0; idx < size; idx++)
129 | {
130 | dst[idx] = src[idx];
131 | }
132 | #endif
133 |
134 | #ifdef USE_POINTER
135 | /* Get array length */
136 | uint32_t arrayLength = size;
137 |
138 | while (arrayLength > 0)
139 | {
140 | /* Copy one word then increment the pointers */
141 | *dst++ = *src++;
142 |
143 | /* Decrement array length */
144 | arrayLength--;
145 | }
146 | #endif
147 | /* Return OK */
148 | returnStatus = RETURN_STATUS_OK;
149 | }
150 | else
151 | {
152 | /* Null pointer, Return status is not OK */
153 | returnStatus = RETURN_STATUS_NOT_OK;
154 | }
155 |
156 | /* Return status */
157 | return returnStatus;
158 | }
159 |
160 |
161 | /**
162 | * @}
163 | */
164 | /**
165 | * @}
166 | */
167 | /**
168 | * @}
169 | */
170 |
--------------------------------------------------------------------------------
/src/src/nvic.c:
--------------------------------------------------------------------------------
1 | /*******************************************************************************
2 | * @file nvic.c
3 | * @author Rashad Shubita
4 | * @email shubitarashad@gmail.com
5 | * @date 08.02.2019
6 | *
7 | * @brief NVIC configuration source file
8 | * @note
9 | *
10 | @verbatim
11 | Copyright (C) 2019, Rashad Shubita
12 |
13 | This program is free software: you can redistribute it and/or modify it under
14 | the terms of the GNU General Public License as published by the Free Software
15 | Foundation, either version 3 of the License, or any later version.
16 |
17 | This program is distributed in the hope that it will be useful, but WITHOUT
18 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
19 | FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
20 |
21 | You should have received a copy of the GNU General Public License along with
22 | this program. If not, see .
23 | @endverbatim
24 | *******************************************************************************/
25 |
26 |
27 | /* Includes */
28 | #include "nvic.h"
29 |
30 |
31 | /**
32 | * @brief NVIC IRQs initialization function
33 | * @note
34 | * @param None
35 | * @retval None
36 | */
37 | void NVIC_Init(void)
38 | {
39 | /* Set priority group to 3
40 | * bits[3:0] are the sub-priority,
41 | * bits[7:4] are the pre-empt priority */
42 |
43 | NVIC_SetPriorityGrouping(3);
44 |
45 | /* Set priority levels */
46 | //NVIC_SetPriority(EXTI0_IRQn, 1);
47 | //NVIC_SetPriority(DMA1_Channel3_IRQn, 1);
48 | //NVIC_SetPriority(DMA1_Channel4_IRQn, 1);
49 | //NVIC_SetPriority(DMA1_Channel5_IRQn, 1);
50 | NVIC_SetPriority(DMA1_Channel2_IRQn, 1);
51 | NVIC_SetPriority(DMA1_Channel3_IRQn, 1);
52 | //NVIC_SetPriority(USART1_IRQn,1);
53 | NVIC_SetPriority(USART3_IRQn,1);
54 |
55 | /* Enable interrupts at NVIC */
56 | //NVIC_EnableIRQ(EXTI0_IRQn);
57 | //NVIC_EnableIRQ(DMA1_Channel3_IRQn);
58 | //NVIC_EnableIRQ(DMA1_Channel4_IRQn);
59 | //NVIC_EnableIRQ(DMA1_Channel5_IRQn);
60 | NVIC_EnableIRQ(DMA1_Channel2_IRQn);
61 | NVIC_EnableIRQ(DMA1_Channel3_IRQn);
62 | //NVIC_EnableIRQ(USART1_IRQn);
63 | NVIC_EnableIRQ(USART3_IRQn);
64 |
65 | }
66 |
--------------------------------------------------------------------------------
/src/src/usart.c:
--------------------------------------------------------------------------------
1 | /*******************************************************************************
2 | * @file usart.c
3 | * @author Rashad Shubita
4 | * @email shubitarashad@gmail.com
5 | * @date 15.01.2019
6 | *
7 | * @brief USART configuration source file
8 | * @note
9 | *
10 | @verbatim
11 | Copyright (C) 2019, Rashad Shubita
12 |
13 | This program is free software: you can redistribute it and/or modify it under
14 | the terms of the GNU General Public License as published by the Free Software
15 | Foundation, either version 3 of the License, or any later version.
16 |
17 | This program is distributed in the hope that it will be useful, but WITHOUT
18 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
19 | FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
20 |
21 | You should have received a copy of the GNU General Public License along with
22 | this program. If not, see .
23 | @endverbatim
24 | *******************************************************************************/
25 |
26 | #include "usart.h"
27 | #include
28 |
29 | /* Private typedef -----------------------------------------------------------*/
30 | /**
31 | * @brief USART1 states definition
32 | */
33 | typedef enum
34 | {
35 | USART1_IDLE,
36 | USART1_WAIT_FOR_RESPONCE,
37 | USART1_ASK_FOR_NAME,
38 | USART1_WAIT_FOR_NAME,
39 | USART1_WAIT_FOR_COMMAND,
40 | } USART1_StateType;
41 |
42 | /**
43 | * @brief USART1 error status definition
44 | */
45 | typedef enum
46 | {
47 | USART1_NO_ERROR,
48 | USART1_PARITY_ERROR
49 | } USART1_ErrorStatusType;
50 |
51 | /**
52 | * @brief Return type
53 | */
54 | typedef enum
55 | {
56 | STR_NOT_EQUAL,
57 | STR_EQUAL
58 | } strCmpReturnType;
59 |
60 | /* Private define ------------------------------------------------------------*/
61 | /**
62 | * @brief Maximum USART reception buffer length
63 | */
64 | #define MAX_BUFFER_LENGTH ((uint32_t) 200u)
65 |
66 | /* Private variables constants -----------------------------------------------*/
67 | /**
68 | * @brief USART1 messages to be transmitted
69 | */
70 | static const char hello_world[] = "Hello World!";
71 | static const char ask_for_name[] = "What is your name?";
72 | static const char hi[] = "Hi,";
73 | static const char ask_for_command[] = "Please, send command";
74 | static const char ask_for_command_ex[] = "Action[turn_on / turn_off] Led[green_led / red_led]";
75 | static const char turn_on_green_led[] = "turn_on green_led";
76 | static const char turn_on_red_led[] = "turn_on red_led";
77 | static const char turn_off_green_led[] = "turn_off green_led";
78 | static const char turn_off_red_led[] = "turn_off red_led";
79 | static const char done[] = "Done";
80 | static const char wrong_command[] = "Wrong Command";
81 | static const char parity_error[] = "Parity Error";
82 |
83 | /* Private variables ---------------------------------------------------------*/
84 | /**
85 | * @brief USART1 current state
86 | */
87 | static USART1_StateType currentState = USART1_IDLE;
88 |
89 | /**
90 | * @brief USART1 current error status
91 | */
92 | static USART1_ErrorStatusType currentErrorStatus = USART1_NO_ERROR;
93 |
94 |
95 | /**
96 | * @brief USART1 RX message buffer
97 | */
98 | static char RxBuffer[MAX_BUFFER_LENGTH ];
99 | char RxDMABuffer[MAX_BUFFER_LENGTH];
100 |
101 | /**
102 | * @brief USART1 message length
103 | */
104 | static uint8_t RxMessageLength = 0;
105 |
106 |
107 | /**
108 | * @brief Compare two strings
109 | * @note take the size of the predefined string
110 | * @param str1, str2, size
111 | * @retval strCmpReturnType
112 | */
113 | static strCmpReturnType strCmp(const char * str1, const char * str2,
114 | const uint8_t size)
115 | {
116 | /* Compare status */
117 | strCmpReturnType cmpStatus = STR_EQUAL;
118 |
119 | /* Check null pointers */
120 | if((NULL != str1) && (NULL != str2))
121 | {
122 | /* Start comparing */
123 | for (int idx = 0; idx < size; idx++)
124 | {
125 | /* When not equal set the return status */
126 | if(str1[idx] != str2[idx])
127 | {
128 | cmpStatus = STR_NOT_EQUAL;
129 | }
130 | else
131 | {
132 | /* Do nothing */
133 | }
134 | }
135 | }
136 | else
137 | {
138 | /* Null pointers, do nothing */
139 | }
140 | return cmpStatus;
141 | }
142 |
143 | /**
144 | * @brief IRQ callback function
145 | * @note
146 | * @param None
147 | * @retval None
148 | */
149 | void USART1_IRQ_Callback(void)
150 | {
151 | /* Check if parity error detected */
152 | if((USART1->SR & USART_SR_PE) == USART_SR_PE)
153 | {
154 | while((USART1->SR & USART_SR_RXNE) != USART_SR_RXNE)
155 | {
156 | /* Wait for RXNE flag to be set */
157 | }
158 |
159 | /* Read data register to clear parity error */
160 | (void)USART1->DR;
161 |
162 | /* Set parity error */
163 | currentErrorStatus = USART1_PARITY_ERROR;
164 |
165 | /* Disable DMA Channel for RX */
166 | DMA_ChannelDisable(DMA1_Channel5);
167 | }
168 | else
169 | {
170 | /* No parity error */
171 | }
172 |
173 | /* Check if idle line detected */
174 | if((USART1->SR & USART_SR_IDLE) == USART_SR_IDLE)
175 | {
176 | uint32_t temp = USART1->SR & USART_SR_IDLE;
177 | temp = USART1->DR;
178 |
179 | /* Disable DMA Channel for RX */
180 | DMA_ChannelDisable(DMA1_Channel5);
181 | /*force DMA1_Channel5_IRQn(USART1_RX_DMA_IRQ_Callback) instead of disable the channel since STM32f1
182 | can not requests the end of transfers when EN bit is cleared by software */
183 | NVIC_SetPendingIRQ(DMA1_Channel5_IRQn);
184 | }
185 | else
186 | {
187 | /* No new data received */
188 | }
189 | }
190 |
191 |
192 | /**
193 | * @brief DMA1 Channel4 initialization function
194 | * @note Used for data transfer between two memory buffers
195 | * @param None
196 | * @retval None
197 | */
198 | void USART1_TX_DMA_Config(void)
199 | {
200 | /* Enable clock for DMA1*/
201 | RCC ->AHBENR |= RCC_AHBENR_DMA1EN;
202 |
203 | /* disable channel, since this registers must not be written when the channel is enabled */
204 | if(DMA_CCR1_EN == (DMA_CCR1_EN & DMA1_Channel4->CCR))
205 | {
206 | /* DMA 2 stream 5 is enabled, shall be disabled first */
207 | DMA_ChannelDisable(DMA1_Channel4);
208 |
209 | /* Wait until EN bit is cleared */
210 | while(DMA_CCR1_EN == (DMA_CCR1_EN & DMA1_Channel4->CCR))
211 | {
212 | /* Do nothing until EN bit is cleared */
213 | }
214 | }
215 | else
216 | {
217 | /* Do nothing, stream 5 is not enabled */
218 | }
219 |
220 | /* Set Peripheral size 8-bits (00)*/
221 | DMA1_Channel4 ->CCR &= ~DMA_CCR1_PSIZE;
222 |
223 | /* Set Memory size 8-bits (00)*/
224 | DMA1_Channel4 ->CCR &= ~DMA_CCR1_MSIZE;
225 |
226 | /* Set Channel priority Very high (11)*/
227 | DMA1_Channel4 ->CCR |= DMA_CCR1_PL;
228 |
229 | /* Disable Peripheral increment mode (0) */
230 | DMA1_Channel4 ->CCR &= ~DMA_CCR1_PINC;
231 |
232 | /* Enable memory increment mode (1)*/
233 | DMA1_Channel4 ->CCR |= DMA_CCR1_MINC;
234 |
235 | /* Disable Circular mode (0)*/
236 | DMA1_Channel4 ->CCR &= ~DMA_CCR1_CIRC;
237 |
238 | /* Diable M2M Mode (0) */
239 | DMA1_Channel4 ->CCR &= ~DMA_CCR1_MEM2MEM;
240 |
241 | /* Data transfer direction Read from memory (1)*/
242 | DMA1_Channel4 ->CCR |= DMA_CCR1_DIR;
243 |
244 | /* Enable Transfer complete interrupt */
245 | DMA1_Channel4 ->CCR |= DMA_CCR1_TCIE;
246 |
247 | /* Set address for peripheral */
248 | DMA1_Channel4 ->CPAR = (uint32_t)&USART1->DR;
249 |
250 | __ASM("NOP");
251 | __ASM("NOP");
252 | __ASM("NOP");
253 | __ASM("NOP");
254 | }
255 |
256 |
257 | /**
258 | * @brief DMA1 Channel5 initialization function
259 | * @note Used for data transfer between two memory buffers
260 | * @param None
261 | * @retval None
262 | */
263 | void USART1_RX_DMA_Config(void)
264 | {
265 | /* Enable clock for DMA1*/
266 | RCC ->AHBENR |= RCC_AHBENR_DMA1EN;
267 |
268 | /* disable channel, since this registers must not be written when the channel is enabled */
269 | if(DMA_CCR1_EN == (DMA_CCR1_EN & DMA1_Channel5->CCR))
270 | {
271 | /* DMA 2 stream 5 is enabled, shall be disabled first */
272 | DMA_ChannelDisable(DMA1_Channel5);
273 |
274 | /* Wait until EN bit is cleared */
275 | while(DMA_CCR1_EN == (DMA_CCR1_EN & DMA1_Channel5->CCR))
276 | {
277 | /* Do nothing until EN bit is cleared */
278 | }
279 | }
280 | else
281 | {
282 | /* Do nothing, stream 5 is not enabled */
283 | }
284 |
285 | /* Set Peripheral size 8-bits (00)*/
286 | DMA1_Channel5 ->CCR &= ~DMA_CCR1_PSIZE;
287 |
288 | /* Set Memory size 8-bits (00)*/
289 | DMA1_Channel5 ->CCR &= ~DMA_CCR1_MSIZE;
290 |
291 | /* Set Channel priority Very high (11)*/
292 | DMA1_Channel5 ->CCR |= DMA_CCR1_PL;
293 |
294 | /* Disable Peripheral increment mode (0) */
295 | DMA1_Channel5 ->CCR &= ~DMA_CCR1_PINC;
296 |
297 | /* Enable memory increment mode (1)*/
298 | DMA1_Channel5 ->CCR |= DMA_CCR1_MINC;
299 |
300 | /* Disable Circular mode (0)*/
301 | DMA1_Channel5 ->CCR &= ~DMA_CCR1_CIRC;
302 |
303 | /* Diable M2M Mode (0) */
304 | DMA1_Channel5 ->CCR &= ~DMA_CCR1_MEM2MEM;
305 |
306 | /* Data transfer direction Read from peripheral (0)*/
307 | DMA1_Channel5 ->CCR &= ~DMA_CCR1_DIR;
308 |
309 | /* Enable Transfer complete interrupt */
310 | DMA1_Channel5 ->CCR |= DMA_CCR1_TCIE;
311 |
312 | /* Set address for peripheral */
313 | DMA1_Channel5 ->CPAR = (uint32_t)&USART1->DR;
314 |
315 | /* Set address for memory */
316 | DMA1_Channel5 ->CMAR = (uint32_t)RxDMABuffer;
317 |
318 | /* Set number of data items */
319 | DMA1_Channel5 ->CNDTR = MAX_BUFFER_LENGTH;
320 |
321 | __ASM("NOP");
322 | __ASM("NOP");
323 | __ASM("NOP");
324 | __ASM("NOP");
325 | }
326 | /**
327 | * @brief IRQ callback function
328 | * @note
329 | * @param None
330 | * @retval None
331 | */
332 | void USART1_TX_DMA_IRQ_Callback(void)
333 | {
334 | /* Check transfer complete flag */
335 | if((DMA1->ISR & DMA_ISR_TCIF4) == DMA_ISR_TCIF4)
336 | {
337 | /* DMA transfer is complete */
338 |
339 | /* Clear transfer complete flag */
340 | DMA1->IFCR |= DMA_IFCR_CTCIF4;
341 |
342 | while((USART1->SR& USART_SR_TC) != USART_SR_TC){}
343 | /* Disable DMA 1 Channel 4 */
344 | DMA_ChannelDisable(DMA1_Channel4);
345 | }
346 |
347 | /* Clears the GIF, TEIF, HTIF and TCIF flags in the DMA_ISR register */
348 | DMA1->IFCR |= DMA_IFCR_CGIF4;
349 | }
350 |
351 | /**
352 | * @brief IRQ callback function
353 | * @note
354 | * @param None
355 | * @retval None
356 | */
357 | void USART1_RX_DMA_IRQ_Callback(void)
358 | {
359 | /* Check transfer complete flag */
360 |
361 | //if((DMA1->ISR & DMA_ISR_TCIF5) == DMA_ISR_TCIF5)
362 | //{
363 | /* Calculate amount of data received */
364 | RxMessageLength = MAX_BUFFER_LENGTH - DMA1_Channel5->CNDTR;
365 | /* Reset address for memory */
366 | DMA1_Channel5 ->CMAR = (uint32_t)RxDMABuffer;
367 |
368 | /* Reset number of data items */
369 | DMA1_Channel5 ->CNDTR = MAX_BUFFER_LENGTH;
370 |
371 | /* Copy data into RX buffer */
372 | for(int idx = 0; idx < RxMessageLength; idx++)
373 | {
374 | RxBuffer[idx] = RxDMABuffer[idx];
375 | }
376 |
377 | /* Check error status */
378 | if(USART1_NO_ERROR != currentErrorStatus)
379 | {
380 | /* Error detected, discard the received data */
381 | RxMessageLength = 0;
382 | }
383 | else
384 | {
385 | /* No error detected */
386 | }
387 |
388 |
389 | /* Clears the GIF, TEIF, HTIF and TCIF flags in the DMA_ISR register */
390 | DMA1->IFCR |= DMA_IFCR_CGIF5;
391 |
392 | /* Enable DMA 1 Channel 5 */
393 | DMA_ChannelEnable(DMA1_Channel5,1,5);
394 | // }
395 | //else
396 | //{
397 | /* Do nothing, this interrupt is not handled */
398 | //}
399 | }
400 |
401 |
402 | /**
403 | * @brief String transmit
404 | * @note
405 | * @param USARTX, str
406 | * @retval None
407 | */
408 | void USART_Send_String(USART_TypeDef *USARTx,const char *str)
409 | {
410 | /* Check null pointers */
411 | if(NULL != str)
412 | {
413 |
414 | /* Wait until DMA1 Channel 4 is disabled */
415 | while(DMA_CCR1_EN == (DMA_CCR1_EN & DMA1_Channel4->CCR))
416 | {
417 | /* Do nothing, the enable flag shall reset
418 | * when DMA transfer complete */
419 | }
420 | /* Set address for memory */
421 | DMA1_Channel4 ->CMAR = (uint32_t)str;
422 |
423 | /* Set no. of data to transfer */
424 | int size =0;
425 | while(*str++ != '\0')size++;
426 |
427 | DMA1_Channel4 ->CNDTR = ++size;
428 | /* Enable DMA */
429 | DMA_ChannelEnable(DMA1_Channel4,1,4);
430 | }
431 | else
432 | {
433 | /* Null pointers, do nothing */
434 | }
435 | }
436 |
437 |
438 |
439 | /**
440 | * @brief USART1 GPIO initialization function
441 | * @note PA9 -> USART1_TX
442 | * PA10 -> USART1_RX
443 | * PA11 -> USART1_CTS
444 | * PA12 -> USART1_RTS
445 | * "Table 5. Medium-density STM32F103xx pin definitions" in Datasheet
446 | * "Table 24. USARTs" in Reference manual
447 | * @param HFC if = 1 -> Init. CTS & RTS pins
448 | * @retval None
449 | */
450 | void USART1_GPIO_Init(uint8_t HFC)
451 | {
452 | /* GPIOA clock enable */
453 | RCC ->APB2ENR |= RCC_APB2ENR_IOPAEN;
454 |
455 | /* PA9 TX: Output mode, max speed 2 MHz. */
456 | GPIOA ->CRH &= ~GPIO_CRH_MODE9;
457 | GPIOA ->CRH |= GPIO_CRH_MODE9_1;
458 |
459 | /* PA9 TX: Alternate function output Push-pull */
460 | GPIOA ->CRH &= ~GPIO_CRH_CNF9;
461 | GPIOA ->CRH |= GPIO_CRH_CNF9_1;
462 |
463 | /* PA10 RX: Floating input */
464 | GPIOA ->CRH &= ~GPIO_CRH_CNF10;
465 | GPIOA ->CRH |= GPIO_CRH_CNF10_0;
466 |
467 | /* PA10 RX: Input mode */
468 | GPIOA ->CRH &= ~GPIO_CRH_MODE10;
469 | if(HFC == 1)
470 | {
471 | /* PA11 CTS: Floating input */
472 | GPIOA ->CRH &= ~GPIO_CRH_CNF11;
473 | GPIOA ->CRH |= GPIO_CRH_CNF11_0;
474 |
475 | /* PA11 CTS: Input mode */
476 | GPIOA ->CRH &= ~GPIO_CRH_MODE11;
477 |
478 | /* PA12 RTS: Output mode, max speed 2 MHz. */
479 | GPIOA ->CRH &= ~GPIO_CRH_MODE12;
480 | GPIOA ->CRH |= GPIO_CRH_MODE12_1;
481 |
482 | /* PA12 RTS: Alternate function output Push-pull */
483 | GPIOA ->CRH &= ~GPIO_CRH_CNF12;
484 | GPIOA ->CRH |= GPIO_CRH_CNF12_1;
485 | }
486 |
487 |
488 | }
489 |
490 | /**
491 | * @brief USART BRR value calculation
492 | * @note F_CK Input clock to the peripheral(PCLK1[APB1] for USART2, 3, 4, 5 or PCLK2[APB2] for USART1) & always over-sampling by 16
493 | * @param Baud_Rate: Desired Baud Rate value
494 | * F_CK: Input clock to the peripheral in Hz
495 | * @retval Value of BRR
496 | */
497 | uint16_t Cal_USART_BRR_Val(uint32_t Baud_Rate, uint32_t F_CK)
498 | {
499 | double USARTDIV=0;
500 | uint8_t Fraction;
501 |
502 | /* Set baud rate = 115200 Bps
503 | * USARTDIV = Fck / (16 * baud_rate)
504 | * = 72000000 / (16 * 115200) = 39.0625
505 | *
506 | * DIV_Fraction = 16 * 0.0625 = 1 = 0x1
507 | * DIV_Mantissa = 39 = 0x27
508 | *
509 | * BRR = 0x271 */
510 |
511 | USARTDIV = ( F_CK/(Baud_Rate*16.0) );
512 | Fraction = round( (USARTDIV - ((uint16_t)USARTDIV) )* 16 ) ;
513 | if(Fraction > 15)
514 | {
515 | Fraction=0;
516 | USARTDIV++;
517 | }
518 | return ( ( ((uint16_t)USARTDIV) << 4 ) + Fraction) ;
519 | }
520 |
521 |
522 | /**
523 | * @brief USART initialization function
524 | * @note None
525 | * @param BRR_Val: Can be calculated using Cal_USART_BRR_Val function
526 | * @retval None
527 | */
528 | void USART1_Init(uint16_t BRR_Val)
529 | {
530 |
531 | /* USART GPIO configuration -------------------------------------------------------*/
532 |
533 | /* Configuration GPIOA TX & RX based on Reference manual Table 24 & Table 54 */
534 | USART1_GPIO_Init(1);
535 |
536 | /* USART configuration -------------------------------------------------------*/
537 | /*Enable USART1 clock */
538 | RCC ->APB2ENR |= RCC_APB2ENR_USART1EN;
539 |
540 | /* select 1 Start bit, 9 Data bits, n Stop bit */
541 | USART1 ->CR1 |= USART_CR1_M;
542 |
543 | /* STOP bits, 00: 1 Stop bit */
544 | USART1->CR2 &= ~USART_CR2_STOP;
545 |
546 | /* Select odd parity */
547 | USART1->CR1 |= USART_CR1_PS;
548 |
549 | /* Enable parity control */
550 | USART1->CR1 |= USART_CR1_PCE;
551 |
552 | /* Set Baud Rate */
553 | USART1->BRR = BRR_Val;
554 |
555 | /* DMA mode enabled for reception */
556 | USART1->CR3 |= USART_CR3_DMAR;
557 |
558 | /* DMA mode enabled for transmitting */
559 | USART1->CR3 |= USART_CR3_DMAT;
560 |
561 | /* Enable RTS flow control */
562 | //USART1->CR3 |= USART_CR3_RTSE;
563 |
564 | /* Enable CTS flow control */
565 | //USART1->CR3 |= USART_CR3_CTSE;
566 |
567 | __ASM("NOP");
568 | __ASM("NOP");
569 | __ASM("NOP");
570 | __ASM("NOP");
571 |
572 | }
573 |
574 | /**
575 | * @brief Enable USART transmitter and receiver
576 | * @note
577 | * @param USARTx ,where x=1 ..3
578 | * @retval None
579 | */
580 | void USART_Enable(USART_TypeDef *USARTx)
581 | {
582 | /* Enable USART1 */
583 | USARTx->CR1 |= USART_CR1_UE;
584 |
585 | /* Enable transmitter */
586 | USARTx->CR1 |= USART_CR1_TE;
587 |
588 | /* Enable receiver */
589 | USARTx->CR1 |= USART_CR1_RE;
590 |
591 | /* Enable reception buffer not empty flag interrupt */
592 | USARTx->CR1 |= USART_CR1_RXNEIE;
593 |
594 | /* Enable parity error interrupt */
595 | USARTx->CR1 |= USART_CR1_PEIE;
596 |
597 | /* Enable idle line detection interrupt */
598 | USARTx->CR1 |= USART_CR1_IDLEIE;
599 |
600 | }
601 |
602 |
603 | /**
604 | * @brief USART1 transmit and receive data
605 | * @note
606 | * @param None
607 | * @retval None
608 | */
609 | void USART1_Process(void)
610 | {
611 | /* Check error status */
612 | if(USART1_NO_ERROR == currentErrorStatus)
613 | {
614 | /* Check current USART state */
615 | switch (currentState)
616 | {
617 | case USART1_IDLE:
618 | /* Transmit data */
619 | USART_Send_String(USART1, hello_world);
620 |
621 | /* Go to next state */
622 | currentState = USART1_WAIT_FOR_RESPONCE;
623 | break;
624 |
625 | case USART1_WAIT_FOR_RESPONCE:
626 | /* Check if new message received */
627 | if(0 != RxMessageLength)
628 | {
629 | /* Reset message length */
630 | RxMessageLength = 0;
631 |
632 | /* Go to next state */
633 | currentState = USART1_ASK_FOR_NAME;
634 | }
635 | else
636 | {
637 | /* Nothing received yet */
638 | }
639 | break;
640 |
641 | case USART1_ASK_FOR_NAME:
642 | /* Transmit data */
643 | USART_Send_String(USART1, ask_for_name);
644 |
645 | /* Go to next state */
646 | currentState = USART1_WAIT_FOR_NAME;
647 | break;
648 |
649 | case USART1_WAIT_FOR_NAME:
650 | /* Check if new message received */
651 | if(0 != RxMessageLength)
652 | {
653 | /* Transmit data */
654 | USART_Send_String(USART1, hi);
655 | USART_Send_String(USART1, RxBuffer);
656 | USART_Send_String(USART1,ask_for_command);
657 | USART_Send_String(USART1,ask_for_command_ex);
658 |
659 | /* Reset message length */
660 | RxMessageLength = 0;
661 |
662 | /* Go to next state */
663 | currentState = USART1_WAIT_FOR_COMMAND;
664 | }
665 | else
666 | {
667 | /* Nothing received yet */
668 | }
669 | break;
670 |
671 | case USART1_WAIT_FOR_COMMAND:
672 | /* Check if new message received */
673 | if(0 != RxMessageLength)
674 | {
675 | /* Reset message length */
676 | RxMessageLength = 0;
677 |
678 | /* String compare results */
679 | strCmpReturnType isMatch_01 = STR_NOT_EQUAL;
680 | strCmpReturnType isMatch_02 = STR_NOT_EQUAL;
681 | strCmpReturnType isMatch_03 = STR_NOT_EQUAL;
682 | strCmpReturnType isMatch_04 = STR_NOT_EQUAL;
683 |
684 | /* Compare with turn on green led command */
685 | isMatch_01 = strCmp(turn_on_green_led, RxBuffer,
686 | sizeof(turn_on_green_led));
687 |
688 | /* Check return status */
689 | if(STR_EQUAL == isMatch_01)
690 | {
691 | /* Turn on green led */
692 | // GPIO_TurnON_LED(EVAL_GREEN_LED);
693 |
694 | /* Transmit data */
695 | USART_Send_String(USART1,done);
696 | }
697 | else
698 | {
699 | /* Compare with turn on red led command */
700 | isMatch_02 = strCmp(turn_on_red_led, RxBuffer,
701 | sizeof(turn_on_red_led));
702 | }
703 |
704 | /* Check return status */
705 | if(STR_EQUAL == isMatch_02)
706 | {
707 | /* Turn on red led */
708 | // GPIO_TurnON_LED(EVAL_RED_LED);
709 |
710 | /* Transmit data */
711 | USART_Send_String(USART1,done);
712 | }
713 | else if(STR_NOT_EQUAL == isMatch_01)
714 | {
715 | /* Compare with turn off green led command */
716 | isMatch_03 = strCmp(turn_off_green_led, RxBuffer,
717 | sizeof(turn_off_green_led));
718 | }
719 | else
720 | {
721 | /* Do nothing */
722 | }
723 |
724 | /* Check return status */
725 | if(STR_EQUAL == isMatch_03)
726 | {
727 | /* Turn off green led */
728 | // GPIO_TurnOFF_LED(EVAL_GREEN_LED);
729 |
730 | /* Transmit data */
731 | USART_Send_String(USART1,done);
732 | }
733 | else if((STR_NOT_EQUAL == isMatch_02)
734 | && (STR_NOT_EQUAL == isMatch_01))
735 | {
736 | /* Compare with turn off red led command */
737 | isMatch_04 = strCmp(turn_off_red_led, RxBuffer,
738 | sizeof(turn_off_red_led));
739 | }
740 | else
741 | {
742 | /* Do nothing */
743 | }
744 |
745 | /* Check return status */
746 | if(STR_EQUAL == isMatch_04)
747 | {
748 | /* Turn off red led */
749 | //GPIO_TurnOFF_LED(EVAL_RED_LED);
750 |
751 | /* Transmit data */
752 | USART_Send_String(USART1,done);
753 | }
754 | else if((STR_NOT_EQUAL == isMatch_03)
755 | && (STR_NOT_EQUAL == isMatch_02)
756 | && (STR_NOT_EQUAL == isMatch_01))
757 | {
758 | /* Transmit data */
759 | USART_Send_String(USART1,wrong_command);
760 | }
761 | else
762 | {
763 | /* Do nothing */
764 | }
765 | }
766 | else
767 | {
768 | /* Nothing received yet */
769 | }
770 | break;
771 |
772 | default:
773 | break;
774 | }
775 | }
776 | else if(USART1_PARITY_ERROR == currentErrorStatus)
777 | {
778 | /* Transmit parity error */
779 | USART_Send_String(USART1,parity_error);
780 |
781 | /* Clear error status */
782 | currentErrorStatus = USART1_NO_ERROR;
783 | }
784 | else
785 | {
786 | /* No error detected */
787 | }
788 | }
789 |
790 |
--------------------------------------------------------------------------------
/stm32_flash.ld:
--------------------------------------------------------------------------------
1 | /*
2 | ******************************************************************************
3 | File: stm32_flash.ld
4 | Info: Generated by Atollic TrueSTUDIO(R) 9.0.0 2018-06-29
5 |
6 | Abstract: Linker script for STM32F103C8 device
7 | Set heap size, stack size, stack location, memory areas and
8 | sections according to application requirements.
9 |
10 | The MIT License (MIT)
11 | Copyright (c) 2018 STMicroelectronics
12 |
13 | Permission is hereby granted, free of charge, to any person obtaining a copy
14 | of this software and associated documentation files (the "Software"), to deal
15 | in the Software without restriction, including without limitation the rights
16 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
17 | copies of the Software, and to permit persons to whom the Software is
18 | furnished to do so, subject to the following conditions:
19 |
20 | The above copyright notice and this permission notice shall be included in all
21 | copies or substantial portions of the Software.
22 |
23 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
24 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
25 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
26 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
27 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
28 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
29 | SOFTWARE.
30 |
31 | ******************************************************************************
32 | */
33 |
34 | /* Entry Point */
35 | ENTRY(Reset_Handler)
36 |
37 | /* Highest address of the user mode stack */
38 | _estack = 0x20005000; /* end of 20K RAM */
39 |
40 | /* Generate a link error if heap and stack don't fit into RAM */
41 | _Min_Heap_Size = 0; /* required amount of heap */
42 | _Min_Stack_Size = 0x100; /* required amount of stack */
43 |
44 | /* Specify the memory areas */
45 | MEMORY
46 | {
47 | FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 64K
48 | RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 20K
49 | MEMORY_B1 (rx) : ORIGIN = 0x60000000, LENGTH = 0K
50 | }
51 |
52 | /* Define output sections */
53 | SECTIONS
54 | {
55 | /* The startup code goes first into FLASH */
56 | .isr_vector :
57 | {
58 | . = ALIGN(4);
59 | KEEP(*(.isr_vector)) /* Startup code */
60 | . = ALIGN(4);
61 | } >FLASH
62 |
63 | /* The program code and other data goes into FLASH */
64 | .text :
65 | {
66 | . = ALIGN(4);
67 | *(.text) /* .text sections (code) */
68 | *(.text*) /* .text* sections (code) */
69 | *(.glue_7) /* glue arm to thumb code */
70 | *(.glue_7t) /* glue thumb to arm code */
71 | *(.eh_frame)
72 |
73 | KEEP (*(.init))
74 | KEEP (*(.fini))
75 |
76 | . = ALIGN(4);
77 | _etext = .; /* define a global symbols at end of code */
78 | } >FLASH
79 |
80 | /* Constant data goes into FLASH */
81 | .rodata :
82 | {
83 | . = ALIGN(4);
84 | *(.rodata) /* .rodata sections (constants, strings, etc.) */
85 | *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
86 | . = ALIGN(4);
87 | } >FLASH
88 |
89 | .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
90 | .ARM : {
91 | __exidx_start = .;
92 | *(.ARM.exidx*)
93 | __exidx_end = .;
94 | } >FLASH
95 |
96 | .preinit_array :
97 | {
98 | PROVIDE_HIDDEN (__preinit_array_start = .);
99 | KEEP (*(.preinit_array*))
100 | PROVIDE_HIDDEN (__preinit_array_end = .);
101 | } >FLASH
102 | .init_array :
103 | {
104 | PROVIDE_HIDDEN (__init_array_start = .);
105 | KEEP (*(SORT(.init_array.*)))
106 | KEEP (*(.init_array*))
107 | PROVIDE_HIDDEN (__init_array_end = .);
108 | } >FLASH
109 | .fini_array :
110 | {
111 | PROVIDE_HIDDEN (__fini_array_start = .);
112 | KEEP (*(SORT(.fini_array.*)))
113 | KEEP (*(.fini_array*))
114 | PROVIDE_HIDDEN (__fini_array_end = .);
115 | } >FLASH
116 |
117 | /* used by the startup to initialize data */
118 | _sidata = LOADADDR(.data);
119 |
120 | /* Initialized data sections goes into RAM, load LMA copy after code */
121 | .data :
122 | {
123 | . = ALIGN(4);
124 | _sdata = .; /* create a global symbol at data start */
125 | *(.data) /* .data sections */
126 | *(.data*) /* .data* sections */
127 |
128 | . = ALIGN(4);
129 | _edata = .; /* define a global symbol at data end */
130 | } >RAM AT> FLASH
131 |
132 | /* Uninitialized data section */
133 | . = ALIGN(4);
134 | .bss :
135 | {
136 | /* This is used by the startup in order to initialize the .bss secion */
137 | _sbss = .; /* define a global symbol at bss start */
138 | __bss_start__ = _sbss;
139 | *(.bss)
140 | *(.bss*)
141 | *(COMMON)
142 |
143 | . = ALIGN(4);
144 | _ebss = .; /* define a global symbol at bss end */
145 | __bss_end__ = _ebss;
146 | } >RAM
147 |
148 | /* User_heap_stack section, used to check that there is enough RAM left */
149 | ._user_heap_stack :
150 | {
151 | . = ALIGN(4);
152 | PROVIDE ( end = . );
153 | PROVIDE ( _end = . );
154 | . = . + _Min_Heap_Size;
155 | . = . + _Min_Stack_Size;
156 | . = ALIGN(4);
157 | } >RAM
158 |
159 | /* MEMORY_bank1 section, code must be located here explicitly */
160 | /* Example: extern int foo(void) __attribute__ ((section (".mb1text"))); */
161 | .memory_b1_text :
162 | {
163 | *(.mb1text) /* .mb1text sections (code) */
164 | *(.mb1text*) /* .mb1text* sections (code) */
165 | *(.mb1rodata) /* read-only data (constants) */
166 | *(.mb1rodata*)
167 | } >MEMORY_B1
168 |
169 | /* Remove information from the standard libraries */
170 | /DISCARD/ :
171 | {
172 | libc.a ( * )
173 | libm.a ( * )
174 | libgcc.a ( * )
175 | }
176 |
177 | .ARM.attributes 0 : { *(.ARM.attributes) }
178 | }
179 |
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