├── package.json
├── CHANGELOG
├── settings
    └── language-verilog.cson
├── README.md
├── snippets
    └── language-verilog.cson
└── grammars
    └── verilog.cson


/package.json:
--------------------------------------------------------------------------------
 1 | {
 2 |   "name": "language-verilog",
 3 |   "version": "0.4.0",
 4 |   "description": "Verilog language support in Atom",
 5 |   "repository": {
 6 |     "type": "git",
 7 |     "url": "https://github.com/Razer6/language-verilog"
 8 |   },
 9 |   "bugs": {
10 |     "url": "https://github.com/Razer6/language-verilog/issues"
11 |   },
12 |   "license": "MIT",
13 |   "engines": {
14 |     "atom": ">0.50.0"
15 |   },
16 |   "dependencies": {}
17 | }
18 | 


--------------------------------------------------------------------------------
/CHANGELOG:
--------------------------------------------------------------------------------
 1 | v 0.5.0 (unreleased)
 2 |   - Make semaphore a keyword
 3 |    
 4 | v 0.4.0
 5 |   - Fix single line comments
 6 |   - Add more snippets
 7 |   - Add more keywords for SystemVerilog
 8 |   - Add SystemVerilog header *.svh to supported filetypes
 9 | 
10 | v 0.3.0
11 |   - Rename scoped properties to fix deprecated Package.loadSettings call
12 | 
13 | v 0.2.0
14 |   - Add additional keywords from Verilog IEEE Std 1800-2012
15 | 
16 | v 0.1.0
17 |   - Initial import from TextMate bundle
18 | 


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/settings/language-verilog.cson:
--------------------------------------------------------------------------------
1 | '.source.verilog':
2 |   'editor':
3 |     'foldEndPattern': '\\s*(end(case|module)?|`endif)\\b'
4 |     'commentStart': '// '
5 |     'increaseIndentPattern': "(.*\\bbegin\\b)|(^\\s*(function|case|module|class|task|generate|interface|fork|sequence|property|covergroup|clocking|program|package|config|table|primitive)\\b)"
6 |     'decreaseIndentPattern': "\\s*(end|endfunction|endcase|endmodule|endclass|endtask|endgenerate|endinterface|join|join_any|join_none|endsequence|endproperty|endgroup|endclocking|endprogram|endpackage|endconfig|endtable|endprimitive)\\b"
7 | 


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/README.md:
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 1 | # Verilog language support in Atom
 2 | 
 3 | Adds syntax highlighting and snippets to Verilog files in Atom.
 4 | 
 5 | Originally [converted](http://atom.io/docs/latest/converting-a-text-mate-bundle)
 6 | from the [verilog.tmbundle](https://github.com/textmate/verilog.tmbundle).
 7 | 
 8 | ## Contributing
 9 | 
10 | 1. Fork it ( https://github.com/razer6/language-verilog/fork )
11 | 2. Create your feature branch (`git checkout -b my-new-feature`)
12 | 3. Commit your changes (`git commit -am 'Add some feature'`)
13 | 4. Push to the branch (`git push origin my-new-feature`)
14 | 5. Create a new Pull Request
15 | 


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/snippets/language-verilog.cson:
--------------------------------------------------------------------------------
  1 | '.source.verilog':
  2 | #A
  3 |   'always_clock':
  4 |     'prefix': 'always_c'
  5 |     'body': """
  6 |       always @ (posedge ${1:wire}) begin
  7 |       \t$0
  8 |       end
  9 |     """
 10 | 
 11 |   'always_clock_reset':
 12 |     'prefix': 'always_cr'
 13 |     'body': """
 14 |       always @ (posedge ${1:clock} or ${2:reset}) begin
 15 |       \t$0
 16 |       end
 17 |     """
 18 | 
 19 |   'always':
 20 |     'prefix': 'always'
 21 |     'body': """
 22 |       always @ ( * ) begin
 23 |       \t$0
 24 |       end
 25 |     """
 26 | 
 27 |   'always_ff_clock':
 28 |     'prefix': 'always_ff_c'
 29 |     'body': """
 30 |       always_ff @ (posedge ${1:clock}) begin
 31 |       \t$0
 32 |       end
 33 |     """
 34 | 
 35 |   'always_ff_clock_reset':
 36 |     'prefix': 'always_ff_cr'
 37 |     'body': """
 38 |       always_ff @ (posedge ${1:clock} or ${2:reset}) begin
 39 |       \t$0
 40 |       end
 41 |     """
 42 | 
 43 |   'always_latch':
 44 |     'prefix': 'always_latch'
 45 |     'body': """
 46 |       always_latch begin
 47 |       \t$0
 48 |       end
 49 |     """
 50 | 
 51 |   'always_comb':
 52 |     'prefix': 'always_comb'
 53 |     'body': """
 54 |       always_comb begin
 55 |       \t$0
 56 |       end
 57 |     """
 58 | 
 59 |   'assign single':
 60 |     'prefix': 'assign_s'
 61 |     'body': """
 62 |       assign ${1:destination} = (${2:source});
 63 |       $0
 64 |     """
 65 | 
 66 |   'assign multi':
 67 |     'prefix': 'assign_m'
 68 |     'body': """
 69 |       assign ${1:destination} = (${2:question}) ? ${3:true_source} : ${4:else_source}
 70 |       $0
 71 |     """
 72 | 
 73 | 
 74 | #B
 75 | 
 76 | #C
 77 |   'case':
 78 |     'prefix': 'case'
 79 |     'body': """
 80 |       case (${1:condition})
 81 |       \t${2:value}: $0;
 82 |       \tdefault: ;
 83 |       endcase
 84 |     """
 85 | 
 86 | #D
 87 | 
 88 | #E
 89 | 
 90 | #F
 91 | 
 92 | #G
 93 | 
 94 | #H
 95 | 
 96 | #I
 97 |   'if':
 98 |     'prefix': 'if'
 99 |     'body': """
100 |       if (${1:condition}) begin
101 |       \t$0
102 |       end
103 |     """
104 | 
105 |   'if-else':
106 |     'prefix': 'if-else'
107 |     'body': """
108 |       if (${1:condition}) begin
109 |       \t$0
110 |       end else begin
111 |       \t
112 |       end
113 |     """
114 | 
115 |   'if-elseif':
116 |     'prefix': 'if-elseif'
117 |     'body': """
118 |       if (${1:condition1}) begin
119 |       \t$0
120 |       end else if (${2:condition2}) begin
121 |       \t
122 |       end
123 |     """
124 | 
125 |   'if-elseif-else':
126 |     'prefix': 'if-elseif-else'
127 |     'body': """
128 |       if (${1:condition1}) begin
129 |       \t$0
130 |       end else if (${2:condition2}) begin
131 |       \t
132 |       end else begin
133 |       \t
134 |       end
135 |     """
136 | 
137 |   'input':
138 |     'prefix': 'input'
139 |     'body': """
140 |       input $0
141 |     """
142 | 
143 |   'initial':
144 |     'prefix': 'initial'
145 |     'body': """
146 |       initial begin
147 |       \t$0
148 |       end
149 |     """
150 | 
151 |   'ifdef_simulation':
152 |     'prefix': 'ifdef_sim'
153 |     'body': """
154 |       `ifdef SIMULATION
155 |       \t$0
156 |       `endif
157 |     """
158 | 
159 | 
160 | #J
161 | 
162 | #K
163 | 
164 | #L
165 |   'localparam':
166 |     'prefix': 'localparam'
167 |     'body': """
168 |       localparam  ${1:param_name} = ${2:param_value};
169 |     """
170 | 
171 |   'logic_range':
172 |     'prefix': 'logic_range'
173 |     'body': """
174 |       logic [${1:left_range}:${2:right_range}] ${3:name};
175 |       $0
176 |     """
177 | 
178 | #M
179 |   'module':
180 |     'prefix': 'module'
181 |     'body': """
182 |       module ${1:module_name} ($0);
183 |       \t
184 |       endmodule // $1
185 |     """
186 | 
187 | #N
188 | 
189 | #O
190 |   'output':
191 |     'prefix': 'output'
192 |     'body': """
193 |       output $0
194 |     """
195 | 
196 | #P
197 |   'parameter':
198 |     'prefix': 'parameter'
199 |     'body': """
200 |       parameter ${1:parameter_type} ${2:parameter_name} = ${3:parameter_value},
201 |       $0
202 |     """
203 | 
204 | #Q
205 | 
206 | #R
207 |   'reg':
208 |     'prefix': 'reg'
209 |     'body': """
210 |       reg ${1:name};
211 |       $0
212 |     """
213 | 
214 |   'reg_range':
215 |     'prefix': 'reg_range'
216 |     'body': """
217 |       reg [${1:left_range}:${2:right_range}] ${3:name};
218 |       $0
219 |     """
220 | 
221 | #S
222 | 
223 | #T
224 |   'timescale':
225 |     'prefix': 'timescale'
226 |     'body': """
227 |       `timescale ${1:time} / ${2:time}
228 |       $0
229 |     """
230 | 
231 | #U
232 | 
233 | #V
234 | 
235 | #W
236 |   'while':
237 |     'prefix': 'while'
238 |     'body': """
239 |       while (${1:wire}) begin
240 |       \t$0
241 |       end
242 |     """
243 | 
244 |   'wire':
245 |     'prefix': 'wire'
246 |     'body': """
247 |       wire ${1:name};
248 |       $0
249 |     """
250 | 
251 |   'wire_range':
252 |     'prefix': 'wire_range'
253 |     'body': """
254 |       wire [${1:left_range}:${2:right_range}] ${3:name};
255 |       $0
256 |     """
257 | 
258 | #X
259 | 
260 | #Y
261 | 
262 | #Z
263 | 


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/grammars/verilog.cson:
--------------------------------------------------------------------------------
  1 | 'fileTypes': [
  2 |   'v'
  3 |   'sv'
  4 |   'vh'
  5 |   'svh'
  6 | ]
  7 | 'name': 'Verilog'
  8 | 'patterns': [
  9 |   {
 10 |     'include': '#comments'
 11 |   }
 12 |   {
 13 |     'include': '#module_pattern'
 14 |   }
 15 |   {
 16 |     'include': '#keywords'
 17 |   }
 18 |   {
 19 |     'include': '#constants'
 20 |   }
 21 |   {
 22 |     'include': '#strings'
 23 |   }
 24 |   {
 25 |     'include': '#operators'
 26 |   }
 27 | ]
 28 | 'repository':
 29 |   'comments':
 30 |     'patterns': [
 31 |       {
 32 |         'begin': '(^[ \\t]+)?(?=//)'
 33 |         'beginCaptures':
 34 |           '1':
 35 |             'name': 'punctuation.whitespace.comment.leading.verilog'
 36 |         'end': '(?!\\G)'
 37 |         'patterns': [
 38 |           {
 39 |             'begin': '//'
 40 |             'beginCaptures':
 41 |               '0':
 42 |                 'name': 'punctuation.definition.comment.verilog'
 43 |             'end': '\\n'
 44 |             'name': 'comment.line.double-slash.verilog'
 45 |           }
 46 |         ]
 47 |       }
 48 |       {
 49 |         'begin': '/\\*'
 50 |         'end': '\\*/'
 51 |         'name': 'comment.block.c-style.verilog'
 52 |       }
 53 |     ]
 54 |   'constants':
 55 |     'patterns': [
 56 |       {
 57 |         'match': '\\b[0-9]+\'[bBoOdDhH][a-fA-F0-9_xXzZ]+\\b'
 58 |         'name': 'constant.numeric.sized_integer.verilog'
 59 |       }
 60 |       {
 61 |         'match': '\\s\'[bBoOdDhH][a-fA-F0-9_xXzZ]+\\b'
 62 |         'name': 'constant.numeric.unsized_integer.verilog'
 63 |       }
 64 |       {
 65 |         'captures':
 66 |           '1':
 67 |             'name': 'constant.numeric.integer.verilog'
 68 |           '2':
 69 |             'name': 'punctuation.separator.range.verilog'
 70 |           '3':
 71 |             'name': 'constant.numeric.integer.verilog'
 72 |         'match': '\\b(\\d+)(:)(\\d+)\\b'
 73 |         'name': 'meta.block.numeric.range.verilog'
 74 |       }
 75 |       {
 76 |         'match': '\\b\\d+(?i:e\\d+)?\\b'
 77 |         'name': 'constant.numeric.integer.verilog'
 78 |       }
 79 |       {
 80 |         'match': '\\b\\d+\\.\\d+(?i:e\\d+)?\\b'
 81 |         'name': 'constant.numeric.real.verilog'
 82 |       }
 83 |       {
 84 |         'match': '#\\d+'
 85 |         'name': 'constant.numeric.delay.verilog'
 86 |       }
 87 |       {
 88 |         'match': '\\b[01xXzZ]+\\b'
 89 |         'name': 'constant.numeric.logic.verilog'
 90 |       }
 91 |     ]
 92 |   'instantiation_patterns':
 93 |     'patterns': [
 94 |       {
 95 |         'include': '#keywords'
 96 |       }
 97 |       {
 98 |         'begin': '^\\s*([a-zA-Z][a-zA-Z0-9_]*)\\s+([a-zA-Z][a-zA-Z0-9_]*)(?<!begin|if)\\s*(?=\\(|$)'
 99 |         'beginCaptures':
100 |           '1':
101 |             'name': 'entity.name.tag.module.reference.verilog'
102 |           '2':
103 |             'name': 'entity.name.tag.module.identifier.verilog'
104 |         'end': ';'
105 |         'endCaptures':
106 |           '0':
107 |             'name': 'punctuation.terminator.expression.verilog'
108 |         'name': 'meta.block.instantiation.parameterless.verilog'
109 |         'patterns': [
110 |           {
111 |             'include': '#comments'
112 |           }
113 |           {
114 |             'include': '#constants'
115 |           }
116 |           {
117 |             'include': '#strings'
118 |           }
119 |         ]
120 |       }
121 |       {
122 |         'begin': '^\\s*([a-zA-Z][a-zA-Z0-9_]*)\\s*(#)(?=\\s*\\()'
123 |         'beginCaptures':
124 |           '1':
125 |             'name': 'entity.name.tag.module.reference.verilog'
126 |         'end': ';'
127 |         'endCaptures':
128 |           '0':
129 |             'name': 'punctuation.terminator.expression.verilog'
130 |         'name': 'meta.block.instantiation.with.parameters.verilog'
131 |         'patterns': [
132 |           {
133 |             'include': '#parenthetical_list'
134 |           }
135 |           {
136 |             'match': '[a-zA-Z][a-zA-Z0-9_]*'
137 |             'name': 'entity.name.tag.module.identifier.verilog'
138 |           }
139 |         ]
140 |       }
141 |     ]
142 |   'keywords':
143 |     'patterns': [
144 |       {
145 |         'match': '\\b(alias|always|always_comb|always_ff|always_latch|and|assert|assign|assume|attribute|automatic|begin|before|bind|bins|binsof|bit|break|buf|bufif0|bufif1|byte|case(xz)?|cell|chandle|class|clocking|cmos|config|const|constraint|context|continue|cover|covergroup|coverpoint|cross|dist|do|deassign|default|defparam|design|disable|edge|else|end(attribute|case|class|clocking|config|function|generate|group|interface|module|package|primitive|program|property|sequence|specify|table|task)?|enum|event|expect|export|extends|extern|final|first_match|for|foreach|force|forever|fork|forkjoin|function|generate|genvar|incdir|include|instance|highz(01)|if(none|f)?|ignore_bins|import|initial|inout|input|inside|integer|int|interface|interact|join|join_any|join_none|large|liblist|library|local|logic|localparam|longing|matches|medium|module|modport|macromodule|nand|negedge|new|nmos|nor|noshowcancelled|not|notif(01)|null|or|output|package|packed|parameter|pmos|posedge|primitive|priority|program|property|protected|pull0|pull1|pulldown|pullup|pulsestyle_onevent|pulsestyle_ondetect|pure|rand|randc|randcase|randsequence|rcmos|real|realtime|ref|reg|release|repeat|return|rnmos|rpmos|rtran|rtranif(01)|scalared|sequence|semaphore|shortint|shortreal|showcancelled|signed|small|solve|specify|specparam|static|strength|string|strong0|strong1|struct|super|supply0|supply1|table|tagged|task|this|throughout|time|timeprecision|timeunit|type|typedef|ran|tranif(01)|tri(01)?|tri(and|or|reg)|union|unique|unsigned|use|uwire|var|vectored|virtual|void|wait|wait_order|wand|weak(01)|wildcard|while|with|within|wire|wor|xnor|xor)\\b'
146 |         'name': 'keyword.other.verilog'
147 |       }
148 |       {
149 |         'match': '^\\s*`((cell)?define|default_(decay_time|nettype|trireg_strength)|delay_mode_(path|unit|zero)|ifdef|ifndef|include|end(if|celldefine)|else|(no)?unconnected_drive|resetall|timescale|undef)\\b'
150 |         'name': 'keyword.other.compiler.directive.verilog'
151 |       }
152 |       {
153 |         'match': '\\$(f(open|close|gets)|readmem(b|h)|timeformat|printtimescale|stop|finish|(s|real)?time|sformatf|realtobits|bitstoreal|rtoi|itor|(f)?(display|write(h|b))|error|info|fatal|write|bits|cast)\\b'
154 |         'name': 'support.function.system.console.tasks.verilog'
155 |       }
156 |       {
157 |         'match': '\\$(random|dist_(chi_square|erlang|exponential|normal|poisson|t|uniform)|urandom_range)\\b'
158 |         'name': 'support.function.system.random_number.tasks.verilog'
159 |       }
160 |       {
161 |         'match': '\\$((a)?sync\\$((n)?and|(n)or)\\$(array|plane))\\b'
162 |         'name': 'support.function.system.pld_modeling.tasks.verilog'
163 |       }
164 |       {
165 |         'match': '\\$(q_(initialize|add|remove|full|exam))\\b'
166 |         'name': 'support.function.system.stochastic.tasks.verilog'
167 |       }
168 |       {
169 |         'match': '\\$(fullskew|hold|nochange|period|recovery|recrem|removal|setup(hold)?|skew|timeskew|width)\\b'
170 |         'name': 'support.function.system.timing.tasks.verilog'
171 |       }
172 |       {
173 |         'match': '\\$(dump(file|vars|off|on|all|limit|flush)|clog2)\\b'
174 |         'name': 'support.function.system.vcd.tasks.verilog'
175 |       }
176 |       {
177 |         'match': '\\$(countdrivers|list|input|scope|showscopes|(no)?(key|log)|reset(_count|_value)?|(inc)?save|restart|showvars|getpattern|sreadmem(b|h)|scale)'
178 |         'name': 'support.function.non-standard.tasks.verilog'
179 |       }
180 |     ]
181 |   'module_pattern':
182 |     'patterns': [
183 |       {
184 |         'begin': '\\b(module)\\s+([a-zA-Z][a-zA-Z0-9_]*)'
185 |         'beginCaptures':
186 |           '1':
187 |             'name': 'storage.type.module.verilog'
188 |           '2':
189 |             'name': 'entity.name.type.module.verilog'
190 |         'end': '\\bendmodule\\b'
191 |         'endCaptures':
192 |           '0':
193 |             'name': 'storage.type.module.verilog'
194 |         'name': 'meta.block.module.verilog'
195 |         'patterns': [
196 |           {
197 |             'include': '#comments'
198 |           }
199 |           {
200 |             'include': '#keywords'
201 |           }
202 |           {
203 |             'include': '#constants'
204 |           }
205 |           {
206 |             'include': '#strings'
207 |           }
208 |           {
209 |             'include': '#instantiation_patterns'
210 |           }
211 |           {
212 |             'include': '#operators'
213 |           }
214 |         ]
215 |       }
216 |     ]
217 |   'operators':
218 |     'patterns': [
219 |       {
220 |         'match': '\\+|-|\\*|/|%|<|>|=|(!|=)?==?|!|&&?|\\|\\|?|\\^?~|~\\^?'
221 |         'name': 'keyword.operator.verilog'
222 |       }
223 |     ]
224 |   'parenthetical_list':
225 |     'patterns': [
226 |       {
227 |         'begin': '\\('
228 |         'beginCaptures':
229 |           '0':
230 |             'name': 'punctuation.section.list.verilog'
231 |         'end': '\\)'
232 |         'endCaptures':
233 |           '0':
234 |             'name': 'punctuation.section.list.verilog'
235 |         'name': 'meta.block.parenthetical_list.verilog'
236 |         'patterns': [
237 |           {
238 |             'include': '#parenthetical_list'
239 |           }
240 |           {
241 |             'include': '#comments'
242 |           }
243 |           {
244 |             'include': '#keywords'
245 |           }
246 |           {
247 |             'include': '#constants'
248 |           }
249 |           {
250 |             'include': '#strings'
251 |           }
252 |         ]
253 |       }
254 |     ]
255 |   'strings':
256 |     'patterns': [
257 |       {
258 |         'begin': '"'
259 |         'end': '"'
260 |         'name': 'string.quoted.double.verilog'
261 |         'patterns': [
262 |           {
263 |             'match': '\\\\.'
264 |             'name': 'constant.character.escape.verilog'
265 |           }
266 |         ]
267 |       }
268 |     ]
269 | 'scopeName': 'source.verilog'
270 | 


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