├── LICENSE ├── Makefile ├── archive └── fpga_0.93.bit.xz ├── axi4lite.rst ├── brd └── redpitaya │ └── 1.1 │ ├── board.xml │ ├── part0_pins.xml │ ├── preset.xml │ └── redpitaya.jpg ├── doc ├── calibregs.adoc ├── calibregs.pdf ├── redpitaya_block.odg └── redpitaya_block.odt ├── dts ├── clkc.dtsi ├── ethernet.dtsi ├── gpio.dtsi ├── i2c0.dtsi ├── i2c2gpio.dtsi ├── led-system-red.dtsi ├── led-system.dtso ├── led-user.dtsi ├── led-user.dtso ├── memory.dtsi ├── miso2gpio.dtsi ├── pl.dtsi.patch ├── qspi.dtsi ├── redpitaya.dtsi ├── spi1.dtsi ├── spi2gpio.dtsi ├── tft │ ├── tft-E2.dtsi │ ├── tft-hx8357d-stmpe601.dtsi │ └── tft-ili9341-ads7846.dtsi ├── uart2gpio.dtsi ├── uio-api.dtsi ├── usb0.dtsi ├── watchdog.dtsi ├── xadc.dtsi └── zynq-7000.dts ├── dts_250 ├── clkc.dtsi ├── ethernet.dtsi ├── gpio.dtsi ├── i2c0.dtsi ├── i2c2gpio.dtsi ├── led-system-red.dtsi ├── led-system.dtso ├── led-user.dtsi ├── led-user.dtso ├── memory.dtsi ├── miso2gpio.dtsi ├── pl.dtsi.patch ├── qspi.dtsi ├── redpitaya.dtsi ├── spi1.dtsi ├── spi2gpio.dtsi ├── tft │ ├── tft-E2.dtsi │ ├── tft-hx8357d-stmpe601.dtsi │ └── tft-ili9341-ads7846.dtsi ├── uart2gpio.dtsi ├── uio-api.dtsi ├── usb0.dtsi ├── watchdog.dtsi ├── xadc.dtsi └── zynq-7000.dts ├── dts_250a ├── clkc.dtsi ├── ethernet.dtsi ├── gpio.dtsi ├── i2c0.dtsi ├── i2c2gpio.dtsi ├── led-system-red.dtsi ├── led-system.dtso ├── led-user.dtsi ├── led-user.dtso ├── memory.dtsi ├── miso2gpio.dtsi ├── pl.dtsi.patch ├── qspi.dtsi ├── redpitaya.dtsi ├── spi1.dtsi ├── spi2gpio.dtsi ├── tft │ ├── tft-E2.dtsi │ ├── tft-hx8357d-stmpe601.dtsi │ └── tft-ili9341-ads7846.dtsi ├── uart2gpio.dtsi ├── uio-api.dtsi ├── usb0.dtsi ├── watchdog.dtsi ├── xadc.dtsi └── zynq-7000.dts ├── dts_uboot ├── clkc.dtsi ├── ethernet.dtsi ├── i2c0.dtsi ├── pcw.dtsi ├── qspi.dtsi ├── redpitaya.dtsi ├── system-top.dts ├── usb0.dtsi ├── zynq-7000.dts └── zynq-7000.dtsi ├── ip ├── asg_dat_fifo │ ├── asg_dat_fifo.dcp │ ├── asg_dat_fifo.xci │ ├── asg_dat_fifo.xdc │ ├── asg_dat_fifo.xml │ ├── asg_dat_fifo_clocks.xdc │ ├── asg_dat_fifo_ooc.xdc │ ├── asg_dat_fifo_sim_netlist.v │ ├── asg_dat_fifo_sim_netlist.vhdl │ ├── asg_dat_fifo_stub.v │ ├── asg_dat_fifo_stub.vhdl │ ├── hdl │ │ ├── blk_mem_gen_v8_4_vhsyn_rfs.vhd │ │ └── fifo_generator_v13_2_vhsyn_rfs.vhd │ └── synth │ │ └── asg_dat_fifo.vhd ├── ila_0 │ └── ila_0.xci └── sync_fifo │ ├── hdl │ ├── blk_mem_gen_v8_4_vhsyn_rfs.vhd │ └── fifo_generator_v13_2_vhsyn_rfs.vhd │ ├── sync_fifo.dcp │ ├── sync_fifo.xci │ ├── sync_fifo.xdc │ ├── sync_fifo.xml │ ├── sync_fifo_clocks.xdc │ ├── sync_fifo_ooc.xdc │ ├── sync_fifo_sim_netlist.v │ ├── sync_fifo_sim_netlist.vhdl │ ├── sync_fifo_stub.v │ ├── sync_fifo_stub.vhdl │ └── synth │ └── sync_fifo.vhd ├── ip_250 ├── asg_dat_fifo │ └── asg_dat_fifo.xci └── sync_fifo │ └── sync_fifo.xci ├── prj ├── Examples │ ├── .gitignore │ ├── Frequency_counter │ │ ├── basic_red_pitaya_bd.tcl │ │ ├── cfg │ │ │ ├── clocks.xdc │ │ │ ├── ports.tcl │ │ │ ├── ports.xdc │ │ │ └── red_pitaya.xml │ │ ├── cores │ │ │ ├── axi_bram_reader_v1_0 │ │ │ │ ├── axi_bram_reader.v │ │ │ │ ├── bram_reader_v1_0_S00_AXI.v │ │ │ │ └── core_config.tcl │ │ │ ├── axi_cfg_register_v1_0 │ │ │ │ ├── axi_cfg_register.v │ │ │ │ └── core_config.tcl │ │ │ ├── axis_averager_v1_0 │ │ │ │ ├── axis_averager.v │ │ │ │ └── core_config.tcl │ │ │ ├── axis_constant_v1_0 │ │ │ │ ├── axis_constant.v │ │ │ │ └── core_config.tcl │ │ │ ├── axis_red_pitaya_adc_v1_0 │ │ │ │ ├── axis_red_pitaya_adc.v │ │ │ │ └── core_config.tcl │ │ │ ├── axis_red_pitaya_dac_v1_0 │ │ │ │ ├── axis_red_pitaya_dac.v │ │ │ │ └── core_config.tcl │ │ │ └── bram_switch_v1_0 │ │ │ │ ├── bram_switch.v │ │ │ │ └── core_config.tcl │ │ ├── frequency_counter.v │ │ ├── make_cores.tcl │ │ ├── make_project.tcl │ │ ├── pow2.v │ │ ├── scripts │ │ │ └── core.tcl │ │ ├── server │ │ │ └── counter.c │ │ ├── signal_decoder.v │ │ ├── signal_split.v │ │ └── sim │ │ │ ├── 4_fc_simulations.png │ │ │ └── freq_count_sim.v │ ├── Knight_rider │ │ ├── cfg │ │ │ ├── clocks.xdc │ │ │ ├── ports.tcl │ │ │ ├── ports.xdc │ │ │ └── red_pitaya.xml │ │ ├── knight_rider.v │ │ ├── make_project.tcl │ │ └── sim │ │ │ └── knight_rider_tb.v │ ├── Led_blink │ │ ├── cfg │ │ │ ├── clocks.xdc │ │ │ ├── ports.tcl │ │ │ ├── ports.xdc │ │ │ └── red_pitaya.xml │ │ └── make_project.tcl │ ├── README.md │ ├── Simple_moving_average │ │ ├── dts │ │ │ ├── fpga.dts │ │ │ └── fpga.dtso │ │ ├── ip │ │ │ ├── systemZ10.tcl │ │ │ ├── systemZ20.tcl │ │ │ └── systemZ20_14.tcl │ │ ├── make_project.tcl │ │ ├── rtl │ │ │ ├── loop_scope.v │ │ │ ├── moving_average.vhd │ │ │ ├── red_pitaya_proc.vhd │ │ │ ├── red_pitaya_ps.sv │ │ │ ├── red_pitaya_scope.v │ │ │ ├── red_pitaya_top.sv │ │ │ └── red_pitaya_top_Z20.sv │ │ ├── sdc │ │ │ └── red_pitaya.xdc │ │ └── tbn │ │ │ ├── red_pitaya_proc_tb.vhd │ │ │ ├── red_pitaya_ps_sim.sv │ │ │ ├── red_pitaya_top_sim.sv │ │ │ ├── sim_script.tcl │ │ │ ├── top_tb.sv │ │ │ └── top_tc.sv │ ├── Stopwatch │ │ ├── cfg │ │ │ ├── clocks.xdc │ │ │ ├── ports.tcl │ │ │ ├── ports.xdc │ │ │ └── red_pitaya.xml │ │ ├── make_project.tcl │ │ └── stopwatch.c │ ├── Vga_draw │ │ ├── Vitis_sources │ │ │ └── main.c │ │ ├── make_project.tcl │ │ ├── rtl │ │ │ ├── design_1_wrapper.v │ │ │ ├── picture.vhd │ │ │ └── vga_vhdl.vhd │ │ ├── sdc │ │ │ └── pinout.xdc │ │ ├── tb │ │ │ └── vga_tb.v │ │ └── vga_test.tcl │ ├── Vga_game │ │ ├── Vitis_sources │ │ │ └── vga_game.cpp │ │ ├── ip_repo │ │ │ ├── BlockImage_1.0 │ │ │ │ ├── bd │ │ │ │ │ └── bd.tcl │ │ │ │ ├── component.xml │ │ │ │ ├── example_designs │ │ │ │ │ ├── bfm_design │ │ │ │ │ │ ├── BlockImage_v1_0_tb.sv │ │ │ │ │ │ └── design.tcl │ │ │ │ │ └── debug_hw_design │ │ │ │ │ │ ├── BlockImage_v1_0_hw_test.tcl │ │ │ │ │ │ └── design.tcl │ │ │ │ ├── hdl │ │ │ │ │ ├── BlockImage_v1_0.v │ │ │ │ │ └── BlockImage_v1_0_S00_AXI.v │ │ │ │ ├── src │ │ │ │ │ ├── RectPic.v │ │ │ │ │ ├── pic_tb.v │ │ │ │ │ └── vga_vhdl.vhd │ │ │ │ └── xgui │ │ │ │ │ └── BlockImage_v1_0.tcl │ │ │ ├── CircleImage_1.0 │ │ │ │ ├── bd │ │ │ │ │ └── bd.tcl │ │ │ │ ├── component.xml │ │ │ │ ├── example_designs │ │ │ │ │ ├── bfm_design │ │ │ │ │ │ ├── CircleImage_v1_0_tb.sv │ │ │ │ │ │ └── design.tcl │ │ │ │ │ └── debug_hw_design │ │ │ │ │ │ ├── CircleImage_v1_0_hw_test.tcl │ │ │ │ │ │ └── design.tcl │ │ │ │ ├── hdl │ │ │ │ │ ├── CircleImage_v1_0.v │ │ │ │ │ └── CircleImage_v1_0_S00_AXI.v │ │ │ │ ├── src │ │ │ │ │ ├── CircPic.v │ │ │ │ │ ├── Circic_tb.v │ │ │ │ │ └── vga_vhdl.vhd │ │ │ │ └── xgui │ │ │ │ │ └── CircleImage_v1_0.tcl │ │ │ └── Keyboard_1.0 │ │ │ │ ├── bd │ │ │ │ └── bd.tcl │ │ │ │ ├── component.xml │ │ │ │ ├── example_designs │ │ │ │ ├── bfm_design │ │ │ │ │ ├── Keyboard_v1_0_tb.sv │ │ │ │ │ └── design.tcl │ │ │ │ └── debug_hw_design │ │ │ │ │ ├── Keyboard_v1_0_hw_test.tcl │ │ │ │ │ └── design.tcl │ │ │ │ ├── hdl │ │ │ │ ├── Keyboard_v1_0.v │ │ │ │ └── Keyboard_v1_0_S00_AXI.v │ │ │ │ └── xgui │ │ │ │ └── Keyboard_v1_0.tcl │ │ ├── make_project.tcl │ │ ├── rtl │ │ │ ├── design_1_wrapper.v │ │ │ └── vga_vhdl.vhd │ │ ├── sdc │ │ │ └── pinout.xdc │ │ └── tb │ │ │ ├── Circic_tb.v │ │ │ ├── pic_tb.v │ │ │ └── vga_tb.v │ ├── Vga_image │ │ ├── make_project.tcl │ │ ├── rtl │ │ │ ├── design_1_wrapper.v │ │ │ ├── picture.vhd │ │ │ └── vga_vhdl.vhd │ │ ├── sdc │ │ │ └── pinout.xdc │ │ └── tb │ │ │ └── vga_tb.v │ └── make_project.tcl ├── axi4lite │ ├── dts │ │ ├── fpga.dts │ │ ├── fpga.dtso │ │ └── pl_patch.dtsi │ ├── ip │ │ ├── systemZ10.tcl │ │ ├── systemZ20.tcl │ │ └── systemZ20_14.tcl │ ├── rtl │ │ ├── axi4lite_gpio.sv │ │ ├── red_pitaya_ps.sv │ │ └── red_pitaya_top.sv │ └── sdc │ │ └── red_pitaya.xdc ├── barebones │ ├── dts │ │ ├── fpga.dts │ │ ├── fpga.dtso │ │ └── pl_patch.dtsi │ ├── ip │ │ ├── systemZ10.tcl │ │ ├── systemZ20.tcl │ │ ├── systemZ20_14.tcl │ │ ├── systemZ20_G2.tcl │ │ └── systemZ20_ll.tcl │ ├── rtl │ │ ├── red_pitaya_top.sv │ │ ├── red_pitaya_top_4ADC.sv │ │ ├── red_pitaya_top_Z20.sv │ │ └── red_pitaya_top_ll.sv │ └── sdc │ │ ├── red_pitaya.xdc │ │ ├── red_pitaya_4ADC.xdc │ │ └── red_pitaya_G2.xdc ├── barebones_250 │ ├── dts │ │ ├── fpga.dts │ │ ├── fpga.dtso │ │ └── pl_patch.dtsi │ ├── ip │ │ ├── systemZ10.tcl │ │ └── systemZ20.tcl │ ├── rtl_250 │ │ ├── red_pitaya_top.sv │ │ └── red_pitaya_top_Z20.sv │ └── sdc │ │ └── red_pitaya.xdc ├── classic │ ├── dts │ │ ├── fpga.dts │ │ ├── fpga.dtso │ │ └── pl_patch.dtsi │ ├── ip │ │ ├── systemZ10.tcl │ │ ├── systemZ20.tcl │ │ └── systemZ20_14.tcl │ ├── rtl │ │ ├── red_pitaya_ps.sv │ │ └── red_pitaya_top.sv │ ├── sdc │ │ └── red_pitaya.xdc │ ├── sim │ │ ├── Makefile │ │ ├── red_pitaya_pwm_tb.gtkw │ │ └── red_pitaya_scope_tb.gtkw │ └── tbn │ │ ├── dfilt1_sim_values.txt │ │ ├── red_pitaya_ams_tb.sv │ │ ├── red_pitaya_asg_tb.sv │ │ ├── red_pitaya_dfilt1_tb.sv │ │ ├── red_pitaya_hk_tb.sv │ │ ├── red_pitaya_pid_tb.sv │ │ ├── red_pitaya_pwm_tb.sv │ │ ├── red_pitaya_scope_tb.sv │ │ ├── red_pitaya_scope_tb.v │ │ ├── system.sv │ │ └── top_tb.sv ├── fsbl │ ├── dts │ │ ├── fpga.dts │ │ ├── fpga.dtso │ │ └── pl_patch.dtsi │ ├── ip │ │ ├── systemZ10.tcl │ │ └── systemZ20.tcl │ ├── rtl │ │ ├── red_pitaya_top.sv │ │ ├── red_pitaya_top_4ADC.sv │ │ └── red_pitaya_top_Z20.sv │ ├── rtl_250 │ │ ├── red_pitaya_top.sv │ │ └── red_pitaya_top_Z20.sv │ └── sdc │ │ ├── red_pitaya.xdc │ │ └── red_pitaya_4ADC.xdc ├── logic │ ├── dts │ │ ├── dma.dtsi │ │ ├── fpga.dts │ │ ├── fpga.dtso │ │ └── pl_patch.dtsi │ ├── ip │ │ ├── systemZ10.tcl │ │ ├── systemZ20.tcl │ │ ├── systemZ20_14.tcl │ │ └── systemZ20_G2.tcl │ ├── rtl │ │ ├── red_pitaya_ps.sv │ │ ├── red_pitaya_top.sv │ │ ├── red_pitaya_top_4ADC.sv │ │ ├── red_pitaya_top_Z20.sv │ │ └── red_pitaya_top_ll.sv │ ├── sdc │ │ ├── red_pitaya.xdc │ │ ├── red_pitaya_4ADC.xdc │ │ └── red_pitaya_G2.xdc │ ├── sim │ │ └── top_tb.tcl │ └── tbn │ │ ├── system.sv │ │ └── top_tb.sv ├── logic_250 │ ├── dts │ │ ├── dma.dtsi │ │ ├── fpga.dts │ │ ├── fpga.dtso │ │ └── pl_patch.dtsi │ ├── ip │ │ ├── systemZ10.tcl │ │ └── systemZ20.tcl │ ├── rtl_250 │ │ ├── red_pitaya_ps.sv │ │ └── red_pitaya_top.sv │ ├── sdc │ │ └── red_pitaya.xdc │ ├── sim │ │ └── top_tb.tcl │ └── tbn │ │ ├── system.sv │ │ └── top_tb.sv ├── mercury │ ├── dts │ │ ├── fpga.dts │ │ ├── fpga.dtso │ │ └── pl_patch.dtsi │ ├── ip │ │ ├── systemZ10.tcl │ │ ├── systemZ20.tcl │ │ └── systemZ20_14.tcl │ ├── rtl │ │ ├── red_pitaya_ps.sv │ │ ├── red_pitaya_top.sv │ │ └── red_pitaya_top_pkg.sv │ ├── sdc │ │ └── red_pitaya.xdc │ ├── sim │ │ ├── Makefile │ │ └── top_tb.tcl │ └── tbn │ │ ├── system.sv │ │ └── top_tb.sv ├── pyrpl │ ├── dts │ │ └── pl_patch.dtsi │ ├── ip │ │ ├── systemZ10.tcl │ │ ├── systemZ20.tcl │ │ └── systemZ20_14.tcl │ ├── rtl │ │ ├── axi_master.v │ │ ├── axi_slave.v │ │ ├── axi_wr_fifo.v │ │ ├── pwm.sv │ │ ├── red_pitaya_adv_trigger.v │ │ ├── red_pitaya_ams.v │ │ ├── red_pitaya_asg.v │ │ ├── red_pitaya_asg_ch.v │ │ ├── red_pitaya_dfilt1.v │ │ ├── red_pitaya_dsp.v │ │ ├── red_pitaya_filter_block.v │ │ ├── red_pitaya_hk.v │ │ ├── red_pitaya_iir_block.v │ │ ├── red_pitaya_iir_block.v.current │ │ ├── red_pitaya_iq_block.v │ │ ├── red_pitaya_iq_demodulator_block.v │ │ ├── red_pitaya_iq_fgen_block.v │ │ ├── red_pitaya_iq_hpf_block.v │ │ ├── red_pitaya_iq_lpf_block.v │ │ ├── red_pitaya_iq_modulator_block.v │ │ ├── red_pitaya_lpf_block.v │ │ ├── red_pitaya_pfd_block.v │ │ ├── red_pitaya_pid_block.v │ │ ├── red_pitaya_pll.sv │ │ ├── red_pitaya_prng.v │ │ ├── red_pitaya_product_sat.v │ │ ├── red_pitaya_ps.sv │ │ ├── red_pitaya_pwm.sv │ │ ├── red_pitaya_saturate.v │ │ ├── red_pitaya_scope.v │ │ ├── red_pitaya_top.v │ │ ├── red_pitaya_top_Z20.v │ │ └── red_pitaya_trigger_block.v │ ├── rtl_unused │ │ ├── red_pitaya_compressor_block.v │ │ ├── red_pitaya_normalizer_block.v │ │ └── red_pitaya_pid_block_with_normalizer.v │ ├── sdc │ │ ├── red_pitaya.xdc │ │ └── red_pitaya_4ADC.xdc │ └── sdc_250 │ │ ├── red_pitaya.xdc │ │ └── red_pitaya_v1r0.xdc ├── stream_app │ ├── dts │ │ ├── fpga.dts │ │ ├── fpga.dtso │ │ └── pl_patch.dtsi │ ├── ip │ │ ├── rp_concat │ │ │ ├── component.xml │ │ │ ├── rp_concat.v │ │ │ ├── rp_concat.xpr │ │ │ └── rp_concat_v1_0.tcl │ │ ├── rp_dac │ │ │ ├── component.xml │ │ │ ├── dac_calib.v │ │ │ ├── dac_cfg.sv │ │ │ ├── dac_top.v │ │ │ ├── fifo_axi_data_dac │ │ │ │ ├── fifo_axi_data_dac.xci │ │ │ │ └── fifo_axi_data_dac.xml │ │ │ ├── fifo_axi_req │ │ │ │ ├── fifo_axi_req.xci │ │ │ │ └── fifo_axi_req.xml │ │ │ ├── reg_ctrl │ │ │ │ ├── reg_ctrl.xci │ │ │ │ └── reg_ctrl.xml │ │ │ ├── rp_dac.v │ │ │ ├── rp_dac.xpr │ │ │ ├── rp_dac_v1_0.tcl │ │ │ ├── rp_dma_mm2s.v │ │ │ ├── rp_dma_mm2s_ctrl.v │ │ │ ├── rp_dma_mm2s_data_ctrl.v │ │ │ ├── rp_dma_mm2s_downsize.v │ │ │ └── xgui │ │ │ │ └── rp_dac_v1_0.tcl │ │ ├── rp_gpio │ │ │ ├── component.xml │ │ │ ├── cts.sv │ │ │ ├── fifo_axi_data │ │ │ │ ├── fifo_axi_data.xci │ │ │ │ └── fifo_axi_data.xml │ │ │ ├── fifo_axi_data_dac │ │ │ │ ├── fifo_axi_data_dac.xci │ │ │ │ └── fifo_axi_data_dac.xml │ │ │ ├── fifo_axi_req │ │ │ │ ├── fifo_axi_req.xci │ │ │ │ └── fifo_axi_req.xml │ │ │ ├── gpio_dma_mm2s.v │ │ │ ├── gpio_dma_mm2s_ctrl.v │ │ │ ├── gpio_dma_mm2s_data_ctrl.v │ │ │ ├── gpio_dma_mm2s_downsize.v │ │ │ ├── gpio_dma_s2mm.v │ │ │ ├── gpio_dma_s2mm_ctrl.v │ │ │ ├── gpio_dma_s2mm_data_ctrl.v │ │ │ ├── gpio_dma_s2mm_upsize.v │ │ │ ├── gpio_in_top.sv │ │ │ ├── gpio_out_top.sv │ │ │ ├── reg_ctrl │ │ │ │ ├── reg_ctrl.xci │ │ │ │ └── reg_ctrl.xml │ │ │ ├── rle_rev.sv │ │ │ ├── rp_gpio.sv │ │ │ ├── rp_gpio.xpr │ │ │ ├── rp_gpio_v1_0.tcl │ │ │ └── xgui │ │ │ │ └── rp_gpio_v1_0.tcl │ │ ├── rp_oscilloscope │ │ │ ├── component.xml │ │ │ ├── fifo_axi_data │ │ │ │ ├── fifo_axi_data.xci │ │ │ │ └── fifo_axi_data.xml │ │ │ ├── fifo_axi_req │ │ │ │ ├── fifo_axi_req.veo │ │ │ │ ├── fifo_axi_req.vho │ │ │ │ ├── fifo_axi_req.xci │ │ │ │ └── fifo_axi_req.xml │ │ │ ├── osc_aquire.v │ │ │ ├── osc_calib.v │ │ │ ├── osc_decimator.v │ │ │ ├── osc_filter.v │ │ │ ├── osc_top.v │ │ │ ├── osc_trigger.v │ │ │ ├── red_pitaya_dfilt1.sv │ │ │ ├── rp_dma_s2mm.v │ │ │ ├── rp_dma_s2mm_ctrl.v │ │ │ ├── rp_dma_s2mm_data_ctrl.v │ │ │ ├── rp_dma_s2mm_upsize.v │ │ │ ├── rp_oscilloscope.v │ │ │ ├── rp_oscilloscope.xpr │ │ │ ├── rp_oscilloscope_v1_16.tcl │ │ │ ├── scope_cfg.sv │ │ │ ├── scope_filter.sv │ │ │ ├── sine.data │ │ │ └── xgui │ │ │ │ └── rp_oscilloscope_v1_16.tcl │ │ ├── systemZ10.tcl │ │ ├── systemZ20.tcl │ │ ├── systemZ20_14.tcl │ │ ├── systemZ20_4.tcl │ │ └── systemZ20_G2.tcl │ ├── regset_common_streaming.rst │ ├── rtl │ │ ├── red_pitaya_top.sv │ │ ├── red_pitaya_top_4ADC.sv │ │ ├── red_pitaya_top_Z20.sv │ │ └── red_pitaya_top_ll.sv │ ├── sdc │ │ ├── red_pitaya.xdc │ │ ├── red_pitaya_4ADC.xdc │ │ └── red_pitaya_G2.xdc │ └── tbn │ │ └── systemZ10_sim.tcl ├── stream_app_250 │ ├── dts │ │ ├── fpga.dts │ │ ├── fpga.dtso │ │ ├── pl_patch.dtsi │ │ └── pl_patch.dtsi.bak │ ├── ip │ │ ├── rp_concat │ │ │ ├── component.xml │ │ │ ├── rp_concat.v │ │ │ ├── rp_concat.xpr │ │ │ └── rp_concat_v1_0.tcl │ │ ├── rp_oscilloscope │ │ │ ├── component.xml │ │ │ ├── fifo_axi_data │ │ │ │ ├── fifo_axi_data.xci │ │ │ │ └── fifo_axi_data.xml │ │ │ ├── fifo_axi_req │ │ │ │ ├── fifo_axi_req.veo │ │ │ │ ├── fifo_axi_req.vho │ │ │ │ ├── fifo_axi_req.xci │ │ │ │ └── fifo_axi_req.xml │ │ │ ├── osc_aquire.v │ │ │ ├── osc_calib.v │ │ │ ├── osc_decimator.v │ │ │ ├── osc_filter.v │ │ │ ├── osc_top.v │ │ │ ├── osc_trigger.v │ │ │ ├── red_pitaya_dfilt1.sv │ │ │ ├── rp_dma_s2mm.v │ │ │ ├── rp_dma_s2mm_ctrl.v │ │ │ ├── rp_dma_s2mm_data_ctrl.v │ │ │ ├── rp_dma_s2mm_upsize.v │ │ │ ├── rp_oscilloscope.v │ │ │ ├── rp_oscilloscope.xpr │ │ │ ├── scope_cfg.sv │ │ │ ├── scope_filter.sv │ │ │ ├── sine.data │ │ │ └── xgui │ │ │ │ └── rp_oscilloscope_v1_16.tcl │ │ ├── systemZ10.tcl │ │ └── systemZ20.tcl │ ├── rtl_250 │ │ ├── red_pitaya_top.sv │ │ └── red_pitaya_top_Z20.sv │ ├── sdc │ │ └── red_pitaya.xdc │ └── tbn │ │ ├── red_pitaya_top_sim.sv │ │ ├── sim_script_Z20.tcl │ │ ├── top_tb.sv │ │ └── top_tc.sv ├── stream_app_4ch │ ├── dts │ │ ├── fpga.dts │ │ ├── fpga.dtso │ │ └── pl_patch.dtsi │ ├── ip │ │ ├── rp_concat │ │ │ ├── component.xml │ │ │ ├── rp_concat.v │ │ │ ├── rp_concat.xpr │ │ │ └── rp_concat_v1_0.tcl │ │ ├── rp_dac │ │ │ ├── component.xml │ │ │ ├── dac_calib.v │ │ │ ├── dac_cfg.sv │ │ │ ├── dac_top.v │ │ │ ├── fifo_axi_data_dac │ │ │ │ ├── fifo_axi_data_dac.xci │ │ │ │ └── fifo_axi_data_dac.xml │ │ │ ├── fifo_axi_req │ │ │ │ ├── fifo_axi_req.xci │ │ │ │ └── fifo_axi_req.xml │ │ │ ├── reg_ctrl │ │ │ │ ├── reg_ctrl.xci │ │ │ │ └── reg_ctrl.xml │ │ │ ├── rp_dac.v │ │ │ ├── rp_dac.xpr │ │ │ ├── rp_dac_v1_0.tcl │ │ │ ├── rp_dma_mm2s.v │ │ │ ├── rp_dma_mm2s_ctrl.v │ │ │ ├── rp_dma_mm2s_data_ctrl.v │ │ │ ├── rp_dma_mm2s_downsize.v │ │ │ └── xgui │ │ │ │ └── rp_dac_v1_0.tcl │ │ ├── rp_gpio │ │ │ ├── component.xml │ │ │ ├── cts.sv │ │ │ ├── fifo_axi_data │ │ │ │ ├── fifo_axi_data.xci │ │ │ │ └── fifo_axi_data.xml │ │ │ ├── fifo_axi_data_dac │ │ │ │ ├── fifo_axi_data_dac.xci │ │ │ │ └── fifo_axi_data_dac.xml │ │ │ ├── fifo_axi_req │ │ │ │ ├── fifo_axi_req.xci │ │ │ │ └── fifo_axi_req.xml │ │ │ ├── gpio_dma_mm2s.v │ │ │ ├── gpio_dma_mm2s_ctrl.v │ │ │ ├── gpio_dma_mm2s_data_ctrl.v │ │ │ ├── gpio_dma_mm2s_downsize.v │ │ │ ├── gpio_dma_s2mm.v │ │ │ ├── gpio_dma_s2mm_ctrl.v │ │ │ ├── gpio_dma_s2mm_data_ctrl.v │ │ │ ├── gpio_dma_s2mm_upsize.v │ │ │ ├── gpio_in_top.sv │ │ │ ├── gpio_out_top.sv │ │ │ ├── reg_ctrl │ │ │ │ ├── reg_ctrl.xci │ │ │ │ └── reg_ctrl.xml │ │ │ ├── rle_rev.sv │ │ │ ├── rp_gpio.sv │ │ │ ├── rp_gpio.xpr │ │ │ ├── rp_gpio_v1_0.tcl │ │ │ └── xgui │ │ │ │ └── rp_gpio_v1_0.tcl │ │ ├── rp_oscilloscope │ │ │ ├── component.xml │ │ │ ├── fifo_axi_data │ │ │ │ ├── fifo_axi_data.xci │ │ │ │ └── fifo_axi_data.xml │ │ │ ├── fifo_axi_req │ │ │ │ ├── fifo_axi_req.veo │ │ │ │ ├── fifo_axi_req.vho │ │ │ │ ├── fifo_axi_req.xci │ │ │ │ └── fifo_axi_req.xml │ │ │ ├── osc_aquire.v │ │ │ ├── osc_calib.v │ │ │ ├── osc_decimator.v │ │ │ ├── osc_filter.v │ │ │ ├── osc_top.v │ │ │ ├── osc_trigger.v │ │ │ ├── red_pitaya_dfilt1.sv │ │ │ ├── rp_dma_s2mm.v │ │ │ ├── rp_dma_s2mm_ctrl.v │ │ │ ├── rp_dma_s2mm_data_ctrl.v │ │ │ ├── rp_dma_s2mm_upsize.v │ │ │ ├── rp_oscilloscope.v │ │ │ ├── rp_oscilloscope.xpr │ │ │ ├── rp_oscilloscope_v1_16.tcl │ │ │ ├── scope_cfg.sv │ │ │ ├── scope_filter.sv │ │ │ ├── sine.data │ │ │ └── xgui │ │ │ │ └── rp_oscilloscope_v1_16.tcl │ │ ├── systemZ10.tcl │ │ ├── systemZ20.tcl │ │ ├── systemZ20_14.tcl │ │ └── systemZ20_4.tcl │ ├── regset_common_streaming.rst │ ├── rtl │ │ ├── red_pitaya_top.sv │ │ ├── red_pitaya_top_4ADC.sv │ │ └── red_pitaya_top_Z20.sv │ ├── sdc │ │ ├── red_pitaya.xdc │ │ └── red_pitaya_4ADC.xdc │ └── tbn │ │ ├── dac_sim.sv │ │ ├── gpio_sim.sv │ │ ├── red_pitaya_top_sim.sv │ │ ├── rp_4ADC_sim.sv │ │ ├── sim_script.tcl │ │ ├── sim_script_4ADC.tcl │ │ ├── sim_script_ADC.tcl │ │ ├── sim_script_DAC.tcl │ │ ├── sim_script_GPIO.tcl │ │ ├── top_tb.sv │ │ ├── top_tb_4ADC.sv │ │ ├── top_tc.sv │ │ ├── top_tc_4ADC.sv │ │ ├── top_tc_dac.sv │ │ └── top_tc_gpio.sv ├── tft │ ├── dts │ │ ├── fpga.dts │ │ └── pl_patch.dtsi │ ├── ip │ │ ├── systemZ10.tcl │ │ └── systemZ20.tcl │ ├── rtl │ │ ├── red_pitaya_ps.sv │ │ ├── red_pitaya_top.sv │ │ └── red_pitaya_top_Z20.sv │ └── sdc │ │ └── red_pitaya.xdc ├── v0.94 │ ├── dts │ │ ├── fpga.dts │ │ ├── fpga.dtso │ │ └── pl_patch.dtsi │ ├── ip │ │ ├── systemZ10.tcl │ │ ├── systemZ20.tcl │ │ ├── systemZ20_14.tcl │ │ └── systemZ20_G2.tcl │ ├── rtl │ │ ├── osc_calib.v │ │ ├── osc_filter.v │ │ ├── red_pitaya_ps.sv │ │ ├── red_pitaya_top.sv │ │ ├── red_pitaya_top_4ADC.sv │ │ ├── red_pitaya_top_Z20.sv │ │ ├── red_pitaya_top_ll.sv │ │ └── tb_red_pitaya_scope.sv │ ├── sdc │ │ ├── red_pitaya.xdc │ │ ├── red_pitaya_4ADC.xdc │ │ ├── red_pitaya_4adc_test.xdc │ │ └── red_pitaya_G2.xdc │ └── tbn │ │ └── .gitkeep ├── v0.94_250 │ ├── dts │ │ ├── fpga.dts │ │ ├── fpga.dtso │ │ └── pl_patch.dtsi │ ├── ip │ │ ├── systemZ10.tcl │ │ └── systemZ20.tcl │ ├── rtl_250 │ │ ├── red_pitaya_ps.sv │ │ └── red_pitaya_top.sv │ ├── sdc │ │ └── red_pitaya.xdc │ └── tbn │ │ ├── red_pitaya_ps_sim.sv │ │ ├── red_pitaya_top_sim.sv │ │ ├── sim_script.tcl │ │ ├── system.sv │ │ ├── top_tb.sv │ │ └── top_tc.sv └── v0.94_ll │ ├── dts │ ├── fpga.dts │ ├── fpga.dtso │ └── pl_patch.dtsi │ ├── ip │ ├── disable_qspi_v0.94.diff │ ├── systemZ10.tcl │ ├── systemZ20.tcl │ └── systemZ20_ll.tcl │ ├── rtl │ ├── osc_filter.v │ ├── red_pitaya_ps.sv │ └── red_pitaya_top.sv │ ├── sdc │ └── red_pitaya.xdc │ └── tbn │ ├── model_ad366x.sv │ ├── system.sv │ ├── top_tb.sv │ └── top_tc.sv ├── red_pitaya_average_filter_Z10.tcl ├── red_pitaya_hsi_dts.tcl ├── red_pitaya_hsi_fsbl.tcl ├── red_pitaya_vivado_Z10.tcl ├── red_pitaya_vivado_Z10_4_test.tcl ├── red_pitaya_vivado_Z20.tcl ├── red_pitaya_vivado_Z20_14.tcl ├── red_pitaya_vivado_Z20_250.tcl ├── red_pitaya_vivado_Z20_4.tcl ├── red_pitaya_vivado_Z20_G2.tcl ├── red_pitaya_vivado_Z20_ll.tcl ├── red_pitaya_vivado_project_Z10.tcl ├── red_pitaya_vivado_project_Z20.tcl ├── red_pitaya_vivado_project_Z20_14.tcl ├── red_pitaya_vivado_project_Z20_250.tcl ├── red_pitaya_vivado_project_Z20_4.tcl ├── red_pitaya_vivado_project_Z20_G2.tcl ├── red_pitaya_vivado_project_Z20_ll.tcl ├── red_pitaya_vivado_sim.tcl ├── rtl ├── acq.sv ├── adc366x_top.sv ├── asg.sv ├── asg_bst.sv ├── asg_per.sv ├── axi4_lite_slave.v ├── axi4_slave.sv ├── axi4_stream_cnt.sv ├── axi4_stream_demux.sv ├── axi4_stream_dly.sv ├── axi4_stream_mux.sv ├── axi4_stream_pas.sv ├── axi4_stream_reg.sv ├── bin_and.sv ├── classic │ ├── axi_master.v │ ├── axi_rd_burst.sv │ ├── axi_rd_fifo.v │ ├── axi_rd_single.sv │ ├── axi_wr_fifo.v │ ├── red_pitaya_ams.v │ ├── red_pitaya_asg.sv │ ├── red_pitaya_asg_ch.sv │ ├── red_pitaya_daisy.v │ ├── red_pitaya_daisy_rx.v │ ├── red_pitaya_daisy_test.v │ ├── red_pitaya_daisy_tx.v │ ├── red_pitaya_hk.v │ ├── red_pitaya_hk_4adc.v │ ├── red_pitaya_hk_ll.v │ ├── red_pitaya_id.v │ ├── red_pitaya_pdm.sv │ ├── red_pitaya_pid.v │ ├── red_pitaya_pid_block.v │ ├── red_pitaya_pwm.sv │ ├── red_pitaya_scope.v │ ├── red_pitaya_scope_Z20.v │ ├── rp_acq_bram.v │ ├── rp_adc_trig.v │ ├── rp_asg_axi.sv │ ├── rp_axi_sm.v │ ├── rp_bram_sm.v │ ├── rp_decim.v │ ├── rp_delay.v │ ├── rp_ext_trig.v │ ├── rp_scope_calib.v │ ├── rp_scope_cfg.v │ ├── rp_scope_com.v │ └── rp_trig_src.v ├── clb.sv ├── clkdiv.sv ├── ctrg.sv ├── cts.sv ├── debounce.sv ├── divide.v ├── drp_ctrl.sv ├── evn_pkg.sv ├── freq_meter.sv ├── gen.sv ├── id.rst ├── id.sv ├── interface │ ├── axi4_if.sv │ ├── axi4_lite_if.sv │ ├── axi4_stream_if.sv │ ├── axi_sys_if.sv │ ├── gpio_if.sv │ ├── spi_if.sv │ └── sys_bus_if.sv ├── la.sv ├── la_trg.sv ├── lg.sv ├── lin_add.sv ├── lin_mul.sv ├── mgmt.sv ├── muxctl.sv ├── old_acq.sv ├── old_asg.sv ├── old_asg_top.sv ├── old_id.sv ├── old_la_top.sv ├── osc.sv ├── osc_trg.sv ├── pdm.sv ├── pid.sv ├── pid_block.sv ├── pwm.sv ├── rand_lfsr.v ├── red_pitaya_dfilt1.sv ├── red_pitaya_pll.sv ├── red_pitaya_pll_4adc.sv ├── red_pitaya_pll_ll.sv ├── rle.sv ├── scope_dec_avg.sv ├── scope_filter.sv ├── spi_master.v ├── str2mm.sv ├── str_dec.sv ├── sync.v ├── sync_rw_single.v ├── sys_bus_cdc.sv ├── sys_bus_interconnect.sv ├── sys_bus_stub.sv ├── sys_bus_sync.sv └── sys_reg_array_o.sv ├── rtl_250 ├── acq.sv ├── asg.sv ├── asg_bst.sv ├── asg_per.sv ├── axi4_lite_slave.v ├── axi4_slave.sv ├── axi4_stream_cnt.sv ├── axi4_stream_demux.sv ├── axi4_stream_dly.sv ├── axi4_stream_mux.sv ├── axi4_stream_pas.sv ├── axi4_stream_reg.sv ├── bin_and.sv ├── classic │ ├── axi_master.v │ ├── axi_rd_burst.sv │ ├── axi_rd_single.sv │ ├── axi_wr_fifo.v │ ├── red_pitaya_ams.v │ ├── red_pitaya_asg.sv │ ├── red_pitaya_asg_ch.sv │ ├── red_pitaya_daisy.v │ ├── red_pitaya_daisy_rx.v │ ├── red_pitaya_daisy_test.v │ ├── red_pitaya_daisy_tx.v │ ├── red_pitaya_hk.v │ ├── red_pitaya_id.v │ ├── red_pitaya_pdm.sv │ ├── red_pitaya_pid.v │ ├── red_pitaya_pid_block.v │ ├── red_pitaya_pwm.sv │ ├── red_pitaya_scope.v │ ├── rp_acq_bram.v │ ├── rp_adc_trig.v │ ├── rp_asg_axi.sv │ ├── rp_axi_sm.v │ ├── rp_bram_sm.v │ ├── rp_decim.v │ ├── rp_delay.v │ ├── rp_ext_trig.v │ ├── rp_scope_calib.v │ ├── rp_scope_cfg.v │ ├── rp_scope_com.v │ └── rp_trig_src.v ├── clb.sv ├── clkdiv.sv ├── ctrg.sv ├── cts.sv ├── debounce.sv ├── divide.v ├── drp_ctrl.sv ├── evn_pkg.sv ├── freq_meter.sv ├── gen.sv ├── id.rst ├── id.sv ├── interface │ ├── axi4_if.sv │ ├── axi4_lite_if.sv │ ├── axi4_stream_if.sv │ ├── axi_sys_if.sv │ ├── gpio_if.sv │ ├── spi_if.sv │ └── sys_bus_if.sv ├── la.sv ├── la_trg.sv ├── lg.sv ├── lin_add.sv ├── lin_mul.sv ├── mgmt.sv ├── muxctl.sv ├── old_acq.sv ├── old_asg.sv ├── old_asg_top.sv ├── old_id.sv ├── old_la_top.sv ├── osc.sv ├── osc_trg.sv ├── pdm.sv ├── pid.sv ├── pid_block.sv ├── pwm.sv ├── rand_lfsr.v ├── red_pitaya_dfilt1.sv ├── red_pitaya_pll.sv ├── rle.sv ├── scope_dec_avg.sv ├── scope_filter.sv ├── spi_master.v ├── str2mm.sv ├── str_dec.sv ├── sync.v ├── sys_bus_cdc.sv ├── sys_bus_interconnect.sv ├── sys_bus_stub.sv └── sys_reg_array_o.sv ├── sdc ├── red_pitaya.xdc └── red_pitaya_Z20.xdc ├── sdc_250 ├── red_pitaya.xdc └── red_pitaya_v1r0.xdc ├── sdc_ll └── red_pitaya.xdc ├── src └── scope_filter │ ├── RP_DFILT_1.m │ ├── Untitled.ipynb │ └── acq10kA.txt ├── synCheck.sh ├── tbn ├── README ├── acq_tb.sv ├── adc_driver.sv ├── asg_tb.sv ├── axi4_lite_master.sv ├── axi4_slave_tb.sv ├── axi4_stream_cnt_tb.sv ├── axi4_stream_drn.sv ├── axi4_stream_pkg.sv ├── axi4_stream_src.sv ├── axi4_sync.sv ├── axi_bus_model.sv ├── axi_master_model.sv ├── axi_prot_check │ └── axi_prot_check.xci ├── axi_slave_model.v ├── clk_gen.v ├── create_driver_files.m ├── ctrg_tb.sv ├── dac_driver.sv ├── debounce_tb.sv ├── gen_tb.sv ├── glbl.v ├── gpio_tb.sv ├── id_tb.sv ├── la_trg_tb.sv ├── lin_add_tb.sv ├── model_ad366x.sv ├── monitor_tcs_094.sv ├── monitor_tcs_strm.sv ├── osc_trg_tb.sv ├── pll_tbn.sv ├── ps_model │ ├── component.xml │ └── xgui │ │ └── system_model_v1_0.tcl ├── pwm_tb.sv ├── red_pitaya_daisy_tb.sv ├── red_pitaya_pid_tb.sv ├── red_pitaya_pll_tb.sv ├── rle_tb.sv ├── scope_dec_avg_tb.sv ├── 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