├── README.md ├── datapath_pipeline.png ├── datapath_single.png ├── pipeline ├── pipeline.cache │ ├── ip │ │ └── 2019.2 │ │ │ ├── ac4765ccab3a8c3a │ │ │ ├── ac4765ccab3a8c3a.xci │ │ │ ├── data_mem.dcp │ │ │ ├── data_mem_sim_netlist.v │ │ │ ├── data_mem_sim_netlist.vhdl │ │ │ ├── data_mem_stub.v │ │ │ └── data_mem_stub.vhdl │ │ │ ├── ce28ec6061e64c3c │ │ │ ├── ce28ec6061e64c3c.xci │ │ │ ├── inst_mem.dcp │ │ │ ├── inst_mem_sim_netlist.v │ │ │ ├── inst_mem_sim_netlist.vhdl │ │ │ ├── inst_mem_stub.v │ │ │ └── inst_mem_stub.vhdl │ │ │ └── e97bb78a59256adc │ │ │ ├── cpuclk.dcp │ │ │ ├── cpuclk_sim_netlist.v │ │ │ ├── cpuclk_sim_netlist.vhdl │ │ │ ├── cpuclk_stub.v │ │ │ ├── cpuclk_stub.vhdl │ │ │ └── e97bb78a59256adc.xci │ └── wt │ │ ├── gui_handlers.wdf │ │ ├── java_command_handlers.wdf │ │ ├── project.wpc │ │ ├── synthesis.wdf │ │ └── webtalk_pa.xml ├── pipeline.hw │ └── pipeline.lpr ├── pipeline.ip_user_files │ ├── README.txt │ ├── ip │ │ ├── cpuclk │ │ │ ├── cpuclk.veo │ │ │ ├── cpuclk_stub.v │ │ │ └── cpuclk_stub.vhdl │ │ ├── data_mem │ │ │ ├── data_mem.veo │ │ │ ├── data_mem.vho │ │ │ ├── data_mem_stub.v │ │ │ └── data_mem_stub.vhdl │ │ └── inst_mem │ │ │ ├── inst_mem.veo │ │ │ ├── inst_mem.vho │ │ │ ├── inst_mem_stub.v │ │ │ └── inst_mem_stub.vhdl │ ├── ipstatic │ │ └── simulation │ │ │ └── dist_mem_gen_v8_0.v │ └── sim_scripts │ │ ├── cpuclk │ │ ├── README.txt │ │ ├── activehdl │ │ │ ├── README.txt │ │ │ ├── compile.do │ │ │ ├── cpuclk.sh │ │ │ ├── cpuclk.udo │ │ │ ├── file_info.txt │ │ │ ├── glbl.v │ │ │ ├── simulate.do │ │ │ └── wave.do │ │ ├── ies │ │ │ ├── README.txt │ │ │ ├── cpuclk.sh │ │ │ ├── file_info.txt │ │ │ ├── glbl.v │ │ │ └── run.f │ │ ├── modelsim │ │ │ ├── README.txt │ │ │ ├── compile.do │ │ │ ├── cpuclk.sh │ │ │ ├── cpuclk.udo │ │ │ ├── file_info.txt │ │ │ ├── glbl.v │ │ │ ├── simulate.do │ │ │ └── wave.do │ │ ├── questa │ │ │ ├── README.txt │ │ │ ├── compile.do │ │ │ ├── cpuclk.sh │ │ │ ├── cpuclk.udo │ │ │ ├── elaborate.do │ │ │ ├── file_info.txt │ │ │ ├── glbl.v │ │ │ ├── simulate.do │ │ │ └── wave.do │ │ ├── riviera │ │ │ ├── README.txt │ │ │ ├── compile.do │ │ │ ├── cpuclk.sh │ │ │ ├── cpuclk.udo │ │ │ ├── file_info.txt │ │ │ ├── glbl.v │ │ │ ├── simulate.do │ │ │ └── wave.do │ │ ├── vcs │ │ │ ├── README.txt │ │ │ ├── cpuclk.sh │ │ │ ├── file_info.txt │ │ │ ├── glbl.v │ │ │ └── simulate.do │ │ ├── xcelium │ │ │ ├── README.txt │ │ │ ├── cpuclk.sh │ │ │ ├── file_info.txt │ │ │ ├── glbl.v │ │ │ └── run.f │ │ └── xsim │ │ │ ├── README.txt │ │ │ ├── cmd.tcl │ │ │ ├── cpuclk.sh │ │ │ ├── elab.opt │ │ │ ├── file_info.txt │ │ │ ├── glbl.v │ │ │ ├── vlog.prj │ │ │ └── xsim.ini │ │ ├── data_mem │ │ ├── README.txt │ │ ├── activehdl │ │ │ ├── README.txt │ │ │ ├── compile.do │ │ │ ├── data_mem.sh │ │ │ ├── data_mem.udo │ │ │ ├── file_info.txt │ │ │ ├── glbl.v │ │ │ ├── simulate.do │ │ │ └── wave.do │ │ ├── ies │ │ │ ├── README.txt │ │ │ ├── data_mem.sh │ │ │ ├── file_info.txt │ │ │ ├── glbl.v │ │ │ └── run.f │ │ ├── modelsim │ │ │ ├── README.txt │ │ │ ├── compile.do │ │ │ ├── data_mem.sh │ │ │ ├── data_mem.udo │ │ │ ├── file_info.txt │ │ │ ├── glbl.v │ │ │ ├── simulate.do │ │ │ └── wave.do │ │ ├── questa │ │ │ ├── README.txt │ │ │ ├── compile.do │ │ │ ├── data_mem.sh │ │ │ ├── data_mem.udo │ │ │ ├── elaborate.do │ │ │ ├── file_info.txt │ │ │ ├── glbl.v │ │ │ ├── simulate.do │ │ │ └── wave.do │ │ ├── riviera │ │ │ ├── README.txt │ │ │ ├── compile.do │ │ │ ├── data_mem.sh │ │ │ ├── data_mem.udo │ │ │ ├── file_info.txt │ │ │ ├── glbl.v │ │ │ ├── simulate.do │ │ │ └── wave.do │ │ ├── vcs │ │ │ ├── README.txt │ │ │ ├── data_mem.sh │ │ │ ├── file_info.txt │ │ │ ├── glbl.v │ │ │ └── simulate.do │ │ ├── xcelium │ │ │ ├── README.txt │ │ │ ├── data_mem.sh │ │ │ ├── file_info.txt │ │ │ ├── glbl.v │ │ │ └── run.f │ │ └── xsim │ │ │ ├── README.txt │ │ │ ├── cmd.tcl │ │ │ ├── data_mem.sh │ │ │ ├── elab.opt │ │ │ ├── file_info.txt │ │ │ ├── glbl.v │ │ │ ├── vlog.prj │ │ │ └── xsim.ini │ │ └── inst_mem │ │ ├── README.txt │ │ ├── activehdl │ │ ├── README.txt │ │ ├── compile.do │ │ ├── file_info.txt │ │ ├── glbl.v │ │ ├── inst_mem.sh │ │ ├── inst_mem.udo │ │ ├── simulate.do │ │ └── wave.do │ │ ├── ies │ │ ├── README.txt │ │ ├── file_info.txt │ │ ├── glbl.v │ │ ├── inst_mem.sh │ │ └── run.f │ │ ├── modelsim │ │ ├── README.txt │ │ ├── compile.do │ │ ├── file_info.txt │ │ ├── glbl.v │ │ ├── inst_mem.sh │ │ ├── inst_mem.udo │ │ ├── simulate.do │ │ └── wave.do │ │ ├── questa │ │ ├── README.txt │ │ ├── compile.do │ │ ├── elaborate.do │ │ ├── file_info.txt │ │ ├── glbl.v │ │ ├── inst_mem.sh │ │ ├── inst_mem.udo │ │ ├── simulate.do │ │ └── wave.do │ │ ├── riviera │ │ ├── README.txt │ │ ├── compile.do │ │ ├── file_info.txt │ │ ├── glbl.v │ │ ├── inst_mem.sh │ │ ├── inst_mem.udo │ │ ├── simulate.do │ │ └── wave.do │ │ ├── vcs │ │ ├── README.txt │ │ ├── file_info.txt │ │ ├── glbl.v │ │ ├── inst_mem.sh │ │ └── simulate.do │ │ ├── xcelium │ │ ├── README.txt │ │ ├── file_info.txt │ │ ├── glbl.v │ │ ├── inst_mem.sh │ │ └── run.f │ │ └── xsim │ │ ├── README.txt │ │ ├── cmd.tcl │ │ ├── elab.opt │ │ ├── file_info.txt │ │ ├── glbl.v │ │ ├── inst_mem.sh │ │ ├── vlog.prj │ │ └── xsim.ini ├── pipeline.runs │ ├── .jobs │ │ ├── vrs_config_1.xml │ │ ├── vrs_config_2.xml │ │ └── vrs_config_3.xml │ ├── cpuclk_synth_1 │ │ ├── .Vivado_Synthesis.queue.rst │ │ ├── .Xil │ │ │ └── cpuclk_propImpl.xdc │ │ ├── .vivado.begin.rst │ │ ├── .vivado.end.rst │ │ ├── ISEWrap.js │ │ ├── ISEWrap.sh │ │ ├── __synthesis_is_complete__ │ │ ├── cpuclk.dcp │ │ ├── cpuclk.tcl │ │ ├── cpuclk.vds │ │ ├── cpuclk_utilization_synth.pb │ │ ├── cpuclk_utilization_synth.rpt │ │ ├── dont_touch.xdc │ │ ├── gen_run.xml │ │ ├── htr.txt │ │ ├── project.wdf │ │ ├── rundef.js │ │ ├── runme.bat │ │ ├── runme.log │ │ ├── runme.sh │ │ ├── vivado.jou │ │ └── vivado.pb │ ├── data_mem_synth_1 │ │ ├── .Vivado_Synthesis.queue.rst │ │ ├── .vivado.begin.rst │ │ ├── .vivado.end.rst │ │ ├── ISEWrap.js │ │ ├── ISEWrap.sh │ │ ├── __synthesis_is_complete__ │ │ ├── data_mem.dcp │ │ ├── data_mem.tcl │ │ ├── data_mem.vds │ │ ├── data_mem_utilization_synth.pb │ │ ├── data_mem_utilization_synth.rpt │ │ ├── dont_touch.xdc │ │ ├── gen_run.xml │ │ ├── htr.txt │ │ ├── project.wdf │ │ ├── rundef.js │ │ ├── runme.bat │ │ ├── runme.log │ │ ├── runme.sh │ │ ├── vivado.jou │ │ └── vivado.pb │ └── inst_mem_synth_1 │ │ ├── .Vivado_Synthesis.queue.rst │ │ ├── .vivado.begin.rst │ │ ├── .vivado.end.rst │ │ ├── ISEWrap.js │ │ ├── ISEWrap.sh │ │ ├── __synthesis_is_complete__ │ │ ├── dont_touch.xdc │ │ ├── gen_run.xml │ │ ├── htr.txt │ │ ├── inst_mem.dcp │ │ ├── inst_mem.tcl │ │ ├── inst_mem.vds │ │ ├── inst_mem_utilization_synth.pb │ │ ├── inst_mem_utilization_synth.rpt │ │ ├── project.wdf │ │ ├── rundef.js │ │ ├── runme.bat │ │ ├── runme.log │ │ ├── runme.sh │ │ ├── vivado.jou │ │ └── vivado.pb ├── pipeline.srcs │ └── sources_1 │ │ ├── imports │ │ └── pipeline │ │ │ ├── adder_for_plus_4.v │ │ │ ├── algorithm_calculation.v │ │ │ ├── algorithm_logic_unit.v │ │ │ ├── branch_compare.v │ │ │ ├── branch_reg_select.v │ │ │ ├── control_hazard.v │ │ │ ├── control_unit.v │ │ │ ├── forwarding_unit.v │ │ │ ├── hazard_detection_unit.v │ │ │ ├── j_format_stall.v │ │ │ ├── lb_lh_unit.v │ │ │ ├── logic_calculation.v │ │ │ ├── mini_rv.v │ │ │ ├── mux_3.v │ │ │ ├── mux_5.v │ │ │ ├── mux_6.v │ │ │ ├── mux_7.v │ │ │ ├── param.v │ │ │ ├── pipeline_reg0.v │ │ │ ├── pipeline_reg1.v │ │ │ ├── pipeline_reg2.v │ │ │ ├── pipeline_reg3.v │ │ │ ├── program_counter.v │ │ │ ├── reg_file.v │ │ │ ├── reg_for_inst_before_LW.v │ │ │ ├── shift.v │ │ │ ├── sign_extention.v │ │ │ ├── sl_sh_unit.v │ │ │ ├── top.v │ │ │ └── wb_value_recorder.v │ │ └── ip │ │ ├── cpuclk │ │ ├── cpuclk.dcp │ │ ├── cpuclk.v │ │ ├── cpuclk.veo │ │ ├── cpuclk.xci │ │ ├── cpuclk.xdc │ │ ├── cpuclk.xml │ │ ├── cpuclk_board.xdc │ │ ├── cpuclk_clk_wiz.v │ │ ├── cpuclk_ooc.xdc │ │ ├── cpuclk_sim_netlist.v │ │ ├── cpuclk_sim_netlist.vhdl │ │ ├── cpuclk_stub.v │ │ ├── cpuclk_stub.vhdl │ │ ├── doc │ │ │ └── clk_wiz_v6_0_changelog.txt │ │ ├── mmcm_pll_drp_func_7s_mmcm.vh │ │ ├── mmcm_pll_drp_func_7s_pll.vh │ │ ├── mmcm_pll_drp_func_us_mmcm.vh │ │ ├── mmcm_pll_drp_func_us_pll.vh │ │ ├── mmcm_pll_drp_func_us_plus_mmcm.vh │ │ └── mmcm_pll_drp_func_us_plus_pll.vh │ │ ├── data_mem │ │ ├── data_mem.dcp │ │ ├── data_mem.veo │ │ ├── data_mem.vho │ │ ├── data_mem.xci │ │ ├── data_mem.xml │ │ ├── data_mem_ooc.xdc │ │ ├── data_mem_sim_netlist.v │ │ ├── data_mem_sim_netlist.vhdl │ │ ├── data_mem_stub.v │ │ ├── data_mem_stub.vhdl │ │ ├── doc │ │ │ └── dist_mem_gen_v8_0_changelog.txt │ │ ├── hdl │ │ │ └── dist_mem_gen_v8_0_vhsyn_rfs.vhd │ │ ├── sim │ │ │ └── data_mem.v │ │ ├── simulation │ │ │ └── dist_mem_gen_v8_0.v │ │ └── synth │ │ │ └── data_mem.vhd │ │ └── inst_mem │ │ ├── doc │ │ └── dist_mem_gen_v8_0_changelog.txt │ │ ├── hdl │ │ └── dist_mem_gen_v8_0_vhsyn_rfs.vhd │ │ ├── inst_mem.dcp │ │ ├── inst_mem.veo │ │ ├── inst_mem.vho │ │ ├── inst_mem.xci │ │ ├── inst_mem.xml │ │ ├── inst_mem_ooc.xdc │ │ ├── inst_mem_sim_netlist.v │ │ ├── inst_mem_sim_netlist.vhdl │ │ ├── inst_mem_stub.v │ │ ├── inst_mem_stub.vhdl │ │ ├── sim │ │ └── inst_mem.v │ │ ├── simulation │ │ └── dist_mem_gen_v8_0.v │ │ └── synth │ │ └── inst_mem.vhd └── pipeline.xpr └── single ├── single.cache ├── ip │ └── 2019.2 │ │ ├── ac4765ccab3a8c3a │ │ ├── ac4765ccab3a8c3a.xci │ │ ├── data_mem.dcp │ │ ├── data_mem_sim_netlist.v │ │ ├── data_mem_sim_netlist.vhdl │ │ ├── data_mem_stub.v │ │ └── data_mem_stub.vhdl │ │ ├── b7219d93de4be123 │ │ ├── b7219d93de4be123.xci │ │ ├── cpuclk.dcp │ │ ├── cpuclk_sim_netlist.v │ │ ├── cpuclk_sim_netlist.vhdl │ │ ├── cpuclk_stub.v │ │ └── cpuclk_stub.vhdl │ │ └── ce28ec6061e64c3c │ │ ├── ce28ec6061e64c3c.xci │ │ ├── inst_mem.dcp │ │ ├── inst_mem_sim_netlist.v │ │ ├── inst_mem_sim_netlist.vhdl │ │ ├── inst_mem_stub.v │ │ └── inst_mem_stub.vhdl └── wt │ ├── gui_handlers.wdf │ ├── java_command_handlers.wdf │ ├── project.wpc │ ├── synthesis.wdf │ └── webtalk_pa.xml ├── single.hw └── single.lpr ├── single.ip_user_files ├── README.txt ├── ip │ ├── cpuclk │ │ ├── cpuclk.veo │ │ ├── cpuclk_stub.v │ │ └── cpuclk_stub.vhdl │ ├── data_mem │ │ ├── data_mem.veo │ │ ├── data_mem.vho │ │ ├── data_mem_stub.v │ │ └── data_mem_stub.vhdl │ └── inst_mem │ │ ├── inst_mem.veo │ │ ├── inst_mem.vho │ │ ├── inst_mem_stub.v │ │ └── inst_mem_stub.vhdl ├── ipstatic │ └── simulation │ │ └── dist_mem_gen_v8_0.v └── sim_scripts │ ├── cpuclk │ ├── README.txt │ ├── activehdl │ │ ├── README.txt │ │ ├── compile.do │ │ ├── cpuclk.sh │ │ ├── cpuclk.udo │ │ ├── file_info.txt │ │ ├── glbl.v │ │ ├── simulate.do │ │ └── wave.do │ ├── ies │ │ ├── README.txt │ │ ├── cpuclk.sh │ │ ├── file_info.txt │ │ ├── glbl.v │ │ └── run.f │ ├── modelsim │ │ ├── README.txt │ │ ├── compile.do │ │ ├── cpuclk.sh │ │ ├── cpuclk.udo │ │ ├── file_info.txt │ │ ├── glbl.v │ │ ├── simulate.do │ │ └── wave.do │ ├── questa │ │ ├── README.txt │ │ ├── compile.do │ │ ├── cpuclk.sh │ │ ├── cpuclk.udo │ │ ├── elaborate.do │ │ ├── file_info.txt │ │ ├── glbl.v │ │ ├── simulate.do │ │ └── wave.do │ ├── riviera │ │ ├── README.txt │ │ ├── compile.do │ │ ├── cpuclk.sh │ │ ├── cpuclk.udo │ │ ├── file_info.txt │ │ ├── glbl.v │ │ ├── simulate.do │ │ └── wave.do │ ├── vcs │ │ ├── README.txt │ │ ├── cpuclk.sh │ │ ├── file_info.txt │ │ ├── glbl.v │ │ └── simulate.do │ ├── xcelium │ │ ├── README.txt │ │ ├── cpuclk.sh │ │ ├── file_info.txt │ │ ├── glbl.v │ │ └── run.f │ └── xsim │ │ ├── README.txt │ │ ├── cmd.tcl │ │ ├── cpuclk.sh │ │ ├── elab.opt │ │ ├── file_info.txt │ │ ├── glbl.v │ │ ├── vlog.prj │ │ └── xsim.ini │ ├── data_mem │ ├── README.txt │ ├── activehdl │ │ ├── README.txt │ │ ├── compile.do │ │ ├── data_mem.sh │ │ ├── data_mem.udo │ │ ├── file_info.txt │ │ ├── glbl.v │ │ ├── simulate.do │ │ └── wave.do │ ├── ies │ │ ├── README.txt │ │ ├── data_mem.sh │ │ ├── file_info.txt │ │ ├── glbl.v │ │ └── run.f │ ├── modelsim │ │ ├── README.txt │ │ ├── compile.do │ │ ├── data_mem.sh │ │ ├── data_mem.udo │ │ ├── file_info.txt │ │ ├── glbl.v │ │ ├── simulate.do │ │ └── wave.do │ ├── questa │ │ ├── README.txt │ │ ├── compile.do │ │ ├── data_mem.sh │ │ ├── data_mem.udo │ │ ├── elaborate.do │ │ ├── file_info.txt │ │ ├── glbl.v │ │ ├── simulate.do │ │ └── wave.do │ ├── riviera │ │ ├── README.txt │ │ ├── compile.do │ │ ├── data_mem.sh │ │ ├── data_mem.udo │ │ ├── file_info.txt │ │ ├── glbl.v │ │ ├── simulate.do │ │ └── wave.do │ ├── vcs │ │ ├── README.txt │ │ ├── data_mem.sh │ │ ├── file_info.txt │ │ ├── glbl.v │ │ └── simulate.do │ ├── xcelium │ │ ├── README.txt │ │ ├── data_mem.sh │ │ ├── file_info.txt │ │ ├── glbl.v │ │ └── run.f │ └── xsim │ │ ├── README.txt │ │ ├── cmd.tcl │ │ ├── data_mem.sh │ │ ├── elab.opt │ │ ├── file_info.txt │ │ ├── glbl.v │ │ ├── vlog.prj │ │ └── xsim.ini │ └── inst_mem │ ├── README.txt │ ├── activehdl │ ├── README.txt │ ├── compile.do │ ├── file_info.txt │ ├── glbl.v │ ├── inst_mem.sh │ ├── inst_mem.udo │ ├── simulate.do │ └── wave.do │ ├── ies │ ├── README.txt │ ├── file_info.txt │ ├── glbl.v │ ├── inst_mem.sh │ └── run.f │ ├── modelsim │ ├── README.txt │ ├── compile.do │ ├── file_info.txt │ ├── glbl.v │ ├── inst_mem.sh │ ├── inst_mem.udo │ ├── simulate.do │ └── wave.do │ ├── questa │ ├── README.txt │ ├── compile.do │ ├── elaborate.do │ ├── file_info.txt │ ├── glbl.v │ ├── inst_mem.sh │ ├── inst_mem.udo │ ├── simulate.do │ └── wave.do │ ├── riviera │ ├── README.txt │ ├── compile.do │ ├── file_info.txt │ ├── glbl.v │ ├── inst_mem.sh │ ├── inst_mem.udo │ ├── simulate.do │ └── wave.do │ ├── vcs │ ├── README.txt │ ├── file_info.txt │ ├── glbl.v │ ├── inst_mem.sh │ └── simulate.do │ ├── xcelium │ ├── README.txt │ ├── file_info.txt │ ├── glbl.v │ ├── inst_mem.sh │ └── run.f │ └── xsim │ ├── README.txt │ ├── cmd.tcl │ ├── elab.opt │ ├── file_info.txt │ ├── glbl.v │ ├── inst_mem.sh │ ├── vlog.prj │ └── xsim.ini ├── single.runs ├── .jobs │ ├── vrs_config_1.xml │ ├── vrs_config_2.xml │ └── vrs_config_3.xml ├── cpuclk_synth_1 │ ├── .Vivado_Synthesis.queue.rst │ ├── .Xil │ │ └── cpuclk_propImpl.xdc │ ├── .vivado.begin.rst │ ├── .vivado.end.rst │ ├── ISEWrap.js │ ├── ISEWrap.sh │ ├── __synthesis_is_complete__ │ ├── cpuclk.dcp │ ├── cpuclk.tcl │ ├── cpuclk.vds │ ├── cpuclk_utilization_synth.pb │ ├── cpuclk_utilization_synth.rpt │ ├── dont_touch.xdc │ ├── gen_run.xml │ ├── htr.txt │ ├── project.wdf │ ├── rundef.js │ ├── runme.bat │ ├── runme.log │ ├── runme.sh │ ├── vivado.jou │ └── vivado.pb ├── data_mem_synth_1 │ ├── .Vivado_Synthesis.queue.rst │ ├── .vivado.begin.rst │ ├── .vivado.end.rst │ ├── ISEWrap.js │ ├── ISEWrap.sh │ ├── __synthesis_is_complete__ │ ├── data_mem.dcp │ ├── data_mem.tcl │ ├── data_mem.vds │ ├── data_mem_utilization_synth.pb │ ├── data_mem_utilization_synth.rpt │ ├── dont_touch.xdc │ ├── gen_run.xml │ ├── htr.txt │ ├── project.wdf │ ├── rundef.js │ ├── runme.bat │ ├── runme.log │ ├── runme.sh │ ├── vivado.jou │ └── vivado.pb └── inst_mem_synth_1 │ ├── .Vivado_Synthesis.queue.rst │ ├── .vivado.begin.rst │ ├── .vivado.end.rst │ ├── ISEWrap.js │ ├── ISEWrap.sh │ ├── __synthesis_is_complete__ │ ├── dont_touch.xdc │ ├── gen_run.xml │ ├── htr.txt │ ├── inst_mem.dcp │ ├── inst_mem.tcl │ ├── inst_mem.vds │ ├── inst_mem_utilization_synth.pb │ ├── inst_mem_utilization_synth.rpt │ ├── project.wdf │ ├── rundef.js │ ├── runme.bat │ ├── runme.log │ ├── runme.sh │ ├── vivado.jou │ └── vivado.pb ├── single.srcs └── sources_1 │ ├── imports │ └── single_cycle │ │ ├── adder_for_plus_4.v │ │ ├── algorithm_calculation.v │ │ ├── algorithm_logic_unit.v │ │ ├── branch_compare.v │ │ ├── control_unit.v │ │ ├── lb_lh_unit.v │ │ ├── logic_calculation.v │ │ ├── mux_2.v │ │ ├── mux_4.v │ │ ├── param.v │ │ ├── program_counter.v │ │ ├── reg_file.v │ │ ├── shift.v │ │ ├── sign_extention.v │ │ ├── sl_sh_unit.v │ │ └── top.v │ └── ip │ ├── cpuclk │ ├── cpuclk.dcp │ ├── cpuclk.v │ ├── cpuclk.veo │ ├── cpuclk.xci │ ├── cpuclk.xdc │ ├── cpuclk.xml │ ├── cpuclk_board.xdc │ ├── cpuclk_clk_wiz.v │ ├── cpuclk_ooc.xdc │ ├── cpuclk_sim_netlist.v │ ├── cpuclk_sim_netlist.vhdl │ ├── cpuclk_stub.v │ ├── cpuclk_stub.vhdl │ ├── doc │ │ └── clk_wiz_v6_0_changelog.txt │ ├── mmcm_pll_drp_func_7s_mmcm.vh │ ├── mmcm_pll_drp_func_7s_pll.vh │ ├── mmcm_pll_drp_func_us_mmcm.vh │ ├── mmcm_pll_drp_func_us_pll.vh │ ├── mmcm_pll_drp_func_us_plus_mmcm.vh │ └── mmcm_pll_drp_func_us_plus_pll.vh │ ├── data_mem │ ├── data_mem.dcp │ ├── data_mem.veo │ ├── data_mem.vho │ ├── data_mem.xci │ ├── data_mem.xml │ ├── data_mem_ooc.xdc │ ├── data_mem_sim_netlist.v │ ├── data_mem_sim_netlist.vhdl │ ├── data_mem_stub.v │ ├── data_mem_stub.vhdl │ ├── doc │ │ └── dist_mem_gen_v8_0_changelog.txt │ ├── hdl │ │ └── dist_mem_gen_v8_0_vhsyn_rfs.vhd │ ├── sim │ │ └── data_mem.v │ ├── simulation │ │ └── dist_mem_gen_v8_0.v │ └── synth │ │ └── data_mem.vhd │ └── inst_mem │ ├── doc │ └── dist_mem_gen_v8_0_changelog.txt │ ├── hdl │ └── dist_mem_gen_v8_0_vhsyn_rfs.vhd │ ├── inst_mem.dcp │ ├── inst_mem.veo │ ├── inst_mem.vho │ ├── inst_mem.xci │ ├── inst_mem.xml │ ├── inst_mem_ooc.xdc │ ├── inst_mem_sim_netlist.v │ ├── inst_mem_sim_netlist.vhdl │ ├── inst_mem_stub.v │ ├── inst_mem_stub.vhdl │ ├── sim │ └── inst_mem.v │ ├── simulation │ └── dist_mem_gen_v8_0.v │ └── synth │ └── inst_mem.vhd └── single.xpr /README.md: -------------------------------------------------------------------------------- 1 | # RISC-V CPU 2 | 3 | 记录一下夏季学期计算机设计与实践课上写的RISC-V单周期CPU和RISC-V五级流水线CPU 4 | 5 | 6 | 7 | ## 已实现功能 8 | 9 | * miniRV-1指令集 10 | * 流水线CPU的停顿、前递、静态分支预测 11 | 12 | 13 | 14 | ## 说明 15 | 16 | * 开发板 17 | 18 | Minisys开发板 (芯片型号：**XC7A100TFGG484-1**) 19 | 20 | * 实现频率 21 | 22 | 单周期CPU：25MHz 23 | 24 | 流水线CPU：70MHz 25 | 26 | 27 | 28 | ## 数据通路 29 | 30 | * 单周期CPU 31 | 32 | ![image](https://github.com/lanofblue/RISC-V-CPU/blob/master/datapath_single.png) 33 | 34 | * 流水线CPU 35 | 36 | ![image](https://github.com/lanofblue/RISC-V-CPU/blob/master/datapath_pipeline.png) 37 | -------------------------------------------------------------------------------- /datapath_pipeline.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/RegiaYoung/RISC-V-CPU/f410822af82f772b51abdce42b78c99bbe729cba/datapath_pipeline.png -------------------------------------------------------------------------------- /datapath_single.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/RegiaYoung/RISC-V-CPU/f410822af82f772b51abdce42b78c99bbe729cba/datapath_single.png -------------------------------------------------------------------------------- /pipeline/pipeline.cache/ip/2019.2/ac4765ccab3a8c3a/data_mem.dcp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/RegiaYoung/RISC-V-CPU/f410822af82f772b51abdce42b78c99bbe729cba/pipeline/pipeline.cache/ip/2019.2/ac4765ccab3a8c3a/data_mem.dcp -------------------------------------------------------------------------------- /pipeline/pipeline.cache/ip/2019.2/ac4765ccab3a8c3a/data_mem_stub.v: -------------------------------------------------------------------------------- 1 | // Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 2 | // -------------------------------------------------------------------------------- 3 | // Tool Version: Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019 4 | // Date : Mon Sep 6 16:57:50 2021 5 | // Host : DESKTOP-S2SIT85 running 64-bit major release (build 9200) 6 | // Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix 7 | // decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ data_mem_stub.v 8 | // Design : data_mem 9 | // Purpose : Stub declaration of top-level module interface 10 | // Device : xc7a100tfgg484-1 11 | // -------------------------------------------------------------------------------- 12 | 13 | // This empty module with port declaration file causes synthesis tools to infer a black box for IP. 14 | // The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. 15 | // Please paste the declaration into a Verilog source file or add the file as an additional source. 16 | (* x_core_info = "dist_mem_gen_v8_0_13,Vivado 2019.2" *) 17 | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(a, d, clk, we, spo) 18 | /* synthesis syn_black_box black_box_pad_pin="a[13:0],d[31:0],clk,we,spo[31:0]" */; 19 | input [13:0]a; 20 | input [31:0]d; 21 | input clk; 22 | input we; 23 | output [31:0]spo; 24 | endmodule 25 | -------------------------------------------------------------------------------- /pipeline/pipeline.cache/ip/2019.2/ce28ec6061e64c3c/inst_mem.dcp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/RegiaYoung/RISC-V-CPU/f410822af82f772b51abdce42b78c99bbe729cba/pipeline/pipeline.cache/ip/2019.2/ce28ec6061e64c3c/inst_mem.dcp -------------------------------------------------------------------------------- /pipeline/pipeline.cache/ip/2019.2/ce28ec6061e64c3c/inst_mem_stub.v: -------------------------------------------------------------------------------- 1 | // Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 2 | // -------------------------------------------------------------------------------- 3 | // Tool Version: Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019 4 | // Date : Mon Sep 6 16:57:01 2021 5 | // Host : DESKTOP-S2SIT85 running 64-bit major release (build 9200) 6 | // Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix 7 | // decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ inst_mem_stub.v 8 | // Design : inst_mem 9 | // Purpose : Stub declaration of top-level module interface 10 | // Device : xc7a100tfgg484-1 11 | // -------------------------------------------------------------------------------- 12 | 13 | // This empty module with port declaration file causes synthesis tools to infer a black box for IP. 14 | // The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. 15 | // Please paste the declaration into a Verilog source file or add the file as an additional source. 16 | (* x_core_info = "dist_mem_gen_v8_0_13,Vivado 2019.2" *) 17 | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(a, spo) 18 | /* synthesis syn_black_box black_box_pad_pin="a[13:0],spo[31:0]" */; 19 | input [13:0]a; 20 | output [31:0]spo; 21 | endmodule 22 | -------------------------------------------------------------------------------- /pipeline/pipeline.cache/ip/2019.2/ce28ec6061e64c3c/inst_mem_stub.vhdl: -------------------------------------------------------------------------------- 1 | -- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 2 | -- -------------------------------------------------------------------------------- 3 | -- Tool Version: Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019 4 | -- Date : Mon Sep 6 16:57:01 2021 5 | -- Host : DESKTOP-S2SIT85 running 64-bit major release (build 9200) 6 | -- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix 7 | -- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ inst_mem_stub.vhdl 8 | -- Design : inst_mem 9 | -- Purpose : Stub declaration of top-level module interface 10 | -- Device : xc7a100tfgg484-1 11 | -- -------------------------------------------------------------------------------- 12 | library IEEE; 13 | use IEEE.STD_LOGIC_1164.ALL; 14 | 15 | entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is 16 | Port ( 17 | a : in STD_LOGIC_VECTOR ( 13 downto 0 ); 18 | spo : out STD_LOGIC_VECTOR ( 31 downto 0 ) 19 | ); 20 | 21 | end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix; 22 | 23 | architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is 24 | attribute syn_black_box : boolean; 25 | attribute black_box_pad_pin : string; 26 | attribute syn_black_box of stub : architecture is true; 27 | attribute black_box_pad_pin of stub : architecture is "a[13:0],spo[31:0]"; 28 | attribute x_core_info : string; 29 | attribute x_core_info of stub : architecture is "dist_mem_gen_v8_0_13,Vivado 2019.2"; 30 | begin 31 | end; 32 | -------------------------------------------------------------------------------- /pipeline/pipeline.cache/ip/2019.2/e97bb78a59256adc/cpuclk.dcp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/RegiaYoung/RISC-V-CPU/f410822af82f772b51abdce42b78c99bbe729cba/pipeline/pipeline.cache/ip/2019.2/e97bb78a59256adc/cpuclk.dcp -------------------------------------------------------------------------------- /pipeline/pipeline.cache/ip/2019.2/e97bb78a59256adc/cpuclk_stub.v: -------------------------------------------------------------------------------- 1 | // Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 2 | // -------------------------------------------------------------------------------- 3 | // Tool Version: Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019 4 | // Date : Mon Sep 6 16:54:58 2021 5 | // Host : DESKTOP-S2SIT85 running 64-bit major release (build 9200) 6 | // Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix 7 | // decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ cpuclk_stub.v 8 | // Design : cpuclk 9 | // Purpose : Stub declaration of top-level module interface 10 | // Device : xc7a100tfgg484-1 11 | // -------------------------------------------------------------------------------- 12 | 13 | // This empty module with port declaration file causes synthesis tools to infer a black box for IP. 14 | // The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. 15 | // Please paste the declaration into a Verilog source file or add the file as an additional source. 16 | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clk_out1, locked, clk_in1) 17 | /* synthesis syn_black_box black_box_pad_pin="clk_out1,locked,clk_in1" */; 18 | output clk_out1; 19 | output locked; 20 | input clk_in1; 21 | endmodule 22 | -------------------------------------------------------------------------------- /pipeline/pipeline.cache/ip/2019.2/e97bb78a59256adc/cpuclk_stub.vhdl: -------------------------------------------------------------------------------- 1 | -- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 2 | -- -------------------------------------------------------------------------------- 3 | -- Tool Version: Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019 4 | -- Date : Mon Sep 6 16:54:58 2021 5 | -- Host : DESKTOP-S2SIT85 running 64-bit major release (build 9200) 6 | -- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix 7 | -- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ cpuclk_stub.vhdl 8 | -- Design : cpuclk 9 | -- Purpose : Stub declaration of top-level module interface 10 | -- Device : xc7a100tfgg484-1 11 | -- -------------------------------------------------------------------------------- 12 | library IEEE; 13 | use IEEE.STD_LOGIC_1164.ALL; 14 | 15 | entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is 16 | Port ( 17 | clk_out1 : out STD_LOGIC; 18 | locked : out STD_LOGIC; 19 | clk_in1 : in STD_LOGIC 20 | ); 21 | 22 | end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix; 23 | 24 | architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is 25 | attribute syn_black_box : boolean; 26 | attribute black_box_pad_pin : string; 27 | attribute syn_black_box of stub : architecture is true; 28 | attribute black_box_pad_pin of stub : architecture is "clk_out1,locked,clk_in1"; 29 | begin 30 | end; 31 | -------------------------------------------------------------------------------- /pipeline/pipeline.cache/wt/java_command_handlers.wdf: -------------------------------------------------------------------------------- 1 | version:1 2 | 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:636f726576696577:31:00:00 3 | 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:637573746f6d697a65636f7265:33:00:00 4 | 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6e657770726f6a656374:31:00:00 5 | 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:736574676c6f62616c696e636c756465:31:00:00 6 | eof:3636137316 7 | -------------------------------------------------------------------------------- /pipeline/pipeline.cache/wt/project.wpc: -------------------------------------------------------------------------------- 1 | version:1 2 | 6d6f64655f636f756e7465727c4755494d6f6465:1 3 | eof: 4 | -------------------------------------------------------------------------------- /pipeline/pipeline.hw/pipeline.lpr: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | -------------------------------------------------------------------------------- /pipeline/pipeline.ip_user_files/README.txt: -------------------------------------------------------------------------------- 1 | The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended. 2 | -------------------------------------------------------------------------------- /pipeline/pipeline.ip_user_files/ip/cpuclk/cpuclk_stub.v: -------------------------------------------------------------------------------- 1 | // Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 2 | // -------------------------------------------------------------------------------- 3 | // Tool Version: Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019 4 | // Date : Mon Sep 6 16:54:58 2021 5 | // Host : DESKTOP-S2SIT85 running 64-bit major release (build 9200) 6 | // Command : write_verilog -force -mode synth_stub 7 | // d:/STUDY/CPU/pipeline/pipeline.srcs/sources_1/ip/cpuclk/cpuclk_stub.v 8 | // Design : cpuclk 9 | // Purpose : Stub declaration of top-level module interface 10 | // Device : xc7a100tfgg484-1 11 | // -------------------------------------------------------------------------------- 12 | 13 | // This empty module with port declaration file causes synthesis tools to infer a black box for IP. 14 | // The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. 15 | // Please paste the declaration into a Verilog source file or add the file as an additional source. 16 | module cpuclk(clk_out1, locked, clk_in1) 17 | /* synthesis syn_black_box black_box_pad_pin="clk_out1,locked,clk_in1" */; 18 | output clk_out1; 19 | output locked; 20 | input clk_in1; 21 | endmodule 22 | -------------------------------------------------------------------------------- /pipeline/pipeline.ip_user_files/ip/cpuclk/cpuclk_stub.vhdl: -------------------------------------------------------------------------------- 1 | -- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 2 | -- -------------------------------------------------------------------------------- 3 | -- Tool Version: Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019 4 | -- Date : Mon Sep 6 16:54:58 2021 5 | -- Host : DESKTOP-S2SIT85 running 64-bit major release (build 9200) 6 | -- Command : write_vhdl -force -mode synth_stub 7 | -- d:/STUDY/CPU/pipeline/pipeline.srcs/sources_1/ip/cpuclk/cpuclk_stub.vhdl 8 | -- Design : cpuclk 9 | -- Purpose : Stub declaration of top-level module interface 10 | -- Device : xc7a100tfgg484-1 11 | -- -------------------------------------------------------------------------------- 12 | library IEEE; 13 | use IEEE.STD_LOGIC_1164.ALL; 14 | 15 | entity cpuclk is 16 | Port ( 17 | clk_out1 : out STD_LOGIC; 18 | locked : out STD_LOGIC; 19 | clk_in1 : in STD_LOGIC 20 | ); 21 | 22 | end cpuclk; 23 | 24 | architecture stub of cpuclk is 25 | attribute syn_black_box : boolean; 26 | attribute black_box_pad_pin : string; 27 | attribute syn_black_box of stub : architecture is true; 28 | attribute black_box_pad_pin of stub : architecture is "clk_out1,locked,clk_in1"; 29 | begin 30 | end; 31 | -------------------------------------------------------------------------------- /pipeline/pipeline.ip_user_files/ip/data_mem/data_mem_stub.v: -------------------------------------------------------------------------------- 1 | // Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 2 | // -------------------------------------------------------------------------------- 3 | // Tool Version: Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019 4 | // Date : Mon Sep 6 16:57:54 2021 5 | // Host : DESKTOP-S2SIT85 running 64-bit major release (build 9200) 6 | // Command : write_verilog -force -mode synth_stub 7 | // d:/STUDY/CPU/pipeline/pipeline.srcs/sources_1/ip/data_mem/data_mem_stub.v 8 | // Design : data_mem 9 | // Purpose : Stub declaration of top-level module interface 10 | // Device : xc7a100tfgg484-1 11 | // -------------------------------------------------------------------------------- 12 | 13 | // This empty module with port declaration file causes synthesis tools to infer a black box for IP. 14 | // The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. 15 | // Please paste the declaration into a Verilog source file or add the file as an additional source. 16 | (* x_core_info = "dist_mem_gen_v8_0_13,Vivado 2019.2" *) 17 | module data_mem(a, d, clk, we, spo) 18 | /* synthesis syn_black_box black_box_pad_pin="a[13:0],d[31:0],clk,we,spo[31:0]" */; 19 | input [13:0]a; 20 | input [31:0]d; 21 | input clk; 22 | input we; 23 | output [31:0]spo; 24 | endmodule 25 | -------------------------------------------------------------------------------- /pipeline/pipeline.ip_user_files/ip/data_mem/data_mem_stub.vhdl: -------------------------------------------------------------------------------- 1 | -- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 2 | -- -------------------------------------------------------------------------------- 3 | -- Tool Version: Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019 4 | -- Date : Mon Sep 6 16:57:54 2021 5 | -- Host : DESKTOP-S2SIT85 running 64-bit major release (build 9200) 6 | -- Command : write_vhdl -force -mode synth_stub 7 | -- d:/STUDY/CPU/pipeline/pipeline.srcs/sources_1/ip/data_mem/data_mem_stub.vhdl 8 | -- Design : data_mem 9 | -- Purpose : Stub declaration of top-level module interface 10 | -- Device : xc7a100tfgg484-1 11 | -- -------------------------------------------------------------------------------- 12 | library IEEE; 13 | use IEEE.STD_LOGIC_1164.ALL; 14 | 15 | entity data_mem is 16 | Port ( 17 | a : in STD_LOGIC_VECTOR ( 13 downto 0 ); 18 | d : in STD_LOGIC_VECTOR ( 31 downto 0 ); 19 | clk : in STD_LOGIC; 20 | we : in STD_LOGIC; 21 | spo : out STD_LOGIC_VECTOR ( 31 downto 0 ) 22 | ); 23 | 24 | end data_mem; 25 | 26 | architecture stub of data_mem is 27 | attribute syn_black_box : boolean; 28 | attribute black_box_pad_pin : string; 29 | attribute syn_black_box of stub : architecture is true; 30 | attribute black_box_pad_pin of stub : architecture is "a[13:0],d[31:0],clk,we,spo[31:0]"; 31 | attribute x_core_info : string; 32 | attribute x_core_info of stub : architecture is "dist_mem_gen_v8_0_13,Vivado 2019.2"; 33 | begin 34 | end; 35 | -------------------------------------------------------------------------------- /pipeline/pipeline.ip_user_files/ip/inst_mem/inst_mem_stub.v: -------------------------------------------------------------------------------- 1 | // Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 2 | // -------------------------------------------------------------------------------- 3 | // Tool Version: Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019 4 | // Date : Mon Sep 6 16:57:01 2021 5 | // Host : DESKTOP-S2SIT85 running 64-bit major release (build 9200) 6 | // Command : write_verilog -force -mode synth_stub 7 | // d:/STUDY/CPU/pipeline/pipeline.srcs/sources_1/ip/inst_mem/inst_mem_stub.v 8 | // Design : inst_mem 9 | // Purpose : Stub declaration of top-level module interface 10 | // Device : xc7a100tfgg484-1 11 | // -------------------------------------------------------------------------------- 12 | 13 | // This empty module with port declaration file causes synthesis tools to infer a black box for IP. 14 | // The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. 15 | // Please paste the declaration into a Verilog source file or add the file as an additional source. 16 | (* x_core_info = "dist_mem_gen_v8_0_13,Vivado 2019.2" *) 17 | module inst_mem(a, spo) 18 | /* synthesis syn_black_box black_box_pad_pin="a[13:0],spo[31:0]" */; 19 | input [13:0]a; 20 | output [31:0]spo; 21 | endmodule 22 | -------------------------------------------------------------------------------- /pipeline/pipeline.ip_user_files/ip/inst_mem/inst_mem_stub.vhdl: -------------------------------------------------------------------------------- 1 | -- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 2 | -- -------------------------------------------------------------------------------- 3 | -- Tool Version: Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019 4 | -- Date : Mon Sep 6 16:57:01 2021 5 | -- Host : DESKTOP-S2SIT85 running 64-bit major release (build 9200) 6 | -- Command : write_vhdl -force -mode synth_stub 7 | -- d:/STUDY/CPU/pipeline/pipeline.srcs/sources_1/ip/inst_mem/inst_mem_stub.vhdl 8 | -- Design : inst_mem 9 | -- Purpose : Stub declaration of top-level module interface 10 | -- Device : xc7a100tfgg484-1 11 | -- -------------------------------------------------------------------------------- 12 | library IEEE; 13 | use IEEE.STD_LOGIC_1164.ALL; 14 | 15 | entity inst_mem is 16 | Port ( 17 | a : in STD_LOGIC_VECTOR ( 13 downto 0 ); 18 | spo : out STD_LOGIC_VECTOR ( 31 downto 0 ) 19 | ); 20 | 21 | end inst_mem; 22 | 23 | architecture stub of inst_mem is 24 | attribute syn_black_box : boolean; 25 | attribute black_box_pad_pin : string; 26 | attribute syn_black_box of stub : architecture is true; 27 | attribute black_box_pad_pin of stub : architecture is "a[13:0],spo[31:0]"; 28 | attribute x_core_info : string; 29 | attribute x_core_info of stub : architecture is "dist_mem_gen_v8_0_13,Vivado 2019.2"; 30 | begin 31 | end; 32 | -------------------------------------------------------------------------------- /pipeline/pipeline.ip_user_files/sim_scripts/cpuclk/activehdl/compile.do: -------------------------------------------------------------------------------- 1 | vlib work 2 | vlib activehdl 3 | 4 | vlib activehdl/xpm 5 | vlib activehdl/xil_defaultlib 6 | 7 | vmap xpm activehdl/xpm 8 | vmap xil_defaultlib activehdl/xil_defaultlib 9 | 10 | vlog -work xpm -sv2k12 "+incdir+../../../ipstatic" \ 11 | "D:/Applications/Vivado2020/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ 12 | 13 | vcom -work xpm -93 \ 14 | "D:/Applications/Vivado2020/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd" \ 15 | 16 | vlog -work xil_defaultlib -v2k5 "+incdir+../../../ipstatic" \ 17 | "../../../../pipeline.srcs/sources_1/ip/cpuclk/cpuclk_clk_wiz.v" \ 18 | "../../../../pipeline.srcs/sources_1/ip/cpuclk/cpuclk.v" \ 19 | 20 | vlog -work xil_defaultlib \ 21 | "glbl.v" 22 | 23 | -------------------------------------------------------------------------------- /pipeline/pipeline.ip_user_files/sim_scripts/cpuclk/activehdl/cpuclk.udo: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/RegiaYoung/RISC-V-CPU/f410822af82f772b51abdce42b78c99bbe729cba/pipeline/pipeline.ip_user_files/sim_scripts/cpuclk/activehdl/cpuclk.udo -------------------------------------------------------------------------------- /pipeline/pipeline.ip_user_files/sim_scripts/cpuclk/activehdl/file_info.txt: -------------------------------------------------------------------------------- 1 | xpm_cdc.sv,systemverilog,xpm,D:/Applications/Vivado2020/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ipstatic"incdir="../../../ipstatic" 2 | xpm_VCOMP.vhd,vhdl,xpm,D:/Applications/Vivado2020/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ipstatic"incdir="../../../ipstatic" 3 | cpuclk_clk_wiz.v,verilog,xil_defaultlib,../../../../pipeline.srcs/sources_1/ip/cpuclk/cpuclk_clk_wiz.v,incdir="../../../ipstatic"incdir="../../../ipstatic" 4 | cpuclk.v,verilog,xil_defaultlib,../../../../pipeline.srcs/sources_1/ip/cpuclk/cpuclk.v,incdir="../../../ipstatic"incdir="../../../ipstatic" 5 | glbl.v,Verilog,xil_defaultlib,glbl.v 6 | -------------------------------------------------------------------------------- /pipeline/pipeline.ip_user_files/sim_scripts/cpuclk/activehdl/simulate.do: -------------------------------------------------------------------------------- 1 | onbreak {quit -force} 2 | onerror {quit -force} 3 | 4 | asim -t 1ps +access +r +m+cpuclk -L xpm -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.cpuclk xil_defaultlib.glbl 5 | 6 | do {wave.do} 7 | 8 | view wave 9 | view structure 10 | 11 | do {cpuclk.udo} 12 | 13 | run -all 14 | 15 | endsim 16 | 17 | quit -force 18 | -------------------------------------------------------------------------------- /pipeline/pipeline.ip_user_files/sim_scripts/cpuclk/activehdl/wave.do: -------------------------------------------------------------------------------- 1 | add wave * 2 | add wave /glbl/GSR 3 | -------------------------------------------------------------------------------- /pipeline/pipeline.ip_user_files/sim_scripts/cpuclk/ies/file_info.txt: -------------------------------------------------------------------------------- 1 | xpm_cdc.sv,systemverilog,xpm,D:/Applications/Vivado2020/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="$ref_dir/../../../ipstatic"incdir="../../../ipstatic" 2 | xpm_VCOMP.vhd,vhdl,xpm,D:/Applications/Vivado2020/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="$ref_dir/../../../ipstatic"incdir="../../../ipstatic" 3 | cpuclk_clk_wiz.v,verilog,xil_defaultlib,../../../../pipeline.srcs/sources_1/ip/cpuclk/cpuclk_clk_wiz.v,incdir="$ref_dir/../../../ipstatic"incdir="../../../ipstatic" 4 | cpuclk.v,verilog,xil_defaultlib,../../../../pipeline.srcs/sources_1/ip/cpuclk/cpuclk.v,incdir="$ref_dir/../../../ipstatic"incdir="../../../ipstatic" 5 | glbl.v,Verilog,xil_defaultlib,glbl.v 6 | -------------------------------------------------------------------------------- /pipeline/pipeline.ip_user_files/sim_scripts/cpuclk/ies/run.f: -------------------------------------------------------------------------------- 1 | -makelib ies_lib/xpm -sv \ 2 | "D:/Applications/Vivado2020/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ 3 | -endlib 4 | -makelib ies_lib/xpm \ 5 | "D:/Applications/Vivado2020/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd" \ 6 | -endlib 7 | -makelib ies_lib/xil_defaultlib \ 8 | "../../../../pipeline.srcs/sources_1/ip/cpuclk/cpuclk_clk_wiz.v" \ 9 | "../../../../pipeline.srcs/sources_1/ip/cpuclk/cpuclk.v" \ 10 | -endlib 11 | -makelib ies_lib/xil_defaultlib \ 12 | glbl.v 13 | -endlib 14 | 15 | -------------------------------------------------------------------------------- /pipeline/pipeline.ip_user_files/sim_scripts/cpuclk/modelsim/compile.do: -------------------------------------------------------------------------------- 1 | vlib modelsim_lib/work 2 | vlib modelsim_lib/msim 3 | 4 | vlib modelsim_lib/msim/xpm 5 | vlib modelsim_lib/msim/xil_defaultlib 6 | 7 | vmap xpm modelsim_lib/msim/xpm 8 | vmap xil_defaultlib modelsim_lib/msim/xil_defaultlib 9 | 10 | vlog -work xpm -64 -incr -sv "+incdir+../../../ipstatic" \ 11 | "D:/Applications/Vivado2020/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ 12 | 13 | vcom -work xpm -64 -93 \ 14 | "D:/Applications/Vivado2020/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd" \ 15 | 16 | vlog -work xil_defaultlib -64 -incr "+incdir+../../../ipstatic" \ 17 | "../../../../pipeline.srcs/sources_1/ip/cpuclk/cpuclk_clk_wiz.v" \ 18 | "../../../../pipeline.srcs/sources_1/ip/cpuclk/cpuclk.v" \ 19 | 20 | vlog -work xil_defaultlib \ 21 | "glbl.v" 22 | 23 | -------------------------------------------------------------------------------- /pipeline/pipeline.ip_user_files/sim_scripts/cpuclk/modelsim/cpuclk.udo: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/RegiaYoung/RISC-V-CPU/f410822af82f772b51abdce42b78c99bbe729cba/pipeline/pipeline.ip_user_files/sim_scripts/cpuclk/modelsim/cpuclk.udo -------------------------------------------------------------------------------- /pipeline/pipeline.ip_user_files/sim_scripts/cpuclk/modelsim/file_info.txt: -------------------------------------------------------------------------------- 1 | xpm_cdc.sv,systemverilog,xpm,D:/Applications/Vivado2020/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ipstatic"incdir="../../../ipstatic" 2 | xpm_VCOMP.vhd,vhdl,xpm,D:/Applications/Vivado2020/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ipstatic"incdir="../../../ipstatic" 3 | cpuclk_clk_wiz.v,verilog,xil_defaultlib,../../../../pipeline.srcs/sources_1/ip/cpuclk/cpuclk_clk_wiz.v,incdir="../../../ipstatic"incdir="../../../ipstatic" 4 | cpuclk.v,verilog,xil_defaultlib,../../../../pipeline.srcs/sources_1/ip/cpuclk/cpuclk.v,incdir="../../../ipstatic"incdir="../../../ipstatic" 5 | glbl.v,Verilog,xil_defaultlib,glbl.v 6 | -------------------------------------------------------------------------------- /pipeline/pipeline.ip_user_files/sim_scripts/cpuclk/modelsim/simulate.do: -------------------------------------------------------------------------------- 1 | onbreak {quit -f} 2 | onerror {quit -f} 3 | 4 | vsim -voptargs="+acc" -t 1ps -L xpm -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -lib xil_defaultlib xil_defaultlib.cpuclk xil_defaultlib.glbl 5 | 6 | do {wave.do} 7 | 8 | view wave 9 | view structure 10 | view signals 11 | 12 | do {cpuclk.udo} 13 | 14 | run -all 15 | 16 | quit -force 17 | -------------------------------------------------------------------------------- /pipeline/pipeline.ip_user_files/sim_scripts/cpuclk/modelsim/wave.do: -------------------------------------------------------------------------------- 1 | add wave * 2 | add wave /glbl/GSR 3 | -------------------------------------------------------------------------------- /pipeline/pipeline.ip_user_files/sim_scripts/cpuclk/questa/compile.do: -------------------------------------------------------------------------------- 1 | vlib questa_lib/work 2 | vlib questa_lib/msim 3 | 4 | vlib questa_lib/msim/xpm 5 | vlib questa_lib/msim/xil_defaultlib 6 | 7 | vmap xpm questa_lib/msim/xpm 8 | vmap xil_defaultlib questa_lib/msim/xil_defaultlib 9 | 10 | vlog -work xpm -64 -sv "+incdir+../../../ipstatic" \ 11 | "D:/Applications/Vivado2020/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ 12 | 13 | vcom -work xpm -64 -93 \ 14 | "D:/Applications/Vivado2020/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd" \ 15 | 16 | vlog -work xil_defaultlib -64 "+incdir+../../../ipstatic" \ 17 | "../../../../pipeline.srcs/sources_1/ip/cpuclk/cpuclk_clk_wiz.v" \ 18 | "../../../../pipeline.srcs/sources_1/ip/cpuclk/cpuclk.v" \ 19 | 20 | vlog -work xil_defaultlib \ 21 | "glbl.v" 22 | 23 | -------------------------------------------------------------------------------- /pipeline/pipeline.ip_user_files/sim_scripts/cpuclk/questa/cpuclk.udo: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/RegiaYoung/RISC-V-CPU/f410822af82f772b51abdce42b78c99bbe729cba/pipeline/pipeline.ip_user_files/sim_scripts/cpuclk/questa/cpuclk.udo -------------------------------------------------------------------------------- /pipeline/pipeline.ip_user_files/sim_scripts/cpuclk/questa/elaborate.do: -------------------------------------------------------------------------------- 1 | vopt -64 +acc -l elaborate.log -L xpm -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -work xil_defaultlib xil_defaultlib.cpuclk xil_defaultlib.glbl -o cpuclk_opt 2 | -------------------------------------------------------------------------------- /pipeline/pipeline.ip_user_files/sim_scripts/cpuclk/questa/file_info.txt: -------------------------------------------------------------------------------- 1 | xpm_cdc.sv,systemverilog,xpm,D:/Applications/Vivado2020/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ipstatic"incdir="../../../ipstatic" 2 | xpm_VCOMP.vhd,vhdl,xpm,D:/Applications/Vivado2020/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ipstatic"incdir="../../../ipstatic" 3 | cpuclk_clk_wiz.v,verilog,xil_defaultlib,../../../../pipeline.srcs/sources_1/ip/cpuclk/cpuclk_clk_wiz.v,incdir="../../../ipstatic"incdir="../../../ipstatic" 4 | cpuclk.v,verilog,xil_defaultlib,../../../../pipeline.srcs/sources_1/ip/cpuclk/cpuclk.v,incdir="../../../ipstatic"incdir="../../../ipstatic" 5 | glbl.v,Verilog,xil_defaultlib,glbl.v 6 | -------------------------------------------------------------------------------- /pipeline/pipeline.ip_user_files/sim_scripts/cpuclk/questa/simulate.do: -------------------------------------------------------------------------------- 1 | onbreak {quit -f} 2 | onerror {quit -f} 3 | 4 | vsim -t 1ps -lib xil_defaultlib cpuclk_opt 5 | 6 | do {wave.do} 7 | 8 | view wave 9 | view structure 10 | view signals 11 | 12 | do {cpuclk.udo} 13 | 14 | run -all 15 | 16 | quit -force 17 | -------------------------------------------------------------------------------- /pipeline/pipeline.ip_user_files/sim_scripts/cpuclk/questa/wave.do: -------------------------------------------------------------------------------- 1 | add wave * 2 | add wave /glbl/GSR 3 | -------------------------------------------------------------------------------- /pipeline/pipeline.ip_user_files/sim_scripts/cpuclk/riviera/compile.do: -------------------------------------------------------------------------------- 1 | vlib work 2 | vlib riviera 3 | 4 | vlib riviera/xpm 5 | vlib riviera/xil_defaultlib 6 | 7 | vmap xpm riviera/xpm 8 | vmap xil_defaultlib riviera/xil_defaultlib 9 | 10 | vlog -work xpm -sv2k12 "+incdir+../../../ipstatic" \ 11 | "D:/Applications/Vivado2020/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ 12 | 13 | vcom -work xpm -93 \ 14 | "D:/Applications/Vivado2020/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd" \ 15 | 16 | vlog -work xil_defaultlib -v2k5 "+incdir+../../../ipstatic" \ 17 | "../../../../pipeline.srcs/sources_1/ip/cpuclk/cpuclk_clk_wiz.v" \ 18 | "../../../../pipeline.srcs/sources_1/ip/cpuclk/cpuclk.v" \ 19 | 20 | vlog -work xil_defaultlib \ 21 | "glbl.v" 22 | 23 | -------------------------------------------------------------------------------- /pipeline/pipeline.ip_user_files/sim_scripts/cpuclk/riviera/cpuclk.udo: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/RegiaYoung/RISC-V-CPU/f410822af82f772b51abdce42b78c99bbe729cba/pipeline/pipeline.ip_user_files/sim_scripts/cpuclk/riviera/cpuclk.udo -------------------------------------------------------------------------------- /pipeline/pipeline.ip_user_files/sim_scripts/cpuclk/riviera/file_info.txt: -------------------------------------------------------------------------------- 1 | xpm_cdc.sv,systemverilog,xpm,D:/Applications/Vivado2020/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ipstatic"incdir="../../../ipstatic" 2 | xpm_VCOMP.vhd,vhdl,xpm,D:/Applications/Vivado2020/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ipstatic"incdir="../../../ipstatic" 3 | cpuclk_clk_wiz.v,verilog,xil_defaultlib,../../../../pipeline.srcs/sources_1/ip/cpuclk/cpuclk_clk_wiz.v,incdir="../../../ipstatic"incdir="../../../ipstatic" 4 | cpuclk.v,verilog,xil_defaultlib,../../../../pipeline.srcs/sources_1/ip/cpuclk/cpuclk.v,incdir="../../../ipstatic"incdir="../../../ipstatic" 5 | glbl.v,Verilog,xil_defaultlib,glbl.v 6 | -------------------------------------------------------------------------------- /pipeline/pipeline.ip_user_files/sim_scripts/cpuclk/riviera/simulate.do: -------------------------------------------------------------------------------- 1 | onbreak {quit -force} 2 | onerror {quit -force} 3 | 4 | asim -t 1ps +access +r +m+cpuclk -L xpm -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.cpuclk xil_defaultlib.glbl 5 | 6 | do {wave.do} 7 | 8 | view wave 9 | view structure 10 | 11 | do {cpuclk.udo} 12 | 13 | run -all 14 | 15 | endsim 16 | 17 | quit -force 18 | -------------------------------------------------------------------------------- /pipeline/pipeline.ip_user_files/sim_scripts/cpuclk/riviera/wave.do: -------------------------------------------------------------------------------- 1 | add wave * 2 | add wave /glbl/GSR 3 | -------------------------------------------------------------------------------- /pipeline/pipeline.ip_user_files/sim_scripts/cpuclk/vcs/file_info.txt: -------------------------------------------------------------------------------- 1 | xpm_cdc.sv,systemverilog,xpm,D:/Applications/Vivado2020/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="$ref_dir/../../../ipstatic"incdir="../../../ipstatic" 2 | xpm_VCOMP.vhd,vhdl,xpm,D:/Applications/Vivado2020/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="$ref_dir/../../../ipstatic"incdir="../../../ipstatic" 3 | cpuclk_clk_wiz.v,verilog,xil_defaultlib,../../../../pipeline.srcs/sources_1/ip/cpuclk/cpuclk_clk_wiz.v,incdir="$ref_dir/../../../ipstatic"incdir="../../../ipstatic" 4 | cpuclk.v,verilog,xil_defaultlib,../../../../pipeline.srcs/sources_1/ip/cpuclk/cpuclk.v,incdir="$ref_dir/../../../ipstatic"incdir="../../../ipstatic" 5 | glbl.v,Verilog,xil_defaultlib,glbl.v 6 | -------------------------------------------------------------------------------- /pipeline/pipeline.ip_user_files/sim_scripts/cpuclk/vcs/simulate.do: -------------------------------------------------------------------------------- 1 | run 2 | quit 3 | -------------------------------------------------------------------------------- /pipeline/pipeline.ip_user_files/sim_scripts/cpuclk/xcelium/file_info.txt: -------------------------------------------------------------------------------- 1 | xpm_cdc.sv,systemverilog,xpm,D:/Applications/Vivado2020/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="$ref_dir/../../../ipstatic"incdir="../../../ipstatic" 2 | xpm_VCOMP.vhd,vhdl,xpm,D:/Applications/Vivado2020/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="$ref_dir/../../../ipstatic"incdir="../../../ipstatic" 3 | cpuclk_clk_wiz.v,verilog,xil_defaultlib,../../../../pipeline.srcs/sources_1/ip/cpuclk/cpuclk_clk_wiz.v,incdir="$ref_dir/../../../ipstatic"incdir="../../../ipstatic" 4 | cpuclk.v,verilog,xil_defaultlib,../../../../pipeline.srcs/sources_1/ip/cpuclk/cpuclk.v,incdir="$ref_dir/../../../ipstatic"incdir="../../../ipstatic" 5 | glbl.v,Verilog,xil_defaultlib,glbl.v 6 | -------------------------------------------------------------------------------- /pipeline/pipeline.ip_user_files/sim_scripts/cpuclk/xcelium/run.f: -------------------------------------------------------------------------------- 1 | -makelib xcelium_lib/xpm -sv \ 2 | "D:/Applications/Vivado2020/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ 3 | -endlib 4 | -makelib xcelium_lib/xpm \ 5 | "D:/Applications/Vivado2020/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd" \ 6 | -endlib 7 | -makelib xcelium_lib/xil_defaultlib \ 8 | "../../../../pipeline.srcs/sources_1/ip/cpuclk/cpuclk_clk_wiz.v" \ 9 | "../../../../pipeline.srcs/sources_1/ip/cpuclk/cpuclk.v" \ 10 | -endlib 11 | -makelib xcelium_lib/xil_defaultlib \ 12 | glbl.v 13 | -endlib 14 | 15 | -------------------------------------------------------------------------------- /pipeline/pipeline.ip_user_files/sim_scripts/cpuclk/xsim/cmd.tcl: -------------------------------------------------------------------------------- 1 | set curr_wave [current_wave_config] 2 | if { [string length $curr_wave] == 0 } { 3 | if { [llength [get_objects]] > 0} { 4 | add_wave / 5 | set_property needs_save false [current_wave_config] 6 | } else { 7 | send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." 8 | } 9 | } 10 | 11 | run -all 12 | quit 13 | -------------------------------------------------------------------------------- /pipeline/pipeline.ip_user_files/sim_scripts/cpuclk/xsim/elab.opt: -------------------------------------------------------------------------------- 1 | --relax --debug typical --mt auto -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot cpuclk xil_defaultlib.cpuclk xil_defaultlib.glbl -log elaborate.log 2 | -------------------------------------------------------------------------------- /pipeline/pipeline.ip_user_files/sim_scripts/cpuclk/xsim/file_info.txt: -------------------------------------------------------------------------------- 1 | cpuclk_clk_wiz.v,verilog,xil_defaultlib,../../../../pipeline.srcs/sources_1/ip/cpuclk/cpuclk_clk_wiz.v,incdir="$ref_dir/../../../ipstatic"incdir="../../../ipstatic" 2 | cpuclk.v,verilog,xil_defaultlib,../../../../pipeline.srcs/sources_1/ip/cpuclk/cpuclk.v,incdir="$ref_dir/../../../ipstatic"incdir="../../../ipstatic" 3 | glbl.v,Verilog,xil_defaultlib,glbl.v 4 | -------------------------------------------------------------------------------- /pipeline/pipeline.ip_user_files/sim_scripts/cpuclk/xsim/vlog.prj: -------------------------------------------------------------------------------- 1 | verilog xil_defaultlib --include "../../../ipstatic" \ 2 | "../../../../pipeline.srcs/sources_1/ip/cpuclk/cpuclk_clk_wiz.v" \ 3 | "../../../../pipeline.srcs/sources_1/ip/cpuclk/cpuclk.v" \ 4 | 5 | verilog xil_defaultlib "glbl.v" 6 | 7 | nosort 8 | -------------------------------------------------------------------------------- /pipeline/pipeline.ip_user_files/sim_scripts/data_mem/activehdl/compile.do: -------------------------------------------------------------------------------- 1 | vlib work 2 | vlib activehdl 3 | 4 | vlib activehdl/dist_mem_gen_v8_0_13 5 | vlib activehdl/xil_defaultlib 6 | 7 | vmap dist_mem_gen_v8_0_13 activehdl/dist_mem_gen_v8_0_13 8 | vmap xil_defaultlib activehdl/xil_defaultlib 9 | 10 | vlog -work dist_mem_gen_v8_0_13 -v2k5 \ 11 | "../../../ipstatic/simulation/dist_mem_gen_v8_0.v" \ 12 | 13 | vlog -work xil_defaultlib -v2k5 \ 14 | "../../../../pipeline.srcs/sources_1/ip/data_mem/sim/data_mem.v" \ 15 | 16 | 17 | vlog -work xil_defaultlib \ 18 | "glbl.v" 19 | 20 | -------------------------------------------------------------------------------- /pipeline/pipeline.ip_user_files/sim_scripts/data_mem/activehdl/data_mem.udo: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/RegiaYoung/RISC-V-CPU/f410822af82f772b51abdce42b78c99bbe729cba/pipeline/pipeline.ip_user_files/sim_scripts/data_mem/activehdl/data_mem.udo -------------------------------------------------------------------------------- /pipeline/pipeline.ip_user_files/sim_scripts/data_mem/activehdl/file_info.txt: -------------------------------------------------------------------------------- 1 | dist_mem_gen_v8_0.v,verilog,dist_mem_gen_v8_0_13,../../../ipstatic/simulation/dist_mem_gen_v8_0.v, 2 | data_mem.v,verilog,xil_defaultlib,../../../../pipeline.srcs/sources_1/ip/data_mem/sim/data_mem.v, 3 | glbl.v,Verilog,xil_defaultlib,glbl.v 4 | -------------------------------------------------------------------------------- /pipeline/pipeline.ip_user_files/sim_scripts/data_mem/activehdl/simulate.do: -------------------------------------------------------------------------------- 1 | onbreak {quit -force} 2 | onerror {quit -force} 3 | 4 | asim -t 1ps +access +r +m+data_mem -L dist_mem_gen_v8_0_13 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.data_mem xil_defaultlib.glbl 5 | 6 | do {wave.do} 7 | 8 | view wave 9 | view structure 10 | 11 | do {data_mem.udo} 12 | 13 | run -all 14 | 15 | endsim 16 | 17 | quit -force 18 | -------------------------------------------------------------------------------- /pipeline/pipeline.ip_user_files/sim_scripts/data_mem/activehdl/wave.do: -------------------------------------------------------------------------------- 1 | add wave * 2 | add wave /glbl/GSR 3 | -------------------------------------------------------------------------------- /pipeline/pipeline.ip_user_files/sim_scripts/data_mem/ies/file_info.txt: -------------------------------------------------------------------------------- 1 | dist_mem_gen_v8_0.v,verilog,dist_mem_gen_v8_0_13,../../../ipstatic/simulation/dist_mem_gen_v8_0.v, 2 | data_mem.v,verilog,xil_defaultlib,../../../../pipeline.srcs/sources_1/ip/data_mem/sim/data_mem.v, 3 | glbl.v,Verilog,xil_defaultlib,glbl.v 4 | -------------------------------------------------------------------------------- /pipeline/pipeline.ip_user_files/sim_scripts/data_mem/ies/run.f: -------------------------------------------------------------------------------- 1 | -makelib ies_lib/dist_mem_gen_v8_0_13 \ 2 | "../../../ipstatic/simulation/dist_mem_gen_v8_0.v" \ 3 | -endlib 4 | -makelib ies_lib/xil_defaultlib \ 5 | "../../../../pipeline.srcs/sources_1/ip/data_mem/sim/data_mem.v" \ 6 | -endlib 7 | -makelib ies_lib/xil_defaultlib \ 8 | glbl.v 9 | -endlib 10 | 11 | -------------------------------------------------------------------------------- /pipeline/pipeline.ip_user_files/sim_scripts/data_mem/modelsim/compile.do: -------------------------------------------------------------------------------- 1 | vlib modelsim_lib/work 2 | vlib modelsim_lib/msim 3 | 4 | vlib modelsim_lib/msim/dist_mem_gen_v8_0_13 5 | vlib modelsim_lib/msim/xil_defaultlib 6 | 7 | vmap dist_mem_gen_v8_0_13 modelsim_lib/msim/dist_mem_gen_v8_0_13 8 | vmap xil_defaultlib modelsim_lib/msim/xil_defaultlib 9 | 10 | vlog -work dist_mem_gen_v8_0_13 -64 -incr \ 11 | "../../../ipstatic/simulation/dist_mem_gen_v8_0.v" \ 12 | 13 | vlog -work xil_defaultlib -64 -incr \ 14 | "../../../../pipeline.srcs/sources_1/ip/data_mem/sim/data_mem.v" \ 15 | 16 | 17 | vlog -work xil_defaultlib \ 18 | "glbl.v" 19 | 20 | -------------------------------------------------------------------------------- /pipeline/pipeline.ip_user_files/sim_scripts/data_mem/modelsim/data_mem.udo: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/RegiaYoung/RISC-V-CPU/f410822af82f772b51abdce42b78c99bbe729cba/pipeline/pipeline.ip_user_files/sim_scripts/data_mem/modelsim/data_mem.udo -------------------------------------------------------------------------------- /pipeline/pipeline.ip_user_files/sim_scripts/data_mem/modelsim/file_info.txt: -------------------------------------------------------------------------------- 1 | dist_mem_gen_v8_0.v,verilog,dist_mem_gen_v8_0_13,../../../ipstatic/simulation/dist_mem_gen_v8_0.v, 2 | data_mem.v,verilog,xil_defaultlib,../../../../pipeline.srcs/sources_1/ip/data_mem/sim/data_mem.v, 3 | glbl.v,Verilog,xil_defaultlib,glbl.v 4 | -------------------------------------------------------------------------------- /pipeline/pipeline.ip_user_files/sim_scripts/data_mem/modelsim/simulate.do: -------------------------------------------------------------------------------- 1 | onbreak {quit -f} 2 | onerror {quit -f} 3 | 4 | vsim -voptargs="+acc" -t 1ps -L dist_mem_gen_v8_0_13 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -lib xil_defaultlib xil_defaultlib.data_mem xil_defaultlib.glbl 5 | 6 | do {wave.do} 7 | 8 | view wave 9 | view structure 10 | view signals 11 | 12 | do {data_mem.udo} 13 | 14 | run -all 15 | 16 | quit -force 17 | -------------------------------------------------------------------------------- /pipeline/pipeline.ip_user_files/sim_scripts/data_mem/modelsim/wave.do: -------------------------------------------------------------------------------- 1 | add wave * 2 | add wave /glbl/GSR 3 | -------------------------------------------------------------------------------- /pipeline/pipeline.ip_user_files/sim_scripts/data_mem/questa/compile.do: -------------------------------------------------------------------------------- 1 | vlib questa_lib/work 2 | vlib questa_lib/msim 3 | 4 | vlib questa_lib/msim/dist_mem_gen_v8_0_13 5 | vlib questa_lib/msim/xil_defaultlib 6 | 7 | vmap dist_mem_gen_v8_0_13 questa_lib/msim/dist_mem_gen_v8_0_13 8 | vmap xil_defaultlib questa_lib/msim/xil_defaultlib 9 | 10 | vlog -work dist_mem_gen_v8_0_13 -64 \ 11 | "../../../ipstatic/simulation/dist_mem_gen_v8_0.v" \ 12 | 13 | vlog -work xil_defaultlib -64 \ 14 | "../../../../pipeline.srcs/sources_1/ip/data_mem/sim/data_mem.v" \ 15 | 16 | 17 | vlog -work xil_defaultlib \ 18 | "glbl.v" 19 | 20 | -------------------------------------------------------------------------------- /pipeline/pipeline.ip_user_files/sim_scripts/data_mem/questa/data_mem.udo: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/RegiaYoung/RISC-V-CPU/f410822af82f772b51abdce42b78c99bbe729cba/pipeline/pipeline.ip_user_files/sim_scripts/data_mem/questa/data_mem.udo -------------------------------------------------------------------------------- /pipeline/pipeline.ip_user_files/sim_scripts/data_mem/questa/elaborate.do: -------------------------------------------------------------------------------- 1 | vopt -64 +acc -l elaborate.log -L dist_mem_gen_v8_0_13 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -work xil_defaultlib xil_defaultlib.data_mem xil_defaultlib.glbl -o data_mem_opt 2 | -------------------------------------------------------------------------------- /pipeline/pipeline.ip_user_files/sim_scripts/data_mem/questa/file_info.txt: -------------------------------------------------------------------------------- 1 | dist_mem_gen_v8_0.v,verilog,dist_mem_gen_v8_0_13,../../../ipstatic/simulation/dist_mem_gen_v8_0.v, 2 | data_mem.v,verilog,xil_defaultlib,../../../../pipeline.srcs/sources_1/ip/data_mem/sim/data_mem.v, 3 | glbl.v,Verilog,xil_defaultlib,glbl.v 4 | -------------------------------------------------------------------------------- /pipeline/pipeline.ip_user_files/sim_scripts/data_mem/questa/simulate.do: -------------------------------------------------------------------------------- 1 | onbreak {quit -f} 2 | onerror {quit -f} 3 | 4 | vsim -t 1ps -lib xil_defaultlib data_mem_opt 5 | 6 | do {wave.do} 7 | 8 | view wave 9 | view structure 10 | view signals 11 | 12 | do {data_mem.udo} 13 | 14 | run -all 15 | 16 | quit -force 17 | -------------------------------------------------------------------------------- /pipeline/pipeline.ip_user_files/sim_scripts/data_mem/questa/wave.do: -------------------------------------------------------------------------------- 1 | add wave * 2 | add wave /glbl/GSR 3 | -------------------------------------------------------------------------------- /pipeline/pipeline.ip_user_files/sim_scripts/data_mem/riviera/compile.do: -------------------------------------------------------------------------------- 1 | vlib work 2 | vlib riviera 3 | 4 | vlib riviera/dist_mem_gen_v8_0_13 5 | vlib riviera/xil_defaultlib 6 | 7 | vmap dist_mem_gen_v8_0_13 riviera/dist_mem_gen_v8_0_13 8 | vmap xil_defaultlib riviera/xil_defaultlib 9 | 10 | vlog -work dist_mem_gen_v8_0_13 -v2k5 \ 11 | "../../../ipstatic/simulation/dist_mem_gen_v8_0.v" \ 12 | 13 | vlog -work xil_defaultlib -v2k5 \ 14 | "../../../../pipeline.srcs/sources_1/ip/data_mem/sim/data_mem.v" \ 15 | 16 | 17 | vlog -work xil_defaultlib \ 18 | "glbl.v" 19 | 20 | -------------------------------------------------------------------------------- /pipeline/pipeline.ip_user_files/sim_scripts/data_mem/riviera/data_mem.udo: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/RegiaYoung/RISC-V-CPU/f410822af82f772b51abdce42b78c99bbe729cba/pipeline/pipeline.ip_user_files/sim_scripts/data_mem/riviera/data_mem.udo -------------------------------------------------------------------------------- /pipeline/pipeline.ip_user_files/sim_scripts/data_mem/riviera/file_info.txt: -------------------------------------------------------------------------------- 1 | dist_mem_gen_v8_0.v,verilog,dist_mem_gen_v8_0_13,../../../ipstatic/simulation/dist_mem_gen_v8_0.v, 2 | data_mem.v,verilog,xil_defaultlib,../../../../pipeline.srcs/sources_1/ip/data_mem/sim/data_mem.v, 3 | glbl.v,Verilog,xil_defaultlib,glbl.v 4 | -------------------------------------------------------------------------------- /pipeline/pipeline.ip_user_files/sim_scripts/data_mem/riviera/simulate.do: -------------------------------------------------------------------------------- 1 | onbreak {quit -force} 2 | onerror {quit -force} 3 | 4 | asim -t 1ps +access +r +m+data_mem -L dist_mem_gen_v8_0_13 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.data_mem xil_defaultlib.glbl 5 | 6 | do {wave.do} 7 | 8 | view wave 9 | view structure 10 | 11 | do {data_mem.udo} 12 | 13 | run -all 14 | 15 | endsim 16 | 17 | quit -force 18 | -------------------------------------------------------------------------------- /pipeline/pipeline.ip_user_files/sim_scripts/data_mem/riviera/wave.do: -------------------------------------------------------------------------------- 1 | add wave * 2 | add wave /glbl/GSR 3 | -------------------------------------------------------------------------------- /pipeline/pipeline.ip_user_files/sim_scripts/data_mem/vcs/file_info.txt: -------------------------------------------------------------------------------- 1 | dist_mem_gen_v8_0.v,verilog,dist_mem_gen_v8_0_13,../../../ipstatic/simulation/dist_mem_gen_v8_0.v, 2 | data_mem.v,verilog,xil_defaultlib,../../../../pipeline.srcs/sources_1/ip/data_mem/sim/data_mem.v, 3 | glbl.v,Verilog,xil_defaultlib,glbl.v 4 | -------------------------------------------------------------------------------- /pipeline/pipeline.ip_user_files/sim_scripts/data_mem/vcs/simulate.do: -------------------------------------------------------------------------------- 1 | run 2 | quit 3 | -------------------------------------------------------------------------------- /pipeline/pipeline.ip_user_files/sim_scripts/data_mem/xcelium/file_info.txt: -------------------------------------------------------------------------------- 1 | dist_mem_gen_v8_0.v,verilog,dist_mem_gen_v8_0_13,../../../ipstatic/simulation/dist_mem_gen_v8_0.v, 2 | data_mem.v,verilog,xil_defaultlib,../../../../pipeline.srcs/sources_1/ip/data_mem/sim/data_mem.v, 3 | glbl.v,Verilog,xil_defaultlib,glbl.v 4 | -------------------------------------------------------------------------------- /pipeline/pipeline.ip_user_files/sim_scripts/data_mem/xcelium/run.f: -------------------------------------------------------------------------------- 1 | -makelib xcelium_lib/dist_mem_gen_v8_0_13 \ 2 | "../../../ipstatic/simulation/dist_mem_gen_v8_0.v" \ 3 | -endlib 4 | -makelib xcelium_lib/xil_defaultlib \ 5 | "../../../../pipeline.srcs/sources_1/ip/data_mem/sim/data_mem.v" \ 6 | -endlib 7 | -makelib xcelium_lib/xil_defaultlib \ 8 | glbl.v 9 | -endlib 10 | 11 | -------------------------------------------------------------------------------- /pipeline/pipeline.ip_user_files/sim_scripts/data_mem/xsim/cmd.tcl: -------------------------------------------------------------------------------- 1 | set curr_wave [current_wave_config] 2 | if { [string length $curr_wave] == 0 } { 3 | if { [llength [get_objects]] > 0} { 4 | add_wave / 5 | set_property needs_save false [current_wave_config] 6 | } else { 7 | send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." 8 | } 9 | } 10 | 11 | run -all 12 | quit 13 | -------------------------------------------------------------------------------- /pipeline/pipeline.ip_user_files/sim_scripts/data_mem/xsim/elab.opt: -------------------------------------------------------------------------------- 1 | --relax --debug typical --mt auto -L dist_mem_gen_v8_0_13 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot data_mem xil_defaultlib.data_mem xil_defaultlib.glbl -log elaborate.log 2 | -------------------------------------------------------------------------------- /pipeline/pipeline.ip_user_files/sim_scripts/data_mem/xsim/file_info.txt: -------------------------------------------------------------------------------- 1 | data_mem.v,verilog,xil_defaultlib,../../../../pipeline.srcs/sources_1/ip/data_mem/sim/data_mem.v, 2 | glbl.v,Verilog,xil_defaultlib,glbl.v 3 | -------------------------------------------------------------------------------- /pipeline/pipeline.ip_user_files/sim_scripts/data_mem/xsim/vlog.prj: -------------------------------------------------------------------------------- 1 | verilog xil_defaultlib \ 2 | "../../../../pipeline.srcs/sources_1/ip/data_mem/sim/data_mem.v" \ 3 | 4 | verilog xil_defaultlib "glbl.v" 5 | 6 | nosort 7 | -------------------------------------------------------------------------------- /pipeline/pipeline.ip_user_files/sim_scripts/inst_mem/activehdl/compile.do: -------------------------------------------------------------------------------- 1 | vlib work 2 | vlib activehdl 3 | 4 | vlib activehdl/dist_mem_gen_v8_0_13 5 | vlib activehdl/xil_defaultlib 6 | 7 | vmap dist_mem_gen_v8_0_13 activehdl/dist_mem_gen_v8_0_13 8 | vmap xil_defaultlib activehdl/xil_defaultlib 9 | 10 | vlog -work dist_mem_gen_v8_0_13 -v2k5 \ 11 | "../../../ipstatic/simulation/dist_mem_gen_v8_0.v" \ 12 | 13 | vlog -work xil_defaultlib -v2k5 \ 14 | "../../../../pipeline.srcs/sources_1/ip/inst_mem/sim/inst_mem.v" \ 15 | 16 | 17 | vlog -work xil_defaultlib \ 18 | "glbl.v" 19 | 20 | -------------------------------------------------------------------------------- /pipeline/pipeline.ip_user_files/sim_scripts/inst_mem/activehdl/file_info.txt: -------------------------------------------------------------------------------- 1 | dist_mem_gen_v8_0.v,verilog,dist_mem_gen_v8_0_13,../../../ipstatic/simulation/dist_mem_gen_v8_0.v, 2 | inst_mem.v,verilog,xil_defaultlib,../../../../pipeline.srcs/sources_1/ip/inst_mem/sim/inst_mem.v, 3 | glbl.v,Verilog,xil_defaultlib,glbl.v 4 | -------------------------------------------------------------------------------- /pipeline/pipeline.ip_user_files/sim_scripts/inst_mem/activehdl/inst_mem.udo: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/RegiaYoung/RISC-V-CPU/f410822af82f772b51abdce42b78c99bbe729cba/pipeline/pipeline.ip_user_files/sim_scripts/inst_mem/activehdl/inst_mem.udo -------------------------------------------------------------------------------- /pipeline/pipeline.ip_user_files/sim_scripts/inst_mem/activehdl/simulate.do: -------------------------------------------------------------------------------- 1 | onbreak {quit -force} 2 | onerror {quit -force} 3 | 4 | asim -t 1ps +access +r +m+inst_mem -L dist_mem_gen_v8_0_13 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.inst_mem xil_defaultlib.glbl 5 | 6 | do {wave.do} 7 | 8 | view wave 9 | view structure 10 | 11 | do {inst_mem.udo} 12 | 13 | run -all 14 | 15 | endsim 16 | 17 | quit -force 18 | -------------------------------------------------------------------------------- /pipeline/pipeline.ip_user_files/sim_scripts/inst_mem/activehdl/wave.do: -------------------------------------------------------------------------------- 1 | add wave * 2 | add wave /glbl/GSR 3 | -------------------------------------------------------------------------------- /pipeline/pipeline.ip_user_files/sim_scripts/inst_mem/ies/file_info.txt: -------------------------------------------------------------------------------- 1 | dist_mem_gen_v8_0.v,verilog,dist_mem_gen_v8_0_13,../../../ipstatic/simulation/dist_mem_gen_v8_0.v, 2 | inst_mem.v,verilog,xil_defaultlib,../../../../pipeline.srcs/sources_1/ip/inst_mem/sim/inst_mem.v, 3 | glbl.v,Verilog,xil_defaultlib,glbl.v 4 | -------------------------------------------------------------------------------- /pipeline/pipeline.ip_user_files/sim_scripts/inst_mem/ies/run.f: -------------------------------------------------------------------------------- 1 | -makelib ies_lib/dist_mem_gen_v8_0_13 \ 2 | "../../../ipstatic/simulation/dist_mem_gen_v8_0.v" \ 3 | -endlib 4 | -makelib ies_lib/xil_defaultlib \ 5 | "../../../../pipeline.srcs/sources_1/ip/inst_mem/sim/inst_mem.v" \ 6 | -endlib 7 | -makelib ies_lib/xil_defaultlib \ 8 | glbl.v 9 | -endlib 10 | 11 | -------------------------------------------------------------------------------- /pipeline/pipeline.ip_user_files/sim_scripts/inst_mem/modelsim/compile.do: -------------------------------------------------------------------------------- 1 | vlib modelsim_lib/work 2 | vlib modelsim_lib/msim 3 | 4 | vlib modelsim_lib/msim/dist_mem_gen_v8_0_13 5 | vlib modelsim_lib/msim/xil_defaultlib 6 | 7 | vmap dist_mem_gen_v8_0_13 modelsim_lib/msim/dist_mem_gen_v8_0_13 8 | vmap xil_defaultlib modelsim_lib/msim/xil_defaultlib 9 | 10 | vlog -work dist_mem_gen_v8_0_13 -64 -incr \ 11 | "../../../ipstatic/simulation/dist_mem_gen_v8_0.v" \ 12 | 13 | vlog -work xil_defaultlib -64 -incr \ 14 | "../../../../pipeline.srcs/sources_1/ip/inst_mem/sim/inst_mem.v" \ 15 | 16 | 17 | vlog -work xil_defaultlib \ 18 | "glbl.v" 19 | 20 | -------------------------------------------------------------------------------- /pipeline/pipeline.ip_user_files/sim_scripts/inst_mem/modelsim/file_info.txt: -------------------------------------------------------------------------------- 1 | dist_mem_gen_v8_0.v,verilog,dist_mem_gen_v8_0_13,../../../ipstatic/simulation/dist_mem_gen_v8_0.v, 2 | inst_mem.v,verilog,xil_defaultlib,../../../../pipeline.srcs/sources_1/ip/inst_mem/sim/inst_mem.v, 3 | glbl.v,Verilog,xil_defaultlib,glbl.v 4 | -------------------------------------------------------------------------------- /pipeline/pipeline.ip_user_files/sim_scripts/inst_mem/modelsim/inst_mem.udo: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/RegiaYoung/RISC-V-CPU/f410822af82f772b51abdce42b78c99bbe729cba/pipeline/pipeline.ip_user_files/sim_scripts/inst_mem/modelsim/inst_mem.udo -------------------------------------------------------------------------------- /pipeline/pipeline.ip_user_files/sim_scripts/inst_mem/modelsim/simulate.do: -------------------------------------------------------------------------------- 1 | onbreak {quit -f} 2 | onerror {quit -f} 3 | 4 | vsim -voptargs="+acc" -t 1ps -L dist_mem_gen_v8_0_13 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -lib xil_defaultlib xil_defaultlib.inst_mem xil_defaultlib.glbl 5 | 6 | do {wave.do} 7 | 8 | view wave 9 | view structure 10 | view signals 11 | 12 | do {inst_mem.udo} 13 | 14 | run -all 15 | 16 | quit -force 17 | -------------------------------------------------------------------------------- /pipeline/pipeline.ip_user_files/sim_scripts/inst_mem/modelsim/wave.do: -------------------------------------------------------------------------------- 1 | add wave * 2 | add wave /glbl/GSR 3 | -------------------------------------------------------------------------------- /pipeline/pipeline.ip_user_files/sim_scripts/inst_mem/questa/compile.do: -------------------------------------------------------------------------------- 1 | vlib questa_lib/work 2 | vlib questa_lib/msim 3 | 4 | vlib questa_lib/msim/dist_mem_gen_v8_0_13 5 | vlib questa_lib/msim/xil_defaultlib 6 | 7 | vmap dist_mem_gen_v8_0_13 questa_lib/msim/dist_mem_gen_v8_0_13 8 | vmap xil_defaultlib questa_lib/msim/xil_defaultlib 9 | 10 | vlog -work dist_mem_gen_v8_0_13 -64 \ 11 | "../../../ipstatic/simulation/dist_mem_gen_v8_0.v" \ 12 | 13 | vlog -work xil_defaultlib -64 \ 14 | "../../../../pipeline.srcs/sources_1/ip/inst_mem/sim/inst_mem.v" \ 15 | 16 | 17 | vlog -work xil_defaultlib \ 18 | "glbl.v" 19 | 20 | -------------------------------------------------------------------------------- /pipeline/pipeline.ip_user_files/sim_scripts/inst_mem/questa/elaborate.do: -------------------------------------------------------------------------------- 1 | vopt -64 +acc -l elaborate.log -L dist_mem_gen_v8_0_13 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -work xil_defaultlib xil_defaultlib.inst_mem xil_defaultlib.glbl -o inst_mem_opt 2 | -------------------------------------------------------------------------------- /pipeline/pipeline.ip_user_files/sim_scripts/inst_mem/questa/file_info.txt: -------------------------------------------------------------------------------- 1 | dist_mem_gen_v8_0.v,verilog,dist_mem_gen_v8_0_13,../../../ipstatic/simulation/dist_mem_gen_v8_0.v, 2 | inst_mem.v,verilog,xil_defaultlib,../../../../pipeline.srcs/sources_1/ip/inst_mem/sim/inst_mem.v, 3 | glbl.v,Verilog,xil_defaultlib,glbl.v 4 | -------------------------------------------------------------------------------- /pipeline/pipeline.ip_user_files/sim_scripts/inst_mem/questa/inst_mem.udo: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/RegiaYoung/RISC-V-CPU/f410822af82f772b51abdce42b78c99bbe729cba/pipeline/pipeline.ip_user_files/sim_scripts/inst_mem/questa/inst_mem.udo -------------------------------------------------------------------------------- /pipeline/pipeline.ip_user_files/sim_scripts/inst_mem/questa/simulate.do: -------------------------------------------------------------------------------- 1 | onbreak {quit -f} 2 | onerror {quit -f} 3 | 4 | vsim -t 1ps -lib xil_defaultlib inst_mem_opt 5 | 6 | do {wave.do} 7 | 8 | view wave 9 | view structure 10 | view signals 11 | 12 | do {inst_mem.udo} 13 | 14 | run -all 15 | 16 | quit -force 17 | -------------------------------------------------------------------------------- /pipeline/pipeline.ip_user_files/sim_scripts/inst_mem/questa/wave.do: -------------------------------------------------------------------------------- 1 | add wave * 2 | add wave /glbl/GSR 3 | -------------------------------------------------------------------------------- /pipeline/pipeline.ip_user_files/sim_scripts/inst_mem/riviera/compile.do: -------------------------------------------------------------------------------- 1 | vlib work 2 | vlib riviera 3 | 4 | vlib riviera/dist_mem_gen_v8_0_13 5 | vlib riviera/xil_defaultlib 6 | 7 | vmap dist_mem_gen_v8_0_13 riviera/dist_mem_gen_v8_0_13 8 | vmap xil_defaultlib riviera/xil_defaultlib 9 | 10 | vlog -work dist_mem_gen_v8_0_13 -v2k5 \ 11 | "../../../ipstatic/simulation/dist_mem_gen_v8_0.v" \ 12 | 13 | vlog -work xil_defaultlib -v2k5 \ 14 | "../../../../pipeline.srcs/sources_1/ip/inst_mem/sim/inst_mem.v" \ 15 | 16 | 17 | vlog -work xil_defaultlib \ 18 | "glbl.v" 19 | 20 | -------------------------------------------------------------------------------- /pipeline/pipeline.ip_user_files/sim_scripts/inst_mem/riviera/file_info.txt: -------------------------------------------------------------------------------- 1 | dist_mem_gen_v8_0.v,verilog,dist_mem_gen_v8_0_13,../../../ipstatic/simulation/dist_mem_gen_v8_0.v, 2 | inst_mem.v,verilog,xil_defaultlib,../../../../pipeline.srcs/sources_1/ip/inst_mem/sim/inst_mem.v, 3 | glbl.v,Verilog,xil_defaultlib,glbl.v 4 | -------------------------------------------------------------------------------- /pipeline/pipeline.ip_user_files/sim_scripts/inst_mem/riviera/inst_mem.udo: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/RegiaYoung/RISC-V-CPU/f410822af82f772b51abdce42b78c99bbe729cba/pipeline/pipeline.ip_user_files/sim_scripts/inst_mem/riviera/inst_mem.udo -------------------------------------------------------------------------------- /pipeline/pipeline.ip_user_files/sim_scripts/inst_mem/riviera/simulate.do: -------------------------------------------------------------------------------- 1 | onbreak {quit -force} 2 | onerror {quit -force} 3 | 4 | asim -t 1ps +access +r +m+inst_mem -L dist_mem_gen_v8_0_13 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.inst_mem xil_defaultlib.glbl 5 | 6 | do {wave.do} 7 | 8 | view wave 9 | view structure 10 | 11 | do {inst_mem.udo} 12 | 13 | run -all 14 | 15 | endsim 16 | 17 | quit -force 18 | -------------------------------------------------------------------------------- /pipeline/pipeline.ip_user_files/sim_scripts/inst_mem/riviera/wave.do: -------------------------------------------------------------------------------- 1 | add wave * 2 | add wave /glbl/GSR 3 | -------------------------------------------------------------------------------- /pipeline/pipeline.ip_user_files/sim_scripts/inst_mem/vcs/file_info.txt: -------------------------------------------------------------------------------- 1 | dist_mem_gen_v8_0.v,verilog,dist_mem_gen_v8_0_13,../../../ipstatic/simulation/dist_mem_gen_v8_0.v, 2 | inst_mem.v,verilog,xil_defaultlib,../../../../pipeline.srcs/sources_1/ip/inst_mem/sim/inst_mem.v, 3 | glbl.v,Verilog,xil_defaultlib,glbl.v 4 | -------------------------------------------------------------------------------- /pipeline/pipeline.ip_user_files/sim_scripts/inst_mem/vcs/simulate.do: -------------------------------------------------------------------------------- 1 | run 2 | quit 3 | -------------------------------------------------------------------------------- /pipeline/pipeline.ip_user_files/sim_scripts/inst_mem/xcelium/file_info.txt: -------------------------------------------------------------------------------- 1 | dist_mem_gen_v8_0.v,verilog,dist_mem_gen_v8_0_13,../../../ipstatic/simulation/dist_mem_gen_v8_0.v, 2 | inst_mem.v,verilog,xil_defaultlib,../../../../pipeline.srcs/sources_1/ip/inst_mem/sim/inst_mem.v, 3 | glbl.v,Verilog,xil_defaultlib,glbl.v 4 | -------------------------------------------------------------------------------- /pipeline/pipeline.ip_user_files/sim_scripts/inst_mem/xcelium/run.f: -------------------------------------------------------------------------------- 1 | -makelib xcelium_lib/dist_mem_gen_v8_0_13 \ 2 | "../../../ipstatic/simulation/dist_mem_gen_v8_0.v" \ 3 | -endlib 4 | -makelib xcelium_lib/xil_defaultlib \ 5 | "../../../../pipeline.srcs/sources_1/ip/inst_mem/sim/inst_mem.v" \ 6 | -endlib 7 | -makelib xcelium_lib/xil_defaultlib \ 8 | glbl.v 9 | -endlib 10 | 11 | -------------------------------------------------------------------------------- /pipeline/pipeline.ip_user_files/sim_scripts/inst_mem/xsim/cmd.tcl: -------------------------------------------------------------------------------- 1 | set curr_wave [current_wave_config] 2 | if { [string length $curr_wave] == 0 } { 3 | if { [llength [get_objects]] > 0} { 4 | add_wave / 5 | set_property needs_save false [current_wave_config] 6 | } else { 7 | send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." 8 | } 9 | } 10 | 11 | run -all 12 | quit 13 | -------------------------------------------------------------------------------- /pipeline/pipeline.ip_user_files/sim_scripts/inst_mem/xsim/elab.opt: -------------------------------------------------------------------------------- 1 | --relax --debug typical --mt auto -L dist_mem_gen_v8_0_13 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot inst_mem xil_defaultlib.inst_mem xil_defaultlib.glbl -log elaborate.log 2 | -------------------------------------------------------------------------------- /pipeline/pipeline.ip_user_files/sim_scripts/inst_mem/xsim/file_info.txt: -------------------------------------------------------------------------------- 1 | inst_mem.v,verilog,xil_defaultlib,../../../../pipeline.srcs/sources_1/ip/inst_mem/sim/inst_mem.v, 2 | glbl.v,Verilog,xil_defaultlib,glbl.v 3 | -------------------------------------------------------------------------------- /pipeline/pipeline.ip_user_files/sim_scripts/inst_mem/xsim/vlog.prj: -------------------------------------------------------------------------------- 1 | verilog xil_defaultlib \ 2 | "../../../../pipeline.srcs/sources_1/ip/inst_mem/sim/inst_mem.v" \ 3 | 4 | verilog xil_defaultlib "glbl.v" 5 | 6 | nosort 7 | -------------------------------------------------------------------------------- /pipeline/pipeline.runs/.jobs/vrs_config_1.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | -------------------------------------------------------------------------------- /pipeline/pipeline.runs/.jobs/vrs_config_2.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | -------------------------------------------------------------------------------- /pipeline/pipeline.runs/.jobs/vrs_config_3.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | -------------------------------------------------------------------------------- /pipeline/pipeline.runs/cpuclk_synth_1/.Vivado_Synthesis.queue.rst: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/RegiaYoung/RISC-V-CPU/f410822af82f772b51abdce42b78c99bbe729cba/pipeline/pipeline.runs/cpuclk_synth_1/.Vivado_Synthesis.queue.rst -------------------------------------------------------------------------------- /pipeline/pipeline.runs/cpuclk_synth_1/.Xil/cpuclk_propImpl.xdc: -------------------------------------------------------------------------------- 1 | set_property SRC_FILE_INFO {cfile:d:/STUDY/CPU/pipeline/pipeline.srcs/sources_1/ip/cpuclk/cpuclk.xdc rfile:../../../pipeline.srcs/sources_1/ip/cpuclk/cpuclk.xdc id:1 order:EARLY scoped_inst:inst} [current_design] 2 | current_instance inst 3 | set_property src_info {type:SCOPED_XDC file:1 line:57 export:INPUT save:INPUT read:READ} [current_design] 4 | set_input_jitter [get_clocks -of_objects [get_ports clk_in1]] 0.1 5 | -------------------------------------------------------------------------------- /pipeline/pipeline.runs/cpuclk_synth_1/.vivado.begin.rst: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | -------------------------------------------------------------------------------- /pipeline/pipeline.runs/cpuclk_synth_1/.vivado.end.rst: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/RegiaYoung/RISC-V-CPU/f410822af82f772b51abdce42b78c99bbe729cba/pipeline/pipeline.runs/cpuclk_synth_1/.vivado.end.rst -------------------------------------------------------------------------------- /pipeline/pipeline.runs/cpuclk_synth_1/__synthesis_is_complete__: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/RegiaYoung/RISC-V-CPU/f410822af82f772b51abdce42b78c99bbe729cba/pipeline/pipeline.runs/cpuclk_synth_1/__synthesis_is_complete__ -------------------------------------------------------------------------------- /pipeline/pipeline.runs/cpuclk_synth_1/cpuclk.dcp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/RegiaYoung/RISC-V-CPU/f410822af82f772b51abdce42b78c99bbe729cba/pipeline/pipeline.runs/cpuclk_synth_1/cpuclk.dcp -------------------------------------------------------------------------------- /pipeline/pipeline.runs/cpuclk_synth_1/cpuclk_utilization_synth.pb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/RegiaYoung/RISC-V-CPU/f410822af82f772b51abdce42b78c99bbe729cba/pipeline/pipeline.runs/cpuclk_synth_1/cpuclk_utilization_synth.pb -------------------------------------------------------------------------------- /pipeline/pipeline.runs/cpuclk_synth_1/htr.txt: -------------------------------------------------------------------------------- 1 | REM 2 | REM Vivado(TM) 3 | REM htr.txt: a Vivado-generated description of how-to-repeat the 4 | REM the basic steps of a run. Note that runme.bat/sh needs 5 | REM to be invoked for Vivado to track run status. 6 | REM Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 7 | REM 8 | 9 | vivado -log cpuclk.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source cpuclk.tcl 10 | -------------------------------------------------------------------------------- /pipeline/pipeline.runs/cpuclk_synth_1/rundef.js: -------------------------------------------------------------------------------- 1 | // 2 | // Vivado(TM) 3 | // rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6 4 | // Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 5 | // 6 | 7 | var WshShell = new ActiveXObject( "WScript.Shell" ); 8 | var ProcEnv = WshShell.Environment( "Process" ); 9 | var PathVal = ProcEnv("PATH"); 10 | if ( PathVal.length == 0 ) { 11 | PathVal = "D:/Applications/Vivado2020/Vivado/2019.2/ids_lite/ISE/bin/nt64;D:/Applications/Vivado2020/Vivado/2019.2/ids_lite/ISE/lib/nt64;D:/Applications/Vivado2020/Vivado/2019.2/bin;"; 12 | } else { 13 | PathVal = "D:/Applications/Vivado2020/Vivado/2019.2/ids_lite/ISE/bin/nt64;D:/Applications/Vivado2020/Vivado/2019.2/ids_lite/ISE/lib/nt64;D:/Applications/Vivado2020/Vivado/2019.2/bin;" + PathVal; 14 | } 15 | 16 | ProcEnv("PATH") = PathVal; 17 | 18 | var RDScrFP = WScript.ScriptFullName; 19 | var RDScrN = WScript.ScriptName; 20 | var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 ); 21 | var ISEJScriptLib = RDScrDir + "/ISEWrap.js"; 22 | eval( EAInclude(ISEJScriptLib) ); 23 | 24 | 25 | ISEStep( "vivado", 26 | "-log cpuclk.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source cpuclk.tcl" ); 27 | 28 | 29 | 30 | function EAInclude( EAInclFilename ) { 31 | var EAFso = new ActiveXObject( "Scripting.FileSystemObject" ); 32 | var EAInclFile = EAFso.OpenTextFile( EAInclFilename ); 33 | var EAIFContents = EAInclFile.ReadAll(); 34 | EAInclFile.Close(); 35 | return EAIFContents; 36 | } 37 | -------------------------------------------------------------------------------- /pipeline/pipeline.runs/cpuclk_synth_1/runme.bat: -------------------------------------------------------------------------------- 1 | @echo off 2 | 3 | rem Vivado (TM) 4 | rem runme.bat: a Vivado-generated Script 5 | rem Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 6 | 7 | 8 | set HD_SDIR=%~dp0 9 | cd /d "%HD_SDIR%" 10 | cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %* 11 | -------------------------------------------------------------------------------- /pipeline/pipeline.runs/cpuclk_synth_1/runme.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | # 4 | # Vivado(TM) 5 | # runme.sh: a Vivado-generated Runs Script for UNIX 6 | # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 7 | # 8 | 9 | echo "This script was generated under a different operating system." 10 | echo "Please update the PATH and LD_LIBRARY_PATH variables below, before executing this script" 11 | exit 12 | 13 | if [ -z "$PATH" ]; then 14 | PATH=D:/Applications/Vivado2020/Vivado/2019.2/ids_lite/ISE/bin/nt64;D:/Applications/Vivado2020/Vivado/2019.2/ids_lite/ISE/lib/nt64:D:/Applications/Vivado2020/Vivado/2019.2/bin 15 | else 16 | PATH=D:/Applications/Vivado2020/Vivado/2019.2/ids_lite/ISE/bin/nt64;D:/Applications/Vivado2020/Vivado/2019.2/ids_lite/ISE/lib/nt64:D:/Applications/Vivado2020/Vivado/2019.2/bin:$PATH 17 | fi 18 | export PATH 19 | 20 | if [ -z "$LD_LIBRARY_PATH" ]; then 21 | LD_LIBRARY_PATH= 22 | else 23 | LD_LIBRARY_PATH=:$LD_LIBRARY_PATH 24 | fi 25 | export LD_LIBRARY_PATH 26 | 27 | HD_PWD='D:/STUDY/CPU/pipeline/pipeline.runs/cpuclk_synth_1' 28 | cd "$HD_PWD" 29 | 30 | HD_LOG=runme.log 31 | /bin/touch $HD_LOG 32 | 33 | ISEStep="./ISEWrap.sh" 34 | EAStep() 35 | { 36 | $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1 37 | if [ $? -ne 0 ] 38 | then 39 | exit 40 | fi 41 | } 42 | 43 | EAStep vivado -log cpuclk.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source cpuclk.tcl 44 | -------------------------------------------------------------------------------- /pipeline/pipeline.runs/cpuclk_synth_1/vivado.jou: -------------------------------------------------------------------------------- 1 | #----------------------------------------------------------- 2 | # Vivado v2019.2 (64-bit) 3 | # SW Build 2708876 on Wed Nov 6 21:40:23 MST 2019 4 | # IP Build 2700528 on Thu Nov 7 00:09:20 MST 2019 5 | # Start of session at: Mon Sep 6 16:54:15 2021 6 | # Process ID: 15760 7 | # Current directory: D:/STUDY/CPU/pipeline/pipeline.runs/cpuclk_synth_1 8 | # Command line: vivado.exe -log cpuclk.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source cpuclk.tcl 9 | # Log file: D:/STUDY/CPU/pipeline/pipeline.runs/cpuclk_synth_1/cpuclk.vds 10 | # Journal file: D:/STUDY/CPU/pipeline/pipeline.runs/cpuclk_synth_1\vivado.jou 11 | #----------------------------------------------------------- 12 | source cpuclk.tcl -notrace 13 | -------------------------------------------------------------------------------- /pipeline/pipeline.runs/cpuclk_synth_1/vivado.pb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/RegiaYoung/RISC-V-CPU/f410822af82f772b51abdce42b78c99bbe729cba/pipeline/pipeline.runs/cpuclk_synth_1/vivado.pb -------------------------------------------------------------------------------- /pipeline/pipeline.runs/data_mem_synth_1/.Vivado_Synthesis.queue.rst: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/RegiaYoung/RISC-V-CPU/f410822af82f772b51abdce42b78c99bbe729cba/pipeline/pipeline.runs/data_mem_synth_1/.Vivado_Synthesis.queue.rst -------------------------------------------------------------------------------- /pipeline/pipeline.runs/data_mem_synth_1/.vivado.begin.rst: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | -------------------------------------------------------------------------------- /pipeline/pipeline.runs/data_mem_synth_1/.vivado.end.rst: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/RegiaYoung/RISC-V-CPU/f410822af82f772b51abdce42b78c99bbe729cba/pipeline/pipeline.runs/data_mem_synth_1/.vivado.end.rst -------------------------------------------------------------------------------- /pipeline/pipeline.runs/data_mem_synth_1/__synthesis_is_complete__: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/RegiaYoung/RISC-V-CPU/f410822af82f772b51abdce42b78c99bbe729cba/pipeline/pipeline.runs/data_mem_synth_1/__synthesis_is_complete__ -------------------------------------------------------------------------------- /pipeline/pipeline.runs/data_mem_synth_1/data_mem.dcp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/RegiaYoung/RISC-V-CPU/f410822af82f772b51abdce42b78c99bbe729cba/pipeline/pipeline.runs/data_mem_synth_1/data_mem.dcp -------------------------------------------------------------------------------- /pipeline/pipeline.runs/data_mem_synth_1/data_mem_utilization_synth.pb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/RegiaYoung/RISC-V-CPU/f410822af82f772b51abdce42b78c99bbe729cba/pipeline/pipeline.runs/data_mem_synth_1/data_mem_utilization_synth.pb -------------------------------------------------------------------------------- /pipeline/pipeline.runs/data_mem_synth_1/dont_touch.xdc: -------------------------------------------------------------------------------- 1 | # This file is automatically generated. 2 | # It contains project source information necessary for synthesis and implementation. 3 | 4 | # IP: d:/STUDY/CPU/pipeline/pipeline.srcs/sources_1/ip/data_mem/data_mem.xci 5 | # IP: The module: 'data_mem' is the root of the design. Do not add the DONT_TOUCH constraint. 6 | 7 | # XDC: d:/STUDY/CPU/pipeline/pipeline.srcs/sources_1/ip/data_mem/data_mem_ooc.xdc 8 | # XDC: The top module name and the constraint reference have the same name: 'data_mem'. Do not add the DONT_TOUCH constraint. 9 | set_property DONT_TOUCH TRUE [get_cells U0 -quiet] -quiet 10 | 11 | # IP: d:/STUDY/CPU/pipeline/pipeline.srcs/sources_1/ip/data_mem/data_mem.xci 12 | # IP: The module: 'data_mem' is the root of the design. Do not add the DONT_TOUCH constraint. 13 | 14 | # XDC: d:/STUDY/CPU/pipeline/pipeline.srcs/sources_1/ip/data_mem/data_mem_ooc.xdc 15 | # XDC: The top module name and the constraint reference have the same name: 'data_mem'. Do not add the DONT_TOUCH constraint. 16 | #dup# set_property DONT_TOUCH TRUE [get_cells U0 -quiet] -quiet 17 | -------------------------------------------------------------------------------- /pipeline/pipeline.runs/data_mem_synth_1/htr.txt: -------------------------------------------------------------------------------- 1 | REM 2 | REM Vivado(TM) 3 | REM htr.txt: a Vivado-generated description of how-to-repeat the 4 | REM the basic steps of a run. Note that runme.bat/sh needs 5 | REM to be invoked for Vivado to track run status. 6 | REM Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 7 | REM 8 | 9 | vivado -log data_mem.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source data_mem.tcl 10 | -------------------------------------------------------------------------------- /pipeline/pipeline.runs/data_mem_synth_1/rundef.js: -------------------------------------------------------------------------------- 1 | // 2 | // Vivado(TM) 3 | // rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6 4 | // Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 5 | // 6 | 7 | var WshShell = new ActiveXObject( "WScript.Shell" ); 8 | var ProcEnv = WshShell.Environment( "Process" ); 9 | var PathVal = ProcEnv("PATH"); 10 | if ( PathVal.length == 0 ) { 11 | PathVal = "D:/Applications/Vivado2020/Vivado/2019.2/ids_lite/ISE/bin/nt64;D:/Applications/Vivado2020/Vivado/2019.2/ids_lite/ISE/lib/nt64;D:/Applications/Vivado2020/Vivado/2019.2/bin;"; 12 | } else { 13 | PathVal = "D:/Applications/Vivado2020/Vivado/2019.2/ids_lite/ISE/bin/nt64;D:/Applications/Vivado2020/Vivado/2019.2/ids_lite/ISE/lib/nt64;D:/Applications/Vivado2020/Vivado/2019.2/bin;" + PathVal; 14 | } 15 | 16 | ProcEnv("PATH") = PathVal; 17 | 18 | var RDScrFP = WScript.ScriptFullName; 19 | var RDScrN = WScript.ScriptName; 20 | var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 ); 21 | var ISEJScriptLib = RDScrDir + "/ISEWrap.js"; 22 | eval( EAInclude(ISEJScriptLib) ); 23 | 24 | 25 | ISEStep( "vivado", 26 | "-log data_mem.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source data_mem.tcl" ); 27 | 28 | 29 | 30 | function EAInclude( EAInclFilename ) { 31 | var EAFso = new ActiveXObject( "Scripting.FileSystemObject" ); 32 | var EAInclFile = EAFso.OpenTextFile( EAInclFilename ); 33 | var EAIFContents = EAInclFile.ReadAll(); 34 | EAInclFile.Close(); 35 | return EAIFContents; 36 | } 37 | -------------------------------------------------------------------------------- /pipeline/pipeline.runs/data_mem_synth_1/runme.bat: -------------------------------------------------------------------------------- 1 | @echo off 2 | 3 | rem Vivado (TM) 4 | rem runme.bat: a Vivado-generated Script 5 | rem Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 6 | 7 | 8 | set HD_SDIR=%~dp0 9 | cd /d "%HD_SDIR%" 10 | cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %* 11 | -------------------------------------------------------------------------------- /pipeline/pipeline.runs/data_mem_synth_1/runme.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | # 4 | # Vivado(TM) 5 | # runme.sh: a Vivado-generated Runs Script for UNIX 6 | # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 7 | # 8 | 9 | echo "This script was generated under a different operating system." 10 | echo "Please update the PATH and LD_LIBRARY_PATH variables below, before executing this script" 11 | exit 12 | 13 | if [ -z "$PATH" ]; then 14 | PATH=D:/Applications/Vivado2020/Vivado/2019.2/ids_lite/ISE/bin/nt64;D:/Applications/Vivado2020/Vivado/2019.2/ids_lite/ISE/lib/nt64:D:/Applications/Vivado2020/Vivado/2019.2/bin 15 | else 16 | PATH=D:/Applications/Vivado2020/Vivado/2019.2/ids_lite/ISE/bin/nt64;D:/Applications/Vivado2020/Vivado/2019.2/ids_lite/ISE/lib/nt64:D:/Applications/Vivado2020/Vivado/2019.2/bin:$PATH 17 | fi 18 | export PATH 19 | 20 | if [ -z "$LD_LIBRARY_PATH" ]; then 21 | LD_LIBRARY_PATH= 22 | else 23 | LD_LIBRARY_PATH=:$LD_LIBRARY_PATH 24 | fi 25 | export LD_LIBRARY_PATH 26 | 27 | HD_PWD='D:/STUDY/CPU/pipeline/pipeline.runs/data_mem_synth_1' 28 | cd "$HD_PWD" 29 | 30 | HD_LOG=runme.log 31 | /bin/touch $HD_LOG 32 | 33 | ISEStep="./ISEWrap.sh" 34 | EAStep() 35 | { 36 | $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1 37 | if [ $? -ne 0 ] 38 | then 39 | exit 40 | fi 41 | } 42 | 43 | EAStep vivado -log data_mem.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source data_mem.tcl 44 | -------------------------------------------------------------------------------- /pipeline/pipeline.runs/data_mem_synth_1/vivado.jou: -------------------------------------------------------------------------------- 1 | #----------------------------------------------------------- 2 | # Vivado v2019.2 (64-bit) 3 | # SW Build 2708876 on Wed Nov 6 21:40:23 MST 2019 4 | # IP Build 2700528 on Thu Nov 7 00:09:20 MST 2019 5 | # Start of session at: Mon Sep 6 16:56:40 2021 6 | # Process ID: 19252 7 | # Current directory: D:/STUDY/CPU/pipeline/pipeline.runs/data_mem_synth_1 8 | # Command line: vivado.exe -log data_mem.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source data_mem.tcl 9 | # Log file: D:/STUDY/CPU/pipeline/pipeline.runs/data_mem_synth_1/data_mem.vds 10 | # Journal file: D:/STUDY/CPU/pipeline/pipeline.runs/data_mem_synth_1\vivado.jou 11 | #----------------------------------------------------------- 12 | source data_mem.tcl -notrace 13 | -------------------------------------------------------------------------------- /pipeline/pipeline.runs/data_mem_synth_1/vivado.pb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/RegiaYoung/RISC-V-CPU/f410822af82f772b51abdce42b78c99bbe729cba/pipeline/pipeline.runs/data_mem_synth_1/vivado.pb -------------------------------------------------------------------------------- /pipeline/pipeline.runs/inst_mem_synth_1/.Vivado_Synthesis.queue.rst: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/RegiaYoung/RISC-V-CPU/f410822af82f772b51abdce42b78c99bbe729cba/pipeline/pipeline.runs/inst_mem_synth_1/.Vivado_Synthesis.queue.rst -------------------------------------------------------------------------------- /pipeline/pipeline.runs/inst_mem_synth_1/.vivado.begin.rst: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | -------------------------------------------------------------------------------- /pipeline/pipeline.runs/inst_mem_synth_1/.vivado.end.rst: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/RegiaYoung/RISC-V-CPU/f410822af82f772b51abdce42b78c99bbe729cba/pipeline/pipeline.runs/inst_mem_synth_1/.vivado.end.rst -------------------------------------------------------------------------------- /pipeline/pipeline.runs/inst_mem_synth_1/__synthesis_is_complete__: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/RegiaYoung/RISC-V-CPU/f410822af82f772b51abdce42b78c99bbe729cba/pipeline/pipeline.runs/inst_mem_synth_1/__synthesis_is_complete__ -------------------------------------------------------------------------------- /pipeline/pipeline.runs/inst_mem_synth_1/dont_touch.xdc: -------------------------------------------------------------------------------- 1 | # This file is automatically generated. 2 | # It contains project source information necessary for synthesis and implementation. 3 | 4 | # IP: d:/STUDY/CPU/pipeline/pipeline.srcs/sources_1/ip/inst_mem/inst_mem.xci 5 | # IP: The module: 'inst_mem' is the root of the design. Do not add the DONT_TOUCH constraint. 6 | 7 | # XDC: d:/STUDY/CPU/pipeline/pipeline.srcs/sources_1/ip/inst_mem/inst_mem_ooc.xdc 8 | # XDC: The top module name and the constraint reference have the same name: 'inst_mem'. Do not add the DONT_TOUCH constraint. 9 | set_property DONT_TOUCH TRUE [get_cells U0 -quiet] -quiet 10 | 11 | # IP: d:/STUDY/CPU/pipeline/pipeline.srcs/sources_1/ip/inst_mem/inst_mem.xci 12 | # IP: The module: 'inst_mem' is the root of the design. Do not add the DONT_TOUCH constraint. 13 | 14 | # XDC: d:/STUDY/CPU/pipeline/pipeline.srcs/sources_1/ip/inst_mem/inst_mem_ooc.xdc 15 | # XDC: The top module name and the constraint reference have the same name: 'inst_mem'. Do not add the DONT_TOUCH constraint. 16 | #dup# set_property DONT_TOUCH TRUE [get_cells U0 -quiet] -quiet 17 | -------------------------------------------------------------------------------- /pipeline/pipeline.runs/inst_mem_synth_1/htr.txt: -------------------------------------------------------------------------------- 1 | REM 2 | REM Vivado(TM) 3 | REM htr.txt: a Vivado-generated description of how-to-repeat the 4 | REM the basic steps of a run. Note that runme.bat/sh needs 5 | REM to be invoked for Vivado to track run status. 6 | REM Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 7 | REM 8 | 9 | vivado -log inst_mem.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source inst_mem.tcl 10 | -------------------------------------------------------------------------------- /pipeline/pipeline.runs/inst_mem_synth_1/inst_mem.dcp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/RegiaYoung/RISC-V-CPU/f410822af82f772b51abdce42b78c99bbe729cba/pipeline/pipeline.runs/inst_mem_synth_1/inst_mem.dcp -------------------------------------------------------------------------------- /pipeline/pipeline.runs/inst_mem_synth_1/inst_mem_utilization_synth.pb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/RegiaYoung/RISC-V-CPU/f410822af82f772b51abdce42b78c99bbe729cba/pipeline/pipeline.runs/inst_mem_synth_1/inst_mem_utilization_synth.pb -------------------------------------------------------------------------------- /pipeline/pipeline.runs/inst_mem_synth_1/rundef.js: -------------------------------------------------------------------------------- 1 | // 2 | // Vivado(TM) 3 | // rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6 4 | // Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 5 | // 6 | 7 | var WshShell = new ActiveXObject( "WScript.Shell" ); 8 | var ProcEnv = WshShell.Environment( "Process" ); 9 | var PathVal = ProcEnv("PATH"); 10 | if ( PathVal.length == 0 ) { 11 | PathVal = "D:/Applications/Vivado2020/Vivado/2019.2/ids_lite/ISE/bin/nt64;D:/Applications/Vivado2020/Vivado/2019.2/ids_lite/ISE/lib/nt64;D:/Applications/Vivado2020/Vivado/2019.2/bin;"; 12 | } else { 13 | PathVal = "D:/Applications/Vivado2020/Vivado/2019.2/ids_lite/ISE/bin/nt64;D:/Applications/Vivado2020/Vivado/2019.2/ids_lite/ISE/lib/nt64;D:/Applications/Vivado2020/Vivado/2019.2/bin;" + PathVal; 14 | } 15 | 16 | ProcEnv("PATH") = PathVal; 17 | 18 | var RDScrFP = WScript.ScriptFullName; 19 | var RDScrN = WScript.ScriptName; 20 | var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 ); 21 | var ISEJScriptLib = RDScrDir + "/ISEWrap.js"; 22 | eval( EAInclude(ISEJScriptLib) ); 23 | 24 | 25 | ISEStep( "vivado", 26 | "-log inst_mem.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source inst_mem.tcl" ); 27 | 28 | 29 | 30 | function EAInclude( EAInclFilename ) { 31 | var EAFso = new ActiveXObject( "Scripting.FileSystemObject" ); 32 | var EAInclFile = EAFso.OpenTextFile( EAInclFilename ); 33 | var EAIFContents = EAInclFile.ReadAll(); 34 | EAInclFile.Close(); 35 | return EAIFContents; 36 | } 37 | -------------------------------------------------------------------------------- /pipeline/pipeline.runs/inst_mem_synth_1/runme.bat: -------------------------------------------------------------------------------- 1 | @echo off 2 | 3 | rem Vivado (TM) 4 | rem runme.bat: a Vivado-generated Script 5 | rem Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 6 | 7 | 8 | set HD_SDIR=%~dp0 9 | cd /d "%HD_SDIR%" 10 | cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %* 11 | -------------------------------------------------------------------------------- /pipeline/pipeline.runs/inst_mem_synth_1/runme.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | # 4 | # Vivado(TM) 5 | # runme.sh: a Vivado-generated Runs Script for UNIX 6 | # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 7 | # 8 | 9 | echo "This script was generated under a different operating system." 10 | echo "Please update the PATH and LD_LIBRARY_PATH variables below, before executing this script" 11 | exit 12 | 13 | if [ -z "$PATH" ]; then 14 | PATH=D:/Applications/Vivado2020/Vivado/2019.2/ids_lite/ISE/bin/nt64;D:/Applications/Vivado2020/Vivado/2019.2/ids_lite/ISE/lib/nt64:D:/Applications/Vivado2020/Vivado/2019.2/bin 15 | else 16 | PATH=D:/Applications/Vivado2020/Vivado/2019.2/ids_lite/ISE/bin/nt64;D:/Applications/Vivado2020/Vivado/2019.2/ids_lite/ISE/lib/nt64:D:/Applications/Vivado2020/Vivado/2019.2/bin:$PATH 17 | fi 18 | export PATH 19 | 20 | if [ -z "$LD_LIBRARY_PATH" ]; then 21 | LD_LIBRARY_PATH= 22 | else 23 | LD_LIBRARY_PATH=:$LD_LIBRARY_PATH 24 | fi 25 | export LD_LIBRARY_PATH 26 | 27 | HD_PWD='D:/STUDY/CPU/pipeline/pipeline.runs/inst_mem_synth_1' 28 | cd "$HD_PWD" 29 | 30 | HD_LOG=runme.log 31 | /bin/touch $HD_LOG 32 | 33 | ISEStep="./ISEWrap.sh" 34 | EAStep() 35 | { 36 | $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1 37 | if [ $? -ne 0 ] 38 | then 39 | exit 40 | fi 41 | } 42 | 43 | EAStep vivado -log inst_mem.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source inst_mem.tcl 44 | -------------------------------------------------------------------------------- /pipeline/pipeline.runs/inst_mem_synth_1/vivado.jou: -------------------------------------------------------------------------------- 1 | #----------------------------------------------------------- 2 | # Vivado v2019.2 (64-bit) 3 | # SW Build 2708876 on Wed Nov 6 21:40:23 MST 2019 4 | # IP Build 2700528 on Thu Nov 7 00:09:20 MST 2019 5 | # Start of session at: Mon Sep 6 16:55:58 2021 6 | # Process ID: 3888 7 | # Current directory: D:/STUDY/CPU/pipeline/pipeline.runs/inst_mem_synth_1 8 | # Command line: vivado.exe -log inst_mem.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source inst_mem.tcl 9 | # Log file: D:/STUDY/CPU/pipeline/pipeline.runs/inst_mem_synth_1/inst_mem.vds 10 | # Journal file: D:/STUDY/CPU/pipeline/pipeline.runs/inst_mem_synth_1\vivado.jou 11 | #----------------------------------------------------------- 12 | source inst_mem.tcl -notrace 13 | -------------------------------------------------------------------------------- /pipeline/pipeline.runs/inst_mem_synth_1/vivado.pb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/RegiaYoung/RISC-V-CPU/f410822af82f772b51abdce42b78c99bbe729cba/pipeline/pipeline.runs/inst_mem_synth_1/vivado.pb -------------------------------------------------------------------------------- /pipeline/pipeline.srcs/sources_1/imports/pipeline/adder_for_plus_4.v: -------------------------------------------------------------------------------- 1 | module adder_for_plus_4( 2 | input [31:0] pc_from_pc_i, 3 | output [31:0] pc_plus_4_o 4 | ); 5 | 6 | reg [31:0] pc_plus_4; 7 | assign pc_plus_4_o = pc_plus_4; 8 | always @ (*) 9 | begin 10 | pc_plus_4 = pc_from_pc_i + 4; 11 | end 12 | endmodule 13 | -------------------------------------------------------------------------------- /pipeline/pipeline.srcs/sources_1/imports/pipeline/algorithm_calculation.v: -------------------------------------------------------------------------------- 1 | 2 | module algorithm_calculation( 3 | input [3:0] algorithm_op_sel_i, 4 | input [31:0] operand_A_i, 5 | input [31:0] operand_B_i, 6 | output [31:0] result_from_algorithm_o 7 | ); 8 | 9 | 10 | 11 | reg [31:0] result; 12 | assign result_from_algorithm_o = result; 13 | always @ (*) 14 | begin 15 | case(algorithm_op_sel_i) 16 | `ADD: result = operand_A_i + operand_B_i; 17 | `SUB: result = operand_A_i + (operand_B_i ^ 32'b1111_1111_1111_1111_1111_1111_1111_1111) + 1'b1; 18 | default:result = 0; 19 | endcase 20 | end 21 | endmodule 22 | -------------------------------------------------------------------------------- /pipeline/pipeline.srcs/sources_1/imports/pipeline/branch_compare.v: -------------------------------------------------------------------------------- 1 | module branch_compare( 2 | input [31:0] data1_from_rf_i, 3 | input [31:0] data2_from_rf_i, 4 | output [1:0] cmp_result_from_branch_o, 5 | input [2:0] func3 6 | ); 7 | 8 | reg [1:0] cmp_result_from_branch; 9 | assign cmp_result_from_branch_o = cmp_result_from_branch; 10 | always @ (*) 11 | begin 12 | if (func3 == 3'b110 || func3 == 3'b111) cmp_result_from_branch = ((~(data1_from_rf_i < data2_from_rf_i)) ? 2'b01 : 2'b10); 13 | else if (($signed(data1_from_rf_i)) == ($signed(data2_from_rf_i))) cmp_result_from_branch = 2'b00; 14 | else if (($signed(data1_from_rf_i)) > ($signed(data2_from_rf_i))) cmp_result_from_branch = 2'b01; 15 | else cmp_result_from_branch = 2'b10; 16 | end 17 | endmodule 18 | -------------------------------------------------------------------------------- /pipeline/pipeline.srcs/sources_1/imports/pipeline/hazard_detection_unit.v: -------------------------------------------------------------------------------- 1 | module hazard_detection_unit( 2 | input rst_n, 3 | input clk_i, 4 | input [31:0] instruction_from_preg1_i, 5 | input [4:0] rd_from_ID_EX_i, 6 | input [4:0] rs1_from_IF_ID_i, 7 | input [4:0] rs2_from_IF_ID_i, 8 | output lw_stall_o 9 | ); 10 | reg lw_stall; 11 | // stop for 2 cycles 12 | reg counter = 0; 13 | always @ (posedge clk_i) 14 | begin 15 | if (~rst_n) 16 | counter <= 0; 17 | else if (lw_stall) 18 | counter <= counter + 1; 19 | else 20 | counter <= 0; 21 | end 22 | 23 | reg [1:0] stop_for_2_cycles = 0; 24 | always @ (posedge clk_i) 25 | begin 26 | if (~rst_n) 27 | stop_for_2_cycles <= 0; 28 | else if (instruction_from_preg1_i[6:0] == 7'b0000011 && instruction_from_preg1_i[14:12] != 3'b010) 29 | stop_for_2_cycles <= stop_for_2_cycles + 1; 30 | else if (stop_for_2_cycles == 1) 31 | stop_for_2_cycles <= stop_for_2_cycles + 1; 32 | else 33 | stop_for_2_cycles <= 0; 34 | end 35 | always @ (posedge clk_i) 36 | begin 37 | 38 | end 39 | assign lw_stall_o = lw_stall; 40 | always @ (*) 41 | begin 42 | if (~rst_n) 43 | lw_stall = 0; 44 | else if (stop_for_2_cycles) 45 | lw_stall = 1; 46 | else if (counter) 47 | lw_stall = 0; 48 | else if (instruction_from_preg1_i[6:2] != 5'b00000) 49 | lw_stall = 0; 50 | else if (rd_from_ID_EX_i == 0) 51 | lw_stall = 0; 52 | else if (rd_from_ID_EX_i == rs1_from_IF_ID_i || rd_from_ID_EX_i == rs2_from_IF_ID_i) 53 | lw_stall = 1; 54 | else 55 | lw_stall = 0; 56 | end 57 | 58 | endmodule 59 | 60 | -------------------------------------------------------------------------------- /pipeline/pipeline.srcs/sources_1/imports/pipeline/j_format_stall.v: -------------------------------------------------------------------------------- 1 | module j_format_stall( 2 | input rst_n, 3 | input bstall_i, 4 | input clk_i, 5 | input [31:0] instruction_from_preg1_i, 6 | input [31:0] instruction_from_preg0_i, 7 | output jstall_o 8 | ); 9 | reg stall; 10 | assign jstall_o = stall; 11 | reg [2:0] counter = 0; 12 | // stop for 3 cycles 13 | always @ (posedge clk_i) 14 | begin 15 | if (~rst_n) 16 | counter <= 0; 17 | else if (counter == 1) 18 | counter <= 0; 19 | else if (stall) 20 | counter <= counter + 1; 21 | else 22 | counter <= 0; 23 | end 24 | // stop for 3 cycles 25 | always @ (*) 26 | begin 27 | if (~rst_n) 28 | stall = 0; 29 | else if (bstall_i) 30 | stall = 0; 31 | else if (instruction_from_preg1_i[6:2] == 5'b11000) 32 | stall = 0; 33 | else if (instruction_from_preg0_i[6:2] == 5'b11011 || instruction_from_preg0_i[6:2] == 5'b11001) 34 | stall = 1; 35 | else if (counter != 0) 36 | stall = 1; 37 | else 38 | stall = 0; 39 | end 40 | endmodule 41 | -------------------------------------------------------------------------------- /pipeline/pipeline.srcs/sources_1/imports/pipeline/logic_calculation.v: -------------------------------------------------------------------------------- 1 | 2 | module logic_calculation( 3 | input [3:0] logic_op_sel_i, 4 | input [31:0] operand_A_i, 5 | input [31:0] operand_B_i, 6 | output [31:0] result_from_logic_o 7 | ); 8 | 9 | 10 | reg [31:0] result; 11 | assign result_from_logic_o = result; 12 | always @ (*) 13 | begin 14 | case(logic_op_sel_i) 15 | `AND: result = operand_A_i & operand_B_i; 16 | `OR: result = operand_A_i | operand_B_i; 17 | `XOR: result = operand_A_i ^ operand_B_i; 18 | default:result = 0; 19 | endcase 20 | end 21 | endmodule 22 | -------------------------------------------------------------------------------- /pipeline/pipeline.srcs/sources_1/imports/pipeline/mux_3.v: -------------------------------------------------------------------------------- 1 | module mux_3( 2 | input [1:0] select_signal, 3 | input [31:0] input0, 4 | input [31:0] input1, 5 | input [31:0] input2, 6 | output [31:0] output_data 7 | ); 8 | 9 | reg [31:0] output_reg; 10 | assign output_data = output_reg; 11 | always @ (*) 12 | begin 13 | case(select_signal) 14 | 2'b00: output_reg = input0; 15 | 2'b01: output_reg = input1; 16 | 2'b10: output_reg = input2; 17 | default: output_reg = input0; 18 | endcase 19 | end 20 | endmodule 21 | -------------------------------------------------------------------------------- /pipeline/pipeline.srcs/sources_1/imports/pipeline/mux_5.v: -------------------------------------------------------------------------------- 1 | module mux_5( 2 | input [2:0] select_signal, 3 | input [31:0] input0, 4 | input [31:0] input1, 5 | input [31:0] input2, 6 | input [31:0] input3, 7 | input [31:0] input4, 8 | output [31:0] output_data 9 | ); 10 | reg [31:0] result; 11 | assign output_data = result; 12 | always @ (*) 13 | begin 14 | case(select_signal) 15 | 3'b000: result = input0; 16 | 3'b001: result = input1; 17 | 3'b010: result = input2; 18 | 3'b011: result = input3; 19 | 3'b100: result = input4; 20 | default:result = input0; 21 | endcase 22 | end 23 | endmodule 24 | -------------------------------------------------------------------------------- /pipeline/pipeline.srcs/sources_1/imports/pipeline/mux_6.v: -------------------------------------------------------------------------------- 1 | module mux_6( 2 | input [2:0] select_signal, 3 | input [31:0] input0, 4 | input [31:0] input1, 5 | input [31:0] input2, 6 | input [31:0] input3, 7 | input [31:0] input4, 8 | input [31:0] input5, 9 | output [31:0] output_data 10 | ); 11 | reg [31:0] result; 12 | assign output_data = result; 13 | always @ (*) 14 | begin 15 | case(select_signal) 16 | 3'b000: result = input0; 17 | 3'b001: result = input1; 18 | 3'b010: result = input2; 19 | 3'b011: result = input3; 20 | 3'b100: result = input4; 21 | 3'b101: result = input5; 22 | default:result = input0; 23 | endcase 24 | end 25 | endmodule 26 | -------------------------------------------------------------------------------- /pipeline/pipeline.srcs/sources_1/imports/pipeline/mux_7.v: -------------------------------------------------------------------------------- 1 | module mux_7( 2 | input [2:0] select_signal, 3 | input [31:0] input0, 4 | input [31:0] input1, 5 | input [31:0] input2, 6 | input [31:0] input3, 7 | input [31:0] input4, 8 | input [31:0] input5, 9 | input [31:0] input6, 10 | output [31:0] output_data 11 | ); 12 | reg [31:0] result; 13 | assign output_data = result; 14 | always @ (*) 15 | begin 16 | case(select_signal) 17 | 3'b000: result = input0; 18 | 3'b001: result = input1; 19 | 3'b010: result = input2; 20 | 3'b011: result = input3; 21 | 3'b100: result = input4; 22 | 3'b101: result = input5; 23 | 3'b110: result = input6; 24 | default:result = input0; 25 | endcase 26 | end 27 | endmodule 28 | -------------------------------------------------------------------------------- /pipeline/pipeline.srcs/sources_1/imports/pipeline/param.v: -------------------------------------------------------------------------------- 1 | // file: param.v 2 | `ifndef CPU_PARAM 3 | `define CPU_PARAM 4 | 5 | `define ADD 4'b0000 6 | `define SUB 4'b0001 7 | `define AND 4'b0010 8 | `define OR 4'b0011 9 | `define XOR 4'b0100 10 | `define SLL 4'b0101 11 | `define SRL 4'b0110 12 | `define SRA 4'b0111 13 | 14 | `define SLT 4'b1000 15 | `define SLTU 4'b1001 16 | `define SLTI 4'b1010 17 | `define SLTIU 4'b1011 18 | 19 | `endif 20 | -------------------------------------------------------------------------------- /pipeline/pipeline.srcs/sources_1/imports/pipeline/program_counter.v: -------------------------------------------------------------------------------- 1 | module program_counter( 2 | input clk_i, 3 | input reset_i, 4 | input stall_i, 5 | input [31:0] next_pc_i, 6 | output [31:0] pc_o 7 | ); 8 | reg [31:0] pc; 9 | assign pc_o = pc; 10 | 11 | always @ (posedge clk_i or posedge reset_i) 12 | begin 13 | if (reset_i) pc <= 'hffff_fffc; 14 | else if (stall_i) pc <= pc; 15 | else pc <= next_pc_i; 16 | end 17 | 18 | 19 | endmodule 20 | -------------------------------------------------------------------------------- /pipeline/pipeline.srcs/sources_1/imports/pipeline/reg_file.v: -------------------------------------------------------------------------------- 1 | module reg_file( 2 | input clk_i, 3 | input [4:0] rR1_i, 4 | input [4:0] rR2_i, 5 | input [4:0] wR_i, 6 | input WE_i, 7 | input [31:0] wD_i, 8 | output [31:0] rD1_o, 9 | output [31:0] rD2_o 10 | ); 11 | 12 | reg [31:0] register [0:31]; 13 | reg [31:0] data1; 14 | reg [31:0] data2; 15 | assign rD1_o = data1; 16 | assign rD2_o = data2; 17 | 18 | // read logic 19 | always @ (*) 20 | begin 21 | data1 = register[rR1_i]; 22 | data2 = register[rR2_i]; 23 | end 24 | 25 | // write logic 26 | always @ (posedge clk_i) 27 | begin 28 | register[0] <= 0; 29 | if (WE_i && wR_i != 0) 30 | register[wR_i] <= wD_i; 31 | end 32 | 33 | endmodule 34 | -------------------------------------------------------------------------------- /pipeline/pipeline.srcs/sources_1/imports/pipeline/reg_for_inst_before_LW.v: -------------------------------------------------------------------------------- 1 | module reg_for_inst_before_LW( 2 | input rst_n, 3 | input clk_i, 4 | input [31:0] instruction_from_preg3_i, 5 | output [31:0] instruction_before_o 6 | ); 7 | reg [31:0] instruction_before; 8 | assign instruction_before_o = instruction_before; 9 | always @ (posedge clk_i) 10 | begin 11 | if (~rst_n) 12 | instruction_before <= 0; 13 | else 14 | instruction_before <= instruction_from_preg3_i; 15 | end 16 | 17 | endmodule 18 | -------------------------------------------------------------------------------- /pipeline/pipeline.srcs/sources_1/imports/pipeline/top.v: -------------------------------------------------------------------------------- 1 | module top( 2 | input clk, 3 | input rst_n, 4 | output debug_wb_have_inst, 5 | output [31:0] debug_wb_pc, 6 | output debug_wb_ena, 7 | output [4:0] debug_wb_reg, 8 | output [31:0] debug_wb_value 9 | 10 | ); 11 | 12 | wire [31:0] pc_from_pc; 13 | wire [31:0] instruction_from_irom; 14 | wire [31:0] addr_i; 15 | wire [31:0] rd_data_o; 16 | wire mem_wr_i; 17 | wire [31:0] wr_data_i; 18 | 19 | inst_mem U0_irom ( 20 | .a(pc_from_pc[15:2]), // input wire [13:0] a 21 | .spo(instruction_from_irom) // output wire [31:0] spo 22 | ); 23 | 24 | wire ram_clk; // reverse clk for Data RAM 25 | assign ram_clk = !clk; 26 | data_mem U_dram ( 27 | .clk (ram_clk), // input wire clka 28 | .a (addr_i[15:2]), // input wire [13:0] addra 29 | .spo (rd_data_o), // output wire [31:0] douta 30 | .we (memwr_i), // input wire [0:0] wea 31 | .d (wr_data_i) // input wire [31:0] dina 32 | ); 33 | 34 | mini_rv U_mini_rv( 35 | .rst_n(rst_n), 36 | .clk(clk), 37 | .debug_wb_have_inst(debug_wb_have_inst), 38 | .debug_wb_pc(debug_wb_pc), 39 | .debug_wb_ena(debug_wb_ena), 40 | .debug_wb_reg(debug_wb_reg), 41 | .debug_wb_value(debug_wb_value), 42 | 43 | 44 | .pc_from_pc_o(pc_from_pc), 45 | .instruction_from_irom(instruction_from_irom), 46 | .addr_i(addr_i), 47 | .rd_data_o(rd_data_o), 48 | .memwr_i(memwr_i), 49 | .wr_data_i(wr_data_i) 50 | 51 | ); 52 | endmodule 53 | 54 | -------------------------------------------------------------------------------- /pipeline/pipeline.srcs/sources_1/imports/pipeline/wb_value_recorder.v: -------------------------------------------------------------------------------- 1 | module wb_value_recorder( 2 | input rst_n, 3 | input clk_i, 4 | input [31:0] wb_value_i, 5 | output [31:0] wb_value_3_o, 6 | output [31:0] wb_value_2_o, 7 | output [31:0] wb_value_1_o, 8 | output [31:0] wb_value_0_o 9 | ); 10 | 11 | reg [31:0] wb_value_3; 12 | reg [31:0] wb_value_2; 13 | reg [31:0] wb_value_1; 14 | assign wb_value_3_o = wb_value_3; 15 | assign wb_value_2_o = wb_value_2; 16 | assign wb_value_1_o = wb_value_1; 17 | assign wb_value_0_o = wb_value_i; 18 | 19 | always @ (posedge clk_i) 20 | begin 21 | if (~rst_n) 22 | begin 23 | wb_value_3 <= 0; 24 | wb_value_2 <= 0; 25 | wb_value_1 <= 0; 26 | end 27 | else 28 | begin 29 | wb_value_3 <= wb_value_2; 30 | wb_value_2 <= wb_value_1; 31 | wb_value_1 <= wb_value_i; 32 | end 33 | end 34 | endmodule 35 | 36 | -------------------------------------------------------------------------------- /pipeline/pipeline.srcs/sources_1/ip/cpuclk/cpuclk.dcp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/RegiaYoung/RISC-V-CPU/f410822af82f772b51abdce42b78c99bbe729cba/pipeline/pipeline.srcs/sources_1/ip/cpuclk/cpuclk.dcp -------------------------------------------------------------------------------- /pipeline/pipeline.srcs/sources_1/ip/cpuclk/cpuclk_board.xdc: -------------------------------------------------------------------------------- 1 | #--------------------Physical Constraints----------------- 2 | 3 | -------------------------------------------------------------------------------- /pipeline/pipeline.srcs/sources_1/ip/cpuclk/cpuclk_stub.v: -------------------------------------------------------------------------------- 1 | // Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 2 | // -------------------------------------------------------------------------------- 3 | // Tool Version: Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019 4 | // Date : Mon Sep 6 16:54:58 2021 5 | // Host : DESKTOP-S2SIT85 running 64-bit major release (build 9200) 6 | // Command : write_verilog -force -mode synth_stub 7 | // d:/STUDY/CPU/pipeline/pipeline.srcs/sources_1/ip/cpuclk/cpuclk_stub.v 8 | // Design : cpuclk 9 | // Purpose : Stub declaration of top-level module interface 10 | // Device : xc7a100tfgg484-1 11 | // -------------------------------------------------------------------------------- 12 | 13 | // This empty module with port declaration file causes synthesis tools to infer a black box for IP. 14 | // The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. 15 | // Please paste the declaration into a Verilog source file or add the file as an additional source. 16 | module cpuclk(clk_out1, locked, clk_in1) 17 | /* synthesis syn_black_box black_box_pad_pin="clk_out1,locked,clk_in1" */; 18 | output clk_out1; 19 | output locked; 20 | input clk_in1; 21 | endmodule 22 | -------------------------------------------------------------------------------- /pipeline/pipeline.srcs/sources_1/ip/cpuclk/cpuclk_stub.vhdl: -------------------------------------------------------------------------------- 1 | -- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 2 | -- -------------------------------------------------------------------------------- 3 | -- Tool Version: Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019 4 | -- Date : Mon Sep 6 16:54:58 2021 5 | -- Host : DESKTOP-S2SIT85 running 64-bit major release (build 9200) 6 | -- Command : write_vhdl -force -mode synth_stub 7 | -- d:/STUDY/CPU/pipeline/pipeline.srcs/sources_1/ip/cpuclk/cpuclk_stub.vhdl 8 | -- Design : cpuclk 9 | -- Purpose : Stub declaration of top-level module interface 10 | -- Device : xc7a100tfgg484-1 11 | -- -------------------------------------------------------------------------------- 12 | library IEEE; 13 | use IEEE.STD_LOGIC_1164.ALL; 14 | 15 | entity cpuclk is 16 | Port ( 17 | clk_out1 : out STD_LOGIC; 18 | locked : out STD_LOGIC; 19 | clk_in1 : in STD_LOGIC 20 | ); 21 | 22 | end cpuclk; 23 | 24 | architecture stub of cpuclk is 25 | attribute syn_black_box : boolean; 26 | attribute black_box_pad_pin : string; 27 | attribute syn_black_box of stub : architecture is true; 28 | attribute black_box_pad_pin of stub : architecture is "clk_out1,locked,clk_in1"; 29 | begin 30 | end; 31 | -------------------------------------------------------------------------------- /pipeline/pipeline.srcs/sources_1/ip/data_mem/data_mem.dcp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/RegiaYoung/RISC-V-CPU/f410822af82f772b51abdce42b78c99bbe729cba/pipeline/pipeline.srcs/sources_1/ip/data_mem/data_mem.dcp -------------------------------------------------------------------------------- /pipeline/pipeline.srcs/sources_1/ip/data_mem/data_mem_stub.v: -------------------------------------------------------------------------------- 1 | // Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 2 | // -------------------------------------------------------------------------------- 3 | // Tool Version: Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019 4 | // Date : Mon Sep 6 16:57:54 2021 5 | // Host : DESKTOP-S2SIT85 running 64-bit major release (build 9200) 6 | // Command : write_verilog -force -mode synth_stub 7 | // d:/STUDY/CPU/pipeline/pipeline.srcs/sources_1/ip/data_mem/data_mem_stub.v 8 | // Design : data_mem 9 | // Purpose : Stub declaration of top-level module interface 10 | // Device : xc7a100tfgg484-1 11 | // -------------------------------------------------------------------------------- 12 | 13 | // This empty module with port declaration file causes synthesis tools to infer a black box for IP. 14 | // The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. 15 | // Please paste the declaration into a Verilog source file or add the file as an additional source. 16 | (* x_core_info = "dist_mem_gen_v8_0_13,Vivado 2019.2" *) 17 | module data_mem(a, d, clk, we, spo) 18 | /* synthesis syn_black_box black_box_pad_pin="a[13:0],d[31:0],clk,we,spo[31:0]" */; 19 | input [13:0]a; 20 | input [31:0]d; 21 | input clk; 22 | input we; 23 | output [31:0]spo; 24 | endmodule 25 | -------------------------------------------------------------------------------- /pipeline/pipeline.srcs/sources_1/ip/data_mem/data_mem_stub.vhdl: -------------------------------------------------------------------------------- 1 | -- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 2 | -- -------------------------------------------------------------------------------- 3 | -- Tool Version: Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019 4 | -- Date : Mon Sep 6 16:57:54 2021 5 | -- Host : DESKTOP-S2SIT85 running 64-bit major release (build 9200) 6 | -- Command : write_vhdl -force -mode synth_stub 7 | -- d:/STUDY/CPU/pipeline/pipeline.srcs/sources_1/ip/data_mem/data_mem_stub.vhdl 8 | -- Design : data_mem 9 | -- Purpose : Stub declaration of top-level module interface 10 | -- Device : xc7a100tfgg484-1 11 | -- -------------------------------------------------------------------------------- 12 | library IEEE; 13 | use IEEE.STD_LOGIC_1164.ALL; 14 | 15 | entity data_mem is 16 | Port ( 17 | a : in STD_LOGIC_VECTOR ( 13 downto 0 ); 18 | d : in STD_LOGIC_VECTOR ( 31 downto 0 ); 19 | clk : in STD_LOGIC; 20 | we : in STD_LOGIC; 21 | spo : out STD_LOGIC_VECTOR ( 31 downto 0 ) 22 | ); 23 | 24 | end data_mem; 25 | 26 | architecture stub of data_mem is 27 | attribute syn_black_box : boolean; 28 | attribute black_box_pad_pin : string; 29 | attribute syn_black_box of stub : architecture is true; 30 | attribute black_box_pad_pin of stub : architecture is "a[13:0],d[31:0],clk,we,spo[31:0]"; 31 | attribute x_core_info : string; 32 | attribute x_core_info of stub : architecture is "dist_mem_gen_v8_0_13,Vivado 2019.2"; 33 | begin 34 | end; 35 | -------------------------------------------------------------------------------- /pipeline/pipeline.srcs/sources_1/ip/inst_mem/inst_mem.dcp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/RegiaYoung/RISC-V-CPU/f410822af82f772b51abdce42b78c99bbe729cba/pipeline/pipeline.srcs/sources_1/ip/inst_mem/inst_mem.dcp -------------------------------------------------------------------------------- /pipeline/pipeline.srcs/sources_1/ip/inst_mem/inst_mem_stub.v: -------------------------------------------------------------------------------- 1 | // Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 2 | // -------------------------------------------------------------------------------- 3 | // Tool Version: Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019 4 | // Date : Mon Sep 6 16:57:01 2021 5 | // Host : DESKTOP-S2SIT85 running 64-bit major release (build 9200) 6 | // Command : write_verilog -force -mode synth_stub 7 | // d:/STUDY/CPU/pipeline/pipeline.srcs/sources_1/ip/inst_mem/inst_mem_stub.v 8 | // Design : inst_mem 9 | // Purpose : Stub declaration of top-level module interface 10 | // Device : xc7a100tfgg484-1 11 | // -------------------------------------------------------------------------------- 12 | 13 | // This empty module with port declaration file causes synthesis tools to infer a black box for IP. 14 | // The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. 15 | // Please paste the declaration into a Verilog source file or add the file as an additional source. 16 | (* x_core_info = "dist_mem_gen_v8_0_13,Vivado 2019.2" *) 17 | module inst_mem(a, spo) 18 | /* synthesis syn_black_box black_box_pad_pin="a[13:0],spo[31:0]" */; 19 | input [13:0]a; 20 | output [31:0]spo; 21 | endmodule 22 | -------------------------------------------------------------------------------- /pipeline/pipeline.srcs/sources_1/ip/inst_mem/inst_mem_stub.vhdl: -------------------------------------------------------------------------------- 1 | -- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 2 | -- -------------------------------------------------------------------------------- 3 | -- Tool Version: Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019 4 | -- Date : Mon Sep 6 16:57:01 2021 5 | -- Host : DESKTOP-S2SIT85 running 64-bit major release (build 9200) 6 | -- Command : write_vhdl -force -mode synth_stub 7 | -- d:/STUDY/CPU/pipeline/pipeline.srcs/sources_1/ip/inst_mem/inst_mem_stub.vhdl 8 | -- Design : inst_mem 9 | -- Purpose : Stub declaration of top-level module interface 10 | -- Device : xc7a100tfgg484-1 11 | -- -------------------------------------------------------------------------------- 12 | library IEEE; 13 | use IEEE.STD_LOGIC_1164.ALL; 14 | 15 | entity inst_mem is 16 | Port ( 17 | a : in STD_LOGIC_VECTOR ( 13 downto 0 ); 18 | spo : out STD_LOGIC_VECTOR ( 31 downto 0 ) 19 | ); 20 | 21 | end inst_mem; 22 | 23 | architecture stub of inst_mem is 24 | attribute syn_black_box : boolean; 25 | attribute black_box_pad_pin : string; 26 | attribute syn_black_box of stub : architecture is true; 27 | attribute black_box_pad_pin of stub : architecture is "a[13:0],spo[31:0]"; 28 | attribute x_core_info : string; 29 | attribute x_core_info of stub : architecture is "dist_mem_gen_v8_0_13,Vivado 2019.2"; 30 | begin 31 | end; 32 | -------------------------------------------------------------------------------- /single/single.cache/ip/2019.2/ac4765ccab3a8c3a/data_mem.dcp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/RegiaYoung/RISC-V-CPU/f410822af82f772b51abdce42b78c99bbe729cba/single/single.cache/ip/2019.2/ac4765ccab3a8c3a/data_mem.dcp -------------------------------------------------------------------------------- /single/single.cache/ip/2019.2/ac4765ccab3a8c3a/data_mem_stub.v: -------------------------------------------------------------------------------- 1 | // Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 2 | // -------------------------------------------------------------------------------- 3 | // Tool Version: Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019 4 | // Date : Mon Sep 6 16:57:18 2021 5 | // Host : DESKTOP-S2SIT85 running 64-bit major release (build 9200) 6 | // Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix 7 | // decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ data_mem_stub.v 8 | // Design : data_mem 9 | // Purpose : Stub declaration of top-level module interface 10 | // Device : xc7a100tfgg484-1 11 | // -------------------------------------------------------------------------------- 12 | 13 | // This empty module with port declaration file causes synthesis tools to infer a black box for IP. 14 | // The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. 15 | // Please paste the declaration into a Verilog source file or add the file as an additional source. 16 | (* x_core_info = "dist_mem_gen_v8_0_13,Vivado 2019.2" *) 17 | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(a, d, clk, we, spo) 18 | /* synthesis syn_black_box black_box_pad_pin="a[13:0],d[31:0],clk,we,spo[31:0]" */; 19 | input [13:0]a; 20 | input [31:0]d; 21 | input clk; 22 | input we; 23 | output [31:0]spo; 24 | endmodule 25 | -------------------------------------------------------------------------------- /single/single.cache/ip/2019.2/b7219d93de4be123/cpuclk.dcp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/RegiaYoung/RISC-V-CPU/f410822af82f772b51abdce42b78c99bbe729cba/single/single.cache/ip/2019.2/b7219d93de4be123/cpuclk.dcp -------------------------------------------------------------------------------- /single/single.cache/ip/2019.2/b7219d93de4be123/cpuclk_stub.v: -------------------------------------------------------------------------------- 1 | // Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 2 | // -------------------------------------------------------------------------------- 3 | // Tool Version: Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019 4 | // Date : Mon Sep 6 16:54:50 2021 5 | // Host : DESKTOP-S2SIT85 running 64-bit major release (build 9200) 6 | // Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix 7 | // decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ cpuclk_stub.v 8 | // Design : cpuclk 9 | // Purpose : Stub declaration of top-level module interface 10 | // Device : xc7a100tfgg484-1 11 | // -------------------------------------------------------------------------------- 12 | 13 | // This empty module with port declaration file causes synthesis tools to infer a black box for IP. 14 | // The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. 15 | // Please paste the declaration into a Verilog source file or add the file as an additional source. 16 | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clk_out1, locked, clk_in1) 17 | /* synthesis syn_black_box black_box_pad_pin="clk_out1,locked,clk_in1" */; 18 | output clk_out1; 19 | output locked; 20 | input clk_in1; 21 | endmodule 22 | -------------------------------------------------------------------------------- /single/single.cache/ip/2019.2/b7219d93de4be123/cpuclk_stub.vhdl: -------------------------------------------------------------------------------- 1 | -- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 2 | -- -------------------------------------------------------------------------------- 3 | -- Tool Version: Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019 4 | -- Date : Mon Sep 6 16:54:50 2021 5 | -- Host : DESKTOP-S2SIT85 running 64-bit major release (build 9200) 6 | -- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix 7 | -- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ cpuclk_stub.vhdl 8 | -- Design : cpuclk 9 | -- Purpose : Stub declaration of top-level module interface 10 | -- Device : xc7a100tfgg484-1 11 | -- -------------------------------------------------------------------------------- 12 | library IEEE; 13 | use IEEE.STD_LOGIC_1164.ALL; 14 | 15 | entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is 16 | Port ( 17 | clk_out1 : out STD_LOGIC; 18 | locked : out STD_LOGIC; 19 | clk_in1 : in STD_LOGIC 20 | ); 21 | 22 | end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix; 23 | 24 | architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is 25 | attribute syn_black_box : boolean; 26 | attribute black_box_pad_pin : string; 27 | attribute syn_black_box of stub : architecture is true; 28 | attribute black_box_pad_pin of stub : architecture is "clk_out1,locked,clk_in1"; 29 | begin 30 | end; 31 | -------------------------------------------------------------------------------- /single/single.cache/ip/2019.2/ce28ec6061e64c3c/inst_mem.dcp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/RegiaYoung/RISC-V-CPU/f410822af82f772b51abdce42b78c99bbe729cba/single/single.cache/ip/2019.2/ce28ec6061e64c3c/inst_mem.dcp -------------------------------------------------------------------------------- /single/single.cache/ip/2019.2/ce28ec6061e64c3c/inst_mem_stub.v: -------------------------------------------------------------------------------- 1 | // Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 2 | // -------------------------------------------------------------------------------- 3 | // Tool Version: Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019 4 | // Date : Mon Sep 6 16:55:32 2021 5 | // Host : DESKTOP-S2SIT85 running 64-bit major release (build 9200) 6 | // Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix 7 | // decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ inst_mem_stub.v 8 | // Design : inst_mem 9 | // Purpose : Stub declaration of top-level module interface 10 | // Device : xc7a100tfgg484-1 11 | // -------------------------------------------------------------------------------- 12 | 13 | // This empty module with port declaration file causes synthesis tools to infer a black box for IP. 14 | // The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. 15 | // Please paste the declaration into a Verilog source file or add the file as an additional source. 16 | (* x_core_info = "dist_mem_gen_v8_0_13,Vivado 2019.2" *) 17 | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(a, spo) 18 | /* synthesis syn_black_box black_box_pad_pin="a[13:0],spo[31:0]" */; 19 | input [13:0]a; 20 | output [31:0]spo; 21 | endmodule 22 | -------------------------------------------------------------------------------- /single/single.cache/ip/2019.2/ce28ec6061e64c3c/inst_mem_stub.vhdl: -------------------------------------------------------------------------------- 1 | -- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 2 | -- -------------------------------------------------------------------------------- 3 | -- Tool Version: Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019 4 | -- Date : Mon Sep 6 16:55:32 2021 5 | -- Host : DESKTOP-S2SIT85 running 64-bit major release (build 9200) 6 | -- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix 7 | -- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ inst_mem_stub.vhdl 8 | -- Design : inst_mem 9 | -- Purpose : Stub declaration of top-level module interface 10 | -- Device : xc7a100tfgg484-1 11 | -- -------------------------------------------------------------------------------- 12 | library IEEE; 13 | use IEEE.STD_LOGIC_1164.ALL; 14 | 15 | entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is 16 | Port ( 17 | a : in STD_LOGIC_VECTOR ( 13 downto 0 ); 18 | spo : out STD_LOGIC_VECTOR ( 31 downto 0 ) 19 | ); 20 | 21 | end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix; 22 | 23 | architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is 24 | attribute syn_black_box : boolean; 25 | attribute black_box_pad_pin : string; 26 | attribute syn_black_box of stub : architecture is true; 27 | attribute black_box_pad_pin of stub : architecture is "a[13:0],spo[31:0]"; 28 | attribute x_core_info : string; 29 | attribute x_core_info of stub : architecture is "dist_mem_gen_v8_0_13,Vivado 2019.2"; 30 | begin 31 | end; 32 | -------------------------------------------------------------------------------- /single/single.cache/wt/java_command_handlers.wdf: -------------------------------------------------------------------------------- 1 | version:1 2 | 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:636f726576696577:31:00:00 3 | 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:637573746f6d697a65636f7265:33:00:00 4 | 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6e657770726f6a656374:31:00:00 5 | 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:736574676c6f62616c696e636c756465:31:00:00 6 | eof:3636137316 7 | -------------------------------------------------------------------------------- /single/single.cache/wt/project.wpc: -------------------------------------------------------------------------------- 1 | version:1 2 | 6d6f64655f636f756e7465727c4755494d6f6465:1 3 | eof: 4 | -------------------------------------------------------------------------------- /single/single.hw/single.lpr: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | -------------------------------------------------------------------------------- /single/single.ip_user_files/README.txt: -------------------------------------------------------------------------------- 1 | The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended. 2 | -------------------------------------------------------------------------------- /single/single.ip_user_files/ip/cpuclk/cpuclk_stub.v: -------------------------------------------------------------------------------- 1 | // Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 2 | // -------------------------------------------------------------------------------- 3 | // Tool Version: Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019 4 | // Date : Mon Sep 6 16:54:51 2021 5 | // Host : DESKTOP-S2SIT85 running 64-bit major release (build 9200) 6 | // Command : write_verilog -force -mode synth_stub d:/STUDY/CPU/single/single.srcs/sources_1/ip/cpuclk/cpuclk_stub.v 7 | // Design : cpuclk 8 | // Purpose : Stub declaration of top-level module interface 9 | // Device : xc7a100tfgg484-1 10 | // -------------------------------------------------------------------------------- 11 | 12 | // This empty module with port declaration file causes synthesis tools to infer a black box for IP. 13 | // The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. 14 | // Please paste the declaration into a Verilog source file or add the file as an additional source. 15 | module cpuclk(clk_out1, locked, clk_in1) 16 | /* synthesis syn_black_box black_box_pad_pin="clk_out1,locked,clk_in1" */; 17 | output clk_out1; 18 | output locked; 19 | input clk_in1; 20 | endmodule 21 | -------------------------------------------------------------------------------- /single/single.ip_user_files/ip/cpuclk/cpuclk_stub.vhdl: -------------------------------------------------------------------------------- 1 | -- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 2 | -- -------------------------------------------------------------------------------- 3 | -- Tool Version: Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019 4 | -- Date : Mon Sep 6 16:54:51 2021 5 | -- Host : DESKTOP-S2SIT85 running 64-bit major release (build 9200) 6 | -- Command : write_vhdl -force -mode synth_stub d:/STUDY/CPU/single/single.srcs/sources_1/ip/cpuclk/cpuclk_stub.vhdl 7 | -- Design : cpuclk 8 | -- Purpose : Stub declaration of top-level module interface 9 | -- Device : xc7a100tfgg484-1 10 | -- -------------------------------------------------------------------------------- 11 | library IEEE; 12 | use IEEE.STD_LOGIC_1164.ALL; 13 | 14 | entity cpuclk is 15 | Port ( 16 | clk_out1 : out STD_LOGIC; 17 | locked : out STD_LOGIC; 18 | clk_in1 : in STD_LOGIC 19 | ); 20 | 21 | end cpuclk; 22 | 23 | architecture stub of cpuclk is 24 | attribute syn_black_box : boolean; 25 | attribute black_box_pad_pin : string; 26 | attribute syn_black_box of stub : architecture is true; 27 | attribute black_box_pad_pin of stub : architecture is "clk_out1,locked,clk_in1"; 28 | begin 29 | end; 30 | -------------------------------------------------------------------------------- /single/single.ip_user_files/ip/data_mem/data_mem_stub.v: -------------------------------------------------------------------------------- 1 | // Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 2 | // -------------------------------------------------------------------------------- 3 | // Tool Version: Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019 4 | // Date : Mon Sep 6 16:57:21 2021 5 | // Host : DESKTOP-S2SIT85 running 64-bit major release (build 9200) 6 | // Command : write_verilog -force -mode synth_stub 7 | // d:/STUDY/CPU/single/single.srcs/sources_1/ip/data_mem/data_mem_stub.v 8 | // Design : data_mem 9 | // Purpose : Stub declaration of top-level module interface 10 | // Device : xc7a100tfgg484-1 11 | // -------------------------------------------------------------------------------- 12 | 13 | // This empty module with port declaration file causes synthesis tools to infer a black box for IP. 14 | // The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. 15 | // Please paste the declaration into a Verilog source file or add the file as an additional source. 16 | (* x_core_info = "dist_mem_gen_v8_0_13,Vivado 2019.2" *) 17 | module data_mem(a, d, clk, we, spo) 18 | /* synthesis syn_black_box black_box_pad_pin="a[13:0],d[31:0],clk,we,spo[31:0]" */; 19 | input [13:0]a; 20 | input [31:0]d; 21 | input clk; 22 | input we; 23 | output [31:0]spo; 24 | endmodule 25 | -------------------------------------------------------------------------------- /single/single.ip_user_files/ip/data_mem/data_mem_stub.vhdl: -------------------------------------------------------------------------------- 1 | -- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 2 | -- -------------------------------------------------------------------------------- 3 | -- Tool Version: Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019 4 | -- Date : Mon Sep 6 16:57:21 2021 5 | -- Host : DESKTOP-S2SIT85 running 64-bit major release (build 9200) 6 | -- Command : write_vhdl -force -mode synth_stub 7 | -- d:/STUDY/CPU/single/single.srcs/sources_1/ip/data_mem/data_mem_stub.vhdl 8 | -- Design : data_mem 9 | -- Purpose : Stub declaration of top-level module interface 10 | -- Device : xc7a100tfgg484-1 11 | -- -------------------------------------------------------------------------------- 12 | library IEEE; 13 | use IEEE.STD_LOGIC_1164.ALL; 14 | 15 | entity data_mem is 16 | Port ( 17 | a : in STD_LOGIC_VECTOR ( 13 downto 0 ); 18 | d : in STD_LOGIC_VECTOR ( 31 downto 0 ); 19 | clk : in STD_LOGIC; 20 | we : in STD_LOGIC; 21 | spo : out STD_LOGIC_VECTOR ( 31 downto 0 ) 22 | ); 23 | 24 | end data_mem; 25 | 26 | architecture stub of data_mem is 27 | attribute syn_black_box : boolean; 28 | attribute black_box_pad_pin : string; 29 | attribute syn_black_box of stub : architecture is true; 30 | attribute black_box_pad_pin of stub : architecture is "a[13:0],d[31:0],clk,we,spo[31:0]"; 31 | attribute x_core_info : string; 32 | attribute x_core_info of stub : architecture is "dist_mem_gen_v8_0_13,Vivado 2019.2"; 33 | begin 34 | end; 35 | -------------------------------------------------------------------------------- /single/single.ip_user_files/ip/inst_mem/inst_mem_stub.v: -------------------------------------------------------------------------------- 1 | // Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 2 | // -------------------------------------------------------------------------------- 3 | // Tool Version: Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019 4 | // Date : Mon Sep 6 16:55:32 2021 5 | // Host : DESKTOP-S2SIT85 running 64-bit major release (build 9200) 6 | // Command : write_verilog -force -mode synth_stub 7 | // d:/STUDY/CPU/single/single.srcs/sources_1/ip/inst_mem/inst_mem_stub.v 8 | // Design : inst_mem 9 | // Purpose : Stub declaration of top-level module interface 10 | // Device : xc7a100tfgg484-1 11 | // -------------------------------------------------------------------------------- 12 | 13 | // This empty module with port declaration file causes synthesis tools to infer a black box for IP. 14 | // The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. 15 | // Please paste the declaration into a Verilog source file or add the file as an additional source. 16 | (* x_core_info = "dist_mem_gen_v8_0_13,Vivado 2019.2" *) 17 | module inst_mem(a, spo) 18 | /* synthesis syn_black_box black_box_pad_pin="a[13:0],spo[31:0]" */; 19 | input [13:0]a; 20 | output [31:0]spo; 21 | endmodule 22 | -------------------------------------------------------------------------------- /single/single.ip_user_files/ip/inst_mem/inst_mem_stub.vhdl: -------------------------------------------------------------------------------- 1 | -- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 2 | -- -------------------------------------------------------------------------------- 3 | -- Tool Version: Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019 4 | -- Date : Mon Sep 6 16:55:32 2021 5 | -- Host : DESKTOP-S2SIT85 running 64-bit major release (build 9200) 6 | -- Command : write_vhdl -force -mode synth_stub 7 | -- d:/STUDY/CPU/single/single.srcs/sources_1/ip/inst_mem/inst_mem_stub.vhdl 8 | -- Design : inst_mem 9 | -- Purpose : Stub declaration of top-level module interface 10 | -- Device : xc7a100tfgg484-1 11 | -- -------------------------------------------------------------------------------- 12 | library IEEE; 13 | use IEEE.STD_LOGIC_1164.ALL; 14 | 15 | entity inst_mem is 16 | Port ( 17 | a : in STD_LOGIC_VECTOR ( 13 downto 0 ); 18 | spo : out STD_LOGIC_VECTOR ( 31 downto 0 ) 19 | ); 20 | 21 | end inst_mem; 22 | 23 | architecture stub of inst_mem is 24 | attribute syn_black_box : boolean; 25 | attribute black_box_pad_pin : string; 26 | attribute syn_black_box of stub : architecture is true; 27 | attribute black_box_pad_pin of stub : architecture is "a[13:0],spo[31:0]"; 28 | attribute x_core_info : string; 29 | attribute x_core_info of stub : architecture is "dist_mem_gen_v8_0_13,Vivado 2019.2"; 30 | begin 31 | end; 32 | -------------------------------------------------------------------------------- /single/single.ip_user_files/sim_scripts/cpuclk/activehdl/compile.do: -------------------------------------------------------------------------------- 1 | vlib work 2 | vlib activehdl 3 | 4 | vlib activehdl/xpm 5 | vlib activehdl/xil_defaultlib 6 | 7 | vmap xpm activehdl/xpm 8 | vmap xil_defaultlib activehdl/xil_defaultlib 9 | 10 | vlog -work xpm -sv2k12 "+incdir+../../../ipstatic" \ 11 | "D:/Applications/Vivado2020/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ 12 | 13 | vcom -work xpm -93 \ 14 | "D:/Applications/Vivado2020/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd" \ 15 | 16 | vlog -work xil_defaultlib -v2k5 "+incdir+../../../ipstatic" \ 17 | "../../../../single.srcs/sources_1/ip/cpuclk/cpuclk_clk_wiz.v" \ 18 | "../../../../single.srcs/sources_1/ip/cpuclk/cpuclk.v" \ 19 | 20 | vlog -work xil_defaultlib \ 21 | "glbl.v" 22 | 23 | -------------------------------------------------------------------------------- /single/single.ip_user_files/sim_scripts/cpuclk/activehdl/cpuclk.udo: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/RegiaYoung/RISC-V-CPU/f410822af82f772b51abdce42b78c99bbe729cba/single/single.ip_user_files/sim_scripts/cpuclk/activehdl/cpuclk.udo -------------------------------------------------------------------------------- /single/single.ip_user_files/sim_scripts/cpuclk/activehdl/file_info.txt: -------------------------------------------------------------------------------- 1 | xpm_cdc.sv,systemverilog,xpm,D:/Applications/Vivado2020/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ipstatic"incdir="../../../ipstatic" 2 | xpm_VCOMP.vhd,vhdl,xpm,D:/Applications/Vivado2020/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ipstatic"incdir="../../../ipstatic" 3 | cpuclk_clk_wiz.v,verilog,xil_defaultlib,../../../../single.srcs/sources_1/ip/cpuclk/cpuclk_clk_wiz.v,incdir="../../../ipstatic"incdir="../../../ipstatic" 4 | cpuclk.v,verilog,xil_defaultlib,../../../../single.srcs/sources_1/ip/cpuclk/cpuclk.v,incdir="../../../ipstatic"incdir="../../../ipstatic" 5 | glbl.v,Verilog,xil_defaultlib,glbl.v 6 | -------------------------------------------------------------------------------- /single/single.ip_user_files/sim_scripts/cpuclk/activehdl/simulate.do: -------------------------------------------------------------------------------- 1 | onbreak {quit -force} 2 | onerror {quit -force} 3 | 4 | asim -t 1ps +access +r +m+cpuclk -L xpm -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.cpuclk xil_defaultlib.glbl 5 | 6 | do {wave.do} 7 | 8 | view wave 9 | view structure 10 | 11 | do {cpuclk.udo} 12 | 13 | run -all 14 | 15 | endsim 16 | 17 | quit -force 18 | -------------------------------------------------------------------------------- /single/single.ip_user_files/sim_scripts/cpuclk/activehdl/wave.do: -------------------------------------------------------------------------------- 1 | add wave * 2 | add wave /glbl/GSR 3 | -------------------------------------------------------------------------------- /single/single.ip_user_files/sim_scripts/cpuclk/ies/file_info.txt: -------------------------------------------------------------------------------- 1 | xpm_cdc.sv,systemverilog,xpm,D:/Applications/Vivado2020/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="$ref_dir/../../../ipstatic"incdir="../../../ipstatic" 2 | xpm_VCOMP.vhd,vhdl,xpm,D:/Applications/Vivado2020/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="$ref_dir/../../../ipstatic"incdir="../../../ipstatic" 3 | cpuclk_clk_wiz.v,verilog,xil_defaultlib,../../../../single.srcs/sources_1/ip/cpuclk/cpuclk_clk_wiz.v,incdir="$ref_dir/../../../ipstatic"incdir="../../../ipstatic" 4 | cpuclk.v,verilog,xil_defaultlib,../../../../single.srcs/sources_1/ip/cpuclk/cpuclk.v,incdir="$ref_dir/../../../ipstatic"incdir="../../../ipstatic" 5 | glbl.v,Verilog,xil_defaultlib,glbl.v 6 | -------------------------------------------------------------------------------- /single/single.ip_user_files/sim_scripts/cpuclk/ies/run.f: -------------------------------------------------------------------------------- 1 | -makelib ies_lib/xpm -sv \ 2 | "D:/Applications/Vivado2020/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ 3 | -endlib 4 | -makelib ies_lib/xpm \ 5 | "D:/Applications/Vivado2020/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd" \ 6 | -endlib 7 | -makelib ies_lib/xil_defaultlib \ 8 | "../../../../single.srcs/sources_1/ip/cpuclk/cpuclk_clk_wiz.v" \ 9 | "../../../../single.srcs/sources_1/ip/cpuclk/cpuclk.v" \ 10 | -endlib 11 | -makelib ies_lib/xil_defaultlib \ 12 | glbl.v 13 | -endlib 14 | 15 | -------------------------------------------------------------------------------- /single/single.ip_user_files/sim_scripts/cpuclk/modelsim/compile.do: -------------------------------------------------------------------------------- 1 | vlib modelsim_lib/work 2 | vlib modelsim_lib/msim 3 | 4 | vlib modelsim_lib/msim/xpm 5 | vlib modelsim_lib/msim/xil_defaultlib 6 | 7 | vmap xpm modelsim_lib/msim/xpm 8 | vmap xil_defaultlib modelsim_lib/msim/xil_defaultlib 9 | 10 | vlog -work xpm -64 -incr -sv "+incdir+../../../ipstatic" \ 11 | "D:/Applications/Vivado2020/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ 12 | 13 | vcom -work xpm -64 -93 \ 14 | "D:/Applications/Vivado2020/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd" \ 15 | 16 | vlog -work xil_defaultlib -64 -incr "+incdir+../../../ipstatic" \ 17 | "../../../../single.srcs/sources_1/ip/cpuclk/cpuclk_clk_wiz.v" \ 18 | "../../../../single.srcs/sources_1/ip/cpuclk/cpuclk.v" \ 19 | 20 | vlog -work xil_defaultlib \ 21 | "glbl.v" 22 | 23 | -------------------------------------------------------------------------------- /single/single.ip_user_files/sim_scripts/cpuclk/modelsim/cpuclk.udo: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/RegiaYoung/RISC-V-CPU/f410822af82f772b51abdce42b78c99bbe729cba/single/single.ip_user_files/sim_scripts/cpuclk/modelsim/cpuclk.udo -------------------------------------------------------------------------------- /single/single.ip_user_files/sim_scripts/cpuclk/modelsim/file_info.txt: -------------------------------------------------------------------------------- 1 | xpm_cdc.sv,systemverilog,xpm,D:/Applications/Vivado2020/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ipstatic"incdir="../../../ipstatic" 2 | xpm_VCOMP.vhd,vhdl,xpm,D:/Applications/Vivado2020/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ipstatic"incdir="../../../ipstatic" 3 | cpuclk_clk_wiz.v,verilog,xil_defaultlib,../../../../single.srcs/sources_1/ip/cpuclk/cpuclk_clk_wiz.v,incdir="../../../ipstatic"incdir="../../../ipstatic" 4 | cpuclk.v,verilog,xil_defaultlib,../../../../single.srcs/sources_1/ip/cpuclk/cpuclk.v,incdir="../../../ipstatic"incdir="../../../ipstatic" 5 | glbl.v,Verilog,xil_defaultlib,glbl.v 6 | -------------------------------------------------------------------------------- /single/single.ip_user_files/sim_scripts/cpuclk/modelsim/simulate.do: -------------------------------------------------------------------------------- 1 | onbreak {quit -f} 2 | onerror {quit -f} 3 | 4 | vsim -voptargs="+acc" -t 1ps -L xpm -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -lib xil_defaultlib xil_defaultlib.cpuclk xil_defaultlib.glbl 5 | 6 | do {wave.do} 7 | 8 | view wave 9 | view structure 10 | view signals 11 | 12 | do {cpuclk.udo} 13 | 14 | run -all 15 | 16 | quit -force 17 | -------------------------------------------------------------------------------- /single/single.ip_user_files/sim_scripts/cpuclk/modelsim/wave.do: -------------------------------------------------------------------------------- 1 | add wave * 2 | add wave /glbl/GSR 3 | -------------------------------------------------------------------------------- /single/single.ip_user_files/sim_scripts/cpuclk/questa/compile.do: -------------------------------------------------------------------------------- 1 | vlib questa_lib/work 2 | vlib questa_lib/msim 3 | 4 | vlib questa_lib/msim/xpm 5 | vlib questa_lib/msim/xil_defaultlib 6 | 7 | vmap xpm questa_lib/msim/xpm 8 | vmap xil_defaultlib questa_lib/msim/xil_defaultlib 9 | 10 | vlog -work xpm -64 -sv "+incdir+../../../ipstatic" \ 11 | "D:/Applications/Vivado2020/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ 12 | 13 | vcom -work xpm -64 -93 \ 14 | "D:/Applications/Vivado2020/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd" \ 15 | 16 | vlog -work xil_defaultlib -64 "+incdir+../../../ipstatic" \ 17 | "../../../../single.srcs/sources_1/ip/cpuclk/cpuclk_clk_wiz.v" \ 18 | "../../../../single.srcs/sources_1/ip/cpuclk/cpuclk.v" \ 19 | 20 | vlog -work xil_defaultlib \ 21 | "glbl.v" 22 | 23 | -------------------------------------------------------------------------------- /single/single.ip_user_files/sim_scripts/cpuclk/questa/cpuclk.udo: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/RegiaYoung/RISC-V-CPU/f410822af82f772b51abdce42b78c99bbe729cba/single/single.ip_user_files/sim_scripts/cpuclk/questa/cpuclk.udo -------------------------------------------------------------------------------- /single/single.ip_user_files/sim_scripts/cpuclk/questa/elaborate.do: -------------------------------------------------------------------------------- 1 | vopt -64 +acc -l elaborate.log -L xpm -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -work xil_defaultlib xil_defaultlib.cpuclk xil_defaultlib.glbl -o cpuclk_opt 2 | -------------------------------------------------------------------------------- /single/single.ip_user_files/sim_scripts/cpuclk/questa/file_info.txt: -------------------------------------------------------------------------------- 1 | xpm_cdc.sv,systemverilog,xpm,D:/Applications/Vivado2020/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ipstatic"incdir="../../../ipstatic" 2 | xpm_VCOMP.vhd,vhdl,xpm,D:/Applications/Vivado2020/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ipstatic"incdir="../../../ipstatic" 3 | cpuclk_clk_wiz.v,verilog,xil_defaultlib,../../../../single.srcs/sources_1/ip/cpuclk/cpuclk_clk_wiz.v,incdir="../../../ipstatic"incdir="../../../ipstatic" 4 | cpuclk.v,verilog,xil_defaultlib,../../../../single.srcs/sources_1/ip/cpuclk/cpuclk.v,incdir="../../../ipstatic"incdir="../../../ipstatic" 5 | glbl.v,Verilog,xil_defaultlib,glbl.v 6 | -------------------------------------------------------------------------------- /single/single.ip_user_files/sim_scripts/cpuclk/questa/simulate.do: -------------------------------------------------------------------------------- 1 | onbreak {quit -f} 2 | onerror {quit -f} 3 | 4 | vsim -t 1ps -lib xil_defaultlib cpuclk_opt 5 | 6 | do {wave.do} 7 | 8 | view wave 9 | view structure 10 | view signals 11 | 12 | do {cpuclk.udo} 13 | 14 | run -all 15 | 16 | quit -force 17 | -------------------------------------------------------------------------------- /single/single.ip_user_files/sim_scripts/cpuclk/questa/wave.do: -------------------------------------------------------------------------------- 1 | add wave * 2 | add wave /glbl/GSR 3 | -------------------------------------------------------------------------------- /single/single.ip_user_files/sim_scripts/cpuclk/riviera/compile.do: -------------------------------------------------------------------------------- 1 | vlib work 2 | vlib riviera 3 | 4 | vlib riviera/xpm 5 | vlib riviera/xil_defaultlib 6 | 7 | vmap xpm riviera/xpm 8 | vmap xil_defaultlib riviera/xil_defaultlib 9 | 10 | vlog -work xpm -sv2k12 "+incdir+../../../ipstatic" \ 11 | "D:/Applications/Vivado2020/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ 12 | 13 | vcom -work xpm -93 \ 14 | "D:/Applications/Vivado2020/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd" \ 15 | 16 | vlog -work xil_defaultlib -v2k5 "+incdir+../../../ipstatic" \ 17 | "../../../../single.srcs/sources_1/ip/cpuclk/cpuclk_clk_wiz.v" \ 18 | "../../../../single.srcs/sources_1/ip/cpuclk/cpuclk.v" \ 19 | 20 | vlog -work xil_defaultlib \ 21 | "glbl.v" 22 | 23 | -------------------------------------------------------------------------------- /single/single.ip_user_files/sim_scripts/cpuclk/riviera/cpuclk.udo: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/RegiaYoung/RISC-V-CPU/f410822af82f772b51abdce42b78c99bbe729cba/single/single.ip_user_files/sim_scripts/cpuclk/riviera/cpuclk.udo -------------------------------------------------------------------------------- /single/single.ip_user_files/sim_scripts/cpuclk/riviera/file_info.txt: -------------------------------------------------------------------------------- 1 | xpm_cdc.sv,systemverilog,xpm,D:/Applications/Vivado2020/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ipstatic"incdir="../../../ipstatic" 2 | xpm_VCOMP.vhd,vhdl,xpm,D:/Applications/Vivado2020/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ipstatic"incdir="../../../ipstatic" 3 | cpuclk_clk_wiz.v,verilog,xil_defaultlib,../../../../single.srcs/sources_1/ip/cpuclk/cpuclk_clk_wiz.v,incdir="../../../ipstatic"incdir="../../../ipstatic" 4 | cpuclk.v,verilog,xil_defaultlib,../../../../single.srcs/sources_1/ip/cpuclk/cpuclk.v,incdir="../../../ipstatic"incdir="../../../ipstatic" 5 | glbl.v,Verilog,xil_defaultlib,glbl.v 6 | -------------------------------------------------------------------------------- /single/single.ip_user_files/sim_scripts/cpuclk/riviera/simulate.do: -------------------------------------------------------------------------------- 1 | onbreak {quit -force} 2 | onerror {quit -force} 3 | 4 | asim -t 1ps +access +r +m+cpuclk -L xpm -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.cpuclk xil_defaultlib.glbl 5 | 6 | do {wave.do} 7 | 8 | view wave 9 | view structure 10 | 11 | do {cpuclk.udo} 12 | 13 | run -all 14 | 15 | endsim 16 | 17 | quit -force 18 | -------------------------------------------------------------------------------- /single/single.ip_user_files/sim_scripts/cpuclk/riviera/wave.do: -------------------------------------------------------------------------------- 1 | add wave * 2 | add wave /glbl/GSR 3 | -------------------------------------------------------------------------------- /single/single.ip_user_files/sim_scripts/cpuclk/vcs/file_info.txt: -------------------------------------------------------------------------------- 1 | xpm_cdc.sv,systemverilog,xpm,D:/Applications/Vivado2020/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="$ref_dir/../../../ipstatic"incdir="../../../ipstatic" 2 | xpm_VCOMP.vhd,vhdl,xpm,D:/Applications/Vivado2020/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="$ref_dir/../../../ipstatic"incdir="../../../ipstatic" 3 | cpuclk_clk_wiz.v,verilog,xil_defaultlib,../../../../single.srcs/sources_1/ip/cpuclk/cpuclk_clk_wiz.v,incdir="$ref_dir/../../../ipstatic"incdir="../../../ipstatic" 4 | cpuclk.v,verilog,xil_defaultlib,../../../../single.srcs/sources_1/ip/cpuclk/cpuclk.v,incdir="$ref_dir/../../../ipstatic"incdir="../../../ipstatic" 5 | glbl.v,Verilog,xil_defaultlib,glbl.v 6 | -------------------------------------------------------------------------------- /single/single.ip_user_files/sim_scripts/cpuclk/vcs/simulate.do: -------------------------------------------------------------------------------- 1 | run 2 | quit 3 | -------------------------------------------------------------------------------- /single/single.ip_user_files/sim_scripts/cpuclk/xcelium/file_info.txt: -------------------------------------------------------------------------------- 1 | xpm_cdc.sv,systemverilog,xpm,D:/Applications/Vivado2020/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="$ref_dir/../../../ipstatic"incdir="../../../ipstatic" 2 | xpm_VCOMP.vhd,vhdl,xpm,D:/Applications/Vivado2020/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="$ref_dir/../../../ipstatic"incdir="../../../ipstatic" 3 | cpuclk_clk_wiz.v,verilog,xil_defaultlib,../../../../single.srcs/sources_1/ip/cpuclk/cpuclk_clk_wiz.v,incdir="$ref_dir/../../../ipstatic"incdir="../../../ipstatic" 4 | cpuclk.v,verilog,xil_defaultlib,../../../../single.srcs/sources_1/ip/cpuclk/cpuclk.v,incdir="$ref_dir/../../../ipstatic"incdir="../../../ipstatic" 5 | glbl.v,Verilog,xil_defaultlib,glbl.v 6 | -------------------------------------------------------------------------------- /single/single.ip_user_files/sim_scripts/cpuclk/xcelium/run.f: -------------------------------------------------------------------------------- 1 | -makelib xcelium_lib/xpm -sv \ 2 | "D:/Applications/Vivado2020/Vivado/2019.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ 3 | -endlib 4 | -makelib xcelium_lib/xpm \ 5 | "D:/Applications/Vivado2020/Vivado/2019.2/data/ip/xpm/xpm_VCOMP.vhd" \ 6 | -endlib 7 | -makelib xcelium_lib/xil_defaultlib \ 8 | "../../../../single.srcs/sources_1/ip/cpuclk/cpuclk_clk_wiz.v" \ 9 | "../../../../single.srcs/sources_1/ip/cpuclk/cpuclk.v" \ 10 | -endlib 11 | -makelib xcelium_lib/xil_defaultlib \ 12 | glbl.v 13 | -endlib 14 | 15 | -------------------------------------------------------------------------------- /single/single.ip_user_files/sim_scripts/cpuclk/xsim/cmd.tcl: -------------------------------------------------------------------------------- 1 | set curr_wave [current_wave_config] 2 | if { [string length $curr_wave] == 0 } { 3 | if { [llength [get_objects]] > 0} { 4 | add_wave / 5 | set_property needs_save false [current_wave_config] 6 | } else { 7 | send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." 8 | } 9 | } 10 | 11 | run -all 12 | quit 13 | -------------------------------------------------------------------------------- /single/single.ip_user_files/sim_scripts/cpuclk/xsim/elab.opt: -------------------------------------------------------------------------------- 1 | --relax --debug typical --mt auto -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot cpuclk xil_defaultlib.cpuclk xil_defaultlib.glbl -log elaborate.log 2 | -------------------------------------------------------------------------------- /single/single.ip_user_files/sim_scripts/cpuclk/xsim/file_info.txt: -------------------------------------------------------------------------------- 1 | cpuclk_clk_wiz.v,verilog,xil_defaultlib,../../../../single.srcs/sources_1/ip/cpuclk/cpuclk_clk_wiz.v,incdir="$ref_dir/../../../ipstatic"incdir="../../../ipstatic" 2 | cpuclk.v,verilog,xil_defaultlib,../../../../single.srcs/sources_1/ip/cpuclk/cpuclk.v,incdir="$ref_dir/../../../ipstatic"incdir="../../../ipstatic" 3 | glbl.v,Verilog,xil_defaultlib,glbl.v 4 | -------------------------------------------------------------------------------- /single/single.ip_user_files/sim_scripts/cpuclk/xsim/vlog.prj: -------------------------------------------------------------------------------- 1 | verilog xil_defaultlib --include "../../../ipstatic" \ 2 | "../../../../single.srcs/sources_1/ip/cpuclk/cpuclk_clk_wiz.v" \ 3 | "../../../../single.srcs/sources_1/ip/cpuclk/cpuclk.v" \ 4 | 5 | verilog xil_defaultlib "glbl.v" 6 | 7 | nosort 8 | -------------------------------------------------------------------------------- /single/single.ip_user_files/sim_scripts/data_mem/activehdl/compile.do: -------------------------------------------------------------------------------- 1 | vlib work 2 | vlib activehdl 3 | 4 | vlib activehdl/dist_mem_gen_v8_0_13 5 | vlib activehdl/xil_defaultlib 6 | 7 | vmap dist_mem_gen_v8_0_13 activehdl/dist_mem_gen_v8_0_13 8 | vmap xil_defaultlib activehdl/xil_defaultlib 9 | 10 | vlog -work dist_mem_gen_v8_0_13 -v2k5 \ 11 | "../../../ipstatic/simulation/dist_mem_gen_v8_0.v" \ 12 | 13 | vlog -work xil_defaultlib -v2k5 \ 14 | "../../../../single.srcs/sources_1/ip/data_mem/sim/data_mem.v" \ 15 | 16 | 17 | vlog -work xil_defaultlib \ 18 | "glbl.v" 19 | 20 | -------------------------------------------------------------------------------- /single/single.ip_user_files/sim_scripts/data_mem/activehdl/data_mem.udo: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/RegiaYoung/RISC-V-CPU/f410822af82f772b51abdce42b78c99bbe729cba/single/single.ip_user_files/sim_scripts/data_mem/activehdl/data_mem.udo -------------------------------------------------------------------------------- /single/single.ip_user_files/sim_scripts/data_mem/activehdl/file_info.txt: -------------------------------------------------------------------------------- 1 | dist_mem_gen_v8_0.v,verilog,dist_mem_gen_v8_0_13,../../../ipstatic/simulation/dist_mem_gen_v8_0.v, 2 | data_mem.v,verilog,xil_defaultlib,../../../../single.srcs/sources_1/ip/data_mem/sim/data_mem.v, 3 | glbl.v,Verilog,xil_defaultlib,glbl.v 4 | -------------------------------------------------------------------------------- /single/single.ip_user_files/sim_scripts/data_mem/activehdl/simulate.do: -------------------------------------------------------------------------------- 1 | onbreak {quit -force} 2 | onerror {quit -force} 3 | 4 | asim -t 1ps +access +r +m+data_mem -L dist_mem_gen_v8_0_13 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.data_mem xil_defaultlib.glbl 5 | 6 | do {wave.do} 7 | 8 | view wave 9 | view structure 10 | 11 | do {data_mem.udo} 12 | 13 | run -all 14 | 15 | endsim 16 | 17 | quit -force 18 | -------------------------------------------------------------------------------- /single/single.ip_user_files/sim_scripts/data_mem/activehdl/wave.do: -------------------------------------------------------------------------------- 1 | add wave * 2 | add wave /glbl/GSR 3 | -------------------------------------------------------------------------------- /single/single.ip_user_files/sim_scripts/data_mem/ies/file_info.txt: -------------------------------------------------------------------------------- 1 | dist_mem_gen_v8_0.v,verilog,dist_mem_gen_v8_0_13,../../../ipstatic/simulation/dist_mem_gen_v8_0.v, 2 | data_mem.v,verilog,xil_defaultlib,../../../../single.srcs/sources_1/ip/data_mem/sim/data_mem.v, 3 | glbl.v,Verilog,xil_defaultlib,glbl.v 4 | -------------------------------------------------------------------------------- /single/single.ip_user_files/sim_scripts/data_mem/ies/run.f: -------------------------------------------------------------------------------- 1 | -makelib ies_lib/dist_mem_gen_v8_0_13 \ 2 | "../../../ipstatic/simulation/dist_mem_gen_v8_0.v" \ 3 | -endlib 4 | -makelib ies_lib/xil_defaultlib \ 5 | "../../../../single.srcs/sources_1/ip/data_mem/sim/data_mem.v" \ 6 | -endlib 7 | -makelib ies_lib/xil_defaultlib \ 8 | glbl.v 9 | -endlib 10 | 11 | -------------------------------------------------------------------------------- /single/single.ip_user_files/sim_scripts/data_mem/modelsim/compile.do: -------------------------------------------------------------------------------- 1 | vlib modelsim_lib/work 2 | vlib modelsim_lib/msim 3 | 4 | vlib modelsim_lib/msim/dist_mem_gen_v8_0_13 5 | vlib modelsim_lib/msim/xil_defaultlib 6 | 7 | vmap dist_mem_gen_v8_0_13 modelsim_lib/msim/dist_mem_gen_v8_0_13 8 | vmap xil_defaultlib modelsim_lib/msim/xil_defaultlib 9 | 10 | vlog -work dist_mem_gen_v8_0_13 -64 -incr \ 11 | "../../../ipstatic/simulation/dist_mem_gen_v8_0.v" \ 12 | 13 | vlog -work xil_defaultlib -64 -incr \ 14 | "../../../../single.srcs/sources_1/ip/data_mem/sim/data_mem.v" \ 15 | 16 | 17 | vlog -work xil_defaultlib \ 18 | "glbl.v" 19 | 20 | -------------------------------------------------------------------------------- /single/single.ip_user_files/sim_scripts/data_mem/modelsim/data_mem.udo: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/RegiaYoung/RISC-V-CPU/f410822af82f772b51abdce42b78c99bbe729cba/single/single.ip_user_files/sim_scripts/data_mem/modelsim/data_mem.udo -------------------------------------------------------------------------------- /single/single.ip_user_files/sim_scripts/data_mem/modelsim/file_info.txt: -------------------------------------------------------------------------------- 1 | dist_mem_gen_v8_0.v,verilog,dist_mem_gen_v8_0_13,../../../ipstatic/simulation/dist_mem_gen_v8_0.v, 2 | data_mem.v,verilog,xil_defaultlib,../../../../single.srcs/sources_1/ip/data_mem/sim/data_mem.v, 3 | glbl.v,Verilog,xil_defaultlib,glbl.v 4 | -------------------------------------------------------------------------------- /single/single.ip_user_files/sim_scripts/data_mem/modelsim/simulate.do: -------------------------------------------------------------------------------- 1 | onbreak {quit -f} 2 | onerror {quit -f} 3 | 4 | vsim -voptargs="+acc" -t 1ps -L dist_mem_gen_v8_0_13 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -lib xil_defaultlib xil_defaultlib.data_mem xil_defaultlib.glbl 5 | 6 | do {wave.do} 7 | 8 | view wave 9 | view structure 10 | view signals 11 | 12 | do {data_mem.udo} 13 | 14 | run -all 15 | 16 | quit -force 17 | -------------------------------------------------------------------------------- /single/single.ip_user_files/sim_scripts/data_mem/modelsim/wave.do: -------------------------------------------------------------------------------- 1 | add wave * 2 | add wave /glbl/GSR 3 | -------------------------------------------------------------------------------- /single/single.ip_user_files/sim_scripts/data_mem/questa/compile.do: -------------------------------------------------------------------------------- 1 | vlib questa_lib/work 2 | vlib questa_lib/msim 3 | 4 | vlib questa_lib/msim/dist_mem_gen_v8_0_13 5 | vlib questa_lib/msim/xil_defaultlib 6 | 7 | vmap dist_mem_gen_v8_0_13 questa_lib/msim/dist_mem_gen_v8_0_13 8 | vmap xil_defaultlib questa_lib/msim/xil_defaultlib 9 | 10 | vlog -work dist_mem_gen_v8_0_13 -64 \ 11 | "../../../ipstatic/simulation/dist_mem_gen_v8_0.v" \ 12 | 13 | vlog -work xil_defaultlib -64 \ 14 | "../../../../single.srcs/sources_1/ip/data_mem/sim/data_mem.v" \ 15 | 16 | 17 | vlog -work xil_defaultlib \ 18 | "glbl.v" 19 | 20 | -------------------------------------------------------------------------------- /single/single.ip_user_files/sim_scripts/data_mem/questa/data_mem.udo: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/RegiaYoung/RISC-V-CPU/f410822af82f772b51abdce42b78c99bbe729cba/single/single.ip_user_files/sim_scripts/data_mem/questa/data_mem.udo -------------------------------------------------------------------------------- /single/single.ip_user_files/sim_scripts/data_mem/questa/elaborate.do: -------------------------------------------------------------------------------- 1 | vopt -64 +acc -l elaborate.log -L dist_mem_gen_v8_0_13 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -work xil_defaultlib xil_defaultlib.data_mem xil_defaultlib.glbl -o data_mem_opt 2 | -------------------------------------------------------------------------------- /single/single.ip_user_files/sim_scripts/data_mem/questa/file_info.txt: -------------------------------------------------------------------------------- 1 | dist_mem_gen_v8_0.v,verilog,dist_mem_gen_v8_0_13,../../../ipstatic/simulation/dist_mem_gen_v8_0.v, 2 | data_mem.v,verilog,xil_defaultlib,../../../../single.srcs/sources_1/ip/data_mem/sim/data_mem.v, 3 | glbl.v,Verilog,xil_defaultlib,glbl.v 4 | -------------------------------------------------------------------------------- /single/single.ip_user_files/sim_scripts/data_mem/questa/simulate.do: -------------------------------------------------------------------------------- 1 | onbreak {quit -f} 2 | onerror {quit -f} 3 | 4 | vsim -t 1ps -lib xil_defaultlib data_mem_opt 5 | 6 | do {wave.do} 7 | 8 | view wave 9 | view structure 10 | view signals 11 | 12 | do {data_mem.udo} 13 | 14 | run -all 15 | 16 | quit -force 17 | -------------------------------------------------------------------------------- /single/single.ip_user_files/sim_scripts/data_mem/questa/wave.do: -------------------------------------------------------------------------------- 1 | add wave * 2 | add wave /glbl/GSR 3 | -------------------------------------------------------------------------------- /single/single.ip_user_files/sim_scripts/data_mem/riviera/compile.do: -------------------------------------------------------------------------------- 1 | vlib work 2 | vlib riviera 3 | 4 | vlib riviera/dist_mem_gen_v8_0_13 5 | vlib riviera/xil_defaultlib 6 | 7 | vmap dist_mem_gen_v8_0_13 riviera/dist_mem_gen_v8_0_13 8 | vmap xil_defaultlib riviera/xil_defaultlib 9 | 10 | vlog -work dist_mem_gen_v8_0_13 -v2k5 \ 11 | "../../../ipstatic/simulation/dist_mem_gen_v8_0.v" \ 12 | 13 | vlog -work xil_defaultlib -v2k5 \ 14 | "../../../../single.srcs/sources_1/ip/data_mem/sim/data_mem.v" \ 15 | 16 | 17 | vlog -work xil_defaultlib \ 18 | "glbl.v" 19 | 20 | -------------------------------------------------------------------------------- /single/single.ip_user_files/sim_scripts/data_mem/riviera/data_mem.udo: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/RegiaYoung/RISC-V-CPU/f410822af82f772b51abdce42b78c99bbe729cba/single/single.ip_user_files/sim_scripts/data_mem/riviera/data_mem.udo -------------------------------------------------------------------------------- /single/single.ip_user_files/sim_scripts/data_mem/riviera/file_info.txt: -------------------------------------------------------------------------------- 1 | dist_mem_gen_v8_0.v,verilog,dist_mem_gen_v8_0_13,../../../ipstatic/simulation/dist_mem_gen_v8_0.v, 2 | data_mem.v,verilog,xil_defaultlib,../../../../single.srcs/sources_1/ip/data_mem/sim/data_mem.v, 3 | glbl.v,Verilog,xil_defaultlib,glbl.v 4 | -------------------------------------------------------------------------------- /single/single.ip_user_files/sim_scripts/data_mem/riviera/simulate.do: -------------------------------------------------------------------------------- 1 | onbreak {quit -force} 2 | onerror {quit -force} 3 | 4 | asim -t 1ps +access +r +m+data_mem -L dist_mem_gen_v8_0_13 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.data_mem xil_defaultlib.glbl 5 | 6 | do {wave.do} 7 | 8 | view wave 9 | view structure 10 | 11 | do {data_mem.udo} 12 | 13 | run -all 14 | 15 | endsim 16 | 17 | quit -force 18 | -------------------------------------------------------------------------------- /single/single.ip_user_files/sim_scripts/data_mem/riviera/wave.do: -------------------------------------------------------------------------------- 1 | add wave * 2 | add wave /glbl/GSR 3 | -------------------------------------------------------------------------------- /single/single.ip_user_files/sim_scripts/data_mem/vcs/file_info.txt: -------------------------------------------------------------------------------- 1 | dist_mem_gen_v8_0.v,verilog,dist_mem_gen_v8_0_13,../../../ipstatic/simulation/dist_mem_gen_v8_0.v, 2 | data_mem.v,verilog,xil_defaultlib,../../../../single.srcs/sources_1/ip/data_mem/sim/data_mem.v, 3 | glbl.v,Verilog,xil_defaultlib,glbl.v 4 | -------------------------------------------------------------------------------- /single/single.ip_user_files/sim_scripts/data_mem/vcs/simulate.do: -------------------------------------------------------------------------------- 1 | run 2 | quit 3 | -------------------------------------------------------------------------------- /single/single.ip_user_files/sim_scripts/data_mem/xcelium/file_info.txt: -------------------------------------------------------------------------------- 1 | dist_mem_gen_v8_0.v,verilog,dist_mem_gen_v8_0_13,../../../ipstatic/simulation/dist_mem_gen_v8_0.v, 2 | data_mem.v,verilog,xil_defaultlib,../../../../single.srcs/sources_1/ip/data_mem/sim/data_mem.v, 3 | glbl.v,Verilog,xil_defaultlib,glbl.v 4 | -------------------------------------------------------------------------------- /single/single.ip_user_files/sim_scripts/data_mem/xcelium/run.f: -------------------------------------------------------------------------------- 1 | -makelib xcelium_lib/dist_mem_gen_v8_0_13 \ 2 | "../../../ipstatic/simulation/dist_mem_gen_v8_0.v" \ 3 | -endlib 4 | -makelib xcelium_lib/xil_defaultlib \ 5 | "../../../../single.srcs/sources_1/ip/data_mem/sim/data_mem.v" \ 6 | -endlib 7 | -makelib xcelium_lib/xil_defaultlib \ 8 | glbl.v 9 | -endlib 10 | 11 | -------------------------------------------------------------------------------- /single/single.ip_user_files/sim_scripts/data_mem/xsim/cmd.tcl: -------------------------------------------------------------------------------- 1 | set curr_wave [current_wave_config] 2 | if { [string length $curr_wave] == 0 } { 3 | if { [llength [get_objects]] > 0} { 4 | add_wave / 5 | set_property needs_save false [current_wave_config] 6 | } else { 7 | send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." 8 | } 9 | } 10 | 11 | run -all 12 | quit 13 | -------------------------------------------------------------------------------- /single/single.ip_user_files/sim_scripts/data_mem/xsim/elab.opt: -------------------------------------------------------------------------------- 1 | --relax --debug typical --mt auto -L dist_mem_gen_v8_0_13 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot data_mem xil_defaultlib.data_mem xil_defaultlib.glbl -log elaborate.log 2 | -------------------------------------------------------------------------------- /single/single.ip_user_files/sim_scripts/data_mem/xsim/file_info.txt: -------------------------------------------------------------------------------- 1 | data_mem.v,verilog,xil_defaultlib,../../../../single.srcs/sources_1/ip/data_mem/sim/data_mem.v, 2 | glbl.v,Verilog,xil_defaultlib,glbl.v 3 | -------------------------------------------------------------------------------- /single/single.ip_user_files/sim_scripts/data_mem/xsim/vlog.prj: -------------------------------------------------------------------------------- 1 | verilog xil_defaultlib \ 2 | "../../../../single.srcs/sources_1/ip/data_mem/sim/data_mem.v" \ 3 | 4 | verilog xil_defaultlib "glbl.v" 5 | 6 | nosort 7 | -------------------------------------------------------------------------------- /single/single.ip_user_files/sim_scripts/inst_mem/activehdl/compile.do: -------------------------------------------------------------------------------- 1 | vlib work 2 | vlib activehdl 3 | 4 | vlib activehdl/dist_mem_gen_v8_0_13 5 | vlib activehdl/xil_defaultlib 6 | 7 | vmap dist_mem_gen_v8_0_13 activehdl/dist_mem_gen_v8_0_13 8 | vmap xil_defaultlib activehdl/xil_defaultlib 9 | 10 | vlog -work dist_mem_gen_v8_0_13 -v2k5 \ 11 | "../../../ipstatic/simulation/dist_mem_gen_v8_0.v" \ 12 | 13 | vlog -work xil_defaultlib -v2k5 \ 14 | "../../../../single.srcs/sources_1/ip/inst_mem/sim/inst_mem.v" \ 15 | 16 | 17 | vlog -work xil_defaultlib \ 18 | "glbl.v" 19 | 20 | -------------------------------------------------------------------------------- /single/single.ip_user_files/sim_scripts/inst_mem/activehdl/file_info.txt: -------------------------------------------------------------------------------- 1 | dist_mem_gen_v8_0.v,verilog,dist_mem_gen_v8_0_13,../../../ipstatic/simulation/dist_mem_gen_v8_0.v, 2 | inst_mem.v,verilog,xil_defaultlib,../../../../single.srcs/sources_1/ip/inst_mem/sim/inst_mem.v, 3 | glbl.v,Verilog,xil_defaultlib,glbl.v 4 | -------------------------------------------------------------------------------- /single/single.ip_user_files/sim_scripts/inst_mem/activehdl/inst_mem.udo: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/RegiaYoung/RISC-V-CPU/f410822af82f772b51abdce42b78c99bbe729cba/single/single.ip_user_files/sim_scripts/inst_mem/activehdl/inst_mem.udo -------------------------------------------------------------------------------- /single/single.ip_user_files/sim_scripts/inst_mem/activehdl/simulate.do: -------------------------------------------------------------------------------- 1 | onbreak {quit -force} 2 | onerror {quit -force} 3 | 4 | asim -t 1ps +access +r +m+inst_mem -L dist_mem_gen_v8_0_13 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.inst_mem xil_defaultlib.glbl 5 | 6 | do {wave.do} 7 | 8 | view wave 9 | view structure 10 | 11 | do {inst_mem.udo} 12 | 13 | run -all 14 | 15 | endsim 16 | 17 | quit -force 18 | -------------------------------------------------------------------------------- /single/single.ip_user_files/sim_scripts/inst_mem/activehdl/wave.do: -------------------------------------------------------------------------------- 1 | add wave * 2 | add wave /glbl/GSR 3 | -------------------------------------------------------------------------------- /single/single.ip_user_files/sim_scripts/inst_mem/ies/file_info.txt: -------------------------------------------------------------------------------- 1 | dist_mem_gen_v8_0.v,verilog,dist_mem_gen_v8_0_13,../../../ipstatic/simulation/dist_mem_gen_v8_0.v, 2 | inst_mem.v,verilog,xil_defaultlib,../../../../single.srcs/sources_1/ip/inst_mem/sim/inst_mem.v, 3 | glbl.v,Verilog,xil_defaultlib,glbl.v 4 | -------------------------------------------------------------------------------- /single/single.ip_user_files/sim_scripts/inst_mem/ies/run.f: -------------------------------------------------------------------------------- 1 | -makelib ies_lib/dist_mem_gen_v8_0_13 \ 2 | "../../../ipstatic/simulation/dist_mem_gen_v8_0.v" \ 3 | -endlib 4 | -makelib ies_lib/xil_defaultlib \ 5 | "../../../../single.srcs/sources_1/ip/inst_mem/sim/inst_mem.v" \ 6 | -endlib 7 | -makelib ies_lib/xil_defaultlib \ 8 | glbl.v 9 | -endlib 10 | 11 | -------------------------------------------------------------------------------- /single/single.ip_user_files/sim_scripts/inst_mem/modelsim/compile.do: -------------------------------------------------------------------------------- 1 | vlib modelsim_lib/work 2 | vlib modelsim_lib/msim 3 | 4 | vlib modelsim_lib/msim/dist_mem_gen_v8_0_13 5 | vlib modelsim_lib/msim/xil_defaultlib 6 | 7 | vmap dist_mem_gen_v8_0_13 modelsim_lib/msim/dist_mem_gen_v8_0_13 8 | vmap xil_defaultlib modelsim_lib/msim/xil_defaultlib 9 | 10 | vlog -work dist_mem_gen_v8_0_13 -64 -incr \ 11 | "../../../ipstatic/simulation/dist_mem_gen_v8_0.v" \ 12 | 13 | vlog -work xil_defaultlib -64 -incr \ 14 | "../../../../single.srcs/sources_1/ip/inst_mem/sim/inst_mem.v" \ 15 | 16 | 17 | vlog -work xil_defaultlib \ 18 | "glbl.v" 19 | 20 | -------------------------------------------------------------------------------- /single/single.ip_user_files/sim_scripts/inst_mem/modelsim/file_info.txt: -------------------------------------------------------------------------------- 1 | dist_mem_gen_v8_0.v,verilog,dist_mem_gen_v8_0_13,../../../ipstatic/simulation/dist_mem_gen_v8_0.v, 2 | inst_mem.v,verilog,xil_defaultlib,../../../../single.srcs/sources_1/ip/inst_mem/sim/inst_mem.v, 3 | glbl.v,Verilog,xil_defaultlib,glbl.v 4 | -------------------------------------------------------------------------------- /single/single.ip_user_files/sim_scripts/inst_mem/modelsim/inst_mem.udo: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/RegiaYoung/RISC-V-CPU/f410822af82f772b51abdce42b78c99bbe729cba/single/single.ip_user_files/sim_scripts/inst_mem/modelsim/inst_mem.udo -------------------------------------------------------------------------------- /single/single.ip_user_files/sim_scripts/inst_mem/modelsim/simulate.do: -------------------------------------------------------------------------------- 1 | onbreak {quit -f} 2 | onerror {quit -f} 3 | 4 | vsim -voptargs="+acc" -t 1ps -L dist_mem_gen_v8_0_13 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -lib xil_defaultlib xil_defaultlib.inst_mem xil_defaultlib.glbl 5 | 6 | do {wave.do} 7 | 8 | view wave 9 | view structure 10 | view signals 11 | 12 | do {inst_mem.udo} 13 | 14 | run -all 15 | 16 | quit -force 17 | -------------------------------------------------------------------------------- /single/single.ip_user_files/sim_scripts/inst_mem/modelsim/wave.do: -------------------------------------------------------------------------------- 1 | add wave * 2 | add wave /glbl/GSR 3 | -------------------------------------------------------------------------------- /single/single.ip_user_files/sim_scripts/inst_mem/questa/compile.do: -------------------------------------------------------------------------------- 1 | vlib questa_lib/work 2 | vlib questa_lib/msim 3 | 4 | vlib questa_lib/msim/dist_mem_gen_v8_0_13 5 | vlib questa_lib/msim/xil_defaultlib 6 | 7 | vmap dist_mem_gen_v8_0_13 questa_lib/msim/dist_mem_gen_v8_0_13 8 | vmap xil_defaultlib questa_lib/msim/xil_defaultlib 9 | 10 | vlog -work dist_mem_gen_v8_0_13 -64 \ 11 | "../../../ipstatic/simulation/dist_mem_gen_v8_0.v" \ 12 | 13 | vlog -work xil_defaultlib -64 \ 14 | "../../../../single.srcs/sources_1/ip/inst_mem/sim/inst_mem.v" \ 15 | 16 | 17 | vlog -work xil_defaultlib \ 18 | "glbl.v" 19 | 20 | -------------------------------------------------------------------------------- /single/single.ip_user_files/sim_scripts/inst_mem/questa/elaborate.do: -------------------------------------------------------------------------------- 1 | vopt -64 +acc -l elaborate.log -L dist_mem_gen_v8_0_13 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -work xil_defaultlib xil_defaultlib.inst_mem xil_defaultlib.glbl -o inst_mem_opt 2 | -------------------------------------------------------------------------------- /single/single.ip_user_files/sim_scripts/inst_mem/questa/file_info.txt: -------------------------------------------------------------------------------- 1 | dist_mem_gen_v8_0.v,verilog,dist_mem_gen_v8_0_13,../../../ipstatic/simulation/dist_mem_gen_v8_0.v, 2 | inst_mem.v,verilog,xil_defaultlib,../../../../single.srcs/sources_1/ip/inst_mem/sim/inst_mem.v, 3 | glbl.v,Verilog,xil_defaultlib,glbl.v 4 | -------------------------------------------------------------------------------- /single/single.ip_user_files/sim_scripts/inst_mem/questa/inst_mem.udo: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/RegiaYoung/RISC-V-CPU/f410822af82f772b51abdce42b78c99bbe729cba/single/single.ip_user_files/sim_scripts/inst_mem/questa/inst_mem.udo -------------------------------------------------------------------------------- /single/single.ip_user_files/sim_scripts/inst_mem/questa/simulate.do: -------------------------------------------------------------------------------- 1 | onbreak {quit -f} 2 | onerror {quit -f} 3 | 4 | vsim -t 1ps -lib xil_defaultlib inst_mem_opt 5 | 6 | do {wave.do} 7 | 8 | view wave 9 | view structure 10 | view signals 11 | 12 | do {inst_mem.udo} 13 | 14 | run -all 15 | 16 | quit -force 17 | -------------------------------------------------------------------------------- /single/single.ip_user_files/sim_scripts/inst_mem/questa/wave.do: -------------------------------------------------------------------------------- 1 | add wave * 2 | add wave /glbl/GSR 3 | -------------------------------------------------------------------------------- /single/single.ip_user_files/sim_scripts/inst_mem/riviera/compile.do: -------------------------------------------------------------------------------- 1 | vlib work 2 | vlib riviera 3 | 4 | vlib riviera/dist_mem_gen_v8_0_13 5 | vlib riviera/xil_defaultlib 6 | 7 | vmap dist_mem_gen_v8_0_13 riviera/dist_mem_gen_v8_0_13 8 | vmap xil_defaultlib riviera/xil_defaultlib 9 | 10 | vlog -work dist_mem_gen_v8_0_13 -v2k5 \ 11 | "../../../ipstatic/simulation/dist_mem_gen_v8_0.v" \ 12 | 13 | vlog -work xil_defaultlib -v2k5 \ 14 | "../../../../single.srcs/sources_1/ip/inst_mem/sim/inst_mem.v" \ 15 | 16 | 17 | vlog -work xil_defaultlib \ 18 | "glbl.v" 19 | 20 | -------------------------------------------------------------------------------- /single/single.ip_user_files/sim_scripts/inst_mem/riviera/file_info.txt: -------------------------------------------------------------------------------- 1 | dist_mem_gen_v8_0.v,verilog,dist_mem_gen_v8_0_13,../../../ipstatic/simulation/dist_mem_gen_v8_0.v, 2 | inst_mem.v,verilog,xil_defaultlib,../../../../single.srcs/sources_1/ip/inst_mem/sim/inst_mem.v, 3 | glbl.v,Verilog,xil_defaultlib,glbl.v 4 | -------------------------------------------------------------------------------- /single/single.ip_user_files/sim_scripts/inst_mem/riviera/inst_mem.udo: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/RegiaYoung/RISC-V-CPU/f410822af82f772b51abdce42b78c99bbe729cba/single/single.ip_user_files/sim_scripts/inst_mem/riviera/inst_mem.udo -------------------------------------------------------------------------------- /single/single.ip_user_files/sim_scripts/inst_mem/riviera/simulate.do: -------------------------------------------------------------------------------- 1 | onbreak {quit -force} 2 | onerror {quit -force} 3 | 4 | asim -t 1ps +access +r +m+inst_mem -L dist_mem_gen_v8_0_13 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.inst_mem xil_defaultlib.glbl 5 | 6 | do {wave.do} 7 | 8 | view wave 9 | view structure 10 | 11 | do {inst_mem.udo} 12 | 13 | run -all 14 | 15 | endsim 16 | 17 | quit -force 18 | -------------------------------------------------------------------------------- /single/single.ip_user_files/sim_scripts/inst_mem/riviera/wave.do: -------------------------------------------------------------------------------- 1 | add wave * 2 | add wave /glbl/GSR 3 | -------------------------------------------------------------------------------- /single/single.ip_user_files/sim_scripts/inst_mem/vcs/file_info.txt: -------------------------------------------------------------------------------- 1 | dist_mem_gen_v8_0.v,verilog,dist_mem_gen_v8_0_13,../../../ipstatic/simulation/dist_mem_gen_v8_0.v, 2 | inst_mem.v,verilog,xil_defaultlib,../../../../single.srcs/sources_1/ip/inst_mem/sim/inst_mem.v, 3 | glbl.v,Verilog,xil_defaultlib,glbl.v 4 | -------------------------------------------------------------------------------- /single/single.ip_user_files/sim_scripts/inst_mem/vcs/simulate.do: -------------------------------------------------------------------------------- 1 | run 2 | quit 3 | -------------------------------------------------------------------------------- /single/single.ip_user_files/sim_scripts/inst_mem/xcelium/file_info.txt: -------------------------------------------------------------------------------- 1 | dist_mem_gen_v8_0.v,verilog,dist_mem_gen_v8_0_13,../../../ipstatic/simulation/dist_mem_gen_v8_0.v, 2 | inst_mem.v,verilog,xil_defaultlib,../../../../single.srcs/sources_1/ip/inst_mem/sim/inst_mem.v, 3 | glbl.v,Verilog,xil_defaultlib,glbl.v 4 | -------------------------------------------------------------------------------- /single/single.ip_user_files/sim_scripts/inst_mem/xcelium/run.f: -------------------------------------------------------------------------------- 1 | -makelib xcelium_lib/dist_mem_gen_v8_0_13 \ 2 | "../../../ipstatic/simulation/dist_mem_gen_v8_0.v" \ 3 | -endlib 4 | -makelib xcelium_lib/xil_defaultlib \ 5 | "../../../../single.srcs/sources_1/ip/inst_mem/sim/inst_mem.v" \ 6 | -endlib 7 | -makelib xcelium_lib/xil_defaultlib \ 8 | glbl.v 9 | -endlib 10 | 11 | -------------------------------------------------------------------------------- /single/single.ip_user_files/sim_scripts/inst_mem/xsim/cmd.tcl: -------------------------------------------------------------------------------- 1 | set curr_wave [current_wave_config] 2 | if { [string length $curr_wave] == 0 } { 3 | if { [llength [get_objects]] > 0} { 4 | add_wave / 5 | set_property needs_save false [current_wave_config] 6 | } else { 7 | send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." 8 | } 9 | } 10 | 11 | run -all 12 | quit 13 | -------------------------------------------------------------------------------- /single/single.ip_user_files/sim_scripts/inst_mem/xsim/elab.opt: -------------------------------------------------------------------------------- 1 | --relax --debug typical --mt auto -L dist_mem_gen_v8_0_13 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot inst_mem xil_defaultlib.inst_mem xil_defaultlib.glbl -log elaborate.log 2 | -------------------------------------------------------------------------------- /single/single.ip_user_files/sim_scripts/inst_mem/xsim/file_info.txt: -------------------------------------------------------------------------------- 1 | inst_mem.v,verilog,xil_defaultlib,../../../../single.srcs/sources_1/ip/inst_mem/sim/inst_mem.v, 2 | glbl.v,Verilog,xil_defaultlib,glbl.v 3 | -------------------------------------------------------------------------------- /single/single.ip_user_files/sim_scripts/inst_mem/xsim/vlog.prj: -------------------------------------------------------------------------------- 1 | verilog xil_defaultlib \ 2 | "../../../../single.srcs/sources_1/ip/inst_mem/sim/inst_mem.v" \ 3 | 4 | verilog xil_defaultlib "glbl.v" 5 | 6 | nosort 7 | -------------------------------------------------------------------------------- /single/single.runs/.jobs/vrs_config_1.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | -------------------------------------------------------------------------------- /single/single.runs/.jobs/vrs_config_2.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | -------------------------------------------------------------------------------- /single/single.runs/.jobs/vrs_config_3.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | -------------------------------------------------------------------------------- /single/single.runs/cpuclk_synth_1/.Vivado_Synthesis.queue.rst: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/RegiaYoung/RISC-V-CPU/f410822af82f772b51abdce42b78c99bbe729cba/single/single.runs/cpuclk_synth_1/.Vivado_Synthesis.queue.rst -------------------------------------------------------------------------------- /single/single.runs/cpuclk_synth_1/.Xil/cpuclk_propImpl.xdc: -------------------------------------------------------------------------------- 1 | set_property SRC_FILE_INFO {cfile:d:/STUDY/CPU/single/single.srcs/sources_1/ip/cpuclk/cpuclk.xdc rfile:../../../single.srcs/sources_1/ip/cpuclk/cpuclk.xdc id:1 order:EARLY scoped_inst:inst} [current_design] 2 | current_instance inst 3 | set_property src_info {type:SCOPED_XDC file:1 line:57 export:INPUT save:INPUT read:READ} [current_design] 4 | set_input_jitter [get_clocks -of_objects [get_ports clk_in1]] 0.1 5 | -------------------------------------------------------------------------------- /single/single.runs/cpuclk_synth_1/.vivado.begin.rst: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | -------------------------------------------------------------------------------- /single/single.runs/cpuclk_synth_1/.vivado.end.rst: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/RegiaYoung/RISC-V-CPU/f410822af82f772b51abdce42b78c99bbe729cba/single/single.runs/cpuclk_synth_1/.vivado.end.rst -------------------------------------------------------------------------------- /single/single.runs/cpuclk_synth_1/__synthesis_is_complete__: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/RegiaYoung/RISC-V-CPU/f410822af82f772b51abdce42b78c99bbe729cba/single/single.runs/cpuclk_synth_1/__synthesis_is_complete__ -------------------------------------------------------------------------------- /single/single.runs/cpuclk_synth_1/cpuclk.dcp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/RegiaYoung/RISC-V-CPU/f410822af82f772b51abdce42b78c99bbe729cba/single/single.runs/cpuclk_synth_1/cpuclk.dcp -------------------------------------------------------------------------------- /single/single.runs/cpuclk_synth_1/cpuclk_utilization_synth.pb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/RegiaYoung/RISC-V-CPU/f410822af82f772b51abdce42b78c99bbe729cba/single/single.runs/cpuclk_synth_1/cpuclk_utilization_synth.pb -------------------------------------------------------------------------------- /single/single.runs/cpuclk_synth_1/htr.txt: -------------------------------------------------------------------------------- 1 | REM 2 | REM Vivado(TM) 3 | REM htr.txt: a Vivado-generated description of how-to-repeat the 4 | REM the basic steps of a run. Note that runme.bat/sh needs 5 | REM to be invoked for Vivado to track run status. 6 | REM Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 7 | REM 8 | 9 | vivado -log cpuclk.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source cpuclk.tcl 10 | -------------------------------------------------------------------------------- /single/single.runs/cpuclk_synth_1/rundef.js: -------------------------------------------------------------------------------- 1 | // 2 | // Vivado(TM) 3 | // rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6 4 | // Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 5 | // 6 | 7 | var WshShell = new ActiveXObject( "WScript.Shell" ); 8 | var ProcEnv = WshShell.Environment( "Process" ); 9 | var PathVal = ProcEnv("PATH"); 10 | if ( PathVal.length == 0 ) { 11 | PathVal = "D:/Applications/Vivado2020/Vivado/2019.2/ids_lite/ISE/bin/nt64;D:/Applications/Vivado2020/Vivado/2019.2/ids_lite/ISE/lib/nt64;D:/Applications/Vivado2020/Vivado/2019.2/bin;"; 12 | } else { 13 | PathVal = "D:/Applications/Vivado2020/Vivado/2019.2/ids_lite/ISE/bin/nt64;D:/Applications/Vivado2020/Vivado/2019.2/ids_lite/ISE/lib/nt64;D:/Applications/Vivado2020/Vivado/2019.2/bin;" + PathVal; 14 | } 15 | 16 | ProcEnv("PATH") = PathVal; 17 | 18 | var RDScrFP = WScript.ScriptFullName; 19 | var RDScrN = WScript.ScriptName; 20 | var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 ); 21 | var ISEJScriptLib = RDScrDir + "/ISEWrap.js"; 22 | eval( EAInclude(ISEJScriptLib) ); 23 | 24 | 25 | ISEStep( "vivado", 26 | "-log cpuclk.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source cpuclk.tcl" ); 27 | 28 | 29 | 30 | function EAInclude( EAInclFilename ) { 31 | var EAFso = new ActiveXObject( "Scripting.FileSystemObject" ); 32 | var EAInclFile = EAFso.OpenTextFile( EAInclFilename ); 33 | var EAIFContents = EAInclFile.ReadAll(); 34 | EAInclFile.Close(); 35 | return EAIFContents; 36 | } 37 | -------------------------------------------------------------------------------- /single/single.runs/cpuclk_synth_1/runme.bat: -------------------------------------------------------------------------------- 1 | @echo off 2 | 3 | rem Vivado (TM) 4 | rem runme.bat: a Vivado-generated Script 5 | rem Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 6 | 7 | 8 | set HD_SDIR=%~dp0 9 | cd /d "%HD_SDIR%" 10 | cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %* 11 | -------------------------------------------------------------------------------- /single/single.runs/cpuclk_synth_1/runme.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | # 4 | # Vivado(TM) 5 | # runme.sh: a Vivado-generated Runs Script for UNIX 6 | # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 7 | # 8 | 9 | echo "This script was generated under a different operating system." 10 | echo "Please update the PATH and LD_LIBRARY_PATH variables below, before executing this script" 11 | exit 12 | 13 | if [ -z "$PATH" ]; then 14 | PATH=D:/Applications/Vivado2020/Vivado/2019.2/ids_lite/ISE/bin/nt64;D:/Applications/Vivado2020/Vivado/2019.2/ids_lite/ISE/lib/nt64:D:/Applications/Vivado2020/Vivado/2019.2/bin 15 | else 16 | PATH=D:/Applications/Vivado2020/Vivado/2019.2/ids_lite/ISE/bin/nt64;D:/Applications/Vivado2020/Vivado/2019.2/ids_lite/ISE/lib/nt64:D:/Applications/Vivado2020/Vivado/2019.2/bin:$PATH 17 | fi 18 | export PATH 19 | 20 | if [ -z "$LD_LIBRARY_PATH" ]; then 21 | LD_LIBRARY_PATH= 22 | else 23 | LD_LIBRARY_PATH=:$LD_LIBRARY_PATH 24 | fi 25 | export LD_LIBRARY_PATH 26 | 27 | HD_PWD='D:/STUDY/CPU/single/single.runs/cpuclk_synth_1' 28 | cd "$HD_PWD" 29 | 30 | HD_LOG=runme.log 31 | /bin/touch $HD_LOG 32 | 33 | ISEStep="./ISEWrap.sh" 34 | EAStep() 35 | { 36 | $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1 37 | if [ $? -ne 0 ] 38 | then 39 | exit 40 | fi 41 | } 42 | 43 | EAStep vivado -log cpuclk.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source cpuclk.tcl 44 | -------------------------------------------------------------------------------- /single/single.runs/cpuclk_synth_1/vivado.jou: -------------------------------------------------------------------------------- 1 | #----------------------------------------------------------- 2 | # Vivado v2019.2 (64-bit) 3 | # SW Build 2708876 on Wed Nov 6 21:40:23 MST 2019 4 | # IP Build 2700528 on Thu Nov 7 00:09:20 MST 2019 5 | # Start of session at: Mon Sep 6 16:54:08 2021 6 | # Process ID: 5904 7 | # Current directory: D:/STUDY/CPU/single/single.runs/cpuclk_synth_1 8 | # Command line: vivado.exe -log cpuclk.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source cpuclk.tcl 9 | # Log file: D:/STUDY/CPU/single/single.runs/cpuclk_synth_1/cpuclk.vds 10 | # Journal file: D:/STUDY/CPU/single/single.runs/cpuclk_synth_1\vivado.jou 11 | #----------------------------------------------------------- 12 | source cpuclk.tcl -notrace 13 | -------------------------------------------------------------------------------- /single/single.runs/cpuclk_synth_1/vivado.pb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/RegiaYoung/RISC-V-CPU/f410822af82f772b51abdce42b78c99bbe729cba/single/single.runs/cpuclk_synth_1/vivado.pb -------------------------------------------------------------------------------- /single/single.runs/data_mem_synth_1/.Vivado_Synthesis.queue.rst: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/RegiaYoung/RISC-V-CPU/f410822af82f772b51abdce42b78c99bbe729cba/single/single.runs/data_mem_synth_1/.Vivado_Synthesis.queue.rst -------------------------------------------------------------------------------- /single/single.runs/data_mem_synth_1/.vivado.begin.rst: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | -------------------------------------------------------------------------------- /single/single.runs/data_mem_synth_1/.vivado.end.rst: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/RegiaYoung/RISC-V-CPU/f410822af82f772b51abdce42b78c99bbe729cba/single/single.runs/data_mem_synth_1/.vivado.end.rst -------------------------------------------------------------------------------- /single/single.runs/data_mem_synth_1/__synthesis_is_complete__: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/RegiaYoung/RISC-V-CPU/f410822af82f772b51abdce42b78c99bbe729cba/single/single.runs/data_mem_synth_1/__synthesis_is_complete__ -------------------------------------------------------------------------------- /single/single.runs/data_mem_synth_1/data_mem.dcp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/RegiaYoung/RISC-V-CPU/f410822af82f772b51abdce42b78c99bbe729cba/single/single.runs/data_mem_synth_1/data_mem.dcp -------------------------------------------------------------------------------- /single/single.runs/data_mem_synth_1/data_mem_utilization_synth.pb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/RegiaYoung/RISC-V-CPU/f410822af82f772b51abdce42b78c99bbe729cba/single/single.runs/data_mem_synth_1/data_mem_utilization_synth.pb -------------------------------------------------------------------------------- /single/single.runs/data_mem_synth_1/dont_touch.xdc: -------------------------------------------------------------------------------- 1 | # This file is automatically generated. 2 | # It contains project source information necessary for synthesis and implementation. 3 | 4 | # IP: d:/STUDY/CPU/single/single.srcs/sources_1/ip/data_mem/data_mem.xci 5 | # IP: The module: 'data_mem' is the root of the design. Do not add the DONT_TOUCH constraint. 6 | 7 | # XDC: d:/STUDY/CPU/single/single.srcs/sources_1/ip/data_mem/data_mem_ooc.xdc 8 | # XDC: The top module name and the constraint reference have the same name: 'data_mem'. Do not add the DONT_TOUCH constraint. 9 | set_property DONT_TOUCH TRUE [get_cells U0 -quiet] -quiet 10 | 11 | # IP: d:/STUDY/CPU/single/single.srcs/sources_1/ip/data_mem/data_mem.xci 12 | # IP: The module: 'data_mem' is the root of the design. Do not add the DONT_TOUCH constraint. 13 | 14 | # XDC: d:/STUDY/CPU/single/single.srcs/sources_1/ip/data_mem/data_mem_ooc.xdc 15 | # XDC: The top module name and the constraint reference have the same name: 'data_mem'. Do not add the DONT_TOUCH constraint. 16 | #dup# set_property DONT_TOUCH TRUE [get_cells U0 -quiet] -quiet 17 | -------------------------------------------------------------------------------- /single/single.runs/data_mem_synth_1/htr.txt: -------------------------------------------------------------------------------- 1 | REM 2 | REM Vivado(TM) 3 | REM htr.txt: a Vivado-generated description of how-to-repeat the 4 | REM the basic steps of a run. Note that runme.bat/sh needs 5 | REM to be invoked for Vivado to track run status. 6 | REM Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 7 | REM 8 | 9 | vivado -log data_mem.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source data_mem.tcl 10 | -------------------------------------------------------------------------------- /single/single.runs/data_mem_synth_1/rundef.js: -------------------------------------------------------------------------------- 1 | // 2 | // Vivado(TM) 3 | // rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6 4 | // Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 5 | // 6 | 7 | var WshShell = new ActiveXObject( "WScript.Shell" ); 8 | var ProcEnv = WshShell.Environment( "Process" ); 9 | var PathVal = ProcEnv("PATH"); 10 | if ( PathVal.length == 0 ) { 11 | PathVal = "D:/Applications/Vivado2020/Vivado/2019.2/ids_lite/ISE/bin/nt64;D:/Applications/Vivado2020/Vivado/2019.2/ids_lite/ISE/lib/nt64;D:/Applications/Vivado2020/Vivado/2019.2/bin;"; 12 | } else { 13 | PathVal = "D:/Applications/Vivado2020/Vivado/2019.2/ids_lite/ISE/bin/nt64;D:/Applications/Vivado2020/Vivado/2019.2/ids_lite/ISE/lib/nt64;D:/Applications/Vivado2020/Vivado/2019.2/bin;" + PathVal; 14 | } 15 | 16 | ProcEnv("PATH") = PathVal; 17 | 18 | var RDScrFP = WScript.ScriptFullName; 19 | var RDScrN = WScript.ScriptName; 20 | var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 ); 21 | var ISEJScriptLib = RDScrDir + "/ISEWrap.js"; 22 | eval( EAInclude(ISEJScriptLib) ); 23 | 24 | 25 | ISEStep( "vivado", 26 | "-log data_mem.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source data_mem.tcl" ); 27 | 28 | 29 | 30 | function EAInclude( EAInclFilename ) { 31 | var EAFso = new ActiveXObject( "Scripting.FileSystemObject" ); 32 | var EAInclFile = EAFso.OpenTextFile( EAInclFilename ); 33 | var EAIFContents = EAInclFile.ReadAll(); 34 | EAInclFile.Close(); 35 | return EAIFContents; 36 | } 37 | -------------------------------------------------------------------------------- /single/single.runs/data_mem_synth_1/runme.bat: -------------------------------------------------------------------------------- 1 | @echo off 2 | 3 | rem Vivado (TM) 4 | rem runme.bat: a Vivado-generated Script 5 | rem Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 6 | 7 | 8 | set HD_SDIR=%~dp0 9 | cd /d "%HD_SDIR%" 10 | cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %* 11 | -------------------------------------------------------------------------------- /single/single.runs/data_mem_synth_1/runme.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | # 4 | # Vivado(TM) 5 | # runme.sh: a Vivado-generated Runs Script for UNIX 6 | # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 7 | # 8 | 9 | echo "This script was generated under a different operating system." 10 | echo "Please update the PATH and LD_LIBRARY_PATH variables below, before executing this script" 11 | exit 12 | 13 | if [ -z "$PATH" ]; then 14 | PATH=D:/Applications/Vivado2020/Vivado/2019.2/ids_lite/ISE/bin/nt64;D:/Applications/Vivado2020/Vivado/2019.2/ids_lite/ISE/lib/nt64:D:/Applications/Vivado2020/Vivado/2019.2/bin 15 | else 16 | PATH=D:/Applications/Vivado2020/Vivado/2019.2/ids_lite/ISE/bin/nt64;D:/Applications/Vivado2020/Vivado/2019.2/ids_lite/ISE/lib/nt64:D:/Applications/Vivado2020/Vivado/2019.2/bin:$PATH 17 | fi 18 | export PATH 19 | 20 | if [ -z "$LD_LIBRARY_PATH" ]; then 21 | LD_LIBRARY_PATH= 22 | else 23 | LD_LIBRARY_PATH=:$LD_LIBRARY_PATH 24 | fi 25 | export LD_LIBRARY_PATH 26 | 27 | HD_PWD='D:/STUDY/CPU/single/single.runs/data_mem_synth_1' 28 | cd "$HD_PWD" 29 | 30 | HD_LOG=runme.log 31 | /bin/touch $HD_LOG 32 | 33 | ISEStep="./ISEWrap.sh" 34 | EAStep() 35 | { 36 | $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1 37 | if [ $? -ne 0 ] 38 | then 39 | exit 40 | fi 41 | } 42 | 43 | EAStep vivado -log data_mem.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source data_mem.tcl 44 | -------------------------------------------------------------------------------- /single/single.runs/data_mem_synth_1/vivado.jou: -------------------------------------------------------------------------------- 1 | #----------------------------------------------------------- 2 | # Vivado v2019.2 (64-bit) 3 | # SW Build 2708876 on Wed Nov 6 21:40:23 MST 2019 4 | # IP Build 2700528 on Thu Nov 7 00:09:20 MST 2019 5 | # Start of session at: Mon Sep 6 16:56:03 2021 6 | # Process ID: 9564 7 | # Current directory: D:/STUDY/CPU/single/single.runs/data_mem_synth_1 8 | # Command line: vivado.exe -log data_mem.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source data_mem.tcl 9 | # Log file: D:/STUDY/CPU/single/single.runs/data_mem_synth_1/data_mem.vds 10 | # Journal file: D:/STUDY/CPU/single/single.runs/data_mem_synth_1\vivado.jou 11 | #----------------------------------------------------------- 12 | source data_mem.tcl -notrace 13 | -------------------------------------------------------------------------------- /single/single.runs/data_mem_synth_1/vivado.pb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/RegiaYoung/RISC-V-CPU/f410822af82f772b51abdce42b78c99bbe729cba/single/single.runs/data_mem_synth_1/vivado.pb -------------------------------------------------------------------------------- /single/single.runs/inst_mem_synth_1/.Vivado_Synthesis.queue.rst: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/RegiaYoung/RISC-V-CPU/f410822af82f772b51abdce42b78c99bbe729cba/single/single.runs/inst_mem_synth_1/.Vivado_Synthesis.queue.rst -------------------------------------------------------------------------------- /single/single.runs/inst_mem_synth_1/.vivado.begin.rst: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | -------------------------------------------------------------------------------- /single/single.runs/inst_mem_synth_1/.vivado.end.rst: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/RegiaYoung/RISC-V-CPU/f410822af82f772b51abdce42b78c99bbe729cba/single/single.runs/inst_mem_synth_1/.vivado.end.rst -------------------------------------------------------------------------------- /single/single.runs/inst_mem_synth_1/__synthesis_is_complete__: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/RegiaYoung/RISC-V-CPU/f410822af82f772b51abdce42b78c99bbe729cba/single/single.runs/inst_mem_synth_1/__synthesis_is_complete__ -------------------------------------------------------------------------------- /single/single.runs/inst_mem_synth_1/dont_touch.xdc: -------------------------------------------------------------------------------- 1 | # This file is automatically generated. 2 | # It contains project source information necessary for synthesis and implementation. 3 | 4 | # IP: d:/STUDY/CPU/single/single.srcs/sources_1/ip/inst_mem/inst_mem.xci 5 | # IP: The module: 'inst_mem' is the root of the design. Do not add the DONT_TOUCH constraint. 6 | 7 | # XDC: d:/STUDY/CPU/single/single.srcs/sources_1/ip/inst_mem/inst_mem_ooc.xdc 8 | # XDC: The top module name and the constraint reference have the same name: 'inst_mem'. Do not add the DONT_TOUCH constraint. 9 | set_property DONT_TOUCH TRUE [get_cells U0 -quiet] -quiet 10 | 11 | # IP: d:/STUDY/CPU/single/single.srcs/sources_1/ip/inst_mem/inst_mem.xci 12 | # IP: The module: 'inst_mem' is the root of the design. Do not add the DONT_TOUCH constraint. 13 | 14 | # XDC: d:/STUDY/CPU/single/single.srcs/sources_1/ip/inst_mem/inst_mem_ooc.xdc 15 | # XDC: The top module name and the constraint reference have the same name: 'inst_mem'. Do not add the DONT_TOUCH constraint. 16 | #dup# set_property DONT_TOUCH TRUE [get_cells U0 -quiet] -quiet 17 | -------------------------------------------------------------------------------- /single/single.runs/inst_mem_synth_1/htr.txt: -------------------------------------------------------------------------------- 1 | REM 2 | REM Vivado(TM) 3 | REM htr.txt: a Vivado-generated description of how-to-repeat the 4 | REM the basic steps of a run. Note that runme.bat/sh needs 5 | REM to be invoked for Vivado to track run status. 6 | REM Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 7 | REM 8 | 9 | vivado -log inst_mem.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source inst_mem.tcl 10 | -------------------------------------------------------------------------------- /single/single.runs/inst_mem_synth_1/inst_mem.dcp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/RegiaYoung/RISC-V-CPU/f410822af82f772b51abdce42b78c99bbe729cba/single/single.runs/inst_mem_synth_1/inst_mem.dcp -------------------------------------------------------------------------------- /single/single.runs/inst_mem_synth_1/inst_mem_utilization_synth.pb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/RegiaYoung/RISC-V-CPU/f410822af82f772b51abdce42b78c99bbe729cba/single/single.runs/inst_mem_synth_1/inst_mem_utilization_synth.pb -------------------------------------------------------------------------------- /single/single.runs/inst_mem_synth_1/rundef.js: -------------------------------------------------------------------------------- 1 | // 2 | // Vivado(TM) 3 | // rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6 4 | // Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 5 | // 6 | 7 | var WshShell = new ActiveXObject( "WScript.Shell" ); 8 | var ProcEnv = WshShell.Environment( "Process" ); 9 | var PathVal = ProcEnv("PATH"); 10 | if ( PathVal.length == 0 ) { 11 | PathVal = "D:/Applications/Vivado2020/Vivado/2019.2/ids_lite/ISE/bin/nt64;D:/Applications/Vivado2020/Vivado/2019.2/ids_lite/ISE/lib/nt64;D:/Applications/Vivado2020/Vivado/2019.2/bin;"; 12 | } else { 13 | PathVal = "D:/Applications/Vivado2020/Vivado/2019.2/ids_lite/ISE/bin/nt64;D:/Applications/Vivado2020/Vivado/2019.2/ids_lite/ISE/lib/nt64;D:/Applications/Vivado2020/Vivado/2019.2/bin;" + PathVal; 14 | } 15 | 16 | ProcEnv("PATH") = PathVal; 17 | 18 | var RDScrFP = WScript.ScriptFullName; 19 | var RDScrN = WScript.ScriptName; 20 | var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 ); 21 | var ISEJScriptLib = RDScrDir + "/ISEWrap.js"; 22 | eval( EAInclude(ISEJScriptLib) ); 23 | 24 | 25 | ISEStep( "vivado", 26 | "-log inst_mem.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source inst_mem.tcl" ); 27 | 28 | 29 | 30 | function EAInclude( EAInclFilename ) { 31 | var EAFso = new ActiveXObject( "Scripting.FileSystemObject" ); 32 | var EAInclFile = EAFso.OpenTextFile( EAInclFilename ); 33 | var EAIFContents = EAInclFile.ReadAll(); 34 | EAInclFile.Close(); 35 | return EAIFContents; 36 | } 37 | -------------------------------------------------------------------------------- /single/single.runs/inst_mem_synth_1/runme.bat: -------------------------------------------------------------------------------- 1 | @echo off 2 | 3 | rem Vivado (TM) 4 | rem runme.bat: a Vivado-generated Script 5 | rem Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 6 | 7 | 8 | set HD_SDIR=%~dp0 9 | cd /d "%HD_SDIR%" 10 | cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %* 11 | -------------------------------------------------------------------------------- /single/single.runs/inst_mem_synth_1/runme.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | # 4 | # Vivado(TM) 5 | # runme.sh: a Vivado-generated Runs Script for UNIX 6 | # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 7 | # 8 | 9 | echo "This script was generated under a different operating system." 10 | echo "Please update the PATH and LD_LIBRARY_PATH variables below, before executing this script" 11 | exit 12 | 13 | if [ -z "$PATH" ]; then 14 | PATH=D:/Applications/Vivado2020/Vivado/2019.2/ids_lite/ISE/bin/nt64;D:/Applications/Vivado2020/Vivado/2019.2/ids_lite/ISE/lib/nt64:D:/Applications/Vivado2020/Vivado/2019.2/bin 15 | else 16 | PATH=D:/Applications/Vivado2020/Vivado/2019.2/ids_lite/ISE/bin/nt64;D:/Applications/Vivado2020/Vivado/2019.2/ids_lite/ISE/lib/nt64:D:/Applications/Vivado2020/Vivado/2019.2/bin:$PATH 17 | fi 18 | export PATH 19 | 20 | if [ -z "$LD_LIBRARY_PATH" ]; then 21 | LD_LIBRARY_PATH= 22 | else 23 | LD_LIBRARY_PATH=:$LD_LIBRARY_PATH 24 | fi 25 | export LD_LIBRARY_PATH 26 | 27 | HD_PWD='D:/STUDY/CPU/single/single.runs/inst_mem_synth_1' 28 | cd "$HD_PWD" 29 | 30 | HD_LOG=runme.log 31 | /bin/touch $HD_LOG 32 | 33 | ISEStep="./ISEWrap.sh" 34 | EAStep() 35 | { 36 | $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1 37 | if [ $? -ne 0 ] 38 | then 39 | exit 40 | fi 41 | } 42 | 43 | EAStep vivado -log inst_mem.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source inst_mem.tcl 44 | -------------------------------------------------------------------------------- /single/single.runs/inst_mem_synth_1/vivado.jou: -------------------------------------------------------------------------------- 1 | #----------------------------------------------------------- 2 | # Vivado v2019.2 (64-bit) 3 | # SW Build 2708876 on Wed Nov 6 21:40:23 MST 2019 4 | # IP Build 2700528 on Thu Nov 7 00:09:20 MST 2019 5 | # Start of session at: Mon Sep 6 16:54:40 2021 6 | # Process ID: 17772 7 | # Current directory: D:/STUDY/CPU/single/single.runs/inst_mem_synth_1 8 | # Command line: vivado.exe -log inst_mem.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source inst_mem.tcl 9 | # Log file: D:/STUDY/CPU/single/single.runs/inst_mem_synth_1/inst_mem.vds 10 | # Journal file: D:/STUDY/CPU/single/single.runs/inst_mem_synth_1\vivado.jou 11 | #----------------------------------------------------------- 12 | source inst_mem.tcl -notrace 13 | -------------------------------------------------------------------------------- /single/single.runs/inst_mem_synth_1/vivado.pb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/RegiaYoung/RISC-V-CPU/f410822af82f772b51abdce42b78c99bbe729cba/single/single.runs/inst_mem_synth_1/vivado.pb -------------------------------------------------------------------------------- /single/single.srcs/sources_1/imports/single_cycle/adder_for_plus_4.v: -------------------------------------------------------------------------------- 1 | 2 | 3 | module adder_for_plus_4( 4 | input [31:0] pc_from_pc_i, 5 | output [31:0] pc_plus_4_o 6 | ); 7 | 8 | reg [31:0] pc_plus_4; 9 | assign pc_plus_4_o = pc_plus_4; 10 | always @ (*) 11 | begin 12 | pc_plus_4 = pc_from_pc_i + 4; 13 | end 14 | endmodule 15 | -------------------------------------------------------------------------------- /single/single.srcs/sources_1/imports/single_cycle/algorithm_calculation.v: -------------------------------------------------------------------------------- 1 | 2 | module algorithm_calculation( 3 | input [3:0] algorithm_op_sel_i, 4 | input [31:0] operand_A_i, 5 | input [31:0] operand_B_i, 6 | output [31:0] result_from_algorithm_o 7 | ); 8 | 9 | 10 | 11 | reg [31:0] result; 12 | assign result_from_algorithm_o = result; 13 | always @ (*) 14 | begin 15 | case(algorithm_op_sel_i) 16 | `ADD: result = operand_A_i + operand_B_i; 17 | `SUB: result = operand_A_i + (operand_B_i ^ 32'b1111_1111_1111_1111_1111_1111_1111_1111) + 1'b1; 18 | default:result = 0; 19 | endcase 20 | end 21 | endmodule 22 | -------------------------------------------------------------------------------- /single/single.srcs/sources_1/imports/single_cycle/branch_compare.v: -------------------------------------------------------------------------------- 1 | module branch_compare( 2 | input [31:0] data1_from_rf_i, 3 | input [31:0] data2_from_rf_i, 4 | output [1:0] cmp_result_from_branch_o, 5 | input [2:0] func3 6 | ); 7 | 8 | reg [1:0] cmp_result_from_branch; 9 | assign cmp_result_from_branch_o = cmp_result_from_branch; 10 | always @ (*) 11 | begin 12 | if (func3 == 3'b110 || func3 == 3'b111) cmp_result_from_branch = ((~(data1_from_rf_i < data2_from_rf_i)) ? 2'b01 : 2'b10); 13 | else if (($signed(data1_from_rf_i)) == ($signed(data2_from_rf_i))) cmp_result_from_branch = 2'b00; 14 | else if (($signed(data1_from_rf_i)) > ($signed(data2_from_rf_i))) cmp_result_from_branch = 2'b01; 15 | else cmp_result_from_branch = 2'b10; 16 | end 17 | endmodule 18 | -------------------------------------------------------------------------------- /single/single.srcs/sources_1/imports/single_cycle/logic_calculation.v: -------------------------------------------------------------------------------- 1 | 2 | module logic_calculation( 3 | input [3:0] logic_op_sel_i, 4 | input [31:0] operand_A_i, 5 | input [31:0] operand_B_i, 6 | output [31:0] result_from_logic_o 7 | ); 8 | 9 | 10 | reg [31:0] result; 11 | assign result_from_logic_o = result; 12 | always @ (*) 13 | begin 14 | case(logic_op_sel_i) 15 | `AND: result = operand_A_i & operand_B_i; 16 | `OR: result = operand_A_i | operand_B_i; 17 | `XOR: result = operand_A_i ^ operand_B_i; 18 | default:result = 0; 19 | endcase 20 | end 21 | endmodule 22 | -------------------------------------------------------------------------------- /single/single.srcs/sources_1/imports/single_cycle/mux_2.v: -------------------------------------------------------------------------------- 1 | 2 | 3 | module mux_2( 4 | input select_signal, 5 | input [31:0] input0, 6 | input [31:0] input1, 7 | output [31:0] output_data 8 | ); 9 | 10 | reg [31:0] result; 11 | assign output_data = result; 12 | always @ (*) 13 | begin 14 | if(select_signal) result = input1; 15 | else result = input0; 16 | end 17 | endmodule 18 | -------------------------------------------------------------------------------- /single/single.srcs/sources_1/imports/single_cycle/mux_4.v: -------------------------------------------------------------------------------- 1 | 2 | module mux_4( 3 | input [0:1] select_signal, 4 | input [31:0] input0, 5 | input [31:0] input1, 6 | input [31:0] input2, 7 | input [31:0] input3, 8 | output [31:0] output_data 9 | ); 10 | reg [31:0] result; 11 | assign output_data = result; 12 | always @ (*) 13 | begin 14 | case(select_signal) 15 | 2'b00: result = input0; 16 | 2'b01: result = input1; 17 | 2'b10: result = input2; 18 | 2'b11: result = input3; 19 | default:result = input0; 20 | endcase 21 | end 22 | endmodule 23 | -------------------------------------------------------------------------------- /single/single.srcs/sources_1/imports/single_cycle/param.v: -------------------------------------------------------------------------------- 1 | // file: param.v 2 | `ifndef CPU_PARAM 3 | `define CPU_PARAM 4 | 5 | `define ADD 4'b0000 6 | `define SUB 4'b0001 7 | `define AND 4'b0010 8 | `define OR 4'b0011 9 | `define XOR 4'b0100 10 | `define SLL 4'b0101 11 | `define SRL 4'b0110 12 | `define SRA 4'b0111 13 | 14 | `define SLT 4'b1000 15 | `define SLTU 4'b1001 16 | `define SLTI 4'b1010 17 | `define SLTIU 4'b1011 18 | 19 | `endif 20 | -------------------------------------------------------------------------------- /single/single.srcs/sources_1/imports/single_cycle/program_counter.v: -------------------------------------------------------------------------------- 1 | 2 | 3 | module program_counter( 4 | input clk_i, 5 | input reset_i, 6 | input [31:0] next_pc_i, 7 | output [31:0] pc_o 8 | ); 9 | reg [31:0] pc; 10 | assign pc_o = pc; 11 | 12 | always @ (posedge clk_i or posedge reset_i) 13 | begin 14 | if (reset_i) pc <= 'hffff_fffc; 15 | else pc <= next_pc_i; 16 | end 17 | 18 | 19 | endmodule 20 | -------------------------------------------------------------------------------- /single/single.srcs/sources_1/imports/single_cycle/reg_file.v: -------------------------------------------------------------------------------- 1 | 2 | module reg_file( 3 | input clk_i, 4 | input [4:0] rR1_i, 5 | input [4:0] rR2_i, 6 | input [4:0] wR_i, 7 | input WE_i, 8 | input [31:0] wD_i, 9 | output [31:0] rD1_o, 10 | output [31:0] rD2_o 11 | ); 12 | 13 | reg [31:0] register [0:31]; 14 | reg [31:0] data1; 15 | reg [31:0] data2; 16 | assign rD1_o = data1; 17 | assign rD2_o = data2; 18 | 19 | // read logic 20 | always @ (*) 21 | begin 22 | data1 = register[rR1_i]; 23 | data2 = register[rR2_i]; 24 | end 25 | 26 | // write logic 27 | always @ (posedge clk_i) 28 | begin 29 | register[0] <= 0; 30 | if (WE_i && wR_i != 0) 31 | register[wR_i] <= wD_i; 32 | end 33 | 34 | endmodule 35 | -------------------------------------------------------------------------------- /single/single.srcs/sources_1/ip/cpuclk/cpuclk.dcp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/RegiaYoung/RISC-V-CPU/f410822af82f772b51abdce42b78c99bbe729cba/single/single.srcs/sources_1/ip/cpuclk/cpuclk.dcp -------------------------------------------------------------------------------- /single/single.srcs/sources_1/ip/cpuclk/cpuclk_board.xdc: -------------------------------------------------------------------------------- 1 | #--------------------Physical Constraints----------------- 2 | 3 | -------------------------------------------------------------------------------- /single/single.srcs/sources_1/ip/cpuclk/cpuclk_stub.v: -------------------------------------------------------------------------------- 1 | // Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 2 | // -------------------------------------------------------------------------------- 3 | // Tool Version: Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019 4 | // Date : Mon Sep 6 16:54:51 2021 5 | // Host : DESKTOP-S2SIT85 running 64-bit major release (build 9200) 6 | // Command : write_verilog -force -mode synth_stub d:/STUDY/CPU/single/single.srcs/sources_1/ip/cpuclk/cpuclk_stub.v 7 | // Design : cpuclk 8 | // Purpose : Stub declaration of top-level module interface 9 | // Device : xc7a100tfgg484-1 10 | // -------------------------------------------------------------------------------- 11 | 12 | // This empty module with port declaration file causes synthesis tools to infer a black box for IP. 13 | // The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. 14 | // Please paste the declaration into a Verilog source file or add the file as an additional source. 15 | module cpuclk(clk_out1, locked, clk_in1) 16 | /* synthesis syn_black_box black_box_pad_pin="clk_out1,locked,clk_in1" */; 17 | output clk_out1; 18 | output locked; 19 | input clk_in1; 20 | endmodule 21 | -------------------------------------------------------------------------------- /single/single.srcs/sources_1/ip/cpuclk/cpuclk_stub.vhdl: -------------------------------------------------------------------------------- 1 | -- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 2 | -- -------------------------------------------------------------------------------- 3 | -- Tool Version: Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019 4 | -- Date : Mon Sep 6 16:54:51 2021 5 | -- Host : DESKTOP-S2SIT85 running 64-bit major release (build 9200) 6 | -- Command : write_vhdl -force -mode synth_stub d:/STUDY/CPU/single/single.srcs/sources_1/ip/cpuclk/cpuclk_stub.vhdl 7 | -- Design : cpuclk 8 | -- Purpose : Stub declaration of top-level module interface 9 | -- Device : xc7a100tfgg484-1 10 | -- -------------------------------------------------------------------------------- 11 | library IEEE; 12 | use IEEE.STD_LOGIC_1164.ALL; 13 | 14 | entity cpuclk is 15 | Port ( 16 | clk_out1 : out STD_LOGIC; 17 | locked : out STD_LOGIC; 18 | clk_in1 : in STD_LOGIC 19 | ); 20 | 21 | end cpuclk; 22 | 23 | architecture stub of cpuclk is 24 | attribute syn_black_box : boolean; 25 | attribute black_box_pad_pin : string; 26 | attribute syn_black_box of stub : architecture is true; 27 | attribute black_box_pad_pin of stub : architecture is "clk_out1,locked,clk_in1"; 28 | begin 29 | end; 30 | -------------------------------------------------------------------------------- /single/single.srcs/sources_1/ip/data_mem/data_mem.dcp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/RegiaYoung/RISC-V-CPU/f410822af82f772b51abdce42b78c99bbe729cba/single/single.srcs/sources_1/ip/data_mem/data_mem.dcp -------------------------------------------------------------------------------- /single/single.srcs/sources_1/ip/data_mem/data_mem_stub.v: -------------------------------------------------------------------------------- 1 | // Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 2 | // -------------------------------------------------------------------------------- 3 | // Tool Version: Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019 4 | // Date : Mon Sep 6 16:57:21 2021 5 | // Host : DESKTOP-S2SIT85 running 64-bit major release (build 9200) 6 | // Command : write_verilog -force -mode synth_stub 7 | // d:/STUDY/CPU/single/single.srcs/sources_1/ip/data_mem/data_mem_stub.v 8 | // Design : data_mem 9 | // Purpose : Stub declaration of top-level module interface 10 | // Device : xc7a100tfgg484-1 11 | // -------------------------------------------------------------------------------- 12 | 13 | // This empty module with port declaration file causes synthesis tools to infer a black box for IP. 14 | // The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. 15 | // Please paste the declaration into a Verilog source file or add the file as an additional source. 16 | (* x_core_info = "dist_mem_gen_v8_0_13,Vivado 2019.2" *) 17 | module data_mem(a, d, clk, we, spo) 18 | /* synthesis syn_black_box black_box_pad_pin="a[13:0],d[31:0],clk,we,spo[31:0]" */; 19 | input [13:0]a; 20 | input [31:0]d; 21 | input clk; 22 | input we; 23 | output [31:0]spo; 24 | endmodule 25 | -------------------------------------------------------------------------------- /single/single.srcs/sources_1/ip/data_mem/data_mem_stub.vhdl: -------------------------------------------------------------------------------- 1 | -- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 2 | -- -------------------------------------------------------------------------------- 3 | -- Tool Version: Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019 4 | -- Date : Mon Sep 6 16:57:21 2021 5 | -- Host : DESKTOP-S2SIT85 running 64-bit major release (build 9200) 6 | -- Command : write_vhdl -force -mode synth_stub 7 | -- d:/STUDY/CPU/single/single.srcs/sources_1/ip/data_mem/data_mem_stub.vhdl 8 | -- Design : data_mem 9 | -- Purpose : Stub declaration of top-level module interface 10 | -- Device : xc7a100tfgg484-1 11 | -- -------------------------------------------------------------------------------- 12 | library IEEE; 13 | use IEEE.STD_LOGIC_1164.ALL; 14 | 15 | entity data_mem is 16 | Port ( 17 | a : in STD_LOGIC_VECTOR ( 13 downto 0 ); 18 | d : in STD_LOGIC_VECTOR ( 31 downto 0 ); 19 | clk : in STD_LOGIC; 20 | we : in STD_LOGIC; 21 | spo : out STD_LOGIC_VECTOR ( 31 downto 0 ) 22 | ); 23 | 24 | end data_mem; 25 | 26 | architecture stub of data_mem is 27 | attribute syn_black_box : boolean; 28 | attribute black_box_pad_pin : string; 29 | attribute syn_black_box of stub : architecture is true; 30 | attribute black_box_pad_pin of stub : architecture is "a[13:0],d[31:0],clk,we,spo[31:0]"; 31 | attribute x_core_info : string; 32 | attribute x_core_info of stub : architecture is "dist_mem_gen_v8_0_13,Vivado 2019.2"; 33 | begin 34 | end; 35 | -------------------------------------------------------------------------------- /single/single.srcs/sources_1/ip/inst_mem/inst_mem.dcp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/RegiaYoung/RISC-V-CPU/f410822af82f772b51abdce42b78c99bbe729cba/single/single.srcs/sources_1/ip/inst_mem/inst_mem.dcp -------------------------------------------------------------------------------- /single/single.srcs/sources_1/ip/inst_mem/inst_mem_stub.v: -------------------------------------------------------------------------------- 1 | // Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 2 | // -------------------------------------------------------------------------------- 3 | // Tool Version: Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019 4 | // Date : Mon Sep 6 16:55:32 2021 5 | // Host : DESKTOP-S2SIT85 running 64-bit major release (build 9200) 6 | // Command : write_verilog -force -mode synth_stub 7 | // d:/STUDY/CPU/single/single.srcs/sources_1/ip/inst_mem/inst_mem_stub.v 8 | // Design : inst_mem 9 | // Purpose : Stub declaration of top-level module interface 10 | // Device : xc7a100tfgg484-1 11 | // -------------------------------------------------------------------------------- 12 | 13 | // This empty module with port declaration file causes synthesis tools to infer a black box for IP. 14 | // The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. 15 | // Please paste the declaration into a Verilog source file or add the file as an additional source. 16 | (* x_core_info = "dist_mem_gen_v8_0_13,Vivado 2019.2" *) 17 | module inst_mem(a, spo) 18 | /* synthesis syn_black_box black_box_pad_pin="a[13:0],spo[31:0]" */; 19 | input [13:0]a; 20 | output [31:0]spo; 21 | endmodule 22 | -------------------------------------------------------------------------------- /single/single.srcs/sources_1/ip/inst_mem/inst_mem_stub.vhdl: -------------------------------------------------------------------------------- 1 | -- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 2 | -- -------------------------------------------------------------------------------- 3 | -- Tool Version: Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019 4 | -- Date : Mon Sep 6 16:55:32 2021 5 | -- Host : DESKTOP-S2SIT85 running 64-bit major release (build 9200) 6 | -- Command : write_vhdl -force -mode synth_stub 7 | -- d:/STUDY/CPU/single/single.srcs/sources_1/ip/inst_mem/inst_mem_stub.vhdl 8 | -- Design : inst_mem 9 | -- Purpose : Stub declaration of top-level module interface 10 | -- Device : xc7a100tfgg484-1 11 | -- -------------------------------------------------------------------------------- 12 | library IEEE; 13 | use IEEE.STD_LOGIC_1164.ALL; 14 | 15 | entity inst_mem is 16 | Port ( 17 | a : in STD_LOGIC_VECTOR ( 13 downto 0 ); 18 | spo : out STD_LOGIC_VECTOR ( 31 downto 0 ) 19 | ); 20 | 21 | end inst_mem; 22 | 23 | architecture stub of inst_mem is 24 | attribute syn_black_box : boolean; 25 | attribute black_box_pad_pin : string; 26 | attribute syn_black_box of stub : architecture is true; 27 | attribute black_box_pad_pin of stub : architecture is "a[13:0],spo[31:0]"; 28 | attribute x_core_info : string; 29 | attribute x_core_info of stub : architecture is "dist_mem_gen_v8_0_13,Vivado 2019.2"; 30 | begin 31 | end; 32 | --------------------------------------------------------------------------------