├── .gitattributes ├── .gitignore ├── ChangeLog.md ├── README.md ├── Src ├── Cache │ ├── DCache_Controller.v │ ├── DCache_Ram.v │ ├── ICache_Controller.v │ └── ICache_Ram.v ├── Config.v ├── Core │ ├── ALU_EX.v │ ├── ALU_MEM.v │ ├── CP0.v │ ├── Control.v │ ├── Core_Top.v │ ├── Decode.v │ ├── Divider.v │ ├── Exception.v │ ├── HiLo_LLbit.v │ ├── MMU.v │ ├── PC.v │ ├── RegFile.v │ ├── Reg_EX_MEM.v │ ├── Reg_ID_EX.v │ ├── Reg_IF_ID.v │ ├── Reg_MEM_WB.v │ ├── TLBU.v │ └── WriteBack.v ├── Defines.v ├── MangoMIPS_Top.v ├── NSCSCC_Top │ ├── nscscc_axi_top.v │ └── nscscc_sram_top.v └── Xilinx_IP │ ├── Bus_Interface │ └── Bus_Interface.xci │ ├── DCache_Ram_IP │ └── DCache_Ram_IP.xci │ └── ICache_Ram_IP │ └── ICache_Ram_IP.xci └── Testbench ├── Bin2Mem ├── Bin2Mem-BE.c ├── Bin2Mem-BE.exe ├── Bin2Mem-LE.c └── Bin2Mem-LE.exe ├── Cache_Test ├── Makefile ├── ram.ld ├── test.S └── test_ram.data └── TLB_Test ├── Makefile ├── ram.ld ├── test.S └── test_ram.data /.gitattributes: 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