├── .gitignore ├── .gitmodules ├── LICENSE.md ├── README.md ├── bench └── verilog │ ├── AHB3LiteBus.sv │ ├── AHB3LiteDrv.sv │ ├── AHB3LiteMon.sv │ ├── AHB3Lite_hdr.sv │ ├── AHBBusTr.sv │ ├── BaseConfig.sv │ ├── BaseDrv.sv │ ├── BaseMon.sv │ ├── BaseScoreBoard.sv │ ├── BaseTr.sv │ ├── BusGenerator.sv │ ├── BusTr.sv │ ├── Config.sv │ ├── Environment.sv │ ├── ScoreBoard.sv │ ├── ahb3lite_if.sv │ ├── test.sv │ ├── testbench_pkg.sv │ └── testbench_top.sv ├── docs ├── Gemfile ├── _config.yml ├── _layouts │ └── roalogic.html ├── _pages │ ├── index.md │ ├── license.md │ └── test.md ├── _sass │ ├── rlskin.scss │ ├── roalogic.scss │ └── rouge-github.scss ├── ahb3lite_interconnect_datasheet.md ├── ahb3lite_interconnect_datasheet.pdf ├── ahb3lite_interconnect_datasheet.tex ├── assets │ ├── css │ │ └── style.scss │ ├── graffle │ │ └── AHB-Lite-Switch.graffle │ ├── img │ │ ├── RoaLogicHeader-eps-converted-to.pdf │ │ ├── RoaLogicHeader.eps │ │ ├── RoaLogicHeader.png │ │ ├── RoaLogicLogo.png │ │ ├── Tagged_Logo-eps-converted-to.pdf │ │ ├── Tagged_Logo.eps │ │ ├── ahb-lite-switch-sys-eps-converted-to.pdf │ │ ├── ahb-lite-switch-sys.eps │ │ ├── ahb-lite-switch-sys.png │ │ ├── ahb-lite-switch-sys1-eps-converted-to.pdf │ │ ├── ahb-lite-switch-sys1.eps │ │ ├── ahb-lite-switch-sys1.png │ │ ├── ahb-lite-switch-sys2-eps-converted-to.pdf │ │ ├── ahb-lite-switch-sys2.eps │ │ ├── ahb-lite-switch-sys2.png │ │ ├── ahb-lite-switch-sys3-eps-converted-to.pdf │ │ ├── ahb-lite-switch-sys3.eps │ │ ├── ahb-lite-switch-sys3.png │ │ ├── ahb-lite-switch-sys4-eps-converted-to.pdf │ │ ├── ahb-lite-switch-sys4.eps │ │ ├── ahb-lite-switch-sys4.png │ │ ├── ahb-lite-switch-sys5-eps-converted-to.pdf │ │ ├── ahb-lite-switch-sys5.eps │ │ ├── ahb-lite-switch-sys5.png │ │ ├── arrow-down.png │ │ ├── octocat-small.png │ │ └── pdf.png │ └── js │ │ └── scale.fix.js ├── favicon.ico ├── markdown │ ├── compile │ ├── config │ │ ├── frontmatter.md │ │ └── latex2markdown.yaml │ └── scripts │ │ ├── create_markdown.sh │ │ └── lpp.pl ├── pkg │ └── roalogicdatasheet.sty ├── readme.md └── tex │ ├── configuration.tex │ ├── history.tex │ ├── interfaces.tex │ ├── introduction.tex │ ├── preamble.tex │ ├── references.tex │ ├── resources.tex │ ├── setup.tex │ └── specification.tex ├── rtl ├── filelist.f └── verilog │ ├── LICENSE.txt │ ├── ahb3lite_interconnect.sv │ ├── ahb3lite_interconnect_master_port.sv │ ├── ahb3lite_interconnect_slave_port.sv │ └── ahb3lite_interconnect_slave_priority.sv └── sim └── rtlsim ├── bin ├── Makefile ├── Makefile.include └── sims │ ├── Makefile.bps │ ├── Makefile.msim │ ├── Makefile.ncsim │ ├── Makefile.riviera │ ├── Makefile.vcs │ ├── bluepearl.runme.tcl │ └── roalogic.settings.tcl └── run ├── Makefile └── Makefile.include /.gitignore: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/RoaLogic/ahb3lite_interconnect/HEAD/.gitignore -------------------------------------------------------------------------------- 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