├── CNN-FPGA-Vivado ├── CNN-FPGA-Vivado.srcs │ ├── sim_1 │ │ └── new │ │ │ └── lenet_TB.v │ └── sources_1 │ │ ├── imports │ │ └── Integration first part │ │ │ ├── ANNfull.v │ │ │ ├── IntegrationConvPart.v │ │ │ ├── RFselector.v │ │ │ ├── activationFunction.v │ │ │ ├── convLayerMulti.v │ │ │ ├── convLayerSingle.v │ │ │ ├── convUnit.v │ │ │ ├── floatAdd.v │ │ │ ├── floatAdd16.v │ │ │ ├── floatMult.v │ │ │ ├── floatMult16.v │ │ │ ├── layer.v │ │ │ ├── processingElement.v │ │ │ ├── processingElement16.v │ │ │ ├── softmax_tb.v │ │ │ └── weightMemory.v │ │ └── new │ │ ├── FindMax.v │ │ ├── IEEE162IEEE32.v │ │ ├── Lenet.v │ │ ├── MaxPoolMulti.v │ │ ├── MaxPoolSingle.v │ │ ├── UsingTheRelu.v │ │ ├── UsingTheRelu16.v │ │ └── max.v ├── CNN-FPGA-Vivado.xpr └── README.md ├── LICENSE ├── README.md ├── cifar-10-torch ├── README.md ├── cifar-source │ ├── distill.py │ ├── lenet5_parameters_cifar.txt │ ├── models.py │ ├── res │ │ └── distilled_lenet5_best.pt │ ├── save_params.py │ ├── test.py │ └── train.py └── figures │ └── code.png ├── quantification ├── distilled_lenet5_best.pt ├── input_pic2_lable8.txt ├── quantification_img.py └── quantification_para.py ├── weight ├── classifier.txt ├── fc1.txt ├── fc2.txt ├── layer1.txt └── layer2.txt └── 技术报告.pdf /CNN-FPGA-Vivado/CNN-FPGA-Vivado.srcs/sim_1/new/lenet_TB.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Robin-WZQ/CNN-FPGA/HEAD/CNN-FPGA-Vivado/CNN-FPGA-Vivado.srcs/sim_1/new/lenet_TB.v -------------------------------------------------------------------------------- /CNN-FPGA-Vivado/CNN-FPGA-Vivado.srcs/sources_1/imports/Integration first part/ANNfull.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Robin-WZQ/CNN-FPGA/HEAD/CNN-FPGA-Vivado/CNN-FPGA-Vivado.srcs/sources_1/imports/Integration first part/ANNfull.v -------------------------------------------------------------------------------- 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