├── .gitignore ├── ADC_LTC2308_FIFO ├── adc_data_fifo.qip ├── adc_data_fifo.v ├── adc_data_fifo_bb.v ├── adc_ltc2308.v ├── adc_ltc2308_fifo.v ├── adc_ltc2308_hw.tcl └── greybox_tmp │ └── cbx_args.txt ├── altsource_probe ├── hps_reset.qip ├── hps_reset.v └── hps_reset_bb.v ├── debounce └── debounce.v ├── edge_detect └── altera_edge_detector.v ├── filters ├── LowpassFilterDesign.m ├── lowpass_filter.v └── lowpass_filter_tb.v ├── intr_capturer ├── intr_capturer.v └── intr_capturer_hw.tcl ├── roboy_fpga_code ├── a133x │ ├── A1339.sv │ └── A1339Control.sv ├── ball_joint │ ├── BallJoint_hw.tcl │ └── ball_joint.sv ├── controller │ ├── PID_controller.sv │ └── PID_controller_tb.v ├── fpu │ ├── branches │ │ └── russelmann │ │ │ ├── FPU.pdf │ │ │ ├── README │ │ │ ├── fcmp │ │ │ ├── test_bench │ │ │ │ └── test_top.v │ │ │ └── verilog │ │ │ │ └── fcmp.v │ │ │ ├── test_bench │ │ │ ├── sel_test.vh │ │ │ └── test_top.v │ │ │ ├── test_vectors │ │ │ ├── README │ │ │ ├── mkall.bat │ │ │ ├── mkall_fcmp.bat │ │ │ ├── pg-src │ │ │ │ ├── README │ │ │ │ └── fptpg.c │ │ │ └── pg.exe │ │ │ └── verilog │ │ │ ├── except.v │ │ │ ├── fpu.v │ │ │ ├── post_norm.v │ │ │ ├── pre_norm.v │ │ │ ├── pre_norm_fmul.v │ │ │ └── primitives.v │ ├── tags │ │ ├── INITIALRELEASE │ │ │ ├── FPU.pdf │ │ │ ├── README │ │ │ ├── test_bench │ │ │ │ ├── sel_test.vh │ │ │ │ └── test_top.v │ │ │ ├── test_vectors │ │ │ │ ├── README │ │ │ │ ├── mkall.bat │ │ │ │ ├── pg-src │ │ │ │ │ ├── README │ │ │ │ │ └── fptpg.c │ │ │ │ └── pg.exe │ │ │ └── verilog │ │ │ │ ├── except.v │ │ │ │ ├── fpu.v │ │ │ │ ├── post_norm.v │ │ │ │ ├── pre_norm.v │ │ │ │ ├── pre_norm_fmul.v │ │ │ │ └── primitives.v │ │ ├── released │ │ │ ├── FPU.pdf │ │ │ ├── README │ │ │ ├── test_bench │ │ │ │ ├── sel_test.vh │ │ │ │ └── test_top.v │ │ │ ├── test_vectors │ │ │ │ ├── README │ │ │ │ ├── mkall.bat │ │ │ │ ├── pg-src │ │ │ │ │ ├── README │ │ │ │ │ └── fptpg.c │ │ │ │ └── pg.exe │ │ │ └── verilog │ │ │ │ ├── except.v │ │ │ │ ├── fpu.v │ │ │ │ ├── post_norm.v │ │ │ │ ├── pre_norm.v │ │ │ │ ├── pre_norm_fmul.v │ │ │ │ └── primitives.v │ │ └── third_release │ │ │ ├── FPU.pdf │ │ │ ├── README │ │ │ ├── fcmp │ │ │ ├── test_bench │ │ │ │ └── test_top.v │ │ │ └── verilog │ │ │ │ └── fcmp.v │ │ │ ├── test_bench │ │ │ ├── sel_test.vh │ │ │ └── test_top.v │ │ │ ├── test_vectors │ │ │ ├── README │ │ │ ├── mkall.bat │ │ │ ├── mkall_fcmp.bat │ │ │ ├── pg-src │ │ │ │ ├── README │ │ │ │ └── fptpg.c │ │ │ └── pg.exe │ │ │ └── verilog │ │ │ ├── except.v │ │ │ ├── fpu.v │ │ │ ├── post_norm.v │ │ │ ├── pre_norm.v │ │ │ ├── pre_norm_fmul.v │ │ │ └── primitives.v │ ├── trunk │ │ ├── FPU.pdf │ │ ├── README │ │ ├── fcmp │ │ │ ├── test_bench │ │ │ │ └── test_top.v │ │ │ └── verilog │ │ │ │ └── fcmp.v │ │ ├── test_bench │ │ │ ├── sel_test.vh │ │ │ └── test_top.v │ │ ├── test_vectors │ │ │ ├── README │ │ │ ├── mkall.bat │ │ │ ├── mkall_fcmp.bat │ │ │ ├── pg-src │ │ │ │ ├── README │ │ │ │ └── fptpg.c │ │ │ └── pg.exe │ │ └── verilog │ │ │ ├── except.v │ │ │ ├── fpu.v │ │ │ ├── post_norm.v │ │ │ ├── pre_norm.v │ │ │ ├── pre_norm_fmul.v │ │ │ └── primitives.v │ └── web_uploads │ │ └── index.shtml ├── i2c │ ├── I2C_avalon_bridge.v │ ├── I2C_hw.tcl │ ├── fifo.qip │ ├── fifo.v │ ├── fifo_bb.v │ ├── i2c_controller.v │ ├── i2c_master.vhd │ └── oneshot.v ├── icebus │ ├── ArmBusComs.sv │ ├── crc16.sv │ ├── iCEboardComs.sv │ ├── iCEbusControl.sv │ └── iCEbusControl_hw.tcl ├── interfaces │ └── A1339Interface.sv ├── lighthouse_tracking │ ├── DarkRoom.v │ ├── DarkRoomOOTXdecoder.v │ ├── DarkRoomOOTXdecoder_hw.tcl │ ├── DarkRoom_hw.tcl │ ├── SpiControl_esp8266.v │ ├── lighthouse_ootx_decoder.vhdl │ ├── lighthouse_sensor.vhd │ ├── ts4231.v │ └── uart_tx.v ├── mems │ ├── MEMS_THAT_SHIT.v │ ├── clk_div.v │ ├── filter.v │ ├── filter_tb.v │ ├── iir.v │ └── serv_req_info.txt ├── msj_platform │ ├── MSJPlatformControl.sv │ └── MSJPlatformPIDController.sv ├── myo_control │ ├── A1335Control.v │ ├── ArmControl.v │ ├── FpuTest.v │ ├── MYOControl.sv │ ├── MYOControl_hw.tcl │ ├── PIDController.v │ ├── SpiControl.v │ └── spi_master_slave │ │ └── trunk │ │ ├── doc │ │ ├── UNDER_CONSTRUCTION.txt │ │ └── src │ │ │ ├── SPI_MODES.jpg │ │ │ └── spi_master_slave_Specifications.doc │ │ ├── license │ │ └── lgpl.txt │ │ ├── rtl │ │ └── spi_master_slave │ │ │ ├── grp_debouncer.vhd │ │ │ ├── readme.txt │ │ │ ├── spi_loopback.ucf │ │ │ ├── spi_loopback.vhd │ │ │ ├── spi_loopback_test.vhd │ │ │ ├── spi_master.vhd │ │ │ └── spi_slave.vhd │ │ └── syn │ │ ├── ATLYS_01.SET │ │ ├── ATLYS_02.SET │ │ ├── ATLYS_03.SET │ │ ├── ATLYS_04.SET │ │ ├── ATLYS_05.SET │ │ ├── fuse.xmsgs │ │ ├── fuseRelaunch.cmd │ │ ├── grp_debouncer.vhd │ │ ├── par_usage_statistics.html │ │ ├── readme.txt │ │ ├── sim_master_slave_ct.pdf │ │ ├── spi_master.vhd │ │ ├── spi_master_atlys.ucf │ │ ├── spi_master_atlys_test.vhd │ │ ├── spi_master_atlys_top.drc │ │ ├── spi_master_atlys_top.par │ │ ├── spi_master_atlys_top.pcf │ │ ├── spi_master_atlys_top.syr │ │ ├── spi_master_atlys_top.twr │ │ ├── spi_master_atlys_top.vhd │ │ ├── spi_master_atlys_top.xst │ │ ├── spi_master_atlys_top_bit.zip │ │ ├── spi_master_atlys_top_bitgen.xwbt │ │ ├── spi_master_atlys_top_envsettings.html │ │ ├── spi_master_atlys_top_guide.ncd │ │ ├── spi_master_atlys_top_map.map │ │ ├── spi_master_atlys_top_map.mrp │ │ ├── spi_master_atlys_top_map.psr │ │ ├── spi_master_atlys_top_summary.html │ │ ├── spi_master_envsettings.html │ │ ├── spi_master_scope_photos.zip │ │ ├── spi_master_summary.html │ │ ├── spi_ms_atlys.gise │ │ ├── spi_ms_atlys.xise │ │ ├── spi_slave.vhd │ │ ├── spi_test_ct.wcfg │ │ └── usage_statistics_webtalk.html ├── neopixel │ ├── Counter.v │ ├── neopixel.v │ ├── neopixel_fifo.qip │ ├── neopixel_fifo.v │ ├── neopixel_fifo_bb.v │ └── neopixel_hw.tcl ├── pwm_control │ ├── FanControl_hw.tcl │ ├── fan_control.sv │ ├── pwm.vhd │ ├── pwm_avalon_bridge.v │ └── pwm_hw.tcl ├── quadrature │ ├── myoQuad.v │ └── quad.v ├── sigma_delta_dac_dual_loop │ └── trunk │ │ ├── README │ │ ├── dsm2 │ │ ├── dac_dsm2.vhd │ │ ├── dac_dsm2_top.vhd │ │ ├── dac_dsm2v.vhd │ │ ├── dac_tb.vhd │ │ ├── makefile │ │ ├── show_dac.py │ │ └── work-obj93.cf │ │ └── dsm3 │ │ ├── dac_dsm3.vhd │ │ ├── dac_dsm3_top.vhd │ │ ├── dac_dsm3v.vhd │ │ ├── dac_tb.vhd │ │ ├── makefile │ │ └── show_dac.py ├── tli4970 │ ├── TLI4970_hw.tcl │ ├── tli4970.sv │ └── tli4970.v ├── tlv493 │ ├── TLV493.sv │ └── TLV493_hw.tcl ├── uart │ ├── uart_rx.v │ └── uart_tx.v └── xl320 │ ├── XL320.sv │ ├── XL320_hw.tcl │ └── XL320_tb.v └── subsystemA.qsys.bk /.gitignore: -------------------------------------------------------------------------------- 1 | *.bak 2 | *~ 3 | .qsys_edit 4 | -------------------------------------------------------------------------------- /ADC_LTC2308_FIFO/adc_data_fifo.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "FIFO" 2 | set_global_assignment -name IP_TOOL_VERSION "13.0" 3 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "adc_data_fifo.v"] 4 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "adc_data_fifo_bb.v"] 5 | -------------------------------------------------------------------------------- /ADC_LTC2308_FIFO/greybox_tmp/cbx_args.txt: -------------------------------------------------------------------------------- 1 | INTENDED_DEVICE_FAMILY="Cyclone V" 2 | LPM_NUMWORDS=2048 3 | LPM_SHOWAHEAD=ON 4 | LPM_TYPE=dcfifo 5 | LPM_WIDTH=12 6 | LPM_WIDTHU=11 7 | OVERFLOW_CHECKING=ON 8 | RDSYNC_DELAYPIPE=4 9 | READ_ACLR_SYNCH=OFF 10 | UNDERFLOW_CHECKING=ON 11 | USE_EAB=ON 12 | WRITE_ACLR_SYNCH=OFF 13 | WRSYNC_DELAYPIPE=4 14 | DEVICE_FAMILY="Cyclone V" 15 | aclr 16 | data 17 | rdclk 18 | rdreq 19 | wrclk 20 | wrreq 21 | q 22 | rdempty 23 | wrfull 24 | -------------------------------------------------------------------------------- /altsource_probe/hps_reset.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "In-System Sources and Probes" 2 | set_global_assignment -name IP_TOOL_VERSION "17.0" 3 | set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}" 4 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "hps_reset.v"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "hps_reset_bb.v"] 6 | -------------------------------------------------------------------------------- /altsource_probe/hps_reset.v: -------------------------------------------------------------------------------- 1 | // megafunction wizard: %In-System Sources and Probes% 2 | // GENERATION: STANDARD 3 | // VERSION: WM1.0 4 | // MODULE: altsource_probe 5 | 6 | // ============================================================ 7 | // File Name: hps_reset.v 8 | // Megafunction Name(s): 9 | // altsource_probe 10 | // 11 | // Simulation Library Files(s): 12 | // 13 | // ============================================================ 14 | // ************************************************************ 15 | // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! 16 | // 17 | // 17.0.0 Build 595 04/25/2017 SJ Lite Edition 18 | // ************************************************************ 19 | 20 | 21 | //Copyright (C) 2017 Intel Corporation. All rights reserved. 22 | //Your use of Intel Corporation's design tools, logic functions 23 | //and other software and tools, and its AMPP partner logic 24 | //functions, and any output files from any of the foregoing 25 | //(including device programming or simulation files), and any 26 | //associated documentation or information are expressly subject 27 | //to the terms and conditions of the Intel Program License 28 | //Subscription Agreement, the Intel Quartus Prime License Agreement, 29 | //the Intel MegaCore Function License Agreement, or other 30 | //applicable license agreement, including, without limitation, 31 | //that your use is for the sole purpose of programming logic 32 | //devices manufactured by Intel and sold by Intel or its 33 | //authorized distributors. Please refer to the applicable 34 | //agreement for further details. 35 | 36 | 37 | // synopsys translate_off 38 | `timescale 1 ps / 1 ps 39 | // synopsys translate_on 40 | module hps_reset ( 41 | probe, 42 | source_clk, 43 | source); 44 | 45 | input probe; 46 | input source_clk; 47 | output [2:0] source; 48 | 49 | wire [2:0] sub_wire0; 50 | wire [2:0] source = sub_wire0[2:0]; 51 | 52 | altsource_probe altsource_probe_component ( 53 | .probe (probe), 54 | .source_clk (source_clk), 55 | .source (sub_wire0) 56 | // synopsys translate_off 57 | , 58 | .clr (), 59 | .ena (), 60 | .ir_in (), 61 | .ir_out (), 62 | .jtag_state_cdr (), 63 | .jtag_state_cir (), 64 | .jtag_state_e1dr (), 65 | .jtag_state_sdr (), 66 | .jtag_state_tlr (), 67 | .jtag_state_udr (), 68 | .jtag_state_uir (), 69 | .raw_tck (), 70 | .source_ena (), 71 | .tdi (), 72 | .tdo (), 73 | .usr1 () 74 | // synopsys translate_on 75 | ); 76 | defparam 77 | altsource_probe_component.enable_metastability = "YES", 78 | altsource_probe_component.instance_id = "RST", 79 | altsource_probe_component.probe_width = 0, 80 | altsource_probe_component.sld_auto_instance_index = "YES", 81 | altsource_probe_component.sld_instance_index = 0, 82 | altsource_probe_component.source_initial_value = " 0", 83 | altsource_probe_component.source_width = 3; 84 | 85 | 86 | endmodule 87 | 88 | // ============================================================ 89 | // CNX file retrieval info 90 | // ============================================================ 91 | // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V" 92 | // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all 93 | // Retrieval info: CONSTANT: ENABLE_METASTABILITY STRING "YES" 94 | // Retrieval info: CONSTANT: INSTANCE_ID STRING "RST" 95 | // Retrieval info: CONSTANT: PROBE_WIDTH NUMERIC "0" 96 | // Retrieval info: CONSTANT: SLD_AUTO_INSTANCE_INDEX STRING "YES" 97 | // Retrieval info: CONSTANT: SLD_INSTANCE_INDEX NUMERIC "0" 98 | // Retrieval info: CONSTANT: SOURCE_INITIAL_VALUE STRING " 0" 99 | // Retrieval info: CONSTANT: SOURCE_WIDTH NUMERIC "3" 100 | // Retrieval info: USED_PORT: probe 0 0 0 0 INPUT NODEFVAL "probe" 101 | // Retrieval info: USED_PORT: source 0 0 3 0 OUTPUT NODEFVAL "source[2..0]" 102 | // Retrieval info: USED_PORT: source_clk 0 0 0 0 INPUT NODEFVAL "source_clk" 103 | // Retrieval info: CONNECT: @probe 0 0 0 0 probe 0 0 0 0 104 | // Retrieval info: CONNECT: @source_clk 0 0 0 0 source_clk 0 0 0 0 105 | // Retrieval info: CONNECT: source 0 0 3 0 @source 0 0 3 0 106 | // Retrieval info: GEN_FILE: TYPE_NORMAL hps_reset.v TRUE 107 | // Retrieval info: GEN_FILE: TYPE_NORMAL hps_reset.inc FALSE 108 | // Retrieval info: GEN_FILE: TYPE_NORMAL hps_reset.cmp FALSE 109 | // Retrieval info: GEN_FILE: TYPE_NORMAL hps_reset.bsf FALSE 110 | // Retrieval info: GEN_FILE: TYPE_NORMAL hps_reset_inst.v FALSE 111 | // Retrieval info: GEN_FILE: TYPE_NORMAL hps_reset_bb.v TRUE 112 | -------------------------------------------------------------------------------- /altsource_probe/hps_reset_bb.v: -------------------------------------------------------------------------------- 1 | // megafunction wizard: %In-System Sources and Probes%VBB% 2 | // GENERATION: STANDARD 3 | // VERSION: WM1.0 4 | // MODULE: altsource_probe 5 | 6 | // ============================================================ 7 | // File Name: hps_reset.v 8 | // Megafunction Name(s): 9 | // altsource_probe 10 | // 11 | // Simulation Library Files(s): 12 | // 13 | // ============================================================ 14 | // ************************************************************ 15 | // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! 16 | // 17 | // 17.0.0 Build 595 04/25/2017 SJ Lite Edition 18 | // ************************************************************ 19 | 20 | //Copyright (C) 2017 Intel Corporation. All rights reserved. 21 | //Your use of Intel Corporation's design tools, logic functions 22 | //and other software and tools, and its AMPP partner logic 23 | //functions, and any output files from any of the foregoing 24 | //(including device programming or simulation files), and any 25 | //associated documentation or information are expressly subject 26 | //to the terms and conditions of the Intel Program License 27 | //Subscription Agreement, the Intel Quartus Prime License Agreement, 28 | //the Intel MegaCore Function License Agreement, or other 29 | //applicable license agreement, including, without limitation, 30 | //that your use is for the sole purpose of programming logic 31 | //devices manufactured by Intel and sold by Intel or its 32 | //authorized distributors. Please refer to the applicable 33 | //agreement for further details. 34 | 35 | module hps_reset ( 36 | probe, 37 | source_clk, 38 | source); 39 | 40 | input probe; 41 | input source_clk; 42 | output [2:0] source; 43 | 44 | endmodule 45 | 46 | // ============================================================ 47 | // CNX file retrieval info 48 | // ============================================================ 49 | // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V" 50 | // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all 51 | // Retrieval info: CONSTANT: ENABLE_METASTABILITY STRING "YES" 52 | // Retrieval info: CONSTANT: INSTANCE_ID STRING "RST" 53 | // Retrieval info: CONSTANT: PROBE_WIDTH NUMERIC "0" 54 | // Retrieval info: CONSTANT: SLD_AUTO_INSTANCE_INDEX STRING "YES" 55 | // Retrieval info: CONSTANT: SLD_INSTANCE_INDEX NUMERIC "0" 56 | // Retrieval info: CONSTANT: SOURCE_INITIAL_VALUE STRING " 0" 57 | // Retrieval info: CONSTANT: SOURCE_WIDTH NUMERIC "3" 58 | // Retrieval info: USED_PORT: probe 0 0 0 0 INPUT NODEFVAL "probe" 59 | // Retrieval info: USED_PORT: source 0 0 3 0 OUTPUT NODEFVAL "source[2..0]" 60 | // Retrieval info: USED_PORT: source_clk 0 0 0 0 INPUT NODEFVAL "source_clk" 61 | // Retrieval info: CONNECT: @probe 0 0 0 0 probe 0 0 0 0 62 | // Retrieval info: CONNECT: @source_clk 0 0 0 0 source_clk 0 0 0 0 63 | // Retrieval info: CONNECT: source 0 0 3 0 @source 0 0 3 0 64 | // Retrieval info: GEN_FILE: TYPE_NORMAL hps_reset.v TRUE 65 | // Retrieval info: GEN_FILE: TYPE_NORMAL hps_reset.inc FALSE 66 | // Retrieval info: GEN_FILE: TYPE_NORMAL hps_reset.cmp FALSE 67 | // Retrieval info: GEN_FILE: TYPE_NORMAL hps_reset.bsf FALSE 68 | // Retrieval info: GEN_FILE: TYPE_NORMAL hps_reset_inst.v FALSE 69 | // Retrieval info: GEN_FILE: TYPE_NORMAL hps_reset_bb.v TRUE 70 | -------------------------------------------------------------------------------- /debounce/debounce.v: -------------------------------------------------------------------------------- 1 | //Legal Notice: (C)2013 Altera Corporation. All rights reserved. Your 2 | //use of Altera Corporation's design tools, logic functions and other 3 | //software and tools, and its AMPP partner logic functions, and any 4 | //output files any of the foregoing (including device programming or 5 | //simulation files), and any associated documentation or information are 6 | //expressly subject to the terms and conditions of the Altera Program 7 | //License Subscription Agreement or other applicable license agreement, 8 | //including, without limitation, that your use is for the sole purpose 9 | //of programming logic devices manufactured by Altera and sold by Altera 10 | //or its authorized distributors. Please refer to the applicable 11 | //agreement for further details. 12 | 13 | module debounce ( 14 | clk, 15 | reset_n, 16 | data_in, 17 | data_out 18 | ); 19 | 20 | parameter WIDTH = 32; // set to be the width of the bus being debounced 21 | parameter POLARITY = "HIGH"; // set to be "HIGH" for active high debounce or "LOW" for active low debounce 22 | parameter TIMEOUT = 50000; // number of input clock cycles the input signal needs to be in the active state 23 | parameter TIMEOUT_WIDTH = 16; // set to be ceil(log2(TIMEOUT)) 24 | 25 | input wire clk; 26 | input wire reset_n; 27 | 28 | input wire [WIDTH-1:0] data_in; 29 | output wire [WIDTH-1:0] data_out; 30 | 31 | reg [TIMEOUT_WIDTH-1:0] counter [0:WIDTH-1]; 32 | wire counter_reset [0:WIDTH-1]; 33 | wire counter_enable [0:WIDTH-1]; 34 | 35 | // need one counter per input to debounce 36 | genvar i; 37 | generate for (i = 0; i < WIDTH; i = i+1) 38 | begin: debounce_counter_loop 39 | always @ (posedge clk or negedge reset_n) 40 | begin 41 | if (reset_n == 0) 42 | begin 43 | counter[i] <= 0; 44 | end 45 | else 46 | begin 47 | if (counter_reset[i] == 1) // resetting the counter needs to win 48 | begin 49 | counter[i] <= 0; 50 | end 51 | else if (counter_enable[i] == 1) 52 | begin 53 | counter[i] <= counter[i] + 1'b1; 54 | end 55 | end 56 | end 57 | 58 | if (POLARITY == "HIGH") 59 | begin 60 | assign counter_reset[i] = (data_in[i] == 0); 61 | assign counter_enable[i] = (data_in[i] == 1) & (counter[i] < TIMEOUT); 62 | assign data_out[i] = (counter[i] == TIMEOUT) ? 1'b1 : 1'b0; 63 | end 64 | else 65 | begin 66 | assign counter_reset[i] = (data_in[i] == 1); 67 | assign counter_enable[i] = (data_in[i] == 0) & (counter[i] < TIMEOUT); 68 | assign data_out[i] = (counter[i] == TIMEOUT) ? 1'b0 : 1'b1; 69 | end 70 | 71 | end 72 | endgenerate 73 | 74 | endmodule 75 | -------------------------------------------------------------------------------- /edge_detect/altera_edge_detector.v: -------------------------------------------------------------------------------- 1 | module altera_edge_detector #( 2 | parameter PULSE_EXT = 0, // 0, 1 = edge detection generate single cycle pulse, >1 = pulse extended for specified clock cycle 3 | parameter EDGE_TYPE = 0, // 0 = falling edge, 1 or else = rising edge 4 | parameter IGNORE_RST_WHILE_BUSY = 0 // 0 = module internal reset will be default whenever rst_n asserted, 1 = rst_n request will be ignored while generating pulse out 5 | ) ( 6 | input clk, 7 | input rst_n, 8 | input signal_in, 9 | output pulse_out 10 | ); 11 | 12 | localparam IDLE = 0, ARM = 1, CAPT = 2; 13 | localparam SIGNAL_ASSERT = EDGE_TYPE ? 1'b1 : 1'b0; 14 | localparam SIGNAL_DEASSERT = EDGE_TYPE ? 1'b0 : 1'b1; 15 | 16 | reg [1:0] state, next_state; 17 | reg pulse_detect; 18 | wire busy_pulsing; 19 | 20 | assign busy_pulsing = (IGNORE_RST_WHILE_BUSY)? pulse_out : 1'b0; 21 | assign reset_qual_n = rst_n | busy_pulsing; 22 | 23 | generate 24 | if (PULSE_EXT > 1) begin: pulse_extend 25 | integer i; 26 | reg [PULSE_EXT-1:0] extend_pulse; 27 | always @(posedge clk or negedge reset_qual_n) begin 28 | if (!reset_qual_n) 29 | extend_pulse <= {{PULSE_EXT}{1'b0}}; 30 | else begin 31 | for (i = 1; i < PULSE_EXT; i = i+1) begin 32 | extend_pulse[i] <= extend_pulse[i-1]; 33 | end 34 | extend_pulse[0] <= pulse_detect; 35 | end 36 | end 37 | assign pulse_out = |extend_pulse; 38 | end 39 | else begin: single_pulse 40 | reg pulse_reg; 41 | always @(posedge clk or negedge reset_qual_n) begin 42 | if (!reset_qual_n) 43 | pulse_reg <= 1'b0; 44 | else 45 | pulse_reg <= pulse_detect; 46 | end 47 | assign pulse_out = pulse_reg; 48 | end 49 | endgenerate 50 | 51 | always @(posedge clk) begin 52 | if (!rst_n) 53 | state <= IDLE; 54 | else 55 | state <= next_state; 56 | end 57 | 58 | // edge detect 59 | always @(*) begin 60 | next_state = state; 61 | pulse_detect = 1'b0; 62 | case (state) 63 | IDLE : begin 64 | pulse_detect = 1'b0; 65 | if (signal_in == SIGNAL_DEASSERT) next_state = ARM; 66 | else next_state = IDLE; 67 | end 68 | ARM : begin 69 | pulse_detect = 1'b0; 70 | if (signal_in == SIGNAL_ASSERT) next_state = CAPT; 71 | else next_state = ARM; 72 | end 73 | CAPT : begin 74 | pulse_detect = 1'b1; 75 | if (signal_in == SIGNAL_DEASSERT) next_state = ARM; 76 | else next_state = IDLE; 77 | end 78 | default : begin 79 | pulse_detect = 1'b0; 80 | next_state = IDLE; 81 | end 82 | endcase 83 | end 84 | 85 | endmodule 86 | -------------------------------------------------------------------------------- /filters/LowpassFilterDesign.m: -------------------------------------------------------------------------------- 1 | Fs = 37000; 2 | F3db = 100; 3 | filtdes = fdesign.lowpass('n,f3db', 2, F3db, Fs); 4 | butterFilter = design(filtdes,'butter',... 5 | 'SystemObject',true,'FilterStructure','df1sos'); 6 | fvtool(butterFilter, 'Fs', Fs, 'FrequencyScale', 'log'); 7 | 8 | butterFilter.NumeratorCoefficientsDataType = 'Custom'; 9 | butterFilter.CustomNumeratorCoefficientsDataType = numerictype([],16); 10 | butterFilter.CustomDenominatorCoefficientsDataType = numerictype([],16); 11 | butterFilter.CustomScaleValuesDataType = numerictype([],16); 12 | butterFilter.SectionInputDataType = 'Custom'; 13 | butterFilter.CustomSectionInputDataType = numerictype([],20,15); 14 | butterFilter.SectionOutputDataType = 'Custom'; 15 | butterFilter.CustomSectionOutputDataType = numerictype([],20,15); 16 | butterFilter.NumeratorProductDataType = 'Full precision'; 17 | butterFilter.DenominatorProductDataType = 'Full precision'; 18 | butterFilter.NumeratorAccumulatorDataType = 'Custom'; 19 | butterFilter.CustomNumeratorAccumulatorDataType = numerictype([],32,24); 20 | butterFilter.DenominatorAccumulatorDataType = 'Custom'; 21 | butterFilter.CustomDenominatorAccumulatorDataType = numerictype([],32,25); 22 | butterFilter.OutputDataType = 'Custom'; 23 | butterFilter.CustomOutputDataType = numerictype([],12,0); 24 | butterFilter.RoundingMethod = 'nearest'; 25 | butterFilter.OverflowAction = 'wrap'; 26 | 27 | fvtool(butterFilter, 'Fs', Fs, 'FrequencyScale', 'log','Arithmetic','fixed'); 28 | 29 | scale(butterFilter,'Linf'); 30 | scaless = butterFilter.ScaleValues; 31 | disp(scaless); 32 | 33 | workingdir = tempname; 34 | 35 | userstim = []; 36 | for n = [50, 100, 150, 200, 250, 300] 37 | userstim = [userstim, sin(2*pi*n/Fs*(0:Fs/n))]; %#ok 38 | end 39 | 40 | generatehdl(butterFilter, 'Name', 'hdlbutter',... 41 | 'TargetLanguage', 'Verilog',... 42 | 'TargetDirectory', workingdir, ... 43 | 'GenerateHDLTestbench', 'on', ... 44 | 'TestBenchUserStimulus', userstim, ... 45 | 'InputDataType',numerictype(1,12,0)); -------------------------------------------------------------------------------- /intr_capturer/intr_capturer.v: -------------------------------------------------------------------------------- 1 | //Legal Notice: (C)2013 Altera Corporation. All rights reserved. Your 2 | //use of Altera Corporation's design tools, logic functions and other 3 | //software and tools, and its AMPP partner logic functions, and any 4 | //output files any of the foregoing (including device programming or 5 | //simulation files), and any associated documentation or information are 6 | //expressly subject to the terms and conditions of the Altera Program 7 | //License Subscription Agreement or other applicable license agreement, 8 | //including, without limitation, that your use is for the sole purpose 9 | //of programming logic devices manufactured by Altera and sold by Altera 10 | //or its authorized distributors. Please refer to the applicable 11 | //agreement for further details. 12 | 13 | module intr_capturer #( 14 | parameter NUM_INTR = 32 15 | // active high level interrupt is expected for the input of this capturer module 16 | )( 17 | input clk, 18 | input rst_n, 19 | input [NUM_INTR-1:0] interrupt_in, 20 | //input [31:0] wrdata, 21 | input addr, 22 | input read, 23 | output [31:0] rddata 24 | ); 25 | 26 | reg [NUM_INTR-1:0] interrupt_reg; 27 | reg [31:0] readdata_with_waitstate; 28 | wire [31:0] act_readdata; 29 | wire [31:0] readdata_lower_intr; 30 | wire [31:0] readdata_higher_intr; 31 | wire access_lower_32; 32 | wire access_higher_32; 33 | 34 | always @(posedge clk or negedge rst_n) begin 35 | if (!rst_n) interrupt_reg <= 'b0; 36 | else interrupt_reg <= interrupt_in; 37 | end 38 | 39 | generate 40 | if (NUM_INTR>32) begin : two_intr_reg_needed 41 | assign access_higher_32 = read & (addr == 1); 42 | 43 | assign readdata_lower_intr = interrupt_reg[31:0] & {(32){access_lower_32}}; 44 | assign readdata_higher_intr = interrupt_reg[NUM_INTR-1:32] & {(NUM_INTR-32){access_higher_32}}; 45 | end 46 | else begin : only_1_reg 47 | assign readdata_lower_intr = interrupt_reg & {(NUM_INTR){access_lower_32}}; 48 | assign readdata_higher_intr = {32{1'b0}}; 49 | end 50 | endgenerate 51 | 52 | assign access_lower_32 = read & (addr == 0); 53 | assign act_readdata = readdata_lower_intr | readdata_higher_intr; 54 | assign rddata = readdata_with_waitstate; 55 | 56 | always @(posedge clk or negedge rst_n) begin 57 | if (!rst_n) readdata_with_waitstate <= 32'b0; 58 | else readdata_with_waitstate <= act_readdata; 59 | end 60 | 61 | endmodule 62 | -------------------------------------------------------------------------------- /roboy_fpga_code/a133x/A1339.sv: -------------------------------------------------------------------------------- 1 | module A1339( 2 | input clock, 3 | input reset_n, 4 | // this is for the avalon interface 5 | input [8:0] address, 6 | input read, 7 | output signed [31:0] readdata, 8 | output waitrequest, 9 | // SPI 10 | output sck_o, // clock 11 | output [NUMBER_OF_SENSORS-1:0] ss_n_o, // slave select line for each sensor 12 | output mosi_o, // mosi 13 | input miso_i, // miso 14 | output [2:0] LED 15 | ); 16 | 17 | parameter NUMBER_OF_SENSORS = 1; 18 | 19 | assign waitrequest = (waitFlag || state==4); // if waiting for data 20 | reg waitFlag; 21 | 22 | always @(posedge clock, negedge reset_n) begin: AVALON_READ_INTERFACE 23 | if (reset_n == 0) begin 24 | waitFlag <= 0; 25 | end else begin 26 | waitFlag <= 1; 27 | if(read) begin 28 | readdata[11:0] <= angle[address]; 29 | if(waitFlag==1) begin // after one clock cycle the sensor_data_avalon should be stable 30 | waitFlag <= 0; 31 | end 32 | end 33 | end 34 | end 35 | 36 | wire di_req, wr_ack, do_valid, wren; 37 | reg [19:0] data_send; 38 | wire [15:0] data = 16'h2000; 39 | wire [19:0] data_received; 40 | wire ss_n; 41 | 42 | wire send; 43 | reg trigger; 44 | reg data_valid; 45 | 46 | assign LED[2] = data_valid; 47 | assign LED[0] = trigger; 48 | 49 | reg [7:0] current_sensor; 50 | 51 | reg [11:0] angle [NUMBER_OF_SENSORS-1:0]; 52 | 53 | reg [2:0] state; 54 | always @(posedge clock, negedge reset_n) begin: SPI_DATA_PROCESS 55 | parameter IDLE = 0, CALCULATE_CRC = 1, TRIGGER_SEND = 2, WAIT_FOR_DATA = 4, DELAY = 5; 56 | reg CRC0; 57 | reg CRC1; 58 | reg CRC2; 59 | reg CRC3; 60 | reg DoInvert; 61 | reg [15:0] mask; 62 | reg [3:0] crc; 63 | integer j; 64 | reg send_prev; 65 | reg [31:0] delay_counter; 66 | if (reset_n==0) begin 67 | state <= IDLE; 68 | trigger <= 0; 69 | end else begin 70 | trigger <= 0; 71 | send_prev <= send; 72 | case(state) 73 | IDLE: begin 74 | state <= CALCULATE_CRC; 75 | end 76 | CALCULATE_CRC: begin 77 | CRC0 = 1'b1; 78 | CRC1 = 1'b1; 79 | CRC2 = 1'b1; 80 | CRC3 = 1'b1; 81 | mask = 16'h8000; 82 | for (j = 0; j < 16; j=j+1) begin 83 | DoInvert = ((data & mask) != 0) ^ CRC3; // XOR required? 84 | CRC3 = CRC2; 85 | CRC2 = CRC1; 86 | CRC1 = CRC0 ^ DoInvert; 87 | CRC0 = DoInvert; 88 | mask = mask >> 1; 89 | end 90 | crc = (CRC3 ? 4'd8 : 4'd0) + (CRC2 ? 4'd4 : 4'd0) + (CRC1 ? 4'd2 : 4'd0) + (CRC0 ? 4'd1 : 4'd0); 91 | data_send = {data,crc}; 92 | state = TRIGGER_SEND; 93 | current_sensor = current_sensor+1; 94 | if(current_sensor>=NUMBER_OF_SENSORS) begin 95 | current_sensor = 0; 96 | end 97 | end 98 | TRIGGER_SEND: begin 99 | trigger <= 1; 100 | state <= WAIT_FOR_DATA; 101 | end 102 | WAIT_FOR_DATA: begin 103 | if(do_valid) begin 104 | CRC0 = 1'b1; 105 | CRC1 = 1'b1; 106 | CRC2 = 1'b1; 107 | CRC3 = 1'b1; 108 | mask = 16'h8000; 109 | for (j = 0; j < 16; j=j+1) begin 110 | DoInvert = (((data_received>>4) & mask) != 0) ^ CRC3; // XOR required? 111 | 112 | CRC3 = CRC2; 113 | CRC2 = CRC1; 114 | CRC1 = CRC0 ^ DoInvert; 115 | CRC0 = DoInvert; 116 | mask = mask >> 1; 117 | end 118 | crc = (CRC3 ? 4'd8 : 4'd0) + (CRC2 ? 4'd4 : 4'd0) + (CRC1 ? 4'd2 : 4'd0) + (CRC0 ? 4'd1 : 4'd0); 119 | if(crc == data_received[3:0]) begin 120 | data_valid = 1; 121 | angle[current_sensor] = (data_received>>4); 122 | end else begin 123 | data_valid = 0; 124 | end 125 | 126 | state = DELAY; 127 | delay_counter <= 500; 128 | end 129 | end 130 | DELAY: begin 131 | delay_counter <= delay_counter -1; 132 | if(delay_counter==0) begin 133 | state <= IDLE; 134 | end 135 | end 136 | default: state = IDLE; 137 | endcase 138 | end 139 | end 140 | 141 | genvar k; 142 | generate 143 | for(k=0; k> 1; 70 | end 71 | crc = (CRC3 ? 4'd8 : 4'd0) + (CRC2 ? 4'd4 : 4'd0) + (CRC1 ? 4'd2 : 4'd0) + (CRC0 ? 4'd1 : 4'd0); 72 | data_send = {data,crc}; 73 | state = TRIGGER_SEND; 74 | current_sensor = current_sensor+1; 75 | if(current_sensor>=NUMBER_OF_SENSORS) begin 76 | current_sensor = 0; 77 | end 78 | end 79 | TRIGGER_SEND: begin 80 | trigger <= 1; 81 | state <= WAIT_FOR_DATA; 82 | end 83 | WAIT_FOR_DATA: begin 84 | if(do_valid) begin 85 | CRC0 = 1'b1; 86 | CRC1 = 1'b1; 87 | CRC2 = 1'b1; 88 | CRC3 = 1'b1; 89 | mask = 16'h8000; 90 | for (j = 0; j < 16; j=j+1) begin 91 | DoInvert = (((data_received>>4) & mask) != 0) ^ CRC3; // XOR required? 92 | 93 | CRC3 = CRC2; 94 | CRC2 = CRC1; 95 | CRC1 = CRC0 ^ DoInvert; 96 | CRC0 = DoInvert; 97 | mask = mask >> 1; 98 | end 99 | crc = (CRC3 ? 4'd8 : 4'd0) + (CRC2 ? 4'd4 : 4'd0) + (CRC1 ? 4'd2 : 4'd0) + (CRC0 ? 4'd1 : 4'd0); 100 | if(crc == data_received[3:0]) begin 101 | data_valid = 1; 102 | angle[current_sensor] = (data_received>>4); 103 | end else begin 104 | data_valid = 0; 105 | end 106 | 107 | if(NUMBER_OF_SENSORS==1) begin 108 | state = DELAY; 109 | delay_counter <= 50000; 110 | end else begin 111 | state = DELAY; 112 | delay_counter <= 5000; 113 | end 114 | 115 | end 116 | end 117 | DELAY: begin 118 | delay_counter <= delay_counter -1; 119 | if(delay_counter==0) begin 120 | state <= IDLE; 121 | end 122 | end 123 | default: state = IDLE; 124 | endcase 125 | end 126 | end 127 | 128 | genvar k; 129 | generate 130 | for(k=0; k> 31); 39 | y_1 <= y; 40 | y_2 <= y_1; 41 | x_2 <= x_1; 42 | x_1 <= x; 43 | x_1_out <= x; 44 | x_2_out <= x_1; 45 | y_1_out <= y; 46 | y_2_out <= y_1; 47 | end 48 | end 49 | endmodule 50 | 51 | 52 | module filter_testbench; 53 | 54 | reg pdm_clk, reset; 55 | reg [63:0] raw_pdm_data; 56 | reg [63:0] filt_pdm_data_1; 57 | 58 | 59 | filter #( 60 | .b0(24'd311), 61 | .b1(24'd623), 62 | .b2(24'd311), 63 | .a0(24'd4203641), 64 | .a1(24'd8388608), 65 | .a2(24'd4186212) 66 | ) layer_1 ( 67 | .clk(pdm_clk), 68 | .reset(reset), 69 | .x(raw_pdm_data), 70 | .y(filt_pdm_data_1) 71 | ); 72 | 73 | 74 | initial begin 75 | pdm_clk = 0; 76 | reset = 0; 77 | raw_pdm_data = 0; 78 | end 79 | 80 | always 81 | #5 pdm_clk = ! pdm_clk; 82 | 83 | 84 | endmodule 85 | -------------------------------------------------------------------------------- /roboy_fpga_code/mems/filter_tb.v: -------------------------------------------------------------------------------- 1 | module filter_tb; 2 | 3 | reg pdm_clk, reset; 4 | reg [63:0] raw_pdm_data; 5 | reg [63:0] filt_pdm_data_1; 6 | 7 | 8 | filter #( 9 | .b0(24'd311), 10 | .b1(24'd623), 11 | .b2(24'd311), 12 | .a0(24'd4203641), 13 | .a1(24'd8388608), 14 | .a2(24'd4186212) 15 | ) layer_1 ( 16 | .clk(pdm_clk), 17 | .reset(reset), 18 | .x(raw_pdm_data), 19 | .y(filt_pdm_data_1) 20 | ); 21 | 22 | 23 | initial begin 24 | pdm_clk = 0; 25 | reset = 0; 26 | end 27 | 28 | always 29 | #5 pdm_clk = ! pdm_clk; 30 | 31 | 32 | endmodule -------------------------------------------------------------------------------- /roboy_fpga_code/mems/iir.v: -------------------------------------------------------------------------------- 1 | // Discrete-Time IIR Filter (lowpass - real) 2 | // ------------------------------- 3 | // 4 | // Developer: Ânderson I. Silva 5 | // Repository: https://github.com/aignacio/iir_filter 6 | // 7 | // Parameters: 8 | // 9 | // Fs : 48000 Samples/s 10 | // Fc : 1000 Hz 11 | // Fs : 1500 Hz 12 | // Apass: 1dB 13 | // Astop: -15dB 14 | // Filter Structure : Direct-Form I, Second-Order Sections 15 | // Architecture: Cascade 16 | // Number of Sections : 3 17 | // Stable : Yes 18 | // Linear Phase : No 19 | // Arithmetic : fixed 20 | // 21 | // Design Method Information 22 | // Design Algorithm : butter 23 | // 24 | // Design Options 25 | // Match Exactly : stopband 26 | // Scale Norm : no scaling 27 | // SystemObject : false 28 | // 29 | // Design Specifications 30 | // Sample Rate : N/A (normalized frequency) 31 | // Response : Lowpass 32 | // Specification : Fp,Fst,Ap,Ast 33 | // Stopband Atten. : 15 dB 34 | // Passband Ripple : 1 dB 35 | // Stopband Edge : 0.0625 36 | // Passband Edge : 0.041667 37 | // 38 | // Measurements 39 | // Sample Rate : N/A (normalized frequency) 40 | // Passband Edge : 0.041667 41 | // 3-dB Point : 0.047064 42 | // 6-dB Point : 0.051568 43 | // Stopband Edge : 0.0625 44 | // Passband Ripple : 0.89022 dB 45 | // Stopband Atten. : 14.9855 dB 46 | // Transition Width : 0.020833 47 | // 48 | // Ex arc.: 49 | // 3x ---> X -------b0---> + ------> + -----------> Y 50 | // | | | | 51 | // Z1 | | Z1 52 | // | | | | 53 | // ----b1-----| |----a1----- 54 | // | | | | 55 | // Z2 | | Z2 56 | // | | | | 57 | // ----b3-----| |----a2----- 58 | 59 | module iir ( 60 | input clk, 61 | input rst, 62 | input signed [31:0] x, 63 | output signed [31:0] y 64 | ); 65 | wire signed [31:0] s1_s2, s2_s3; 66 | 67 | reg signed [63:0] z1_a_s1, z2_a_s1, 68 | z1_b_s1, z2_b_s1; 69 | wire signed [31:0] z1_a_next_s1, z2_a_next_s1, 70 | z1_b_next_s1, z2_b_next_s1; 71 | wire signed [63:0] b_out_s1, a_out_s1; 72 | wire signed [31:0] a1_s1, a2_s1, 73 | b0_s1, b1_s1, b2_s1; 74 | 75 | reg signed [63:0] z1_a_s2, z2_a_s2, 76 | z1_b_s2, z2_b_s2; 77 | wire signed [31:0] z1_a_next_s2, z2_a_next_s2, 78 | z1_b_next_s2, z2_b_next_s2; 79 | wire signed [63:0] b_out_s2, a_out_s2; 80 | wire signed [31:0] a1_s2, a2_s2, 81 | b0_s2, b1_s2, b2_s2; 82 | 83 | reg signed [63:0] z1_a_s3, z2_a_s3, 84 | z1_b_s3, z2_b_s3; 85 | wire signed [31:0] z1_a_next_s3, z2_a_next_s3, 86 | z1_b_next_s3, z2_b_next_s3; 87 | wire signed [63:0] b_out_s3, a_out_s3; 88 | wire signed [31:0] a1_s3, a2_s3, 89 | b0_s3, b1_s3, b2_s3; 90 | 91 | assign z1_b_next_s1 = x; 92 | assign z2_b_next_s1 = z1_b_s1; 93 | assign z1_a_next_s1 = s1_s2; 94 | assign z2_a_next_s1 = z1_a_s1; 95 | assign b_out_s1 = x*b0_s1 + z1_b_s1*b1_s1 + z2_b_s1*b2_s1; 96 | assign a_out_s1 = b_out_s1 - z1_a_s1*a1_s1 - z2_a_s1*a2_s1; 97 | assign s1_s2 = a_out_s1 >> 20; 98 | 99 | assign z1_b_next_s2 = s1_s2; 100 | assign z2_b_next_s2 = z1_b_s2; 101 | assign z1_a_next_s2 = s2_s3; 102 | assign z2_a_next_s2 = z1_a_s2; 103 | assign b_out_s2 = s1_s2*b0_s2 + z1_b_s2*b1_s2 + z2_b_s2*b2_s2; 104 | assign a_out_s2 = b_out_s2 - z1_a_s2*a1_s2 - z2_a_s2*a2_s2; 105 | assign s2_s3 = a_out_s2 >> 20; 106 | 107 | assign z1_b_next_s3 = s2_s3; 108 | assign z2_b_next_s3 = z1_b_s3; 109 | assign z1_a_next_s3 = y; 110 | assign z2_a_next_s3 = z1_a_s3; 111 | assign b_out_s3 = s2_s3*b0_s3 + z1_b_s3*b1_s3 + z2_b_s3*b2_s3; 112 | assign a_out_s3 = b_out_s3 - z1_a_s3*a1_s3 - z2_a_s3*a2_s3; 113 | assign y = a_out_s3 >> 20; 114 | 115 | // Q20 Format Coed = Floating Point * 2^20 116 | // -------------- SECTION 1 -------------- 117 | assign b0_s1 = 5509; 118 | assign b1_s1 = 11019; 119 | assign b2_s1 = 5509; 120 | assign a1_s1 = -1998080; 121 | assign a2_s1 = 971584; 122 | // -------------- SECTION 2 -------------- 123 | assign b0_s2 = 5180; 124 | assign b1_s2 = 10360; 125 | assign b2_s2 = 5180; 126 | assign a1_s2 = -1878592; 127 | assign a2_s2 = 850752; 128 | // -------------- SECTION 3 -------------- 129 | assign b0_s3 = 5007; 130 | assign b1_s3 = 10014; 131 | assign b2_s3 = 5007; 132 | assign a1_s3 = -1815872; 133 | assign a2_s3 = 787328; 134 | 135 | always @ (posedge clk or negedge rst) begin 136 | if (rst == 1'b0) begin 137 | z1_a_s1 <= 32'd0; 138 | z2_a_s1 <= 32'd0; 139 | z1_b_s1 <= 32'd0; 140 | z2_b_s1 <= 32'd0; 141 | 142 | z1_a_s2 <= 32'd0; 143 | z2_a_s2 <= 32'd0; 144 | z1_b_s2 <= 32'd0; 145 | z2_b_s2 <= 32'd0; 146 | 147 | z1_a_s3 <= 32'd0; 148 | z2_a_s3 <= 32'd0; 149 | z1_b_s3 <= 32'd0; 150 | z2_b_s3 <= 32'd0; 151 | end else begin 152 | z1_a_s1 <= z1_a_next_s1; 153 | z2_a_s1 <= z2_a_next_s1; 154 | z1_b_s1 <= z1_b_next_s1; 155 | z2_b_s1 <= z2_b_next_s1; 156 | 157 | z1_a_s2 <= z1_a_next_s2; 158 | z2_a_s2 <= z2_a_next_s2; 159 | z1_b_s2 <= z1_b_next_s2; 160 | z2_b_s2 <= z2_b_next_s2; 161 | 162 | z1_a_s3 <= z1_a_next_s3; 163 | z2_a_s3 <= z2_a_next_s3; 164 | z1_b_s3 <= z1_b_next_s3; 165 | z2_b_s3 <= z2_b_next_s3; 166 | end 167 | end 168 | endmodule 169 | -------------------------------------------------------------------------------- /roboy_fpga_code/msj_platform/MSJPlatformPIDController.sv: -------------------------------------------------------------------------------- 1 | // PD controller for the msj platform 2 | // This module implements a PID controller. It has 3 control modes (position, velocity, direct feed through). 3 | // It uses integers only. 4 | // 5 | // BSD 3-Clause License 6 | // 7 | // Copyright (c) 2018, Roboy 8 | // All rights reserved. 9 | // 10 | // Redistribution and use in source and binary forms, with or without 11 | // modification, are permitted provided that the following conditions are met: 12 | // 13 | // * Redistributions of source code must retain the above copyright notice, this 14 | // list of conditions and the following disclaimer. 15 | // 16 | // * Redistributions in binary form must reproduce the above copyright notice, 17 | // this list of conditions and the following disclaimer in the documentation 18 | // and/or other materials provided with the distribution. 19 | // 20 | // * Neither the name of the copyright holder nor the names of its 21 | // contributors may be used to endorse or promote products derived from 22 | // this software without specific prior written permission. 23 | // 24 | // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 25 | // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 | // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 27 | // DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 28 | // FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 | // DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 30 | // SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 31 | // CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 32 | // OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 33 | // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 34 | 35 | // author: Simon Trendel, simon.trendel@tum.de, 2018 36 | 37 | `timescale 1ns/10ps 38 | 39 | module MSJPlatformPIDController ( 40 | input clock, 41 | input reset, 42 | input signed [31:0] Kp, 43 | input signed [31:0] Ki, 44 | input signed [31:0] Kd, 45 | input signed [31:0] sp, 46 | input signed [31:0] outputPosMax, 47 | input signed [31:0] outputNegMax, 48 | input signed [31:0] integralNegMax, 49 | input signed [31:0] integralPosMax, 50 | input signed [31:0] deadBand, 51 | input signed [31:0] zero_speed, 52 | input [1:0] control_mode, // position velocity direct_duty 53 | input signed [31:0] position, 54 | input signed [31:0] velocity, 55 | input signed [31:0] outputDivider, 56 | input update_controller, 57 | output reg signed [31:0] duty 58 | ); 59 | 60 | always @(posedge clock, posedge reset) begin: PD_CONTROLLER_PD_CONTROLLERLOGIC 61 | reg signed [31:0] lastError; 62 | reg signed [31:0] err; 63 | reg signed [31:0] integral; 64 | reg signed [31:0] pterm; 65 | reg signed [31:0] dterm; 66 | reg signed [31:0] ffterm; 67 | reg update_controller_prev; 68 | reg signed [31:0] result; 69 | 70 | if (reset == 1) begin 71 | lastError <= 0; 72 | err <=0; 73 | result <= 0; 74 | update_controller_prev <= 0; 75 | integral <= 0; 76 | end else begin 77 | update_controller_prev <= update_controller; 78 | if(update_controller_prev==0 && update_controller==1) begin 79 | case(control_mode) 80 | 2'b00: err = (sp - position)/outputDivider; 81 | 2'b01: err = (sp - velocity)/outputDivider; 82 | 2'b10: duty = sp; // direct feed through 83 | default: err = 0; 84 | endcase; 85 | if(control_mode!=2'b10) begin 86 | if (((err >= deadBand) || (err <= ((-1) * deadBand)))) begin 87 | pterm = (Kp * err); 88 | if ((pterm < (zero_speed + outputPosMax)) || (pterm > (zero_speed + outputNegMax))) begin //if the proportional term is not maxed 89 | integral = integral + (Ki * err); //add to the integral 90 | if (integral > integralPosMax) begin 91 | integral = integralPosMax; 92 | end else if (integral < integralNegMax) begin 93 | integral = integralNegMax; 94 | end 95 | end 96 | dterm = ((err - lastError) * Kd); 97 | result = zero_speed + (pterm + dterm + integral); 98 | if ((result < outputNegMax)) begin 99 | result = outputNegMax; 100 | end else if ((result > outputPosMax)) begin 101 | result = outputPosMax; 102 | end 103 | end else begin 104 | result = zero_speed; 105 | end 106 | duty = result; 107 | lastError = err; 108 | end 109 | end 110 | end 111 | end 112 | 113 | 114 | endmodule 115 | 116 | -------------------------------------------------------------------------------- /roboy_fpga_code/myo_control/A1335Control.v: -------------------------------------------------------------------------------- 1 | module A1335Control ( 2 | input clock, 3 | input reset, 4 | input wire read_angle, 5 | input wire read_status, 6 | inout wire sda, 7 | output wire scl, 8 | output [2:0] LED, 9 | input [6:0] device_id, 10 | output reg done, 11 | output reg [11:0] angle, 12 | output reg [31:0] status, 13 | output reg ack_error 14 | ); 15 | 16 | reg rw; 17 | reg busy; 18 | reg ena; 19 | reg ena_prev; 20 | wire [7:0] byte_counter; 21 | reg [31:0] data_rd; 22 | wire [31:0] data_read_fifo; 23 | reg [31:0] data_wd; 24 | reg [7:0] number_of_bytes; 25 | 26 | reg [4:0] gpio_set; 27 | reg read_only; 28 | 29 | reg [7:0] read_counter; 30 | reg [7:0] a1335_state; 31 | reg [7:0] a1335_next_state; 32 | 33 | always @(posedge clock, posedge reset) begin: A1335_CONTROL_LOGIC 34 | parameter IDLE = 0, WAIT_FOR_I2C_TRANSMISSION = 1, DONE = 2, READ_ANGLE = 3; 35 | 36 | reg [7:0] command_counter; 37 | if (reset == 1) begin 38 | data_wd <= 0; 39 | ena <= 0; 40 | read_only <= 0; 41 | a1335_state <= IDLE; 42 | done <= 1; 43 | angle <= 7; 44 | end else begin 45 | ena_prev <= ena; 46 | case(a1335_state) 47 | IDLE: begin 48 | ena <= 0; 49 | if(read_angle) begin // read that shit 50 | a1335_state <= READ_ANGLE; 51 | command_counter <= 0; 52 | done <= 0; 53 | end 54 | end 55 | READ_ANGLE: begin 56 | if(command_counter< 2) begin 57 | a1335_state <= WAIT_FOR_I2C_TRANSMISSION; 58 | a1335_next_state <= READ_ANGLE; 59 | rw <= 1; 60 | case(command_counter) 61 | 0: begin data_wd <= {8'h20, 8'h00, 16'h0000}; ena <= 1; number_of_bytes <= 3; end 62 | 1: begin 63 | angle <= data_read_fifo[27:16]; 64 | fifo_read_ack <= 1; 65 | end 66 | default: data_wd <= 0; 67 | endcase 68 | end else begin 69 | command_counter <= 0; 70 | a1335_state <= DONE; 71 | end 72 | end 73 | DONE: begin 74 | a1335_state <= IDLE; 75 | done <= 1; 76 | end 77 | WAIT_FOR_I2C_TRANSMISSION: begin 78 | if(busy==0 && ena==0) begin 79 | a1335_state <= a1335_next_state; 80 | command_counter <= command_counter+1; 81 | end 82 | end 83 | default: a1335_state <= IDLE; 84 | endcase 85 | 86 | // if(read && ~waitrequest && address==1 && ~fifo_empty) begin 87 | // fifo_read_ack <= 1; 88 | // end 89 | 90 | if(byte_counter>=number_of_bytes) begin 91 | ena <= 0; 92 | end 93 | 94 | if(fifo_read_ack==1) begin 95 | fifo_read_ack <= 0; 96 | end 97 | 98 | if(ena_prev == 0 && ena == 1 && ~fifo_empty) begin 99 | fifo_clear <= 1; 100 | end 101 | 102 | if(fifo_clear == 1) begin 103 | fifo_clear <= 0; 104 | end 105 | end 106 | end 107 | 108 | wire fifo_write; 109 | reg read_fifo; 110 | reg write_fifo; 111 | wire fifo_write_ack; 112 | reg fifo_read_ack; 113 | reg fifo_clear; 114 | wire fifo_empty; 115 | wire fifo_full; 116 | wire [7:0] usedw; 117 | 118 | fifo fifo( 119 | .clock(clock), 120 | .data(data_rd), 121 | .rdreq(fifo_read_ack), 122 | .sclr(reset||fifo_clear), 123 | .wrreq(fifo_write), 124 | .q(data_read_fifo), 125 | .empty(fifo_empty), 126 | .full(fifo_full), 127 | .usedw(usedw) 128 | ); 129 | 130 | oneshot oneshot( 131 | .clk(clock), 132 | .edge_sig(fifo_write_ack), 133 | .level_sig(fifo_write) 134 | ); 135 | 136 | i2c_master #(50000000, 400000) i2c( 137 | .clk(clock), 138 | .reset_n(~reset), 139 | .ena(ena), 140 | .addr(device_id), 141 | .rw(rw), 142 | .data_wr(data_wd), 143 | .busy(busy), 144 | .data_rd(data_rd), 145 | .ack_error(ack_error), 146 | .sda(sda), 147 | .scl(scl), 148 | .byte_counter(byte_counter), 149 | .read_only(read_only), 150 | .number_of_bytes(number_of_bytes), 151 | .fifo_write_ack(fifo_write_ack) 152 | ); 153 | 154 | endmodule -------------------------------------------------------------------------------- /roboy_fpga_code/myo_control/FpuTest.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns/10ps 2 | 3 | module FpuTest ( 4 | input clock, 5 | input reset, 6 | input [7:0] address, 7 | input write, 8 | input signed [31:0] writedata, 9 | input read, 10 | output signed [31:0] readdata, 11 | output waitrequest 12 | ); 13 | 14 | assign readdata = returnvalue; 15 | assign waitrequest = (waitFlag && read); 16 | reg [31:0] returnvalue; 17 | reg waitFlag; 18 | 19 | reg [31:0] a; 20 | reg [31:0] b; 21 | reg [31:0] result[5:0]; 22 | 23 | always @(posedge clock, posedge reset) begin: AVALON_READ_INTERFACE 24 | if (reset == 1) begin 25 | waitFlag <= 1; 26 | end else begin 27 | waitFlag <= 1; 28 | if(read) begin 29 | case(address) 30 | 8'h00: returnvalue <= result[ADD]; 31 | 8'h01: returnvalue <= result[SUB]; 32 | 8'h02: returnvalue <= result[MUL]; 33 | 8'h03: returnvalue <= result[DIV]; 34 | 8'h04: returnvalue <= result[INT2FLO]; 35 | 8'h05: returnvalue <= result[FLO2INT]; 36 | default: returnvalue <= 32'hDEADBEEF; 37 | endcase 38 | if(waitFlag==1) begin // next clock cycle the returnvalue should be ready 39 | waitFlag <= 0; 40 | end 41 | end 42 | end 43 | end 44 | 45 | always @(posedge clock, posedge reset) begin: FPU_LOGIC 46 | if (reset == 1) begin 47 | 48 | end else begin 49 | // if we are writing via avalon bus and waitrequest is deasserted, write the respective register 50 | if(write && ~waitrequest) begin 51 | case(address) 52 | 8'h00: a <= writedata[31:0]; 53 | 8'h01: b <= writedata[31:0]; 54 | endcase 55 | end 56 | 57 | end 58 | end 59 | 60 | localparam ADD = 0; 61 | localparam SUB = 1; 62 | localparam MUL = 2; 63 | localparam DIV = 3; 64 | localparam INT2FLO = 4; 65 | localparam FLO2INT = 5; 66 | 67 | fpu add( clock, 0, ADD, a, b, result[ADD]); 68 | fpu sub( clock, 0, SUB, a, b, result[SUB]); 69 | fpu mul( clock, 0, MUL, a, b, result[MUL]); 70 | fpu div( clock, 0, DIV, a, b, result[DIV]); 71 | fpu int2flo( clock, 0, INT2FLO, a, b, result[INT2FLO]); 72 | fpu flo2int( clock, 0, FLO2INT, a, b, result[FLO2INT]); 73 | 74 | endmodule -------------------------------------------------------------------------------- /roboy_fpga_code/myo_control/PIDController.v: -------------------------------------------------------------------------------- 1 | // PID controller myoRobotics style 2 | // This module implements a PID controller. It has 3 control modes (position, velocity,displacement). 3 | // It uses integers only. 4 | // 5 | // BSD 3-Clause License 6 | // 7 | // Copyright (c) 2017, Roboy 8 | // All rights reserved. 9 | // 10 | // Redistribution and use in source and binary forms, with or without 11 | // modification, are permitted provided that the following conditions are met: 12 | // 13 | // * Redistributions of source code must retain the above copyright notice, this 14 | // list of conditions and the following disclaimer. 15 | // 16 | // * Redistributions in binary form must reproduce the above copyright notice, 17 | // this list of conditions and the following disclaimer in the documentation 18 | // and/or other materials provided with the distribution. 19 | // 20 | // * Neither the name of the copyright holder nor the names of its 21 | // contributors may be used to endorse or promote products derived from 22 | // this software without specific prior written permission. 23 | // 24 | // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 25 | // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 | // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 27 | // DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 28 | // FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 | // DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 30 | // SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 31 | // CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 32 | // OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 33 | // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 34 | 35 | // author: Simon Trendel, simon.trendel@tum.de, 2018 36 | 37 | `timescale 1ns/10ps 38 | 39 | module PIDController ( 40 | input clock, 41 | input reset, 42 | input signed [31:0] Kp, 43 | input signed [31:0] Kd, 44 | input signed [31:0] Ki, 45 | input signed [31:0] sp, 46 | input signed [31:0] forwardGain, 47 | input signed [31:0] outputPosMax, 48 | input signed [31:0] outputNegMax, 49 | input signed [31:0] IntegralNegMax, 50 | input signed [31:0] IntegralPosMax, 51 | input signed [31:0] deadBand, 52 | input [2:0] control_mode, // position velocity displacement current direct 53 | input signed [31:0] position, 54 | input signed [15:0] velocity, 55 | input signed [31:0] displacement, 56 | input signed [31:0] motor_angle, 57 | input signed [15:0] current, 58 | input signed [31:0] outputShifter, 59 | input update_controller, 60 | input myo_brick, 61 | output reg signed [15:0] pwmRef 62 | ); 63 | 64 | always @(posedge clock, posedge reset) begin: PID_CONTROLLER_PID_CONTROLLERLOGIC 65 | reg signed [31:0] integral; 66 | reg signed [31:0] lastError; 67 | reg signed [31:0] err; 68 | reg signed [31:0] pterm; 69 | reg signed [31:0] dterm; 70 | reg signed [31:0] ffterm; 71 | reg signed [31:0] displacement_offset; 72 | reg update_controller_prev; 73 | reg signed [31:0] result; 74 | 75 | if (reset == 1) begin 76 | integral <= 0; 77 | lastError <= 0; 78 | err <=0; 79 | result <= 0; 80 | update_controller_prev <= 0; 81 | end else begin 82 | update_controller_prev <= update_controller; 83 | if(update_controller_prev==0 && update_controller==1) begin 84 | case(control_mode) 85 | 0: err = (sp - position); 86 | 1: err = (sp - velocity); 87 | 2: begin 88 | if(~myo_brick)begin 89 | if(displacement<0) begin 90 | displacement_offset = displacement; 91 | end else begin 92 | displacement_offset = 0; 93 | end 94 | if (sp>0) begin 95 | err = (sp - (displacement-displacement_offset)); 96 | end else begin 97 | err = 0; 98 | end 99 | end else begin 100 | if (sp>0) begin 101 | err = (sp - motor_angle); 102 | end else begin 103 | err = 0; 104 | end 105 | end 106 | end 107 | default: err = 0; 108 | endcase; 109 | if(control_mode!=3) begin 110 | if (((err >= deadBand) || (err <= ((-1) * deadBand)))) begin 111 | pterm = (Kp * err); 112 | if ((pterm < outputPosMax) || (pterm > outputNegMax)) begin //if the proportional term is not maxed 113 | integral = integral + (Ki * err); //add to the integral 114 | if (integral > IntegralPosMax) begin 115 | integral = IntegralPosMax; 116 | end else if (integral < IntegralNegMax) begin 117 | integral = IntegralNegMax; 118 | end 119 | end 120 | dterm = ((err - lastError) * Kd); 121 | // ffterm = (forwardGain * sp); 122 | // result = (((ffterm + pterm) + integral) + dterm)>>>outputShifter; 123 | result = (pterm + dterm + integral)>>>outputShifter; 124 | end else begin 125 | result = integral; 126 | end 127 | lastError = err; 128 | end else begin 129 | result = sp; 130 | end 131 | // limit output 132 | if ((result < outputNegMax)) begin 133 | result = outputNegMax; 134 | end else if ((result > outputPosMax)) begin 135 | result = outputPosMax; 136 | end 137 | pwmRef = result; 138 | end 139 | end 140 | end 141 | 142 | 143 | endmodule 144 | 145 | -------------------------------------------------------------------------------- /roboy_fpga_code/myo_control/spi_master_slave/trunk/doc/UNDER_CONSTRUCTION.txt: -------------------------------------------------------------------------------- 1 | Please note that this documentation is still under construction, and it is lagging behind the code. 2 | It will be updated as it is evolving, but eventually there will be a complete manual and implementation guide. 3 | 4 | Jonny Doin -------------------------------------------------------------------------------- /roboy_fpga_code/myo_control/spi_master_slave/trunk/doc/src/SPI_MODES.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Roboy/roboy_fpga_code/e76cbaf8cc916359927d2e0692fff6fd377feff7/roboy_fpga_code/myo_control/spi_master_slave/trunk/doc/src/SPI_MODES.jpg -------------------------------------------------------------------------------- /roboy_fpga_code/myo_control/spi_master_slave/trunk/doc/src/spi_master_slave_Specifications.doc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Roboy/roboy_fpga_code/e76cbaf8cc916359927d2e0692fff6fd377feff7/roboy_fpga_code/myo_control/spi_master_slave/trunk/doc/src/spi_master_slave_Specifications.doc -------------------------------------------------------------------------------- /roboy_fpga_code/myo_control/spi_master_slave/trunk/rtl/spi_master_slave/readme.txt: -------------------------------------------------------------------------------- 1 | SPI_MASTER_SLAVE 2 | ================ 3 | 4 | 5 | This project was started from the need to have a robust yet simple SPI interface core 6 | written in VHDL to use in generic FPGA-to-device interfacing. 7 | The resulting cores generate very small and efficient circuits, that operate from very 8 | slow SPI clocks up to over 50MHz SPI clocks. 9 | 10 | 11 | VHDL files for spi master/slave project: 12 | --------------------------------------- 13 | 14 | spi_master.vhd spi master module, can be used independently 15 | spi_slave.vhd spi slave module, can be used independently 16 | spi_loopback.vhd wrapper module for simulating the master and slave modules 17 | spi_loopback_test.vhd testbench for simulating the loopback module, test master against slave 18 | spi_loopback.ucf constraints for simulation: Spartan-6, area, LUT compression. 19 | 20 | 21 | The original development is done in Xilinx ISE 13.1, targeted to a Spartan-6 device. 22 | 23 | ISIM SIMULATION 24 | --------------- 25 | 26 | VHDL simulation was done in ISIM, after Place & Route, with default constraints, for the slowest 27 | Spartan-6 device, synthesis generated 41 slices, and the design was simulated at 25MHz spi SCK, and 100MHz for the parallel interfaces clocks. 28 | 29 | SILICON VERIFICATION 30 | -------------------- 31 | 32 | Design verification in silicon was done in a Digilent Atlys board, and the verification project can be found at the \trunk\syn directory, with all the required files to replicate the verification tests, including pinlock constraints for the Atlys board. 33 | 34 | LICENSING 35 | --------- 36 | 37 | This work is licensed as a LGPL work. If you find this licensing too restrictive for hardware, or it is not adequate for you, please get in touch with me and we can arrange a more suitable open source hardware licensing. 38 | 39 | 40 | 41 | If you have any questions or usage issues with this core, please open a thread in OpenCores forum, and I will be pleased to answer. 42 | 43 | If you find a bug or a design fault in the models, or if you have an issue that you like to be addressed, please open a bug/issue in the OpenCores bugtracker for this project, at 44 | http://opencores.org/project,spi_master_slave,bugtracker. 45 | 46 | 47 | In any case, thank you for testing and using this core. 48 | 49 | 50 | Jonny Doin 51 | jdoin@opencores.org 52 | 53 | -------------------------------------------------------------------------------- /roboy_fpga_code/myo_control/spi_master_slave/trunk/rtl/spi_master_slave/spi_loopback.ucf: -------------------------------------------------------------------------------- 1 | 2 | #Created by Constraints Editor (xc6slx45t-csg484-3) - 2011/06/08 3 | NET "s_clk_i" TNM_NET = s_clk_i; 4 | TIMESPEC TS_s_clk_i = PERIOD "s_clk_i" 8 ns HIGH 50%; 5 | #Created by Constraints Editor (xc6slx45t-csg484-3) - 2011/06/08 6 | NET "m_clk_i" TNM_NET = m_clk_i; 7 | TIMESPEC TS_m_clk_i = PERIOD "m_clk_i" 8 ns HIGH 50%; 8 | NET "s_spi_sck_i" TNM_NET = s_spi_sck_i; 9 | TIMESPEC TS_s_spi_sck_i = PERIOD "s_spi_sck_i" 30 ns HIGH 50%; 10 | NET "m_spi_sck_o_OBUF" TNM_NET = m_spi_sck_o_OBUF; 11 | TIMESPEC TS_m_spi_sck_o_OBUF = PERIOD "m_spi_sck_o_OBUF" 30 ns HIGH 50%; 12 | NET "Inst_spi_master/core_n_clk" TNM_NET = Inst_spi_master/core_n_clk; 13 | TIMESPEC TS_Inst_spi_master_core_n_clk = PERIOD "Inst_spi_master/core_n_clk" 30 ns HIGH 50%; 14 | INST "m_di_i<0>" TNM = m_di; 15 | INST "m_di_i<1>" TNM = m_di; 16 | INST "m_di_i<2>" TNM = m_di; 17 | INST "m_di_i<3>" TNM = m_di; 18 | INST "m_di_i<4>" TNM = m_di; 19 | INST "m_di_i<5>" TNM = m_di; 20 | INST "m_di_i<6>" TNM = m_di; 21 | INST "m_di_i<7>" TNM = m_di; 22 | INST "m_di_i<8>" TNM = m_di; 23 | INST "m_di_i<9>" TNM = m_di; 24 | INST "m_di_i<10>" TNM = m_di; 25 | INST "m_di_i<11>" TNM = m_di; 26 | INST "m_di_i<12>" TNM = m_di; 27 | INST "m_di_i<13>" TNM = m_di; 28 | INST "m_di_i<14>" TNM = m_di; 29 | INST "m_di_i<15>" TNM = m_di; 30 | INST "m_di_i<16>" TNM = m_di; 31 | INST "m_di_i<17>" TNM = m_di; 32 | INST "m_di_i<18>" TNM = m_di; 33 | INST "m_di_i<19>" TNM = m_di; 34 | INST "m_di_i<20>" TNM = m_di; 35 | INST "m_di_i<21>" TNM = m_di; 36 | INST "m_di_i<22>" TNM = m_di; 37 | INST "m_di_i<23>" TNM = m_di; 38 | INST "m_di_i<24>" TNM = m_di; 39 | INST "m_di_i<25>" TNM = m_di; 40 | INST "m_di_i<26>" TNM = m_di; 41 | INST "m_di_i<27>" TNM = m_di; 42 | INST "m_di_i<28>" TNM = m_di; 43 | INST "m_di_i<29>" TNM = m_di; 44 | INST "m_di_i<30>" TNM = m_di; 45 | INST "m_di_i<31>" TNM = m_di; 46 | TIMEGRP "m_di" OFFSET = IN 8 ns VALID 8 ns BEFORE "m_clk_i" RISING; 47 | INST "m_spi_miso_i" TNM = m_miso; 48 | INST "s_di_i<0>" TNM = s_di; 49 | INST "s_di_i<1>" TNM = s_di; 50 | INST "s_di_i<2>" TNM = s_di; 51 | INST "s_di_i<3>" TNM = s_di; 52 | INST "s_di_i<4>" TNM = s_di; 53 | INST "s_di_i<5>" TNM = s_di; 54 | INST "s_di_i<6>" TNM = s_di; 55 | INST "s_di_i<7>" TNM = s_di; 56 | INST "s_di_i<8>" TNM = s_di; 57 | INST "s_di_i<9>" TNM = s_di; 58 | INST "s_di_i<10>" TNM = s_di; 59 | INST "s_di_i<11>" TNM = s_di; 60 | INST "s_di_i<12>" TNM = s_di; 61 | INST "s_di_i<13>" TNM = s_di; 62 | INST "s_di_i<14>" TNM = s_di; 63 | INST "s_di_i<15>" TNM = s_di; 64 | INST "s_di_i<16>" TNM = s_di; 65 | INST "s_di_i<17>" TNM = s_di; 66 | INST "s_di_i<18>" TNM = s_di; 67 | INST "s_di_i<19>" TNM = s_di; 68 | INST "s_di_i<20>" TNM = s_di; 69 | INST "s_di_i<21>" TNM = s_di; 70 | INST "s_di_i<22>" TNM = s_di; 71 | INST "s_di_i<23>" TNM = s_di; 72 | INST "s_di_i<24>" TNM = s_di; 73 | INST "s_di_i<25>" TNM = s_di; 74 | INST "s_di_i<26>" TNM = s_di; 75 | INST "s_di_i<27>" TNM = s_di; 76 | INST "s_di_i<28>" TNM = s_di; 77 | INST "s_di_i<29>" TNM = s_di; 78 | INST "s_di_i<30>" TNM = s_di; 79 | INST "s_di_i<31>" TNM = s_di; 80 | TIMEGRP "s_di" OFFSET = IN 8 ns VALID 8 ns BEFORE "s_clk_i" RISING; 81 | INST "s_spi_mosi_i" TNM = s_mosi; 82 | INST "m_do_o<0>" TNM = m_do; 83 | INST "m_do_o<1>" TNM = m_do; 84 | INST "m_do_o<2>" TNM = m_do; 85 | INST "m_do_o<3>" TNM = m_do; 86 | INST "m_do_o<4>" TNM = m_do; 87 | INST "m_do_o<5>" TNM = m_do; 88 | INST "m_do_o<6>" TNM = m_do; 89 | INST "m_do_o<7>" TNM = m_do; 90 | INST "m_do_o<8>" TNM = m_do; 91 | INST "m_do_o<9>" TNM = m_do; 92 | INST "m_do_o<10>" TNM = m_do; 93 | INST "m_do_o<11>" TNM = m_do; 94 | INST "m_do_o<12>" TNM = m_do; 95 | INST "m_do_o<13>" TNM = m_do; 96 | INST "m_do_o<14>" TNM = m_do; 97 | INST "m_do_o<15>" TNM = m_do; 98 | INST "m_do_o<16>" TNM = m_do; 99 | INST "m_do_o<17>" TNM = m_do; 100 | INST "m_do_o<18>" TNM = m_do; 101 | INST "m_do_o<19>" TNM = m_do; 102 | INST "m_do_o<20>" TNM = m_do; 103 | INST "m_do_o<21>" TNM = m_do; 104 | INST "m_do_o<22>" TNM = m_do; 105 | INST "m_do_o<23>" TNM = m_do; 106 | INST "m_do_o<24>" TNM = m_do; 107 | INST "m_do_o<25>" TNM = m_do; 108 | INST "m_do_o<26>" TNM = m_do; 109 | INST "m_do_o<27>" TNM = m_do; 110 | INST "m_do_o<28>" TNM = m_do; 111 | INST "m_do_o<29>" TNM = m_do; 112 | INST "m_do_o<30>" TNM = m_do; 113 | INST "m_do_o<31>" TNM = m_do; 114 | #Created by Constraints Editor (xc6slx45t-csg484-3) - 2011/06/09 115 | INST "m_rx_bit_reg_o" TNM = m_rx_bit; 116 | -------------------------------------------------------------------------------- /roboy_fpga_code/myo_control/spi_master_slave/trunk/syn/ATLYS_01.SET: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Roboy/roboy_fpga_code/e76cbaf8cc916359927d2e0692fff6fd377feff7/roboy_fpga_code/myo_control/spi_master_slave/trunk/syn/ATLYS_01.SET -------------------------------------------------------------------------------- /roboy_fpga_code/myo_control/spi_master_slave/trunk/syn/ATLYS_03.SET: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Roboy/roboy_fpga_code/e76cbaf8cc916359927d2e0692fff6fd377feff7/roboy_fpga_code/myo_control/spi_master_slave/trunk/syn/ATLYS_03.SET -------------------------------------------------------------------------------- /roboy_fpga_code/myo_control/spi_master_slave/trunk/syn/ATLYS_04.SET: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Roboy/roboy_fpga_code/e76cbaf8cc916359927d2e0692fff6fd377feff7/roboy_fpga_code/myo_control/spi_master_slave/trunk/syn/ATLYS_04.SET -------------------------------------------------------------------------------- /roboy_fpga_code/myo_control/spi_master_slave/trunk/syn/ATLYS_05.SET: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Roboy/roboy_fpga_code/e76cbaf8cc916359927d2e0692fff6fd377feff7/roboy_fpga_code/myo_control/spi_master_slave/trunk/syn/ATLYS_05.SET -------------------------------------------------------------------------------- /roboy_fpga_code/myo_control/spi_master_slave/trunk/syn/fuse.xmsgs: -------------------------------------------------------------------------------- 1 | 2 | 7 | 8 | 9 | 10 | -------------------------------------------------------------------------------- /roboy_fpga_code/myo_control/spi_master_slave/trunk/syn/fuseRelaunch.cmd: -------------------------------------------------------------------------------- 1 | -intstyle "ise" -incremental -lib "secureip" -o "C:/dropbox/Dropbox/VHDL_training/OpenCores/spi_master_slave/spi_master_slave/trunk/syn/testbench_isim_par.exe" -prj "C:/dropbox/Dropbox/VHDL_training/OpenCores/spi_master_slave/spi_master_slave/trunk/syn/testbench_par.prj" "work.testbench" 2 | -------------------------------------------------------------------------------- /roboy_fpga_code/myo_control/spi_master_slave/trunk/syn/par_usage_statistics.html: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 |
Par Statistics
Total Non-vccgnd Signals=306
Total Non-vccgnd Design Pins=851
Total Non-vccgnd Conns=851
Total Non-vccgnd Timing Constrained Conns=711
Phase 1 CPU=5.3 sec
Phase 2 CPU=6.3 sec
Phase 3 CPU=7.6 sec
Phase 4 CPU=9.0 sec
Phase 5 CPU=9.4 sec
Phase 6 CPU=9.4 sec
Phase 7 CPU=9.4 sec
Phase 8 CPU=9.4 sec
Phase 9 CPU=9.4 sec
Phase 10 CPU=9.5 sec
AvgWirelenPerPin Fanout 1=10.0
AvgWirelenPerPin Fanout 2=3.5
AvgWirelenPerPin Fanout 3=5.3
AvgWirelenPerPin Fanout 4=7.3
AvgWirelenPerPin Fanout 10=2.6
AvgWirelenPerPin Fanout 50=3.0
AvgWirelenPerPin Fanout 100=17.8
AvgWirelenPerPin Fanout 500=0.0
AvgWirelenPerPin Fanout 5000=0.0
AvgWirelenPerPin Fanout 20000=0.0
AvgWirelenPerPin Fanout 50000=0.0
AvgWirelenPerPin Fanout 100000=0.0
IRR Gamma=1.0202
33 | -------------------------------------------------------------------------------- /roboy_fpga_code/myo_control/spi_master_slave/trunk/syn/readme.txt: -------------------------------------------------------------------------------- 1 | SPI_MASTER_ATLYS 2 | ================ 3 | 4 | This is a ISE 13.1 project to test the spi_master.vhd, spi_slave.vhd and grp_debouncer.vhd models in silicon. 5 | The target board is a Digilent Atlys FPGA board (Spartan-6 @ 100MHz), and the circuit was tested at different SPI clock frequencies. 6 | See the scope screenshots in the spi_master_scope_photos.zip file for each SPI frequency tested. 7 | The circuit verifies both master and slave cores, with transmit and receive streams operating full-duplex at 50MHz of SPI clock. 8 | 9 | This circuit also includes a very robust debouncing circuit to use with multiple inputs. The model, "grp_debouncer.vhd" is also published under a LGPL license. 10 | 11 | The files are: 12 | ------------- 13 | 14 | spi_master.vhd vhdl model for the spi_master interface 15 | spi_slave.vhd vhdl model for the spi_slave interface 16 | grp_debouncer.vhd vhdl model for the switch debouncer 17 | spi_master_atlys_top.vhd vhdl model for the toplevel block to synthesize for the Atlys board 18 | spi_master_atlys_test.vhd testbench for the synthesizable toplevel 'spi_master_atlys_top.vhd' 19 | spi_master_atlys.xise ISE 13.1 project file 20 | spi_master_atlys.ucf pin lock constraints for the Atlys board 21 | spi_master_scope_photos.zip Tektronix MSO2014 screenshots for the verification tests 22 | spi_master_envsettings.html synthesis env settings, with the tools setup used 23 | ATLYS_0x.SET Tek MSO2014 settings files with the debug pin names 24 | spi_master_atlys_top_bit.zip bitgen file to program the Atlys board 25 | 26 | 27 | LICENSING 28 | --------- 29 | 30 | This work is licensed as a LGPL work. If you find this licensing too restrictive for hardware, or it is not adequate for you, please get in touch with me and we can arrange a more suitable open source hardware licensing. 31 | 32 | 33 | 34 | If you need assistance on putting this to work, please place a thread in the OpenCores forum, and I will be glad to answer, or send me e-mail: jdoin@opencores.org 35 | 36 | If you find a bug or a design fault in the models, or if you have an issue that you like to be addressed, please open a bug/issue in the OpenCores bugtracker for this project, at 37 | 38 | http://opencores.org/project,spi_master_slave,bugtracker 39 | 40 | If you find this core useful, please let me know: jdoin@opencores.org 41 | 42 | In any case, thank you very much for testing this core. 43 | 44 | 45 | Jonny Doin 46 | jdoin@opencores.org 47 | 48 | -------------------------------------------------------------------------------- /roboy_fpga_code/myo_control/spi_master_slave/trunk/syn/sim_master_slave_ct.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Roboy/roboy_fpga_code/e76cbaf8cc916359927d2e0692fff6fd377feff7/roboy_fpga_code/myo_control/spi_master_slave/trunk/syn/sim_master_slave_ct.pdf -------------------------------------------------------------------------------- /roboy_fpga_code/myo_control/spi_master_slave/trunk/syn/spi_master_atlys_top.drc: -------------------------------------------------------------------------------- 1 | Release 13.1 Drc O.40d (nt) 2 | Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. 3 | 4 | Mon Aug 29 00:11:21 2011 5 | 6 | drc -z spi_master_atlys_top.ncd spi_master_atlys_top.pcf 7 | 8 | DRC detected 0 errors and 0 warnings. 9 | -------------------------------------------------------------------------------- /roboy_fpga_code/myo_control/spi_master_slave/trunk/syn/spi_master_atlys_top.pcf: -------------------------------------------------------------------------------- 1 | //! ************************************************************************** 2 | // Written by: Map O.40d on Thu Sep 01 13:07:27 2011 3 | //! ************************************************************************** 4 | 5 | SCHEMATIC START; 6 | COMP "dbg_o<10>" LOCATE = SITE "V13" LEVEL 1; 7 | COMP "dbg_o<11>" LOCATE = SITE "U13" LEVEL 1; 8 | COMP "spi_miso_o" LOCATE = SITE "V15" LEVEL 1; 9 | COMP "spi_mosi_o" LOCATE = SITE "U15" LEVEL 1; 10 | COMP "sw_i<0>" LOCATE = SITE "A10" LEVEL 1; 11 | COMP "sw_i<1>" LOCATE = SITE "D14" LEVEL 1; 12 | COMP "sw_i<2>" LOCATE = SITE "C14" LEVEL 1; 13 | COMP "sw_i<3>" LOCATE = SITE "P15" LEVEL 1; 14 | COMP "sw_i<4>" LOCATE = SITE "P12" LEVEL 1; 15 | COMP "sw_i<5>" LOCATE = SITE "R5" LEVEL 1; 16 | COMP "sw_i<6>" LOCATE = SITE "T5" LEVEL 1; 17 | COMP "sw_i<7>" LOCATE = SITE "E4" LEVEL 1; 18 | COMP "spi_ssel_o" LOCATE = SITE "U16" LEVEL 1; 19 | COMP "m_state_o<0>" LOCATE = SITE "T3" LEVEL 1; 20 | COMP "m_state_o<1>" LOCATE = SITE "R3" LEVEL 1; 21 | COMP "m_state_o<2>" LOCATE = SITE "P6" LEVEL 1; 22 | COMP "m_state_o<3>" LOCATE = SITE "N5" LEVEL 1; 23 | COMP "dbg_o<0>" LOCATE = SITE "N9" LEVEL 1; 24 | COMP "dbg_o<1>" LOCATE = SITE "M10" LEVEL 1; 25 | COMP "dbg_o<2>" LOCATE = SITE "P11" LEVEL 1; 26 | COMP "dbg_o<3>" LOCATE = SITE "N10" LEVEL 1; 27 | COMP "dbg_o<4>" LOCATE = SITE "V12" LEVEL 1; 28 | COMP "dbg_o<5>" LOCATE = SITE "T12" LEVEL 1; 29 | COMP "dbg_o<6>" LOCATE = SITE "T11" LEVEL 1; 30 | COMP "dbg_o<7>" LOCATE = SITE "R11" LEVEL 1; 31 | COMP "dbg_o<8>" LOCATE = SITE "N11" LEVEL 1; 32 | COMP "dbg_o<9>" LOCATE = SITE "M11" LEVEL 1; 33 | COMP "btn_i<0>" LOCATE = SITE "T15" LEVEL 1; 34 | COMP "btn_i<1>" LOCATE = SITE "N4" LEVEL 1; 35 | COMP "btn_i<2>" LOCATE = SITE "P4" LEVEL 1; 36 | COMP "btn_i<3>" LOCATE = SITE "P3" LEVEL 1; 37 | COMP "btn_i<4>" LOCATE = SITE "F6" LEVEL 1; 38 | COMP "btn_i<5>" LOCATE = SITE "F5" LEVEL 1; 39 | COMP "led_o<0>" LOCATE = SITE "U18" LEVEL 1; 40 | COMP "led_o<1>" LOCATE = SITE "M14" LEVEL 1; 41 | COMP "led_o<2>" LOCATE = SITE "N14" LEVEL 1; 42 | COMP "led_o<3>" LOCATE = SITE "L14" LEVEL 1; 43 | COMP "led_o<4>" LOCATE = SITE "M13" LEVEL 1; 44 | COMP "led_o<5>" LOCATE = SITE "D4" LEVEL 1; 45 | COMP "led_o<6>" LOCATE = SITE "P16" LEVEL 1; 46 | COMP "led_o<7>" LOCATE = SITE "N12" LEVEL 1; 47 | COMP "spi_sck_o" LOCATE = SITE "V16" LEVEL 1; 48 | COMP "s_state_o<0>" LOCATE = SITE "V9" LEVEL 1; 49 | COMP "s_state_o<1>" LOCATE = SITE "T9" LEVEL 1; 50 | COMP "s_state_o<2>" LOCATE = SITE "V4" LEVEL 1; 51 | COMP "s_state_o<3>" LOCATE = SITE "T4" LEVEL 1; 52 | SCHEMATIC END; 53 | 54 | -------------------------------------------------------------------------------- /roboy_fpga_code/myo_control/spi_master_slave/trunk/syn/spi_master_atlys_top.xst: -------------------------------------------------------------------------------- 1 | set -tmpdir "xst/projnav.tmp" 2 | set -xsthdpdir "xst" 3 | run 4 | -ifn spi_master_atlys_top.prj 5 | -ifmt mixed 6 | -ofn spi_master_atlys_top 7 | -ofmt NGC 8 | -p xc6slx45-2-csg324 9 | -top spi_master_atlys_top 10 | -opt_mode Speed 11 | -opt_level 2 12 | -power NO 13 | -iuc NO 14 | -keep_hierarchy No 15 | -netlist_hierarchy As_Optimized 16 | -rtlview Yes 17 | -glob_opt AllClockNets 18 | -read_cores YES 19 | -write_timing_constraints NO 20 | -cross_clock_analysis NO 21 | -hierarchy_separator / 22 | -bus_delimiter <> 23 | -case Maintain 24 | -slice_utilization_ratio 100 25 | -bram_utilization_ratio 100 26 | -dsp_utilization_ratio 100 27 | -lc Area 28 | -reduce_control_sets Auto 29 | -fsm_extract YES -fsm_encoding Gray 30 | -safe_implementation No 31 | -fsm_style LUT 32 | -ram_extract No 33 | -rom_extract No 34 | -shreg_extract NO 35 | -auto_bram_packing NO 36 | -resource_sharing YES 37 | -async_to_sync NO 38 | -shreg_min_size 2 39 | -use_dsp48 Auto 40 | -iobuf YES 41 | -max_fanout 100000 42 | -bufg 16 43 | -register_duplication YES 44 | -register_balancing No 45 | -optimize_primitives NO 46 | -use_clock_enable Auto 47 | -use_sync_set Auto 48 | -use_sync_reset Auto 49 | -iob Auto 50 | -equivalent_register_removal YES 51 | -slice_utilization_ratio_maxmargin 5 52 | -------------------------------------------------------------------------------- /roboy_fpga_code/myo_control/spi_master_slave/trunk/syn/spi_master_atlys_top_bit.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Roboy/roboy_fpga_code/e76cbaf8cc916359927d2e0692fff6fd377feff7/roboy_fpga_code/myo_control/spi_master_slave/trunk/syn/spi_master_atlys_top_bit.zip -------------------------------------------------------------------------------- /roboy_fpga_code/myo_control/spi_master_slave/trunk/syn/spi_master_atlys_top_bitgen.xwbt: -------------------------------------------------------------------------------- 1 | INTSTYLE=ise 2 | INFILE=C:\dropbox\Dropbox\VHDL_training\OpenCores\spimasterslave\spi_master_slave\trunk\syn\spi_master_atlys_top.ncd 3 | OUTFILE=C:\dropbox\Dropbox\VHDL_training\OpenCores\spimasterslave\spi_master_slave\trunk\syn\spi_master_atlys_top.bit 4 | FAMILY=Spartan6 5 | PART=xc6slx45-2csg324 6 | WORKINGDIR=C:\dropbox\Dropbox\VHDL_training\OpenCores\spimasterslave\spi_master_slave\trunk\syn 7 | LICENSE=WebPack 8 | USER_INFO=205970357_0_0_751 9 | -------------------------------------------------------------------------------- /roboy_fpga_code/myo_control/spi_master_slave/trunk/syn/spi_master_scope_photos.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Roboy/roboy_fpga_code/e76cbaf8cc916359927d2e0692fff6fd377feff7/roboy_fpga_code/myo_control/spi_master_slave/trunk/syn/spi_master_scope_photos.zip -------------------------------------------------------------------------------- /roboy_fpga_code/myo_control/spi_master_slave/trunk/syn/spi_master_summary.html: -------------------------------------------------------------------------------- 1 | Xilinx Design Summary 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | 45 | 46 | 47 |
spi_master_atlys_top Project Status
Project File:spi_ms_atlys_ct.xiseParser Errors:
Module Name:spi_master_atlys_topImplementation State:New
Target Device:xc6slx45-2csg324
  • Errors:
 
Product Version:ISE 13.1
  • Warnings:
 
Design Goal:Balanced
  • Routing Results:
 33 |  
Design Strategy:Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment: 
  • Final Timing Score:
  
48 | 49 | 50 | 51 |  
52 | 53 | 54 |
Current Errors [-]
No Errors Found
55 | 56 | 57 | 58 |  
59 | 60 | 61 |
Current Warnings [-]
No Warnings Found
62 | 63 | 64 | 65 | 66 | 67 | 68 | 69 | 70 | 71 | 72 | 73 | 74 | 75 |  
76 | 77 | 78 | 79 | 80 | 81 | 82 | 83 | 84 | 85 | 86 |
Detailed Reports [-]
Report NameStatusGeneratedErrorsWarningsInfos
Synthesis Report     
Translation Report     
Map Report     
Place and Route Report     
Power Report     
Post-PAR Static Timing Report     
Bitgen Report     
87 |  
88 | 89 | 90 |
Secondary Reports [-]
Report NameStatusGenerated
91 | 92 | 93 |
Date Generated: 08/10/2011 - 22:47:40
94 | -------------------------------------------------------------------------------- /roboy_fpga_code/neopixel/Counter.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns/10ps 2 | 3 | module Counter ( 4 | input clk, 5 | input reset, 6 | output reg [31:0] counter 7 | ); 8 | 9 | always @(posedge clk, posedge reset) begin: COUNTER_COUNTERLOGIC 10 | if (reset == 1) begin 11 | counter <= 0; 12 | end else begin 13 | counter <= counter + 1; 14 | end 15 | end 16 | 17 | endmodule 18 | -------------------------------------------------------------------------------- /roboy_fpga_code/neopixel/neopixel.v: -------------------------------------------------------------------------------- 1 | // neopixel transmitter 2 | 3 | `timescale 1ns/10ps 4 | 5 | module neopixel ( 6 | input clock, 7 | input reset, 8 | // this is for the avalon interface 9 | input [7:0] address, 10 | input write, 11 | input signed [31:0] writedata, 12 | input read, 13 | output signed [31:0] readdata, 14 | output waitrequest, 15 | output reg one_wire 16 | ); 17 | 18 | assign readdata = 19 | ((address == 0))? send_to_neopixels: 20 | 32'hDEAD_BEEF; 21 | 22 | parameter CLOCK_SPEED_HZ = 50_000_000; 23 | parameter NUMBER_OF_NEOPIXEL = 35; 24 | localparam RGBW = 0; 25 | 26 | reg send_to_neopixels; 27 | 28 | always @(posedge clock, posedge reset) begin: NEOPIXEL_CONTROL_LOGIC 29 | reg spi_done_prev; 30 | if (reset == 1) begin 31 | send_to_neopixels <= 0; 32 | end else begin 33 | // if we are writing via avalon bus and waitrequest is deasserted, write the respective register 34 | if(write && ~waitrequest) begin 35 | if(address==0) begin 36 | send_to_neopixels <= (writedata[31:0]!=0); 37 | end else begin 38 | if(address(CLOCK_SPEED_HZ/pwm_freq))begin 56 | counter <= 0; 57 | end 58 | if(auto_fan)begin 59 | duty_ticks <= current_average*sensitivity; 60 | end 61 | end 62 | end 63 | 64 | 65 | endmodule // FanControl 66 | -------------------------------------------------------------------------------- /roboy_fpga_code/pwm_control/pwm_avalon_bridge.v: -------------------------------------------------------------------------------- 1 | // pwm_avalon_bridge node 2 | // you can read out the registers via avalon bus in the following way: 3 | // #define IORD(base,reg) (*(((volatile uint32_t*)base)+reg)) 4 | // #define IOWR(base,reg,data) (*(((volatile uint32_t*)base)+reg)=data) 5 | // where reg corresponds to the address of the avalon slave 6 | 7 | `timescale 1ns/10ps 8 | 9 | module pwm_avalon_bridge ( 10 | input clock, 11 | input reset, 12 | // this is for the avalon interface 13 | input [15:0] address, 14 | input write, 15 | input signed [31:0] writedata, 16 | // these are the pwm ports 17 | output [NUMBER_OF_MOTORS-1:0] PWM 18 | ); 19 | 20 | parameter NUMBER_OF_MOTORS = 6; 21 | parameter CLOCK_SPEED_HZ = 50_000_000; 22 | parameter PWM_FREQ = 60; 23 | parameter PWM_PAUSE_FREQ = 50; 24 | parameter PWM_RESOLUTION = 12; 25 | parameter PWM_PHASES = 1; 26 | 27 | reg [31:0] i; 28 | reg [31:0] duty[NUMBER_OF_MOTORS-1:0]; 29 | reg [NUMBER_OF_MOTORS-1:0] ena; 30 | 31 | always @(posedge clock, posedge reset) begin: PWM_CONTROL_LOGIC 32 | if (reset == 1) begin 33 | for(i=0; i '0'); 42 | constant c1 : signed(nbits+2 downto 0) := to_signed(1, nbits+3); 43 | constant c_1 : signed(nbits+2 downto 0) := to_signed(-1, nbits+3); 44 | begin -- beh1 45 | 46 | process (clk, n_rst) 47 | begin -- process 48 | if n_rst = '0' then -- asynchronous reset (active low) 49 | del1 <= (others => '0'); 50 | del2 <= (others => '0'); 51 | dout <= '0'; 52 | elsif clk'event and clk = '1' then -- rising clock edge 53 | del1 <= din - d_q + del1; 54 | del2 <= din - d_q + del1 - d_q + del2; 55 | if din - d_q + del1 - d_q + del2 > 0 then 56 | d_q <= shift_left(c1, nbits); 57 | dout <= '1'; 58 | else 59 | d_q <= shift_left(c_1, nbits); 60 | dout <= '0'; 61 | end if; 62 | end if; 63 | end process; 64 | 65 | 66 | end beh1; 67 | -------------------------------------------------------------------------------- /roboy_fpga_code/sigma_delta_dac_dual_loop/trunk/dsm2/dac_dsm2_top.vhd: -------------------------------------------------------------------------------- 1 | ------------------------------------------------------------------------------- 2 | -- Title : DAC_DSM2 - sigma-delta DAC converter with double loop 3 | -- Project : 4 | ------------------------------------------------------------------------------- 5 | -- File : dac_dsm2.vhd 6 | -- Author : Wojciech M. Zabolotny ( wzab[at]ise.pw.edu.pl ) 7 | -- Company : 8 | -- Created : 2009-04-28 9 | -- Last update: 2012-10-16 10 | -- Platform : 11 | -- Standard : VHDL'93c 12 | ------------------------------------------------------------------------------- 13 | -- Description: Top entity 14 | ------------------------------------------------------------------------------- 15 | -- Copyright (c) 2009 - THIS IS PUBLIC DOMAIN CODE!!! 16 | ------------------------------------------------------------------------------- 17 | -- Revisions : 18 | -- Date Version Author Description 19 | -- 2009-04-28 1.0 wzab Created 20 | ------------------------------------------------------------------------------- 21 | 22 | library ieee; 23 | use ieee.std_logic_1164.all; 24 | use ieee.numeric_std.all; 25 | 26 | entity dac_dsm2_top is 27 | generic ( 28 | nbits : integer); 29 | port ( 30 | din : in signed(15 downto 0); 31 | dout : out std_logic; 32 | clk : in std_logic; 33 | n_rst : in std_logic); 34 | 35 | end dac_dsm2_top; 36 | 37 | architecture beh1 of dac_dsm2_top is 38 | 39 | component dac_dsm2 40 | generic ( 41 | nbits : integer); 42 | port ( 43 | din : in signed((nbits-1) downto 0); 44 | dout : out std_logic; 45 | clk : in std_logic; 46 | n_rst : in std_logic); 47 | end component; 48 | 49 | begin 50 | dac_dsm2_1 : dac_dsm2 51 | generic map ( 52 | nbits => nbits) 53 | port map ( 54 | din => din, 55 | dout => dout, 56 | clk => clk, 57 | n_rst => n_rst); 58 | end beh1; 59 | -------------------------------------------------------------------------------- /roboy_fpga_code/sigma_delta_dac_dual_loop/trunk/dsm2/dac_dsm2v.vhd: -------------------------------------------------------------------------------- 1 | ------------------------------------------------------------------------------- 2 | -- Title : DAC_DSM2 - sigma-delta DAC converter with double loop 3 | -- Project : 4 | ------------------------------------------------------------------------------- 5 | -- File : dac_dsm2.vhd 6 | -- Author : Wojciech M. Zabolotny ( wzab[at]ise.pw.edu.pl ) 7 | -- Company : 8 | -- Created : 2009-04-28 9 | -- Last update: 2009-04-29 10 | -- Platform : 11 | -- Standard : VHDL'93c 12 | ------------------------------------------------------------------------------- 13 | -- Description: Implementation with use of variables inside of process 14 | ------------------------------------------------------------------------------- 15 | -- Copyright (c) 2009 - THIS IS PUBLIC DOMAIN CODE!!! 16 | ------------------------------------------------------------------------------- 17 | -- Revisions : 18 | -- Date Version Author Description 19 | -- 2009-04-28 1.0 wzab Created 20 | ------------------------------------------------------------------------------- 21 | 22 | library ieee; 23 | use ieee.std_logic_1164.all; 24 | use ieee.numeric_std.all; 25 | 26 | entity dac_dsm2v is 27 | 28 | generic ( 29 | nbits : integer := 16); 30 | 31 | port ( 32 | din : in signed((nbits-1) downto 0); 33 | dout : out std_logic; 34 | clk : in std_logic; 35 | n_rst : in std_logic); 36 | 37 | end dac_dsm2v; 38 | 39 | architecture beh1 of dac_dsm2v is 40 | 41 | signal del1, del2, d_q : signed(nbits+2 downto 0) := (others => '0'); 42 | constant c1 : signed(nbits+2 downto 0) := to_signed(1, nbits+3); 43 | constant c_1 : signed(nbits+2 downto 0) := to_signed(-1, nbits+3); 44 | begin -- beh1 45 | 46 | process (clk, n_rst) 47 | variable v1, v2 : signed(nbits+2 downto 0) := (others => '0'); 48 | begin -- process 49 | if n_rst = '0' then -- asynchronous reset (active low) 50 | del1 <= (others => '0'); 51 | del2 <= (others => '0'); 52 | dout <= '0'; 53 | elsif clk'event and clk = '1' then -- rising clock edge 54 | v1 := din - d_q + del1; 55 | v2 := v1 - d_q + del2; 56 | if v2 > 0 then 57 | d_q <= shift_left(c1, nbits); 58 | dout <= '1'; 59 | else 60 | d_q <= shift_left(c_1, nbits); 61 | dout <= '0'; 62 | end if; 63 | del1 <= v1; 64 | del2 <= v2; 65 | end if; 66 | end process; 67 | 68 | 69 | end beh1; 70 | -------------------------------------------------------------------------------- /roboy_fpga_code/sigma_delta_dac_dual_loop/trunk/dsm2/dac_tb.vhd: -------------------------------------------------------------------------------- 1 | ------------------------------------------------------------------------------- 2 | -- Title : Testbench for design "dac_dsm2" 3 | -- Project : 4 | ------------------------------------------------------------------------------- 5 | -- File : dac_dsm2_tb.vhd 6 | -- Author : Wojciech M. Zabolotny ( wzab[at]ise.pw.edu.pl ) 7 | -- Company : 8 | -- Created : 2009-04-28 9 | -- Last update: 2012-10-16 10 | -- Platform : 11 | -- Standard : VHDL'93c 12 | ------------------------------------------------------------------------------- 13 | -- Description: Testbench for S-D DAC converters 14 | ------------------------------------------------------------------------------- 15 | -- Copyright (c) 2009 - THIS IS PUBLIC DOMAIN CODE!!! 16 | ------------------------------------------------------------------------------- 17 | -- Revisions : 18 | -- Date Version Author Description 19 | -- 2009-04-28 1.0 wzab Created 20 | ------------------------------------------------------------------------------- 21 | 22 | library ieee; 23 | use ieee.std_logic_1164.all; 24 | use ieee.numeric_std.all; 25 | use ieee.math_real.all; 26 | use std.textio.all; 27 | 28 | ------------------------------------------------------------------------------- 29 | 30 | entity dac_tb is 31 | 32 | end dac_tb; 33 | 34 | ------------------------------------------------------------------------------- 35 | 36 | architecture beh1 of dac_tb is 37 | 38 | -- Configuration of the testbench 39 | -- Clock period [ns] 40 | constant TCLK : time := 10 ns; 41 | constant OSR : real := 256.0; -- Oversampling ratio: 42 | 43 | constant FREQ1 : real := 0.35; -- Frequency of the first sinusoid (relative to the sampling frequency) 44 | constant AMP1 : real := 0.2; -- Amplitude of the first sinusoid 45 | constant PHASE1 : real := 0.35; -- Phase of the first sinusoid 46 | constant FREQ2 : real := 0.3; -- Frequency of the second sinusoid (relative to the sampling frequency) 47 | constant AMP2 : real := 0.4; -- Amplitude of the second sinusoid 48 | constant PHASE2 : real := 0.35; -- Phase of the second sinusoid 49 | constant FREQ3 : real := 0.25; -- Frequency of the third sinusoid (relative to the sampling frequency) 50 | constant AMP3 : real := 0.3; -- Amplitude of the third sinusoid 51 | constant PHASE3 : real := 0.35; -- Phase of the third sinusoid 52 | constant TSTEP : real := 3.1415926 / OSR; -- Phase/time step of the sinusoid generation (considering the OSR) 53 | 54 | file OUTFILE : text is out "dac_tb.dat"; 55 | 56 | component dac_dsm2_top 57 | generic ( 58 | nbits : integer); 59 | port ( 60 | din : in signed((nbits-1) downto 0); 61 | dout : out std_logic; 62 | clk : in std_logic; 63 | n_rst : in std_logic); 64 | end component; 65 | 66 | -- component generics 67 | constant nbits : integer := 16; 68 | 69 | -- component ports 70 | signal din : signed((nbits-1) downto 0) := (others => '0'); 71 | signal dout : std_logic := '0'; 72 | signal n_rst : std_logic := '0'; 73 | 74 | -- input signal 75 | signal s_inp : real := 0.0; 76 | signal s_time : real := 0.0; 77 | -- clock 78 | signal Clk : std_logic := '1'; 79 | 80 | begin -- beh1 81 | 82 | -- component instantiation 83 | DUT1 : dac_dsm2_top 84 | generic map ( 85 | nbits => nbits) 86 | port map ( 87 | din => din, 88 | dout => dout, 89 | clk => clk, 90 | n_rst => n_rst); 91 | 92 | -- clock generation 93 | Clk <= not Clk after TCLK/2.0; 94 | 95 | -- Generation of input signal and simulation of DACs 96 | din <= to_signed(integer(s_inp), nbits); 97 | process (clk, n_rst) 98 | variable s : line; 99 | variable c : character := ' '; 100 | variable c1 : character := '1'; 101 | variable c0 : character := '0'; 102 | begin -- process 103 | if n_rst = '0' then -- asynchronous reset (active low) 104 | s_time <= 0.0; 105 | elsif clk'event and clk = '1' then -- rising clock edge 106 | s_time <= s_time+TSTEP; 107 | s_inp <= (2.0**(nbits-1))*( 108 | AMP1 * sin(s_time*FREQ1+PHASE1) + 109 | AMP2 * sin(s_time*FREQ2+PHASE2) + 110 | AMP3 * sin(s_time*FREQ3+PHASE3) 111 | ); 112 | -- Write results to file 113 | write(s, s_inp); 114 | write(s, c); 115 | 116 | if dout = '1' then 117 | write(s, c1); 118 | else 119 | write(s, c0); 120 | end if; 121 | writeline(OUTFILE, s); 122 | end if; 123 | end process; 124 | 125 | -- waveform generation 126 | WaveGen_Proc : process 127 | begin 128 | -- insert signal assignments here 129 | wait until Clk = '1'; 130 | wait for 25 ns; 131 | n_rst <= '1'; 132 | end process WaveGen_Proc; 133 | 134 | end beh1; 135 | 136 | 137 | -------------------------------------------------------------------------------- /roboy_fpga_code/sigma_delta_dac_dual_loop/trunk/dsm2/makefile: -------------------------------------------------------------------------------- 1 | VHDLS = \ 2 | dac_dsm2.vhd \ 3 | dac_dsm2v.vhd \ 4 | dac_dsm2_top.vhd \ 5 | dac_tb.vhd \ 6 | 7 | 8 | STD=standard 9 | #STD=synopsys 10 | show_spectra: dac_tb.dat 11 | python show_dac.py 12 | show_ghw: dac_tb dac_tb.ghw 13 | gtkwave dac_tb.ghw wzrmb.sav 14 | dac_tb: ${VHDLS} 15 | ghdl -a --std=93c --ieee=${STD} ${VHDLS} 16 | ghdl -e --std=93c -fexplicit --ieee=${STD} dac_tb 17 | dac_tb.dat: dac_tb 18 | ./dac_tb --wave=dac_tb.ghw --stop-time=2000000ns 19 | dac_tb.ghw: dac_tb 20 | ./dac_tb --wave=dac_tb.ghw --stop-time=2000000ns 21 | clean: 22 | rm *.o *.vcd *.ghw *.dat *.cf dac_tb 23 | -------------------------------------------------------------------------------- /roboy_fpga_code/sigma_delta_dac_dual_loop/trunk/dsm2/show_dac.py: -------------------------------------------------------------------------------- 1 | import pylab 2 | #w=load("dac_tb.dat") 3 | import numpy 4 | w=numpy.loadtxt("dac_tb.dat") 5 | t1=[i[1] for i in w]; t1=t1-pylab.mean(t1) 6 | f1=20.0*pylab.log(0.0001+abs(pylab.fft(t1))) 7 | pylab.plot(f1) 8 | pylab.title("Whole spectra of output signal") 9 | pylab.grid() 10 | pylab.show() 11 | pylab.plot(f1[0:1000]) 12 | pylab.title("First 1000 samples of spectra") 13 | pylab.grid() 14 | pylab.show() 15 | -------------------------------------------------------------------------------- /roboy_fpga_code/sigma_delta_dac_dual_loop/trunk/dsm2/work-obj93.cf: -------------------------------------------------------------------------------- 1 | v 4 2 | file . "dac_tb.vhd" "b1eb92910415672a695922204b563e33fa44bd94" "20200119131153.521": 3 | entity dac_tb at 22( 959) + 0 on 17; 4 | architecture beh1 of dac_tb at 36( 1266) + 0 on 18; 5 | file . "dac_dsm2_top.vhd" "a14ac3d73d9c07a827b8eb42abd1ce3a892535e2" "20200119131153.517": 6 | entity dac_dsm2_top at 22( 956) + 0 on 15; 7 | architecture beh1 of dac_dsm2_top at 37( 1237) + 0 on 16; 8 | file . "dac_dsm2v.vhd" "cd2e373cc1400f3f397ba9c071f9ab0e56d5a935" "20200119131153.516": 9 | entity dac_dsm2v at 22( 1000) + 0 on 13; 10 | architecture beh1 of dac_dsm2v at 39( 1286) + 0 on 14; 11 | file . "dac_dsm2.vhd" "c904a204a097051edd61ff82f94f4f6bdf5b2af2" "20200119131153.514": 12 | entity dac_dsm2 at 22( 977) + 0 on 11; 13 | architecture beh1 of dac_dsm2 at 39( 1261) + 0 on 12; 14 | -------------------------------------------------------------------------------- /roboy_fpga_code/sigma_delta_dac_dual_loop/trunk/dsm3/dac_dsm3.vhd: -------------------------------------------------------------------------------- 1 | ------------------------------------------------------------------------------- 2 | -- Title : DAC_DSM2 - sigma-delta DAC converter with double loop 3 | -- Project : 4 | ------------------------------------------------------------------------------- 5 | -- File : dac_dsm2.vhd 6 | -- Author : Wojciech M. Zabolotny ( wzab[at]ise.pw.edu.pl ) 7 | -- Company : 8 | -- Created : 2009-04-28 9 | -- Last update: 2012-10-16 10 | -- Platform : 11 | -- Standard : VHDL'93c 12 | ------------------------------------------------------------------------------- 13 | -- Description: Implementation without variables 14 | ------------------------------------------------------------------------------- 15 | -- Copyright (c) 2009 - THIS IS PUBLIC DOMAIN CODE!!! 16 | ------------------------------------------------------------------------------- 17 | -- Revisions : 18 | -- Date Version Author Description 19 | -- 2009-04-28 1.0 wzab Created 20 | ------------------------------------------------------------------------------- 21 | 22 | library ieee; 23 | use ieee.std_logic_1164.all; 24 | use ieee.numeric_std.all; 25 | 26 | entity dac_dsm3 is 27 | 28 | generic ( 29 | nbits : integer := 16); 30 | 31 | port ( 32 | din : in signed((nbits-1) downto 0); 33 | dout : out std_logic; 34 | clk : in std_logic; 35 | clk_ena : in std_logic; 36 | n_rst : in std_logic); 37 | 38 | end dac_dsm3; 39 | 40 | architecture beh1 of dac_dsm3 is 41 | 42 | signal del1, del2, d_q : signed(nbits+2 downto 0) := (others => '0'); 43 | constant c1 : signed(nbits+2 downto 0) := to_signed(1, nbits+3); 44 | constant c_1 : signed(nbits+2 downto 0) := to_signed(-1, nbits+3); 45 | begin -- beh1 46 | 47 | process (clk, n_rst) 48 | begin -- process 49 | if n_rst = '0' then -- asynchronous reset (active low) 50 | del1 <= (others => '0'); 51 | del2 <= (others => '0'); 52 | dout <= '0'; 53 | elsif clk'event and clk = '1' then -- rising clock edge 54 | if clk_ena = '1' then 55 | del1 <= din - d_q + del1; 56 | del2 <= din - d_q + del1 - d_q + del2; 57 | if din - d_q + del1 - d_q + del2 > 0 then 58 | d_q <= shift_left(c1, nbits); 59 | dout <= '1'; 60 | else 61 | d_q <= shift_left(c_1, nbits); 62 | dout <= '0'; 63 | end if; 64 | end if; 65 | end if; 66 | end process; 67 | 68 | 69 | end beh1; 70 | -------------------------------------------------------------------------------- /roboy_fpga_code/sigma_delta_dac_dual_loop/trunk/dsm3/dac_dsm3_top.vhd: -------------------------------------------------------------------------------- 1 | ------------------------------------------------------------------------------- 2 | -- Title : DAC_DSM2 - sigma-delta DAC converter with double loop 3 | -- Project : 4 | ------------------------------------------------------------------------------- 5 | -- File : dac_dsm2.vhd 6 | -- Author : Wojciech M. Zabolotny ( wzab[at]ise.pw.edu.pl ) 7 | -- Company : 8 | -- Created : 2009-04-28 9 | -- Last update: 2012-10-16 10 | -- Platform : 11 | -- Standard : VHDL'93c 12 | ------------------------------------------------------------------------------- 13 | -- Description: Top entity - contains DAC and output circuit 14 | -- generating the 3-bit sequences 15 | ------------------------------------------------------------------------------- 16 | -- Copyright (c) 2009 - THIS IS PUBLIC DOMAIN CODE!!! 17 | ------------------------------------------------------------------------------- 18 | -- Revisions : 19 | -- Date Version Author Description 20 | -- 2009-04-28 1.0 wzab Created 21 | ------------------------------------------------------------------------------- 22 | 23 | library ieee; 24 | use ieee.std_logic_1164.all; 25 | use ieee.numeric_std.all; 26 | 27 | entity dac_dsm3_top is 28 | generic ( 29 | nbits : integer); 30 | port ( 31 | din : in signed(15 downto 0); 32 | dout : out std_logic; 33 | clk : in std_logic; 34 | n_rst : in std_logic); 35 | 36 | end dac_dsm3_top; 37 | 38 | architecture beh1 of dac_dsm3_top is 39 | 40 | component dac_dsm3 41 | generic ( 42 | nbits : integer); 43 | port ( 44 | din : in signed((nbits-1) downto 0); 45 | dout : out std_logic; 46 | clk : in std_logic; 47 | clk_ena : in std_logic; 48 | n_rst : in std_logic); 49 | end component; 50 | 51 | signal clk_cnt : integer range 0 to 2 := 0; 52 | signal clk_ena : std_logic := '0'; 53 | signal dac_dout : std_logic := '0'; 54 | 55 | begin 56 | -- The clock cycle counter 57 | clken1 : process (clk, n_rst) 58 | begin -- process 59 | if n_rst = '0' then -- asynchronous reset (active low) 60 | clk_cnt <= 0; 61 | elsif clk'event and clk = '1' then -- rising clock edge 62 | -- Update the cycle counter 63 | if clk_cnt < 2 then 64 | clk_cnt <= clk_cnt + 1; 65 | else 66 | clk_cnt <= 0; 67 | end if; 68 | -- Generate the clk_ena only in the first cycle 69 | if clk_cnt = 2 then 70 | clk_ena <= '1'; 71 | else 72 | clk_ena <= '0'; 73 | end if; 74 | -- Generate the narrow (if dac_dout='0') or wide (if dac_output='1') 75 | -- output pulse 76 | if clk_cnt = 0 then 77 | dout <= '1'; -- always the rising slope after the first 78 | -- clock cycle 79 | elsif (clk_cnt = 1) and (dac_dout = '0') then 80 | dout <= '0'; -- short dout pulse when dac_dout = '0' 81 | elsif clk_cnt = 2 then 82 | dout <= '0'; -- always the falling slope after the 83 | -- third cycle 84 | end if; 85 | end if; 86 | end process clken1; 87 | 88 | dac_dsm3_1 : dac_dsm3 89 | generic map ( 90 | nbits => 16) 91 | port map ( 92 | din => din, 93 | dout => dout, 94 | clk => clk, 95 | clk_ena => clk_ena, 96 | n_rst => n_rst); 97 | end beh1; 98 | -------------------------------------------------------------------------------- /roboy_fpga_code/sigma_delta_dac_dual_loop/trunk/dsm3/dac_dsm3v.vhd: -------------------------------------------------------------------------------- 1 | ------------------------------------------------------------------------------- 2 | -- Title : DAC_DSM3 - sigma-delta DAC converter with double loop 3 | -- Project : 4 | ------------------------------------------------------------------------------- 5 | -- File : dac_dsm2.vhd 6 | -- Author : Wojciech M. Zabolotny ( wzab[at]ise.pw.edu.pl ) 7 | -- Company : 8 | -- Created : 2009-04-28 9 | -- Last update: 2012-10-16 10 | -- Platform : 11 | -- Standard : VHDL'93c 12 | ------------------------------------------------------------------------------- 13 | -- Description: Implementation with use of variables inside of process 14 | -- : and with one rising and falling slope for each output cycle 15 | ------------------------------------------------------------------------------- 16 | -- Copyright (c) 2009 - THIS IS PUBLIC DOMAIN CODE!!! 17 | ------------------------------------------------------------------------------- 18 | -- Revisions : 19 | -- Date Version Author Description 20 | -- 2009-04-28 1.0 wzab Created 21 | ------------------------------------------------------------------------------- 22 | 23 | library ieee; 24 | use ieee.std_logic_1164.all; 25 | use ieee.numeric_std.all; 26 | 27 | entity dac_dsm3v is 28 | 29 | generic ( 30 | nbits : integer := 16); 31 | 32 | port ( 33 | din : in signed((nbits-1) downto 0); 34 | dout : out std_logic; 35 | clk : in std_logic; 36 | clk_ena : in std_logic; 37 | n_rst : in std_logic); 38 | 39 | end dac_dsm3v; 40 | 41 | architecture beh1 of dac_dsm3v is 42 | 43 | signal del1, del2, d_q : signed(nbits+2 downto 0) := (others => '0'); 44 | constant c1 : signed(nbits+2 downto 0) := to_signed(1, nbits+3); 45 | constant c_1 : signed(nbits+2 downto 0) := to_signed(-1, nbits+3); 46 | begin -- beh1 47 | 48 | process (clk, n_rst) 49 | variable v1, v2 : signed(nbits+2 downto 0) := (others => '0'); 50 | begin -- process 51 | if n_rst = '0' then -- asynchronous reset (active low) 52 | del1 <= (others => '0'); 53 | del2 <= (others => '0'); 54 | dout <= '0'; 55 | elsif clk'event and clk = '1' then -- rising clock edge 56 | if clk_ena = '1' then 57 | v1 := din - d_q + del1; 58 | v2 := v1 - d_q + del2; 59 | if v2 > 0 then 60 | d_q <= shift_left(c1, nbits); 61 | dout <= '1'; 62 | else 63 | d_q <= shift_left(c_1, nbits); 64 | dout <= '0'; 65 | end if; 66 | del1 <= v1; 67 | del2 <= v2; 68 | end if; 69 | end if; 70 | end process; 71 | 72 | 73 | end beh1; 74 | -------------------------------------------------------------------------------- /roboy_fpga_code/sigma_delta_dac_dual_loop/trunk/dsm3/dac_tb.vhd: -------------------------------------------------------------------------------- 1 | ------------------------------------------------------------------------------- 2 | -- Title : Testbench for design "dac_dsm2" 3 | -- Project : 4 | ------------------------------------------------------------------------------- 5 | -- File : dac_dsm2_tb.vhd 6 | -- Author : Wojciech M. Zabolotny ( wzab[at]ise.pw.edu.pl ) 7 | -- Company : 8 | -- Created : 2009-04-28 9 | -- Last update: 2012-10-16 10 | -- Platform : 11 | -- Standard : VHDL'93c 12 | ------------------------------------------------------------------------------- 13 | -- Description: Testbench for S-D DAC converters 14 | ------------------------------------------------------------------------------- 15 | -- Copyright (c) 2009 - THIS IS PUBLIC DOMAIN CODE!!! 16 | ------------------------------------------------------------------------------- 17 | -- Revisions : 18 | -- Date Version Author Description 19 | -- 2009-04-28 1.0 wzab Created 20 | ------------------------------------------------------------------------------- 21 | 22 | library ieee; 23 | use ieee.std_logic_1164.all; 24 | use ieee.numeric_std.all; 25 | use ieee.math_real.all; 26 | use std.textio.all; 27 | 28 | ------------------------------------------------------------------------------- 29 | 30 | entity dac_tb is 31 | 32 | end dac_tb; 33 | 34 | ------------------------------------------------------------------------------- 35 | 36 | architecture beh1 of dac_tb is 37 | 38 | -- Configuration of the testbench 39 | -- Clock period [ns] 40 | constant TCLK : time := 10 ns; 41 | constant OSR : real := 256.0; -- Oversampling ratio: 42 | 43 | constant FREQ1 : real := 0.35; -- Frequency of the first sinusoid (relative to the sampling frequency) 44 | constant AMP1 : real := 0.2; -- Amplitude of the first sinusoid 45 | constant PHASE1 : real := 0.35; -- Phase of the first sinusoid 46 | constant FREQ2 : real := 0.3; -- Frequency of the second sinusoid (relative to the sampling frequency) 47 | constant AMP2 : real := 0.4; -- Amplitude of the second sinusoid 48 | constant PHASE2 : real := 0.35; -- Phase of the second sinusoid 49 | constant FREQ3 : real := 0.25; -- Frequency of the third sinusoid (relative to the sampling frequency) 50 | constant AMP3 : real := 0.3; -- Amplitude of the third sinusoid 51 | constant PHASE3 : real := 0.35; -- Phase of the third sinusoid 52 | constant TSTEP : real := 3.1415926 / OSR; -- Phase/time step of the sinusoid generation (considering the OSR) 53 | 54 | file OUTFILE : text is out "dac_tb.dat"; 55 | 56 | component dac_dsm3_top 57 | generic ( 58 | nbits : integer); 59 | port ( 60 | din : in signed((nbits-1) downto 0); 61 | dout : out std_logic; 62 | clk : in std_logic; 63 | n_rst : in std_logic); 64 | end component; 65 | 66 | -- component generics 67 | constant nbits : integer := 16; 68 | 69 | -- component ports 70 | signal din : signed((nbits-1) downto 0) := (others => '0'); 71 | signal dout : std_logic := '0'; 72 | signal n_rst : std_logic := '0'; 73 | 74 | -- input signal 75 | signal s_inp : real := 0.0; 76 | signal s_time : real := 0.0; 77 | -- clock 78 | signal Clk : std_logic := '1'; 79 | 80 | begin -- beh1 81 | 82 | -- component instantiation 83 | DUT1 : dac_dsm3_top 84 | generic map ( 85 | nbits => nbits) 86 | port map ( 87 | din => din, 88 | dout => dout, 89 | clk => clk, 90 | n_rst => n_rst); 91 | 92 | -- clock generation 93 | Clk <= not Clk after TCLK/2.0; 94 | 95 | -- Generation of input signal and simulation of DACs 96 | din <= to_signed(integer(s_inp), nbits); 97 | process (clk, n_rst) 98 | variable s : line; 99 | variable c : character := ' '; 100 | variable c1 : character := '1'; 101 | variable c0 : character := '0'; 102 | begin -- process 103 | if n_rst = '0' then -- asynchronous reset (active low) 104 | s_time <= 0.0; 105 | elsif clk'event and clk = '1' then -- rising clock edge 106 | s_time <= s_time+TSTEP; 107 | s_inp <= (2.0**(nbits-1))*( 108 | AMP1 * sin(s_time*FREQ1+PHASE1) + 109 | AMP2 * sin(s_time*FREQ2+PHASE2) + 110 | AMP3 * sin(s_time*FREQ3+PHASE3) 111 | ); 112 | -- Write results to file 113 | write(s, s_inp); 114 | write(s, c); 115 | 116 | if dout = '1' then 117 | write(s, c1); 118 | else 119 | write(s, c0); 120 | end if; 121 | writeline(OUTFILE, s); 122 | end if; 123 | end process; 124 | 125 | -- waveform generation 126 | WaveGen_Proc : process 127 | begin 128 | -- insert signal assignments here 129 | wait until Clk = '1'; 130 | wait for 25 ns; 131 | n_rst <= '1'; 132 | end process WaveGen_Proc; 133 | 134 | end beh1; 135 | 136 | 137 | -------------------------------------------------------------------------------- /roboy_fpga_code/sigma_delta_dac_dual_loop/trunk/dsm3/makefile: -------------------------------------------------------------------------------- 1 | VHDLS = \ 2 | dac_dsm3.vhd \ 3 | dac_dsm3v.vhd \ 4 | dac_dsm3_top.vhd \ 5 | dac_tb.vhd \ 6 | 7 | 8 | STD=standard 9 | #STD=synopsys 10 | show_spectra: dac_tb.dat 11 | python show_dac.py 12 | show_ghw: dac_tb dac_tb.ghw 13 | gtkwave dac_tb.ghw wzrmb.sav 14 | dac_tb: ${VHDLS} 15 | ghdl -a -g --std=93c --ieee=${STD} ${VHDLS} 16 | ghdl -e --std=93c -fexplicit --ieee=${STD} dac_tb 17 | dac_tb.dat: dac_tb 18 | ./dac_tb --wave=dac_tb.ghw --stop-time=2000000ns 19 | dac_tb.ghw: dac_tb 20 | ./dac_tb --wave=dac_tb.ghw --stop-time=2000000ns 21 | clean: 22 | rm *.o *.vcd *.ghw *.dat *.cf dac_tb 23 | -------------------------------------------------------------------------------- /roboy_fpga_code/sigma_delta_dac_dual_loop/trunk/dsm3/show_dac.py: -------------------------------------------------------------------------------- 1 | import pylab 2 | #w=load("dac_tb.dat") 3 | import numpy 4 | w=numpy.loadtxt("dac_tb.dat") 5 | t1=[i[1] for i in w]; t1=t1-pylab.mean(t1) 6 | f1=20.0*pylab.log(0.0001+abs(pylab.fft(t1))) 7 | pylab.plot(f1) 8 | pylab.title("Whole spectra of output signal") 9 | pylab.grid() 10 | pylab.show() 11 | pylab.plot(f1[0:1000]) 12 | pylab.title("First 1000 samples of spectra") 13 | pylab.grid() 14 | pylab.show() 15 | -------------------------------------------------------------------------------- /roboy_fpga_code/tli4970/tli4970.sv: -------------------------------------------------------------------------------- 1 | // BSD 3-Clause License 2 | // 3 | // Copyright (c) 2019, Roboy 4 | // All rights reserved. 5 | // 6 | // Redistribution and use in source and binary forms, with or without 7 | // modification, are permitted provided that the following conditions are met: 8 | // 9 | // * Redistributions of source code must retain the above copyright notice, this 10 | // list of conditions and the following disclaimer. 11 | // 12 | // * Redistributions in binary form must reproduce the above copyright notice, 13 | // this list of conditions and the following disclaimer in the documentation 14 | // and/or other materials provided with the distribution. 15 | // 16 | // * Neither the name of the copyright holder nor the names of its 17 | // contributors may be used to endorse or promote products derived from 18 | // this software without specific prior written permission. 19 | // 20 | // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 | // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 | // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 23 | // DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 24 | // FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 | // DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 26 | // SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 27 | // CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 28 | // OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 29 | // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 | 31 | // author: Simon Trendel, simon.trendel@tum.de, 19 32 | 33 | `timescale 1ns/10ps 34 | 35 | module TLI4970 ( 36 | input clock, 37 | input reset, 38 | // this is for the avalon interface 39 | input [7:0] address, 40 | input write, 41 | input signed [31:0] writedata, 42 | input read, 43 | output signed [31:0] readdata, 44 | output waitrequest, 45 | // these are the spi ports 46 | output [NUMBER_OF_SENSORS-1:0] ss_n_o, 47 | input miso, 48 | output sck 49 | ); 50 | 51 | parameter NUMBER_OF_SENSORS = 2; 52 | parameter CLOCK_SPEED_HZ = 50_000_000; 53 | parameter UPDATE_FREQUENCY = 1_000; 54 | 55 | assign readdata = returnvalue; 56 | assign waitrequest = (waitFlag && read) || (ss_n==0 && address==current_sensor); 57 | reg [31:0] returnvalue; 58 | reg waitFlag; 59 | 60 | reg [31:0] update_frequency; 61 | reg [31:0] actual_update_frequency; 62 | reg [31:0] delay_counter; 63 | 64 | reg signed [31:0] current_raw[NUMBER_OF_SENSORS-1:0]; 65 | 66 | always @(posedge clock, posedge reset) begin: AVALON_READ_INTERFACE 67 | if (reset == 1) begin 68 | waitFlag <= 1; 69 | end else begin 70 | waitFlag <= 1; 71 | if(read) begin 72 | if(addressCLOCK_DIVIDER)begin 25 | clk_slow <= !clk_slow; 26 | counter <= 0; 27 | end 28 | end 29 | 30 | reg clk_out; 31 | reg slave_select; 32 | assign spi_clk = (slave_select?1:clk_slow)&clk_out; 33 | 34 | genvar j; 35 | generate 36 | for(j=0; j(CLOCK_FREQ/CLOCK_DIVIDER/UPDATE_FREQ/NUMBER_OF_SENSORS))begin 54 | state <= SLAVE_SELECT; 55 | delay_counter <= 0; 56 | end else begin 57 | delay_counter <= delay_counter+1; 58 | end 59 | 60 | case(state) 61 | IDLE: begin 62 | slave_select <= 1; 63 | end 64 | SLAVE_SELECT: begin 65 | if(current_sensor<(NUMBER_OF_SENSORS-1))begin 66 | current_sensor <= current_sensor+1; 67 | end else begin 68 | current_sensor <= 0; 69 | end 70 | slave_select <= 0; 71 | clk_out <= 1; 72 | state <= CLOCK_DATA; 73 | bit_counter <= 15; 74 | end 75 | CLOCK_DATA: begin 76 | data[bit_counter] <= spi_miso; 77 | bit_counter <= bit_counter - 1; 78 | if(bit_counter==0)begin 79 | state <= STOP; 80 | clk_out <= 0; 81 | end 82 | end 83 | STOP: begin 84 | if(data[15]==0)begin 85 | current[current_sensor] <= current_raw-16'd4096; 86 | end 87 | state <= IDLE; 88 | end 89 | endcase 90 | end 91 | 92 | endmodule 93 | -------------------------------------------------------------------------------- /roboy_fpga_code/uart/uart_rx.v: -------------------------------------------------------------------------------- 1 | ////////////////////////////////////////////////////////////////////// 2 | // File Downloaded from http://www.nandland.com 3 | ////////////////////////////////////////////////////////////////////// 4 | // This file contains the UART Receiver. This receiver is able to 5 | // receive 8 bits of serial data, one start bit, one stop bit, 6 | // and no parity bit. When receive is complete o_rx_dv will be 7 | // driven high for one clock cycle. 8 | // 9 | // Set Parameter CLKS_PER_BIT as follows: 10 | // CLKS_PER_BIT = (Frequency of i_Clock)/(Frequency of UART) 11 | // Example: 10 MHz Clock, 115200 baud UART 12 | // (10000000)/(115200) = 87 13 | 14 | module uart_rx #(parameter CLK_FREQ_HZ = 48_000_000) 15 | ( 16 | input i_Clock, 17 | input [31:0] baudrate, 18 | input i_Rx_Serial, 19 | output o_Rx_DV, 20 | output [7:0] o_Rx_Byte 21 | ); 22 | 23 | // localparam CLKS_PER_BIT = CLK_FREQ_HZ/BAUDRATE; // 139 at 16MHz this is 115200 baudrate, 64 at 16MHz is 250000 24 | localparam s_IDLE = 3'b000; 25 | localparam s_RX_START_BIT = 3'b001; 26 | localparam s_RX_DATA_BITS = 3'b010; 27 | localparam s_RX_STOP_BIT = 3'b011; 28 | localparam s_CLEANUP = 3'b100; 29 | 30 | reg r_Rx_Data_R = 1'b1; 31 | reg r_Rx_Data = 1'b1; 32 | 33 | reg [15:0] r_Clock_Count = 0; 34 | reg [2:0] r_Bit_Index = 0; //8 bits total 35 | reg [7:0] r_Rx_Byte = 0; 36 | reg r_Rx_DV = 0; 37 | reg [2:0] r_SM_Main = 0; 38 | 39 | // Purpose: Double-register the incoming data. 40 | // This allows it to be used in the UART RX Clock Domain. 41 | // (It removes problems caused by metastability) 42 | always @(posedge i_Clock) 43 | begin 44 | r_Rx_Data_R <= i_Rx_Serial; 45 | r_Rx_Data <= r_Rx_Data_R; 46 | end 47 | 48 | 49 | // Purpose: Control RX state machine 50 | always @(posedge i_Clock) 51 | begin 52 | 53 | case (r_SM_Main) 54 | s_IDLE : 55 | begin 56 | r_Rx_DV <= 1'b0; 57 | r_Clock_Count <= 0; 58 | r_Bit_Index <= 0; 59 | 60 | if (r_Rx_Data == 1'b0) // Start bit detected 61 | r_SM_Main <= s_RX_START_BIT; 62 | else 63 | r_SM_Main <= s_IDLE; 64 | end 65 | 66 | // Check middle of start bit to make sure it's still low 67 | s_RX_START_BIT : 68 | begin 69 | if (r_Clock_Count == ((CLK_FREQ_HZ/baudrate)-1)/2) 70 | begin 71 | if (r_Rx_Data == 1'b0) 72 | begin 73 | r_Clock_Count <= 0; // reset counter, found the middle 74 | r_SM_Main <= s_RX_DATA_BITS; 75 | end 76 | else 77 | r_SM_Main <= s_IDLE; 78 | end 79 | else 80 | begin 81 | r_Clock_Count <= r_Clock_Count + 1; 82 | r_SM_Main <= s_RX_START_BIT; 83 | end 84 | end // case: s_RX_START_BIT 85 | 86 | 87 | // Wait CLKS_PER_BIT-1 clock cycles to sample serial data 88 | s_RX_DATA_BITS : 89 | begin 90 | if (r_Clock_Count < (CLK_FREQ_HZ/baudrate)-1) 91 | begin 92 | r_Clock_Count <= r_Clock_Count + 1; 93 | r_SM_Main <= s_RX_DATA_BITS; 94 | end 95 | else 96 | begin 97 | r_Clock_Count <= 0; 98 | r_Rx_Byte[r_Bit_Index] <= r_Rx_Data; 99 | 100 | // Check if we have received all bits 101 | if (r_Bit_Index < 7) 102 | begin 103 | r_Bit_Index <= r_Bit_Index + 1; 104 | r_SM_Main <= s_RX_DATA_BITS; 105 | end 106 | else 107 | begin 108 | r_Bit_Index <= 0; 109 | r_SM_Main <= s_RX_STOP_BIT; 110 | end 111 | end 112 | end // case: s_RX_DATA_BITS 113 | 114 | 115 | // Receive Stop bit. Stop bit = 1 116 | s_RX_STOP_BIT : 117 | begin 118 | // Wait CLKS_PER_BIT-1 clock cycles for Stop bit to finish 119 | if (r_Clock_Count < (CLK_FREQ_HZ/baudrate)-1) 120 | begin 121 | r_Clock_Count <= r_Clock_Count + 1; 122 | r_SM_Main <= s_RX_STOP_BIT; 123 | end 124 | else 125 | begin 126 | r_Rx_DV <= 1'b1; 127 | r_Clock_Count <= 0; 128 | r_SM_Main <= s_CLEANUP; 129 | end 130 | end // case: s_RX_STOP_BIT 131 | 132 | 133 | // Stay here 1 clock 134 | s_CLEANUP : 135 | begin 136 | r_SM_Main <= s_IDLE; 137 | r_Rx_DV <= 1'b0; 138 | end 139 | 140 | 141 | default : 142 | r_SM_Main <= s_IDLE; 143 | 144 | endcase 145 | end 146 | 147 | assign o_Rx_DV = r_Rx_DV; 148 | assign o_Rx_Byte = r_Rx_Byte; 149 | 150 | endmodule // uart_rx 151 | -------------------------------------------------------------------------------- /roboy_fpga_code/uart/uart_tx.v: -------------------------------------------------------------------------------- 1 | ////////////////////////////////////////////////////////////////////// 2 | // File Downloaded from http://www.nandland.com 3 | ////////////////////////////////////////////////////////////////////// 4 | // This file contains the UART Transmitter. This transmitter is able 5 | // to transmit 8 bits of serial data, one start bit, one stop bit, 6 | // and no parity bit. When transmit is complete o_Tx_done will be 7 | // driven high for one clock cycle. 8 | // 9 | // Set Parameter CLKS_PER_BIT as follows: 10 | // CLKS_PER_BIT = (Frequency of i_Clock)/(Frequency of UART) 11 | // Example: 10 MHz Clock, 115200 baud UART 12 | // (10000000)/(115200) = 87 13 | 14 | module uart_tx #(parameter CLK_FREQ_HZ = 48_000_000) 15 | ( 16 | input i_Clock, 17 | input [31:0] baudrate, 18 | input i_Tx_DV, 19 | input [7:0] i_Tx_Byte, 20 | output o_Tx_Active, 21 | output reg o_Tx_Serial, 22 | output o_Tx_Enable, 23 | output o_Tx_Done 24 | ); 25 | // localparam CLKS_PER_BIT = CLK_FREQ_HZ/BAUDRATE; // 139 at 16MHz this is 115200 baudrate, 64 at 16MHz is 250000 26 | localparam s_IDLE = 3'b000; 27 | localparam s_TX_START_BIT = 3'b001; 28 | localparam s_TX_DATA_BITS = 3'b010; 29 | localparam s_TX_STOP_BIT = 3'b011; 30 | localparam s_CLEANUP = 3'b100; 31 | 32 | reg [2:0] r_SM_Main = 0; 33 | reg [15:0] r_Clock_Count = 0; 34 | reg [2:0] r_Bit_Index = 0; 35 | reg [7:0] r_Tx_Data = 0; 36 | reg r_Tx_Done = 0; 37 | reg r_Tx_Active = 0; 38 | 39 | assign o_Tx_Enable = !o_Tx_Serial; 40 | 41 | always @(posedge i_Clock) 42 | begin 43 | 44 | case (r_SM_Main) 45 | s_IDLE : 46 | begin 47 | o_Tx_Serial <= 1'b1; // Drive Line High for Idle 48 | r_Tx_Done <= 1'b0; 49 | r_Clock_Count <= 0; 50 | r_Bit_Index <= 0; 51 | 52 | if (i_Tx_DV == 1'b1) 53 | begin 54 | r_Tx_Active <= 1'b1; 55 | r_Tx_Data <= i_Tx_Byte; 56 | r_SM_Main <= s_TX_START_BIT; 57 | end 58 | else 59 | r_SM_Main <= s_IDLE; 60 | end // case: s_IDLE 61 | 62 | 63 | // Send out Start Bit. Start bit = 0 64 | s_TX_START_BIT : 65 | begin 66 | o_Tx_Serial <= 1'b0; 67 | 68 | // Wait CLKS_PER_BIT-1 clock cycles for start bit to finish 69 | if (r_Clock_Count < (CLK_FREQ_HZ/baudrate)-1) 70 | begin 71 | r_Clock_Count <= r_Clock_Count + 1; 72 | r_SM_Main <= s_TX_START_BIT; 73 | end 74 | else 75 | begin 76 | r_Clock_Count <= 0; 77 | r_SM_Main <= s_TX_DATA_BITS; 78 | end 79 | end // case: s_TX_START_BIT 80 | 81 | 82 | // Wait CLKS_PER_BIT-1 clock cycles for data bits to finish 83 | s_TX_DATA_BITS : 84 | begin 85 | o_Tx_Serial <= r_Tx_Data[r_Bit_Index]; 86 | 87 | if (r_Clock_Count < (CLK_FREQ_HZ/baudrate)-1) 88 | begin 89 | r_Clock_Count <= r_Clock_Count + 1; 90 | r_SM_Main <= s_TX_DATA_BITS; 91 | end 92 | else 93 | begin 94 | r_Clock_Count <= 0; 95 | 96 | // Check if we have sent out all bits 97 | if (r_Bit_Index < 7) 98 | begin 99 | r_Bit_Index <= r_Bit_Index + 1; 100 | r_SM_Main <= s_TX_DATA_BITS; 101 | end 102 | else 103 | begin 104 | r_Bit_Index <= 0; 105 | r_SM_Main <= s_TX_STOP_BIT; 106 | end 107 | end 108 | end // case: s_TX_DATA_BITS 109 | 110 | 111 | // Send out Stop bit. Stop bit = 1 112 | s_TX_STOP_BIT : 113 | begin 114 | o_Tx_Serial <= 1; 115 | 116 | // Wait CLKS_PER_BIT-1 clock cycles for Stop bit to finish 117 | if (r_Clock_Count < (CLK_FREQ_HZ/baudrate)-1) 118 | begin 119 | r_Clock_Count <= r_Clock_Count + 1; 120 | r_SM_Main <= s_TX_STOP_BIT; 121 | end 122 | else 123 | begin 124 | r_Tx_Done <= 1'b1; 125 | r_Clock_Count <= 0; 126 | r_SM_Main <= s_CLEANUP; 127 | r_Tx_Active <= 1'b0; 128 | end 129 | end // case: s_Tx_STOP_BIT 130 | 131 | 132 | // Stay here 1 clock 133 | s_CLEANUP : 134 | begin 135 | r_Tx_Done <= 1'b1; 136 | r_SM_Main <= s_IDLE; 137 | end 138 | 139 | 140 | default : 141 | r_SM_Main <= s_IDLE; 142 | 143 | endcase 144 | end 145 | 146 | assign o_Tx_Active = r_Tx_Active; 147 | assign o_Tx_Done = r_Tx_Done; 148 | 149 | endmodule 150 | -------------------------------------------------------------------------------- /roboy_fpga_code/xl320/XL320_tb.v: -------------------------------------------------------------------------------- 1 | `timescale 1 ns/1 ns 2 | module XL320_tb; 3 | 4 | reg clock, reset; 5 | wire serial_io; 6 | reg [15:0] address; 7 | reg write; 8 | reg signed [31:0] writedata; 9 | reg read; 10 | wire signed [31:0] readdata; 11 | wire waitrequest; 12 | 13 | localparam DXL_INST_PING = 8'h01; /**< checks if ID is associated to a Device */ 14 | localparam DXL_INST_READ = 8'h02; /**< read data from the Device */ 15 | localparam DXL_INST_WRITE = 8'h03; /**< write data on the Device */ 16 | localparam DXL_INST_REG_WRITE = 8'h04; /**< registers the write instruction to a standby status */ 17 | localparam DXL_INST_ACTION = 8'h05; /**< executes the write instruction previously registered */ 18 | localparam DXL_INST_FACTORY_RESET = 8'h06; /**< resets the Control Table to its initial factory default settings */ 19 | localparam DXL_INST_REBOOT = 8'h08; /**< reboot the Device */ 20 | localparam DXL_INST_STATUS = 8'h55; /**< Return Instruction for the Instruction Packet */ 21 | localparam DXL_INST_SYNC_READ = 8'h82; /**< (Multiple devices) read data with same Address and length at once */ 22 | localparam DXL_INST_SYNC_WRITE = 8'h83; /**< (Multiple devices) write data on the same Address and length at once */ 23 | localparam DXL_INST_BULK_READ = 8'h92; /**< (Multiple devices) read data from different Addresses and lengths at once */ 24 | localparam DXL_INST_BULK_WRITE = 8'h93; /**< (Multiple devices) write data on different Addresses and lengths at once */ 25 | 26 | /*EEPROM Area*/ 27 | localparam MODEL_NUMBER = 0; /**< Model number [R] (default=350) */ 28 | localparam VERSION = 2; /**< Information on the version of firmware [R] */ 29 | localparam ID = 3; /**< ID of Dynamixel [RW] (default=1 ; min=0 ; max=252) */ 30 | localparam BAUD_RATE = 4; /**< Baud Rate of Dynamixel [RW] (default=3 ; min=0 ; max=3) 0: 9600; 1:57600; 2:115200; 3:1Mbps*/ 31 | localparam RETURN_DELAY_TIME = 5; /**< Return Delay Time [RW] (default=250 ; min=0 ; max=254) */ 32 | localparam CW_ANGLE_LIMIT = 6; /**< clockwise Angle Limit [RW] (default=0 ; min=0 ; max=1023) */ 33 | localparam CCW_ANGLE_LIMIT = 8; /**< counterclockwise Angle Limit [RW] (default=1023 ; min=0 ; max=1023) */ 34 | localparam CONTROL_MODE = 11; /**< Control Mode [RW] (default=2 ; min=1 ; max=2) */ 35 | localparam LIMIT_TEMPERATURE = 12; /**< Internal Limit Temperature [RW] (default=65 ; min=0 ; max=150) */ 36 | localparam LOWER_LIMIT_VOLTAGE = 13; /**< Lowest Limit Voltage [RW] (default=60 ; min=50 ; max=250) */ 37 | localparam UPPPER_LIMIT_VOLTAGE = 14; /**< Upper Limit Voltage [RW] (default=90 ; min=50 ; max=250) */ 38 | localparam MAX_TORQUE = 15; /**< Lowest byte of Max. Torque [RW] (default=1023 ; min=0 ; max=1023) */ 39 | localparam RETURN_LEVEL = 17; /**< Return Level [RW] (default=2 ; min=0 ; max=2) */ 40 | localparam ALARM_SHUTDOWN = 18; /**< Shutdown for Alarm [RW] (default=3 ; min=0 ; max=7) */ 41 | /*RAM Area*/ 42 | localparam TORQUE_ENABLE = 24; /**< Torque On/Off [RW] (default=0 ; min=0 ; max=1) */ 43 | localparam LED = 25; /**< LED On/Off [RW] (default=0 ; min=0 ; max=7) */ 44 | localparam D_GAIN = 27; /**< D Gain [RW] (default=0 ; min=0 ; max=254) */ 45 | localparam I_GAIN = 28; /**< I Gain [RW] (default=0 ; min=0 ; max=254) */ 46 | localparam P_GAIN = 29; /**< P Gain [RW] (default=32 ; min=0 ; max=254) */ 47 | localparam GOAL_POSITION = 30; /**< Goal Position [RW] (min=0 ; max=1023) */ 48 | localparam GOAL_SPEED = 32; /**< Goal Speed [RW] (min=0 ; max=2047) */ 49 | localparam GOAL_TORQUE = 35; /**< Goal Torque [RW] (min=0 ; max=1023) */ 50 | localparam PRESENT_POSITION = 37; /**< Current Position [R] */ 51 | localparam PRESENT_SPEED = 39; /**< Current Speed [R] */ 52 | localparam PRESENT_LOAD = 41; /**< Current Load [R] */ 53 | localparam PRESENT_VOLTAGE = 45; /**< Current Voltage [R] */ 54 | localparam PRESENT_TEMPERATURE = 46; /**< Present temperature [R] */ 55 | localparam REGISTERED_INSTRUCTION = 47; /**< Registered Instruction [R] (default=0) */ 56 | localparam MOVING = 49; /**< Moving [R] (default=0) */ 57 | localparam HARDWARE_ERROR = 50; /**< Hardware error status [R] (default=0) */ 58 | localparam PUNCH = 51; /**< Punch [RW] (default=32 ; min=0 ; max=1023) */ 59 | 60 | localparam READ = 69; 61 | localparam WRITE = 70; 62 | 63 | XL320 UUT( 64 | .clock(clock), 65 | .reset(reset), 66 | .serial_io(serial_io), 67 | .address(address), 68 | .write(write), 69 | .writedata(writedata), 70 | .read(read), 71 | .readdata(readdata), 72 | .waitrequest(waitrequest) 73 | ); 74 | 75 | // setup clock 76 | initial begin 77 | clock = 1'b0; 78 | forever clock = #1 ~clock; 79 | end 80 | 81 | initial begin 82 | reset = 1'b1; 83 | repeat (2) @(posedge clock); 84 | reset = 1'b0; 85 | read = 0; 86 | repeat (2) @(posedge clock); 87 | // set goal position of 1023 for motor 0 88 | address = {8'd70,8'd0}; 89 | writedata = {16'd30,16'd1023}; 90 | write = 1; 91 | repeat (1) @(posedge clock); 92 | write = 0; 93 | repeat (1) @(posedge clock); 94 | 95 | repeat (10000) @(posedge clock); 96 | $stop; 97 | end 98 | 99 | 100 | endmodule -------------------------------------------------------------------------------- /subsystemA.qsys.bk: -------------------------------------------------------------------------------- 1 | 2 | 3 | 10 | 46 | 47 | 48 | 49 | 50 | 51 | 52 | 53 | 54 | 55 | 56 | 57 | 58 | 59 | 60 | 61 | 62 | 63 | 64 | 65 | 70 | 75 | 80 | 81 | 86 | 91 | 96 | 97 | 102 | 107 | 112 | 113 | 118 | 123 | 128 | 129 | 130 | 131 | 132 | 133 | 134 | 135 | 136 | 137 | 138 | 139 | 140 | 141 | 142 | 143 | 144 | 145 | 146 | 147 | 148 | 149 | 150 | --------------------------------------------------------------------------------