├── README.md
└── TAGE
    ├── Branch_Benchmark.zip
    ├── Different_TAG_Lengths
        └── Index_Tag_Generator_Model_3.v
    └── Source
        ├── Bimodal_Table.v
        ├── BranchAddress.v
        ├── Comparator.v
        ├── Incrementer.v
        ├── Index_Tag_Generator.v
        ├── Statistics.v
        ├── TAGE_Controller.v
        ├── TAGE_Table.v
        ├── TopLevel.v
        ├── TopLevel_testbench.v
        ├── prediction.v
        ├── update_history.v
        └── update_predictor.v


/README.md:
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 1 | # TAGE based Predictor Verilog Code
 2 | Verilog Implementation of TAGE based predictor by  Andre Seznec and  Pierre Michaud
 3 | The implementation is based on this paper http://www.irisa.fr/caps/people/seznec/JILP-COTTAGE.pdf
 4 | 
 5 | I have done some modification with respect to the tag length, this was to limit the hardware bugdet by varying the tag- length and number of indexes
 6 | 
 7 | The TAGE predictor has 1 Bimodal Table and 4 TAGGED predictor Component with different geometric lengths respectively 7, 14, 44, 130
 8 | 
 9 | Table 1 . Tag-length of Different tag component in different models
10 | 
11 | | Model No  | T1 | T2 | T3 | T4 | No of Entries |  Total hardware budget in Bits |
12 | |-----------|----|----|----|----|---------------|--------------------------------|
13 | | 2         | 8  | 8  | 9  | 9  | 512           | 29174                          |
14 | | 3         | 5  | 5  | 5  | 5  | 1024          | 44032                          |
15 | 
16 | The source directory has model 2(only the index_Tag.Generator.v file is changed for different models). The Model 3 is there in directory Different_TAG_Lengths.
17 | 
18 | 
19 | I have provided a sample test benchmark. The trace was obtained from the 2011 championship branh predictor tournament.They are in Zip file Branch_Benchmark.zip
20 | 
21 | The implementation is basic, you can optimize the verilog code as per your requirement based on the many TAGE papers published.
22 | 


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/TAGE/Branch_Benchmark.zip:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/RoyanTuscano/-TAGE-based-Predictor-Verilog-Code/eed1c7e3b0e16164a2535cf962eb747bef903918/TAGE/Branch_Benchmark.zip


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/TAGE/Different_TAG_Lengths/Index_Tag_Generator_Model_3.v:
--------------------------------------------------------------------------------
 1 | `timescale 1ns / 1ps
 2 | //Model 3 with all tag lenths as 5 and no of entries 1024 i.e index bit size of 10
 3 | 
 4 | module Index_Tag_Generator(CLK,reset,ghist,pc_addr, Index_bank1,Index_bank2,
 5 | 							Index_bank3, Index_bank4,
 6 | 							Comp_tag_bank1, Comp_tag_bank2, Comp_tag_bank3
 7 | 							,Comp_tag_bank4, index_tag_enable);
 8 | 							
 9 | 	//parameter HistLen_Bank1=8;
10 | 	//parameter HistLen_Bank2=15;
11 | 	//parameter HistLen_Bank3=44;
12 | 	//parameter HistLen_Bank4=130;
13 | 	
14 | 	parameter GlobLen=131;	//This is the global history length
15 | 	
16 | 	//parameter OutLen1=0 ; 	//this is the length that will be thrown out at the end and wont be used...HistLen%OutLen
17 | 	//parameter OutLen2=7 ;
18 | 	//parameter OutLen3=4 ;
19 | 	//parameter OutLen4=2;
20 | 	parameter ADDRESS_SIZE=32;	//length of the program counter
21 | 
22 | 
23 | 							
24 | 	input CLK,reset;
25 | 	input [GlobLen-1:0] ghist;
26 | 	input [ADDRESS_SIZE - 1:0] pc_addr;
27 | 	input index_tag_enable;
28 | 	
29 | 	output reg [tag_len-1 : 0] Comp_tag_bank1, Comp_tag_bank2;
30 | 	output reg [tag_len : 0] Comp_tag_bank3, Comp_tag_bank4;
31 | 	output reg [IL-1 : 0] Index_bank1, Index_bank2, Index_bank3, Index_bank4;
32 | 	
33 | 		always @(posedge CLK) begin
34 | 		if(reset==1'b0)begin
35 | 			Comp_tag_bank1<={tag_len{1'b0}};
36 | 			Comp_tag_bank2<={tag_len{1'b0}};
37 | 			Comp_tag_bank3<={9{1'b0}};
38 | 			Comp_tag_bank4<={9{1'b0}};
39 | 			Index_bank1<={IL{1'b0}};
40 | 			Index_bank2<={IL{1'b0}};
41 | 			Index_bank3<={IL{1'b0}};
42 | 			Index_bank4<={IL{1'b0}};
43 | 			
44 | 		end
45 | 		else if(index_tag_enable==1'b1) begin
46 | 			//compute index
47 | 			
48 | 			Index_bank1<=(pc_addr[9:0])^(pc_addr[19:10])^(pc_addr[29:20])^({2'b00,{ghist[7:0]}});
49 | 			Index_bank2<=(pc_addr[9:0])^(pc_addr[19:10])^(pc_addr[29:20])^(ghist[9:0])^({5'b0000,{ghist[14:10]}});
50 | 			Index_bank3<=(pc_addr[9:0])^(pc_addr[19:10])^(pc_addr[29:20])^(ghist[9:0])^(ghist[19:10])^(ghist[29:20])^(ghist[39:30])^({6'b000000,{ghist[43:40]}});
51 | 			Index_bank4<=(pc_addr[9:0])^(pc_addr[19:10])^(pc_addr[29:20])^(ghist[9:0])^(ghist[19:10])^(ghist[29:20])^(ghist[39:30])
52 | 							^(ghist[49:40])^(ghist[59:50])^(ghist[69:60])^(ghist[79:70])^(ghist[89:80])^(ghist[99:90])^(ghist[109:100])
53 | 							^(ghist[119:110])^(ghist[129:120]); 
54 | 				//Compute Tag
55 | 			 Comp_tag_bank1<=(pc_addr[4:0])^(ghist[4:0]) ^({ghist[3:0],1'b0});
56 | 			 Comp_tag_bank2<=(pc_addr[4:0])^(ghist[4:0])^(ghist[9:5])^(ghist[14:10])^({ghist[3:0],1'b0})^({ghist[7:4],1'b0})^({ghist[11:8],1'b0})^({1'b0,ghist[14:12],1'b0});
57 | 			 Comp_tag_bank3<=(pc_addr[4:0])^(ghist[4:0])^(ghist[9:5])^(ghist[14:10])^(ghist[19:15])^(ghist[24:20])^
58 | 							(ghist[29:25])^(ghist[34:30])^(ghist[39:35])^(ghist[44:40])
59 | 							^({ghist[3:0],1'b0})^({ghist[7:4],1'b0})^({ghist[11:8],1'b0})^({ghist[15:12],1'b0})^({ghist[19:16],1'b0})
60 | 							^({ghist[23:20],1'b0})^({ghist[27:24],1'b0})^({ghist[31:28],1'b0})^({ghist[35:32],1'b0})
61 | 							^({ghist[39:36],1'b0})^({ghist[43:40],1'b0});
62 | 			 Comp_tag_bank4<=(pc_addr[4:0])^(ghist[4:0])^(ghist[9:5])^(ghist[14:10])^(ghist[19:15])^(ghist[24:20])^
63 | 							(ghist[29:25])^(ghist[34:30])^(ghist[39:35])^(ghist[44:40])
64 | 							^(ghist[49:45])^(ghist[54:50])^(ghist[59:55])^(ghist[64:60])^(ghist[69:65])
65 | 							^(ghist[74:70])^(ghist[79:75])^(ghist[84:80])^(ghist[89:85])^(ghist[94:90])
66 | 							^(ghist[99:95])^(ghist[104:100])^(ghist[109:105])^(ghist[114:110])^(ghist[119:115])
67 | 							^(ghist[124:120])^(ghist[129:125])^({ghist[3:0],1'b0})^({ghist[7:4],1'b0})^({ghist[11:8],1'b0})^({ghist[15:12],1'b0})^({ghist[19:16],1'b0})
68 | 							^({ghist[23:20],1'b0})^({ghist[27:24],1'b0})^({ghist[31:28],1'b0})^({ghist[35:32],1'b0})
69 | 							^({ghist[39:36],1'b0})^({ghist[43:40],1'b0})^({ghist[47:44],1'b0})^({ghist[51:48],1'b0})^
70 | 							({ghist[55:52],1'b0})^({ghist[59:56],1'b0})^({ghist[63:60],1'b0})^({ghist[67:64],1'b0})^
71 | 							({ghist[71:68],1'b0})^({ghist[75:72],1'b0})^({ghist[79:76],1'b0})^({ghist[83:80],1'b0})^({ghist[87:84],1'b0})^
72 | 							({ghist[91:88],1'b0})^({ghist[95:92],1'b0})^({ghist[99:96],1'b0})^({ghist[103:100],1'b0})^
73 | 							({ghist[107:104],1'b0})^({ghist[111:108],1'b0})^({ghist[115:112],1'b0})^({ghist[119:116],1'b0})
74 | 							^({ghist[123:120],1'b0})^({ghist[127:124],1'b0})^({2'b00,ghist[129:128],1'b0})	;						
75 | 									
76 | 		end
77 | 		else begin
78 | 			Index_bank2<=Index_bank1;
79 | 			Index_bank2<=Index_bank2;
80 | 			Index_bank3<=Index_bank3;
81 | 			Index_bank4<=Index_bank4;
82 | 			Comp_tag_bank1<=Comp_tag_bank1;
83 | 			Comp_tag_bank2<=Comp_tag_bank2;
84 | 			Comp_tag_bank3<=Comp_tag_bank3;
85 | 			Comp_tag_bank4<=Comp_tag_bank4;
86 | 		end
87 | 
88 | 		
89 | 	end
90 | 	
91 | endmodule
92 | 


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/TAGE/Source/Bimodal_Table.v:
--------------------------------------------------------------------------------
 1 | `timescale 1ns / 1ps
 2 | 
 3 | module 	Bimodal_Table(Clk, wr, rd, index/*pc*/, rdata_c_bits, correct_prediction, inc_counter, dec_counter,update_enable);
 4 |    
 5 | 	parameter IL=13;	//Index size ie number of addresses
 6 | 	parameter CL=3;		//Counter length
 7 | 
 8 | 	reg [ CL-1 : 0 ] c_bits[(1 << IL) - 1 : 0];		//Counter table
 9 | 	
10 | 	output [ CL-1 : 0 ] rdata_c_bits;
11 | 	reg [ CL-1 : 0 ] rdata_c_bits_reg;
12 | 	input [IL - 1 : 0]index;
13 | 	input Clk,rd,wr;
14 |     input correct_prediction;
15 | 	input inc_counter;
16 | 	input dec_counter;
17 | 	input update_enable;
18 | 
19 |     integer i, j;
20 |    
21 |     initial
22 |     begin
23 |       for (i = 0; i < (1<<IL); i = i+1)
24 | 			begin	
25 | 				c_bits[i] = {CL{1'b0}};		//initialize the bits
26 | 			end
27 | 	end
28 |    
29 |    // Keep addr and write data
30 |    
31 |   always @(posedge Clk)
32 | 	begin
33 | 		    if (inc_counter==1'b1 && update_enable==1'b1 && c_bits[index]!= {CL{1'b1}})
34 | 				begin
35 | 						c_bits[index]<=c_bits[index] + 1'b1;
36 | 				end
37 | 			else if(dec_counter==1'b1 && update_enable==1'b1 && c_bits[index]!= {CL{1'b0}})
38 | 				begin	
39 | 						c_bits[index]<=c_bits[index] - 1'b1;
40 | 				end
41 | 			else
42 | 				begin
43 | 						c_bits[index]<=c_bits[index];
44 | 				end
45 | 					
46 | 	end
47 | 
48 | 
49 |   //
50 |   // Read process
51 |   // ------------
52 | 
53 | 
54 |   always @(posedge Clk)
55 | 	begin
56 | 		if (rd)
57 | 			begin
58 | 				rdata_c_bits_reg <= c_bits[index];
59 | 			end
60 | 		else
61 | 			begin
62 | 				rdata_c_bits_reg <= {CL{1'bX}};
63 | 			end
64 | 	end
65 | 		
66 |   assign rdata_c_bits = rdata_c_bits_reg;
67 | 	
68 | endmodule
69 | 
70 | 


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/TAGE/Source/BranchAddress.v:
--------------------------------------------------------------------------------
 1 | `timescale 1ns / 1ps
 2 | 
 3 | module BranchAddress(Clk, reset, InstructionNumber, BranchAddress, BranchResult);
 4 |     parameter ADDRESS_SIZE = 8;
 5 |     parameter TRAINING_DATA_SIZE = 3898078;
 6 |     parameter INSTRUCTION_INDEX_SIZE = $clog2(TRAINING_DATA_SIZE);   
 7 |     input Clk,reset;
 8 |     input [INSTRUCTION_INDEX_SIZE - 1:0] InstructionNumber;
 9 |     output reg [ADDRESS_SIZE - 1:0] BranchAddress;
10 |     output reg BranchResult;
11 |     reg [ADDRESS_SIZE - 1:0] Address [TRAINING_DATA_SIZE - 1:0];
12 |     reg Branch [TRAINING_DATA_SIZE - 1:0];
13 |     integer i;
14 |     
15 |     initial begin
16 |         for (i = 0; i < TRAINING_DATA_SIZE; i = i + 'd1) begin
17 |             Address[i] = 0;
18 |             Branch[i] = 0;
19 |         end
20 |         BranchAddress <= {ADDRESS_SIZE{1'b0}};
21 |         BranchResult <= {1{1'b0}};
22 | 	    //edit this as per location of the address and branch addresses of the file
23 | 	    $readmemh("../Data/CLIENT01_Address.txt", Address);
24 | 	    $readmemb("../Data/CLIENT01_branchresult.txt", Branch);
25 |     end
26 |   
27 |     always@(Clk) begin
28 | 		if(reset==1'b0) begin
29 | 		    BranchAddress <= {ADDRESS_SIZE{1'b0}};
30 | 			BranchResult <= {1{1'b0}};
31 | 		end
32 | 		else begin
33 | 		    BranchAddress <= Address[InstructionNumber];
34 | 			BranchResult <= Branch[InstructionNumber];
35 | 		end
36 | 
37 |     end 
38 |     
39 | endmodule
40 | 


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/TAGE/Source/Comparator.v:
--------------------------------------------------------------------------------
 1 | `timescale 1ns / 1ps
 2 | 
 3 | module comparator(clk,reset, a, b, eq);
 4 |     parameter DATAWIDTH = 1;
 5 |     input [DATAWIDTH-1:0] a, b;
 6 |     output reg eq;
 7 |     input clk,reset;
 8 |     
 9 |     always@(posedge clk) begin
10 |         if(reset==1'b0)
11 |         begin
12 |             eq<=1'b0;
13 |         end
14 |         else if (a == b) begin
15 |             eq <= 1'b1;  
16 |         end
17 |         else begin
18 |             eq <= 1'b0;
19 |         end
20 |     end
21 | endmodule
22 | 


--------------------------------------------------------------------------------
/TAGE/Source/Incrementer.v:
--------------------------------------------------------------------------------
 1 | `timescale 1ns / 1ps
 2 | 
 3 | module Incrementer(Clk, Rst, en, InstructionNumber_in, InstructionNumber_out);
 4 |     parameter TRAINING_DATA_SIZE = 256;
 5 |     parameter INSTRUCTION_INDEX_SIZE = $clog2(TRAINING_DATA_SIZE);
 6 |     input Clk, Rst, en;
 7 |     input [INSTRUCTION_INDEX_SIZE - 1:0] InstructionNumber_in;
 8 |     output reg [INSTRUCTION_INDEX_SIZE - 1:0] InstructionNumber_out;
 9 |     
10 |     initial begin
11 |         InstructionNumber_out <= 0;
12 |     end
13 |     
14 |     always@(posedge Clk, posedge Rst) begin
15 |         if (Rst == 1'b0) begin
16 |             InstructionNumber_out <= 0;
17 |         end
18 |         else if (en == 1'b1) begin
19 |             InstructionNumber_out <= InstructionNumber_out + 1'b1;
20 |         end
21 | 		else
22 | 			InstructionNumber_out <= InstructionNumber_out;
23 | 		
24 |     end
25 |     
26 | endmodule
27 | 


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/TAGE/Source/Index_Tag_Generator.v:
--------------------------------------------------------------------------------
 1 | `timescale 1ns / 1ps
 2 | 
 3 | //This is for Model 2 with tag length 8 and 9
 4 | 
 5 | module Index_Tag_Generator(CLK,reset,ghist,pc_addr, Index_bank1,Index_bank2,
 6 | 							Index_bank3, Index_bank4,
 7 | 							Comp_tag_bank1, Comp_tag_bank2, Comp_tag_bank3
 8 | 							,Comp_tag_bank4, index_tag_enable);
 9 | 							
10 | 	//parameter HistLen_Bank1=8;
11 | 	//parameter HistLen_Bank2=15;
12 | 	//parameter HistLen_Bank3=44;
13 | 	//parameter HistLen_Bank4=130;
14 | 	
15 | 	parameter GlobLen=131;	//This is the global history length
16 | 	
17 | 	//parameter OutLen1=0 ; 	//this is the length that will be thrown out at the end and wont be used...HistLen%OutLen
18 | 	//parameter OutLen2=7 ;
19 | 	//parameter OutLen3=4 ;
20 | 	//parameter OutLen4=2;
21 | 	parameter ADDRESS_SIZE=32;	//length of the program counter
22 | 	parameter tag_len=8;	//length of the tag used
23 | 	parameter IL=10;		//Index size ie number of addresses...this is like the compressed length
24 | 
25 | 							
26 | 	input CLK,reset;
27 | 	input [GlobLen-1:0] ghist;
28 | 	input [ADDRESS_SIZE - 1:0] pc_addr;
29 | 	input index_tag_enable;
30 | 	
31 | 	output reg [tag_len-1 : 0] Comp_tag_bank1, Comp_tag_bank2;
32 | 	output reg [tag_len : 0] Comp_tag_bank3, Comp_tag_bank4;
33 | 	output reg [IL-1 : 0] Index_bank1, Index_bank2, Index_bank3, Index_bank4;
34 | 	
35 | 		always @(posedge CLK) begin
36 | 		if(reset==1'b0)begin
37 | 			Comp_tag_bank1<={tag_len{1'b0}};
38 | 			Comp_tag_bank2<={tag_len{1'b0}};
39 | 			Comp_tag_bank3<={9{1'b0}};
40 | 			Comp_tag_bank4<={9{1'b0}};
41 | 			Index_bank1<={IL{1'b0}};
42 | 			Index_bank2<={IL{1'b0}};
43 | 			Index_bank3<={IL{1'b0}};
44 | 			Index_bank4<={IL{1'b0}};
45 | 			
46 | 		end
47 | 		else if(index_tag_enable==1'b1) begin
48 | 			//compute index
49 | 			
50 | 			Index_bank1<=(pc_addr[9:0])^(pc_addr[19:10])^(pc_addr[29:20])^({2'b00,{ghist[7:0]}});
51 | 			Index_bank2<=(pc_addr[9:0])^(pc_addr[19:10])^(pc_addr[29:20])^(ghist[9:0])^({5'b0000,{ghist[14:10]}});
52 | 			Index_bank3<=(pc_addr[9:0])^(pc_addr[19:10])^(pc_addr[29:20])^(ghist[9:0])^(ghist[19:10])^(ghist[29:20])^(ghist[39:30])^({6'b000000,{ghist[43:40]}});
53 | 			Index_bank4<=(pc_addr[9:0])^(pc_addr[19:10])^(pc_addr[29:20])^(ghist[9:0])^(ghist[19:10])^(ghist[29:20])^(ghist[39:30])
54 | 							^(ghist[49:40])^(ghist[59:50])^(ghist[69:60])^(ghist[79:70])^(ghist[89:80])^(ghist[99:90])^(ghist[109:100])
55 | 							^(ghist[119:110])^(ghist[129:120]); 
56 | 							 
57 | 			//compute tag 
58 | 		    Comp_tag_bank1<=(pc_addr[7:0])^ghist[7:0] ^({ghist[6:0],1'b0});
59 |             Comp_tag_bank2<=(pc_addr[7:0])^(ghist[7:0])^({1'b0,ghist[14:8]})^({ghist[6:0],1'b0})^({ghist[13:7],1'b0});
60 |             Comp_tag_bank3<=(pc_addr[8:0])^(ghist[8:0])^(ghist[17:9])^(ghist[26:18])^(ghist[35:27])^({1'b0,ghist[43:36]})
61 | 							^({ghist[7:0],1'b0})^({ghist[15:8],1'b0})^({ghist[23:16],1'b0})^({ghist[31:24],1'b0})
62 | 							^({ghist[39:32],1'b0})^({4'h0,ghist[43:40],1'b0});
63 |             Comp_tag_bank4<=(pc_addr[8:0])^(ghist[8:0])^(ghist[17:9])^(ghist[26:18])^(ghist[35:27])^(ghist[44:36])^(ghist[53:45])
64 |                             ^(ghist[62:54])^(ghist[71:63])^(ghist[80:72])^(ghist[89:81])^(ghist[98:90])^(ghist[107:99])^(ghist[116:108])
65 |                             ^(ghist[125:117])^({5'b0,ghist[129:126]})
66 | 							^({ghist[7:0],1'b0})^({ghist[15:8],1'b0})^({ghist[23:16],1'b0})^({ghist[31:24],1'b0})^({ghist[39:32],1'b0})
67 | 							^({ghist[47:40],1'b0})^({ghist[55:48],1'b0})^({ghist[63:56],1'b0})^({ghist[71:64],1'b0})^({ghist[79:72],1'b0})
68 | 							^({ghist[87:80],1'b0})^({ghist[95:88],1'b0})^({ghist[103:96],1'b0})^({ghist[111:104],1'b0})^({ghist[119:112],1'b0})
69 | 							^({ghist[127:120],1'b0})^({6'b000000,ghist[129:128],1'b0});
70 | 		
71 | 		end
72 | 		else begin
73 | 			Index_bank2<=Index_bank1;
74 | 			Index_bank2<=Index_bank2;
75 | 			Index_bank3<=Index_bank3;
76 | 			Index_bank4<=Index_bank4;
77 | 			Comp_tag_bank1<=Comp_tag_bank1;
78 | 			Comp_tag_bank2<=Comp_tag_bank2;
79 | 			Comp_tag_bank3<=Comp_tag_bank3;
80 | 			Comp_tag_bank4<=Comp_tag_bank4;
81 | 		end
82 | 
83 | 		
84 | 	end
85 | 	
86 | endmodule
87 | 


--------------------------------------------------------------------------------
/TAGE/Source/Statistics.v:
--------------------------------------------------------------------------------
 1 | `timescale 1ns / 1ps
 2 | //This file updates on the correct prediction and gives statistics
 3 | module Statistics(Clk,reset, BranchResult, CorrectlyPredicted, TotalBranches,enable);
 4 |     parameter TRAINING_DATA_SIZE = 65536;
 5 |     parameter INSTRUCTION_INDEX_SIZE = $clog2(TRAINING_DATA_SIZE);
 6 |     
 7 |     input Clk,reset,enable;
 8 |     input BranchResult;
 9 |     reg [INSTRUCTION_INDEX_SIZE - 1:0] CorrectlyPredicted_reg, TotalBranches_reg;
10 |     output reg [INSTRUCTION_INDEX_SIZE - 1:0] CorrectlyPredicted, TotalBranches;
11 |     
12 |     initial begin
13 |         CorrectlyPredicted <= 0;
14 |         TotalBranches <= 0;
15 |     end
16 |     
17 |     always@(posedge Clk) begin
18 | 		if(reset==1'b0)
19 | 			begin
20 | 				CorrectlyPredicted <= 0;
21 | 				TotalBranches<=0;
22 | 			end
23 |         else if (BranchResult==1'b1 && enable==1'b1) begin
24 |             CorrectlyPredicted <= CorrectlyPredicted + 1;
25 | 			TotalBranches <= TotalBranches + 1;
26 |         end
27 | 		else if(BranchResult==1'b0 && enable==1'b1) begin
28 | 			CorrectlyPredicted<= CorrectlyPredicted;
29 | 			TotalBranches<= TotalBranches + 1;		
30 | 		end
31 | 		else begin
32 | 			CorrectlyPredicted <= CorrectlyPredicted;
33 | 			TotalBranches <= TotalBranches;	
34 | 		end
35 |         
36 |     end
37 |     
38 | endmodule
39 | 


--------------------------------------------------------------------------------
/TAGE/Source/TAGE_Controller.v:
--------------------------------------------------------------------------------
  1 | `timescale 1ns / 1ps
  2 | //This is the module that is responsible for controlling the operations of the TAGE predictor, you can pipeline the operations for higher speedup
  3 | module TAGE_Controller(CLK,reset,
  4 | 						index_tag_enable,instruction_inc_en,table_read_en, update_enable, update_predictor_enable);
  5 | 
  6 | 
  7 | input CLK,reset;
  8 | 
  9 | 
 10 | output reg index_tag_enable;		//This is to enable the calculation of Table Address
 11 | output reg instruction_inc_en;				//This is to load the instruction
 12 | output reg table_read_en, update_predictor_enable, update_enable;
 13 | 
 14 | 
 15 | wire temp1;
 16 | wire temp2;
 17 | reg[3:0] state, next_state;
 18 | 
 19 | initial begin
 20 | 
 21 | end
 22 | 
 23 | 
 24 | 
 25 | parameter[3:0] wait_state=0, state_1 = 1, state_2 = 2, state_3 = 3, state_4 = 4, state_5 = 5,
 26 | 				state_6 = 6, state_7 = 7, state_8 = 8, state_9 = 9;
 27 | 
 28 | 		always @(posedge CLK)begin
 29 | 			if(reset==0) begin
 30 | 				state<=wait_state;
 31 | 				end
 32 | 			else begin
 33 | 			state<=next_state;
 34 | 				end
 35 | 			end
 36 | 
 37 | 	always @(state)
 38 | 	begin
 39 | 		case(state)
 40 | 			wait_state: 		
 41 | 					begin
 42 | 						instruction_inc_en <= 1'b0;		
 43 | 						index_tag_enable<=1'b0;
 44 | 						table_read_en<=1'b0;
 45 | 						update_predictor_enable<=1'b0;
 46 | 						update_enable<=1'b0;
 47 | 						next_state<=state_1;
 48 | 					end
 49 | 			state_1:begin			
 50 | 						instruction_inc_en <= 1'b1;	
 51 | 						index_tag_enable<=1'b0;
 52 | 						table_read_en<=1'b0;
 53 | 						update_predictor_enable<=1'b0;
 54 | 						update_enable<=1'b0;
 55 | 						next_state <= state_2;
 56 | 					end
 57 | 			state_2:begin			
 58 | 						instruction_inc_en <= 1'b0;	
 59 | 						index_tag_enable<=1'b1;
 60 | 						table_read_en<=1'b0;
 61 | 						update_predictor_enable<=1'b0;
 62 | 						update_enable<=1'b0;						
 63 | 						next_state <= state_3;
 64 | 						
 65 | 					end
 66 | 			state_3:begin			
 67 | 						instruction_inc_en <= 1'b0;	
 68 | 						index_tag_enable<=1'b0;
 69 | 						table_read_en<=1'b1;
 70 | 						next_state <= state_4;						
 71 | 						update_predictor_enable<=1'b0;
 72 | 						update_enable<=1'b0;					
 73 | 					end
 74 | 					
 75 | 			state_4:begin		//comparasion of the tags takes place	
 76 | 						instruction_inc_en <= 1'b0;	
 77 | 						index_tag_enable<=1'b0;
 78 | 						table_read_en<=1'b1;
 79 | 						next_state <= state_5;
 80 | 						update_predictor_enable<=1'b0;
 81 | 						update_enable<=1'b0;
 82 | 						end
 83 | 			state_5:begin	//predicition takes place
 84 | 						instruction_inc_en <= 1'b0;	
 85 | 						index_tag_enable<=1'b0;
 86 | 						table_read_en<=1'b1;
 87 | 						update_predictor_enable<=1'b0;
 88 | 						update_enable<=1'b0;
 89 | 						next_state <= state_6;						
 90 | 					end
 91 | 			state_6:begin
 92 | 						instruction_inc_en <= 1'b0;	
 93 | 						index_tag_enable<=1'b0;
 94 | 						table_read_en<=1'b1;
 95 | 						update_predictor_enable<=1'b1;
 96 | 						update_enable<=1'b0;
 97 | 						next_state <= state_7;	
 98 | 					end
 99 | 			state_7:begin
100 | 						instruction_inc_en <= 1'b0;	
101 | 						index_tag_enable<=1'b0;
102 | 						table_read_en<=1'b1;
103 | 						update_predictor_enable<=1'b0;
104 | 						update_enable<=1'b1;
105 | 						next_state <= state_1;						
106 | 					end
107 | 			default:begin
108 | 					end
109 | 		
110 | 
111 | 	       endcase
112 | 	     end
113 | 
114 | 			
115 | 			
116 | 
117 | 
118 |   
119 | endmodule
120 | 
121 | 
122 | 
123 | 
124 | 
125 | 
126 | 
127 | 
128 | 
129 | 
130 | 
131 | 
132 | 
133 | 
134 | 
135 | 
136 | 
137 | 
138 | 


--------------------------------------------------------------------------------
/TAGE/Source/TAGE_Table.v:
--------------------------------------------------------------------------------
  1 | `timescale 1ns / 1ps
  2 | //This is the TAGE precitor component or table.. hear  you modify and update the TAG bits, Useful bits and predictor bits
  3 | module TAGE_Table(Clk, wr, rd, index, rdata_tag_bits, rdata_u_bits, rdata_c_bits, wdata_tag_bits,
  4 | 					correct_prediction, inc_u_bit,dec_u_bit, inc_c_bit, dec_c_bit, alloc,update_enable);
  5 |    
  6 | 	parameter IL=10;	//Index size ie number of addresses
  7 | 	parameter tag_len=8;	//Tag length
  8 | 	parameter UL=2;		//Useful length
  9 | 	parameter CL=3;		//Counter length
 10 | 
 11 |     
 12 | 	reg [ tag_len-1 : 0 ] tag_bits[(1 << IL) - 1 : 0];	//tag table 
 13 | 	reg [ UL-1 : 0 ] u_bits[(1 << IL) - 1 : 0];		//Useful table
 14 | 	reg [ CL-1 : 0 ] c_bits[(1 << IL) - 1 : 0];		//Counter table
 15 | 	reg[CL-1:0] rdata_c_bits_reg;
 16 | 	reg[UL-1:0] rdata_u_bits_reg;
 17 | 	reg [ tag_len-1 : 0 ] rdata_tag_bits_reg;
 18 | 	output [ tag_len-1 : 0 ] rdata_tag_bits;
 19 | 	output [ UL-1 : 0 ] rdata_u_bits;
 20 | 	output [ CL-1 : 0 ] rdata_c_bits;
 21 | 	
 22 | 	input [ tag_len-1 : 0 ] wdata_tag_bits;
 23 | 	input [IL - 1 : 0]index;
 24 | 	input Clk,rd,wr;
 25 |     input correct_prediction;
 26 | 	input inc_u_bit,dec_u_bit;
 27 | 	input inc_c_bit, dec_c_bit;
 28 | 	input alloc;
 29 | 	input update_enable;
 30 | 
 31 |     integer i;
 32 |    
 33 |     initial
 34 |     begin
 35 |       for (i = 0; i < (1<<IL); i = i+1)
 36 | 			begin
 37 | 				tag_bits[i] = {tag_len{1'b0}};		//initialize the bits
 38 | 				u_bits[i] =	{UL{1'b0}};	
 39 | 				c_bits[i] = {CL{1'b0}};
 40 | 			end
 41 | 	end
 42 |    
 43 |    // Keep addr and write data
 44 |   always @(posedge Clk)
 45 | 	begin
 46 | 		//update useful bits
 47 | 			if(alloc==1'b0 && inc_c_bit==1'b1 && update_enable==1'b1 && c_bits[index]!= {CL{1'b1}})
 48 | 				c_bits[index]<=c_bits[index] + 1;
 49 | 			else if(alloc==1'b0 && dec_c_bit==1'b1 && update_enable==1'b1 && c_bits[index]!= {CL{1'b0}})
 50 | 				c_bits[index]<=c_bits[index] - 1;
 51 | 			else
 52 | 				c_bits[index]<=c_bits[index];
 53 | 				
 54 | 		//update counter bits
 55 | 			if(inc_u_bit==1'b1 && update_enable==1'b1 && u_bits[index]!={UL{1'b1}})
 56 | 				u_bits[index]<=u_bits[index]+1;
 57 | 			else if(dec_u_bit==1'b1 && update_enable==1'b1 && u_bits[index]!={UL{1'b0}})
 58 | 				u_bits[index]<=u_bits[index]-1;
 59 | 			else
 60 | 				u_bits[index]<=u_bits[index];
 61 | 				
 62 | 		//update the tags
 63 | 
 64 | 			if(alloc==1'b1 && dec_u_bit==1'b1 && update_enable==1'b1)
 65 | 				tag_bits[index]<=wdata_tag_bits;
 66 | 			else
 67 | 				tag_bits[index]<=tag_bits[index];
 68 | 					
 69 | 	end
 70 | 
 71 | 
 72 |   //
 73 |   // Read process
 74 |   // ------------
 75 | 
 76 | 
 77 |   always @(posedge Clk)
 78 | 	begin
 79 | 		if (rd)
 80 | 			begin
 81 | 				rdata_tag_bits_reg <= tag_bits[index];
 82 | 				rdata_u_bits_reg <= u_bits[index];
 83 | 				rdata_c_bits_reg <= c_bits[index];
 84 | 			end
 85 | 		else
 86 | 			begin
 87 | 				rdata_tag_bits_reg <= {tag_len{1'bX}};
 88 | 				rdata_u_bits_reg <= {UL{1'bX}};
 89 | 				rdata_c_bits_reg <= {CL{1'bX}};
 90 | 			end
 91 | 	end
 92 | 		
 93 |   assign rdata_tag_bits = rdata_tag_bits_reg;
 94 |   assign rdata_u_bits = rdata_u_bits_reg;
 95 |   assign rdata_c_bits = rdata_c_bits_reg;
 96 | 	
 97 | 
 98 | endmodule
 99 | /*
100 | always @(posedge clk)
101 | 	begin
102 | 		    if (wr && correct_prediction)
103 | 				begin
104 | 					tag_bits[index]<=new_tag_bits;
105 | 					if(branch_taken || c_bits[index] !=3'b111)
106 | 						c_bits[index]<=c_bits[index] + 1;
107 | 					else if(~branch_taken || c_bits[index] !=3'b000)
108 | 						c_bits[index]<=c_bits[index] - 1;
109 | 					else
110 | 						c_bits[index]<=c_bits[index];
111 | 					
112 | 					if(u_bits !=2'b11)
113 | 						u_bits[index]<=u_bits[index]+1;
114 | 					else	
115 | 						u_bits[index]<=u_bits[index];
116 | 				end
117 | 			else if(wr && ~correct_prediction)
118 | 				begin	
119 | 					tag_bits[index]<=new_tag_bits;
120 | 					if(branch_taken || c_bits[index] !=3'b000)		//branch_taken is predicted but since its wrong we decrement the c bit
121 | 						c_bits[index]<=c_bits[index] - 1'b1;
122 | 					else if(~branch_taken || c_bits[index] !=3'b111)	//branch not taken is predicted but since its wrong we increment the c bit
123 | 						c_bits[index]<=c_bits[index] + 1'b1;
124 | 					else
125 | 						c_bits[index]<=c_bits[index];
126 | 					
127 | 					if(u_bits !=2'b00)
128 | 						u_bits[index]<=u_bits[index]-1;
129 | 					else	
130 | 						u_bits[index]<=u_bits[index];
131 | 				end
132 | 					
133 | 	end
134 | 
135 | */
136 | 


--------------------------------------------------------------------------------
/TAGE/Source/TopLevel.v:
--------------------------------------------------------------------------------
  1 | `timescale 1ns / 1ps
  2 | //This is the Top module of the source..you can change the index bits to vary number of enteries in the Bimodal table, and TAG component tables
  3 | 
  4 | module TopLevel(CLK, reset, BranchPrediction, PredictionCorrectReg, CorrectlyPredicted, TotalBranches);
  5 |     parameter ADDRESS_SIZE = 32;
  6 |     parameter TRAINING_DATA_SIZE = 131072/2;
  7 |     parameter INSTRUCTION_INDEX_SIZE = $clog2(TRAINING_DATA_SIZE);
  8 |     parameter GHL = 23;
  9 |     parameter WS = 5;
 10 |     parameter LS = 128;
 11 |     parameter LS_INDEX_SIZE = $clog2(LS);
 12 | 	parameter GlobLen=131;	//This is the global history length
 13 |     parameter PLen=16 ;		//this is length of path History
 14 | 	parameter tag_len=8;	//length of the tag used
 15 | 	parameter tag_len1=9;	//length of the tag used for another CSR during folding
 16 | 	parameter IL=10;		//Index size ie number of addresses...this is like the compressed length
 17 | 	parameter CL=3;		//Counter length
 18 | 	parameter UL=2;		//Useful length
 19 | 	
 20 | 	parameter HistLen_Bank1=8;
 21 | 	parameter HistLen_Bank2=15;
 22 | 	parameter HistLen_Bank3=44;
 23 | 	parameter HistLen_Bank4=130;
 24 | 	
 25 | 	parameter OutLen1=0 ; 	//this is the length that will be thrown out at the end and wont be used...HistLen%OutLen
 26 | 	parameter OutLen2=7 ;
 27 | 	parameter OutLen3=4 ;
 28 | 	parameter OutLen4=2;
 29 | 	
 30 | 	parameter pc_shift=10;
 31 | 	
 32 |     input CLK, reset;
 33 |     wire Clk_decode, Clk_execute, Clk_done;
 34 |     wire [ADDRESS_SIZE - 1:0] BranchAddress,pc;
 35 |     wire [INSTRUCTION_INDEX_SIZE - 1:0] InstructionNumber,InstructionNumber_in;
 36 |     wire [LS_INDEX_SIZE - 1:0] index;
 37 |     wire BranchResult, BranchResult_register;
 38 |     wire [(GHL * WS) - 1:0] Perceptron;
 39 |     wire [(GHL * WS) - 1:0] DotProduct_out;
 40 |     wire PredictionCorrect;
 41 |     wire [GHL - 1:0] GlobalHistoryTable;
 42 |     output PredictionCorrectReg;
 43 |     output BranchPrediction;
 44 |     output [INSTRUCTION_INDEX_SIZE - 1:0] CorrectlyPredicted, TotalBranches;
 45 | 	
 46 | 	
 47 | 	
 48 | 	wire instruction_inc_en,index_tag_enable, table_read_en,wr;
 49 | 	wire Actual_branch;
 50 | 	
 51 | 	wire [PLen-1:0]  phist;
 52 | 	wire [GlobLen-1:0] ghist;
 53 | 	wire [tag_len-1 : 0] Comp_tag_bank1, Comp_tag_bank2;
 54 | 	wire [tag_len : 0] Comp_tag_bank3, Comp_tag_bank4;
 55 | 	
 56 | 	wire [tag_len-1 : 0] tag_bank1, tag_bank2;
 57 | 	wire [tag_len : 0] tag_bank3,tag_bank4;
 58 | 	
 59 | 	wire [IL-1 : 0] Index_bank1, Index_bank2, Index_bank3, Index_bank4;
 60 | 	wire[CL-1:0] Bimodal_C_bit,C_bit_Bank1,C_bit_Bank2, C_bit_Bank3, C_bit_Bank4;
 61 | 	wire[UL-1:0] U_bit_Bank1, U_bit_Bank2, U_bit_Bank3, U_bit_Bank4;
 62 | 	
 63 | 	wire inc_c_bit_Bimodal, dec_c_bit_Bimodal;
 64 | 	wire inc_c_bit_bank1,inc_c_bit_bank2, inc_c_bit_bank3, inc_c_bit_bank4;
 65 | 	wire dec_c_bit_bank1,dec_c_bit_bank2, dec_c_bit_bank3, dec_c_bit_bank4;
 66 | 	wire inc_u_bit_bank1,inc_u_bit_bank2, inc_u_bit_bank3, inc_u_bit_bank4;
 67 | 	wire dec_u_bit_bank1,dec_u_bit_bank2, dec_u_bit_bank3, dec_u_bit_bank4;
 68 | 	
 69 | 	wire correct_prediction, update_enable, Alloc, update_predictor_enable;
 70 | 
 71 | 	TAGE_Controller Controller(.CLK(CLK),.reset(reset), .index_tag_enable(index_tag_enable),
 72 | 								.instruction_inc_en(instruction_inc_en),.table_read_en(table_read_en),
 73 | 								.update_enable(update_enable),.update_predictor_enable(update_predictor_enable));
 74 | 	
 75 | 
 76 |     Incrementer#(TRAINING_DATA_SIZE) Incrementer_0(.Clk(CLK), .Rst(reset), 
 77 |                                 .en(instruction_inc_en), .InstructionNumber_in(InstructionNumber_in), 
 78 |                                   .InstructionNumber_out(InstructionNumber));
 79 |     BranchAddress#(ADDRESS_SIZE, TRAINING_DATA_SIZE) BranchAddress_0(.Clk(CLK), .InstructionNumber(InstructionNumber), .BranchAddress(pc), .BranchResult(Actual_branch));
 80 | 	
 81 | 	
 82 | Index_Tag_Generator Index_Tag_Generator01(CLK,reset,ghist,pc, Index_bank1,Index_bank2,
 83 | 							Index_bank3, Index_bank4,
 84 | 							Comp_tag_bank1, Comp_tag_bank2, Comp_tag_bank3
 85 | 							,Comp_tag_bank4, index_tag_enable);
 86 | 
 87 | 	Bimodal_Table#(IL, CL) Bimodal_Table1(.Clk(CLK), .wr(wr), .rd(table_read_en), .index(pc)/*pc*/, .rdata_c_bits(Bimodal_C_bit)
 88 | 											, .correct_prediction(correct_prediction), .inc_counter(inc_c_bit_Bimodal), .dec_counter(dec_c_bit_Bimodal)
 89 | 											,.update_enable(update_enable));
 90 | 	
 91 | 	TAGE_Table#(IL,tag_len,UL,CL )  bank1(.Clk(CLK), .wr(wr), .rd(table_read_en), .index(Index_bank1), .rdata_tag_bits(tag_bank1), .rdata_u_bits(U_bit_Bank1),
 92 | 									.rdata_c_bits(C_bit_Bank1), .wdata_tag_bits(Comp_tag_bank1),
 93 | 								.correct_prediction(correct_prediction), .inc_u_bit(inc_u_bit_bank1),.dec_u_bit(dec_u_bit_bank1),
 94 | 								.inc_c_bit(inc_c_bit_bank1), .dec_c_bit(dec_c_bit_bank1), .alloc(Alloc),.update_enable(update_enable));
 95 | 								
 96 | 	TAGE_Table#(IL,tag_len,UL,CL )  bank2(.Clk(CLK), .wr(wr), .rd(table_read_en), .index(Index_bank2), .rdata_tag_bits(tag_bank2), .rdata_u_bits(U_bit_Bank2),
 97 | 									.rdata_c_bits(C_bit_Bank2), .wdata_tag_bits(Comp_tag_bank2),
 98 | 								.correct_prediction(correct_prediction), .inc_u_bit(inc_u_bit_bank2),.dec_u_bit(dec_u_bit_bank2),
 99 | 								.inc_c_bit(inc_c_bit_bank2), .dec_c_bit(dec_c_bit_bank2), .alloc(Alloc),.update_enable(update_enable));
100 | 								
101 | 	TAGE_Table#(IL,tag_len1,UL,CL )  bank3(.Clk(CLK), .wr(wr), .rd(table_read_en), .index(Index_bank3), .rdata_tag_bits(tag_bank3), .rdata_u_bits(U_bit_Bank3),
102 | 									.rdata_c_bits(C_bit_Bank3), .wdata_tag_bits(Comp_tag_bank3),
103 | 								.correct_prediction(correct_prediction), .inc_u_bit(inc_u_bit_bank3),.dec_u_bit(dec_u_bit_bank3),
104 | 								.inc_c_bit(inc_c_bit_bank3), .dec_c_bit(dec_c_bit_bank3), .alloc(Alloc),.update_enable(update_enable));
105 | 								
106 | 	TAGE_Table#(IL,tag_len1,UL,CL )  bank4(.Clk(CLK), .wr(wr), .rd(table_read_en), .index(Index_bank4), .rdata_tag_bits(tag_bank4), .rdata_u_bits(U_bit_Bank4),
107 | 									.rdata_c_bits(C_bit_Bank4), .wdata_tag_bits(Comp_tag_bank4),
108 | 								.correct_prediction(correct_prediction), .inc_u_bit(inc_u_bit_bank4),.dec_u_bit(dec_u_bit_bank4),
109 | 								.inc_c_bit(inc_c_bit_bank4), .dec_c_bit(dec_c_bit_bank4), .alloc(Alloc),.update_enable(update_enable));
110 | 								
111 | 	wire tag_eq_bank1, tag_eq_bank2, tag_eq_bank3, tag_eq_bank4;
112 | 	
113 | 	comparator#(tag_len) Comparator_Bank1(.clk(CLK),.reset(reset), .a(Comp_tag_bank1), .b(tag_bank1), .eq(tag_eq_bank1));
114 | 	
115 | 	comparator#(tag_len) Comparator_Bank2(.clk(CLK),.reset(reset), .a(Comp_tag_bank2), .b(tag_bank2), .eq(tag_eq_bank2));
116 | 	
117 | 	comparator#(tag_len1) Comparator_Bank3(.clk(CLK),.reset(reset), .a(Comp_tag_bank3), .b(tag_bank3), .eq(tag_eq_bank3));
118 | 	
119 | 	comparator#(tag_len1) Comparator_Bank4(.clk(CLK),.reset(reset), .a(Comp_tag_bank4), .b(tag_bank4), .eq(tag_eq_bank4));
120 | 	
121 | 	wire branch_predicted;
122 | 	//overall prediction#
123 | 	prediction#(CL) prediction_1(.CLK(CLK),.reset(reset), .tag_eq_bank1(tag_eq_bank1), .tag_eq_bank2(tag_eq_bank2),
124 | 								.tag_eq_bank3(tag_eq_bank3), .tag_eq_bank4(tag_eq_bank4),
125 | 							.Bimodal_C_bit(Bimodal_C_bit), .C_bit_Bank1(C_bit_Bank1), .C_bit_Bank2(C_bit_Bank2), 
126 | 							.C_bit_Bank3(C_bit_Bank3), .C_bit_Bank4(C_bit_Bank4),.branch_prediction(branch_predicted));
127 | 							
128 | 	comparator#(1) compare_prediction(.clk(CLK),.reset(reset),.a(branch_predicted),.b(Actual_branch),.eq(correct_prediction));
129 | 	
130 | 	wire branch_pred_bank0, branch_pred_bank1, branch_pred_bank2, branch_pred_bank3, branch_pred_bank4; 
131 | 	comparator#(1) prediction_bank0(.clk(CLK), .reset(reset), .a(Bimodal_C_bit[CL-1]), .b(Actual_branch), .eq(branch_pred_bank0));
132 | 	comparator#(1) prediction_bank1(.clk(CLK), .reset(reset), .a(C_bit_Bank1[CL-1]), .b(Actual_branch), .eq(branch_pred_bank1));
133 | 	comparator#(1) prediction_bank2(.clk(CLK), .reset(reset), .a(C_bit_Bank2[CL-1]), .b(Actual_branch), .eq(branch_pred_bank2));
134 | 	comparator#(1) prediction_bank3(.clk(CLK), .reset(reset), .a(C_bit_Bank3[CL-1]), .b(Actual_branch), .eq(branch_pred_bank3));
135 | 	comparator#(1) prediction_bank4(.clk(CLK), .reset(reset), .a(C_bit_Bank4[CL-1]), .b(Actual_branch), .eq(branch_pred_bank4));
136 | 	wire dummy0;
137 | 	
138 | 	update_predictor#(UL)update_predictor1(.CLK(CLK),.Branch_predicted(branch_predicted), .Actual_branch(Actual_branch), .Alloc(Alloc),
139 | 						.u_bits_1(U_bit_Bank1), .u_bits_2(U_bit_Bank2), .u_bits_3(U_bit_Bank3), .u_bits_4(U_bit_Bank4),
140 | 						.dec_bank1(dec_u_bit_bank1), .dec_bank2(dec_u_bit_bank2), .dec_bank3(dec_u_bit_bank3), .dec_bank4(dec_u_bit_bank4),
141 | 						.inc_bank1(inc_u_bit_bank1), .inc_bank2(inc_u_bit_bank2), .inc_bank3(inc_u_bit_bank3), .inc_bank4(inc_u_bit_bank4),
142 | 						.dec_counter_bank0(dec_c_bit_Bimodal), .dec_counter_bank1(dec_c_bit_bank1), .dec_counter_bank2(dec_c_bit_bank2),
143 | 						.dec_counter_bank3(dec_c_bit_bank3), .dec_counter_bank4(dec_c_bit_bank4),
144 | 						.inc_counter_bank0(inc_c_bit_Bimodal), .inc_counter_bank1(inc_c_bit_bank1), .inc_counter_bank2(inc_c_bit_bank2),
145 | 						.inc_counter_bank3(inc_c_bit_bank3), .inc_counter_bank4(inc_c_bit_bank4),
146 | 						.prediction_bank0(dummy0), .prediction_bank1(tag_eq_bank1), .prediction_bank2(tag_eq_bank2), 
147 | 						.prediction_bank3(tag_eq_bank3), .prediction_bank4(tag_eq_bank4),
148 | 						.branch_pred_bank0(Bimodal_C_bit[CL-1]), .branch_pred_bank1(C_bit_Bank1[CL-1]),
149 | 						.branch_pred_bank2(C_bit_Bank2[CL-1]), .branch_pred_bank3(C_bit_Bank3[CL-1]),
150 | 						.branch_pred_bank4(C_bit_Bank4[CL-1]),
151 | 						.update_predictor_enable(update_predictor_enable)
152 | 						);
153 | 						
154 | 	update_history#(GlobLen,PLen,ADDRESS_SIZE)update_history1(.CLK(CLK),.reset(reset),.ghist(ghist),.phist(phist),
155 | 												.pc(pc),.Actual_branch(Actual_branch),.update_history_enable(update_enable));
156 | 	Statistics#(TRAINING_DATA_SIZE) Statistics_0(.Clk(CLK),.reset(reset), .BranchResult(correct_prediction), 
157 | 	                       .CorrectlyPredicted(CorrectlyPredicted), .TotalBranches(TotalBranches),.enable(update_enable));
158 | 	
159 | 											
160 |   
161 | endmodule
162 | 


--------------------------------------------------------------------------------
/TAGE/Source/TopLevel_testbench.v:
--------------------------------------------------------------------------------
 1 | `timescale 1ns / 1ps
 2 | //This is the testbench for checking the TAGE predictor
 3 | 
 4 | module TopLevel_tb();
 5 |     parameter ADDRESS_SIZE = 32;
 6 |    parameter TRAINING_DATA_SIZE = 4100000;
 7 |     parameter INSTRUCTION_INDEX_SIZE = $clog2(TRAINING_DATA_SIZE);
 8 |     parameter GHL = 22;
 9 |     parameter WS = 5;
10 |     parameter LS = 128;
11 |     parameter LS_INDEX_SIZE = $clog2(LS);
12 |     reg Clk, Rst;
13 |     wire BranchPrediction;
14 |     wire PredictionCorrect;
15 |     wire [INSTRUCTION_INDEX_SIZE - 1:0] CorrectlyPredicted, TotalBranches;
16 | 	reg [INSTRUCTION_INDEX_SIZE - 1:0] temp_branch=32'h00;
17 |     
18 |         
19 |     TopLevel#(ADDRESS_SIZE, TRAINING_DATA_SIZE, INSTRUCTION_INDEX_SIZE, GHL, WS, LS, LS_INDEX_SIZE) 
20 |             TopLevel_0(Clk, Rst, BranchPrediction, PredictionCorrect, CorrectlyPredicted, TotalBranches);
21 |     
22 |     initial begin
23 |             Clk <= 1'b0;
24 |         forever #1 Clk <= ~Clk;
25 |     end 
26 |     
27 |     initial begin 
28 |        Rst <= 0;
29 |        #100
30 |        Rst<=1;
31 |     end
32 | 	
33 | 	always @(TotalBranches)
34 | 	begin
35 | 		if(TotalBranches % 32'd100000==32'd000000)
36 | 			begin
37 | 			$display("The hit rate is%d ,%d, %d",CorrectlyPredicted,TotalBranches,CorrectlyPredicted-temp_branch);
38 | 			//$display("The hit rate is%d",(CorrectlyPredicted-temp_branch)/100000);
39 | 				temp_branch<=CorrectlyPredicted;
40 | 			end
41 | 	end
42 |     
43 | endmodule
44 | 


--------------------------------------------------------------------------------
/TAGE/Source/prediction.v:
--------------------------------------------------------------------------------
 1 | `timescale 1ns / 1ps
 2 | 
 3 | //This is the module for making prediction and choosing appropriate predictor
 4 | module prediction(CLK,reset, tag_eq_bank1, tag_eq_bank2,tag_eq_bank3, tag_eq_bank4,
 5 | 				 Bimodal_C_bit, C_bit_Bank1, C_bit_Bank2, C_bit_Bank3, C_bit_Bank4,branch_prediction);
 6 | 				 
 7 | parameter CL=3;
 8 | 				 
 9 | input CLK,reset;
10 | input tag_eq_bank1,tag_eq_bank2, tag_eq_bank3, tag_eq_bank4;
11 | input [ CL-1 : 0 ] Bimodal_C_bit, C_bit_Bank1, C_bit_Bank2, C_bit_Bank3, C_bit_Bank4;
12 | 
13 | output reg branch_prediction;
14 | 
15 | always @(posedge CLK)
16 | begin
17 | 	if(reset==1'b0)
18 | 		branch_prediction<=1'b0;
19 | 	else begin
20 | 		if(tag_eq_bank4==1'b1)
21 | 			branch_prediction<=C_bit_Bank4[CL-1];
22 | 		else if(tag_eq_bank3==1'b1 && tag_eq_bank4 != 1'b1)
23 | 			branch_prediction<=C_bit_Bank3[CL-1];
24 | 		else if(tag_eq_bank2==1'b1 && tag_eq_bank4 != 1'b1 && tag_eq_bank3 != 1'b1)
25 | 			branch_prediction<=C_bit_Bank2[CL-1];
26 | 		else if(tag_eq_bank1==1'b1 && tag_eq_bank2!=1'b1 && tag_eq_bank4 != 1'b1 && tag_eq_bank3 != 1'b1)
27 | 			branch_prediction<=C_bit_Bank1[CL-1];
28 | 		else 
29 | 			branch_prediction<=Bimodal_C_bit[CL-1];
30 | 	end
31 | 		
32 | end 
33 | 
34 | endmodule
35 | 


--------------------------------------------------------------------------------
/TAGE/Source/update_history.v:
--------------------------------------------------------------------------------
 1 | `timescale 1ns / 1ps
 2 | //This module is to update the Histroy of global register
 3 | 
 4 | module update_history(CLK,reset,ghist,phist,pc,Actual_branch,update_history_enable);
 5 | parameter GlobLen=131;	//This is the global history length
 6 | parameter PLen=16 ;		//this is length of path History
 7 | parameter pc_len=32;
 8 | 
 9 | input CLK,reset;
10 | input[pc_len-1 : 0] pc;
11 | input Actual_branch;
12 | input update_history_enable;
13 | output reg[GlobLen-1:0] ghist;
14 | output reg[PLen-1:0]  phist;
15 | 
16 | initial begin
17 | 	ghist<={GlobLen{1'b0}};
18 | 	phist<={PLen{1'b0}};
19 | end
20 | 
21 | always @(posedge CLK) begin
22 | 	if(reset==1'b0)begin
23 | 		ghist<={GlobLen{1'b0}};
24 | 		phist<={PLen{1'b0}};
25 | 	end
26 | 	else if(update_history_enable==1'b1)begin
27 | 		ghist<={ghist[GlobLen-2:0],Actual_branch};
28 | 		phist<={phist[PLen-1],pc[0]};
29 | 	end
30 | 	else begin
31 | 		ghist<=ghist;
32 | 		phist<=phist;
33 | 		end
34 | end
35 | 
36 | 
37 | endmodule
38 | 


--------------------------------------------------------------------------------
/TAGE/Source/update_predictor.v:
--------------------------------------------------------------------------------
  1 | `timescale 1ns / 1ps
  2 | //This module update the precictor in terms of useful bits, predictor bits and tag bits..It generates the control for respective enteries to update
  3 | module update_predictor(CLK,Branch_predicted, Actual_branch, Alloc,
  4 | 						u_bits_1, u_bits_2, u_bits_3, u_bits_4,
  5 | 						dec_bank1, dec_bank2, dec_bank3, dec_bank4,
  6 | 						inc_bank1, inc_bank2, inc_bank3, inc_bank4,
  7 | 						dec_counter_bank0, dec_counter_bank1, dec_counter_bank2, dec_counter_bank3, dec_counter_bank4,
  8 | 						inc_counter_bank0, inc_counter_bank1, inc_counter_bank2, inc_counter_bank3, inc_counter_bank4,
  9 | 						prediction_bank0, prediction_bank1, prediction_bank2, prediction_bank3, prediction_bank4,
 10 | 						branch_pred_bank0, branch_pred_bank1, branch_pred_bank2, branch_pred_bank3, branch_pred_bank4,
 11 | 						update_predictor_enable
 12 | 						);
 13 | 
 14 | 
 15 | 
 16 | 
 17 | //parameter HistLen=16;	//History length..this is like the original length
 18 | //parameter GlobLen=131;	//This is the global history length
 19 | //parameter IL=10;		//Index size ie number of addresses...this is like the compressed length
 20 | //parameter OutLen=6 ; 	//this is the length that will be thrown out at the end and wont be used...HistLen%OutLen
 21 | //parameter PLen=16 ;		//this is length of path History
 22 | //parameter pc_len=32;	//length of the program counter
 23 | //parameter pc_shift=10;// IL -(NHIS-bank-1)
 24 | parameter UL=2;			// U bits length
 25 | //parameter NHIST =1;		//compute this at top layer
 26 | //parameter Num_bank=5;	//Number of Banks
 27 | 
 28 | 
 29 | //input[pc_len-1 : 0] pc_addr;
 30 | //input[GlobLen-1:0] ghist;
 31 | //input[PLen-1:0]  phist;
 32 | input CLK;
 33 | input Branch_predicted;
 34 | input Actual_branch;
 35 | input update_predictor_enable;
 36 | 
 37 | input[UL-1:0] u_bits_1, u_bits_2, u_bits_3, u_bits_4;
 38 | 
 39 | output reg Alloc;
 40 | output reg dec_bank1;		//Decide if you it as a reg or something else..Because it might continuously decrement
 41 | output reg dec_bank2;		//else use a control loop or a controller
 42 | output reg dec_bank3;
 43 | output reg dec_bank4;
 44 | 
 45 | output reg inc_bank1;
 46 | output reg inc_bank2;
 47 | output reg inc_bank3;
 48 | output reg inc_bank4;
 49 | 
 50 | input prediction_bank0;
 51 | input prediction_bank1;		//this is just to tell which bank is selected for prediction
 52 | input prediction_bank2;
 53 | input prediction_bank3;
 54 | input prediction_bank4;
 55 | 
 56 | 
 57 | input branch_pred_bank0;					//branch prediction of the banks
 58 | input branch_pred_bank1;
 59 | input branch_pred_bank2;
 60 | input branch_pred_bank3;
 61 | input branch_pred_bank4;
 62 | 
 63 | output reg inc_counter_bank0;
 64 | output reg inc_counter_bank1;
 65 | output reg inc_counter_bank2;
 66 | output reg inc_counter_bank3;
 67 | output reg inc_counter_bank4;
 68 | 
 69 | output reg dec_counter_bank0;
 70 | output reg dec_counter_bank1;
 71 | output reg dec_counter_bank2;
 72 | output reg dec_counter_bank3;
 73 | output reg dec_counter_bank4;
 74 | 
 75 | //output reg [Num_bank-1 : 0] select_bank;	//this is to select bank whose tags will be changed
 76 | 
 77 | 
 78 | 
 79 | 	initial begin
 80 | 		Alloc=1'b0;
 81 | 	end
 82 | 
 83 | 
 84 | 	
 85 | 	always @(posedge CLK) begin
 86 | 
 87 | 		if(Branch_predicted != Actual_branch && update_predictor_enable==1'b1) 		//incorrect branch prediction
 88 | 			begin							
 89 | 			inc_bank1<=1'b0;inc_bank2<=1'b0;inc_bank3<=1'b0;inc_bank4<=1'b0;
 90 | 			if(prediction_bank1 != 1'b1 && prediction_bank2 != 1'b1 && prediction_bank3 != 1'b1 && prediction_bank4 != 1'b1)	//this is the bimodal table
 91 | 						begin
 92 | 							inc_counter_bank1 <= 1'b0; inc_counter_bank2 <= 1'b0; inc_counter_bank3 <= 1'b0; inc_counter_bank4 <= 1'b0;
 93 | 							dec_counter_bank1 <= 1'b0; dec_counter_bank2 <= 1'b0; dec_counter_bank3 <= 1'b0; dec_counter_bank4 <= 1'b0;
 94 | 							if(branch_pred_bank0==1'b1)	begin		//correct prediction that it is taken
 95 |                                   dec_counter_bank0 <= 1'b1;
 96 |                                   inc_counter_bank0 <= 1'b0;
 97 |                               end
 98 |                             else begin
 99 |                                 dec_counter_bank0 <= 1'b0;
100 |                                 inc_counter_bank0 <= 1'b1;
101 |                             end		//Branch predicted is taken,but its incorrect hence weaken it
102 | 							//Bank0_to_Update
103 | 							if(u_bits_1 != 0 && u_bits_2 != 0 && u_bits_3 !=0 &&u_bits_4 !=0)
104 | 								begin
105 | 									dec_bank1 <= 1'b1;
106 | 									dec_bank2 <= 1'b1;
107 | 									dec_bank3 <= 1'b1;
108 | 									dec_bank4 <= 1'b1;
109 | 									Alloc <= 1'b0;
110 | 								end	
111 | 							else
112 | 								begin
113 | 									Alloc <= 1'b1;
114 | 											if(u_bits_1 == 2'b00) 
115 | 												dec_bank1 <= 1'b1;	
116 | 											else
117 | 												dec_bank1 <= 1'b0;
118 | 											
119 | 											if(u_bits_2 == 2'b00 && u_bits_1 !=2'b00)
120 | 												dec_bank2 <= 1'b1;
121 | 											else
122 | 												dec_bank2 <= 1'b0;
123 | 												
124 | 											if(u_bits_3 == 2'b00 && u_bits_2 !=2'b00 && u_bits_1 !=2'b00)
125 | 												dec_bank3 <= 1'b1;
126 | 											else
127 | 												dec_bank3 <= 1'b0;
128 | 											
129 | 											if(u_bits_4 == 2'b00 && u_bits_3 !=2'b00 && u_bits_2 !=2'b00 && u_bits_1!=2'b00)
130 | 												dec_bank4 <= 1'b1;
131 | 											else
132 | 												dec_bank4 <= 1'b0;
133 | 								end
134 | 
135 | 						end
136 | 			else if(prediction_bank1 == 1'b1 && prediction_bank2 != 1'b1 && prediction_bank3 != 1'b1 && prediction_bank4 != 1'b1 )
137 | 						begin
138 | 							inc_counter_bank0 <= 1'b0; inc_counter_bank2 <= 1'b0; inc_counter_bank3 <= 1'b0; inc_counter_bank4 <= 1'b0;
139 | 							dec_counter_bank0 <= 1'b0; dec_counter_bank2 <= 1'b0; dec_counter_bank3 <= 1'b0; dec_counter_bank4 <= 1'b0;
140 | 							if(branch_pred_bank1==1'b1)	begin		//correct prediction that it is taken
141 |                                   dec_counter_bank1 <= 1'b1;
142 |                                   inc_counter_bank1 <= 1'b0;
143 |                               end
144 |                             else begin
145 |                                 dec_counter_bank1 <= 1'b0;
146 |                                 inc_counter_bank1 <= 1'b1;
147 |                             end	
148 | 										dec_bank1 <= 1'b1;
149 | 										//Bank1_to_Update
150 | 							if(u_bits_2 != 0 && u_bits_3 !=0 && u_bits_4 !=0)
151 | 								begin
152 | 									dec_bank2 <= 1'b1;
153 | 									dec_bank3 <= 1'b1;
154 | 									dec_bank4 <= 1'b1;
155 | 									Alloc <= 1'b0;
156 | 								end	
157 | 							else
158 | 								begin
159 | 									Alloc <= 1'b1;
160 | 									if(u_bits_2 == 2'b00) 
161 | 										dec_bank2 <= 1'b1;
162 | 									else
163 | 										dec_bank2 <= 1'b0;
164 | 											
165 | 									if(u_bits_3 == 2'b00 && u_bits_2 !=2'b00)
166 | 										dec_bank3 <= 1'b1;
167 | 									else
168 | 										dec_bank3 <= 1'b0;
169 | 											
170 | 									if(u_bits_4 == 2'b00 && u_bits_3 !=2'b00 && u_bits_2 !=2'b00)
171 | 										dec_bank4 <= 1'b1;
172 | 									else
173 | 										dec_bank4 <= 1'b0;
174 | 								end
175 | 						end	
176 | 			else if(prediction_bank2 == 1'b1 && prediction_bank3 != 1'b1 && prediction_bank4 != 1'b1) 
177 | 						begin
178 | 							inc_counter_bank0 <= 1'b0; inc_counter_bank1 <= 1'b0; inc_counter_bank3 <= 1'b0; inc_counter_bank4 <= 1'b0;
179 | 							dec_counter_bank0 <= 1'b0; dec_counter_bank1 <= 1'b0; dec_counter_bank3 <= 1'b0; dec_counter_bank4 <= 1'b0;
180 | 									//Branch predicted is taken,but its incorrect hence weaken it
181 | 							if(branch_pred_bank2==1'b1)	begin		//correct prediction that it is taken
182 |                                   dec_counter_bank2 <= 1'b1;
183 |                                   inc_counter_bank2 <= 1'b0;
184 |                               end
185 |                             else begin
186 |                                 dec_counter_bank2 <= 1'b0;
187 |                                 inc_counter_bank2 <= 1'b1;
188 |                             end	
189 | 							dec_bank1<=1'b0;
190 | 							dec_bank2<=1'b1;
191 | 							//Bank2_to_Update
192 | 							if(u_bits_3 !=0 && u_bits_4 !=0)
193 | 								begin
194 | 									dec_bank3 <= 1'b1;
195 | 									dec_bank4 <= 1'b1;
196 | 									Alloc <= 1'b0;
197 | 								end	
198 | 							else
199 | 								begin
200 | 									Alloc <= 1'b1;
201 | 									if(u_bits_3 == 2'b00) 
202 | 										dec_bank3 <= 1'b1;
203 | 									else
204 | 										dec_bank3 <= 1'b0;
205 | 											
206 | 									if(u_bits_4 == 2'b00 && u_bits_3 !=2'b00)
207 | 										dec_bank4 <= 1'b1;
208 | 									else
209 | 										dec_bank4 <= 1'b0;
210 | 								end
211 | 							
212 | 						end			
213 | 			else if(prediction_bank3 == 1'b1 && prediction_bank4 != 1'b1)
214 | 						begin
215 | 							inc_counter_bank0 <= 1'b0; inc_counter_bank1 <= 1'b0; inc_counter_bank2 <= 1'b0; inc_counter_bank4 <= 1'b0;
216 | 							dec_counter_bank0 <= 1'b0; dec_counter_bank1 <= 1'b0; dec_counter_bank2 <= 1'b0; dec_counter_bank4 <= 1'b0;
217 | 							//Branch predicted is taken,but its incorrect hence weaken it
218 | 							if(branch_pred_bank3==1'b1)	begin		//correct prediction that it is taken
219 |                                   dec_counter_bank3 <= 1'b1;
220 |                                   inc_counter_bank3 <= 1'b0;
221 |                               end
222 |                             else begin
223 |                                 dec_counter_bank3 <= 1'b0;
224 |                                 inc_counter_bank3 <= 1'b1;
225 |                             end	
226 | 							//Bank3_to_Update
227 | 										dec_bank1<=1'b0;
228 | 							dec_bank2<=1'b0;
229 | 							dec_bank3<=1'b1;
230 | 							if(u_bits_4 !=0)
231 | 								begin
232 | 									dec_bank4 <= 1'b1;
233 | 									Alloc <= 1'b0;
234 | 								end	
235 | 							else
236 | 								begin
237 | 									Alloc <= 1'b1;
238 | 									dec_bank4<=1'b1;
239 | 								end
240 | 
241 | 						end
242 | 			else if(prediction_bank4 == 1'b1) 
243 | 						begin
244 | 							inc_counter_bank0 <= 1'b0; inc_counter_bank1 <= 1'b0; inc_counter_bank2 <= 1'b0; inc_counter_bank3 <= 1'b0;
245 | 							dec_counter_bank0 <= 1'b0; dec_counter_bank1 <= 1'b0; dec_counter_bank2 <= 1'b0; dec_counter_bank3 <= 1'b0;
246 | 							if(branch_pred_bank4==1'b1)	begin		//correct prediction that it is taken
247 |                                   dec_counter_bank4 <= 1'b1;
248 |                                   inc_counter_bank4 <= 1'b0;
249 |                               end
250 |                             else begin
251 |                                 dec_counter_bank4 <= 1'b0;
252 |                                 inc_counter_bank4 <= 1'b1;
253 |                             end	
254 | 							dec_bank1 <= 1'b0; dec_bank2 <= 1'b0; dec_bank3 <= 1'b0; dec_bank4 <= 1'b1; 
255 | 
256 | 						end
257 | 			
258 | 		end
259 | 		else if ((Branch_predicted == Actual_branch && update_predictor_enable==1'b1) )
260 | 		begin				//Correct Branch Prediction
261 | 				//This is for Bimodal
262 | 				Alloc<=1'b0;
263 | 				if(prediction_bank1 != 1'b1 && prediction_bank2 != 1'b1 && prediction_bank3 != 1'b1 && prediction_bank4 != 1'b1)	//this is the bimodal table
264 | 						begin
265 | 							if(branch_pred_bank0==1'b1)	begin		//correct prediction that it is taken
266 |                                   inc_counter_bank0 <= 1'b1;
267 |                                   dec_counter_bank0 <= 1'b0;
268 |                               end
269 |                             else begin
270 |                                 inc_counter_bank0 <= 1'b0;
271 |                                 dec_counter_bank0 <= 1'b1;
272 |                             end		
273 | 						end
274 | 				else	
275 | 						begin
276 | 							inc_counter_bank0 <= 1'b0;
277 | 							dec_counter_bank0 <= 1'b0;
278 | 						end
279 | 						
280 | 				
281 | 				//This is for Table one
282 | 				if(prediction_bank1 == 1'b1 && prediction_bank2 != 1'b1 && prediction_bank3 != 1'b1 && prediction_bank4 != 1'b1 )
283 | 						begin
284 | 							inc_bank1 <= 1'b1;		//increse the usefulness of the bank tag
285 | 							dec_bank1 <= 1'b0;
286 | 							if(branch_pred_bank1==1'b1)	begin		//correct prediction that it is taken
287 |                                   inc_counter_bank1 <= 1'b1;
288 |                                   dec_counter_bank1 <= 1'b0;
289 |                               end
290 |                             else begin
291 |                                 inc_counter_bank1 <= 1'b0;
292 |                                 dec_counter_bank1 <= 1'b1;
293 |                             end	
294 | 						end
295 | 				else if(prediction_bank1 == 1'b1 && (prediction_bank2 == 1'b1 || prediction_bank3 == 1'b1 || prediction_bank4 == 1'b1)) begin
296 | 							inc_counter_bank1<=1'b0;
297 | 							dec_counter_bank1 <= 1'b0;
298 | 							//Counter_Update(branch_pred_bank1,inc_bank1,dec_bank1);		//When incorrect or correct prediction is made by the alternative predictor that wont be used
299 | 							if(branch_pred_bank1==Branch_predicted)	begin		
300 |                                   inc_bank1 <= 1'b1;
301 |                                   dec_bank1 <= 1'b0;
302 |                               end
303 |                             else begin
304 |                                 inc_bank1 <= 1'b0;
305 |                                 dec_bank1 <= 1'b1;
306 |                             end	
307 | 					end
308 | 				else begin
309 | 							inc_counter_bank1 <= 1'b0;
310 | 							dec_counter_bank1 <= 1'b0;
311 | 							inc_bank1 <= 1'b0;
312 | 							dec_bank1 <=1'b0;
313 | 				end
314 | 					
315 | 					
316 | 					
317 | 				//This is for table two	
318 | 				if(prediction_bank2 == 1'b1 && prediction_bank3 != 1'b1 && prediction_bank4 != 1'b1) 
319 | 						begin
320 | 							inc_bank2 <= 1'b1;
321 | 							dec_bank2<=1'b0;
322 | 							if(branch_pred_bank2==1'b1)	begin		//correct prediction that it is taken
323 |                                   inc_counter_bank2 <= 1'b1;
324 |                                   dec_counter_bank2 <= 1'b0;
325 |                               end
326 |                             else begin
327 |                                 inc_counter_bank2 <= 1'b0;
328 |                                 dec_counter_bank2 <= 1'b1;
329 |                             end	
330 | 						end
331 | 				else if(prediction_bank2 == 1'b1 && (prediction_bank3 == 1'b1 || prediction_bank4 == 1'b1))
332 | 						begin
333 | 							inc_counter_bank2<=1'b0;
334 | 							dec_counter_bank2 <= 1'b0;
335 | 							//Counter_Update(branch_pred_bank2,inc_bank2,dec_bank2);		//When incorrect or correct prediction is made by the alternative predictor that wont be used
336 | 							if(branch_pred_bank2==Branch_predicted)	begin		
337 |                                   inc_bank2 <= 1'b1;
338 |                                   dec_bank2 <= 1'b0;
339 |                               end
340 |                             else begin
341 |                                 inc_bank2 <= 1'b0;
342 |                                 dec_bank2 <= 1'b1;
343 |                             end						
344 | 						end
345 | 				else begin
346 | 							inc_counter_bank2 <= 1'b0;
347 | 							dec_counter_bank2 <= 1'b0;
348 | 							inc_bank2 <= 1'b0;
349 | 							dec_bank2 <=1'b0;
350 | 				end					
351 | 					
352 | 				//This is for Table 3	
353 | 				if(prediction_bank3 == 1'b1 && prediction_bank4 != 1'b1)
354 | 						begin
355 | 							inc_bank3 <= 1'b1;
356 | 							dec_bank3<=1'b0;
357 | 							if(branch_pred_bank3==1'b1)	begin		//correct prediction that it is taken
358 |                                   inc_counter_bank3 <= 1'b1;
359 |                                   dec_counter_bank3 <= 1'b0;
360 |                               end
361 |                             else begin
362 |                                 inc_counter_bank3 <= 1'b0;
363 |                                 dec_counter_bank3 <= 1'b1;
364 |                             end	
365 | 						end
366 | 				else if(prediction_bank3 == 1'b1 && (prediction_bank4 == 1'b1))
367 | 						begin
368 | 							inc_counter_bank3<=1'b0;
369 | 							dec_counter_bank3 <= 1'b0;
370 | 							//Counter_Update(branch_pred_bank3,inc_bank3,dec_bank3);		//When incorrect or correct prediction is made by the alternative predictor that wont be used
371 | 							if(branch_pred_bank3==Branch_predicted)	begin		
372 |                                   inc_bank3 <= 1'b1;
373 |                                   dec_bank3 <= 1'b0;
374 |                               end
375 |                             else begin
376 |                                 inc_bank3 <= 1'b0;
377 |                                 dec_bank3 <= 1'b1;
378 |                             end						
379 | 						end
380 | 				else begin
381 | 							inc_counter_bank3 <= 1'b0;
382 | 							dec_counter_bank3 <= 1'b0;
383 | 							inc_bank3 <= 1'b0;
384 | 							dec_bank3 <=1'b0;
385 | 				end								
386 | 				
387 | 				//this is for table 4
388 | 				if(prediction_bank4 == 1'b1) 
389 | 						begin
390 | 							inc_bank4 <= 1'b1;
391 | 							dec_bank4<=1'b0;
392 | 							if(branch_pred_bank4==1'b1)	begin		//correct prediction that it is taken
393 |                                   inc_counter_bank4 <= 1'b1;
394 |                                   dec_counter_bank4 <= 1'b0;
395 |                               end
396 |                             else begin
397 |                                 inc_counter_bank4 <= 1'b0;
398 |                                 dec_counter_bank4 <= 1'b1;
399 |                             end						
400 | 						end
401 | 				else begin
402 | 							inc_counter_bank4 <= 1'b0;
403 | 							dec_counter_bank4 <= 1'b0;
404 | 							inc_bank4 <= 1'b0;
405 | 							dec_bank4 <=1'b0;
406 | 				end						
407 | 				
408 | 					
409 | 			end
410 | 	
411 | 		else begin
412 | 				inc_counter_bank0 <= 1'b0; inc_counter_bank1 <= 1'b0; inc_counter_bank2 <= 1'b0; inc_counter_bank3 <= 1'b0; inc_counter_bank4 <= 1'b0;
413 | 				dec_counter_bank0 <= 1'b0; dec_counter_bank1 <= 1'b0; dec_counter_bank2 <= 1'b0; dec_counter_bank3 <= 1'b0; dec_counter_bank4 <= 1'b0;
414 | 				dec_bank1 <= 1'b0; dec_bank2 <= 1'b0; dec_bank3 <= 1'b0; dec_bank4 <= 1'b0; 
415 | 				inc_bank1 <= 1'b0; inc_bank2 <= 1'b0; inc_bank3 <= 1'b0; inc_bank4 <= 1'b0; 
416 | 				Alloc<=1'b0;
417 | 				
418 | 		end
419 | 	end
420 | endmodule
421 | 
422 | 
423 | 
424 | 
425 | 
426 | 
427 | 
428 | 
429 | 
430 | 
431 | 
432 | 
433 | 
434 | 
435 | 
436 | 
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439 | 


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