├── README.md ├── bin ├── x32 │ ├── SymbolCheck.dll │ ├── dbghelp.dll │ ├── msdia140.dll │ ├── symchk.exe │ ├── symsrv.dll │ ├── symsrv.yes │ └── symstore.exe └── x64 │ ├── SymbolCheck.dll │ ├── dbghelp.dll │ ├── msdia140.dll │ ├── symchk.exe │ ├── symsrv.dll │ ├── symsrv.yes │ └── symstore.exe ├── include ├── cvconst.h ├── dia2.h └── diacreate.h └── lib ├── x32 └── diaguids.lib └── x64 └── diaguids.lib /README.md: -------------------------------------------------------------------------------- 1 | Debug Interface Access SDK 2 | ====== 3 | 4 | DIA standas for Debug Interface Access SDK (Microsoft). 5 | 6 | Getting the binaries 7 | ====== 8 | 9 | You can get the latest binaries by cloning them from github: 10 | 11 | git clone https://github.com/milostosic/DIA.git 12 | 13 | -------------------------------------------------------------------------------- /bin/x32/SymbolCheck.dll: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/RudjiGames/DIA/93cf2af4ae986ba5ccf0fd23543f154e536b19be/bin/x32/SymbolCheck.dll -------------------------------------------------------------------------------- /bin/x32/dbghelp.dll: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/RudjiGames/DIA/93cf2af4ae986ba5ccf0fd23543f154e536b19be/bin/x32/dbghelp.dll -------------------------------------------------------------------------------- /bin/x32/msdia140.dll: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/RudjiGames/DIA/93cf2af4ae986ba5ccf0fd23543f154e536b19be/bin/x32/msdia140.dll -------------------------------------------------------------------------------- /bin/x32/symchk.exe: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/RudjiGames/DIA/93cf2af4ae986ba5ccf0fd23543f154e536b19be/bin/x32/symchk.exe -------------------------------------------------------------------------------- /bin/x32/symsrv.dll: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/RudjiGames/DIA/93cf2af4ae986ba5ccf0fd23543f154e536b19be/bin/x32/symsrv.dll -------------------------------------------------------------------------------- /bin/x32/symsrv.yes: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /bin/x32/symstore.exe: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/RudjiGames/DIA/93cf2af4ae986ba5ccf0fd23543f154e536b19be/bin/x32/symstore.exe -------------------------------------------------------------------------------- /bin/x64/SymbolCheck.dll: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/RudjiGames/DIA/93cf2af4ae986ba5ccf0fd23543f154e536b19be/bin/x64/SymbolCheck.dll -------------------------------------------------------------------------------- /bin/x64/dbghelp.dll: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/RudjiGames/DIA/93cf2af4ae986ba5ccf0fd23543f154e536b19be/bin/x64/dbghelp.dll -------------------------------------------------------------------------------- /bin/x64/msdia140.dll: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/RudjiGames/DIA/93cf2af4ae986ba5ccf0fd23543f154e536b19be/bin/x64/msdia140.dll -------------------------------------------------------------------------------- /bin/x64/symchk.exe: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/RudjiGames/DIA/93cf2af4ae986ba5ccf0fd23543f154e536b19be/bin/x64/symchk.exe -------------------------------------------------------------------------------- /bin/x64/symsrv.dll: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/RudjiGames/DIA/93cf2af4ae986ba5ccf0fd23543f154e536b19be/bin/x64/symsrv.dll -------------------------------------------------------------------------------- /bin/x64/symsrv.yes: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /bin/x64/symstore.exe: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/RudjiGames/DIA/93cf2af4ae986ba5ccf0fd23543f154e536b19be/bin/x64/symstore.exe -------------------------------------------------------------------------------- /include/cvconst.h: -------------------------------------------------------------------------------- 1 | // cvconst.h - codeview constant definitions 2 | //----------------------------------------------------------------- 3 | // 4 | // Copyright Microsoft Corporation. All Rights Reserved. 5 | // 6 | //--------------------------------------------------------------- 7 | #ifndef _CVCONST_H_ 8 | #define _CVCONST_H_ 9 | 10 | 11 | 12 | // Enumeration for function call type 13 | 14 | 15 | typedef enum CV_call_e 16 | { 17 | CV_CALL_NEAR_C = 0x00, // near right to left push, caller pops stack 18 | CV_CALL_FAR_C = 0x01, // far right to left push, caller pops stack 19 | CV_CALL_NEAR_PASCAL = 0x02, // near left to right push, callee pops stack 20 | CV_CALL_FAR_PASCAL = 0x03, // far left to right push, callee pops stack 21 | CV_CALL_NEAR_FAST = 0x04, // near left to right push with regs, callee pops stack 22 | CV_CALL_FAR_FAST = 0x05, // far left to right push with regs, callee pops stack 23 | CV_CALL_SKIPPED = 0x06, // skipped (unused) call index 24 | CV_CALL_NEAR_STD = 0x07, // near standard call 25 | CV_CALL_FAR_STD = 0x08, // far standard call 26 | CV_CALL_NEAR_SYS = 0x09, // near sys call 27 | CV_CALL_FAR_SYS = 0x0a, // far sys call 28 | CV_CALL_THISCALL = 0x0b, // this call (this passed in register) 29 | CV_CALL_MIPSCALL = 0x0c, // Mips call 30 | CV_CALL_GENERIC = 0x0d, // Generic call sequence 31 | CV_CALL_ALPHACALL = 0x0e, // Alpha call 32 | CV_CALL_PPCCALL = 0x0f, // PPC call 33 | CV_CALL_SHCALL = 0x10, // Hitachi SuperH call 34 | CV_CALL_ARMCALL = 0x11, // ARM call 35 | CV_CALL_AM33CALL = 0x12, // AM33 call 36 | CV_CALL_TRICALL = 0x13, // TriCore Call 37 | CV_CALL_SH5CALL = 0x14, // Hitachi SuperH-5 call 38 | CV_CALL_M32RCALL = 0x15, // M32R Call 39 | CV_CALL_CLRCALL = 0x16, // clr call 40 | CV_CALL_INLINE = 0x17, // Marker for routines always inlined and thus lacking a convention 41 | CV_CALL_NEAR_VECTOR = 0x18, // near left to right push with regs, callee pops stack 42 | CV_CALL_SWIFT = 0x19, // Swift calling convention 43 | CV_CALL_RESERVED = 0x20 // first unused call enumeration 44 | 45 | // Do NOT add any more machine specific conventions. This is to be used for 46 | // calling conventions in the source only (e.g. __cdecl, __stdcall). 47 | } CV_call_e; 48 | 49 | 50 | // Values for the access protection of class attributes 51 | 52 | 53 | typedef enum CV_access_e 54 | { 55 | CV_private = 1, 56 | CV_protected = 2, 57 | CV_public = 3 58 | } CV_access_e; 59 | 60 | 61 | typedef enum THUNK_ORDINAL 62 | { 63 | THUNK_ORDINAL_NOTYPE, // standard thunk 64 | THUNK_ORDINAL_ADJUSTOR, // "this" adjustor thunk 65 | THUNK_ORDINAL_VCALL, // virtual call thunk 66 | THUNK_ORDINAL_PCODE, // pcode thunk 67 | THUNK_ORDINAL_LOAD, // thunk which loads the address to jump to 68 | // via unknown means... 69 | 70 | // trampoline thunk ordinals - only for use in Trampoline thunk symbols 71 | 72 | THUNK_ORDINAL_TRAMP_INCREMENTAL, 73 | THUNK_ORDINAL_TRAMP_BRANCHISLAND, 74 | THUNK_ORDINAL_TRAMP_STRICTICF, 75 | } THUNK_ORDINAL; 76 | 77 | 78 | enum CV_SourceChksum_t 79 | { 80 | CHKSUM_TYPE_NONE = 0, // indicates no checksum is available 81 | CHKSUM_TYPE_MD5, 82 | CHKSUM_TYPE_SHA1, 83 | CHKSUM_TYPE_SHA_256, 84 | }; 85 | 86 | // 87 | // DIA enums 88 | // 89 | 90 | enum SymTagEnum 91 | { 92 | SymTagNull, 93 | SymTagExe, 94 | SymTagCompiland, 95 | SymTagCompilandDetails, 96 | SymTagCompilandEnv, 97 | SymTagFunction, 98 | SymTagBlock, 99 | SymTagData, 100 | SymTagAnnotation, 101 | SymTagLabel, 102 | SymTagPublicSymbol, 103 | SymTagUDT, 104 | SymTagEnum, 105 | SymTagFunctionType, 106 | SymTagPointerType, 107 | SymTagArrayType, 108 | SymTagBaseType, 109 | SymTagTypedef, 110 | SymTagBaseClass, 111 | SymTagFriend, 112 | SymTagFunctionArgType, 113 | SymTagFuncDebugStart, 114 | SymTagFuncDebugEnd, 115 | SymTagUsingNamespace, 116 | SymTagVTableShape, 117 | SymTagVTable, 118 | SymTagCustom, 119 | SymTagThunk, 120 | SymTagCustomType, 121 | SymTagManagedType, 122 | SymTagDimension, 123 | SymTagCallSite, 124 | SymTagInlineSite, 125 | SymTagBaseInterface, 126 | SymTagVectorType, 127 | SymTagMatrixType, 128 | SymTagHLSLType, 129 | SymTagCaller, 130 | SymTagCallee, 131 | SymTagExport, 132 | SymTagHeapAllocationSite, 133 | SymTagCoffGroup, 134 | SymTagInlinee, 135 | SymTagMax 136 | }; 137 | 138 | enum LocationType 139 | { 140 | LocIsNull, 141 | LocIsStatic, 142 | LocIsTLS, 143 | LocIsRegRel, 144 | LocIsThisRel, 145 | LocIsEnregistered, 146 | LocIsBitField, 147 | LocIsSlot, 148 | LocIsIlRel, 149 | LocInMetaData, 150 | LocIsConstant, 151 | LocIsRegRelAliasIndir, 152 | LocTypeMax 153 | }; 154 | 155 | enum DataKind 156 | { 157 | DataIsUnknown, 158 | DataIsLocal, 159 | DataIsStaticLocal, 160 | DataIsParam, 161 | DataIsObjectPtr, 162 | DataIsFileStatic, 163 | DataIsGlobal, 164 | DataIsMember, 165 | DataIsStaticMember, 166 | DataIsConstant 167 | }; 168 | 169 | enum UdtKind 170 | { 171 | UdtStruct, 172 | UdtClass, 173 | UdtUnion, 174 | UdtInterface 175 | }; 176 | 177 | enum BasicType 178 | { 179 | btNoType = 0, 180 | btVoid = 1, 181 | btChar = 2, 182 | btWChar = 3, 183 | btInt = 6, 184 | btUInt = 7, 185 | btFloat = 8, 186 | btBCD = 9, 187 | btBool = 10, 188 | btLong = 13, 189 | btULong = 14, 190 | btCurrency = 25, 191 | btDate = 26, 192 | btVariant = 27, 193 | btComplex = 28, 194 | btBit = 29, 195 | btBSTR = 30, 196 | btHresult = 31, 197 | btChar16 = 32, // char16_t 198 | btChar32 = 33, // char32_t 199 | btChar8 = 34, // char8_t 200 | }; 201 | 202 | 203 | // enumeration for type modifier values 204 | 205 | typedef enum CV_modifier_e 206 | { 207 | // 0x0000 - 0x01ff - Reserved. 208 | 209 | CV_MOD_INVALID = 0x0000, 210 | 211 | // Standard modifiers. 212 | 213 | CV_MOD_CONST = 0x0001, 214 | CV_MOD_VOLATILE = 0x0002, 215 | CV_MOD_UNALIGNED = 0x0003, 216 | 217 | // 0x0200 - 0x03ff - HLSL modifiers. 218 | 219 | CV_MOD_HLSL_UNIFORM = 0x0200, 220 | CV_MOD_HLSL_LINE = 0x0201, 221 | CV_MOD_HLSL_TRIANGLE = 0x0202, 222 | CV_MOD_HLSL_LINEADJ = 0x0203, 223 | CV_MOD_HLSL_TRIANGLEADJ = 0x0204, 224 | CV_MOD_HLSL_LINEAR = 0x0205, 225 | CV_MOD_HLSL_CENTROID = 0x0206, 226 | CV_MOD_HLSL_CONSTINTERP = 0x0207, 227 | CV_MOD_HLSL_NOPERSPECTIVE = 0x0208, 228 | CV_MOD_HLSL_SAMPLE = 0x0209, 229 | CV_MOD_HLSL_CENTER = 0x020a, 230 | CV_MOD_HLSL_SNORM = 0x020b, 231 | CV_MOD_HLSL_UNORM = 0x020c, 232 | CV_MOD_HLSL_PRECISE = 0x020d, 233 | CV_MOD_HLSL_UAV_GLOBALLY_COHERENT = 0x020e, 234 | 235 | // 0x0400 - 0xffff - Unused. 236 | 237 | } CV_modifier_e; 238 | 239 | 240 | // built-in type kinds 241 | 242 | 243 | typedef enum CV_builtin_e 244 | { 245 | // 0x0000 - 0x01ff - Reserved. 246 | CV_BI_INVALID = 0x0000, 247 | 248 | // 0x0200 - 0x03ff - HLSL types. 249 | 250 | CV_BI_HLSL_INTERFACE_POINTER = 0x0200, 251 | CV_BI_HLSL_TEXTURE1D = 0x0201, 252 | CV_BI_HLSL_TEXTURE1D_ARRAY = 0x0202, 253 | CV_BI_HLSL_TEXTURE2D = 0x0203, 254 | CV_BI_HLSL_TEXTURE2D_ARRAY = 0x0204, 255 | CV_BI_HLSL_TEXTURE3D = 0x0205, 256 | CV_BI_HLSL_TEXTURECUBE = 0x0206, 257 | CV_BI_HLSL_TEXTURECUBE_ARRAY = 0x0207, 258 | CV_BI_HLSL_TEXTURE2DMS = 0x0208, 259 | CV_BI_HLSL_TEXTURE2DMS_ARRAY = 0x0209, 260 | CV_BI_HLSL_SAMPLER = 0x020a, 261 | CV_BI_HLSL_SAMPLERCOMPARISON = 0x020b, 262 | CV_BI_HLSL_BUFFER = 0x020c, 263 | CV_BI_HLSL_POINTSTREAM = 0x020d, 264 | CV_BI_HLSL_LINESTREAM = 0x020e, 265 | CV_BI_HLSL_TRIANGLESTREAM = 0x020f, 266 | CV_BI_HLSL_INPUTPATCH = 0x0210, 267 | CV_BI_HLSL_OUTPUTPATCH = 0x0211, 268 | CV_BI_HLSL_RWTEXTURE1D = 0x0212, 269 | CV_BI_HLSL_RWTEXTURE1D_ARRAY = 0x0213, 270 | CV_BI_HLSL_RWTEXTURE2D = 0x0214, 271 | CV_BI_HLSL_RWTEXTURE2D_ARRAY = 0x0215, 272 | CV_BI_HLSL_RWTEXTURE3D = 0x0216, 273 | CV_BI_HLSL_RWBUFFER = 0x0217, 274 | CV_BI_HLSL_BYTEADDRESS_BUFFER = 0x0218, 275 | CV_BI_HLSL_RWBYTEADDRESS_BUFFER = 0x0219, 276 | CV_BI_HLSL_STRUCTURED_BUFFER = 0x021a, 277 | CV_BI_HLSL_RWSTRUCTURED_BUFFER = 0x021b, 278 | CV_BI_HLSL_APPEND_STRUCTURED_BUFFER = 0x021c, 279 | CV_BI_HLSL_CONSUME_STRUCTURED_BUFFER= 0x021d, 280 | CV_BI_HLSL_MIN8FLOAT = 0x021e, 281 | CV_BI_HLSL_MIN10FLOAT = 0x021f, 282 | CV_BI_HLSL_MIN16FLOAT = 0x0220, 283 | CV_BI_HLSL_MIN12INT = 0x0221, 284 | CV_BI_HLSL_MIN16INT = 0x0222, 285 | CV_BI_HLSL_MIN16UINT = 0x0223, 286 | CV_BI_HLSL_CONSTANT_BUFFER = 0x0224, 287 | 288 | // 0x0400 - 0xffff - Unused. 289 | 290 | } CV_builtin_e; 291 | 292 | 293 | // enum describing the compile flag source language 294 | 295 | 296 | typedef enum CV_CFL_LANG 297 | { 298 | CV_CFL_C = 0x00, 299 | CV_CFL_CXX = 0x01, 300 | CV_CFL_FORTRAN = 0x02, 301 | CV_CFL_MASM = 0x03, 302 | CV_CFL_PASCAL = 0x04, 303 | CV_CFL_BASIC = 0x05, 304 | CV_CFL_COBOL = 0x06, 305 | CV_CFL_LINK = 0x07, 306 | CV_CFL_CVTRES = 0x08, 307 | CV_CFL_CVTPGD = 0x09, 308 | CV_CFL_CSHARP = 0x0A, // C# 309 | CV_CFL_VB = 0x0B, // Visual Basic 310 | CV_CFL_ILASM = 0x0C, // IL (as in CLR) ASM 311 | CV_CFL_JAVA = 0x0D, 312 | CV_CFL_JSCRIPT = 0x0E, 313 | CV_CFL_MSIL = 0x0F, // Unknown MSIL (LTCG of .NETMODULE) 314 | CV_CFL_HLSL = 0x10, // High Level Shader Language 315 | CV_CFL_OBJC = 0x11, // Objective-C 316 | CV_CFL_OBJCXX = 0x12, // Objective-C++ 317 | CV_CFL_SWIFT = 0x13, // Swift 318 | } CV_CFL_LANG; 319 | 320 | 321 | // enum describing target processor 322 | 323 | 324 | typedef enum CV_CPU_TYPE_e 325 | { 326 | CV_CFL_8080 = 0x00, 327 | CV_CFL_8086 = 0x01, 328 | CV_CFL_80286 = 0x02, 329 | CV_CFL_80386 = 0x03, 330 | CV_CFL_80486 = 0x04, 331 | CV_CFL_PENTIUM = 0x05, 332 | CV_CFL_PENTIUMII = 0x06, 333 | CV_CFL_PENTIUMPRO = CV_CFL_PENTIUMII, 334 | CV_CFL_PENTIUMIII = 0x07, 335 | CV_CFL_MIPS = 0x10, 336 | CV_CFL_MIPSR4000 = CV_CFL_MIPS, // don't break current code 337 | CV_CFL_MIPS16 = 0x11, 338 | CV_CFL_MIPS32 = 0x12, 339 | CV_CFL_MIPS64 = 0x13, 340 | CV_CFL_MIPSI = 0x14, 341 | CV_CFL_MIPSII = 0x15, 342 | CV_CFL_MIPSIII = 0x16, 343 | CV_CFL_MIPSIV = 0x17, 344 | CV_CFL_MIPSV = 0x18, 345 | CV_CFL_M68000 = 0x20, 346 | CV_CFL_M68010 = 0x21, 347 | CV_CFL_M68020 = 0x22, 348 | CV_CFL_M68030 = 0x23, 349 | CV_CFL_M68040 = 0x24, 350 | CV_CFL_ALPHA = 0x30, 351 | CV_CFL_ALPHA_21064 = 0x30, 352 | CV_CFL_ALPHA_21164 = 0x31, 353 | CV_CFL_ALPHA_21164A = 0x32, 354 | CV_CFL_ALPHA_21264 = 0x33, 355 | CV_CFL_ALPHA_21364 = 0x34, 356 | CV_CFL_PPC601 = 0x40, 357 | CV_CFL_PPC603 = 0x41, 358 | CV_CFL_PPC604 = 0x42, 359 | CV_CFL_PPC620 = 0x43, 360 | CV_CFL_PPCFP = 0x44, 361 | CV_CFL_PPCBE = 0x45, 362 | CV_CFL_SH3 = 0x50, 363 | CV_CFL_SH3E = 0x51, 364 | CV_CFL_SH3DSP = 0x52, 365 | CV_CFL_SH4 = 0x53, 366 | CV_CFL_SHMEDIA = 0x54, 367 | CV_CFL_ARM3 = 0x60, 368 | CV_CFL_ARM4 = 0x61, 369 | CV_CFL_ARM4T = 0x62, 370 | CV_CFL_ARM5 = 0x63, 371 | CV_CFL_ARM5T = 0x64, 372 | CV_CFL_ARM6 = 0x65, 373 | CV_CFL_ARM_XMAC = 0x66, 374 | CV_CFL_ARM_WMMX = 0x67, 375 | CV_CFL_ARM7 = 0x68, 376 | CV_CFL_OMNI = 0x70, 377 | CV_CFL_IA64 = 0x80, 378 | CV_CFL_IA64_1 = 0x80, 379 | CV_CFL_IA64_2 = 0x81, 380 | CV_CFL_CEE = 0x90, 381 | CV_CFL_AM33 = 0xA0, 382 | CV_CFL_M32R = 0xB0, 383 | CV_CFL_TRICORE = 0xC0, 384 | CV_CFL_X64 = 0xD0, 385 | CV_CFL_AMD64 = CV_CFL_X64, 386 | CV_CFL_EBC = 0xE0, 387 | CV_CFL_THUMB = 0xF0, 388 | CV_CFL_ARMNT = 0xF4, 389 | CV_CFL_ARM64 = 0xF6, 390 | CV_CFL_HYBRID_X86_ARM64 = 0xF7, 391 | CV_CFL_ARM64EC = 0xF8, 392 | CV_CFL_ARM64X = 0xF9, 393 | CV_CFL_D3D11_SHADER = 0x100, 394 | } CV_CPU_TYPE_e; 395 | 396 | typedef enum CV_HREG_e 397 | { 398 | // Register subset shared by all processor types, 399 | // must not overlap with any of the ranges below, hence the high values 400 | 401 | CV_ALLREG_ERR = 30000, 402 | CV_ALLREG_TEB = 30001, 403 | CV_ALLREG_TIMER = 30002, 404 | CV_ALLREG_EFAD1 = 30003, 405 | CV_ALLREG_EFAD2 = 30004, 406 | CV_ALLREG_EFAD3 = 30005, 407 | CV_ALLREG_VFRAME= 30006, 408 | CV_ALLREG_HANDLE= 30007, 409 | CV_ALLREG_PARAMS= 30008, 410 | CV_ALLREG_LOCALS= 30009, 411 | CV_ALLREG_TID = 30010, 412 | CV_ALLREG_ENV = 30011, 413 | CV_ALLREG_CMDLN = 30012, 414 | 415 | 416 | // Register set for the Intel 80x86 and ix86 processor series 417 | // (plus PCODE registers) 418 | 419 | CV_REG_NONE = 0, 420 | CV_REG_AL = 1, 421 | CV_REG_CL = 2, 422 | CV_REG_DL = 3, 423 | CV_REG_BL = 4, 424 | CV_REG_AH = 5, 425 | CV_REG_CH = 6, 426 | CV_REG_DH = 7, 427 | CV_REG_BH = 8, 428 | CV_REG_AX = 9, 429 | CV_REG_CX = 10, 430 | CV_REG_DX = 11, 431 | CV_REG_BX = 12, 432 | CV_REG_SP = 13, 433 | CV_REG_BP = 14, 434 | CV_REG_SI = 15, 435 | CV_REG_DI = 16, 436 | CV_REG_EAX = 17, 437 | CV_REG_ECX = 18, 438 | CV_REG_EDX = 19, 439 | CV_REG_EBX = 20, 440 | CV_REG_ESP = 21, 441 | CV_REG_EBP = 22, 442 | CV_REG_ESI = 23, 443 | CV_REG_EDI = 24, 444 | CV_REG_ES = 25, 445 | CV_REG_CS = 26, 446 | CV_REG_SS = 27, 447 | CV_REG_DS = 28, 448 | CV_REG_FS = 29, 449 | CV_REG_GS = 30, 450 | CV_REG_IP = 31, 451 | CV_REG_FLAGS = 32, 452 | CV_REG_EIP = 33, 453 | CV_REG_EFLAGS = 34, 454 | CV_REG_TEMP = 40, // PCODE Temp 455 | CV_REG_TEMPH = 41, // PCODE TempH 456 | CV_REG_QUOTE = 42, // PCODE Quote 457 | CV_REG_PCDR3 = 43, // PCODE reserved 458 | CV_REG_PCDR4 = 44, // PCODE reserved 459 | CV_REG_PCDR5 = 45, // PCODE reserved 460 | CV_REG_PCDR6 = 46, // PCODE reserved 461 | CV_REG_PCDR7 = 47, // PCODE reserved 462 | CV_REG_CR0 = 80, // CR0 -- control registers 463 | CV_REG_CR1 = 81, 464 | CV_REG_CR2 = 82, 465 | CV_REG_CR3 = 83, 466 | CV_REG_CR4 = 84, // Pentium 467 | CV_REG_DR0 = 90, // Debug register 468 | CV_REG_DR1 = 91, 469 | CV_REG_DR2 = 92, 470 | CV_REG_DR3 = 93, 471 | CV_REG_DR4 = 94, 472 | CV_REG_DR5 = 95, 473 | CV_REG_DR6 = 96, 474 | CV_REG_DR7 = 97, 475 | CV_REG_GDTR = 110, 476 | CV_REG_GDTL = 111, 477 | CV_REG_IDTR = 112, 478 | CV_REG_IDTL = 113, 479 | CV_REG_LDTR = 114, 480 | CV_REG_TR = 115, 481 | 482 | CV_REG_PSEUDO1 = 116, 483 | CV_REG_PSEUDO2 = 117, 484 | CV_REG_PSEUDO3 = 118, 485 | CV_REG_PSEUDO4 = 119, 486 | CV_REG_PSEUDO5 = 120, 487 | CV_REG_PSEUDO6 = 121, 488 | CV_REG_PSEUDO7 = 122, 489 | CV_REG_PSEUDO8 = 123, 490 | CV_REG_PSEUDO9 = 124, 491 | 492 | CV_REG_ST0 = 128, 493 | CV_REG_ST1 = 129, 494 | CV_REG_ST2 = 130, 495 | CV_REG_ST3 = 131, 496 | CV_REG_ST4 = 132, 497 | CV_REG_ST5 = 133, 498 | CV_REG_ST6 = 134, 499 | CV_REG_ST7 = 135, 500 | CV_REG_CTRL = 136, 501 | CV_REG_STAT = 137, 502 | CV_REG_TAG = 138, 503 | CV_REG_FPIP = 139, 504 | CV_REG_FPCS = 140, 505 | CV_REG_FPDO = 141, 506 | CV_REG_FPDS = 142, 507 | CV_REG_ISEM = 143, 508 | CV_REG_FPEIP = 144, 509 | CV_REG_FPEDO = 145, 510 | 511 | CV_REG_MM0 = 146, 512 | CV_REG_MM1 = 147, 513 | CV_REG_MM2 = 148, 514 | CV_REG_MM3 = 149, 515 | CV_REG_MM4 = 150, 516 | CV_REG_MM5 = 151, 517 | CV_REG_MM6 = 152, 518 | CV_REG_MM7 = 153, 519 | 520 | CV_REG_XMM0 = 154, // KATMAI registers 521 | CV_REG_XMM1 = 155, 522 | CV_REG_XMM2 = 156, 523 | CV_REG_XMM3 = 157, 524 | CV_REG_XMM4 = 158, 525 | CV_REG_XMM5 = 159, 526 | CV_REG_XMM6 = 160, 527 | CV_REG_XMM7 = 161, 528 | 529 | CV_REG_XMM00 = 162, // KATMAI sub-registers 530 | CV_REG_XMM01 = 163, 531 | CV_REG_XMM02 = 164, 532 | CV_REG_XMM03 = 165, 533 | CV_REG_XMM10 = 166, 534 | CV_REG_XMM11 = 167, 535 | CV_REG_XMM12 = 168, 536 | CV_REG_XMM13 = 169, 537 | CV_REG_XMM20 = 170, 538 | CV_REG_XMM21 = 171, 539 | CV_REG_XMM22 = 172, 540 | CV_REG_XMM23 = 173, 541 | CV_REG_XMM30 = 174, 542 | CV_REG_XMM31 = 175, 543 | CV_REG_XMM32 = 176, 544 | CV_REG_XMM33 = 177, 545 | CV_REG_XMM40 = 178, 546 | CV_REG_XMM41 = 179, 547 | CV_REG_XMM42 = 180, 548 | CV_REG_XMM43 = 181, 549 | CV_REG_XMM50 = 182, 550 | CV_REG_XMM51 = 183, 551 | CV_REG_XMM52 = 184, 552 | CV_REG_XMM53 = 185, 553 | CV_REG_XMM60 = 186, 554 | CV_REG_XMM61 = 187, 555 | CV_REG_XMM62 = 188, 556 | CV_REG_XMM63 = 189, 557 | CV_REG_XMM70 = 190, 558 | CV_REG_XMM71 = 191, 559 | CV_REG_XMM72 = 192, 560 | CV_REG_XMM73 = 193, 561 | 562 | CV_REG_XMM0L = 194, 563 | CV_REG_XMM1L = 195, 564 | CV_REG_XMM2L = 196, 565 | CV_REG_XMM3L = 197, 566 | CV_REG_XMM4L = 198, 567 | CV_REG_XMM5L = 199, 568 | CV_REG_XMM6L = 200, 569 | CV_REG_XMM7L = 201, 570 | 571 | CV_REG_XMM0H = 202, 572 | CV_REG_XMM1H = 203, 573 | CV_REG_XMM2H = 204, 574 | CV_REG_XMM3H = 205, 575 | CV_REG_XMM4H = 206, 576 | CV_REG_XMM5H = 207, 577 | CV_REG_XMM6H = 208, 578 | CV_REG_XMM7H = 209, 579 | 580 | CV_REG_MXCSR = 211, // XMM status register 581 | 582 | CV_REG_EDXEAX = 212, // EDX:EAX pair 583 | 584 | CV_REG_EMM0L = 220, // XMM sub-registers (WNI integer) 585 | CV_REG_EMM1L = 221, 586 | CV_REG_EMM2L = 222, 587 | CV_REG_EMM3L = 223, 588 | CV_REG_EMM4L = 224, 589 | CV_REG_EMM5L = 225, 590 | CV_REG_EMM6L = 226, 591 | CV_REG_EMM7L = 227, 592 | 593 | CV_REG_EMM0H = 228, 594 | CV_REG_EMM1H = 229, 595 | CV_REG_EMM2H = 230, 596 | CV_REG_EMM3H = 231, 597 | CV_REG_EMM4H = 232, 598 | CV_REG_EMM5H = 233, 599 | CV_REG_EMM6H = 234, 600 | CV_REG_EMM7H = 235, 601 | 602 | // do not change the order of these regs, first one must be even too 603 | CV_REG_MM00 = 236, 604 | CV_REG_MM01 = 237, 605 | CV_REG_MM10 = 238, 606 | CV_REG_MM11 = 239, 607 | CV_REG_MM20 = 240, 608 | CV_REG_MM21 = 241, 609 | CV_REG_MM30 = 242, 610 | CV_REG_MM31 = 243, 611 | CV_REG_MM40 = 244, 612 | CV_REG_MM41 = 245, 613 | CV_REG_MM50 = 246, 614 | CV_REG_MM51 = 247, 615 | CV_REG_MM60 = 248, 616 | CV_REG_MM61 = 249, 617 | CV_REG_MM70 = 250, 618 | CV_REG_MM71 = 251, 619 | 620 | CV_REG_YMM0 = 252, // AVX registers 621 | CV_REG_YMM1 = 253, 622 | CV_REG_YMM2 = 254, 623 | CV_REG_YMM3 = 255, 624 | CV_REG_YMM4 = 256, 625 | CV_REG_YMM5 = 257, 626 | CV_REG_YMM6 = 258, 627 | CV_REG_YMM7 = 259, 628 | 629 | CV_REG_YMM0H = 260, 630 | CV_REG_YMM1H = 261, 631 | CV_REG_YMM2H = 262, 632 | CV_REG_YMM3H = 263, 633 | CV_REG_YMM4H = 264, 634 | CV_REG_YMM5H = 265, 635 | CV_REG_YMM6H = 266, 636 | CV_REG_YMM7H = 267, 637 | 638 | CV_REG_YMM0I0 = 268, // AVX integer registers 639 | CV_REG_YMM0I1 = 269, 640 | CV_REG_YMM0I2 = 270, 641 | CV_REG_YMM0I3 = 271, 642 | CV_REG_YMM1I0 = 272, 643 | CV_REG_YMM1I1 = 273, 644 | CV_REG_YMM1I2 = 274, 645 | CV_REG_YMM1I3 = 275, 646 | CV_REG_YMM2I0 = 276, 647 | CV_REG_YMM2I1 = 277, 648 | CV_REG_YMM2I2 = 278, 649 | CV_REG_YMM2I3 = 279, 650 | CV_REG_YMM3I0 = 280, 651 | CV_REG_YMM3I1 = 281, 652 | CV_REG_YMM3I2 = 282, 653 | CV_REG_YMM3I3 = 283, 654 | CV_REG_YMM4I0 = 284, 655 | CV_REG_YMM4I1 = 285, 656 | CV_REG_YMM4I2 = 286, 657 | CV_REG_YMM4I3 = 287, 658 | CV_REG_YMM5I0 = 288, 659 | CV_REG_YMM5I1 = 289, 660 | CV_REG_YMM5I2 = 290, 661 | CV_REG_YMM5I3 = 291, 662 | CV_REG_YMM6I0 = 292, 663 | CV_REG_YMM6I1 = 293, 664 | CV_REG_YMM6I2 = 294, 665 | CV_REG_YMM6I3 = 295, 666 | CV_REG_YMM7I0 = 296, 667 | CV_REG_YMM7I1 = 297, 668 | CV_REG_YMM7I2 = 298, 669 | CV_REG_YMM7I3 = 299, 670 | 671 | CV_REG_YMM0F0 = 300, // AVX floating-point single precise registers 672 | CV_REG_YMM0F1 = 301, 673 | CV_REG_YMM0F2 = 302, 674 | CV_REG_YMM0F3 = 303, 675 | CV_REG_YMM0F4 = 304, 676 | CV_REG_YMM0F5 = 305, 677 | CV_REG_YMM0F6 = 306, 678 | CV_REG_YMM0F7 = 307, 679 | CV_REG_YMM1F0 = 308, 680 | CV_REG_YMM1F1 = 309, 681 | CV_REG_YMM1F2 = 310, 682 | CV_REG_YMM1F3 = 311, 683 | CV_REG_YMM1F4 = 312, 684 | CV_REG_YMM1F5 = 313, 685 | CV_REG_YMM1F6 = 314, 686 | CV_REG_YMM1F7 = 315, 687 | CV_REG_YMM2F0 = 316, 688 | CV_REG_YMM2F1 = 317, 689 | CV_REG_YMM2F2 = 318, 690 | CV_REG_YMM2F3 = 319, 691 | CV_REG_YMM2F4 = 320, 692 | CV_REG_YMM2F5 = 321, 693 | CV_REG_YMM2F6 = 322, 694 | CV_REG_YMM2F7 = 323, 695 | CV_REG_YMM3F0 = 324, 696 | CV_REG_YMM3F1 = 325, 697 | CV_REG_YMM3F2 = 326, 698 | CV_REG_YMM3F3 = 327, 699 | CV_REG_YMM3F4 = 328, 700 | CV_REG_YMM3F5 = 329, 701 | CV_REG_YMM3F6 = 330, 702 | CV_REG_YMM3F7 = 331, 703 | CV_REG_YMM4F0 = 332, 704 | CV_REG_YMM4F1 = 333, 705 | CV_REG_YMM4F2 = 334, 706 | CV_REG_YMM4F3 = 335, 707 | CV_REG_YMM4F4 = 336, 708 | CV_REG_YMM4F5 = 337, 709 | CV_REG_YMM4F6 = 338, 710 | CV_REG_YMM4F7 = 339, 711 | CV_REG_YMM5F0 = 340, 712 | CV_REG_YMM5F1 = 341, 713 | CV_REG_YMM5F2 = 342, 714 | CV_REG_YMM5F3 = 343, 715 | CV_REG_YMM5F4 = 344, 716 | CV_REG_YMM5F5 = 345, 717 | CV_REG_YMM5F6 = 346, 718 | CV_REG_YMM5F7 = 347, 719 | CV_REG_YMM6F0 = 348, 720 | CV_REG_YMM6F1 = 349, 721 | CV_REG_YMM6F2 = 350, 722 | CV_REG_YMM6F3 = 351, 723 | CV_REG_YMM6F4 = 352, 724 | CV_REG_YMM6F5 = 353, 725 | CV_REG_YMM6F6 = 354, 726 | CV_REG_YMM6F7 = 355, 727 | CV_REG_YMM7F0 = 356, 728 | CV_REG_YMM7F1 = 357, 729 | CV_REG_YMM7F2 = 358, 730 | CV_REG_YMM7F3 = 359, 731 | CV_REG_YMM7F4 = 360, 732 | CV_REG_YMM7F5 = 361, 733 | CV_REG_YMM7F6 = 362, 734 | CV_REG_YMM7F7 = 363, 735 | 736 | CV_REG_YMM0D0 = 364, // AVX floating-point double precise registers 737 | CV_REG_YMM0D1 = 365, 738 | CV_REG_YMM0D2 = 366, 739 | CV_REG_YMM0D3 = 367, 740 | CV_REG_YMM1D0 = 368, 741 | CV_REG_YMM1D1 = 369, 742 | CV_REG_YMM1D2 = 370, 743 | CV_REG_YMM1D3 = 371, 744 | CV_REG_YMM2D0 = 372, 745 | CV_REG_YMM2D1 = 373, 746 | CV_REG_YMM2D2 = 374, 747 | CV_REG_YMM2D3 = 375, 748 | CV_REG_YMM3D0 = 376, 749 | CV_REG_YMM3D1 = 377, 750 | CV_REG_YMM3D2 = 378, 751 | CV_REG_YMM3D3 = 379, 752 | CV_REG_YMM4D0 = 380, 753 | CV_REG_YMM4D1 = 381, 754 | CV_REG_YMM4D2 = 382, 755 | CV_REG_YMM4D3 = 383, 756 | CV_REG_YMM5D0 = 384, 757 | CV_REG_YMM5D1 = 385, 758 | CV_REG_YMM5D2 = 386, 759 | CV_REG_YMM5D3 = 387, 760 | CV_REG_YMM6D0 = 388, 761 | CV_REG_YMM6D1 = 389, 762 | CV_REG_YMM6D2 = 390, 763 | CV_REG_YMM6D3 = 391, 764 | CV_REG_YMM7D0 = 392, 765 | CV_REG_YMM7D1 = 393, 766 | CV_REG_YMM7D2 = 394, 767 | CV_REG_YMM7D3 = 395, 768 | 769 | CV_REG_BND0 = 396, // x86 MPX bounds registers 770 | CV_REG_BND1 = 397, 771 | CV_REG_BND2 = 398, 772 | CV_REG_BND3 = 399, 773 | CV_REG_BNDCFGU = 400, 774 | CV_REG_BNDSTATUS = 401, 775 | 776 | CV_REG_ZMM0 = 402, // AVX-512 registers 777 | CV_REG_ZMM1 = 403, 778 | CV_REG_ZMM2 = 404, 779 | CV_REG_ZMM3 = 405, 780 | CV_REG_ZMM4 = 406, 781 | CV_REG_ZMM5 = 407, 782 | CV_REG_ZMM6 = 408, 783 | CV_REG_ZMM7 = 409, 784 | 785 | CV_REG_ZMM0H = 410, 786 | CV_REG_ZMM1H = 411, 787 | CV_REG_ZMM2H = 412, 788 | CV_REG_ZMM3H = 413, 789 | CV_REG_ZMM4H = 414, 790 | CV_REG_ZMM5H = 415, 791 | CV_REG_ZMM6H = 416, 792 | CV_REG_ZMM7H = 417, 793 | 794 | CV_REG_K0 = 418, 795 | CV_REG_K1 = 419, 796 | CV_REG_K2 = 420, 797 | CV_REG_K3 = 421, 798 | CV_REG_K4 = 422, 799 | CV_REG_K5 = 423, 800 | CV_REG_K6 = 424, 801 | CV_REG_K7 = 425, 802 | 803 | CV_REG_SSP = 426, // CET- Shadow Stack Pointer 804 | 805 | // registers for the 68K processors 806 | 807 | CV_R68_D0 = 0, 808 | CV_R68_D1 = 1, 809 | CV_R68_D2 = 2, 810 | CV_R68_D3 = 3, 811 | CV_R68_D4 = 4, 812 | CV_R68_D5 = 5, 813 | CV_R68_D6 = 6, 814 | CV_R68_D7 = 7, 815 | CV_R68_A0 = 8, 816 | CV_R68_A1 = 9, 817 | CV_R68_A2 = 10, 818 | CV_R68_A3 = 11, 819 | CV_R68_A4 = 12, 820 | CV_R68_A5 = 13, 821 | CV_R68_A6 = 14, 822 | CV_R68_A7 = 15, 823 | CV_R68_CCR = 16, 824 | CV_R68_SR = 17, 825 | CV_R68_USP = 18, 826 | CV_R68_MSP = 19, 827 | CV_R68_SFC = 20, 828 | CV_R68_DFC = 21, 829 | CV_R68_CACR = 22, 830 | CV_R68_VBR = 23, 831 | CV_R68_CAAR = 24, 832 | CV_R68_ISP = 25, 833 | CV_R68_PC = 26, 834 | //reserved 27 835 | CV_R68_FPCR = 28, 836 | CV_R68_FPSR = 29, 837 | CV_R68_FPIAR = 30, 838 | //reserved 31 839 | CV_R68_FP0 = 32, 840 | CV_R68_FP1 = 33, 841 | CV_R68_FP2 = 34, 842 | CV_R68_FP3 = 35, 843 | CV_R68_FP4 = 36, 844 | CV_R68_FP5 = 37, 845 | CV_R68_FP6 = 38, 846 | CV_R68_FP7 = 39, 847 | //reserved 40 848 | CV_R68_MMUSR030 = 41, 849 | CV_R68_MMUSR = 42, 850 | CV_R68_URP = 43, 851 | CV_R68_DTT0 = 44, 852 | CV_R68_DTT1 = 45, 853 | CV_R68_ITT0 = 46, 854 | CV_R68_ITT1 = 47, 855 | //reserved 50 856 | CV_R68_PSR = 51, 857 | CV_R68_PCSR = 52, 858 | CV_R68_VAL = 53, 859 | CV_R68_CRP = 54, 860 | CV_R68_SRP = 55, 861 | CV_R68_DRP = 56, 862 | CV_R68_TC = 57, 863 | CV_R68_AC = 58, 864 | CV_R68_SCC = 59, 865 | CV_R68_CAL = 60, 866 | CV_R68_TT0 = 61, 867 | CV_R68_TT1 = 62, 868 | //reserved 63 869 | CV_R68_BAD0 = 64, 870 | CV_R68_BAD1 = 65, 871 | CV_R68_BAD2 = 66, 872 | CV_R68_BAD3 = 67, 873 | CV_R68_BAD4 = 68, 874 | CV_R68_BAD5 = 69, 875 | CV_R68_BAD6 = 70, 876 | CV_R68_BAD7 = 71, 877 | CV_R68_BAC0 = 72, 878 | CV_R68_BAC1 = 73, 879 | CV_R68_BAC2 = 74, 880 | CV_R68_BAC3 = 75, 881 | CV_R68_BAC4 = 76, 882 | CV_R68_BAC5 = 77, 883 | CV_R68_BAC6 = 78, 884 | CV_R68_BAC7 = 79, 885 | 886 | // Register set for the MIPS 4000 887 | 888 | CV_M4_NOREG = CV_REG_NONE, 889 | 890 | CV_M4_IntZERO = 10, /* CPU REGISTER */ 891 | CV_M4_IntAT = 11, 892 | CV_M4_IntV0 = 12, 893 | CV_M4_IntV1 = 13, 894 | CV_M4_IntA0 = 14, 895 | CV_M4_IntA1 = 15, 896 | CV_M4_IntA2 = 16, 897 | CV_M4_IntA3 = 17, 898 | CV_M4_IntT0 = 18, 899 | CV_M4_IntT1 = 19, 900 | CV_M4_IntT2 = 20, 901 | CV_M4_IntT3 = 21, 902 | CV_M4_IntT4 = 22, 903 | CV_M4_IntT5 = 23, 904 | CV_M4_IntT6 = 24, 905 | CV_M4_IntT7 = 25, 906 | CV_M4_IntS0 = 26, 907 | CV_M4_IntS1 = 27, 908 | CV_M4_IntS2 = 28, 909 | CV_M4_IntS3 = 29, 910 | CV_M4_IntS4 = 30, 911 | CV_M4_IntS5 = 31, 912 | CV_M4_IntS6 = 32, 913 | CV_M4_IntS7 = 33, 914 | CV_M4_IntT8 = 34, 915 | CV_M4_IntT9 = 35, 916 | CV_M4_IntKT0 = 36, 917 | CV_M4_IntKT1 = 37, 918 | CV_M4_IntGP = 38, 919 | CV_M4_IntSP = 39, 920 | CV_M4_IntS8 = 40, 921 | CV_M4_IntRA = 41, 922 | CV_M4_IntLO = 42, 923 | CV_M4_IntHI = 43, 924 | 925 | CV_M4_Fir = 50, 926 | CV_M4_Psr = 51, 927 | 928 | CV_M4_FltF0 = 60, /* Floating point registers */ 929 | CV_M4_FltF1 = 61, 930 | CV_M4_FltF2 = 62, 931 | CV_M4_FltF3 = 63, 932 | CV_M4_FltF4 = 64, 933 | CV_M4_FltF5 = 65, 934 | CV_M4_FltF6 = 66, 935 | CV_M4_FltF7 = 67, 936 | CV_M4_FltF8 = 68, 937 | CV_M4_FltF9 = 69, 938 | CV_M4_FltF10 = 70, 939 | CV_M4_FltF11 = 71, 940 | CV_M4_FltF12 = 72, 941 | CV_M4_FltF13 = 73, 942 | CV_M4_FltF14 = 74, 943 | CV_M4_FltF15 = 75, 944 | CV_M4_FltF16 = 76, 945 | CV_M4_FltF17 = 77, 946 | CV_M4_FltF18 = 78, 947 | CV_M4_FltF19 = 79, 948 | CV_M4_FltF20 = 80, 949 | CV_M4_FltF21 = 81, 950 | CV_M4_FltF22 = 82, 951 | CV_M4_FltF23 = 83, 952 | CV_M4_FltF24 = 84, 953 | CV_M4_FltF25 = 85, 954 | CV_M4_FltF26 = 86, 955 | CV_M4_FltF27 = 87, 956 | CV_M4_FltF28 = 88, 957 | CV_M4_FltF29 = 89, 958 | CV_M4_FltF30 = 90, 959 | CV_M4_FltF31 = 91, 960 | CV_M4_FltFsr = 92, 961 | 962 | 963 | // Register set for the ALPHA AXP 964 | 965 | CV_ALPHA_NOREG = CV_REG_NONE, 966 | 967 | CV_ALPHA_FltF0 = 10, // Floating point registers 968 | CV_ALPHA_FltF1 = 11, 969 | CV_ALPHA_FltF2 = 12, 970 | CV_ALPHA_FltF3 = 13, 971 | CV_ALPHA_FltF4 = 14, 972 | CV_ALPHA_FltF5 = 15, 973 | CV_ALPHA_FltF6 = 16, 974 | CV_ALPHA_FltF7 = 17, 975 | CV_ALPHA_FltF8 = 18, 976 | CV_ALPHA_FltF9 = 19, 977 | CV_ALPHA_FltF10 = 20, 978 | CV_ALPHA_FltF11 = 21, 979 | CV_ALPHA_FltF12 = 22, 980 | CV_ALPHA_FltF13 = 23, 981 | CV_ALPHA_FltF14 = 24, 982 | CV_ALPHA_FltF15 = 25, 983 | CV_ALPHA_FltF16 = 26, 984 | CV_ALPHA_FltF17 = 27, 985 | CV_ALPHA_FltF18 = 28, 986 | CV_ALPHA_FltF19 = 29, 987 | CV_ALPHA_FltF20 = 30, 988 | CV_ALPHA_FltF21 = 31, 989 | CV_ALPHA_FltF22 = 32, 990 | CV_ALPHA_FltF23 = 33, 991 | CV_ALPHA_FltF24 = 34, 992 | CV_ALPHA_FltF25 = 35, 993 | CV_ALPHA_FltF26 = 36, 994 | CV_ALPHA_FltF27 = 37, 995 | CV_ALPHA_FltF28 = 38, 996 | CV_ALPHA_FltF29 = 39, 997 | CV_ALPHA_FltF30 = 40, 998 | CV_ALPHA_FltF31 = 41, 999 | 1000 | CV_ALPHA_IntV0 = 42, // Integer registers 1001 | CV_ALPHA_IntT0 = 43, 1002 | CV_ALPHA_IntT1 = 44, 1003 | CV_ALPHA_IntT2 = 45, 1004 | CV_ALPHA_IntT3 = 46, 1005 | CV_ALPHA_IntT4 = 47, 1006 | CV_ALPHA_IntT5 = 48, 1007 | CV_ALPHA_IntT6 = 49, 1008 | CV_ALPHA_IntT7 = 50, 1009 | CV_ALPHA_IntS0 = 51, 1010 | CV_ALPHA_IntS1 = 52, 1011 | CV_ALPHA_IntS2 = 53, 1012 | CV_ALPHA_IntS3 = 54, 1013 | CV_ALPHA_IntS4 = 55, 1014 | CV_ALPHA_IntS5 = 56, 1015 | CV_ALPHA_IntFP = 57, 1016 | CV_ALPHA_IntA0 = 58, 1017 | CV_ALPHA_IntA1 = 59, 1018 | CV_ALPHA_IntA2 = 60, 1019 | CV_ALPHA_IntA3 = 61, 1020 | CV_ALPHA_IntA4 = 62, 1021 | CV_ALPHA_IntA5 = 63, 1022 | CV_ALPHA_IntT8 = 64, 1023 | CV_ALPHA_IntT9 = 65, 1024 | CV_ALPHA_IntT10 = 66, 1025 | CV_ALPHA_IntT11 = 67, 1026 | CV_ALPHA_IntRA = 68, 1027 | CV_ALPHA_IntT12 = 69, 1028 | CV_ALPHA_IntAT = 70, 1029 | CV_ALPHA_IntGP = 71, 1030 | CV_ALPHA_IntSP = 72, 1031 | CV_ALPHA_IntZERO = 73, 1032 | 1033 | 1034 | CV_ALPHA_Fpcr = 74, // Control registers 1035 | CV_ALPHA_Fir = 75, 1036 | CV_ALPHA_Psr = 76, 1037 | CV_ALPHA_FltFsr = 77, 1038 | CV_ALPHA_SoftFpcr = 78, 1039 | 1040 | // Register Set for Motorola/IBM PowerPC 1041 | 1042 | /* 1043 | ** PowerPC General Registers ( User Level ) 1044 | */ 1045 | CV_PPC_GPR0 = 1, 1046 | CV_PPC_GPR1 = 2, 1047 | CV_PPC_GPR2 = 3, 1048 | CV_PPC_GPR3 = 4, 1049 | CV_PPC_GPR4 = 5, 1050 | CV_PPC_GPR5 = 6, 1051 | CV_PPC_GPR6 = 7, 1052 | CV_PPC_GPR7 = 8, 1053 | CV_PPC_GPR8 = 9, 1054 | CV_PPC_GPR9 = 10, 1055 | CV_PPC_GPR10 = 11, 1056 | CV_PPC_GPR11 = 12, 1057 | CV_PPC_GPR12 = 13, 1058 | CV_PPC_GPR13 = 14, 1059 | CV_PPC_GPR14 = 15, 1060 | CV_PPC_GPR15 = 16, 1061 | CV_PPC_GPR16 = 17, 1062 | CV_PPC_GPR17 = 18, 1063 | CV_PPC_GPR18 = 19, 1064 | CV_PPC_GPR19 = 20, 1065 | CV_PPC_GPR20 = 21, 1066 | CV_PPC_GPR21 = 22, 1067 | CV_PPC_GPR22 = 23, 1068 | CV_PPC_GPR23 = 24, 1069 | CV_PPC_GPR24 = 25, 1070 | CV_PPC_GPR25 = 26, 1071 | CV_PPC_GPR26 = 27, 1072 | CV_PPC_GPR27 = 28, 1073 | CV_PPC_GPR28 = 29, 1074 | CV_PPC_GPR29 = 30, 1075 | CV_PPC_GPR30 = 31, 1076 | CV_PPC_GPR31 = 32, 1077 | 1078 | /* 1079 | ** PowerPC Condition Register ( User Level ) 1080 | */ 1081 | CV_PPC_CR = 33, 1082 | CV_PPC_CR0 = 34, 1083 | CV_PPC_CR1 = 35, 1084 | CV_PPC_CR2 = 36, 1085 | CV_PPC_CR3 = 37, 1086 | CV_PPC_CR4 = 38, 1087 | CV_PPC_CR5 = 39, 1088 | CV_PPC_CR6 = 40, 1089 | CV_PPC_CR7 = 41, 1090 | 1091 | /* 1092 | ** PowerPC Floating Point Registers ( User Level ) 1093 | */ 1094 | CV_PPC_FPR0 = 42, 1095 | CV_PPC_FPR1 = 43, 1096 | CV_PPC_FPR2 = 44, 1097 | CV_PPC_FPR3 = 45, 1098 | CV_PPC_FPR4 = 46, 1099 | CV_PPC_FPR5 = 47, 1100 | CV_PPC_FPR6 = 48, 1101 | CV_PPC_FPR7 = 49, 1102 | CV_PPC_FPR8 = 50, 1103 | CV_PPC_FPR9 = 51, 1104 | CV_PPC_FPR10 = 52, 1105 | CV_PPC_FPR11 = 53, 1106 | CV_PPC_FPR12 = 54, 1107 | CV_PPC_FPR13 = 55, 1108 | CV_PPC_FPR14 = 56, 1109 | CV_PPC_FPR15 = 57, 1110 | CV_PPC_FPR16 = 58, 1111 | CV_PPC_FPR17 = 59, 1112 | CV_PPC_FPR18 = 60, 1113 | CV_PPC_FPR19 = 61, 1114 | CV_PPC_FPR20 = 62, 1115 | CV_PPC_FPR21 = 63, 1116 | CV_PPC_FPR22 = 64, 1117 | CV_PPC_FPR23 = 65, 1118 | CV_PPC_FPR24 = 66, 1119 | CV_PPC_FPR25 = 67, 1120 | CV_PPC_FPR26 = 68, 1121 | CV_PPC_FPR27 = 69, 1122 | CV_PPC_FPR28 = 70, 1123 | CV_PPC_FPR29 = 71, 1124 | CV_PPC_FPR30 = 72, 1125 | CV_PPC_FPR31 = 73, 1126 | 1127 | /* 1128 | ** PowerPC Floating Point Status and Control Register ( User Level ) 1129 | */ 1130 | CV_PPC_FPSCR = 74, 1131 | 1132 | /* 1133 | ** PowerPC Machine State Register ( Supervisor Level ) 1134 | */ 1135 | CV_PPC_MSR = 75, 1136 | 1137 | /* 1138 | ** PowerPC Segment Registers ( Supervisor Level ) 1139 | */ 1140 | CV_PPC_SR0 = 76, 1141 | CV_PPC_SR1 = 77, 1142 | CV_PPC_SR2 = 78, 1143 | CV_PPC_SR3 = 79, 1144 | CV_PPC_SR4 = 80, 1145 | CV_PPC_SR5 = 81, 1146 | CV_PPC_SR6 = 82, 1147 | CV_PPC_SR7 = 83, 1148 | CV_PPC_SR8 = 84, 1149 | CV_PPC_SR9 = 85, 1150 | CV_PPC_SR10 = 86, 1151 | CV_PPC_SR11 = 87, 1152 | CV_PPC_SR12 = 88, 1153 | CV_PPC_SR13 = 89, 1154 | CV_PPC_SR14 = 90, 1155 | CV_PPC_SR15 = 91, 1156 | 1157 | /* 1158 | ** For all of the special purpose registers add 100 to the SPR# that the 1159 | ** Motorola/IBM documentation gives with the exception of any imaginary 1160 | ** registers. 1161 | */ 1162 | 1163 | /* 1164 | ** PowerPC Special Purpose Registers ( User Level ) 1165 | */ 1166 | CV_PPC_PC = 99, // PC (imaginary register) 1167 | 1168 | CV_PPC_MQ = 100, // MPC601 1169 | CV_PPC_XER = 101, 1170 | CV_PPC_RTCU = 104, // MPC601 1171 | CV_PPC_RTCL = 105, // MPC601 1172 | CV_PPC_LR = 108, 1173 | CV_PPC_CTR = 109, 1174 | 1175 | CV_PPC_COMPARE = 110, // part of XER (internal to the debugger only) 1176 | CV_PPC_COUNT = 111, // part of XER (internal to the debugger only) 1177 | 1178 | /* 1179 | ** PowerPC Special Purpose Registers ( Supervisor Level ) 1180 | */ 1181 | CV_PPC_DSISR = 118, 1182 | CV_PPC_DAR = 119, 1183 | CV_PPC_DEC = 122, 1184 | CV_PPC_SDR1 = 125, 1185 | CV_PPC_SRR0 = 126, 1186 | CV_PPC_SRR1 = 127, 1187 | CV_PPC_SPRG0 = 372, 1188 | CV_PPC_SPRG1 = 373, 1189 | CV_PPC_SPRG2 = 374, 1190 | CV_PPC_SPRG3 = 375, 1191 | CV_PPC_ASR = 280, // 64-bit implementations only 1192 | CV_PPC_EAR = 382, 1193 | CV_PPC_PVR = 287, 1194 | CV_PPC_BAT0U = 628, 1195 | CV_PPC_BAT0L = 629, 1196 | CV_PPC_BAT1U = 630, 1197 | CV_PPC_BAT1L = 631, 1198 | CV_PPC_BAT2U = 632, 1199 | CV_PPC_BAT2L = 633, 1200 | CV_PPC_BAT3U = 634, 1201 | CV_PPC_BAT3L = 635, 1202 | CV_PPC_DBAT0U = 636, 1203 | CV_PPC_DBAT0L = 637, 1204 | CV_PPC_DBAT1U = 638, 1205 | CV_PPC_DBAT1L = 639, 1206 | CV_PPC_DBAT2U = 640, 1207 | CV_PPC_DBAT2L = 641, 1208 | CV_PPC_DBAT3U = 642, 1209 | CV_PPC_DBAT3L = 643, 1210 | 1211 | /* 1212 | ** PowerPC Special Purpose Registers Implementation Dependent ( Supervisor Level ) 1213 | */ 1214 | 1215 | /* 1216 | ** Doesn't appear that IBM/Motorola has finished defining these. 1217 | */ 1218 | 1219 | CV_PPC_PMR0 = 1044, // MPC620, 1220 | CV_PPC_PMR1 = 1045, // MPC620, 1221 | CV_PPC_PMR2 = 1046, // MPC620, 1222 | CV_PPC_PMR3 = 1047, // MPC620, 1223 | CV_PPC_PMR4 = 1048, // MPC620, 1224 | CV_PPC_PMR5 = 1049, // MPC620, 1225 | CV_PPC_PMR6 = 1050, // MPC620, 1226 | CV_PPC_PMR7 = 1051, // MPC620, 1227 | CV_PPC_PMR8 = 1052, // MPC620, 1228 | CV_PPC_PMR9 = 1053, // MPC620, 1229 | CV_PPC_PMR10 = 1054, // MPC620, 1230 | CV_PPC_PMR11 = 1055, // MPC620, 1231 | CV_PPC_PMR12 = 1056, // MPC620, 1232 | CV_PPC_PMR13 = 1057, // MPC620, 1233 | CV_PPC_PMR14 = 1058, // MPC620, 1234 | CV_PPC_PMR15 = 1059, // MPC620, 1235 | 1236 | CV_PPC_DMISS = 1076, // MPC603 1237 | CV_PPC_DCMP = 1077, // MPC603 1238 | CV_PPC_HASH1 = 1078, // MPC603 1239 | CV_PPC_HASH2 = 1079, // MPC603 1240 | CV_PPC_IMISS = 1080, // MPC603 1241 | CV_PPC_ICMP = 1081, // MPC603 1242 | CV_PPC_RPA = 1082, // MPC603 1243 | 1244 | CV_PPC_HID0 = 1108, // MPC601, MPC603, MPC620 1245 | CV_PPC_HID1 = 1109, // MPC601 1246 | CV_PPC_HID2 = 1110, // MPC601, MPC603, MPC620 ( IABR ) 1247 | CV_PPC_HID3 = 1111, // Not Defined 1248 | CV_PPC_HID4 = 1112, // Not Defined 1249 | CV_PPC_HID5 = 1113, // MPC601, MPC604, MPC620 ( DABR ) 1250 | CV_PPC_HID6 = 1114, // Not Defined 1251 | CV_PPC_HID7 = 1115, // Not Defined 1252 | CV_PPC_HID8 = 1116, // MPC620 ( BUSCSR ) 1253 | CV_PPC_HID9 = 1117, // MPC620 ( L2CSR ) 1254 | CV_PPC_HID10 = 1118, // Not Defined 1255 | CV_PPC_HID11 = 1119, // Not Defined 1256 | CV_PPC_HID12 = 1120, // Not Defined 1257 | CV_PPC_HID13 = 1121, // MPC604 ( HCR ) 1258 | CV_PPC_HID14 = 1122, // Not Defined 1259 | CV_PPC_HID15 = 1123, // MPC601, MPC604, MPC620 ( PIR ) 1260 | 1261 | // 1262 | // JAVA VM registers 1263 | // 1264 | 1265 | CV_JAVA_PC = 1, 1266 | 1267 | // 1268 | // Register set for the Hitachi SH3 1269 | // 1270 | 1271 | CV_SH3_NOREG = CV_REG_NONE, 1272 | 1273 | CV_SH3_IntR0 = 10, // CPU REGISTER 1274 | CV_SH3_IntR1 = 11, 1275 | CV_SH3_IntR2 = 12, 1276 | CV_SH3_IntR3 = 13, 1277 | CV_SH3_IntR4 = 14, 1278 | CV_SH3_IntR5 = 15, 1279 | CV_SH3_IntR6 = 16, 1280 | CV_SH3_IntR7 = 17, 1281 | CV_SH3_IntR8 = 18, 1282 | CV_SH3_IntR9 = 19, 1283 | CV_SH3_IntR10 = 20, 1284 | CV_SH3_IntR11 = 21, 1285 | CV_SH3_IntR12 = 22, 1286 | CV_SH3_IntR13 = 23, 1287 | CV_SH3_IntFp = 24, 1288 | CV_SH3_IntSp = 25, 1289 | CV_SH3_Gbr = 38, 1290 | CV_SH3_Pr = 39, 1291 | CV_SH3_Mach = 40, 1292 | CV_SH3_Macl = 41, 1293 | 1294 | CV_SH3_Pc = 50, 1295 | CV_SH3_Sr = 51, 1296 | 1297 | CV_SH3_BarA = 60, 1298 | CV_SH3_BasrA = 61, 1299 | CV_SH3_BamrA = 62, 1300 | CV_SH3_BbrA = 63, 1301 | CV_SH3_BarB = 64, 1302 | CV_SH3_BasrB = 65, 1303 | CV_SH3_BamrB = 66, 1304 | CV_SH3_BbrB = 67, 1305 | CV_SH3_BdrB = 68, 1306 | CV_SH3_BdmrB = 69, 1307 | CV_SH3_Brcr = 70, 1308 | 1309 | // 1310 | // Additional registers for Hitachi SH processors 1311 | // 1312 | 1313 | CV_SH_Fpscr = 75, // floating point status/control register 1314 | CV_SH_Fpul = 76, // floating point communication register 1315 | 1316 | CV_SH_FpR0 = 80, // Floating point registers 1317 | CV_SH_FpR1 = 81, 1318 | CV_SH_FpR2 = 82, 1319 | CV_SH_FpR3 = 83, 1320 | CV_SH_FpR4 = 84, 1321 | CV_SH_FpR5 = 85, 1322 | CV_SH_FpR6 = 86, 1323 | CV_SH_FpR7 = 87, 1324 | CV_SH_FpR8 = 88, 1325 | CV_SH_FpR9 = 89, 1326 | CV_SH_FpR10 = 90, 1327 | CV_SH_FpR11 = 91, 1328 | CV_SH_FpR12 = 92, 1329 | CV_SH_FpR13 = 93, 1330 | CV_SH_FpR14 = 94, 1331 | CV_SH_FpR15 = 95, 1332 | 1333 | CV_SH_XFpR0 = 96, 1334 | CV_SH_XFpR1 = 97, 1335 | CV_SH_XFpR2 = 98, 1336 | CV_SH_XFpR3 = 99, 1337 | CV_SH_XFpR4 = 100, 1338 | CV_SH_XFpR5 = 101, 1339 | CV_SH_XFpR6 = 102, 1340 | CV_SH_XFpR7 = 103, 1341 | CV_SH_XFpR8 = 104, 1342 | CV_SH_XFpR9 = 105, 1343 | CV_SH_XFpR10 = 106, 1344 | CV_SH_XFpR11 = 107, 1345 | CV_SH_XFpR12 = 108, 1346 | CV_SH_XFpR13 = 109, 1347 | CV_SH_XFpR14 = 110, 1348 | CV_SH_XFpR15 = 111, 1349 | 1350 | // 1351 | // Register set for the ARM processor. 1352 | // 1353 | 1354 | CV_ARM_NOREG = CV_REG_NONE, 1355 | 1356 | CV_ARM_R0 = 10, 1357 | CV_ARM_R1 = 11, 1358 | CV_ARM_R2 = 12, 1359 | CV_ARM_R3 = 13, 1360 | CV_ARM_R4 = 14, 1361 | CV_ARM_R5 = 15, 1362 | CV_ARM_R6 = 16, 1363 | CV_ARM_R7 = 17, 1364 | CV_ARM_R8 = 18, 1365 | CV_ARM_R9 = 19, 1366 | CV_ARM_R10 = 20, 1367 | CV_ARM_R11 = 21, // Frame pointer, if allocated 1368 | CV_ARM_R12 = 22, 1369 | CV_ARM_SP = 23, // Stack pointer 1370 | CV_ARM_LR = 24, // Link Register 1371 | CV_ARM_PC = 25, // Program counter 1372 | CV_ARM_CPSR = 26, // Current program status register 1373 | 1374 | CV_ARM_ACC0 = 27, // DSP co-processor 0 40 bit accumulator 1375 | 1376 | // 1377 | // Registers for ARM VFP10 support 1378 | // 1379 | 1380 | CV_ARM_FPSCR = 40, 1381 | CV_ARM_FPEXC = 41, 1382 | 1383 | CV_ARM_FS0 = 50, 1384 | CV_ARM_FS1 = 51, 1385 | CV_ARM_FS2 = 52, 1386 | CV_ARM_FS3 = 53, 1387 | CV_ARM_FS4 = 54, 1388 | CV_ARM_FS5 = 55, 1389 | CV_ARM_FS6 = 56, 1390 | CV_ARM_FS7 = 57, 1391 | CV_ARM_FS8 = 58, 1392 | CV_ARM_FS9 = 59, 1393 | CV_ARM_FS10 = 60, 1394 | CV_ARM_FS11 = 61, 1395 | CV_ARM_FS12 = 62, 1396 | CV_ARM_FS13 = 63, 1397 | CV_ARM_FS14 = 64, 1398 | CV_ARM_FS15 = 65, 1399 | CV_ARM_FS16 = 66, 1400 | CV_ARM_FS17 = 67, 1401 | CV_ARM_FS18 = 68, 1402 | CV_ARM_FS19 = 69, 1403 | CV_ARM_FS20 = 70, 1404 | CV_ARM_FS21 = 71, 1405 | CV_ARM_FS22 = 72, 1406 | CV_ARM_FS23 = 73, 1407 | CV_ARM_FS24 = 74, 1408 | CV_ARM_FS25 = 75, 1409 | CV_ARM_FS26 = 76, 1410 | CV_ARM_FS27 = 77, 1411 | CV_ARM_FS28 = 78, 1412 | CV_ARM_FS29 = 79, 1413 | CV_ARM_FS30 = 80, 1414 | CV_ARM_FS31 = 81, 1415 | 1416 | // 1417 | // ARM VFP Floating Point Extra control registers 1418 | // 1419 | 1420 | CV_ARM_FPEXTRA0 = 90, 1421 | CV_ARM_FPEXTRA1 = 91, 1422 | CV_ARM_FPEXTRA2 = 92, 1423 | CV_ARM_FPEXTRA3 = 93, 1424 | CV_ARM_FPEXTRA4 = 94, 1425 | CV_ARM_FPEXTRA5 = 95, 1426 | CV_ARM_FPEXTRA6 = 96, 1427 | CV_ARM_FPEXTRA7 = 97, 1428 | 1429 | // XSCALE Concan co-processor registers 1430 | CV_ARM_WR0 = 128, 1431 | CV_ARM_WR1 = 129, 1432 | CV_ARM_WR2 = 130, 1433 | CV_ARM_WR3 = 131, 1434 | CV_ARM_WR4 = 132, 1435 | CV_ARM_WR5 = 133, 1436 | CV_ARM_WR6 = 134, 1437 | CV_ARM_WR7 = 135, 1438 | CV_ARM_WR8 = 136, 1439 | CV_ARM_WR9 = 137, 1440 | CV_ARM_WR10 = 138, 1441 | CV_ARM_WR11 = 139, 1442 | CV_ARM_WR12 = 140, 1443 | CV_ARM_WR13 = 141, 1444 | CV_ARM_WR14 = 142, 1445 | CV_ARM_WR15 = 143, 1446 | 1447 | // XSCALE Concan co-processor control registers 1448 | CV_ARM_WCID = 144, 1449 | CV_ARM_WCON = 145, 1450 | CV_ARM_WCSSF = 146, 1451 | CV_ARM_WCASF = 147, 1452 | CV_ARM_WC4 = 148, 1453 | CV_ARM_WC5 = 149, 1454 | CV_ARM_WC6 = 150, 1455 | CV_ARM_WC7 = 151, 1456 | CV_ARM_WCGR0 = 152, 1457 | CV_ARM_WCGR1 = 153, 1458 | CV_ARM_WCGR2 = 154, 1459 | CV_ARM_WCGR3 = 155, 1460 | CV_ARM_WC12 = 156, 1461 | CV_ARM_WC13 = 157, 1462 | CV_ARM_WC14 = 158, 1463 | CV_ARM_WC15 = 159, 1464 | 1465 | // 1466 | // ARM VFPv3/Neon extended floating Point 1467 | // 1468 | 1469 | CV_ARM_FS32 = 200, 1470 | CV_ARM_FS33 = 201, 1471 | CV_ARM_FS34 = 202, 1472 | CV_ARM_FS35 = 203, 1473 | CV_ARM_FS36 = 204, 1474 | CV_ARM_FS37 = 205, 1475 | CV_ARM_FS38 = 206, 1476 | CV_ARM_FS39 = 207, 1477 | CV_ARM_FS40 = 208, 1478 | CV_ARM_FS41 = 209, 1479 | CV_ARM_FS42 = 210, 1480 | CV_ARM_FS43 = 211, 1481 | CV_ARM_FS44 = 212, 1482 | CV_ARM_FS45 = 213, 1483 | CV_ARM_FS46 = 214, 1484 | CV_ARM_FS47 = 215, 1485 | CV_ARM_FS48 = 216, 1486 | CV_ARM_FS49 = 217, 1487 | CV_ARM_FS50 = 218, 1488 | CV_ARM_FS51 = 219, 1489 | CV_ARM_FS52 = 220, 1490 | CV_ARM_FS53 = 221, 1491 | CV_ARM_FS54 = 222, 1492 | CV_ARM_FS55 = 223, 1493 | CV_ARM_FS56 = 224, 1494 | CV_ARM_FS57 = 225, 1495 | CV_ARM_FS58 = 226, 1496 | CV_ARM_FS59 = 227, 1497 | CV_ARM_FS60 = 228, 1498 | CV_ARM_FS61 = 229, 1499 | CV_ARM_FS62 = 230, 1500 | CV_ARM_FS63 = 231, 1501 | 1502 | // ARM double-precision floating point 1503 | 1504 | CV_ARM_ND0 = 300, 1505 | CV_ARM_ND1 = 301, 1506 | CV_ARM_ND2 = 302, 1507 | CV_ARM_ND3 = 303, 1508 | CV_ARM_ND4 = 304, 1509 | CV_ARM_ND5 = 305, 1510 | CV_ARM_ND6 = 306, 1511 | CV_ARM_ND7 = 307, 1512 | CV_ARM_ND8 = 308, 1513 | CV_ARM_ND9 = 309, 1514 | CV_ARM_ND10 = 310, 1515 | CV_ARM_ND11 = 311, 1516 | CV_ARM_ND12 = 312, 1517 | CV_ARM_ND13 = 313, 1518 | CV_ARM_ND14 = 314, 1519 | CV_ARM_ND15 = 315, 1520 | CV_ARM_ND16 = 316, 1521 | CV_ARM_ND17 = 317, 1522 | CV_ARM_ND18 = 318, 1523 | CV_ARM_ND19 = 319, 1524 | CV_ARM_ND20 = 320, 1525 | CV_ARM_ND21 = 321, 1526 | CV_ARM_ND22 = 322, 1527 | CV_ARM_ND23 = 323, 1528 | CV_ARM_ND24 = 324, 1529 | CV_ARM_ND25 = 325, 1530 | CV_ARM_ND26 = 326, 1531 | CV_ARM_ND27 = 327, 1532 | CV_ARM_ND28 = 328, 1533 | CV_ARM_ND29 = 329, 1534 | CV_ARM_ND30 = 330, 1535 | CV_ARM_ND31 = 331, 1536 | 1537 | // ARM extended precision floating point 1538 | 1539 | CV_ARM_NQ0 = 400, 1540 | CV_ARM_NQ1 = 401, 1541 | CV_ARM_NQ2 = 402, 1542 | CV_ARM_NQ3 = 403, 1543 | CV_ARM_NQ4 = 404, 1544 | CV_ARM_NQ5 = 405, 1545 | CV_ARM_NQ6 = 406, 1546 | CV_ARM_NQ7 = 407, 1547 | CV_ARM_NQ8 = 408, 1548 | CV_ARM_NQ9 = 409, 1549 | CV_ARM_NQ10 = 410, 1550 | CV_ARM_NQ11 = 411, 1551 | CV_ARM_NQ12 = 412, 1552 | CV_ARM_NQ13 = 413, 1553 | CV_ARM_NQ14 = 414, 1554 | CV_ARM_NQ15 = 415, 1555 | 1556 | // 1557 | // Register set for ARM64 1558 | // 1559 | 1560 | CV_ARM64_NOREG = CV_REG_NONE, 1561 | 1562 | // General purpose 32-bit integer registers 1563 | 1564 | CV_ARM64_W0 = 10, 1565 | CV_ARM64_W1 = 11, 1566 | CV_ARM64_W2 = 12, 1567 | CV_ARM64_W3 = 13, 1568 | CV_ARM64_W4 = 14, 1569 | CV_ARM64_W5 = 15, 1570 | CV_ARM64_W6 = 16, 1571 | CV_ARM64_W7 = 17, 1572 | CV_ARM64_W8 = 18, 1573 | CV_ARM64_W9 = 19, 1574 | CV_ARM64_W10 = 20, 1575 | CV_ARM64_W11 = 21, 1576 | CV_ARM64_W12 = 22, 1577 | CV_ARM64_W13 = 23, 1578 | CV_ARM64_W14 = 24, 1579 | CV_ARM64_W15 = 25, 1580 | CV_ARM64_W16 = 26, 1581 | CV_ARM64_W17 = 27, 1582 | CV_ARM64_W18 = 28, 1583 | CV_ARM64_W19 = 29, 1584 | CV_ARM64_W20 = 30, 1585 | CV_ARM64_W21 = 31, 1586 | CV_ARM64_W22 = 32, 1587 | CV_ARM64_W23 = 33, 1588 | CV_ARM64_W24 = 34, 1589 | CV_ARM64_W25 = 35, 1590 | CV_ARM64_W26 = 36, 1591 | CV_ARM64_W27 = 37, 1592 | CV_ARM64_W28 = 38, 1593 | CV_ARM64_W29 = 39, 1594 | CV_ARM64_W30 = 40, 1595 | CV_ARM64_WZR = 41, 1596 | 1597 | // General purpose 64-bit integer registers 1598 | 1599 | CV_ARM64_X0 = 50, 1600 | CV_ARM64_X1 = 51, 1601 | CV_ARM64_X2 = 52, 1602 | CV_ARM64_X3 = 53, 1603 | CV_ARM64_X4 = 54, 1604 | CV_ARM64_X5 = 55, 1605 | CV_ARM64_X6 = 56, 1606 | CV_ARM64_X7 = 57, 1607 | CV_ARM64_X8 = 58, 1608 | CV_ARM64_X9 = 59, 1609 | CV_ARM64_X10 = 60, 1610 | CV_ARM64_X11 = 61, 1611 | CV_ARM64_X12 = 62, 1612 | CV_ARM64_X13 = 63, 1613 | CV_ARM64_X14 = 64, 1614 | CV_ARM64_X15 = 65, 1615 | CV_ARM64_IP0 = 66, 1616 | CV_ARM64_IP1 = 67, 1617 | CV_ARM64_X18 = 68, 1618 | CV_ARM64_X19 = 69, 1619 | CV_ARM64_X20 = 70, 1620 | CV_ARM64_X21 = 71, 1621 | CV_ARM64_X22 = 72, 1622 | CV_ARM64_X23 = 73, 1623 | CV_ARM64_X24 = 74, 1624 | CV_ARM64_X25 = 75, 1625 | CV_ARM64_X26 = 76, 1626 | CV_ARM64_X27 = 77, 1627 | CV_ARM64_X28 = 78, 1628 | CV_ARM64_FP = 79, 1629 | CV_ARM64_LR = 80, 1630 | CV_ARM64_SP = 81, 1631 | CV_ARM64_ZR = 82, 1632 | CV_ARM64_PC = 83, 1633 | 1634 | // status registers 1635 | 1636 | CV_ARM64_NZCV = 90, 1637 | CV_ARM64_CPSR = 91, 1638 | 1639 | // 32-bit floating point registers 1640 | 1641 | CV_ARM64_S0 = 100, 1642 | CV_ARM64_S1 = 101, 1643 | CV_ARM64_S2 = 102, 1644 | CV_ARM64_S3 = 103, 1645 | CV_ARM64_S4 = 104, 1646 | CV_ARM64_S5 = 105, 1647 | CV_ARM64_S6 = 106, 1648 | CV_ARM64_S7 = 107, 1649 | CV_ARM64_S8 = 108, 1650 | CV_ARM64_S9 = 109, 1651 | CV_ARM64_S10 = 110, 1652 | CV_ARM64_S11 = 111, 1653 | CV_ARM64_S12 = 112, 1654 | CV_ARM64_S13 = 113, 1655 | CV_ARM64_S14 = 114, 1656 | CV_ARM64_S15 = 115, 1657 | CV_ARM64_S16 = 116, 1658 | CV_ARM64_S17 = 117, 1659 | CV_ARM64_S18 = 118, 1660 | CV_ARM64_S19 = 119, 1661 | CV_ARM64_S20 = 120, 1662 | CV_ARM64_S21 = 121, 1663 | CV_ARM64_S22 = 122, 1664 | CV_ARM64_S23 = 123, 1665 | CV_ARM64_S24 = 124, 1666 | CV_ARM64_S25 = 125, 1667 | CV_ARM64_S26 = 126, 1668 | CV_ARM64_S27 = 127, 1669 | CV_ARM64_S28 = 128, 1670 | CV_ARM64_S29 = 129, 1671 | CV_ARM64_S30 = 130, 1672 | CV_ARM64_S31 = 131, 1673 | 1674 | // 64-bit floating point registers 1675 | 1676 | CV_ARM64_D0 = 140, 1677 | CV_ARM64_D1 = 141, 1678 | CV_ARM64_D2 = 142, 1679 | CV_ARM64_D3 = 143, 1680 | CV_ARM64_D4 = 144, 1681 | CV_ARM64_D5 = 145, 1682 | CV_ARM64_D6 = 146, 1683 | CV_ARM64_D7 = 147, 1684 | CV_ARM64_D8 = 148, 1685 | CV_ARM64_D9 = 149, 1686 | CV_ARM64_D10 = 150, 1687 | CV_ARM64_D11 = 151, 1688 | CV_ARM64_D12 = 152, 1689 | CV_ARM64_D13 = 153, 1690 | CV_ARM64_D14 = 154, 1691 | CV_ARM64_D15 = 155, 1692 | CV_ARM64_D16 = 156, 1693 | CV_ARM64_D17 = 157, 1694 | CV_ARM64_D18 = 158, 1695 | CV_ARM64_D19 = 159, 1696 | CV_ARM64_D20 = 160, 1697 | CV_ARM64_D21 = 161, 1698 | CV_ARM64_D22 = 162, 1699 | CV_ARM64_D23 = 163, 1700 | CV_ARM64_D24 = 164, 1701 | CV_ARM64_D25 = 165, 1702 | CV_ARM64_D26 = 166, 1703 | CV_ARM64_D27 = 167, 1704 | CV_ARM64_D28 = 168, 1705 | CV_ARM64_D29 = 169, 1706 | CV_ARM64_D30 = 170, 1707 | CV_ARM64_D31 = 171, 1708 | 1709 | // 128-bit SIMD registers 1710 | 1711 | CV_ARM64_Q0 = 180, 1712 | CV_ARM64_Q1 = 181, 1713 | CV_ARM64_Q2 = 182, 1714 | CV_ARM64_Q3 = 183, 1715 | CV_ARM64_Q4 = 184, 1716 | CV_ARM64_Q5 = 185, 1717 | CV_ARM64_Q6 = 186, 1718 | CV_ARM64_Q7 = 187, 1719 | CV_ARM64_Q8 = 188, 1720 | CV_ARM64_Q9 = 189, 1721 | CV_ARM64_Q10 = 190, 1722 | CV_ARM64_Q11 = 191, 1723 | CV_ARM64_Q12 = 192, 1724 | CV_ARM64_Q13 = 193, 1725 | CV_ARM64_Q14 = 194, 1726 | CV_ARM64_Q15 = 195, 1727 | CV_ARM64_Q16 = 196, 1728 | CV_ARM64_Q17 = 197, 1729 | CV_ARM64_Q18 = 198, 1730 | CV_ARM64_Q19 = 199, 1731 | CV_ARM64_Q20 = 200, 1732 | CV_ARM64_Q21 = 201, 1733 | CV_ARM64_Q22 = 202, 1734 | CV_ARM64_Q23 = 203, 1735 | CV_ARM64_Q24 = 204, 1736 | CV_ARM64_Q25 = 205, 1737 | CV_ARM64_Q26 = 206, 1738 | CV_ARM64_Q27 = 207, 1739 | CV_ARM64_Q28 = 208, 1740 | CV_ARM64_Q29 = 209, 1741 | CV_ARM64_Q30 = 210, 1742 | CV_ARM64_Q31 = 211, 1743 | 1744 | // Floating point status register 1745 | 1746 | CV_ARM64_FPSR = 220, 1747 | CV_ARM64_FPCR = 221, 1748 | 1749 | // 8-bit floating point registers 1750 | 1751 | CV_ARM64_B0 = 230, 1752 | CV_ARM64_B1 = 231, 1753 | CV_ARM64_B2 = 232, 1754 | CV_ARM64_B3 = 233, 1755 | CV_ARM64_B4 = 234, 1756 | CV_ARM64_B5 = 235, 1757 | CV_ARM64_B6 = 236, 1758 | CV_ARM64_B7 = 237, 1759 | CV_ARM64_B8 = 238, 1760 | CV_ARM64_B9 = 239, 1761 | CV_ARM64_B10 = 240, 1762 | CV_ARM64_B11 = 241, 1763 | CV_ARM64_B12 = 242, 1764 | CV_ARM64_B13 = 243, 1765 | CV_ARM64_B14 = 244, 1766 | CV_ARM64_B15 = 245, 1767 | CV_ARM64_B16 = 246, 1768 | CV_ARM64_B17 = 247, 1769 | CV_ARM64_B18 = 248, 1770 | CV_ARM64_B19 = 249, 1771 | CV_ARM64_B20 = 250, 1772 | CV_ARM64_B21 = 251, 1773 | CV_ARM64_B22 = 252, 1774 | CV_ARM64_B23 = 253, 1775 | CV_ARM64_B24 = 254, 1776 | CV_ARM64_B25 = 255, 1777 | CV_ARM64_B26 = 256, 1778 | CV_ARM64_B27 = 257, 1779 | CV_ARM64_B28 = 258, 1780 | CV_ARM64_B29 = 259, 1781 | CV_ARM64_B30 = 260, 1782 | CV_ARM64_B31 = 261, 1783 | 1784 | // 16-bit floating point registers 1785 | 1786 | CV_ARM64_H0 = 270, 1787 | CV_ARM64_H1 = 271, 1788 | CV_ARM64_H2 = 272, 1789 | CV_ARM64_H3 = 273, 1790 | CV_ARM64_H4 = 274, 1791 | CV_ARM64_H5 = 275, 1792 | CV_ARM64_H6 = 276, 1793 | CV_ARM64_H7 = 277, 1794 | CV_ARM64_H8 = 278, 1795 | CV_ARM64_H9 = 279, 1796 | CV_ARM64_H10 = 280, 1797 | CV_ARM64_H11 = 281, 1798 | CV_ARM64_H12 = 282, 1799 | CV_ARM64_H13 = 283, 1800 | CV_ARM64_H14 = 284, 1801 | CV_ARM64_H15 = 285, 1802 | CV_ARM64_H16 = 286, 1803 | CV_ARM64_H17 = 287, 1804 | CV_ARM64_H18 = 288, 1805 | CV_ARM64_H19 = 289, 1806 | CV_ARM64_H20 = 290, 1807 | CV_ARM64_H21 = 291, 1808 | CV_ARM64_H22 = 292, 1809 | CV_ARM64_H23 = 293, 1810 | CV_ARM64_H24 = 294, 1811 | CV_ARM64_H25 = 295, 1812 | CV_ARM64_H26 = 296, 1813 | CV_ARM64_H27 = 297, 1814 | CV_ARM64_H28 = 298, 1815 | CV_ARM64_H29 = 299, 1816 | CV_ARM64_H30 = 300, 1817 | CV_ARM64_H31 = 301, 1818 | 1819 | // 128-bit vector registers 1820 | 1821 | CV_ARM64_V0 = 310, 1822 | CV_ARM64_V1 = 311, 1823 | CV_ARM64_V2 = 312, 1824 | CV_ARM64_V3 = 313, 1825 | CV_ARM64_V4 = 314, 1826 | CV_ARM64_V5 = 315, 1827 | CV_ARM64_V6 = 316, 1828 | CV_ARM64_V7 = 317, 1829 | CV_ARM64_V8 = 318, 1830 | CV_ARM64_V9 = 319, 1831 | CV_ARM64_V10 = 320, 1832 | CV_ARM64_V11 = 321, 1833 | CV_ARM64_V12 = 322, 1834 | CV_ARM64_V13 = 323, 1835 | CV_ARM64_V14 = 324, 1836 | CV_ARM64_V15 = 325, 1837 | CV_ARM64_V16 = 326, 1838 | CV_ARM64_V17 = 327, 1839 | CV_ARM64_V18 = 328, 1840 | CV_ARM64_V19 = 329, 1841 | CV_ARM64_V20 = 330, 1842 | CV_ARM64_V21 = 331, 1843 | CV_ARM64_V22 = 332, 1844 | CV_ARM64_V23 = 333, 1845 | CV_ARM64_V24 = 334, 1846 | CV_ARM64_V25 = 335, 1847 | CV_ARM64_V26 = 336, 1848 | CV_ARM64_V27 = 337, 1849 | CV_ARM64_V28 = 338, 1850 | CV_ARM64_V29 = 339, 1851 | CV_ARM64_V30 = 340, 1852 | CV_ARM64_V31 = 341, 1853 | 1854 | // 128-bit SIMD registers upper 64 bits 1855 | 1856 | CV_ARM64_Q0H = 350, 1857 | CV_ARM64_Q1H = 351, 1858 | CV_ARM64_Q2H = 352, 1859 | CV_ARM64_Q3H = 353, 1860 | CV_ARM64_Q4H = 354, 1861 | CV_ARM64_Q5H = 355, 1862 | CV_ARM64_Q6H = 356, 1863 | CV_ARM64_Q7H = 357, 1864 | CV_ARM64_Q8H = 358, 1865 | CV_ARM64_Q9H = 359, 1866 | CV_ARM64_Q10H = 360, 1867 | CV_ARM64_Q11H = 361, 1868 | CV_ARM64_Q12H = 362, 1869 | CV_ARM64_Q13H = 363, 1870 | CV_ARM64_Q14H = 364, 1871 | CV_ARM64_Q15H = 365, 1872 | CV_ARM64_Q16H = 366, 1873 | CV_ARM64_Q17H = 367, 1874 | CV_ARM64_Q18H = 368, 1875 | CV_ARM64_Q19H = 369, 1876 | CV_ARM64_Q20H = 370, 1877 | CV_ARM64_Q21H = 371, 1878 | CV_ARM64_Q22H = 372, 1879 | CV_ARM64_Q23H = 373, 1880 | CV_ARM64_Q24H = 374, 1881 | CV_ARM64_Q25H = 375, 1882 | CV_ARM64_Q26H = 376, 1883 | CV_ARM64_Q27H = 377, 1884 | CV_ARM64_Q28H = 378, 1885 | CV_ARM64_Q29H = 379, 1886 | CV_ARM64_Q30H = 380, 1887 | CV_ARM64_Q31H = 381, 1888 | 1889 | // 1890 | // Register set for Intel IA64 1891 | // 1892 | 1893 | CV_IA64_NOREG = CV_REG_NONE, 1894 | 1895 | // Branch Registers 1896 | 1897 | CV_IA64_Br0 = 512, 1898 | CV_IA64_Br1 = 513, 1899 | CV_IA64_Br2 = 514, 1900 | CV_IA64_Br3 = 515, 1901 | CV_IA64_Br4 = 516, 1902 | CV_IA64_Br5 = 517, 1903 | CV_IA64_Br6 = 518, 1904 | CV_IA64_Br7 = 519, 1905 | 1906 | // Predicate Registers 1907 | 1908 | CV_IA64_P0 = 704, 1909 | CV_IA64_P1 = 705, 1910 | CV_IA64_P2 = 706, 1911 | CV_IA64_P3 = 707, 1912 | CV_IA64_P4 = 708, 1913 | CV_IA64_P5 = 709, 1914 | CV_IA64_P6 = 710, 1915 | CV_IA64_P7 = 711, 1916 | CV_IA64_P8 = 712, 1917 | CV_IA64_P9 = 713, 1918 | CV_IA64_P10 = 714, 1919 | CV_IA64_P11 = 715, 1920 | CV_IA64_P12 = 716, 1921 | CV_IA64_P13 = 717, 1922 | CV_IA64_P14 = 718, 1923 | CV_IA64_P15 = 719, 1924 | CV_IA64_P16 = 720, 1925 | CV_IA64_P17 = 721, 1926 | CV_IA64_P18 = 722, 1927 | CV_IA64_P19 = 723, 1928 | CV_IA64_P20 = 724, 1929 | CV_IA64_P21 = 725, 1930 | CV_IA64_P22 = 726, 1931 | CV_IA64_P23 = 727, 1932 | CV_IA64_P24 = 728, 1933 | CV_IA64_P25 = 729, 1934 | CV_IA64_P26 = 730, 1935 | CV_IA64_P27 = 731, 1936 | CV_IA64_P28 = 732, 1937 | CV_IA64_P29 = 733, 1938 | CV_IA64_P30 = 734, 1939 | CV_IA64_P31 = 735, 1940 | CV_IA64_P32 = 736, 1941 | CV_IA64_P33 = 737, 1942 | CV_IA64_P34 = 738, 1943 | CV_IA64_P35 = 739, 1944 | CV_IA64_P36 = 740, 1945 | CV_IA64_P37 = 741, 1946 | CV_IA64_P38 = 742, 1947 | CV_IA64_P39 = 743, 1948 | CV_IA64_P40 = 744, 1949 | CV_IA64_P41 = 745, 1950 | CV_IA64_P42 = 746, 1951 | CV_IA64_P43 = 747, 1952 | CV_IA64_P44 = 748, 1953 | CV_IA64_P45 = 749, 1954 | CV_IA64_P46 = 750, 1955 | CV_IA64_P47 = 751, 1956 | CV_IA64_P48 = 752, 1957 | CV_IA64_P49 = 753, 1958 | CV_IA64_P50 = 754, 1959 | CV_IA64_P51 = 755, 1960 | CV_IA64_P52 = 756, 1961 | CV_IA64_P53 = 757, 1962 | CV_IA64_P54 = 758, 1963 | CV_IA64_P55 = 759, 1964 | CV_IA64_P56 = 760, 1965 | CV_IA64_P57 = 761, 1966 | CV_IA64_P58 = 762, 1967 | CV_IA64_P59 = 763, 1968 | CV_IA64_P60 = 764, 1969 | CV_IA64_P61 = 765, 1970 | CV_IA64_P62 = 766, 1971 | CV_IA64_P63 = 767, 1972 | 1973 | CV_IA64_Preds = 768, 1974 | 1975 | // Banked General Registers 1976 | 1977 | CV_IA64_IntH0 = 832, 1978 | CV_IA64_IntH1 = 833, 1979 | CV_IA64_IntH2 = 834, 1980 | CV_IA64_IntH3 = 835, 1981 | CV_IA64_IntH4 = 836, 1982 | CV_IA64_IntH5 = 837, 1983 | CV_IA64_IntH6 = 838, 1984 | CV_IA64_IntH7 = 839, 1985 | CV_IA64_IntH8 = 840, 1986 | CV_IA64_IntH9 = 841, 1987 | CV_IA64_IntH10 = 842, 1988 | CV_IA64_IntH11 = 843, 1989 | CV_IA64_IntH12 = 844, 1990 | CV_IA64_IntH13 = 845, 1991 | CV_IA64_IntH14 = 846, 1992 | CV_IA64_IntH15 = 847, 1993 | 1994 | // Special Registers 1995 | 1996 | CV_IA64_Ip = 1016, 1997 | CV_IA64_Umask = 1017, 1998 | CV_IA64_Cfm = 1018, 1999 | CV_IA64_Psr = 1019, 2000 | 2001 | // Banked General Registers 2002 | 2003 | CV_IA64_Nats = 1020, 2004 | CV_IA64_Nats2 = 1021, 2005 | CV_IA64_Nats3 = 1022, 2006 | 2007 | // General-Purpose Registers 2008 | 2009 | // Integer registers 2010 | CV_IA64_IntR0 = 1024, 2011 | CV_IA64_IntR1 = 1025, 2012 | CV_IA64_IntR2 = 1026, 2013 | CV_IA64_IntR3 = 1027, 2014 | CV_IA64_IntR4 = 1028, 2015 | CV_IA64_IntR5 = 1029, 2016 | CV_IA64_IntR6 = 1030, 2017 | CV_IA64_IntR7 = 1031, 2018 | CV_IA64_IntR8 = 1032, 2019 | CV_IA64_IntR9 = 1033, 2020 | CV_IA64_IntR10 = 1034, 2021 | CV_IA64_IntR11 = 1035, 2022 | CV_IA64_IntR12 = 1036, 2023 | CV_IA64_IntR13 = 1037, 2024 | CV_IA64_IntR14 = 1038, 2025 | CV_IA64_IntR15 = 1039, 2026 | CV_IA64_IntR16 = 1040, 2027 | CV_IA64_IntR17 = 1041, 2028 | CV_IA64_IntR18 = 1042, 2029 | CV_IA64_IntR19 = 1043, 2030 | CV_IA64_IntR20 = 1044, 2031 | CV_IA64_IntR21 = 1045, 2032 | CV_IA64_IntR22 = 1046, 2033 | CV_IA64_IntR23 = 1047, 2034 | CV_IA64_IntR24 = 1048, 2035 | CV_IA64_IntR25 = 1049, 2036 | CV_IA64_IntR26 = 1050, 2037 | CV_IA64_IntR27 = 1051, 2038 | CV_IA64_IntR28 = 1052, 2039 | CV_IA64_IntR29 = 1053, 2040 | CV_IA64_IntR30 = 1054, 2041 | CV_IA64_IntR31 = 1055, 2042 | 2043 | // Register Stack 2044 | CV_IA64_IntR32 = 1056, 2045 | CV_IA64_IntR33 = 1057, 2046 | CV_IA64_IntR34 = 1058, 2047 | CV_IA64_IntR35 = 1059, 2048 | CV_IA64_IntR36 = 1060, 2049 | CV_IA64_IntR37 = 1061, 2050 | CV_IA64_IntR38 = 1062, 2051 | CV_IA64_IntR39 = 1063, 2052 | CV_IA64_IntR40 = 1064, 2053 | CV_IA64_IntR41 = 1065, 2054 | CV_IA64_IntR42 = 1066, 2055 | CV_IA64_IntR43 = 1067, 2056 | CV_IA64_IntR44 = 1068, 2057 | CV_IA64_IntR45 = 1069, 2058 | CV_IA64_IntR46 = 1070, 2059 | CV_IA64_IntR47 = 1071, 2060 | CV_IA64_IntR48 = 1072, 2061 | CV_IA64_IntR49 = 1073, 2062 | CV_IA64_IntR50 = 1074, 2063 | CV_IA64_IntR51 = 1075, 2064 | CV_IA64_IntR52 = 1076, 2065 | CV_IA64_IntR53 = 1077, 2066 | CV_IA64_IntR54 = 1078, 2067 | CV_IA64_IntR55 = 1079, 2068 | CV_IA64_IntR56 = 1080, 2069 | CV_IA64_IntR57 = 1081, 2070 | CV_IA64_IntR58 = 1082, 2071 | CV_IA64_IntR59 = 1083, 2072 | CV_IA64_IntR60 = 1084, 2073 | CV_IA64_IntR61 = 1085, 2074 | CV_IA64_IntR62 = 1086, 2075 | CV_IA64_IntR63 = 1087, 2076 | CV_IA64_IntR64 = 1088, 2077 | CV_IA64_IntR65 = 1089, 2078 | CV_IA64_IntR66 = 1090, 2079 | CV_IA64_IntR67 = 1091, 2080 | CV_IA64_IntR68 = 1092, 2081 | CV_IA64_IntR69 = 1093, 2082 | CV_IA64_IntR70 = 1094, 2083 | CV_IA64_IntR71 = 1095, 2084 | CV_IA64_IntR72 = 1096, 2085 | CV_IA64_IntR73 = 1097, 2086 | CV_IA64_IntR74 = 1098, 2087 | CV_IA64_IntR75 = 1099, 2088 | CV_IA64_IntR76 = 1100, 2089 | CV_IA64_IntR77 = 1101, 2090 | CV_IA64_IntR78 = 1102, 2091 | CV_IA64_IntR79 = 1103, 2092 | CV_IA64_IntR80 = 1104, 2093 | CV_IA64_IntR81 = 1105, 2094 | CV_IA64_IntR82 = 1106, 2095 | CV_IA64_IntR83 = 1107, 2096 | CV_IA64_IntR84 = 1108, 2097 | CV_IA64_IntR85 = 1109, 2098 | CV_IA64_IntR86 = 1110, 2099 | CV_IA64_IntR87 = 1111, 2100 | CV_IA64_IntR88 = 1112, 2101 | CV_IA64_IntR89 = 1113, 2102 | CV_IA64_IntR90 = 1114, 2103 | CV_IA64_IntR91 = 1115, 2104 | CV_IA64_IntR92 = 1116, 2105 | CV_IA64_IntR93 = 1117, 2106 | CV_IA64_IntR94 = 1118, 2107 | CV_IA64_IntR95 = 1119, 2108 | CV_IA64_IntR96 = 1120, 2109 | CV_IA64_IntR97 = 1121, 2110 | CV_IA64_IntR98 = 1122, 2111 | CV_IA64_IntR99 = 1123, 2112 | CV_IA64_IntR100 = 1124, 2113 | CV_IA64_IntR101 = 1125, 2114 | CV_IA64_IntR102 = 1126, 2115 | CV_IA64_IntR103 = 1127, 2116 | CV_IA64_IntR104 = 1128, 2117 | CV_IA64_IntR105 = 1129, 2118 | CV_IA64_IntR106 = 1130, 2119 | CV_IA64_IntR107 = 1131, 2120 | CV_IA64_IntR108 = 1132, 2121 | CV_IA64_IntR109 = 1133, 2122 | CV_IA64_IntR110 = 1134, 2123 | CV_IA64_IntR111 = 1135, 2124 | CV_IA64_IntR112 = 1136, 2125 | CV_IA64_IntR113 = 1137, 2126 | CV_IA64_IntR114 = 1138, 2127 | CV_IA64_IntR115 = 1139, 2128 | CV_IA64_IntR116 = 1140, 2129 | CV_IA64_IntR117 = 1141, 2130 | CV_IA64_IntR118 = 1142, 2131 | CV_IA64_IntR119 = 1143, 2132 | CV_IA64_IntR120 = 1144, 2133 | CV_IA64_IntR121 = 1145, 2134 | CV_IA64_IntR122 = 1146, 2135 | CV_IA64_IntR123 = 1147, 2136 | CV_IA64_IntR124 = 1148, 2137 | CV_IA64_IntR125 = 1149, 2138 | CV_IA64_IntR126 = 1150, 2139 | CV_IA64_IntR127 = 1151, 2140 | 2141 | // Floating-Point Registers 2142 | 2143 | // Low Floating Point Registers 2144 | CV_IA64_FltF0 = 2048, 2145 | CV_IA64_FltF1 = 2049, 2146 | CV_IA64_FltF2 = 2050, 2147 | CV_IA64_FltF3 = 2051, 2148 | CV_IA64_FltF4 = 2052, 2149 | CV_IA64_FltF5 = 2053, 2150 | CV_IA64_FltF6 = 2054, 2151 | CV_IA64_FltF7 = 2055, 2152 | CV_IA64_FltF8 = 2056, 2153 | CV_IA64_FltF9 = 2057, 2154 | CV_IA64_FltF10 = 2058, 2155 | CV_IA64_FltF11 = 2059, 2156 | CV_IA64_FltF12 = 2060, 2157 | CV_IA64_FltF13 = 2061, 2158 | CV_IA64_FltF14 = 2062, 2159 | CV_IA64_FltF15 = 2063, 2160 | CV_IA64_FltF16 = 2064, 2161 | CV_IA64_FltF17 = 2065, 2162 | CV_IA64_FltF18 = 2066, 2163 | CV_IA64_FltF19 = 2067, 2164 | CV_IA64_FltF20 = 2068, 2165 | CV_IA64_FltF21 = 2069, 2166 | CV_IA64_FltF22 = 2070, 2167 | CV_IA64_FltF23 = 2071, 2168 | CV_IA64_FltF24 = 2072, 2169 | CV_IA64_FltF25 = 2073, 2170 | CV_IA64_FltF26 = 2074, 2171 | CV_IA64_FltF27 = 2075, 2172 | CV_IA64_FltF28 = 2076, 2173 | CV_IA64_FltF29 = 2077, 2174 | CV_IA64_FltF30 = 2078, 2175 | CV_IA64_FltF31 = 2079, 2176 | 2177 | // High Floating Point Registers 2178 | CV_IA64_FltF32 = 2080, 2179 | CV_IA64_FltF33 = 2081, 2180 | CV_IA64_FltF34 = 2082, 2181 | CV_IA64_FltF35 = 2083, 2182 | CV_IA64_FltF36 = 2084, 2183 | CV_IA64_FltF37 = 2085, 2184 | CV_IA64_FltF38 = 2086, 2185 | CV_IA64_FltF39 = 2087, 2186 | CV_IA64_FltF40 = 2088, 2187 | CV_IA64_FltF41 = 2089, 2188 | CV_IA64_FltF42 = 2090, 2189 | CV_IA64_FltF43 = 2091, 2190 | CV_IA64_FltF44 = 2092, 2191 | CV_IA64_FltF45 = 2093, 2192 | CV_IA64_FltF46 = 2094, 2193 | CV_IA64_FltF47 = 2095, 2194 | CV_IA64_FltF48 = 2096, 2195 | CV_IA64_FltF49 = 2097, 2196 | CV_IA64_FltF50 = 2098, 2197 | CV_IA64_FltF51 = 2099, 2198 | CV_IA64_FltF52 = 2100, 2199 | CV_IA64_FltF53 = 2101, 2200 | CV_IA64_FltF54 = 2102, 2201 | CV_IA64_FltF55 = 2103, 2202 | CV_IA64_FltF56 = 2104, 2203 | CV_IA64_FltF57 = 2105, 2204 | CV_IA64_FltF58 = 2106, 2205 | CV_IA64_FltF59 = 2107, 2206 | CV_IA64_FltF60 = 2108, 2207 | CV_IA64_FltF61 = 2109, 2208 | CV_IA64_FltF62 = 2110, 2209 | CV_IA64_FltF63 = 2111, 2210 | CV_IA64_FltF64 = 2112, 2211 | CV_IA64_FltF65 = 2113, 2212 | CV_IA64_FltF66 = 2114, 2213 | CV_IA64_FltF67 = 2115, 2214 | CV_IA64_FltF68 = 2116, 2215 | CV_IA64_FltF69 = 2117, 2216 | CV_IA64_FltF70 = 2118, 2217 | CV_IA64_FltF71 = 2119, 2218 | CV_IA64_FltF72 = 2120, 2219 | CV_IA64_FltF73 = 2121, 2220 | CV_IA64_FltF74 = 2122, 2221 | CV_IA64_FltF75 = 2123, 2222 | CV_IA64_FltF76 = 2124, 2223 | CV_IA64_FltF77 = 2125, 2224 | CV_IA64_FltF78 = 2126, 2225 | CV_IA64_FltF79 = 2127, 2226 | CV_IA64_FltF80 = 2128, 2227 | CV_IA64_FltF81 = 2129, 2228 | CV_IA64_FltF82 = 2130, 2229 | CV_IA64_FltF83 = 2131, 2230 | CV_IA64_FltF84 = 2132, 2231 | CV_IA64_FltF85 = 2133, 2232 | CV_IA64_FltF86 = 2134, 2233 | CV_IA64_FltF87 = 2135, 2234 | CV_IA64_FltF88 = 2136, 2235 | CV_IA64_FltF89 = 2137, 2236 | CV_IA64_FltF90 = 2138, 2237 | CV_IA64_FltF91 = 2139, 2238 | CV_IA64_FltF92 = 2140, 2239 | CV_IA64_FltF93 = 2141, 2240 | CV_IA64_FltF94 = 2142, 2241 | CV_IA64_FltF95 = 2143, 2242 | CV_IA64_FltF96 = 2144, 2243 | CV_IA64_FltF97 = 2145, 2244 | CV_IA64_FltF98 = 2146, 2245 | CV_IA64_FltF99 = 2147, 2246 | CV_IA64_FltF100 = 2148, 2247 | CV_IA64_FltF101 = 2149, 2248 | CV_IA64_FltF102 = 2150, 2249 | CV_IA64_FltF103 = 2151, 2250 | CV_IA64_FltF104 = 2152, 2251 | CV_IA64_FltF105 = 2153, 2252 | CV_IA64_FltF106 = 2154, 2253 | CV_IA64_FltF107 = 2155, 2254 | CV_IA64_FltF108 = 2156, 2255 | CV_IA64_FltF109 = 2157, 2256 | CV_IA64_FltF110 = 2158, 2257 | CV_IA64_FltF111 = 2159, 2258 | CV_IA64_FltF112 = 2160, 2259 | CV_IA64_FltF113 = 2161, 2260 | CV_IA64_FltF114 = 2162, 2261 | CV_IA64_FltF115 = 2163, 2262 | CV_IA64_FltF116 = 2164, 2263 | CV_IA64_FltF117 = 2165, 2264 | CV_IA64_FltF118 = 2166, 2265 | CV_IA64_FltF119 = 2167, 2266 | CV_IA64_FltF120 = 2168, 2267 | CV_IA64_FltF121 = 2169, 2268 | CV_IA64_FltF122 = 2170, 2269 | CV_IA64_FltF123 = 2171, 2270 | CV_IA64_FltF124 = 2172, 2271 | CV_IA64_FltF125 = 2173, 2272 | CV_IA64_FltF126 = 2174, 2273 | CV_IA64_FltF127 = 2175, 2274 | 2275 | // Application Registers 2276 | 2277 | CV_IA64_ApKR0 = 3072, 2278 | CV_IA64_ApKR1 = 3073, 2279 | CV_IA64_ApKR2 = 3074, 2280 | CV_IA64_ApKR3 = 3075, 2281 | CV_IA64_ApKR4 = 3076, 2282 | CV_IA64_ApKR5 = 3077, 2283 | CV_IA64_ApKR6 = 3078, 2284 | CV_IA64_ApKR7 = 3079, 2285 | CV_IA64_AR8 = 3080, 2286 | CV_IA64_AR9 = 3081, 2287 | CV_IA64_AR10 = 3082, 2288 | CV_IA64_AR11 = 3083, 2289 | CV_IA64_AR12 = 3084, 2290 | CV_IA64_AR13 = 3085, 2291 | CV_IA64_AR14 = 3086, 2292 | CV_IA64_AR15 = 3087, 2293 | CV_IA64_RsRSC = 3088, 2294 | CV_IA64_RsBSP = 3089, 2295 | CV_IA64_RsBSPSTORE = 3090, 2296 | CV_IA64_RsRNAT = 3091, 2297 | CV_IA64_AR20 = 3092, 2298 | CV_IA64_StFCR = 3093, 2299 | CV_IA64_AR22 = 3094, 2300 | CV_IA64_AR23 = 3095, 2301 | CV_IA64_EFLAG = 3096, 2302 | CV_IA64_CSD = 3097, 2303 | CV_IA64_SSD = 3098, 2304 | CV_IA64_CFLG = 3099, 2305 | CV_IA64_StFSR = 3100, 2306 | CV_IA64_StFIR = 3101, 2307 | CV_IA64_StFDR = 3102, 2308 | CV_IA64_AR31 = 3103, 2309 | CV_IA64_ApCCV = 3104, 2310 | CV_IA64_AR33 = 3105, 2311 | CV_IA64_AR34 = 3106, 2312 | CV_IA64_AR35 = 3107, 2313 | CV_IA64_ApUNAT = 3108, 2314 | CV_IA64_AR37 = 3109, 2315 | CV_IA64_AR38 = 3110, 2316 | CV_IA64_AR39 = 3111, 2317 | CV_IA64_StFPSR = 3112, 2318 | CV_IA64_AR41 = 3113, 2319 | CV_IA64_AR42 = 3114, 2320 | CV_IA64_AR43 = 3115, 2321 | CV_IA64_ApITC = 3116, 2322 | CV_IA64_AR45 = 3117, 2323 | CV_IA64_AR46 = 3118, 2324 | CV_IA64_AR47 = 3119, 2325 | CV_IA64_AR48 = 3120, 2326 | CV_IA64_AR49 = 3121, 2327 | CV_IA64_AR50 = 3122, 2328 | CV_IA64_AR51 = 3123, 2329 | CV_IA64_AR52 = 3124, 2330 | CV_IA64_AR53 = 3125, 2331 | CV_IA64_AR54 = 3126, 2332 | CV_IA64_AR55 = 3127, 2333 | CV_IA64_AR56 = 3128, 2334 | CV_IA64_AR57 = 3129, 2335 | CV_IA64_AR58 = 3130, 2336 | CV_IA64_AR59 = 3131, 2337 | CV_IA64_AR60 = 3132, 2338 | CV_IA64_AR61 = 3133, 2339 | CV_IA64_AR62 = 3134, 2340 | CV_IA64_AR63 = 3135, 2341 | CV_IA64_RsPFS = 3136, 2342 | CV_IA64_ApLC = 3137, 2343 | CV_IA64_ApEC = 3138, 2344 | CV_IA64_AR67 = 3139, 2345 | CV_IA64_AR68 = 3140, 2346 | CV_IA64_AR69 = 3141, 2347 | CV_IA64_AR70 = 3142, 2348 | CV_IA64_AR71 = 3143, 2349 | CV_IA64_AR72 = 3144, 2350 | CV_IA64_AR73 = 3145, 2351 | CV_IA64_AR74 = 3146, 2352 | CV_IA64_AR75 = 3147, 2353 | CV_IA64_AR76 = 3148, 2354 | CV_IA64_AR77 = 3149, 2355 | CV_IA64_AR78 = 3150, 2356 | CV_IA64_AR79 = 3151, 2357 | CV_IA64_AR80 = 3152, 2358 | CV_IA64_AR81 = 3153, 2359 | CV_IA64_AR82 = 3154, 2360 | CV_IA64_AR83 = 3155, 2361 | CV_IA64_AR84 = 3156, 2362 | CV_IA64_AR85 = 3157, 2363 | CV_IA64_AR86 = 3158, 2364 | CV_IA64_AR87 = 3159, 2365 | CV_IA64_AR88 = 3160, 2366 | CV_IA64_AR89 = 3161, 2367 | CV_IA64_AR90 = 3162, 2368 | CV_IA64_AR91 = 3163, 2369 | CV_IA64_AR92 = 3164, 2370 | CV_IA64_AR93 = 3165, 2371 | CV_IA64_AR94 = 3166, 2372 | CV_IA64_AR95 = 3167, 2373 | CV_IA64_AR96 = 3168, 2374 | CV_IA64_AR97 = 3169, 2375 | CV_IA64_AR98 = 3170, 2376 | CV_IA64_AR99 = 3171, 2377 | CV_IA64_AR100 = 3172, 2378 | CV_IA64_AR101 = 3173, 2379 | CV_IA64_AR102 = 3174, 2380 | CV_IA64_AR103 = 3175, 2381 | CV_IA64_AR104 = 3176, 2382 | CV_IA64_AR105 = 3177, 2383 | CV_IA64_AR106 = 3178, 2384 | CV_IA64_AR107 = 3179, 2385 | CV_IA64_AR108 = 3180, 2386 | CV_IA64_AR109 = 3181, 2387 | CV_IA64_AR110 = 3182, 2388 | CV_IA64_AR111 = 3183, 2389 | CV_IA64_AR112 = 3184, 2390 | CV_IA64_AR113 = 3185, 2391 | CV_IA64_AR114 = 3186, 2392 | CV_IA64_AR115 = 3187, 2393 | CV_IA64_AR116 = 3188, 2394 | CV_IA64_AR117 = 3189, 2395 | CV_IA64_AR118 = 3190, 2396 | CV_IA64_AR119 = 3191, 2397 | CV_IA64_AR120 = 3192, 2398 | CV_IA64_AR121 = 3193, 2399 | CV_IA64_AR122 = 3194, 2400 | CV_IA64_AR123 = 3195, 2401 | CV_IA64_AR124 = 3196, 2402 | CV_IA64_AR125 = 3197, 2403 | CV_IA64_AR126 = 3198, 2404 | CV_IA64_AR127 = 3199, 2405 | 2406 | // CPUID Registers 2407 | 2408 | CV_IA64_CPUID0 = 3328, 2409 | CV_IA64_CPUID1 = 3329, 2410 | CV_IA64_CPUID2 = 3330, 2411 | CV_IA64_CPUID3 = 3331, 2412 | CV_IA64_CPUID4 = 3332, 2413 | 2414 | // Control Registers 2415 | 2416 | CV_IA64_ApDCR = 4096, 2417 | CV_IA64_ApITM = 4097, 2418 | CV_IA64_ApIVA = 4098, 2419 | CV_IA64_CR3 = 4099, 2420 | CV_IA64_CR4 = 4100, 2421 | CV_IA64_CR5 = 4101, 2422 | CV_IA64_CR6 = 4102, 2423 | CV_IA64_CR7 = 4103, 2424 | CV_IA64_ApPTA = 4104, 2425 | CV_IA64_ApGPTA = 4105, 2426 | CV_IA64_CR10 = 4106, 2427 | CV_IA64_CR11 = 4107, 2428 | CV_IA64_CR12 = 4108, 2429 | CV_IA64_CR13 = 4109, 2430 | CV_IA64_CR14 = 4110, 2431 | CV_IA64_CR15 = 4111, 2432 | CV_IA64_StIPSR = 4112, 2433 | CV_IA64_StISR = 4113, 2434 | CV_IA64_CR18 = 4114, 2435 | CV_IA64_StIIP = 4115, 2436 | CV_IA64_StIFA = 4116, 2437 | CV_IA64_StITIR = 4117, 2438 | CV_IA64_StIIPA = 4118, 2439 | CV_IA64_StIFS = 4119, 2440 | CV_IA64_StIIM = 4120, 2441 | CV_IA64_StIHA = 4121, 2442 | CV_IA64_CR26 = 4122, 2443 | CV_IA64_CR27 = 4123, 2444 | CV_IA64_CR28 = 4124, 2445 | CV_IA64_CR29 = 4125, 2446 | CV_IA64_CR30 = 4126, 2447 | CV_IA64_CR31 = 4127, 2448 | CV_IA64_CR32 = 4128, 2449 | CV_IA64_CR33 = 4129, 2450 | CV_IA64_CR34 = 4130, 2451 | CV_IA64_CR35 = 4131, 2452 | CV_IA64_CR36 = 4132, 2453 | CV_IA64_CR37 = 4133, 2454 | CV_IA64_CR38 = 4134, 2455 | CV_IA64_CR39 = 4135, 2456 | CV_IA64_CR40 = 4136, 2457 | CV_IA64_CR41 = 4137, 2458 | CV_IA64_CR42 = 4138, 2459 | CV_IA64_CR43 = 4139, 2460 | CV_IA64_CR44 = 4140, 2461 | CV_IA64_CR45 = 4141, 2462 | CV_IA64_CR46 = 4142, 2463 | CV_IA64_CR47 = 4143, 2464 | CV_IA64_CR48 = 4144, 2465 | CV_IA64_CR49 = 4145, 2466 | CV_IA64_CR50 = 4146, 2467 | CV_IA64_CR51 = 4147, 2468 | CV_IA64_CR52 = 4148, 2469 | CV_IA64_CR53 = 4149, 2470 | CV_IA64_CR54 = 4150, 2471 | CV_IA64_CR55 = 4151, 2472 | CV_IA64_CR56 = 4152, 2473 | CV_IA64_CR57 = 4153, 2474 | CV_IA64_CR58 = 4154, 2475 | CV_IA64_CR59 = 4155, 2476 | CV_IA64_CR60 = 4156, 2477 | CV_IA64_CR61 = 4157, 2478 | CV_IA64_CR62 = 4158, 2479 | CV_IA64_CR63 = 4159, 2480 | CV_IA64_SaLID = 4160, 2481 | CV_IA64_SaIVR = 4161, 2482 | CV_IA64_SaTPR = 4162, 2483 | CV_IA64_SaEOI = 4163, 2484 | CV_IA64_SaIRR0 = 4164, 2485 | CV_IA64_SaIRR1 = 4165, 2486 | CV_IA64_SaIRR2 = 4166, 2487 | CV_IA64_SaIRR3 = 4167, 2488 | CV_IA64_SaITV = 4168, 2489 | CV_IA64_SaPMV = 4169, 2490 | CV_IA64_SaCMCV = 4170, 2491 | CV_IA64_CR75 = 4171, 2492 | CV_IA64_CR76 = 4172, 2493 | CV_IA64_CR77 = 4173, 2494 | CV_IA64_CR78 = 4174, 2495 | CV_IA64_CR79 = 4175, 2496 | CV_IA64_SaLRR0 = 4176, 2497 | CV_IA64_SaLRR1 = 4177, 2498 | CV_IA64_CR82 = 4178, 2499 | CV_IA64_CR83 = 4179, 2500 | CV_IA64_CR84 = 4180, 2501 | CV_IA64_CR85 = 4181, 2502 | CV_IA64_CR86 = 4182, 2503 | CV_IA64_CR87 = 4183, 2504 | CV_IA64_CR88 = 4184, 2505 | CV_IA64_CR89 = 4185, 2506 | CV_IA64_CR90 = 4186, 2507 | CV_IA64_CR91 = 4187, 2508 | CV_IA64_CR92 = 4188, 2509 | CV_IA64_CR93 = 4189, 2510 | CV_IA64_CR94 = 4190, 2511 | CV_IA64_CR95 = 4191, 2512 | CV_IA64_CR96 = 4192, 2513 | CV_IA64_CR97 = 4193, 2514 | CV_IA64_CR98 = 4194, 2515 | CV_IA64_CR99 = 4195, 2516 | CV_IA64_CR100 = 4196, 2517 | CV_IA64_CR101 = 4197, 2518 | CV_IA64_CR102 = 4198, 2519 | CV_IA64_CR103 = 4199, 2520 | CV_IA64_CR104 = 4200, 2521 | CV_IA64_CR105 = 4201, 2522 | CV_IA64_CR106 = 4202, 2523 | CV_IA64_CR107 = 4203, 2524 | CV_IA64_CR108 = 4204, 2525 | CV_IA64_CR109 = 4205, 2526 | CV_IA64_CR110 = 4206, 2527 | CV_IA64_CR111 = 4207, 2528 | CV_IA64_CR112 = 4208, 2529 | CV_IA64_CR113 = 4209, 2530 | CV_IA64_CR114 = 4210, 2531 | CV_IA64_CR115 = 4211, 2532 | CV_IA64_CR116 = 4212, 2533 | CV_IA64_CR117 = 4213, 2534 | CV_IA64_CR118 = 4214, 2535 | CV_IA64_CR119 = 4215, 2536 | CV_IA64_CR120 = 4216, 2537 | CV_IA64_CR121 = 4217, 2538 | CV_IA64_CR122 = 4218, 2539 | CV_IA64_CR123 = 4219, 2540 | CV_IA64_CR124 = 4220, 2541 | CV_IA64_CR125 = 4221, 2542 | CV_IA64_CR126 = 4222, 2543 | CV_IA64_CR127 = 4223, 2544 | 2545 | // Protection Key Registers 2546 | 2547 | CV_IA64_Pkr0 = 5120, 2548 | CV_IA64_Pkr1 = 5121, 2549 | CV_IA64_Pkr2 = 5122, 2550 | CV_IA64_Pkr3 = 5123, 2551 | CV_IA64_Pkr4 = 5124, 2552 | CV_IA64_Pkr5 = 5125, 2553 | CV_IA64_Pkr6 = 5126, 2554 | CV_IA64_Pkr7 = 5127, 2555 | CV_IA64_Pkr8 = 5128, 2556 | CV_IA64_Pkr9 = 5129, 2557 | CV_IA64_Pkr10 = 5130, 2558 | CV_IA64_Pkr11 = 5131, 2559 | CV_IA64_Pkr12 = 5132, 2560 | CV_IA64_Pkr13 = 5133, 2561 | CV_IA64_Pkr14 = 5134, 2562 | CV_IA64_Pkr15 = 5135, 2563 | 2564 | // Region Registers 2565 | 2566 | CV_IA64_Rr0 = 6144, 2567 | CV_IA64_Rr1 = 6145, 2568 | CV_IA64_Rr2 = 6146, 2569 | CV_IA64_Rr3 = 6147, 2570 | CV_IA64_Rr4 = 6148, 2571 | CV_IA64_Rr5 = 6149, 2572 | CV_IA64_Rr6 = 6150, 2573 | CV_IA64_Rr7 = 6151, 2574 | 2575 | // Performance Monitor Data Registers 2576 | 2577 | CV_IA64_PFD0 = 7168, 2578 | CV_IA64_PFD1 = 7169, 2579 | CV_IA64_PFD2 = 7170, 2580 | CV_IA64_PFD3 = 7171, 2581 | CV_IA64_PFD4 = 7172, 2582 | CV_IA64_PFD5 = 7173, 2583 | CV_IA64_PFD6 = 7174, 2584 | CV_IA64_PFD7 = 7175, 2585 | CV_IA64_PFD8 = 7176, 2586 | CV_IA64_PFD9 = 7177, 2587 | CV_IA64_PFD10 = 7178, 2588 | CV_IA64_PFD11 = 7179, 2589 | CV_IA64_PFD12 = 7180, 2590 | CV_IA64_PFD13 = 7181, 2591 | CV_IA64_PFD14 = 7182, 2592 | CV_IA64_PFD15 = 7183, 2593 | CV_IA64_PFD16 = 7184, 2594 | CV_IA64_PFD17 = 7185, 2595 | 2596 | // Performance Monitor Config Registers 2597 | 2598 | CV_IA64_PFC0 = 7424, 2599 | CV_IA64_PFC1 = 7425, 2600 | CV_IA64_PFC2 = 7426, 2601 | CV_IA64_PFC3 = 7427, 2602 | CV_IA64_PFC4 = 7428, 2603 | CV_IA64_PFC5 = 7429, 2604 | CV_IA64_PFC6 = 7430, 2605 | CV_IA64_PFC7 = 7431, 2606 | CV_IA64_PFC8 = 7432, 2607 | CV_IA64_PFC9 = 7433, 2608 | CV_IA64_PFC10 = 7434, 2609 | CV_IA64_PFC11 = 7435, 2610 | CV_IA64_PFC12 = 7436, 2611 | CV_IA64_PFC13 = 7437, 2612 | CV_IA64_PFC14 = 7438, 2613 | CV_IA64_PFC15 = 7439, 2614 | 2615 | // Instruction Translation Registers 2616 | 2617 | CV_IA64_TrI0 = 8192, 2618 | CV_IA64_TrI1 = 8193, 2619 | CV_IA64_TrI2 = 8194, 2620 | CV_IA64_TrI3 = 8195, 2621 | CV_IA64_TrI4 = 8196, 2622 | CV_IA64_TrI5 = 8197, 2623 | CV_IA64_TrI6 = 8198, 2624 | CV_IA64_TrI7 = 8199, 2625 | 2626 | // Data Translation Registers 2627 | 2628 | CV_IA64_TrD0 = 8320, 2629 | CV_IA64_TrD1 = 8321, 2630 | CV_IA64_TrD2 = 8322, 2631 | CV_IA64_TrD3 = 8323, 2632 | CV_IA64_TrD4 = 8324, 2633 | CV_IA64_TrD5 = 8325, 2634 | CV_IA64_TrD6 = 8326, 2635 | CV_IA64_TrD7 = 8327, 2636 | 2637 | // Instruction Breakpoint Registers 2638 | 2639 | CV_IA64_DbI0 = 8448, 2640 | CV_IA64_DbI1 = 8449, 2641 | CV_IA64_DbI2 = 8450, 2642 | CV_IA64_DbI3 = 8451, 2643 | CV_IA64_DbI4 = 8452, 2644 | CV_IA64_DbI5 = 8453, 2645 | CV_IA64_DbI6 = 8454, 2646 | CV_IA64_DbI7 = 8455, 2647 | 2648 | // Data Breakpoint Registers 2649 | 2650 | CV_IA64_DbD0 = 8576, 2651 | CV_IA64_DbD1 = 8577, 2652 | CV_IA64_DbD2 = 8578, 2653 | CV_IA64_DbD3 = 8579, 2654 | CV_IA64_DbD4 = 8580, 2655 | CV_IA64_DbD5 = 8581, 2656 | CV_IA64_DbD6 = 8582, 2657 | CV_IA64_DbD7 = 8583, 2658 | 2659 | // 2660 | // Register set for the TriCore processor. 2661 | // 2662 | 2663 | CV_TRI_NOREG = CV_REG_NONE, 2664 | 2665 | // General Purpose Data Registers 2666 | 2667 | CV_TRI_D0 = 10, 2668 | CV_TRI_D1 = 11, 2669 | CV_TRI_D2 = 12, 2670 | CV_TRI_D3 = 13, 2671 | CV_TRI_D4 = 14, 2672 | CV_TRI_D5 = 15, 2673 | CV_TRI_D6 = 16, 2674 | CV_TRI_D7 = 17, 2675 | CV_TRI_D8 = 18, 2676 | CV_TRI_D9 = 19, 2677 | CV_TRI_D10 = 20, 2678 | CV_TRI_D11 = 21, 2679 | CV_TRI_D12 = 22, 2680 | CV_TRI_D13 = 23, 2681 | CV_TRI_D14 = 24, 2682 | CV_TRI_D15 = 25, 2683 | 2684 | // General Purpose Address Registers 2685 | 2686 | CV_TRI_A0 = 26, 2687 | CV_TRI_A1 = 27, 2688 | CV_TRI_A2 = 28, 2689 | CV_TRI_A3 = 29, 2690 | CV_TRI_A4 = 30, 2691 | CV_TRI_A5 = 31, 2692 | CV_TRI_A6 = 32, 2693 | CV_TRI_A7 = 33, 2694 | CV_TRI_A8 = 34, 2695 | CV_TRI_A9 = 35, 2696 | CV_TRI_A10 = 36, 2697 | CV_TRI_A11 = 37, 2698 | CV_TRI_A12 = 38, 2699 | CV_TRI_A13 = 39, 2700 | CV_TRI_A14 = 40, 2701 | CV_TRI_A15 = 41, 2702 | 2703 | // Extended (64-bit) data registers 2704 | 2705 | CV_TRI_E0 = 42, 2706 | CV_TRI_E2 = 43, 2707 | CV_TRI_E4 = 44, 2708 | CV_TRI_E6 = 45, 2709 | CV_TRI_E8 = 46, 2710 | CV_TRI_E10 = 47, 2711 | CV_TRI_E12 = 48, 2712 | CV_TRI_E14 = 49, 2713 | 2714 | // Extended (64-bit) address registers 2715 | 2716 | CV_TRI_EA0 = 50, 2717 | CV_TRI_EA2 = 51, 2718 | CV_TRI_EA4 = 52, 2719 | CV_TRI_EA6 = 53, 2720 | CV_TRI_EA8 = 54, 2721 | CV_TRI_EA10 = 55, 2722 | CV_TRI_EA12 = 56, 2723 | CV_TRI_EA14 = 57, 2724 | 2725 | CV_TRI_PSW = 58, 2726 | CV_TRI_PCXI = 59, 2727 | CV_TRI_PC = 60, 2728 | CV_TRI_FCX = 61, 2729 | CV_TRI_LCX = 62, 2730 | CV_TRI_ISP = 63, 2731 | CV_TRI_ICR = 64, 2732 | CV_TRI_BIV = 65, 2733 | CV_TRI_BTV = 66, 2734 | CV_TRI_SYSCON = 67, 2735 | CV_TRI_DPRx_0 = 68, 2736 | CV_TRI_DPRx_1 = 69, 2737 | CV_TRI_DPRx_2 = 70, 2738 | CV_TRI_DPRx_3 = 71, 2739 | CV_TRI_CPRx_0 = 68, 2740 | CV_TRI_CPRx_1 = 69, 2741 | CV_TRI_CPRx_2 = 70, 2742 | CV_TRI_CPRx_3 = 71, 2743 | CV_TRI_DPMx_0 = 68, 2744 | CV_TRI_DPMx_1 = 69, 2745 | CV_TRI_DPMx_2 = 70, 2746 | CV_TRI_DPMx_3 = 71, 2747 | CV_TRI_CPMx_0 = 68, 2748 | CV_TRI_CPMx_1 = 69, 2749 | CV_TRI_CPMx_2 = 70, 2750 | CV_TRI_CPMx_3 = 71, 2751 | CV_TRI_DBGSSR = 72, 2752 | CV_TRI_EXEVT = 73, 2753 | CV_TRI_SWEVT = 74, 2754 | CV_TRI_CREVT = 75, 2755 | CV_TRI_TRnEVT = 76, 2756 | CV_TRI_MMUCON = 77, 2757 | CV_TRI_ASI = 78, 2758 | CV_TRI_TVA = 79, 2759 | CV_TRI_TPA = 80, 2760 | CV_TRI_TPX = 81, 2761 | CV_TRI_TFA = 82, 2762 | 2763 | // 2764 | // Register set for the AM33 and related processors. 2765 | // 2766 | 2767 | CV_AM33_NOREG = CV_REG_NONE, 2768 | 2769 | // "Extended" (general purpose integer) registers 2770 | CV_AM33_E0 = 10, 2771 | CV_AM33_E1 = 11, 2772 | CV_AM33_E2 = 12, 2773 | CV_AM33_E3 = 13, 2774 | CV_AM33_E4 = 14, 2775 | CV_AM33_E5 = 15, 2776 | CV_AM33_E6 = 16, 2777 | CV_AM33_E7 = 17, 2778 | 2779 | // Address registers 2780 | CV_AM33_A0 = 20, 2781 | CV_AM33_A1 = 21, 2782 | CV_AM33_A2 = 22, 2783 | CV_AM33_A3 = 23, 2784 | 2785 | // Integer data registers 2786 | CV_AM33_D0 = 30, 2787 | CV_AM33_D1 = 31, 2788 | CV_AM33_D2 = 32, 2789 | CV_AM33_D3 = 33, 2790 | 2791 | // (Single-precision) floating-point registers 2792 | CV_AM33_FS0 = 40, 2793 | CV_AM33_FS1 = 41, 2794 | CV_AM33_FS2 = 42, 2795 | CV_AM33_FS3 = 43, 2796 | CV_AM33_FS4 = 44, 2797 | CV_AM33_FS5 = 45, 2798 | CV_AM33_FS6 = 46, 2799 | CV_AM33_FS7 = 47, 2800 | CV_AM33_FS8 = 48, 2801 | CV_AM33_FS9 = 49, 2802 | CV_AM33_FS10 = 50, 2803 | CV_AM33_FS11 = 51, 2804 | CV_AM33_FS12 = 52, 2805 | CV_AM33_FS13 = 53, 2806 | CV_AM33_FS14 = 54, 2807 | CV_AM33_FS15 = 55, 2808 | CV_AM33_FS16 = 56, 2809 | CV_AM33_FS17 = 57, 2810 | CV_AM33_FS18 = 58, 2811 | CV_AM33_FS19 = 59, 2812 | CV_AM33_FS20 = 60, 2813 | CV_AM33_FS21 = 61, 2814 | CV_AM33_FS22 = 62, 2815 | CV_AM33_FS23 = 63, 2816 | CV_AM33_FS24 = 64, 2817 | CV_AM33_FS25 = 65, 2818 | CV_AM33_FS26 = 66, 2819 | CV_AM33_FS27 = 67, 2820 | CV_AM33_FS28 = 68, 2821 | CV_AM33_FS29 = 69, 2822 | CV_AM33_FS30 = 70, 2823 | CV_AM33_FS31 = 71, 2824 | 2825 | // Special purpose registers 2826 | 2827 | // Stack pointer 2828 | CV_AM33_SP = 80, 2829 | 2830 | // Program counter 2831 | CV_AM33_PC = 81, 2832 | 2833 | // Multiply-divide/accumulate registers 2834 | CV_AM33_MDR = 82, 2835 | CV_AM33_MDRQ = 83, 2836 | CV_AM33_MCRH = 84, 2837 | CV_AM33_MCRL = 85, 2838 | CV_AM33_MCVF = 86, 2839 | 2840 | // CPU status words 2841 | CV_AM33_EPSW = 87, 2842 | CV_AM33_FPCR = 88, 2843 | 2844 | // Loop buffer registers 2845 | CV_AM33_LIR = 89, 2846 | CV_AM33_LAR = 90, 2847 | 2848 | // 2849 | // Register set for the Mitsubishi M32R 2850 | // 2851 | 2852 | CV_M32R_NOREG = CV_REG_NONE, 2853 | 2854 | CV_M32R_R0 = 10, 2855 | CV_M32R_R1 = 11, 2856 | CV_M32R_R2 = 12, 2857 | CV_M32R_R3 = 13, 2858 | CV_M32R_R4 = 14, 2859 | CV_M32R_R5 = 15, 2860 | CV_M32R_R6 = 16, 2861 | CV_M32R_R7 = 17, 2862 | CV_M32R_R8 = 18, 2863 | CV_M32R_R9 = 19, 2864 | CV_M32R_R10 = 20, 2865 | CV_M32R_R11 = 21, 2866 | CV_M32R_R12 = 22, // Gloabal Pointer, if used 2867 | CV_M32R_R13 = 23, // Frame Pointer, if allocated 2868 | CV_M32R_R14 = 24, // Link Register 2869 | CV_M32R_R15 = 25, // Stack Pointer 2870 | CV_M32R_PSW = 26, // Preocessor Status Register 2871 | CV_M32R_CBR = 27, // Condition Bit Register 2872 | CV_M32R_SPI = 28, // Interrupt Stack Pointer 2873 | CV_M32R_SPU = 29, // User Stack Pointer 2874 | CV_M32R_SPO = 30, // OS Stack Pointer 2875 | CV_M32R_BPC = 31, // Backup Program Counter 2876 | CV_M32R_ACHI = 32, // Accumulator High 2877 | CV_M32R_ACLO = 33, // Accumulator Low 2878 | CV_M32R_PC = 34, // Program Counter 2879 | 2880 | // 2881 | // Register set for the SuperH SHMedia processor including compact 2882 | // mode 2883 | // 2884 | 2885 | // Integer - 64 bit general registers 2886 | CV_SHMEDIA_NOREG = CV_REG_NONE, 2887 | CV_SHMEDIA_R0 = 10, 2888 | CV_SHMEDIA_R1 = 11, 2889 | CV_SHMEDIA_R2 = 12, 2890 | CV_SHMEDIA_R3 = 13, 2891 | CV_SHMEDIA_R4 = 14, 2892 | CV_SHMEDIA_R5 = 15, 2893 | CV_SHMEDIA_R6 = 16, 2894 | CV_SHMEDIA_R7 = 17, 2895 | CV_SHMEDIA_R8 = 18, 2896 | CV_SHMEDIA_R9 = 19, 2897 | CV_SHMEDIA_R10 = 20, 2898 | CV_SHMEDIA_R11 = 21, 2899 | CV_SHMEDIA_R12 = 22, 2900 | CV_SHMEDIA_R13 = 23, 2901 | CV_SHMEDIA_R14 = 24, 2902 | CV_SHMEDIA_R15 = 25, 2903 | CV_SHMEDIA_R16 = 26, 2904 | CV_SHMEDIA_R17 = 27, 2905 | CV_SHMEDIA_R18 = 28, 2906 | CV_SHMEDIA_R19 = 29, 2907 | CV_SHMEDIA_R20 = 30, 2908 | CV_SHMEDIA_R21 = 31, 2909 | CV_SHMEDIA_R22 = 32, 2910 | CV_SHMEDIA_R23 = 33, 2911 | CV_SHMEDIA_R24 = 34, 2912 | CV_SHMEDIA_R25 = 35, 2913 | CV_SHMEDIA_R26 = 36, 2914 | CV_SHMEDIA_R27 = 37, 2915 | CV_SHMEDIA_R28 = 38, 2916 | CV_SHMEDIA_R29 = 39, 2917 | CV_SHMEDIA_R30 = 40, 2918 | CV_SHMEDIA_R31 = 41, 2919 | CV_SHMEDIA_R32 = 42, 2920 | CV_SHMEDIA_R33 = 43, 2921 | CV_SHMEDIA_R34 = 44, 2922 | CV_SHMEDIA_R35 = 45, 2923 | CV_SHMEDIA_R36 = 46, 2924 | CV_SHMEDIA_R37 = 47, 2925 | CV_SHMEDIA_R38 = 48, 2926 | CV_SHMEDIA_R39 = 49, 2927 | CV_SHMEDIA_R40 = 50, 2928 | CV_SHMEDIA_R41 = 51, 2929 | CV_SHMEDIA_R42 = 52, 2930 | CV_SHMEDIA_R43 = 53, 2931 | CV_SHMEDIA_R44 = 54, 2932 | CV_SHMEDIA_R45 = 55, 2933 | CV_SHMEDIA_R46 = 56, 2934 | CV_SHMEDIA_R47 = 57, 2935 | CV_SHMEDIA_R48 = 58, 2936 | CV_SHMEDIA_R49 = 59, 2937 | CV_SHMEDIA_R50 = 60, 2938 | CV_SHMEDIA_R51 = 61, 2939 | CV_SHMEDIA_R52 = 62, 2940 | CV_SHMEDIA_R53 = 63, 2941 | CV_SHMEDIA_R54 = 64, 2942 | CV_SHMEDIA_R55 = 65, 2943 | CV_SHMEDIA_R56 = 66, 2944 | CV_SHMEDIA_R57 = 67, 2945 | CV_SHMEDIA_R58 = 68, 2946 | CV_SHMEDIA_R59 = 69, 2947 | CV_SHMEDIA_R60 = 70, 2948 | CV_SHMEDIA_R61 = 71, 2949 | CV_SHMEDIA_R62 = 72, 2950 | CV_SHMEDIA_R63 = 73, 2951 | 2952 | // Target Registers - 32 bit 2953 | CV_SHMEDIA_TR0 = 74, 2954 | CV_SHMEDIA_TR1 = 75, 2955 | CV_SHMEDIA_TR2 = 76, 2956 | CV_SHMEDIA_TR3 = 77, 2957 | CV_SHMEDIA_TR4 = 78, 2958 | CV_SHMEDIA_TR5 = 79, 2959 | CV_SHMEDIA_TR6 = 80, 2960 | CV_SHMEDIA_TR7 = 81, 2961 | CV_SHMEDIA_TR8 = 82, // future-proof 2962 | CV_SHMEDIA_TR9 = 83, // future-proof 2963 | CV_SHMEDIA_TR10 = 84, // future-proof 2964 | CV_SHMEDIA_TR11 = 85, // future-proof 2965 | CV_SHMEDIA_TR12 = 86, // future-proof 2966 | CV_SHMEDIA_TR13 = 87, // future-proof 2967 | CV_SHMEDIA_TR14 = 88, // future-proof 2968 | CV_SHMEDIA_TR15 = 89, // future-proof 2969 | 2970 | // Single - 32 bit fp registers 2971 | CV_SHMEDIA_FR0 = 128, 2972 | CV_SHMEDIA_FR1 = 129, 2973 | CV_SHMEDIA_FR2 = 130, 2974 | CV_SHMEDIA_FR3 = 131, 2975 | CV_SHMEDIA_FR4 = 132, 2976 | CV_SHMEDIA_FR5 = 133, 2977 | CV_SHMEDIA_FR6 = 134, 2978 | CV_SHMEDIA_FR7 = 135, 2979 | CV_SHMEDIA_FR8 = 136, 2980 | CV_SHMEDIA_FR9 = 137, 2981 | CV_SHMEDIA_FR10 = 138, 2982 | CV_SHMEDIA_FR11 = 139, 2983 | CV_SHMEDIA_FR12 = 140, 2984 | CV_SHMEDIA_FR13 = 141, 2985 | CV_SHMEDIA_FR14 = 142, 2986 | CV_SHMEDIA_FR15 = 143, 2987 | CV_SHMEDIA_FR16 = 144, 2988 | CV_SHMEDIA_FR17 = 145, 2989 | CV_SHMEDIA_FR18 = 146, 2990 | CV_SHMEDIA_FR19 = 147, 2991 | CV_SHMEDIA_FR20 = 148, 2992 | CV_SHMEDIA_FR21 = 149, 2993 | CV_SHMEDIA_FR22 = 150, 2994 | CV_SHMEDIA_FR23 = 151, 2995 | CV_SHMEDIA_FR24 = 152, 2996 | CV_SHMEDIA_FR25 = 153, 2997 | CV_SHMEDIA_FR26 = 154, 2998 | CV_SHMEDIA_FR27 = 155, 2999 | CV_SHMEDIA_FR28 = 156, 3000 | CV_SHMEDIA_FR29 = 157, 3001 | CV_SHMEDIA_FR30 = 158, 3002 | CV_SHMEDIA_FR31 = 159, 3003 | CV_SHMEDIA_FR32 = 160, 3004 | CV_SHMEDIA_FR33 = 161, 3005 | CV_SHMEDIA_FR34 = 162, 3006 | CV_SHMEDIA_FR35 = 163, 3007 | CV_SHMEDIA_FR36 = 164, 3008 | CV_SHMEDIA_FR37 = 165, 3009 | CV_SHMEDIA_FR38 = 166, 3010 | CV_SHMEDIA_FR39 = 167, 3011 | CV_SHMEDIA_FR40 = 168, 3012 | CV_SHMEDIA_FR41 = 169, 3013 | CV_SHMEDIA_FR42 = 170, 3014 | CV_SHMEDIA_FR43 = 171, 3015 | CV_SHMEDIA_FR44 = 172, 3016 | CV_SHMEDIA_FR45 = 173, 3017 | CV_SHMEDIA_FR46 = 174, 3018 | CV_SHMEDIA_FR47 = 175, 3019 | CV_SHMEDIA_FR48 = 176, 3020 | CV_SHMEDIA_FR49 = 177, 3021 | CV_SHMEDIA_FR50 = 178, 3022 | CV_SHMEDIA_FR51 = 179, 3023 | CV_SHMEDIA_FR52 = 180, 3024 | CV_SHMEDIA_FR53 = 181, 3025 | CV_SHMEDIA_FR54 = 182, 3026 | CV_SHMEDIA_FR55 = 183, 3027 | CV_SHMEDIA_FR56 = 184, 3028 | CV_SHMEDIA_FR57 = 185, 3029 | CV_SHMEDIA_FR58 = 186, 3030 | CV_SHMEDIA_FR59 = 187, 3031 | CV_SHMEDIA_FR60 = 188, 3032 | CV_SHMEDIA_FR61 = 189, 3033 | CV_SHMEDIA_FR62 = 190, 3034 | CV_SHMEDIA_FR63 = 191, 3035 | 3036 | // Double - 64 bit synonyms for 32bit fp register pairs 3037 | // subtract 128 to find first base single register 3038 | CV_SHMEDIA_DR0 = 256, 3039 | CV_SHMEDIA_DR2 = 258, 3040 | CV_SHMEDIA_DR4 = 260, 3041 | CV_SHMEDIA_DR6 = 262, 3042 | CV_SHMEDIA_DR8 = 264, 3043 | CV_SHMEDIA_DR10 = 266, 3044 | CV_SHMEDIA_DR12 = 268, 3045 | CV_SHMEDIA_DR14 = 270, 3046 | CV_SHMEDIA_DR16 = 272, 3047 | CV_SHMEDIA_DR18 = 274, 3048 | CV_SHMEDIA_DR20 = 276, 3049 | CV_SHMEDIA_DR22 = 278, 3050 | CV_SHMEDIA_DR24 = 280, 3051 | CV_SHMEDIA_DR26 = 282, 3052 | CV_SHMEDIA_DR28 = 284, 3053 | CV_SHMEDIA_DR30 = 286, 3054 | CV_SHMEDIA_DR32 = 288, 3055 | CV_SHMEDIA_DR34 = 290, 3056 | CV_SHMEDIA_DR36 = 292, 3057 | CV_SHMEDIA_DR38 = 294, 3058 | CV_SHMEDIA_DR40 = 296, 3059 | CV_SHMEDIA_DR42 = 298, 3060 | CV_SHMEDIA_DR44 = 300, 3061 | CV_SHMEDIA_DR46 = 302, 3062 | CV_SHMEDIA_DR48 = 304, 3063 | CV_SHMEDIA_DR50 = 306, 3064 | CV_SHMEDIA_DR52 = 308, 3065 | CV_SHMEDIA_DR54 = 310, 3066 | CV_SHMEDIA_DR56 = 312, 3067 | CV_SHMEDIA_DR58 = 314, 3068 | CV_SHMEDIA_DR60 = 316, 3069 | CV_SHMEDIA_DR62 = 318, 3070 | 3071 | // Vector - 128 bit synonyms for 32bit fp register quads 3072 | // subtract 384 to find first base single register 3073 | CV_SHMEDIA_FV0 = 512, 3074 | CV_SHMEDIA_FV4 = 516, 3075 | CV_SHMEDIA_FV8 = 520, 3076 | CV_SHMEDIA_FV12 = 524, 3077 | CV_SHMEDIA_FV16 = 528, 3078 | CV_SHMEDIA_FV20 = 532, 3079 | CV_SHMEDIA_FV24 = 536, 3080 | CV_SHMEDIA_FV28 = 540, 3081 | CV_SHMEDIA_FV32 = 544, 3082 | CV_SHMEDIA_FV36 = 548, 3083 | CV_SHMEDIA_FV40 = 552, 3084 | CV_SHMEDIA_FV44 = 556, 3085 | CV_SHMEDIA_FV48 = 560, 3086 | CV_SHMEDIA_FV52 = 564, 3087 | CV_SHMEDIA_FV56 = 568, 3088 | CV_SHMEDIA_FV60 = 572, 3089 | 3090 | // Matrix - 512 bit synonyms for 16 adjacent 32bit fp registers 3091 | // subtract 896 to find first base single register 3092 | CV_SHMEDIA_MTRX0 = 1024, 3093 | CV_SHMEDIA_MTRX16 = 1040, 3094 | CV_SHMEDIA_MTRX32 = 1056, 3095 | CV_SHMEDIA_MTRX48 = 1072, 3096 | 3097 | // Control - Implementation defined 64bit control registers 3098 | CV_SHMEDIA_CR0 = 2000, 3099 | CV_SHMEDIA_CR1 = 2001, 3100 | CV_SHMEDIA_CR2 = 2002, 3101 | CV_SHMEDIA_CR3 = 2003, 3102 | CV_SHMEDIA_CR4 = 2004, 3103 | CV_SHMEDIA_CR5 = 2005, 3104 | CV_SHMEDIA_CR6 = 2006, 3105 | CV_SHMEDIA_CR7 = 2007, 3106 | CV_SHMEDIA_CR8 = 2008, 3107 | CV_SHMEDIA_CR9 = 2009, 3108 | CV_SHMEDIA_CR10 = 2010, 3109 | CV_SHMEDIA_CR11 = 2011, 3110 | CV_SHMEDIA_CR12 = 2012, 3111 | CV_SHMEDIA_CR13 = 2013, 3112 | CV_SHMEDIA_CR14 = 2014, 3113 | CV_SHMEDIA_CR15 = 2015, 3114 | CV_SHMEDIA_CR16 = 2016, 3115 | CV_SHMEDIA_CR17 = 2017, 3116 | CV_SHMEDIA_CR18 = 2018, 3117 | CV_SHMEDIA_CR19 = 2019, 3118 | CV_SHMEDIA_CR20 = 2020, 3119 | CV_SHMEDIA_CR21 = 2021, 3120 | CV_SHMEDIA_CR22 = 2022, 3121 | CV_SHMEDIA_CR23 = 2023, 3122 | CV_SHMEDIA_CR24 = 2024, 3123 | CV_SHMEDIA_CR25 = 2025, 3124 | CV_SHMEDIA_CR26 = 2026, 3125 | CV_SHMEDIA_CR27 = 2027, 3126 | CV_SHMEDIA_CR28 = 2028, 3127 | CV_SHMEDIA_CR29 = 2029, 3128 | CV_SHMEDIA_CR30 = 2030, 3129 | CV_SHMEDIA_CR31 = 2031, 3130 | CV_SHMEDIA_CR32 = 2032, 3131 | CV_SHMEDIA_CR33 = 2033, 3132 | CV_SHMEDIA_CR34 = 2034, 3133 | CV_SHMEDIA_CR35 = 2035, 3134 | CV_SHMEDIA_CR36 = 2036, 3135 | CV_SHMEDIA_CR37 = 2037, 3136 | CV_SHMEDIA_CR38 = 2038, 3137 | CV_SHMEDIA_CR39 = 2039, 3138 | CV_SHMEDIA_CR40 = 2040, 3139 | CV_SHMEDIA_CR41 = 2041, 3140 | CV_SHMEDIA_CR42 = 2042, 3141 | CV_SHMEDIA_CR43 = 2043, 3142 | CV_SHMEDIA_CR44 = 2044, 3143 | CV_SHMEDIA_CR45 = 2045, 3144 | CV_SHMEDIA_CR46 = 2046, 3145 | CV_SHMEDIA_CR47 = 2047, 3146 | CV_SHMEDIA_CR48 = 2048, 3147 | CV_SHMEDIA_CR49 = 2049, 3148 | CV_SHMEDIA_CR50 = 2050, 3149 | CV_SHMEDIA_CR51 = 2051, 3150 | CV_SHMEDIA_CR52 = 2052, 3151 | CV_SHMEDIA_CR53 = 2053, 3152 | CV_SHMEDIA_CR54 = 2054, 3153 | CV_SHMEDIA_CR55 = 2055, 3154 | CV_SHMEDIA_CR56 = 2056, 3155 | CV_SHMEDIA_CR57 = 2057, 3156 | CV_SHMEDIA_CR58 = 2058, 3157 | CV_SHMEDIA_CR59 = 2059, 3158 | CV_SHMEDIA_CR60 = 2060, 3159 | CV_SHMEDIA_CR61 = 2061, 3160 | CV_SHMEDIA_CR62 = 2062, 3161 | CV_SHMEDIA_CR63 = 2063, 3162 | 3163 | CV_SHMEDIA_FPSCR = 2064, 3164 | 3165 | // Compact mode synonyms 3166 | CV_SHMEDIA_GBR = CV_SHMEDIA_R16, 3167 | CV_SHMEDIA_MACL = 90, // synonym for lower 32bits of media R17 3168 | CV_SHMEDIA_MACH = 91, // synonym for upper 32bits of media R17 3169 | CV_SHMEDIA_PR = CV_SHMEDIA_R18, 3170 | CV_SHMEDIA_T = 92, // synonym for lowest bit of media R19 3171 | CV_SHMEDIA_FPUL = CV_SHMEDIA_FR32, 3172 | CV_SHMEDIA_PC = 93, 3173 | CV_SHMEDIA_SR = CV_SHMEDIA_CR0, 3174 | 3175 | // 3176 | // AMD64 registers 3177 | // 3178 | 3179 | CV_AMD64_AL = 1, 3180 | CV_AMD64_CL = 2, 3181 | CV_AMD64_DL = 3, 3182 | CV_AMD64_BL = 4, 3183 | CV_AMD64_AH = 5, 3184 | CV_AMD64_CH = 6, 3185 | CV_AMD64_DH = 7, 3186 | CV_AMD64_BH = 8, 3187 | CV_AMD64_AX = 9, 3188 | CV_AMD64_CX = 10, 3189 | CV_AMD64_DX = 11, 3190 | CV_AMD64_BX = 12, 3191 | CV_AMD64_SP = 13, 3192 | CV_AMD64_BP = 14, 3193 | CV_AMD64_SI = 15, 3194 | CV_AMD64_DI = 16, 3195 | CV_AMD64_EAX = 17, 3196 | CV_AMD64_ECX = 18, 3197 | CV_AMD64_EDX = 19, 3198 | CV_AMD64_EBX = 20, 3199 | CV_AMD64_ESP = 21, 3200 | CV_AMD64_EBP = 22, 3201 | CV_AMD64_ESI = 23, 3202 | CV_AMD64_EDI = 24, 3203 | CV_AMD64_ES = 25, 3204 | CV_AMD64_CS = 26, 3205 | CV_AMD64_SS = 27, 3206 | CV_AMD64_DS = 28, 3207 | CV_AMD64_FS = 29, 3208 | CV_AMD64_GS = 30, 3209 | CV_AMD64_FLAGS = 32, 3210 | CV_AMD64_RIP = 33, 3211 | CV_AMD64_EFLAGS = 34, 3212 | 3213 | // Control registers 3214 | CV_AMD64_CR0 = 80, 3215 | CV_AMD64_CR1 = 81, 3216 | CV_AMD64_CR2 = 82, 3217 | CV_AMD64_CR3 = 83, 3218 | CV_AMD64_CR4 = 84, 3219 | CV_AMD64_CR8 = 88, 3220 | 3221 | // Debug registers 3222 | CV_AMD64_DR0 = 90, 3223 | CV_AMD64_DR1 = 91, 3224 | CV_AMD64_DR2 = 92, 3225 | CV_AMD64_DR3 = 93, 3226 | CV_AMD64_DR4 = 94, 3227 | CV_AMD64_DR5 = 95, 3228 | CV_AMD64_DR6 = 96, 3229 | CV_AMD64_DR7 = 97, 3230 | CV_AMD64_DR8 = 98, 3231 | CV_AMD64_DR9 = 99, 3232 | CV_AMD64_DR10 = 100, 3233 | CV_AMD64_DR11 = 101, 3234 | CV_AMD64_DR12 = 102, 3235 | CV_AMD64_DR13 = 103, 3236 | CV_AMD64_DR14 = 104, 3237 | CV_AMD64_DR15 = 105, 3238 | 3239 | CV_AMD64_GDTR = 110, 3240 | CV_AMD64_GDTL = 111, 3241 | CV_AMD64_IDTR = 112, 3242 | CV_AMD64_IDTL = 113, 3243 | CV_AMD64_LDTR = 114, 3244 | CV_AMD64_TR = 115, 3245 | 3246 | CV_AMD64_ST0 = 128, 3247 | CV_AMD64_ST1 = 129, 3248 | CV_AMD64_ST2 = 130, 3249 | CV_AMD64_ST3 = 131, 3250 | CV_AMD64_ST4 = 132, 3251 | CV_AMD64_ST5 = 133, 3252 | CV_AMD64_ST6 = 134, 3253 | CV_AMD64_ST7 = 135, 3254 | CV_AMD64_CTRL = 136, 3255 | CV_AMD64_STAT = 137, 3256 | CV_AMD64_TAG = 138, 3257 | CV_AMD64_FPIP = 139, 3258 | CV_AMD64_FPCS = 140, 3259 | CV_AMD64_FPDO = 141, 3260 | CV_AMD64_FPDS = 142, 3261 | CV_AMD64_ISEM = 143, 3262 | CV_AMD64_FPEIP = 144, 3263 | CV_AMD64_FPEDO = 145, 3264 | 3265 | CV_AMD64_MM0 = 146, 3266 | CV_AMD64_MM1 = 147, 3267 | CV_AMD64_MM2 = 148, 3268 | CV_AMD64_MM3 = 149, 3269 | CV_AMD64_MM4 = 150, 3270 | CV_AMD64_MM5 = 151, 3271 | CV_AMD64_MM6 = 152, 3272 | CV_AMD64_MM7 = 153, 3273 | 3274 | CV_AMD64_XMM0 = 154, // KATMAI registers 3275 | CV_AMD64_XMM1 = 155, 3276 | CV_AMD64_XMM2 = 156, 3277 | CV_AMD64_XMM3 = 157, 3278 | CV_AMD64_XMM4 = 158, 3279 | CV_AMD64_XMM5 = 159, 3280 | CV_AMD64_XMM6 = 160, 3281 | CV_AMD64_XMM7 = 161, 3282 | 3283 | CV_AMD64_XMM0_0 = 162, // KATMAI sub-registers 3284 | CV_AMD64_XMM0_1 = 163, 3285 | CV_AMD64_XMM0_2 = 164, 3286 | CV_AMD64_XMM0_3 = 165, 3287 | CV_AMD64_XMM1_0 = 166, 3288 | CV_AMD64_XMM1_1 = 167, 3289 | CV_AMD64_XMM1_2 = 168, 3290 | CV_AMD64_XMM1_3 = 169, 3291 | CV_AMD64_XMM2_0 = 170, 3292 | CV_AMD64_XMM2_1 = 171, 3293 | CV_AMD64_XMM2_2 = 172, 3294 | CV_AMD64_XMM2_3 = 173, 3295 | CV_AMD64_XMM3_0 = 174, 3296 | CV_AMD64_XMM3_1 = 175, 3297 | CV_AMD64_XMM3_2 = 176, 3298 | CV_AMD64_XMM3_3 = 177, 3299 | CV_AMD64_XMM4_0 = 178, 3300 | CV_AMD64_XMM4_1 = 179, 3301 | CV_AMD64_XMM4_2 = 180, 3302 | CV_AMD64_XMM4_3 = 181, 3303 | CV_AMD64_XMM5_0 = 182, 3304 | CV_AMD64_XMM5_1 = 183, 3305 | CV_AMD64_XMM5_2 = 184, 3306 | CV_AMD64_XMM5_3 = 185, 3307 | CV_AMD64_XMM6_0 = 186, 3308 | CV_AMD64_XMM6_1 = 187, 3309 | CV_AMD64_XMM6_2 = 188, 3310 | CV_AMD64_XMM6_3 = 189, 3311 | CV_AMD64_XMM7_0 = 190, 3312 | CV_AMD64_XMM7_1 = 191, 3313 | CV_AMD64_XMM7_2 = 192, 3314 | CV_AMD64_XMM7_3 = 193, 3315 | 3316 | CV_AMD64_XMM0L = 194, 3317 | CV_AMD64_XMM1L = 195, 3318 | CV_AMD64_XMM2L = 196, 3319 | CV_AMD64_XMM3L = 197, 3320 | CV_AMD64_XMM4L = 198, 3321 | CV_AMD64_XMM5L = 199, 3322 | CV_AMD64_XMM6L = 200, 3323 | CV_AMD64_XMM7L = 201, 3324 | 3325 | CV_AMD64_XMM0H = 202, 3326 | CV_AMD64_XMM1H = 203, 3327 | CV_AMD64_XMM2H = 204, 3328 | CV_AMD64_XMM3H = 205, 3329 | CV_AMD64_XMM4H = 206, 3330 | CV_AMD64_XMM5H = 207, 3331 | CV_AMD64_XMM6H = 208, 3332 | CV_AMD64_XMM7H = 209, 3333 | 3334 | CV_AMD64_MXCSR = 211, // XMM status register 3335 | 3336 | CV_AMD64_EMM0L = 220, // XMM sub-registers (WNI integer) 3337 | CV_AMD64_EMM1L = 221, 3338 | CV_AMD64_EMM2L = 222, 3339 | CV_AMD64_EMM3L = 223, 3340 | CV_AMD64_EMM4L = 224, 3341 | CV_AMD64_EMM5L = 225, 3342 | CV_AMD64_EMM6L = 226, 3343 | CV_AMD64_EMM7L = 227, 3344 | 3345 | CV_AMD64_EMM0H = 228, 3346 | CV_AMD64_EMM1H = 229, 3347 | CV_AMD64_EMM2H = 230, 3348 | CV_AMD64_EMM3H = 231, 3349 | CV_AMD64_EMM4H = 232, 3350 | CV_AMD64_EMM5H = 233, 3351 | CV_AMD64_EMM6H = 234, 3352 | CV_AMD64_EMM7H = 235, 3353 | 3354 | // do not change the order of these regs, first one must be even too 3355 | CV_AMD64_MM00 = 236, 3356 | CV_AMD64_MM01 = 237, 3357 | CV_AMD64_MM10 = 238, 3358 | CV_AMD64_MM11 = 239, 3359 | CV_AMD64_MM20 = 240, 3360 | CV_AMD64_MM21 = 241, 3361 | CV_AMD64_MM30 = 242, 3362 | CV_AMD64_MM31 = 243, 3363 | CV_AMD64_MM40 = 244, 3364 | CV_AMD64_MM41 = 245, 3365 | CV_AMD64_MM50 = 246, 3366 | CV_AMD64_MM51 = 247, 3367 | CV_AMD64_MM60 = 248, 3368 | CV_AMD64_MM61 = 249, 3369 | CV_AMD64_MM70 = 250, 3370 | CV_AMD64_MM71 = 251, 3371 | 3372 | // Extended KATMAI registers 3373 | CV_AMD64_XMM8 = 252, // KATMAI registers 3374 | CV_AMD64_XMM9 = 253, 3375 | CV_AMD64_XMM10 = 254, 3376 | CV_AMD64_XMM11 = 255, 3377 | CV_AMD64_XMM12 = 256, 3378 | CV_AMD64_XMM13 = 257, 3379 | CV_AMD64_XMM14 = 258, 3380 | CV_AMD64_XMM15 = 259, 3381 | 3382 | CV_AMD64_XMM8_0 = 260, // KATMAI sub-registers 3383 | CV_AMD64_XMM8_1 = 261, 3384 | CV_AMD64_XMM8_2 = 262, 3385 | CV_AMD64_XMM8_3 = 263, 3386 | CV_AMD64_XMM9_0 = 264, 3387 | CV_AMD64_XMM9_1 = 265, 3388 | CV_AMD64_XMM9_2 = 266, 3389 | CV_AMD64_XMM9_3 = 267, 3390 | CV_AMD64_XMM10_0 = 268, 3391 | CV_AMD64_XMM10_1 = 269, 3392 | CV_AMD64_XMM10_2 = 270, 3393 | CV_AMD64_XMM10_3 = 271, 3394 | CV_AMD64_XMM11_0 = 272, 3395 | CV_AMD64_XMM11_1 = 273, 3396 | CV_AMD64_XMM11_2 = 274, 3397 | CV_AMD64_XMM11_3 = 275, 3398 | CV_AMD64_XMM12_0 = 276, 3399 | CV_AMD64_XMM12_1 = 277, 3400 | CV_AMD64_XMM12_2 = 278, 3401 | CV_AMD64_XMM12_3 = 279, 3402 | CV_AMD64_XMM13_0 = 280, 3403 | CV_AMD64_XMM13_1 = 281, 3404 | CV_AMD64_XMM13_2 = 282, 3405 | CV_AMD64_XMM13_3 = 283, 3406 | CV_AMD64_XMM14_0 = 284, 3407 | CV_AMD64_XMM14_1 = 285, 3408 | CV_AMD64_XMM14_2 = 286, 3409 | CV_AMD64_XMM14_3 = 287, 3410 | CV_AMD64_XMM15_0 = 288, 3411 | CV_AMD64_XMM15_1 = 289, 3412 | CV_AMD64_XMM15_2 = 290, 3413 | CV_AMD64_XMM15_3 = 291, 3414 | 3415 | CV_AMD64_XMM8L = 292, 3416 | CV_AMD64_XMM9L = 293, 3417 | CV_AMD64_XMM10L = 294, 3418 | CV_AMD64_XMM11L = 295, 3419 | CV_AMD64_XMM12L = 296, 3420 | CV_AMD64_XMM13L = 297, 3421 | CV_AMD64_XMM14L = 298, 3422 | CV_AMD64_XMM15L = 299, 3423 | 3424 | CV_AMD64_XMM8H = 300, 3425 | CV_AMD64_XMM9H = 301, 3426 | CV_AMD64_XMM10H = 302, 3427 | CV_AMD64_XMM11H = 303, 3428 | CV_AMD64_XMM12H = 304, 3429 | CV_AMD64_XMM13H = 305, 3430 | CV_AMD64_XMM14H = 306, 3431 | CV_AMD64_XMM15H = 307, 3432 | 3433 | CV_AMD64_EMM8L = 308, // XMM sub-registers (WNI integer) 3434 | CV_AMD64_EMM9L = 309, 3435 | CV_AMD64_EMM10L = 310, 3436 | CV_AMD64_EMM11L = 311, 3437 | CV_AMD64_EMM12L = 312, 3438 | CV_AMD64_EMM13L = 313, 3439 | CV_AMD64_EMM14L = 314, 3440 | CV_AMD64_EMM15L = 315, 3441 | 3442 | CV_AMD64_EMM8H = 316, 3443 | CV_AMD64_EMM9H = 317, 3444 | CV_AMD64_EMM10H = 318, 3445 | CV_AMD64_EMM11H = 319, 3446 | CV_AMD64_EMM12H = 320, 3447 | CV_AMD64_EMM13H = 321, 3448 | CV_AMD64_EMM14H = 322, 3449 | CV_AMD64_EMM15H = 323, 3450 | 3451 | // Low byte forms of some standard registers 3452 | CV_AMD64_SIL = 324, 3453 | CV_AMD64_DIL = 325, 3454 | CV_AMD64_BPL = 326, 3455 | CV_AMD64_SPL = 327, 3456 | 3457 | // 64-bit regular registers 3458 | CV_AMD64_RAX = 328, 3459 | CV_AMD64_RBX = 329, 3460 | CV_AMD64_RCX = 330, 3461 | CV_AMD64_RDX = 331, 3462 | CV_AMD64_RSI = 332, 3463 | CV_AMD64_RDI = 333, 3464 | CV_AMD64_RBP = 334, 3465 | CV_AMD64_RSP = 335, 3466 | 3467 | // 64-bit integer registers with 8-, 16-, and 32-bit forms (B, W, and D) 3468 | CV_AMD64_R8 = 336, 3469 | CV_AMD64_R9 = 337, 3470 | CV_AMD64_R10 = 338, 3471 | CV_AMD64_R11 = 339, 3472 | CV_AMD64_R12 = 340, 3473 | CV_AMD64_R13 = 341, 3474 | CV_AMD64_R14 = 342, 3475 | CV_AMD64_R15 = 343, 3476 | 3477 | CV_AMD64_R8B = 344, 3478 | CV_AMD64_R9B = 345, 3479 | CV_AMD64_R10B = 346, 3480 | CV_AMD64_R11B = 347, 3481 | CV_AMD64_R12B = 348, 3482 | CV_AMD64_R13B = 349, 3483 | CV_AMD64_R14B = 350, 3484 | CV_AMD64_R15B = 351, 3485 | 3486 | CV_AMD64_R8W = 352, 3487 | CV_AMD64_R9W = 353, 3488 | CV_AMD64_R10W = 354, 3489 | CV_AMD64_R11W = 355, 3490 | CV_AMD64_R12W = 356, 3491 | CV_AMD64_R13W = 357, 3492 | CV_AMD64_R14W = 358, 3493 | CV_AMD64_R15W = 359, 3494 | 3495 | CV_AMD64_R8D = 360, 3496 | CV_AMD64_R9D = 361, 3497 | CV_AMD64_R10D = 362, 3498 | CV_AMD64_R11D = 363, 3499 | CV_AMD64_R12D = 364, 3500 | CV_AMD64_R13D = 365, 3501 | CV_AMD64_R14D = 366, 3502 | CV_AMD64_R15D = 367, 3503 | 3504 | // AVX registers 256 bits 3505 | CV_AMD64_YMM0 = 368, 3506 | CV_AMD64_YMM1 = 369, 3507 | CV_AMD64_YMM2 = 370, 3508 | CV_AMD64_YMM3 = 371, 3509 | CV_AMD64_YMM4 = 372, 3510 | CV_AMD64_YMM5 = 373, 3511 | CV_AMD64_YMM6 = 374, 3512 | CV_AMD64_YMM7 = 375, 3513 | CV_AMD64_YMM8 = 376, 3514 | CV_AMD64_YMM9 = 377, 3515 | CV_AMD64_YMM10 = 378, 3516 | CV_AMD64_YMM11 = 379, 3517 | CV_AMD64_YMM12 = 380, 3518 | CV_AMD64_YMM13 = 381, 3519 | CV_AMD64_YMM14 = 382, 3520 | CV_AMD64_YMM15 = 383, 3521 | 3522 | // AVX registers upper 128 bits 3523 | CV_AMD64_YMM0H = 384, 3524 | CV_AMD64_YMM1H = 385, 3525 | CV_AMD64_YMM2H = 386, 3526 | CV_AMD64_YMM3H = 387, 3527 | CV_AMD64_YMM4H = 388, 3528 | CV_AMD64_YMM5H = 389, 3529 | CV_AMD64_YMM6H = 390, 3530 | CV_AMD64_YMM7H = 391, 3531 | CV_AMD64_YMM8H = 392, 3532 | CV_AMD64_YMM9H = 393, 3533 | CV_AMD64_YMM10H = 394, 3534 | CV_AMD64_YMM11H = 395, 3535 | CV_AMD64_YMM12H = 396, 3536 | CV_AMD64_YMM13H = 397, 3537 | CV_AMD64_YMM14H = 398, 3538 | CV_AMD64_YMM15H = 399, 3539 | 3540 | //Lower/upper 8 bytes of XMM registers. Unlike CV_AMD64_XMM, these 3541 | //values reprsesent the bit patterns of the registers as 64-bit integers, not 3542 | //the representation of these registers as a double. 3543 | CV_AMD64_XMM0IL = 400, 3544 | CV_AMD64_XMM1IL = 401, 3545 | CV_AMD64_XMM2IL = 402, 3546 | CV_AMD64_XMM3IL = 403, 3547 | CV_AMD64_XMM4IL = 404, 3548 | CV_AMD64_XMM5IL = 405, 3549 | CV_AMD64_XMM6IL = 406, 3550 | CV_AMD64_XMM7IL = 407, 3551 | CV_AMD64_XMM8IL = 408, 3552 | CV_AMD64_XMM9IL = 409, 3553 | CV_AMD64_XMM10IL = 410, 3554 | CV_AMD64_XMM11IL = 411, 3555 | CV_AMD64_XMM12IL = 412, 3556 | CV_AMD64_XMM13IL = 413, 3557 | CV_AMD64_XMM14IL = 414, 3558 | CV_AMD64_XMM15IL = 415, 3559 | 3560 | CV_AMD64_XMM0IH = 416, 3561 | CV_AMD64_XMM1IH = 417, 3562 | CV_AMD64_XMM2IH = 418, 3563 | CV_AMD64_XMM3IH = 419, 3564 | CV_AMD64_XMM4IH = 420, 3565 | CV_AMD64_XMM5IH = 421, 3566 | CV_AMD64_XMM6IH = 422, 3567 | CV_AMD64_XMM7IH = 423, 3568 | CV_AMD64_XMM8IH = 424, 3569 | CV_AMD64_XMM9IH = 425, 3570 | CV_AMD64_XMM10IH = 426, 3571 | CV_AMD64_XMM11IH = 427, 3572 | CV_AMD64_XMM12IH = 428, 3573 | CV_AMD64_XMM13IH = 429, 3574 | CV_AMD64_XMM14IH = 430, 3575 | CV_AMD64_XMM15IH = 431, 3576 | 3577 | CV_AMD64_YMM0I0 = 432, // AVX integer registers 3578 | CV_AMD64_YMM0I1 = 433, 3579 | CV_AMD64_YMM0I2 = 434, 3580 | CV_AMD64_YMM0I3 = 435, 3581 | CV_AMD64_YMM1I0 = 436, 3582 | CV_AMD64_YMM1I1 = 437, 3583 | CV_AMD64_YMM1I2 = 438, 3584 | CV_AMD64_YMM1I3 = 439, 3585 | CV_AMD64_YMM2I0 = 440, 3586 | CV_AMD64_YMM2I1 = 441, 3587 | CV_AMD64_YMM2I2 = 442, 3588 | CV_AMD64_YMM2I3 = 443, 3589 | CV_AMD64_YMM3I0 = 444, 3590 | CV_AMD64_YMM3I1 = 445, 3591 | CV_AMD64_YMM3I2 = 446, 3592 | CV_AMD64_YMM3I3 = 447, 3593 | CV_AMD64_YMM4I0 = 448, 3594 | CV_AMD64_YMM4I1 = 449, 3595 | CV_AMD64_YMM4I2 = 450, 3596 | CV_AMD64_YMM4I3 = 451, 3597 | CV_AMD64_YMM5I0 = 452, 3598 | CV_AMD64_YMM5I1 = 453, 3599 | CV_AMD64_YMM5I2 = 454, 3600 | CV_AMD64_YMM5I3 = 455, 3601 | CV_AMD64_YMM6I0 = 456, 3602 | CV_AMD64_YMM6I1 = 457, 3603 | CV_AMD64_YMM6I2 = 458, 3604 | CV_AMD64_YMM6I3 = 459, 3605 | CV_AMD64_YMM7I0 = 460, 3606 | CV_AMD64_YMM7I1 = 461, 3607 | CV_AMD64_YMM7I2 = 462, 3608 | CV_AMD64_YMM7I3 = 463, 3609 | CV_AMD64_YMM8I0 = 464, 3610 | CV_AMD64_YMM8I1 = 465, 3611 | CV_AMD64_YMM8I2 = 466, 3612 | CV_AMD64_YMM8I3 = 467, 3613 | CV_AMD64_YMM9I0 = 468, 3614 | CV_AMD64_YMM9I1 = 469, 3615 | CV_AMD64_YMM9I2 = 470, 3616 | CV_AMD64_YMM9I3 = 471, 3617 | CV_AMD64_YMM10I0 = 472, 3618 | CV_AMD64_YMM10I1 = 473, 3619 | CV_AMD64_YMM10I2 = 474, 3620 | CV_AMD64_YMM10I3 = 475, 3621 | CV_AMD64_YMM11I0 = 476, 3622 | CV_AMD64_YMM11I1 = 477, 3623 | CV_AMD64_YMM11I2 = 478, 3624 | CV_AMD64_YMM11I3 = 479, 3625 | CV_AMD64_YMM12I0 = 480, 3626 | CV_AMD64_YMM12I1 = 481, 3627 | CV_AMD64_YMM12I2 = 482, 3628 | CV_AMD64_YMM12I3 = 483, 3629 | CV_AMD64_YMM13I0 = 484, 3630 | CV_AMD64_YMM13I1 = 485, 3631 | CV_AMD64_YMM13I2 = 486, 3632 | CV_AMD64_YMM13I3 = 487, 3633 | CV_AMD64_YMM14I0 = 488, 3634 | CV_AMD64_YMM14I1 = 489, 3635 | CV_AMD64_YMM14I2 = 490, 3636 | CV_AMD64_YMM14I3 = 491, 3637 | CV_AMD64_YMM15I0 = 492, 3638 | CV_AMD64_YMM15I1 = 493, 3639 | CV_AMD64_YMM15I2 = 494, 3640 | CV_AMD64_YMM15I3 = 495, 3641 | 3642 | CV_AMD64_YMM0F0 = 496, // AVX floating-point single precise registers 3643 | CV_AMD64_YMM0F1 = 497, 3644 | CV_AMD64_YMM0F2 = 498, 3645 | CV_AMD64_YMM0F3 = 499, 3646 | CV_AMD64_YMM0F4 = 500, 3647 | CV_AMD64_YMM0F5 = 501, 3648 | CV_AMD64_YMM0F6 = 502, 3649 | CV_AMD64_YMM0F7 = 503, 3650 | CV_AMD64_YMM1F0 = 504, 3651 | CV_AMD64_YMM1F1 = 505, 3652 | CV_AMD64_YMM1F2 = 506, 3653 | CV_AMD64_YMM1F3 = 507, 3654 | CV_AMD64_YMM1F4 = 508, 3655 | CV_AMD64_YMM1F5 = 509, 3656 | CV_AMD64_YMM1F6 = 510, 3657 | CV_AMD64_YMM1F7 = 511, 3658 | CV_AMD64_YMM2F0 = 512, 3659 | CV_AMD64_YMM2F1 = 513, 3660 | CV_AMD64_YMM2F2 = 514, 3661 | CV_AMD64_YMM2F3 = 515, 3662 | CV_AMD64_YMM2F4 = 516, 3663 | CV_AMD64_YMM2F5 = 517, 3664 | CV_AMD64_YMM2F6 = 518, 3665 | CV_AMD64_YMM2F7 = 519, 3666 | CV_AMD64_YMM3F0 = 520, 3667 | CV_AMD64_YMM3F1 = 521, 3668 | CV_AMD64_YMM3F2 = 522, 3669 | CV_AMD64_YMM3F3 = 523, 3670 | CV_AMD64_YMM3F4 = 524, 3671 | CV_AMD64_YMM3F5 = 525, 3672 | CV_AMD64_YMM3F6 = 526, 3673 | CV_AMD64_YMM3F7 = 527, 3674 | CV_AMD64_YMM4F0 = 528, 3675 | CV_AMD64_YMM4F1 = 529, 3676 | CV_AMD64_YMM4F2 = 530, 3677 | CV_AMD64_YMM4F3 = 531, 3678 | CV_AMD64_YMM4F4 = 532, 3679 | CV_AMD64_YMM4F5 = 533, 3680 | CV_AMD64_YMM4F6 = 534, 3681 | CV_AMD64_YMM4F7 = 535, 3682 | CV_AMD64_YMM5F0 = 536, 3683 | CV_AMD64_YMM5F1 = 537, 3684 | CV_AMD64_YMM5F2 = 538, 3685 | CV_AMD64_YMM5F3 = 539, 3686 | CV_AMD64_YMM5F4 = 540, 3687 | CV_AMD64_YMM5F5 = 541, 3688 | CV_AMD64_YMM5F6 = 542, 3689 | CV_AMD64_YMM5F7 = 543, 3690 | CV_AMD64_YMM6F0 = 544, 3691 | CV_AMD64_YMM6F1 = 545, 3692 | CV_AMD64_YMM6F2 = 546, 3693 | CV_AMD64_YMM6F3 = 547, 3694 | CV_AMD64_YMM6F4 = 548, 3695 | CV_AMD64_YMM6F5 = 549, 3696 | CV_AMD64_YMM6F6 = 550, 3697 | CV_AMD64_YMM6F7 = 551, 3698 | CV_AMD64_YMM7F0 = 552, 3699 | CV_AMD64_YMM7F1 = 553, 3700 | CV_AMD64_YMM7F2 = 554, 3701 | CV_AMD64_YMM7F3 = 555, 3702 | CV_AMD64_YMM7F4 = 556, 3703 | CV_AMD64_YMM7F5 = 557, 3704 | CV_AMD64_YMM7F6 = 558, 3705 | CV_AMD64_YMM7F7 = 559, 3706 | CV_AMD64_YMM8F0 = 560, 3707 | CV_AMD64_YMM8F1 = 561, 3708 | CV_AMD64_YMM8F2 = 562, 3709 | CV_AMD64_YMM8F3 = 563, 3710 | CV_AMD64_YMM8F4 = 564, 3711 | CV_AMD64_YMM8F5 = 565, 3712 | CV_AMD64_YMM8F6 = 566, 3713 | CV_AMD64_YMM8F7 = 567, 3714 | CV_AMD64_YMM9F0 = 568, 3715 | CV_AMD64_YMM9F1 = 569, 3716 | CV_AMD64_YMM9F2 = 570, 3717 | CV_AMD64_YMM9F3 = 571, 3718 | CV_AMD64_YMM9F4 = 572, 3719 | CV_AMD64_YMM9F5 = 573, 3720 | CV_AMD64_YMM9F6 = 574, 3721 | CV_AMD64_YMM9F7 = 575, 3722 | CV_AMD64_YMM10F0 = 576, 3723 | CV_AMD64_YMM10F1 = 577, 3724 | CV_AMD64_YMM10F2 = 578, 3725 | CV_AMD64_YMM10F3 = 579, 3726 | CV_AMD64_YMM10F4 = 580, 3727 | CV_AMD64_YMM10F5 = 581, 3728 | CV_AMD64_YMM10F6 = 582, 3729 | CV_AMD64_YMM10F7 = 583, 3730 | CV_AMD64_YMM11F0 = 584, 3731 | CV_AMD64_YMM11F1 = 585, 3732 | CV_AMD64_YMM11F2 = 586, 3733 | CV_AMD64_YMM11F3 = 587, 3734 | CV_AMD64_YMM11F4 = 588, 3735 | CV_AMD64_YMM11F5 = 589, 3736 | CV_AMD64_YMM11F6 = 590, 3737 | CV_AMD64_YMM11F7 = 591, 3738 | CV_AMD64_YMM12F0 = 592, 3739 | CV_AMD64_YMM12F1 = 593, 3740 | CV_AMD64_YMM12F2 = 594, 3741 | CV_AMD64_YMM12F3 = 595, 3742 | CV_AMD64_YMM12F4 = 596, 3743 | CV_AMD64_YMM12F5 = 597, 3744 | CV_AMD64_YMM12F6 = 598, 3745 | CV_AMD64_YMM12F7 = 599, 3746 | CV_AMD64_YMM13F0 = 600, 3747 | CV_AMD64_YMM13F1 = 601, 3748 | CV_AMD64_YMM13F2 = 602, 3749 | CV_AMD64_YMM13F3 = 603, 3750 | CV_AMD64_YMM13F4 = 604, 3751 | CV_AMD64_YMM13F5 = 605, 3752 | CV_AMD64_YMM13F6 = 606, 3753 | CV_AMD64_YMM13F7 = 607, 3754 | CV_AMD64_YMM14F0 = 608, 3755 | CV_AMD64_YMM14F1 = 609, 3756 | CV_AMD64_YMM14F2 = 610, 3757 | CV_AMD64_YMM14F3 = 611, 3758 | CV_AMD64_YMM14F4 = 612, 3759 | CV_AMD64_YMM14F5 = 613, 3760 | CV_AMD64_YMM14F6 = 614, 3761 | CV_AMD64_YMM14F7 = 615, 3762 | CV_AMD64_YMM15F0 = 616, 3763 | CV_AMD64_YMM15F1 = 617, 3764 | CV_AMD64_YMM15F2 = 618, 3765 | CV_AMD64_YMM15F3 = 619, 3766 | CV_AMD64_YMM15F4 = 620, 3767 | CV_AMD64_YMM15F5 = 621, 3768 | CV_AMD64_YMM15F6 = 622, 3769 | CV_AMD64_YMM15F7 = 623, 3770 | 3771 | CV_AMD64_YMM0D0 = 624, // AVX floating-point double precise registers 3772 | CV_AMD64_YMM0D1 = 625, 3773 | CV_AMD64_YMM0D2 = 626, 3774 | CV_AMD64_YMM0D3 = 627, 3775 | CV_AMD64_YMM1D0 = 628, 3776 | CV_AMD64_YMM1D1 = 629, 3777 | CV_AMD64_YMM1D2 = 630, 3778 | CV_AMD64_YMM1D3 = 631, 3779 | CV_AMD64_YMM2D0 = 632, 3780 | CV_AMD64_YMM2D1 = 633, 3781 | CV_AMD64_YMM2D2 = 634, 3782 | CV_AMD64_YMM2D3 = 635, 3783 | CV_AMD64_YMM3D0 = 636, 3784 | CV_AMD64_YMM3D1 = 637, 3785 | CV_AMD64_YMM3D2 = 638, 3786 | CV_AMD64_YMM3D3 = 639, 3787 | CV_AMD64_YMM4D0 = 640, 3788 | CV_AMD64_YMM4D1 = 641, 3789 | CV_AMD64_YMM4D2 = 642, 3790 | CV_AMD64_YMM4D3 = 643, 3791 | CV_AMD64_YMM5D0 = 644, 3792 | CV_AMD64_YMM5D1 = 645, 3793 | CV_AMD64_YMM5D2 = 646, 3794 | CV_AMD64_YMM5D3 = 647, 3795 | CV_AMD64_YMM6D0 = 648, 3796 | CV_AMD64_YMM6D1 = 649, 3797 | CV_AMD64_YMM6D2 = 650, 3798 | CV_AMD64_YMM6D3 = 651, 3799 | CV_AMD64_YMM7D0 = 652, 3800 | CV_AMD64_YMM7D1 = 653, 3801 | CV_AMD64_YMM7D2 = 654, 3802 | CV_AMD64_YMM7D3 = 655, 3803 | CV_AMD64_YMM8D0 = 656, 3804 | CV_AMD64_YMM8D1 = 657, 3805 | CV_AMD64_YMM8D2 = 658, 3806 | CV_AMD64_YMM8D3 = 659, 3807 | CV_AMD64_YMM9D0 = 660, 3808 | CV_AMD64_YMM9D1 = 661, 3809 | CV_AMD64_YMM9D2 = 662, 3810 | CV_AMD64_YMM9D3 = 663, 3811 | CV_AMD64_YMM10D0 = 664, 3812 | CV_AMD64_YMM10D1 = 665, 3813 | CV_AMD64_YMM10D2 = 666, 3814 | CV_AMD64_YMM10D3 = 667, 3815 | CV_AMD64_YMM11D0 = 668, 3816 | CV_AMD64_YMM11D1 = 669, 3817 | CV_AMD64_YMM11D2 = 670, 3818 | CV_AMD64_YMM11D3 = 671, 3819 | CV_AMD64_YMM12D0 = 672, 3820 | CV_AMD64_YMM12D1 = 673, 3821 | CV_AMD64_YMM12D2 = 674, 3822 | CV_AMD64_YMM12D3 = 675, 3823 | CV_AMD64_YMM13D0 = 676, 3824 | CV_AMD64_YMM13D1 = 677, 3825 | CV_AMD64_YMM13D2 = 678, 3826 | CV_AMD64_YMM13D3 = 679, 3827 | CV_AMD64_YMM14D0 = 680, 3828 | CV_AMD64_YMM14D1 = 681, 3829 | CV_AMD64_YMM14D2 = 682, 3830 | CV_AMD64_YMM14D3 = 683, 3831 | CV_AMD64_YMM15D0 = 684, 3832 | CV_AMD64_YMM15D1 = 685, 3833 | CV_AMD64_YMM15D2 = 686, 3834 | CV_AMD64_YMM15D3 = 687, 3835 | 3836 | CV_AMD64_BND0 = 688, // AMD64 MPX bounds registers 3837 | CV_AMD64_BND1 = 689, 3838 | CV_AMD64_BND2 = 690, 3839 | CV_AMD64_BND3 = 691, 3840 | CV_AMD64_BNDCFGU = 692, 3841 | CV_AMD64_BNDSTATUS = 693, 3842 | 3843 | CV_AMD64_XMM16 = 694, // AVX-512 registers 3844 | CV_AMD64_XMM17 = 695, 3845 | CV_AMD64_XMM18 = 696, 3846 | CV_AMD64_XMM19 = 697, 3847 | CV_AMD64_XMM20 = 698, 3848 | CV_AMD64_XMM21 = 699, 3849 | CV_AMD64_XMM22 = 700, 3850 | CV_AMD64_XMM23 = 701, 3851 | CV_AMD64_XMM24 = 702, 3852 | CV_AMD64_XMM25 = 703, 3853 | CV_AMD64_XMM26 = 704, 3854 | CV_AMD64_XMM27 = 705, 3855 | CV_AMD64_XMM28 = 706, 3856 | CV_AMD64_XMM29 = 707, 3857 | CV_AMD64_XMM30 = 708, 3858 | CV_AMD64_XMM31 = 709, 3859 | 3860 | CV_AMD64_YMM16 = 710, 3861 | CV_AMD64_YMM17 = 711, 3862 | CV_AMD64_YMM18 = 712, 3863 | CV_AMD64_YMM19 = 713, 3864 | CV_AMD64_YMM20 = 714, 3865 | CV_AMD64_YMM21 = 715, 3866 | CV_AMD64_YMM22 = 716, 3867 | CV_AMD64_YMM23 = 717, 3868 | CV_AMD64_YMM24 = 718, 3869 | CV_AMD64_YMM25 = 719, 3870 | CV_AMD64_YMM26 = 720, 3871 | CV_AMD64_YMM27 = 721, 3872 | CV_AMD64_YMM28 = 722, 3873 | CV_AMD64_YMM29 = 723, 3874 | CV_AMD64_YMM30 = 724, 3875 | CV_AMD64_YMM31 = 725, 3876 | 3877 | CV_AMD64_ZMM0 = 726, 3878 | CV_AMD64_ZMM1 = 727, 3879 | CV_AMD64_ZMM2 = 728, 3880 | CV_AMD64_ZMM3 = 729, 3881 | CV_AMD64_ZMM4 = 730, 3882 | CV_AMD64_ZMM5 = 731, 3883 | CV_AMD64_ZMM6 = 732, 3884 | CV_AMD64_ZMM7 = 733, 3885 | CV_AMD64_ZMM8 = 734, 3886 | CV_AMD64_ZMM9 = 735, 3887 | CV_AMD64_ZMM10 = 736, 3888 | CV_AMD64_ZMM11 = 737, 3889 | CV_AMD64_ZMM12 = 738, 3890 | CV_AMD64_ZMM13 = 739, 3891 | CV_AMD64_ZMM14 = 740, 3892 | CV_AMD64_ZMM15 = 741, 3893 | CV_AMD64_ZMM16 = 742, 3894 | CV_AMD64_ZMM17 = 743, 3895 | CV_AMD64_ZMM18 = 744, 3896 | CV_AMD64_ZMM19 = 745, 3897 | CV_AMD64_ZMM20 = 746, 3898 | CV_AMD64_ZMM21 = 747, 3899 | CV_AMD64_ZMM22 = 748, 3900 | CV_AMD64_ZMM23 = 749, 3901 | CV_AMD64_ZMM24 = 750, 3902 | CV_AMD64_ZMM25 = 751, 3903 | CV_AMD64_ZMM26 = 752, 3904 | CV_AMD64_ZMM27 = 753, 3905 | CV_AMD64_ZMM28 = 754, 3906 | CV_AMD64_ZMM29 = 755, 3907 | CV_AMD64_ZMM30 = 756, 3908 | CV_AMD64_ZMM31 = 757, 3909 | 3910 | CV_AMD64_K0 = 758, 3911 | CV_AMD64_K1 = 759, 3912 | CV_AMD64_K2 = 760, 3913 | CV_AMD64_K3 = 761, 3914 | CV_AMD64_K4 = 762, 3915 | CV_AMD64_K5 = 763, 3916 | CV_AMD64_K6 = 764, 3917 | CV_AMD64_K7 = 765, 3918 | 3919 | CV_AMD64_ZMM0H = 766, // upper 256 bits of the first 16 AMD64 AVX-512 registers 3920 | CV_AMD64_ZMM1H = 767, 3921 | CV_AMD64_ZMM2H = 768, 3922 | CV_AMD64_ZMM3H = 769, 3923 | CV_AMD64_ZMM4H = 770, 3924 | CV_AMD64_ZMM5H = 771, 3925 | CV_AMD64_ZMM6H = 772, 3926 | CV_AMD64_ZMM7H = 773, 3927 | CV_AMD64_ZMM8H = 774, 3928 | CV_AMD64_ZMM9H = 775, 3929 | CV_AMD64_ZMM10H = 776, 3930 | CV_AMD64_ZMM11H = 777, 3931 | CV_AMD64_ZMM12H = 778, 3932 | CV_AMD64_ZMM13H = 779, 3933 | CV_AMD64_ZMM14H = 780, 3934 | CV_AMD64_ZMM15H = 781, 3935 | 3936 | CV_AMD64_XMM16L = 782, // extended KATMAI registers 3937 | CV_AMD64_XMM17L = 783, 3938 | CV_AMD64_XMM18L = 784, 3939 | CV_AMD64_XMM19L = 785, 3940 | CV_AMD64_XMM20L = 786, 3941 | CV_AMD64_XMM21L = 787, 3942 | CV_AMD64_XMM22L = 788, 3943 | CV_AMD64_XMM23L = 789, 3944 | CV_AMD64_XMM24L = 790, 3945 | CV_AMD64_XMM25L = 791, 3946 | CV_AMD64_XMM26L = 792, 3947 | CV_AMD64_XMM27L = 793, 3948 | CV_AMD64_XMM28L = 794, 3949 | CV_AMD64_XMM29L = 795, 3950 | CV_AMD64_XMM30L = 796, 3951 | CV_AMD64_XMM31L = 797, 3952 | 3953 | CV_AMD64_XMM16_0 = 798, 3954 | CV_AMD64_XMM17_0 = 799, 3955 | CV_AMD64_XMM18_0 = 800, 3956 | CV_AMD64_XMM19_0 = 801, 3957 | CV_AMD64_XMM20_0 = 802, 3958 | CV_AMD64_XMM21_0 = 803, 3959 | CV_AMD64_XMM22_0 = 804, 3960 | CV_AMD64_XMM23_0 = 805, 3961 | CV_AMD64_XMM24_0 = 806, 3962 | CV_AMD64_XMM25_0 = 807, 3963 | CV_AMD64_XMM26_0 = 808, 3964 | CV_AMD64_XMM27_0 = 809, 3965 | CV_AMD64_XMM28_0 = 810, 3966 | CV_AMD64_XMM29_0 = 811, 3967 | CV_AMD64_XMM30_0 = 812, 3968 | CV_AMD64_XMM31_0 = 813, 3969 | 3970 | CV_AMD64_XMM16H = 814, 3971 | CV_AMD64_XMM17H = 815, 3972 | CV_AMD64_XMM18H = 816, 3973 | CV_AMD64_XMM19H = 817, 3974 | CV_AMD64_XMM20H = 818, 3975 | CV_AMD64_XMM21H = 819, 3976 | CV_AMD64_XMM22H = 820, 3977 | CV_AMD64_XMM23H = 821, 3978 | CV_AMD64_XMM24H = 822, 3979 | CV_AMD64_XMM25H = 823, 3980 | CV_AMD64_XMM26H = 824, 3981 | CV_AMD64_XMM27H = 825, 3982 | CV_AMD64_XMM28H = 826, 3983 | CV_AMD64_XMM29H = 827, 3984 | CV_AMD64_XMM30H = 828, 3985 | CV_AMD64_XMM31H = 829, 3986 | 3987 | CV_AMD64_EMM16H = 830, 3988 | CV_AMD64_EMM17H = 831, 3989 | CV_AMD64_EMM18H = 832, 3990 | CV_AMD64_EMM19H = 833, 3991 | CV_AMD64_EMM20H = 834, 3992 | CV_AMD64_EMM21H = 835, 3993 | CV_AMD64_EMM22H = 836, 3994 | CV_AMD64_EMM23H = 837, 3995 | CV_AMD64_EMM24H = 838, 3996 | CV_AMD64_EMM25H = 839, 3997 | CV_AMD64_EMM26H = 840, 3998 | CV_AMD64_EMM27H = 841, 3999 | CV_AMD64_EMM28H = 842, 4000 | CV_AMD64_EMM29H = 843, 4001 | CV_AMD64_EMM30H = 844, 4002 | CV_AMD64_EMM31H = 845, 4003 | 4004 | CV_AMD64_SSP = 846, // CET- Shadow Stack Pointer 4005 | 4006 | CV_AMD64_TMM0 = 847, // AMX tile registers 4007 | CV_AMD64_TMM1 = 848, 4008 | CV_AMD64_TMM2 = 849, 4009 | CV_AMD64_TMM3 = 850, 4010 | CV_AMD64_TMM4 = 851, 4011 | CV_AMD64_TMM5 = 852, 4012 | CV_AMD64_TMM6 = 853, 4013 | CV_AMD64_TMM7 = 854, 4014 | 4015 | // Note: Next set of platform registers need to go into a new enum... 4016 | // this one is above 44K now. 4017 | 4018 | } CV_HREG_e; 4019 | 4020 | typedef enum CV_HLSLREG_e 4021 | { 4022 | CV_HLSLREG_TEMP = 0, 4023 | CV_HLSLREG_INPUT = 1, 4024 | CV_HLSLREG_OUTPUT = 2, 4025 | CV_HLSLREG_INDEXABLE_TEMP = 3, 4026 | CV_HLSLREG_IMMEDIATE32 = 4, 4027 | CV_HLSLREG_IMMEDIATE64 = 5, 4028 | CV_HLSLREG_SAMPLER = 6, 4029 | CV_HLSLREG_RESOURCE = 7, 4030 | CV_HLSLREG_CONSTANT_BUFFER = 8, 4031 | CV_HLSLREG_IMMEDIATE_CONSTANT_BUFFER = 9, 4032 | CV_HLSLREG_LABEL = 10, 4033 | CV_HLSLREG_INPUT_PRIMITIVEID = 11, 4034 | CV_HLSLREG_OUTPUT_DEPTH = 12, 4035 | CV_HLSLREG_NULL = 13, 4036 | CV_HLSLREG_RASTERIZER = 14, 4037 | CV_HLSLREG_OUTPUT_COVERAGE_MASK = 15, 4038 | CV_HLSLREG_STREAM = 16, 4039 | CV_HLSLREG_FUNCTION_BODY = 17, 4040 | CV_HLSLREG_FUNCTION_TABLE = 18, 4041 | CV_HLSLREG_INTERFACE = 19, 4042 | CV_HLSLREG_FUNCTION_INPUT = 20, 4043 | CV_HLSLREG_FUNCTION_OUTPUT = 21, 4044 | CV_HLSLREG_OUTPUT_CONTROL_POINT_ID = 22, 4045 | CV_HLSLREG_INPUT_FORK_INSTANCE_ID = 23, 4046 | CV_HLSLREG_INPUT_JOIN_INSTANCE_ID = 24, 4047 | CV_HLSLREG_INPUT_CONTROL_POINT = 25, 4048 | CV_HLSLREG_OUTPUT_CONTROL_POINT = 26, 4049 | CV_HLSLREG_INPUT_PATCH_CONSTANT = 27, 4050 | CV_HLSLREG_INPUT_DOMAIN_POINT = 28, 4051 | CV_HLSLREG_THIS_POINTER = 29, 4052 | CV_HLSLREG_UNORDERED_ACCESS_VIEW = 30, 4053 | CV_HLSLREG_THREAD_GROUP_SHARED_MEMORY = 31, 4054 | CV_HLSLREG_INPUT_THREAD_ID = 32, 4055 | CV_HLSLREG_INPUT_THREAD_GROUP_ID = 33, 4056 | CV_HLSLREG_INPUT_THREAD_ID_IN_GROUP = 34, 4057 | CV_HLSLREG_INPUT_COVERAGE_MASK = 35, 4058 | CV_HLSLREG_INPUT_THREAD_ID_IN_GROUP_FLATTENED = 36, 4059 | CV_HLSLREG_INPUT_GS_INSTANCE_ID = 37, 4060 | CV_HLSLREG_OUTPUT_DEPTH_GREATER_EQUAL = 38, 4061 | CV_HLSLREG_OUTPUT_DEPTH_LESS_EQUAL = 39, 4062 | CV_HLSLREG_CYCLE_COUNTER = 40, 4063 | } CV_HLSLREG_e; 4064 | 4065 | enum StackFrameTypeEnum 4066 | { 4067 | FrameTypeFPO, // Frame pointer omitted, FPO info available 4068 | FrameTypeTrap, // Kernel Trap frame 4069 | FrameTypeTSS, // Kernel Trap frame 4070 | FrameTypeStandard, // Standard EBP stackframe 4071 | FrameTypeFrameData, // Frame pointer omitted, FrameData info available 4072 | 4073 | FrameTypeUnknown = -1, // Frame which does not have any debug info 4074 | }; 4075 | 4076 | enum MemoryTypeEnum 4077 | { 4078 | MemTypeCode, // Read only code memory 4079 | MemTypeData, // Read only data/stack memory 4080 | MemTypeStack, // Read only stack memory 4081 | MemTypeCodeOnHeap, // Read only memory for code generated on heap by runtime 4082 | 4083 | MemTypeAny = -1, 4084 | }; 4085 | 4086 | typedef enum CV_HLSLMemorySpace_e 4087 | { 4088 | // HLSL specific memory spaces 4089 | 4090 | CV_HLSL_MEMSPACE_DATA = 0x00, 4091 | CV_HLSL_MEMSPACE_SAMPLER = 0x01, 4092 | CV_HLSL_MEMSPACE_RESOURCE = 0x02, 4093 | CV_HLSL_MEMSPACE_RWRESOURCE = 0x03, 4094 | 4095 | CV_HLSL_MEMSPACE_MAX = 0x0F, 4096 | } CV_HLSLMemorySpace_e; 4097 | 4098 | enum 4099 | { 4100 | NAMEHASH_BUILD_START, 4101 | NAMEHASH_BUILD_PAUSE, 4102 | NAMEHASH_BUILD_RESUME, 4103 | NAMEHASH_BUILD_COMPLETE, 4104 | NAMEHASH_BUILD_ERROR, 4105 | NAMEHASH_BUILD_OOM = NAMEHASH_BUILD_ERROR, 4106 | NAMEHASH_BUILD_FAIL_TO_OPEN_MOD, 4107 | }; 4108 | 4109 | typedef enum CV_CoroutineKind_e 4110 | { 4111 | CV_COROUTINEKIND_NONE, // Not a coroutine 4112 | CV_COROUTINEKIND_PRIMARY, // The original coroutine function 4113 | CV_COROUTINEKIND_INIT, // Initialization function, sets up the coroutine frame 4114 | CV_COROUTINEKIND_RESUME, // Resume function, contains the coroutine body code 4115 | CV_COROUTINEKIND_DESTROY // Destroy function, tears down the coroutine frame 4116 | } CV_CoroutineKind_e; 4117 | 4118 | typedef enum CV_AssociationKind_e 4119 | { 4120 | CV_ASSOCIATIONKIND_NONE, // No associated symbol 4121 | CV_ASSOCIATIONKIND_COROUTINE // Associated symbol is the primary coroutine function 4122 | } CV_AssociationKind_e; 4123 | 4124 | #endif 4125 | -------------------------------------------------------------------------------- /include/diacreate.h: -------------------------------------------------------------------------------- 1 | // diacreate.h - creation helper functions for DIA initialization 2 | //----------------------------------------------------------------- 3 | // 4 | // Copyright Microsoft Corporation. All Rights Reserved. 5 | // 6 | //--------------------------------------------------------------- 7 | #ifndef _DIACREATE_H_ 8 | #define _DIACREATE_H_ 9 | 10 | // 11 | // Create a dia data source object from the dia dll (by dll name - does not access the registry). 12 | // 13 | 14 | HRESULT STDMETHODCALLTYPE NoRegCoCreate( const __wchar_t *dllName, 15 | REFCLSID rclsid, 16 | REFIID riid, 17 | void **ppv); 18 | 19 | #ifndef _NATIVE_WCHAR_T_DEFINED 20 | #ifdef __cplusplus 21 | 22 | HRESULT STDMETHODCALLTYPE NoRegCoCreate( const wchar_t *dllName, 23 | REFCLSID rclsid, 24 | REFIID riid, 25 | void **ppv) 26 | { 27 | return NoRegCoCreate( (const __wchar_t *)dllName, rclsid, riid, ppv ); 28 | } 29 | 30 | #endif 31 | #endif 32 | 33 | 34 | 35 | // 36 | // Create a dia data source object from the dia dll (looks up the class id in the registry). 37 | // 38 | HRESULT STDMETHODCALLTYPE NoOleCoCreate( REFCLSID rclsid, 39 | REFIID riid, 40 | void **ppv); 41 | 42 | #endif 43 | -------------------------------------------------------------------------------- /lib/x32/diaguids.lib: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/RudjiGames/DIA/93cf2af4ae986ba5ccf0fd23543f154e536b19be/lib/x32/diaguids.lib -------------------------------------------------------------------------------- /lib/x64/diaguids.lib: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/RudjiGames/DIA/93cf2af4ae986ba5ccf0fd23543f154e536b19be/lib/x64/diaguids.lib --------------------------------------------------------------------------------