├── .gitattributes
├── .gitignore
├── Image.cpp
├── Image.h
├── Papers
├── README.md
├── Taint-Analyse.sln
├── Taint-Analyse.vcproj
├── Taint-Analyse.vcxproj
├── Taint-Analyse.vcxproj.filters
├── TaintAnalyse.cpp
├── capstone-3.0.4-win32.zip
├── capstone-3.0.4-win32
├── CREDITS.TXT
├── ChangeLog
├── LICENSE.TXT
├── LICENSE_LLVM.TXT
├── README
├── RELEASE_NOTES
├── capstone.dll
├── capstone.lib
├── include
│ ├── arm.h
│ ├── arm64.h
│ ├── capstone.h
│ ├── mips.h
│ ├── platform.h
│ ├── ppc.h
│ ├── sparc.h
│ ├── systemz.h
│ ├── x86.h
│ └── xcore.h
└── test.exe
├── capstone.dll
├── cccapstone-master
├── .gitmodules
├── README.md
└── cppbindings
│ ├── ArmDisasm.hh
│ ├── CsCapstoneHelper.hh
│ ├── CsIns.hpp
│ ├── Disasm.hpp
│ ├── MipsDisasm.hh
│ ├── PPCDisasm.hh
│ ├── SparcDisasm.hh
│ ├── SystemZDisasm.hh
│ ├── X86Disasm.hh
│ └── XCoreDisasm.hh
├── common.cpp
├── common.h
├── disasmble.cpp
├── disasmble.h
├── include
├── z3++.h
├── z3.h
├── z3_algebraic.h
├── z3_api.h
├── z3_ast_containers.h
├── z3_fixedpoint.h
├── z3_fpa.h
├── z3_interp.h
├── z3_macros.h
├── z3_optimization.h
├── z3_polynomial.h
├── z3_rcf.h
└── z3_v1.h
├── klist.cpp
├── klist.h
└── makefile
/.gitattributes:
--------------------------------------------------------------------------------
1 | ###############################################################################
2 | # Set default behavior to automatically normalize line endings.
3 | ###############################################################################
4 | * text=auto
5 |
6 | ###############################################################################
7 | # Set default behavior for command prompt diff.
8 | #
9 | # This is need for earlier builds of msysgit that does not have it on by
10 | # default for csharp files.
11 | # Note: This is only used by command line
12 | ###############################################################################
13 | #*.cs diff=csharp
14 |
15 | ###############################################################################
16 | # Set the merge driver for project and solution files
17 | #
18 | # Merging from the command prompt will add diff markers to the files if there
19 | # are conflicts (Merging from VS is not affected by the settings below, in VS
20 | # the diff markers are never inserted). Diff markers may cause the following
21 | # file extensions to fail to load in VS. An alternative would be to treat
22 | # these files as binary and thus will always conflict and require user
23 | # intervention with every merge. To do so, just uncomment the entries below
24 | ###############################################################################
25 | #*.sln merge=binary
26 | #*.csproj merge=binary
27 | #*.vbproj merge=binary
28 | #*.vcxproj merge=binary
29 | #*.vcproj merge=binary
30 | #*.dbproj merge=binary
31 | #*.fsproj merge=binary
32 | #*.lsproj merge=binary
33 | #*.wixproj merge=binary
34 | #*.modelproj merge=binary
35 | #*.sqlproj merge=binary
36 | #*.wwaproj merge=binary
37 |
38 | ###############################################################################
39 | # behavior for image files
40 | #
41 | # image files are treated as binary by default.
42 | ###############################################################################
43 | #*.jpg binary
44 | #*.png binary
45 | #*.gif binary
46 |
47 | ###############################################################################
48 | # diff behavior for common document formats
49 | #
50 | # Convert binary document formats to text before diffing them. This feature
51 | # is only available from the command line. Turn it on by uncommenting the
52 | # entries below.
53 | ###############################################################################
54 | #*.doc diff=astextplain
55 | #*.DOC diff=astextplain
56 | #*.docx diff=astextplain
57 | #*.DOCX diff=astextplain
58 | #*.dot diff=astextplain
59 | #*.DOT diff=astextplain
60 | #*.pdf diff=astextplain
61 | #*.PDF diff=astextplain
62 | #*.rtf diff=astextplain
63 | #*.RTF diff=astextplain
64 |
--------------------------------------------------------------------------------
/.gitignore:
--------------------------------------------------------------------------------
1 | ## Ignore Visual Studio temporary files, build results, and
2 | ## files generated by popular Visual Studio add-ons.
3 |
4 | # User-specific files
5 | *.suo
6 | *.user
7 | *.userosscache
8 | *.sln.docstates
9 |
10 | # User-specific files (MonoDevelop/Xamarin Studio)
11 | *.userprefs
12 |
13 | # Build results
14 | [Dd]ebug/
15 | [Dd]ebugPublic/
16 | [Rr]elease/
17 | [Rr]eleases/
18 | [Xx]64/
19 | [Xx]86/
20 | [Bb]uild/
21 | bld/
22 | [Bb]in/
23 | [Oo]bj/
24 |
25 | # Visual Studio 2015 cache/options directory
26 | .vs/
27 | # Uncomment if you have tasks that create the project's static files in wwwroot
28 | #wwwroot/
29 |
30 | # MSTest test Results
31 | [Tt]est[Rr]esult*/
32 | [Bb]uild[Ll]og.*
33 |
34 | # NUNIT
35 | *.VisualState.xml
36 | TestResult.xml
37 |
38 | # Build Results of an ATL Project
39 | [Dd]ebugPS/
40 | [Rr]eleasePS/
41 | dlldata.c
42 |
43 | # DNX
44 | project.lock.json
45 | artifacts/
46 |
47 | *_i.c
48 | *_p.c
49 | *_i.h
50 | *.ilk
51 | *.meta
52 | *.obj
53 | *.pch
54 | *.pdb
55 | *.pgc
56 | *.pgd
57 | *.rsp
58 | *.sbr
59 | *.tlb
60 | *.tli
61 | *.tlh
62 | *.tmp
63 | *.tmp_proj
64 | *.log
65 | *.vspscc
66 | *.vssscc
67 | .builds
68 | *.pidb
69 | *.svclog
70 | *.scc
71 |
72 | # Chutzpah Test files
73 | _Chutzpah*
74 |
75 | # Visual C++ cache files
76 | ipch/
77 | *.aps
78 | *.ncb
79 | *.opendb
80 | *.opensdf
81 | *.sdf
82 | *.cachefile
83 | *.VC.db
84 |
85 | # Visual Studio profiler
86 | *.psess
87 | *.vsp
88 | *.vspx
89 | *.sap
90 |
91 | # TFS 2012 Local Workspace
92 | $tf/
93 |
94 | # Guidance Automation Toolkit
95 | *.gpState
96 |
97 | # ReSharper is a .NET coding add-in
98 | _ReSharper*/
99 | *.[Rr]e[Ss]harper
100 | *.DotSettings.user
101 |
102 | # JustCode is a .NET coding add-in
103 | .JustCode
104 |
105 | # TeamCity is a build add-in
106 | _TeamCity*
107 |
108 | # DotCover is a Code Coverage Tool
109 | *.dotCover
110 |
111 | # NCrunch
112 | _NCrunch_*
113 | .*crunch*.local.xml
114 | nCrunchTemp_*
115 |
116 | # MightyMoose
117 | *.mm.*
118 | AutoTest.Net/
119 |
120 | # Web workbench (sass)
121 | .sass-cache/
122 |
123 | # Installshield output folder
124 | [Ee]xpress/
125 |
126 | # DocProject is a documentation generator add-in
127 | DocProject/buildhelp/
128 | DocProject/Help/*.HxT
129 | DocProject/Help/*.HxC
130 | DocProject/Help/*.hhc
131 | DocProject/Help/*.hhk
132 | DocProject/Help/*.hhp
133 | DocProject/Help/Html2
134 | DocProject/Help/html
135 |
136 | # Click-Once directory
137 | publish/
138 |
139 | # Publish Web Output
140 | *.[Pp]ublish.xml
141 | *.azurePubxml
142 |
143 | # TODO: Un-comment the next line if you do not want to checkin
144 | # your web deploy settings because they may include unencrypted
145 | # passwords
146 | #*.pubxml
147 | *.publishproj
148 |
149 | # NuGet Packages
150 | *.nupkg
151 | # The packages folder can be ignored because of Package Restore
152 | **/packages/*
153 | # except build/, which is used as an MSBuild target.
154 | !**/packages/build/
155 | # Uncomment if necessary however generally it will be regenerated when needed
156 | #!**/packages/repositories.config
157 | # NuGet v3's project.json files produces more ignoreable files
158 | *.nuget.props
159 | *.nuget.targets
160 |
161 | # Microsoft Azure Build Output
162 | csx/
163 | *.build.csdef
164 |
165 | # Microsoft Azure Emulator
166 | ecf/
167 | rcf/
168 |
169 | # Windows Store app package directory
170 | AppPackages/
171 | BundleArtifacts/
172 |
173 | # Visual Studio cache files
174 | # files ending in .cache can be ignored
175 | *.[Cc]ache
176 | # but keep track of directories ending in .cache
177 | !*.[Cc]ache/
178 |
179 | # Others
180 | ClientBin/
181 | [Ss]tyle[Cc]op.*
182 | ~$*
183 | *~
184 | *.dbmdl
185 | *.dbproj.schemaview
186 | *.pfx
187 | *.publishsettings
188 | node_modules/
189 | orleans.codegen.cs
190 |
191 | # RIA/Silverlight projects
192 | Generated_Code/
193 |
194 | # Backup & report files from converting an old project file
195 | # to a newer Visual Studio version. Backup files are not needed,
196 | # because we have git ;-)
197 | _UpgradeReport_Files/
198 | Backup*/
199 | UpgradeLog*.XML
200 | UpgradeLog*.htm
201 |
202 | # SQL Server files
203 | *.mdf
204 | *.ldf
205 |
206 | # Business Intelligence projects
207 | *.rdl.data
208 | *.bim.layout
209 | *.bim_*.settings
210 |
211 | # Microsoft Fakes
212 | FakesAssemblies/
213 |
214 | # GhostDoc plugin setting file
215 | *.GhostDoc.xml
216 |
217 | # Node.js Tools for Visual Studio
218 | .ntvs_analysis.dat
219 |
220 | # Visual Studio 6 build log
221 | *.plg
222 |
223 | # Visual Studio 6 workspace options file
224 | *.opt
225 |
226 | # Visual Studio LightSwitch build output
227 | **/*.HTMLClient/GeneratedArtifacts
228 | **/*.DesktopClient/GeneratedArtifacts
229 | **/*.DesktopClient/ModelManifest.xml
230 | **/*.Server/GeneratedArtifacts
231 | **/*.Server/ModelManifest.xml
232 | _Pvt_Extensions
233 |
234 | # LightSwitch generated files
235 | GeneratedArtifacts/
236 | ModelManifest.xml
237 |
238 | # Paket dependency manager
239 | .paket/paket.exe
240 |
241 | # FAKE - F# Make
242 | .fake/
243 |
--------------------------------------------------------------------------------
/Image.cpp:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/SCUBSRGroup/Taint-Analyse/2f14e5035aa1d03d0a63e1cd2386f7930d8728cf/Image.cpp
--------------------------------------------------------------------------------
/Image.h:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/SCUBSRGroup/Taint-Analyse/2f14e5035aa1d03d0a63e1cd2386f7930d8728cf/Image.h
--------------------------------------------------------------------------------
/Papers:
--------------------------------------------------------------------------------
1 | some papers about Taint-Analyse!
2 |
--------------------------------------------------------------------------------
/README.md:
--------------------------------------------------------------------------------
1 | 基于pin的windows平台下的细粒度污点分析工具。
2 |
--------------------------------------------------------------------------------
/Taint-Analyse.sln:
--------------------------------------------------------------------------------
1 |
2 | Microsoft Visual Studio Solution File, Format Version 12.00
3 | # Visual Studio 14
4 | VisualStudioVersion = 14.0.25420.1
5 | MinimumVisualStudioVersion = 10.0.40219.1
6 | Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "MyPinTool", "Taint-Analyse.vcxproj", "{639EF517-FCFC-408E-9500-71F0DC0458DB}"
7 | EndProject
8 | Global
9 | GlobalSection(SolutionConfigurationPlatforms) = preSolution
10 | Debug|Win32 = Debug|Win32
11 | Debug|x64 = Debug|x64
12 | Release|Win32 = Release|Win32
13 | Release|x64 = Release|x64
14 | EndGlobalSection
15 | GlobalSection(ProjectConfigurationPlatforms) = postSolution
16 | {639EF517-FCFC-408E-9500-71F0DC0458DB}.Debug|Win32.ActiveCfg = Debug|Win32
17 | {639EF517-FCFC-408E-9500-71F0DC0458DB}.Debug|Win32.Build.0 = Debug|Win32
18 | {639EF517-FCFC-408E-9500-71F0DC0458DB}.Debug|x64.ActiveCfg = Debug|x64
19 | {639EF517-FCFC-408E-9500-71F0DC0458DB}.Debug|x64.Build.0 = Debug|x64
20 | {639EF517-FCFC-408E-9500-71F0DC0458DB}.Release|Win32.ActiveCfg = Release|Win32
21 | {639EF517-FCFC-408E-9500-71F0DC0458DB}.Release|Win32.Build.0 = Release|Win32
22 | {639EF517-FCFC-408E-9500-71F0DC0458DB}.Release|x64.ActiveCfg = Release|x64
23 | {639EF517-FCFC-408E-9500-71F0DC0458DB}.Release|x64.Build.0 = Release|x64
24 | EndGlobalSection
25 | GlobalSection(SolutionProperties) = preSolution
26 | HideSolutionNode = FALSE
27 | EndGlobalSection
28 | EndGlobal
29 |
--------------------------------------------------------------------------------
/Taint-Analyse.vcproj:
--------------------------------------------------------------------------------
1 |
2 |
10 |
11 |
14 |
17 |
18 |
19 |
20 |
21 |
28 |
31 |
34 |
37 |
40 |
43 |
64 |
67 |
70 |
73 |
91 |
94 |
97 |
100 |
103 |
106 |
109 |
112 |
115 |
116 |
123 |
126 |
129 |
132 |
135 |
139 |
159 |
162 |
165 |
168 |
186 |
189 |
192 |
195 |
198 |
201 |
204 |
207 |
210 |
211 |
219 |
222 |
225 |
228 |
231 |
234 |
256 |
259 |
262 |
265 |
284 |
287 |
290 |
293 |
296 |
299 |
302 |
305 |
308 |
309 |
317 |
320 |
323 |
326 |
329 |
333 |
354 |
357 |
360 |
363 |
382 |
385 |
388 |
391 |
394 |
397 |
400 |
403 |
406 |
407 |
408 |
409 |
410 |
411 |
416 |
419 |
420 |
421 |
426 |
427 |
431 |
434 |
435 |
436 |
437 |
438 |
439 |
440 |
--------------------------------------------------------------------------------
/Taint-Analyse.vcxproj:
--------------------------------------------------------------------------------
1 |
2 |
3 |
4 |
5 | Debug
6 | Win32
7 |
8 |
9 | Debug
10 | x64
11 |
12 |
13 | Release
14 | Win32
15 |
16 |
17 | Release
18 | x64
19 |
20 |
21 |
22 | Taint-Analyse
23 | {639EF517-FCFC-408E-9500-71F0DC0458DB}
24 | MyPinTool
25 | Win32Proj
26 | 8.1
27 |
28 |
29 |
30 | DynamicLibrary
31 | v140
32 | MultiByte
33 | true
34 |
35 |
36 | DynamicLibrary
37 | v100
38 | MultiByte
39 |
40 |
41 | DynamicLibrary
42 | v140
43 | MultiByte
44 | true
45 |
46 |
47 | DynamicLibrary
48 | v140
49 | MultiByte
50 |
51 |
52 |
53 |
54 |
55 |
56 |
57 |
58 |
59 |
60 |
61 |
62 |
63 |
64 |
65 |
66 |
67 |
68 | <_ProjectFileVersion>14.0.25431.1
69 |
70 |
71 | $(ProjectDir)$(Configuration)\
72 | $(Configuration)\
73 | false
74 | false
75 | F:\pin-2.10-45467-msvc10-ia32_intel64-windows\source\tools\TaintAnalyse\include;$(IncludePath)
76 | F:\pin-2.10-45467-msvc10-ia32_intel64-windows\source\tools\TaintAnalyse\bin;$(LibraryPath)
77 |
78 |
79 | $(ProjectDir)$(Platform)\$(Configuration)\
80 | $(Platform)\$(Configuration)\
81 | false
82 | false
83 |
84 |
85 | $(ProjectDir)$(Configuration)\
86 | $(Configuration)\
87 | false
88 | false
89 |
90 |
91 | $(ProjectDir)$(Platform)\$(Configuration)\
92 | $(Platform)\$(Configuration)\
93 | false
94 | false
95 |
96 |
97 |
98 | /EHs- /EHa- %(AdditionalOptions)
99 | Disabled
100 | ..\..\include;..\..\include\gen;..\InstLib;..\..\..\extras\xed2-ia32\include;..\..\..\extras\components\include;%(AdditionalIncludeDirectories)
101 | TARGET_IA32;HOST_IA32;TARGET_WINDOWS;BIGARRAY_MULTIPLIER=1;USING_XED;_CRT_SECURE_NO_DEPRECATE;_SECURE_SCL=0;WIN32
102 | false
103 |
104 | Default
105 | MultiThreaded
106 | false
107 | true
108 | NotSet
109 | false
110 |
111 | Level3
112 | ProgramDatabase
113 | 4530;%(DisableSpecificWarnings)
114 |
115 |
116 | /export:main /SAFESEH:NO %(AdditionalOptions)
117 | pin.lib;libxed.lib;libcpmt.lib;libcmt.lib;pinvm.lib;kernel32.lib;ntdll-32.lib;libz3.lib
118 | ..\..\..\ia32\lib;..\..\..\ia32\lib-ext;..\..\..\extras\xed2-ia32\lib;%(AdditionalLibraryDirectories)
119 | true
120 | true
121 | NotSet
122 | false
123 | Ptrace_DllMainCRTStartup%4012
124 | 0x55000000
125 | MachineX86
126 | true
127 |
128 |
129 |
130 |
131 | X64
132 |
133 |
134 | /EHs- /EHa- %(AdditionalOptions)
135 | Disabled
136 | ..\..\include;..\..\include\gen;..\InstLib;..\..\..\extras\xed2-intel64\include;..\..\..\extras\components\include;%(AdditionalIncludeDirectories)
137 | TARGET_IA32E;HOST_IA32E;TARGET_WINDOWS;BIGARRAY_MULTIPLIER=1;USING_XED;_CRT_SECURE_NO_DEPRECATE;_SECURE_SCL=0;WIN32
138 | false
139 |
140 | Default
141 | MultiThreaded
142 | false
143 | true
144 | false
145 |
146 | Level3
147 | ProgramDatabase
148 | 4530;%(DisableSpecificWarnings)
149 |
150 |
151 | /export:main %(AdditionalOptions)
152 | pin.lib;libxed.lib;libcpmt.lib;libcmt.lib;pinvm.lib;kernel32.lib;ntdll-64.lib
153 | ..\..\..\intel64\lib;..\..\..\intel64\lib-ext;..\..\..\extras\xed2-intel64\lib;%(AdditionalLibraryDirectories)
154 | true
155 | true
156 | NotSet
157 | false
158 | Ptrace_DllMainCRTStartup
159 | 0xC5000000
160 | MachineX64
161 | true
162 |
163 |
164 |
165 |
166 | /EHs- /EHa- %(AdditionalOptions)
167 | true
168 | false
169 | ..\..\include;..\..\include\gen;..\InstLib;..\..\..\extras\xed2-ia32\include;..\..\..\extras\components\include;%(AdditionalIncludeDirectories)
170 | TARGET_IA32;HOST_IA32;TARGET_WINDOWS;BIGARRAY_MULTIPLIER=1;USING_XED;_CRT_SECURE_NO_DEPRECATE;_SECURE_SCL=0;WIN32
171 | false
172 |
173 | Default
174 | MultiThreaded
175 | false
176 | true
177 | NotSet
178 | false
179 |
180 | Level3
181 |
182 | 4530;%(DisableSpecificWarnings)
183 |
184 |
185 | /export:main %(AdditionalOptions)
186 | pin.lib;libxed.lib;libcpmt.lib;libcmt.lib;pinvm.lib;kernel32.lib;ntdll-32.lib
187 | ..\..\..\ia32\lib;..\..\..\ia32\lib-ext;..\..\..\extras\xed2-ia32\lib;%(AdditionalLibraryDirectories)
188 | true
189 | true
190 | NotSet
191 | true
192 |
193 |
194 | Ptrace_DllMainCRTStartup%4012
195 | 0x55000000
196 | MachineX86
197 |
198 |
199 |
200 |
201 | X64
202 |
203 |
204 | /EHs- /EHa- %(AdditionalOptions)
205 | true
206 | false
207 | ..\..\include;..\..\include\gen;..\InstLib;..\..\..\extras\xed2-intel64\include;..\..\..\extras\components\include;%(AdditionalIncludeDirectories)
208 | TARGET_IA32E;HOST_IA32E;TARGET_WINDOWS;BIGARRAY_MULTIPLIER=1;USING_XED;_CRT_SECURE_NO_DEPRECATE;_SECURE_SCL=0;WIN32
209 | false
210 |
211 | Default
212 | MultiThreaded
213 | false
214 | true
215 | false
216 |
217 | Level3
218 |
219 | 4530;%(DisableSpecificWarnings)
220 |
221 |
222 | /export:main %(AdditionalOptions)
223 | pin.lib;libxed.lib;libcpmt.lib;libcmt.lib;pinvm.lib;kernel32.lib;ntdll-64.lib
224 | ..\..\..\intel64\lib;..\..\..\intel64\lib-ext;..\..\..\extras\xed2-intel64\lib;%(AdditionalLibraryDirectories)
225 | true
226 | true
227 | NotSet
228 | true
229 |
230 |
231 | Ptrace_DllMainCRTStartup
232 | 0xC5000000
233 | MachineX64
234 |
235 |
236 |
237 |
238 |
239 |
240 |
241 |
242 |
243 |
244 |
245 |
--------------------------------------------------------------------------------
/Taint-Analyse.vcxproj.filters:
--------------------------------------------------------------------------------
1 |
2 |
3 |
4 |
5 | {4FC737F1-C7A5-4376-A066-2A32D752A2FF}
6 | cpp;c;cc;cxx;def;odl;idl;hpj;bat;asm;asmx
7 |
8 |
9 | {93995380-89BD-4b04-88EB-625FBE52EBFB}
10 | h;hpp;hxx;hm;inl;inc;xsd
11 |
12 |
13 | {6c07bc3a-1814-4ae1-8e65-bcdf4ed5366a}
14 | txt;doc;html
15 |
16 |
17 |
18 |
19 | Documents
20 |
21 |
22 |
23 |
24 | Source Files
25 |
26 |
27 |
--------------------------------------------------------------------------------
/TaintAnalyse.cpp:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/SCUBSRGroup/Taint-Analyse/2f14e5035aa1d03d0a63e1cd2386f7930d8728cf/TaintAnalyse.cpp
--------------------------------------------------------------------------------
/capstone-3.0.4-win32.zip:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/SCUBSRGroup/Taint-Analyse/2f14e5035aa1d03d0a63e1cd2386f7930d8728cf/capstone-3.0.4-win32.zip
--------------------------------------------------------------------------------
/capstone-3.0.4-win32/CREDITS.TXT:
--------------------------------------------------------------------------------
1 | This file credits all the contributors of the Capstone engine project.
2 |
3 | Key developers
4 | ==============
5 | 1. Nguyen Anh Quynh
6 | - Core engine
7 | - Bindings: Python, Ruby, OCaml, Java, C#
8 |
9 | 2. Tan Sheng Di
10 | - Bindings: Ruby
11 |
12 | 3. Ben Nagy
13 | - Bindings: Ruby, Go
14 |
15 | 4. Dang Hoang Vu
16 | - Bindings: Java
17 |
18 |
19 | Beta testers (in random order)
20 | ==============================
21 | Pancake
22 | Van Hauser
23 | FX of Phenoelit
24 | The Grugq, The Grugq <-- our hero for submitting the first ever patch!
25 | Isaac Dawson, Veracode Inc
26 | Patroklos Argyroudis, Census Inc. (http://census-labs.com)
27 | Attila Suszter
28 | Le Dinh Long
29 | Nicolas Ruff
30 | Gunther
31 | Alex Ionescu, Winsider Seminars & Solutions Inc.
32 | Snare
33 | Daniel Godas-Lopez
34 | Joshua J. Drake
35 | Edgar Barbosa
36 | Ralf-Philipp Weinmann
37 | Hugo Fortier
38 | Joxean Koret
39 | Bruce Dang
40 | Andrew Dunham
41 |
42 |
43 | Contributors (in no particular order)
44 | =====================================
45 | (Please let us know if you want to have your name here)
46 |
47 | Ole André Vadla Ravnås (author of the 100th Pull-Request in our Github repo, thanks!)
48 | Axel "0vercl0k" Souchet (@0vercl0k) & Alex Ionescu: port to MSVC.
49 | Daniel Pistelli: Cmake support.
50 | Peter Hlavaty: integrate Capstone for Windows kernel drivers.
51 | Guillaume Jeanne: Ocaml binding.
52 | Martin Tofall, Obsidium Software: Optimize X86 performance & size.
53 | David Martínez Moreno & Hilko Bengen: Debian package.
54 | Félix Cloutier: Xcode project.
55 | Benoit Lecocq: OpenBSD package.
56 | Christophe Avoinne (Hlide): Improve memory management for better performance.
57 | Michael Cohen & Nguyen Tan Cong: Python module installer.
58 | Adel Gadllah, Francisco Alonso & Stefan Cornelius: RPM package.
59 | Felix Gröbert (Google): fuzz testing harness.
60 |
--------------------------------------------------------------------------------
/capstone-3.0.4-win32/ChangeLog:
--------------------------------------------------------------------------------
1 | This file details the changelog of Capstone.
2 |
3 | ---------------------------------
4 | Version 3.0.4: July 15th, 2015
5 |
6 |
7 | [ Library ]
8 |
9 | - Improve cross-compile for Android using Android NDK.
10 | - Support cross-compile for AArch64 Android (with Linux GCC).
11 | - Removed osxkernel_inttypes.h that is incompatible with BSD license.
12 | - Make it possible to compile with CC having a space inside (like "ccache gcc").
13 |
14 |
15 | [ X86 ]
16 |
17 | - Fix a null pointer dereference bug on handling code with special prefixes.
18 | - Properly handle AL/AX/EAX operand for OUT instruction in AT&T syntax.
19 | - Print immediate operand in positive form in some algorithm instructions.
20 | - Properly decode some SSE instructions.
21 |
22 |
23 | [ PowerPC ]
24 |
25 | - Fixed a memory corruption bug.
26 | - Fixed a memory corruption bug for the engine built in DIET mode.
27 |
28 |
29 | [ Mips ]
30 |
31 | - Fixed instruction ID of SUBU instruction.
32 | - Fixed a memory corruption bug.
33 |
34 |
35 | [ Arm ]
36 |
37 | - Fixed a memory corruption bug on IT instruction.
38 |
39 |
40 | [ XCore ]
41 |
42 | - Fixed a memory corruption bug when instruction has a memory operand.
43 |
44 |
45 | [ Python ]
46 |
47 | - Support Virtualenv.
48 | - setup.py supports option --user if not in a virtualenv to allow for local usage.
49 | - Properly handle the destruction of Cs object in the case the shared library
50 | was already unloaded.
51 |
52 | ---------------------------------
53 | Version 3.0.3: May 08th, 2015
54 |
55 |
56 | [ Library ]
57 |
58 | - Support to embed into Mac OS X kernel extensions.
59 | - Now it is possible to compile Capstone with older C compilers, such as
60 | GCC 4.8 on Ubuntu 12.04.
61 | - Add "test_iter" to MSVC project.
62 |
63 |
64 | [ X86 ]
65 |
66 | - All shifted instructions SHL, SHR, SAL, SAR, RCL, RCR, ROL & ROR now support
67 | $1 as first operand in *AT&T* syntax (so we have "rcll $1, %edx" instead of
68 | "rcll %edx").
69 | - CMPXCHG16B is a valid instruction with LOCK prefix.
70 | - Fixed a segfault on the input of 0xF3.
71 |
72 |
73 | [ Arm ]
74 |
75 | - BLX instruction modifies PC & LR registers.
76 |
77 |
78 | [ Sparc ]
79 |
80 | - Improved displacement decoding for sparc banching instructions.
81 |
82 |
83 | [ Python binding ]
84 |
85 | - Fix for Cython so it can properly initialize.
86 | - X86Op.avx_zero_mask now has c_bool type, but not c_uint8 type.
87 | - Properly support compile with Cygwin & install binding (setup.py).
88 |
89 | ---------------------------------
90 | Version 3.0.2: March 11th, 2015
91 |
92 |
93 | [ Library ]
94 |
95 | - On *nix, only export symbols that are part of the API (instead of all
96 | the internal symbols).
97 |
98 |
99 | [ X86 ]
100 |
101 | - Do not consider 0xF2 as REPNE prefix if it is a part of instruction encoding.
102 | - Fix implicit registers read/written & instruction groups of some instructions.
103 | - More flexible on the order of prefixes, so better handle some tricky
104 | instructions.
105 | - REPNE prefix can go with STOS & MOVS instructions.
106 | - Fix a compilation bug for X86_REDUCE mode.
107 | - Fix operand size of instructions with operand PTR []
108 |
109 |
110 | [ Arm ]
111 |
112 | - Fix a bug where arm_op_mem.disp is wrongly calculated (in DETAIL mode).
113 | - Fix a bug on handling the If-Then block.
114 |
115 |
116 | [ Mips ]
117 |
118 | - Sanity check for the input size for MIPS64 mode.
119 |
120 |
121 | [ MSVC ]
122 |
123 | - Compile capstone.dll with static runtime MSVCR built in.
124 |
125 |
126 | [ Python binding ]
127 |
128 | - Fix a compiling issue of Cython binding with gcc 4.9.
129 |
130 | ---------------------------------
131 | Version 3.0.1: February 03rd, 2015
132 |
133 | [ X86 ]
134 |
135 | - Properly handle LOCK, REP, REPE & REPNE prefixes.
136 | - Handle undocumented immediates for SSE's (V)CMPPS/PD/SS/SD instructions.
137 | - Print LJUMP/LCALL without * as prefix for Intel syntax.
138 | - Handle REX prefix properly for segment/MMX related instructions (x86_64).
139 | - Instruction with length > 15 is consider invalid.
140 | - Handle some tricky encodings for instructions MOVSXD, FXCH, FCOM, FCOMP,
141 | FSTP, FSTPNCE, NOP.
142 | - Handle some tricky code for some X86_64 instructions with REX prefix.
143 | - Add missing operands in detail mode for PUSH , POP , IN/OUT reg, reg
144 | - MOV32ms & MOV32sm should reference word rather than dword.
145 |
146 |
147 | [ Arm64 ]
148 |
149 | - BL & BLR instructions do not read SP register.
150 | - Print absolute (rather than relative) address for instructions B, BL,
151 | CBNZ, ADR.
152 |
153 |
154 | [ Arm ]
155 |
156 | - Instructions ADC & SBC do not update flags.
157 | - BL & BLX do not read SP, but PC register.
158 | - Alias LDR instruction with operands [sp], 4 to POP.
159 | - Print immediate operand of MVN instruction in positive hexadecimal form.
160 |
161 |
162 | [ PowerPC ]
163 |
164 | - Fix some compilation bugs when DIET mode is enable.
165 | - Populate SLWI/SRWI instruction details with SH operand.
166 |
167 |
168 | [ Python binding ]
169 |
170 | - Fix a Cython bug when CsInsn.bytes returns a shorten array of bytes.
171 | - Fixed a memory leak for Cython disasm functions when we immaturely quit
172 | the enumeration of disassembled instructions.
173 | - Fix a NULL memory access issue when SKIPDATA & Detail modes are enable
174 | at the same time.
175 | - Fix a memory leaking bug when when we stop enumeration over the disassembled
176 | instructions prematurely.
177 | - Export generic operand types & groups (CS_OP_xxx & CS_GRP_xxx).
178 |
179 | ---------------------------------
180 | Version 3.0: November 19th, 2014
181 |
182 | [ API ]
183 |
184 | - New API: cs_disasm_iter & cs_malloc. See docs/README for tutorials.
185 | - Renamed cs_disasm_ex to cs_disasm (cs_disasm_ex is still supported, but
186 | marked obsolete to be removed in future)
187 | - Support SKIPDATA mode, so Capstone can jump over unknown data and keep going
188 | from the next legitimate instruction. See docs/README for tutorials.
189 | - More details provided in cs_detail struct for all architectures.
190 | - API version was bumped to 3.0.
191 |
192 |
193 | [ Bindings ]
194 |
195 | - Python binding supports Python3 (besides Python2).
196 | - Support Ocaml binding.
197 | - Java: add close() method to be used to deinitialize a Capstone object when
198 | no longer use it.
199 |
200 |
201 | [ Architectures ]
202 |
203 | - New architectures: Sparc, SystemZ & XCore.
204 | - Important bugfixes for Arm, Arm64, Mips, PowerPC & X86.
205 | - Support more instructions for Arm, Arm64, Mips, PowerPC & X86.
206 | - Always expose absolute addresses rather than relative addresses (Arm, Arm64,
207 | Mips, PPC, Sparc, X86).
208 | - Use common instruction operand types REG, IMM, MEM & FP across all
209 | architectures (to enable cross-architecture analysis).
210 | - Use common instruction group types across all architectures (to enable
211 | cross-architecture analysis).
212 |
213 |
214 | [ X86 ]
215 |
216 | - X86 engine is mature & handles all the malware tricks (that we are aware of).
217 | - Added a lot of new instructions (such as AVX512, 3DNow, etc).
218 | - Add prefix symbols X86_PREFIX_REP/REPNE/LOCK/CS/DS/SS/FS/GS/ES/OPSIZE/ADDRSIZE.
219 | - Print immediate in positive form & hexadecimal for AND/OR/XOR instructions.
220 | - More friendly disassembly for JMP16i (in the form segment:offset)
221 |
222 |
223 | [ Mips ]
224 |
225 | - Engine added supports for new hardware modes: Mips32R6 (CS_MODE_MIPS32R6) &
226 | MipsGP64 (CS_MODE_MIPSGP64).
227 | - Removed the ABI-only mode CS_MODE_N64.
228 | - New modes CS_MODE_MIPS32 & CS_MODE_MIPS64 (to use instead of CS_MODE_32 &
229 | CS_MODE_64).
230 |
231 |
232 | [ ARM ]
233 |
234 | - Support new mode CS_MODE_V8 for Armv8 A32 encodings.
235 | - Print immediate in positive form & hexadecimal for AND/ORR/EOR/BIC instructions
236 |
237 |
238 | [ ARM64 ]
239 |
240 | - Print immediate in hexadecimal for AND/ORR/EOR/TST instructions.
241 |
242 |
243 | [ PowerPC ]
244 |
245 | - Do not print a dot in front of absolute address.
246 |
247 |
248 | [ Other features ]
249 |
250 | - Support for Microsoft Visual Studio (so enable Windows native compilation).
251 | - Support CMake compilation.
252 | - Cross-compile for Android.
253 | - Build libraries/tests using XCode project
254 | - Much faster, while consuming less memory for all architectures.
255 |
256 | ---------------------------------
257 | Version 2.1.2: April 3rd, 2014
258 |
259 | This is a stable release to fix some bugs deep in the core. There is no update
260 | to any architectures or bindings, so bindings version 2.1 can be used with this
261 | version 2.1.2 just fine.
262 |
263 | [ Core changes]
264 |
265 | - Support cross-compilation for all iDevices (iPhone/iPad/iPod).
266 | - X86: do not print memory offset in negative form.
267 | - Fix a bug in X86 when Capstone cannot handle short instruction.
268 | - Print negative number above -9 without prefix 0x (arm64, mips, arm).
269 | - Correct the SONAME setup for library versioning (Linux, *BSD, Solaris).
270 | - Set library versioning for dylib of OSX.
271 |
272 | ---------------------------------
273 | Version 2.1.1: March 13th, 2014
274 |
275 | This is a stable release to fix some bugs deep in the core. There is no update
276 | to any architectures or bindings, so bindings version 2.1 can be used with this
277 | version 2.1.1 just fine.
278 |
279 | [ Core changes]
280 |
281 | - Fix a buffer overflow bug in Thumb mode (ARM). Some special input can
282 | trigger this flaw.
283 | - Fix a crash issue when embedding Capstone into OSX kernel. This should
284 | also enable Capstone to be embedded into other systems with limited stack
285 | memory size such as Linux kernel or some firmwares.
286 | - Use a proper SONAME for library versioning (Linux).
287 |
288 | ---------------------------------
289 | Version 2.1: March 5th, 2014
290 |
291 | [ API changes ]
292 |
293 | - API version has been bumped to 2.1.
294 | - Change prototype of cs_close() to be able to invalidate closed handle.
295 | See http://capstone-engine.org/version_2.1_API.html for more information.
296 | - Extend cs_support() to handle more query types, not only about supported
297 | architectures. This change is backward compatible, however, so existent code
298 | do not need to be modified to support this.
299 | - New query type CS_SUPPORT_DIET for cs_support() to ask about diet status of
300 | the engine.
301 | - New error code CS_ERR_DIET to report errors about newly added diet mode.
302 | - New error code CS_ERR_VERSION to report issue of incompatible versions between
303 | bindings & core engine.
304 |
305 |
306 | [ Core changes ]
307 |
308 | - On memory usage, Capstone uses about 40% less memory, while still faster
309 | than version 2.0.
310 | - All architectures are much smaller: binaries size reduce at least 30%.
311 | Especially, X86-only binary reduces from 1.9MB to just 720KB.
312 | - Support "diet" mode, in which engine size is further reduced (by around 40%)
313 | for embedding purpose. The price to pay is that we have to sacrifice some
314 | non-critical data fields. See http://capstone-engine.org/diet.html for more
315 | details.
316 |
317 |
318 | [ Architectures ]
319 |
320 | - Update all 5 architectures to fix bugs.
321 | - PowerPC:
322 | - New instructions: FMR & MSYNC.
323 | - Mips:
324 | - New instruction: DLSA
325 | - X86:
326 | - Properly handle AVX-512 instructions.
327 | - New instructions: PSETPM, SALC, INT1, GETSEC.
328 | - Fix some memory leaking issues in case of prefixed instructions such
329 | as LOCK, REP, REPNE.
330 |
331 |
332 | [ Python binding ]
333 |
334 | - Verify the core version at initialization time. Refuse to run if its version
335 | is different from the core's version.
336 | - New API disasm_lite() added to Cs class. This light API only returns tuples of
337 | (address, size, mnemonic, op_str), rather than list of CsInsn objects. This
338 | improves performance by around 30% in some benchmarks.
339 | - New API version_bind() returns binding's version, which might differ from
340 | the core's API version if the binding is out-of-date.
341 | - New API debug() returns information on Cython support, diet status & archs
342 | compiled in.
343 | - Fixed some memory leaking bugs for Cython binding.
344 | - Fix a bug crashing Cython code when accessing @regs_read/regs_write/groups.
345 | - Support diet mode.
346 |
347 |
348 | [ Java binding ]
349 |
350 | - Fix some memory leaking bugs.
351 | - New API version() returns combined version.
352 | - Support diet mode.
353 | - Better support for detail option.
354 |
355 |
356 | [ Miscellaneous ]
357 |
358 | - make.sh now can uninstall the core engine. This is done with:
359 |
360 | $ sudo ./make.sh uninstall
361 |
362 | ----------------------------------
363 | Version 2.0: January 22nd, 2014
364 |
365 | Release 2.0 deprecates verison 1.0 and brings a lot of crucial changes.
366 |
367 | [ API changes ]
368 |
369 | - API version has been bumped to 2.0 (see cs_version() API)
370 | - New API cs_strerror(errno) returns a string describing error code given
371 | in its only argument.
372 | - cs_version() now returns combined version encoding both major & minor versions.
373 | - New option CS_OPT_MODE allows to change engine’s mode at run-time with
374 | cs_option().
375 | - New option CS_OPT_MEM allows to specify user-defined functions for dynamically
376 | memory management used internally by Capstone. This is useful to embed Capstone
377 | into special environments such as kernel or firware.
378 | - New API cs_support() can be used to check if this lib supports a particular
379 | architecture (this is necessary since we now allow to choose which architectures
380 | to compile in).
381 | - The detail option is OFF by default now. To get detail information, it should be
382 | explicitly turned ON. The details then can be accessed using cs_insn.detail
383 | pointer (to newly added structure cs_detail)
384 |
385 |
386 | [ Core changes ]
387 |
388 | - On memory usage, Capstone uses much less memory, but a lot faster now.
389 | - User now can choose which architectures to be supported by modifying config.mk
390 | before compiling/installing.
391 |
392 |
393 | [ Architectures ]
394 |
395 | - Arm
396 | - Support Big-Endian mode (besides Little-Endian mode).
397 | - Support friendly register, so instead of output sub "r12,r11,0x14",
398 | we have "sub ip,fp,0x14".
399 | - Arm64: support Big-Endian mode (besides Little-Endian mode).
400 | - PowerPC: newly added.
401 | - Mips: support friendly register, so instead of output "srl $2,$1,0x1f",
402 | we have "srl $v0,$at,0x1f".
403 | - X86: bug fixes.
404 |
405 |
406 | [ Python binding ]
407 |
408 | - Python binding is vastly improved in performance: around 3 ~ 4 times faster
409 | than in 1.0.
410 | - Cython support has been added, which can further speed up over the default
411 | pure Python binding (up to 30% in some cases)
412 | - Function cs_disasm_quick() & Cs.disasm() now use generator (rather than a list)
413 | to return succesfully disassembled instructions. This improves the performance
414 | and reduces memory usage.
415 |
416 |
417 | [ Java binding ]
418 |
419 | - Better performance & bug fixes.
420 |
421 |
422 | [ Miscellaneous ]
423 |
424 | - Fixed some installation issues with Gentoo Linux.
425 | - Capstone now can easily compile/install on all *nix, including Linux, OSX,
426 | {Net, Free, Open}BSD & Solaris.
427 |
428 | ----------------------------------
429 | [Version 1.0]: December 18th, 2013
430 |
431 | - Initial public release.
432 |
433 |
--------------------------------------------------------------------------------
/capstone-3.0.4-win32/LICENSE.TXT:
--------------------------------------------------------------------------------
1 | This is the software license for Capstone disassembly framework.
2 | Capstone has been designed & implemented by Nguyen Anh Quynh
3 |
4 | See http://www.capstone-engine.org for further information.
5 |
6 | Copyright (c) 2013, COSEINC.
7 | All rights reserved.
8 |
9 | Redistribution and use in source and binary forms, with or without
10 | modification, are permitted provided that the following conditions are met:
11 |
12 | * Redistributions of source code must retain the above copyright notice,
13 | this list of conditions and the following disclaimer.
14 | * Redistributions in binary form must reproduce the above copyright notice,
15 | this list of conditions and the following disclaimer in the documentation
16 | and/or other materials provided with the distribution.
17 | * Neither the name of the developer(s) nor the names of its
18 | contributors may be used to endorse or promote products derived from this
19 | software without specific prior written permission.
20 |
21 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 | ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
25 | LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 | CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 | SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 | INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 | CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 | ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 | POSSIBILITY OF SUCH DAMAGE.
32 |
--------------------------------------------------------------------------------
/capstone-3.0.4-win32/LICENSE_LLVM.TXT:
--------------------------------------------------------------------------------
1 | ==============================================================================
2 | LLVM Release License
3 | ==============================================================================
4 | University of Illinois/NCSA
5 | Open Source License
6 |
7 | Copyright (c) 2003-2013 University of Illinois at Urbana-Champaign.
8 | All rights reserved.
9 |
10 | Developed by:
11 |
12 | LLVM Team
13 |
14 | University of Illinois at Urbana-Champaign
15 |
16 | http://llvm.org
17 |
18 | Permission is hereby granted, free of charge, to any person obtaining a copy of
19 | this software and associated documentation files (the "Software"), to deal with
20 | the Software without restriction, including without limitation the rights to
21 | use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
22 | of the Software, and to permit persons to whom the Software is furnished to do
23 | so, subject to the following conditions:
24 |
25 | * Redistributions of source code must retain the above copyright notice,
26 | this list of conditions and the following disclaimers.
27 |
28 | * Redistributions in binary form must reproduce the above copyright notice,
29 | this list of conditions and the following disclaimers in the
30 | documentation and/or other materials provided with the distribution.
31 |
32 | * Neither the names of the LLVM Team, University of Illinois at
33 | Urbana-Champaign, nor the names of its contributors may be used to
34 | endorse or promote products derived from this Software without specific
35 | prior written permission.
36 |
37 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
38 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
39 | FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
40 | CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
41 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
42 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH THE
43 | SOFTWARE.
44 |
45 | ==============================================================================
46 | Copyrights and Licenses for Third Party Software Distributed with LLVM:
47 | ==============================================================================
48 | The LLVM software contains code written by third parties. Such software will
49 | have its own individual LICENSE.TXT file in the directory in which it appears.
50 | This file will describe the copyrights, license, and restrictions which apply
51 | to that code.
52 |
53 | The disclaimer of warranty in the University of Illinois Open Source License
54 | applies to all code in the LLVM Distribution, and nothing in any of the
55 | other licenses gives permission to use the names of the LLVM Team or the
56 | University of Illinois to endorse or promote products derived from this
57 | Software.
58 |
59 | The following pieces of software have additional or alternate copyrights,
60 | licenses, and/or restrictions:
61 |
62 | Program Directory
63 | ------- ---------
64 | Autoconf llvm/autoconf
65 | llvm/projects/ModuleMaker/autoconf
66 | llvm/projects/sample/autoconf
67 | Google Test llvm/utils/unittest/googletest
68 | OpenBSD regex llvm/lib/Support/{reg*, COPYRIGHT.regex}
69 | pyyaml tests llvm/test/YAMLParser/{*.data, LICENSE.TXT}
70 | ARM contributions llvm/lib/Target/ARM/LICENSE.TXT
71 | md5 contributions llvm/lib/Support/MD5.cpp llvm/include/llvm/Support/MD5.h
72 |
--------------------------------------------------------------------------------
/capstone-3.0.4-win32/README:
--------------------------------------------------------------------------------
1 | Capstone is a disassembly framework with the target of becoming the ultimate
2 | disasm engine for binary analysis and reversing in the security community.
3 |
4 | Created by Nguyen Anh Quynh, then developed and maintained by a small community,
5 | Capstone offers some unparalleled features:
6 |
7 | - Support multiple hardware architectures: ARM, ARM64 (ARMv8), Mips, PPC, Sparc,
8 | SystemZ, XCore and X86 (including X86_64).
9 |
10 | - Having clean/simple/lightweight/intuitive architecture-neutral API.
11 |
12 | - Provide details on disassembled instruction (called “decomposer” by others).
13 |
14 | - Provide semantics of the disassembled instruction, such as list of implicit
15 | registers read & written.
16 |
17 | - Implemented in pure C language, with lightweight wrappers for C++, C#, Go,
18 | Java, Lua, NodeJS, Ocaml, Python, Ruby, Rust & Vala ready (available in
19 | main code, or provided externally by the community).
20 |
21 | - Native support for all popular platforms: Windows, Mac OSX, iOS, Android,
22 | Linux, *BSD, Solaris, etc.
23 |
24 | - Thread-safe by design.
25 |
26 | - Special support for embedding into firmware or OS kernel.
27 |
28 | - High performance & suitable for malware analysis (capable of handling various
29 | X86 malware tricks).
30 |
31 | - Distributed under the open source BSD license.
32 |
33 | Further information is available at http://www.capstone-engine.org
34 |
35 |
36 | [Compile]
37 |
38 | See COMPILE.TXT file for how to compile and install Capstone.
39 |
40 |
41 | [Documentation]
42 |
43 | See docs/README for how to customize & program your own tools with Capstone.
44 |
45 |
46 | [Hack]
47 |
48 | See HACK.TXT file for the structuture of the source code.
49 |
50 |
51 | [License]
52 |
53 | This project is released under the BSD license. If you redistribute the binary
54 | or source code of Capstone, please attach file LICENSE.TXT with your products.
55 |
--------------------------------------------------------------------------------
/capstone-3.0.4-win32/RELEASE_NOTES:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/SCUBSRGroup/Taint-Analyse/2f14e5035aa1d03d0a63e1cd2386f7930d8728cf/capstone-3.0.4-win32/RELEASE_NOTES
--------------------------------------------------------------------------------
/capstone-3.0.4-win32/capstone.dll:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/SCUBSRGroup/Taint-Analyse/2f14e5035aa1d03d0a63e1cd2386f7930d8728cf/capstone-3.0.4-win32/capstone.dll
--------------------------------------------------------------------------------
/capstone-3.0.4-win32/capstone.lib:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/SCUBSRGroup/Taint-Analyse/2f14e5035aa1d03d0a63e1cd2386f7930d8728cf/capstone-3.0.4-win32/capstone.lib
--------------------------------------------------------------------------------
/capstone-3.0.4-win32/include/mips.h:
--------------------------------------------------------------------------------
1 | #ifndef CAPSTONE_MIPS_H
2 | #define CAPSTONE_MIPS_H
3 |
4 | /* Capstone Disassembly Engine */
5 | /* By Nguyen Anh Quynh , 2013-2014 */
6 |
7 | #ifdef __cplusplus
8 | extern "C" {
9 | #endif
10 |
11 | #include
12 | #include "platform.h"
13 |
14 | // GCC MIPS toolchain has a default macro called "mips" which breaks
15 | // compilation
16 | #undef mips
17 |
18 | #ifdef _MSC_VER
19 | #pragma warning(disable:4201)
20 | #endif
21 |
22 | //> Operand type for instruction's operands
23 | typedef enum mips_op_type {
24 | MIPS_OP_INVALID = 0, // = CS_OP_INVALID (Uninitialized).
25 | MIPS_OP_REG, // = CS_OP_REG (Register operand).
26 | MIPS_OP_IMM, // = CS_OP_IMM (Immediate operand).
27 | MIPS_OP_MEM, // = CS_OP_MEM (Memory operand).
28 | } mips_op_type;
29 |
30 | // Instruction's operand referring to memory
31 | // This is associated with MIPS_OP_MEM operand type above
32 | typedef struct mips_op_mem {
33 | unsigned int base; // base register
34 | int64_t disp; // displacement/offset value
35 | } mips_op_mem;
36 |
37 | // Instruction operand
38 | typedef struct cs_mips_op {
39 | mips_op_type type; // operand type
40 | union {
41 | unsigned int reg; // register value for REG operand
42 | int64_t imm; // immediate value for IMM operand
43 | mips_op_mem mem; // base/index/scale/disp value for MEM operand
44 | };
45 | } cs_mips_op;
46 |
47 | // Instruction structure
48 | typedef struct cs_mips {
49 | // Number of operands of this instruction,
50 | // or 0 when instruction has no operand.
51 | uint8_t op_count;
52 | cs_mips_op operands[8]; // operands for this instruction.
53 | } cs_mips;
54 |
55 | //> MIPS registers
56 | typedef enum mips_reg {
57 | MIPS_REG_INVALID = 0,
58 | //> General purpose registers
59 | MIPS_REG_0,
60 | MIPS_REG_1,
61 | MIPS_REG_2,
62 | MIPS_REG_3,
63 | MIPS_REG_4,
64 | MIPS_REG_5,
65 | MIPS_REG_6,
66 | MIPS_REG_7,
67 | MIPS_REG_8,
68 | MIPS_REG_9,
69 | MIPS_REG_10,
70 | MIPS_REG_11,
71 | MIPS_REG_12,
72 | MIPS_REG_13,
73 | MIPS_REG_14,
74 | MIPS_REG_15,
75 | MIPS_REG_16,
76 | MIPS_REG_17,
77 | MIPS_REG_18,
78 | MIPS_REG_19,
79 | MIPS_REG_20,
80 | MIPS_REG_21,
81 | MIPS_REG_22,
82 | MIPS_REG_23,
83 | MIPS_REG_24,
84 | MIPS_REG_25,
85 | MIPS_REG_26,
86 | MIPS_REG_27,
87 | MIPS_REG_28,
88 | MIPS_REG_29,
89 | MIPS_REG_30,
90 | MIPS_REG_31,
91 |
92 | //> DSP registers
93 | MIPS_REG_DSPCCOND,
94 | MIPS_REG_DSPCARRY,
95 | MIPS_REG_DSPEFI,
96 | MIPS_REG_DSPOUTFLAG,
97 | MIPS_REG_DSPOUTFLAG16_19,
98 | MIPS_REG_DSPOUTFLAG20,
99 | MIPS_REG_DSPOUTFLAG21,
100 | MIPS_REG_DSPOUTFLAG22,
101 | MIPS_REG_DSPOUTFLAG23,
102 | MIPS_REG_DSPPOS,
103 | MIPS_REG_DSPSCOUNT,
104 |
105 | //> ACC registers
106 | MIPS_REG_AC0,
107 | MIPS_REG_AC1,
108 | MIPS_REG_AC2,
109 | MIPS_REG_AC3,
110 |
111 | //> COP registers
112 | MIPS_REG_CC0,
113 | MIPS_REG_CC1,
114 | MIPS_REG_CC2,
115 | MIPS_REG_CC3,
116 | MIPS_REG_CC4,
117 | MIPS_REG_CC5,
118 | MIPS_REG_CC6,
119 | MIPS_REG_CC7,
120 |
121 | //> FPU registers
122 | MIPS_REG_F0,
123 | MIPS_REG_F1,
124 | MIPS_REG_F2,
125 | MIPS_REG_F3,
126 | MIPS_REG_F4,
127 | MIPS_REG_F5,
128 | MIPS_REG_F6,
129 | MIPS_REG_F7,
130 | MIPS_REG_F8,
131 | MIPS_REG_F9,
132 | MIPS_REG_F10,
133 | MIPS_REG_F11,
134 | MIPS_REG_F12,
135 | MIPS_REG_F13,
136 | MIPS_REG_F14,
137 | MIPS_REG_F15,
138 | MIPS_REG_F16,
139 | MIPS_REG_F17,
140 | MIPS_REG_F18,
141 | MIPS_REG_F19,
142 | MIPS_REG_F20,
143 | MIPS_REG_F21,
144 | MIPS_REG_F22,
145 | MIPS_REG_F23,
146 | MIPS_REG_F24,
147 | MIPS_REG_F25,
148 | MIPS_REG_F26,
149 | MIPS_REG_F27,
150 | MIPS_REG_F28,
151 | MIPS_REG_F29,
152 | MIPS_REG_F30,
153 | MIPS_REG_F31,
154 |
155 | MIPS_REG_FCC0,
156 | MIPS_REG_FCC1,
157 | MIPS_REG_FCC2,
158 | MIPS_REG_FCC3,
159 | MIPS_REG_FCC4,
160 | MIPS_REG_FCC5,
161 | MIPS_REG_FCC6,
162 | MIPS_REG_FCC7,
163 |
164 | //> AFPR128
165 | MIPS_REG_W0,
166 | MIPS_REG_W1,
167 | MIPS_REG_W2,
168 | MIPS_REG_W3,
169 | MIPS_REG_W4,
170 | MIPS_REG_W5,
171 | MIPS_REG_W6,
172 | MIPS_REG_W7,
173 | MIPS_REG_W8,
174 | MIPS_REG_W9,
175 | MIPS_REG_W10,
176 | MIPS_REG_W11,
177 | MIPS_REG_W12,
178 | MIPS_REG_W13,
179 | MIPS_REG_W14,
180 | MIPS_REG_W15,
181 | MIPS_REG_W16,
182 | MIPS_REG_W17,
183 | MIPS_REG_W18,
184 | MIPS_REG_W19,
185 | MIPS_REG_W20,
186 | MIPS_REG_W21,
187 | MIPS_REG_W22,
188 | MIPS_REG_W23,
189 | MIPS_REG_W24,
190 | MIPS_REG_W25,
191 | MIPS_REG_W26,
192 | MIPS_REG_W27,
193 | MIPS_REG_W28,
194 | MIPS_REG_W29,
195 | MIPS_REG_W30,
196 | MIPS_REG_W31,
197 |
198 | MIPS_REG_HI,
199 | MIPS_REG_LO,
200 |
201 | MIPS_REG_P0,
202 | MIPS_REG_P1,
203 | MIPS_REG_P2,
204 |
205 | MIPS_REG_MPL0,
206 | MIPS_REG_MPL1,
207 | MIPS_REG_MPL2,
208 |
209 | MIPS_REG_ENDING, // <-- mark the end of the list or registers
210 |
211 | // alias registers
212 | MIPS_REG_ZERO = MIPS_REG_0,
213 | MIPS_REG_AT = MIPS_REG_1,
214 | MIPS_REG_V0 = MIPS_REG_2,
215 | MIPS_REG_V1 = MIPS_REG_3,
216 | MIPS_REG_A0 = MIPS_REG_4,
217 | MIPS_REG_A1 = MIPS_REG_5,
218 | MIPS_REG_A2 = MIPS_REG_6,
219 | MIPS_REG_A3 = MIPS_REG_7,
220 | MIPS_REG_T0 = MIPS_REG_8,
221 | MIPS_REG_T1 = MIPS_REG_9,
222 | MIPS_REG_T2 = MIPS_REG_10,
223 | MIPS_REG_T3 = MIPS_REG_11,
224 | MIPS_REG_T4 = MIPS_REG_12,
225 | MIPS_REG_T5 = MIPS_REG_13,
226 | MIPS_REG_T6 = MIPS_REG_14,
227 | MIPS_REG_T7 = MIPS_REG_15,
228 | MIPS_REG_S0 = MIPS_REG_16,
229 | MIPS_REG_S1 = MIPS_REG_17,
230 | MIPS_REG_S2 = MIPS_REG_18,
231 | MIPS_REG_S3 = MIPS_REG_19,
232 | MIPS_REG_S4 = MIPS_REG_20,
233 | MIPS_REG_S5 = MIPS_REG_21,
234 | MIPS_REG_S6 = MIPS_REG_22,
235 | MIPS_REG_S7 = MIPS_REG_23,
236 | MIPS_REG_T8 = MIPS_REG_24,
237 | MIPS_REG_T9 = MIPS_REG_25,
238 | MIPS_REG_K0 = MIPS_REG_26,
239 | MIPS_REG_K1 = MIPS_REG_27,
240 | MIPS_REG_GP = MIPS_REG_28,
241 | MIPS_REG_SP = MIPS_REG_29,
242 | MIPS_REG_FP = MIPS_REG_30, MIPS_REG_S8 = MIPS_REG_30,
243 | MIPS_REG_RA = MIPS_REG_31,
244 |
245 | MIPS_REG_HI0 = MIPS_REG_AC0,
246 | MIPS_REG_HI1 = MIPS_REG_AC1,
247 | MIPS_REG_HI2 = MIPS_REG_AC2,
248 | MIPS_REG_HI3 = MIPS_REG_AC3,
249 |
250 | MIPS_REG_LO0 = MIPS_REG_HI0,
251 | MIPS_REG_LO1 = MIPS_REG_HI1,
252 | MIPS_REG_LO2 = MIPS_REG_HI2,
253 | MIPS_REG_LO3 = MIPS_REG_HI3,
254 | } mips_reg;
255 |
256 | //> MIPS instruction
257 | typedef enum mips_insn {
258 | MIPS_INS_INVALID = 0,
259 |
260 | MIPS_INS_ABSQ_S,
261 | MIPS_INS_ADD,
262 | MIPS_INS_ADDIUPC,
263 | MIPS_INS_ADDQH,
264 | MIPS_INS_ADDQH_R,
265 | MIPS_INS_ADDQ,
266 | MIPS_INS_ADDQ_S,
267 | MIPS_INS_ADDSC,
268 | MIPS_INS_ADDS_A,
269 | MIPS_INS_ADDS_S,
270 | MIPS_INS_ADDS_U,
271 | MIPS_INS_ADDUH,
272 | MIPS_INS_ADDUH_R,
273 | MIPS_INS_ADDU,
274 | MIPS_INS_ADDU_S,
275 | MIPS_INS_ADDVI,
276 | MIPS_INS_ADDV,
277 | MIPS_INS_ADDWC,
278 | MIPS_INS_ADD_A,
279 | MIPS_INS_ADDI,
280 | MIPS_INS_ADDIU,
281 | MIPS_INS_ALIGN,
282 | MIPS_INS_ALUIPC,
283 | MIPS_INS_AND,
284 | MIPS_INS_ANDI,
285 | MIPS_INS_APPEND,
286 | MIPS_INS_ASUB_S,
287 | MIPS_INS_ASUB_U,
288 | MIPS_INS_AUI,
289 | MIPS_INS_AUIPC,
290 | MIPS_INS_AVER_S,
291 | MIPS_INS_AVER_U,
292 | MIPS_INS_AVE_S,
293 | MIPS_INS_AVE_U,
294 | MIPS_INS_BADDU,
295 | MIPS_INS_BAL,
296 | MIPS_INS_BALC,
297 | MIPS_INS_BALIGN,
298 | MIPS_INS_BC,
299 | MIPS_INS_BC0F,
300 | MIPS_INS_BC0FL,
301 | MIPS_INS_BC0T,
302 | MIPS_INS_BC0TL,
303 | MIPS_INS_BC1EQZ,
304 | MIPS_INS_BC1F,
305 | MIPS_INS_BC1FL,
306 | MIPS_INS_BC1NEZ,
307 | MIPS_INS_BC1T,
308 | MIPS_INS_BC1TL,
309 | MIPS_INS_BC2EQZ,
310 | MIPS_INS_BC2F,
311 | MIPS_INS_BC2FL,
312 | MIPS_INS_BC2NEZ,
313 | MIPS_INS_BC2T,
314 | MIPS_INS_BC2TL,
315 | MIPS_INS_BC3F,
316 | MIPS_INS_BC3FL,
317 | MIPS_INS_BC3T,
318 | MIPS_INS_BC3TL,
319 | MIPS_INS_BCLRI,
320 | MIPS_INS_BCLR,
321 | MIPS_INS_BEQ,
322 | MIPS_INS_BEQC,
323 | MIPS_INS_BEQL,
324 | MIPS_INS_BEQZALC,
325 | MIPS_INS_BEQZC,
326 | MIPS_INS_BGEC,
327 | MIPS_INS_BGEUC,
328 | MIPS_INS_BGEZ,
329 | MIPS_INS_BGEZAL,
330 | MIPS_INS_BGEZALC,
331 | MIPS_INS_BGEZALL,
332 | MIPS_INS_BGEZALS,
333 | MIPS_INS_BGEZC,
334 | MIPS_INS_BGEZL,
335 | MIPS_INS_BGTZ,
336 | MIPS_INS_BGTZALC,
337 | MIPS_INS_BGTZC,
338 | MIPS_INS_BGTZL,
339 | MIPS_INS_BINSLI,
340 | MIPS_INS_BINSL,
341 | MIPS_INS_BINSRI,
342 | MIPS_INS_BINSR,
343 | MIPS_INS_BITREV,
344 | MIPS_INS_BITSWAP,
345 | MIPS_INS_BLEZ,
346 | MIPS_INS_BLEZALC,
347 | MIPS_INS_BLEZC,
348 | MIPS_INS_BLEZL,
349 | MIPS_INS_BLTC,
350 | MIPS_INS_BLTUC,
351 | MIPS_INS_BLTZ,
352 | MIPS_INS_BLTZAL,
353 | MIPS_INS_BLTZALC,
354 | MIPS_INS_BLTZALL,
355 | MIPS_INS_BLTZALS,
356 | MIPS_INS_BLTZC,
357 | MIPS_INS_BLTZL,
358 | MIPS_INS_BMNZI,
359 | MIPS_INS_BMNZ,
360 | MIPS_INS_BMZI,
361 | MIPS_INS_BMZ,
362 | MIPS_INS_BNE,
363 | MIPS_INS_BNEC,
364 | MIPS_INS_BNEGI,
365 | MIPS_INS_BNEG,
366 | MIPS_INS_BNEL,
367 | MIPS_INS_BNEZALC,
368 | MIPS_INS_BNEZC,
369 | MIPS_INS_BNVC,
370 | MIPS_INS_BNZ,
371 | MIPS_INS_BOVC,
372 | MIPS_INS_BPOSGE32,
373 | MIPS_INS_BREAK,
374 | MIPS_INS_BSELI,
375 | MIPS_INS_BSEL,
376 | MIPS_INS_BSETI,
377 | MIPS_INS_BSET,
378 | MIPS_INS_BZ,
379 | MIPS_INS_BEQZ,
380 | MIPS_INS_B,
381 | MIPS_INS_BNEZ,
382 | MIPS_INS_BTEQZ,
383 | MIPS_INS_BTNEZ,
384 | MIPS_INS_CACHE,
385 | MIPS_INS_CEIL,
386 | MIPS_INS_CEQI,
387 | MIPS_INS_CEQ,
388 | MIPS_INS_CFC1,
389 | MIPS_INS_CFCMSA,
390 | MIPS_INS_CINS,
391 | MIPS_INS_CINS32,
392 | MIPS_INS_CLASS,
393 | MIPS_INS_CLEI_S,
394 | MIPS_INS_CLEI_U,
395 | MIPS_INS_CLE_S,
396 | MIPS_INS_CLE_U,
397 | MIPS_INS_CLO,
398 | MIPS_INS_CLTI_S,
399 | MIPS_INS_CLTI_U,
400 | MIPS_INS_CLT_S,
401 | MIPS_INS_CLT_U,
402 | MIPS_INS_CLZ,
403 | MIPS_INS_CMPGDU,
404 | MIPS_INS_CMPGU,
405 | MIPS_INS_CMPU,
406 | MIPS_INS_CMP,
407 | MIPS_INS_COPY_S,
408 | MIPS_INS_COPY_U,
409 | MIPS_INS_CTC1,
410 | MIPS_INS_CTCMSA,
411 | MIPS_INS_CVT,
412 | MIPS_INS_C,
413 | MIPS_INS_CMPI,
414 | MIPS_INS_DADD,
415 | MIPS_INS_DADDI,
416 | MIPS_INS_DADDIU,
417 | MIPS_INS_DADDU,
418 | MIPS_INS_DAHI,
419 | MIPS_INS_DALIGN,
420 | MIPS_INS_DATI,
421 | MIPS_INS_DAUI,
422 | MIPS_INS_DBITSWAP,
423 | MIPS_INS_DCLO,
424 | MIPS_INS_DCLZ,
425 | MIPS_INS_DDIV,
426 | MIPS_INS_DDIVU,
427 | MIPS_INS_DERET,
428 | MIPS_INS_DEXT,
429 | MIPS_INS_DEXTM,
430 | MIPS_INS_DEXTU,
431 | MIPS_INS_DI,
432 | MIPS_INS_DINS,
433 | MIPS_INS_DINSM,
434 | MIPS_INS_DINSU,
435 | MIPS_INS_DIV,
436 | MIPS_INS_DIVU,
437 | MIPS_INS_DIV_S,
438 | MIPS_INS_DIV_U,
439 | MIPS_INS_DLSA,
440 | MIPS_INS_DMFC0,
441 | MIPS_INS_DMFC1,
442 | MIPS_INS_DMFC2,
443 | MIPS_INS_DMOD,
444 | MIPS_INS_DMODU,
445 | MIPS_INS_DMTC0,
446 | MIPS_INS_DMTC1,
447 | MIPS_INS_DMTC2,
448 | MIPS_INS_DMUH,
449 | MIPS_INS_DMUHU,
450 | MIPS_INS_DMUL,
451 | MIPS_INS_DMULT,
452 | MIPS_INS_DMULTU,
453 | MIPS_INS_DMULU,
454 | MIPS_INS_DOTP_S,
455 | MIPS_INS_DOTP_U,
456 | MIPS_INS_DPADD_S,
457 | MIPS_INS_DPADD_U,
458 | MIPS_INS_DPAQX_SA,
459 | MIPS_INS_DPAQX_S,
460 | MIPS_INS_DPAQ_SA,
461 | MIPS_INS_DPAQ_S,
462 | MIPS_INS_DPAU,
463 | MIPS_INS_DPAX,
464 | MIPS_INS_DPA,
465 | MIPS_INS_DPOP,
466 | MIPS_INS_DPSQX_SA,
467 | MIPS_INS_DPSQX_S,
468 | MIPS_INS_DPSQ_SA,
469 | MIPS_INS_DPSQ_S,
470 | MIPS_INS_DPSUB_S,
471 | MIPS_INS_DPSUB_U,
472 | MIPS_INS_DPSU,
473 | MIPS_INS_DPSX,
474 | MIPS_INS_DPS,
475 | MIPS_INS_DROTR,
476 | MIPS_INS_DROTR32,
477 | MIPS_INS_DROTRV,
478 | MIPS_INS_DSBH,
479 | MIPS_INS_DSHD,
480 | MIPS_INS_DSLL,
481 | MIPS_INS_DSLL32,
482 | MIPS_INS_DSLLV,
483 | MIPS_INS_DSRA,
484 | MIPS_INS_DSRA32,
485 | MIPS_INS_DSRAV,
486 | MIPS_INS_DSRL,
487 | MIPS_INS_DSRL32,
488 | MIPS_INS_DSRLV,
489 | MIPS_INS_DSUB,
490 | MIPS_INS_DSUBU,
491 | MIPS_INS_EHB,
492 | MIPS_INS_EI,
493 | MIPS_INS_ERET,
494 | MIPS_INS_EXT,
495 | MIPS_INS_EXTP,
496 | MIPS_INS_EXTPDP,
497 | MIPS_INS_EXTPDPV,
498 | MIPS_INS_EXTPV,
499 | MIPS_INS_EXTRV_RS,
500 | MIPS_INS_EXTRV_R,
501 | MIPS_INS_EXTRV_S,
502 | MIPS_INS_EXTRV,
503 | MIPS_INS_EXTR_RS,
504 | MIPS_INS_EXTR_R,
505 | MIPS_INS_EXTR_S,
506 | MIPS_INS_EXTR,
507 | MIPS_INS_EXTS,
508 | MIPS_INS_EXTS32,
509 | MIPS_INS_ABS,
510 | MIPS_INS_FADD,
511 | MIPS_INS_FCAF,
512 | MIPS_INS_FCEQ,
513 | MIPS_INS_FCLASS,
514 | MIPS_INS_FCLE,
515 | MIPS_INS_FCLT,
516 | MIPS_INS_FCNE,
517 | MIPS_INS_FCOR,
518 | MIPS_INS_FCUEQ,
519 | MIPS_INS_FCULE,
520 | MIPS_INS_FCULT,
521 | MIPS_INS_FCUNE,
522 | MIPS_INS_FCUN,
523 | MIPS_INS_FDIV,
524 | MIPS_INS_FEXDO,
525 | MIPS_INS_FEXP2,
526 | MIPS_INS_FEXUPL,
527 | MIPS_INS_FEXUPR,
528 | MIPS_INS_FFINT_S,
529 | MIPS_INS_FFINT_U,
530 | MIPS_INS_FFQL,
531 | MIPS_INS_FFQR,
532 | MIPS_INS_FILL,
533 | MIPS_INS_FLOG2,
534 | MIPS_INS_FLOOR,
535 | MIPS_INS_FMADD,
536 | MIPS_INS_FMAX_A,
537 | MIPS_INS_FMAX,
538 | MIPS_INS_FMIN_A,
539 | MIPS_INS_FMIN,
540 | MIPS_INS_MOV,
541 | MIPS_INS_FMSUB,
542 | MIPS_INS_FMUL,
543 | MIPS_INS_MUL,
544 | MIPS_INS_NEG,
545 | MIPS_INS_FRCP,
546 | MIPS_INS_FRINT,
547 | MIPS_INS_FRSQRT,
548 | MIPS_INS_FSAF,
549 | MIPS_INS_FSEQ,
550 | MIPS_INS_FSLE,
551 | MIPS_INS_FSLT,
552 | MIPS_INS_FSNE,
553 | MIPS_INS_FSOR,
554 | MIPS_INS_FSQRT,
555 | MIPS_INS_SQRT,
556 | MIPS_INS_FSUB,
557 | MIPS_INS_SUB,
558 | MIPS_INS_FSUEQ,
559 | MIPS_INS_FSULE,
560 | MIPS_INS_FSULT,
561 | MIPS_INS_FSUNE,
562 | MIPS_INS_FSUN,
563 | MIPS_INS_FTINT_S,
564 | MIPS_INS_FTINT_U,
565 | MIPS_INS_FTQ,
566 | MIPS_INS_FTRUNC_S,
567 | MIPS_INS_FTRUNC_U,
568 | MIPS_INS_HADD_S,
569 | MIPS_INS_HADD_U,
570 | MIPS_INS_HSUB_S,
571 | MIPS_INS_HSUB_U,
572 | MIPS_INS_ILVEV,
573 | MIPS_INS_ILVL,
574 | MIPS_INS_ILVOD,
575 | MIPS_INS_ILVR,
576 | MIPS_INS_INS,
577 | MIPS_INS_INSERT,
578 | MIPS_INS_INSV,
579 | MIPS_INS_INSVE,
580 | MIPS_INS_J,
581 | MIPS_INS_JAL,
582 | MIPS_INS_JALR,
583 | MIPS_INS_JALRS,
584 | MIPS_INS_JALS,
585 | MIPS_INS_JALX,
586 | MIPS_INS_JIALC,
587 | MIPS_INS_JIC,
588 | MIPS_INS_JR,
589 | MIPS_INS_JRADDIUSP,
590 | MIPS_INS_JRC,
591 | MIPS_INS_JALRC,
592 | MIPS_INS_LB,
593 | MIPS_INS_LBUX,
594 | MIPS_INS_LBU,
595 | MIPS_INS_LD,
596 | MIPS_INS_LDC1,
597 | MIPS_INS_LDC2,
598 | MIPS_INS_LDC3,
599 | MIPS_INS_LDI,
600 | MIPS_INS_LDL,
601 | MIPS_INS_LDPC,
602 | MIPS_INS_LDR,
603 | MIPS_INS_LDXC1,
604 | MIPS_INS_LH,
605 | MIPS_INS_LHX,
606 | MIPS_INS_LHU,
607 | MIPS_INS_LL,
608 | MIPS_INS_LLD,
609 | MIPS_INS_LSA,
610 | MIPS_INS_LUXC1,
611 | MIPS_INS_LUI,
612 | MIPS_INS_LW,
613 | MIPS_INS_LWC1,
614 | MIPS_INS_LWC2,
615 | MIPS_INS_LWC3,
616 | MIPS_INS_LWL,
617 | MIPS_INS_LWPC,
618 | MIPS_INS_LWR,
619 | MIPS_INS_LWUPC,
620 | MIPS_INS_LWU,
621 | MIPS_INS_LWX,
622 | MIPS_INS_LWXC1,
623 | MIPS_INS_LI,
624 | MIPS_INS_MADD,
625 | MIPS_INS_MADDF,
626 | MIPS_INS_MADDR_Q,
627 | MIPS_INS_MADDU,
628 | MIPS_INS_MADDV,
629 | MIPS_INS_MADD_Q,
630 | MIPS_INS_MAQ_SA,
631 | MIPS_INS_MAQ_S,
632 | MIPS_INS_MAXA,
633 | MIPS_INS_MAXI_S,
634 | MIPS_INS_MAXI_U,
635 | MIPS_INS_MAX_A,
636 | MIPS_INS_MAX,
637 | MIPS_INS_MAX_S,
638 | MIPS_INS_MAX_U,
639 | MIPS_INS_MFC0,
640 | MIPS_INS_MFC1,
641 | MIPS_INS_MFC2,
642 | MIPS_INS_MFHC1,
643 | MIPS_INS_MFHI,
644 | MIPS_INS_MFLO,
645 | MIPS_INS_MINA,
646 | MIPS_INS_MINI_S,
647 | MIPS_INS_MINI_U,
648 | MIPS_INS_MIN_A,
649 | MIPS_INS_MIN,
650 | MIPS_INS_MIN_S,
651 | MIPS_INS_MIN_U,
652 | MIPS_INS_MOD,
653 | MIPS_INS_MODSUB,
654 | MIPS_INS_MODU,
655 | MIPS_INS_MOD_S,
656 | MIPS_INS_MOD_U,
657 | MIPS_INS_MOVE,
658 | MIPS_INS_MOVF,
659 | MIPS_INS_MOVN,
660 | MIPS_INS_MOVT,
661 | MIPS_INS_MOVZ,
662 | MIPS_INS_MSUB,
663 | MIPS_INS_MSUBF,
664 | MIPS_INS_MSUBR_Q,
665 | MIPS_INS_MSUBU,
666 | MIPS_INS_MSUBV,
667 | MIPS_INS_MSUB_Q,
668 | MIPS_INS_MTC0,
669 | MIPS_INS_MTC1,
670 | MIPS_INS_MTC2,
671 | MIPS_INS_MTHC1,
672 | MIPS_INS_MTHI,
673 | MIPS_INS_MTHLIP,
674 | MIPS_INS_MTLO,
675 | MIPS_INS_MTM0,
676 | MIPS_INS_MTM1,
677 | MIPS_INS_MTM2,
678 | MIPS_INS_MTP0,
679 | MIPS_INS_MTP1,
680 | MIPS_INS_MTP2,
681 | MIPS_INS_MUH,
682 | MIPS_INS_MUHU,
683 | MIPS_INS_MULEQ_S,
684 | MIPS_INS_MULEU_S,
685 | MIPS_INS_MULQ_RS,
686 | MIPS_INS_MULQ_S,
687 | MIPS_INS_MULR_Q,
688 | MIPS_INS_MULSAQ_S,
689 | MIPS_INS_MULSA,
690 | MIPS_INS_MULT,
691 | MIPS_INS_MULTU,
692 | MIPS_INS_MULU,
693 | MIPS_INS_MULV,
694 | MIPS_INS_MUL_Q,
695 | MIPS_INS_MUL_S,
696 | MIPS_INS_NLOC,
697 | MIPS_INS_NLZC,
698 | MIPS_INS_NMADD,
699 | MIPS_INS_NMSUB,
700 | MIPS_INS_NOR,
701 | MIPS_INS_NORI,
702 | MIPS_INS_NOT,
703 | MIPS_INS_OR,
704 | MIPS_INS_ORI,
705 | MIPS_INS_PACKRL,
706 | MIPS_INS_PAUSE,
707 | MIPS_INS_PCKEV,
708 | MIPS_INS_PCKOD,
709 | MIPS_INS_PCNT,
710 | MIPS_INS_PICK,
711 | MIPS_INS_POP,
712 | MIPS_INS_PRECEQU,
713 | MIPS_INS_PRECEQ,
714 | MIPS_INS_PRECEU,
715 | MIPS_INS_PRECRQU_S,
716 | MIPS_INS_PRECRQ,
717 | MIPS_INS_PRECRQ_RS,
718 | MIPS_INS_PRECR,
719 | MIPS_INS_PRECR_SRA,
720 | MIPS_INS_PRECR_SRA_R,
721 | MIPS_INS_PREF,
722 | MIPS_INS_PREPEND,
723 | MIPS_INS_RADDU,
724 | MIPS_INS_RDDSP,
725 | MIPS_INS_RDHWR,
726 | MIPS_INS_REPLV,
727 | MIPS_INS_REPL,
728 | MIPS_INS_RINT,
729 | MIPS_INS_ROTR,
730 | MIPS_INS_ROTRV,
731 | MIPS_INS_ROUND,
732 | MIPS_INS_SAT_S,
733 | MIPS_INS_SAT_U,
734 | MIPS_INS_SB,
735 | MIPS_INS_SC,
736 | MIPS_INS_SCD,
737 | MIPS_INS_SD,
738 | MIPS_INS_SDBBP,
739 | MIPS_INS_SDC1,
740 | MIPS_INS_SDC2,
741 | MIPS_INS_SDC3,
742 | MIPS_INS_SDL,
743 | MIPS_INS_SDR,
744 | MIPS_INS_SDXC1,
745 | MIPS_INS_SEB,
746 | MIPS_INS_SEH,
747 | MIPS_INS_SELEQZ,
748 | MIPS_INS_SELNEZ,
749 | MIPS_INS_SEL,
750 | MIPS_INS_SEQ,
751 | MIPS_INS_SEQI,
752 | MIPS_INS_SH,
753 | MIPS_INS_SHF,
754 | MIPS_INS_SHILO,
755 | MIPS_INS_SHILOV,
756 | MIPS_INS_SHLLV,
757 | MIPS_INS_SHLLV_S,
758 | MIPS_INS_SHLL,
759 | MIPS_INS_SHLL_S,
760 | MIPS_INS_SHRAV,
761 | MIPS_INS_SHRAV_R,
762 | MIPS_INS_SHRA,
763 | MIPS_INS_SHRA_R,
764 | MIPS_INS_SHRLV,
765 | MIPS_INS_SHRL,
766 | MIPS_INS_SLDI,
767 | MIPS_INS_SLD,
768 | MIPS_INS_SLL,
769 | MIPS_INS_SLLI,
770 | MIPS_INS_SLLV,
771 | MIPS_INS_SLT,
772 | MIPS_INS_SLTI,
773 | MIPS_INS_SLTIU,
774 | MIPS_INS_SLTU,
775 | MIPS_INS_SNE,
776 | MIPS_INS_SNEI,
777 | MIPS_INS_SPLATI,
778 | MIPS_INS_SPLAT,
779 | MIPS_INS_SRA,
780 | MIPS_INS_SRAI,
781 | MIPS_INS_SRARI,
782 | MIPS_INS_SRAR,
783 | MIPS_INS_SRAV,
784 | MIPS_INS_SRL,
785 | MIPS_INS_SRLI,
786 | MIPS_INS_SRLRI,
787 | MIPS_INS_SRLR,
788 | MIPS_INS_SRLV,
789 | MIPS_INS_SSNOP,
790 | MIPS_INS_ST,
791 | MIPS_INS_SUBQH,
792 | MIPS_INS_SUBQH_R,
793 | MIPS_INS_SUBQ,
794 | MIPS_INS_SUBQ_S,
795 | MIPS_INS_SUBSUS_U,
796 | MIPS_INS_SUBSUU_S,
797 | MIPS_INS_SUBS_S,
798 | MIPS_INS_SUBS_U,
799 | MIPS_INS_SUBUH,
800 | MIPS_INS_SUBUH_R,
801 | MIPS_INS_SUBU,
802 | MIPS_INS_SUBU_S,
803 | MIPS_INS_SUBVI,
804 | MIPS_INS_SUBV,
805 | MIPS_INS_SUXC1,
806 | MIPS_INS_SW,
807 | MIPS_INS_SWC1,
808 | MIPS_INS_SWC2,
809 | MIPS_INS_SWC3,
810 | MIPS_INS_SWL,
811 | MIPS_INS_SWR,
812 | MIPS_INS_SWXC1,
813 | MIPS_INS_SYNC,
814 | MIPS_INS_SYSCALL,
815 | MIPS_INS_TEQ,
816 | MIPS_INS_TEQI,
817 | MIPS_INS_TGE,
818 | MIPS_INS_TGEI,
819 | MIPS_INS_TGEIU,
820 | MIPS_INS_TGEU,
821 | MIPS_INS_TLBP,
822 | MIPS_INS_TLBR,
823 | MIPS_INS_TLBWI,
824 | MIPS_INS_TLBWR,
825 | MIPS_INS_TLT,
826 | MIPS_INS_TLTI,
827 | MIPS_INS_TLTIU,
828 | MIPS_INS_TLTU,
829 | MIPS_INS_TNE,
830 | MIPS_INS_TNEI,
831 | MIPS_INS_TRUNC,
832 | MIPS_INS_V3MULU,
833 | MIPS_INS_VMM0,
834 | MIPS_INS_VMULU,
835 | MIPS_INS_VSHF,
836 | MIPS_INS_WAIT,
837 | MIPS_INS_WRDSP,
838 | MIPS_INS_WSBH,
839 | MIPS_INS_XOR,
840 | MIPS_INS_XORI,
841 |
842 | //> some alias instructions
843 | MIPS_INS_NOP,
844 | MIPS_INS_NEGU,
845 |
846 | //> special instructions
847 | MIPS_INS_JALR_HB, // jump and link with Hazard Barrier
848 | MIPS_INS_JR_HB, // jump register with Hazard Barrier
849 |
850 | MIPS_INS_ENDING,
851 | } mips_insn;
852 |
853 | //> Group of MIPS instructions
854 | typedef enum mips_insn_group {
855 | MIPS_GRP_INVALID = 0, // = CS_GRP_INVALID
856 |
857 | //> Generic groups
858 | // all jump instructions (conditional+direct+indirect jumps)
859 | MIPS_GRP_JUMP, // = CS_GRP_JUMP
860 |
861 | //> Architecture-specific groups
862 | MIPS_GRP_BITCOUNT = 128,
863 | MIPS_GRP_DSP,
864 | MIPS_GRP_DSPR2,
865 | MIPS_GRP_FPIDX,
866 | MIPS_GRP_MSA,
867 | MIPS_GRP_MIPS32R2,
868 | MIPS_GRP_MIPS64,
869 | MIPS_GRP_MIPS64R2,
870 | MIPS_GRP_SEINREG,
871 | MIPS_GRP_STDENC,
872 | MIPS_GRP_SWAP,
873 | MIPS_GRP_MICROMIPS,
874 | MIPS_GRP_MIPS16MODE,
875 | MIPS_GRP_FP64BIT,
876 | MIPS_GRP_NONANSFPMATH,
877 | MIPS_GRP_NOTFP64BIT,
878 | MIPS_GRP_NOTINMICROMIPS,
879 | MIPS_GRP_NOTNACL,
880 | MIPS_GRP_NOTMIPS32R6,
881 | MIPS_GRP_NOTMIPS64R6,
882 | MIPS_GRP_CNMIPS,
883 | MIPS_GRP_MIPS32,
884 | MIPS_GRP_MIPS32R6,
885 | MIPS_GRP_MIPS64R6,
886 | MIPS_GRP_MIPS2,
887 | MIPS_GRP_MIPS3,
888 | MIPS_GRP_MIPS3_32,
889 | MIPS_GRP_MIPS3_32R2,
890 | MIPS_GRP_MIPS4_32,
891 | MIPS_GRP_MIPS4_32R2,
892 | MIPS_GRP_MIPS5_32R2,
893 | MIPS_GRP_GP32BIT,
894 | MIPS_GRP_GP64BIT,
895 |
896 | MIPS_GRP_ENDING,
897 | } mips_insn_group;
898 |
899 | #ifdef __cplusplus
900 | }
901 | #endif
902 |
903 | #endif
904 |
--------------------------------------------------------------------------------
/capstone-3.0.4-win32/include/platform.h:
--------------------------------------------------------------------------------
1 | /* Capstone Disassembly Engine */
2 | /* By Axel Souchet & Nguyen Anh Quynh, 2014 */
3 |
4 | // handle C99 issue (for pre-2013 VisualStudio)
5 | #ifndef CAPSTONE_PLATFORM_H
6 | #define CAPSTONE_PLATFORM_H
7 |
8 | #if !defined(__MINGW32__) && !defined(__MINGW64__) && (defined (WIN32) || defined (WIN64) || defined (_WIN32) || defined (_WIN64))
9 | // MSVC
10 |
11 | // stdbool.h
12 | #if (_MSC_VER < 1800)
13 | #ifndef __cplusplus
14 | typedef unsigned char bool;
15 | #define false 0
16 | #define true 1
17 | #endif
18 |
19 | #else
20 | // VisualStudio 2013+ -> C99 is supported
21 | #include
22 | #endif
23 |
24 | #else // not MSVC -> C99 is supported
25 | #include
26 | #endif
27 |
28 | #endif
29 |
--------------------------------------------------------------------------------
/capstone-3.0.4-win32/include/sparc.h:
--------------------------------------------------------------------------------
1 | #ifndef CAPSTONE_SPARC_H
2 | #define CAPSTONE_SPARC_H
3 |
4 | /* Capstone Disassembly Engine */
5 | /* By Nguyen Anh Quynh , 2014 */
6 |
7 | #ifdef __cplusplus
8 | extern "C" {
9 | #endif
10 |
11 | #include
12 | #include "platform.h"
13 |
14 | // GCC SPARC toolchain has a default macro called "sparc" which breaks
15 | // compilation
16 | #undef sparc
17 |
18 | #ifdef _MSC_VER
19 | #pragma warning(disable:4201)
20 | #endif
21 |
22 | //> Enums corresponding to Sparc condition codes, both icc's and fcc's.
23 | typedef enum sparc_cc {
24 | SPARC_CC_INVALID = 0, // invalid CC (default)
25 | //> Integer condition codes
26 | SPARC_CC_ICC_A = 8+256, // Always
27 | SPARC_CC_ICC_N = 0+256, // Never
28 | SPARC_CC_ICC_NE = 9+256, // Not Equal
29 | SPARC_CC_ICC_E = 1+256, // Equal
30 | SPARC_CC_ICC_G = 10+256, // Greater
31 | SPARC_CC_ICC_LE = 2+256, // Less or Equal
32 | SPARC_CC_ICC_GE = 11+256, // Greater or Equal
33 | SPARC_CC_ICC_L = 3+256, // Less
34 | SPARC_CC_ICC_GU = 12+256, // Greater Unsigned
35 | SPARC_CC_ICC_LEU = 4+256, // Less or Equal Unsigned
36 | SPARC_CC_ICC_CC = 13+256, // Carry Clear/Great or Equal Unsigned
37 | SPARC_CC_ICC_CS = 5+256, // Carry Set/Less Unsigned
38 | SPARC_CC_ICC_POS = 14+256, // Positive
39 | SPARC_CC_ICC_NEG = 6+256, // Negative
40 | SPARC_CC_ICC_VC = 15+256, // Overflow Clear
41 | SPARC_CC_ICC_VS = 7+256, // Overflow Set
42 |
43 | //> Floating condition codes
44 | SPARC_CC_FCC_A = 8+16+256, // Always
45 | SPARC_CC_FCC_N = 0+16+256, // Never
46 | SPARC_CC_FCC_U = 7+16+256, // Unordered
47 | SPARC_CC_FCC_G = 6+16+256, // Greater
48 | SPARC_CC_FCC_UG = 5+16+256, // Unordered or Greater
49 | SPARC_CC_FCC_L = 4+16+256, // Less
50 | SPARC_CC_FCC_UL = 3+16+256, // Unordered or Less
51 | SPARC_CC_FCC_LG = 2+16+256, // Less or Greater
52 | SPARC_CC_FCC_NE = 1+16+256, // Not Equal
53 | SPARC_CC_FCC_E = 9+16+256, // Equal
54 | SPARC_CC_FCC_UE = 10+16+256, // Unordered or Equal
55 | SPARC_CC_FCC_GE = 11+16+256, // Greater or Equal
56 | SPARC_CC_FCC_UGE = 12+16+256, // Unordered or Greater or Equal
57 | SPARC_CC_FCC_LE = 13+16+256, // Less or Equal
58 | SPARC_CC_FCC_ULE = 14+16+256, // Unordered or Less or Equal
59 | SPARC_CC_FCC_O = 15+16+256, // Ordered
60 | } sparc_cc;
61 |
62 | //> Branch hint
63 | typedef enum sparc_hint {
64 | SPARC_HINT_INVALID = 0, // no hint
65 | SPARC_HINT_A = 1 << 0, // annul delay slot instruction
66 | SPARC_HINT_PT = 1 << 1, // branch taken
67 | SPARC_HINT_PN = 1 << 2, // branch NOT taken
68 | } sparc_hint;
69 |
70 | //> Operand type for instruction's operands
71 | typedef enum sparc_op_type {
72 | SPARC_OP_INVALID = 0, // = CS_OP_INVALID (Uninitialized).
73 | SPARC_OP_REG, // = CS_OP_REG (Register operand).
74 | SPARC_OP_IMM, // = CS_OP_IMM (Immediate operand).
75 | SPARC_OP_MEM, // = CS_OP_MEM (Memory operand).
76 | } sparc_op_type;
77 |
78 | // Instruction's operand referring to memory
79 | // This is associated with SPARC_OP_MEM operand type above
80 | typedef struct sparc_op_mem {
81 | uint8_t base; // base register
82 | uint8_t index; // index register
83 | int32_t disp; // displacement/offset value
84 | } sparc_op_mem;
85 |
86 | // Instruction operand
87 | typedef struct cs_sparc_op {
88 | sparc_op_type type; // operand type
89 | union {
90 | unsigned int reg; // register value for REG operand
91 | int32_t imm; // immediate value for IMM operand
92 | sparc_op_mem mem; // base/disp value for MEM operand
93 | };
94 | } cs_sparc_op;
95 |
96 | // Instruction structure
97 | typedef struct cs_sparc {
98 | sparc_cc cc; // code condition for this insn
99 | sparc_hint hint; // branch hint: encoding as bitwise OR of sparc_hint.
100 | // Number of operands of this instruction,
101 | // or 0 when instruction has no operand.
102 | uint8_t op_count;
103 | cs_sparc_op operands[4]; // operands for this instruction.
104 | } cs_sparc;
105 |
106 | //> SPARC registers
107 | typedef enum sparc_reg {
108 | SPARC_REG_INVALID = 0,
109 |
110 | SPARC_REG_F0,
111 | SPARC_REG_F1,
112 | SPARC_REG_F2,
113 | SPARC_REG_F3,
114 | SPARC_REG_F4,
115 | SPARC_REG_F5,
116 | SPARC_REG_F6,
117 | SPARC_REG_F7,
118 | SPARC_REG_F8,
119 | SPARC_REG_F9,
120 | SPARC_REG_F10,
121 | SPARC_REG_F11,
122 | SPARC_REG_F12,
123 | SPARC_REG_F13,
124 | SPARC_REG_F14,
125 | SPARC_REG_F15,
126 | SPARC_REG_F16,
127 | SPARC_REG_F17,
128 | SPARC_REG_F18,
129 | SPARC_REG_F19,
130 | SPARC_REG_F20,
131 | SPARC_REG_F21,
132 | SPARC_REG_F22,
133 | SPARC_REG_F23,
134 | SPARC_REG_F24,
135 | SPARC_REG_F25,
136 | SPARC_REG_F26,
137 | SPARC_REG_F27,
138 | SPARC_REG_F28,
139 | SPARC_REG_F29,
140 | SPARC_REG_F30,
141 | SPARC_REG_F31,
142 | SPARC_REG_F32,
143 | SPARC_REG_F34,
144 | SPARC_REG_F36,
145 | SPARC_REG_F38,
146 | SPARC_REG_F40,
147 | SPARC_REG_F42,
148 | SPARC_REG_F44,
149 | SPARC_REG_F46,
150 | SPARC_REG_F48,
151 | SPARC_REG_F50,
152 | SPARC_REG_F52,
153 | SPARC_REG_F54,
154 | SPARC_REG_F56,
155 | SPARC_REG_F58,
156 | SPARC_REG_F60,
157 | SPARC_REG_F62,
158 | SPARC_REG_FCC0, // Floating condition codes
159 | SPARC_REG_FCC1,
160 | SPARC_REG_FCC2,
161 | SPARC_REG_FCC3,
162 | SPARC_REG_FP,
163 | SPARC_REG_G0,
164 | SPARC_REG_G1,
165 | SPARC_REG_G2,
166 | SPARC_REG_G3,
167 | SPARC_REG_G4,
168 | SPARC_REG_G5,
169 | SPARC_REG_G6,
170 | SPARC_REG_G7,
171 | SPARC_REG_I0,
172 | SPARC_REG_I1,
173 | SPARC_REG_I2,
174 | SPARC_REG_I3,
175 | SPARC_REG_I4,
176 | SPARC_REG_I5,
177 | SPARC_REG_I7,
178 | SPARC_REG_ICC, // Integer condition codes
179 | SPARC_REG_L0,
180 | SPARC_REG_L1,
181 | SPARC_REG_L2,
182 | SPARC_REG_L3,
183 | SPARC_REG_L4,
184 | SPARC_REG_L5,
185 | SPARC_REG_L6,
186 | SPARC_REG_L7,
187 | SPARC_REG_O0,
188 | SPARC_REG_O1,
189 | SPARC_REG_O2,
190 | SPARC_REG_O3,
191 | SPARC_REG_O4,
192 | SPARC_REG_O5,
193 | SPARC_REG_O7,
194 | SPARC_REG_SP,
195 | SPARC_REG_Y,
196 |
197 | // special register
198 | SPARC_REG_XCC,
199 |
200 | SPARC_REG_ENDING, // <-- mark the end of the list of registers
201 |
202 | // extras
203 | SPARC_REG_O6 = SPARC_REG_SP,
204 | SPARC_REG_I6 = SPARC_REG_FP,
205 | } sparc_reg;
206 |
207 | //> SPARC instruction
208 | typedef enum sparc_insn {
209 | SPARC_INS_INVALID = 0,
210 |
211 | SPARC_INS_ADDCC,
212 | SPARC_INS_ADDX,
213 | SPARC_INS_ADDXCC,
214 | SPARC_INS_ADDXC,
215 | SPARC_INS_ADDXCCC,
216 | SPARC_INS_ADD,
217 | SPARC_INS_ALIGNADDR,
218 | SPARC_INS_ALIGNADDRL,
219 | SPARC_INS_ANDCC,
220 | SPARC_INS_ANDNCC,
221 | SPARC_INS_ANDN,
222 | SPARC_INS_AND,
223 | SPARC_INS_ARRAY16,
224 | SPARC_INS_ARRAY32,
225 | SPARC_INS_ARRAY8,
226 | SPARC_INS_B,
227 | SPARC_INS_JMP,
228 | SPARC_INS_BMASK,
229 | SPARC_INS_FB,
230 | SPARC_INS_BRGEZ,
231 | SPARC_INS_BRGZ,
232 | SPARC_INS_BRLEZ,
233 | SPARC_INS_BRLZ,
234 | SPARC_INS_BRNZ,
235 | SPARC_INS_BRZ,
236 | SPARC_INS_BSHUFFLE,
237 | SPARC_INS_CALL,
238 | SPARC_INS_CASX,
239 | SPARC_INS_CAS,
240 | SPARC_INS_CMASK16,
241 | SPARC_INS_CMASK32,
242 | SPARC_INS_CMASK8,
243 | SPARC_INS_CMP,
244 | SPARC_INS_EDGE16,
245 | SPARC_INS_EDGE16L,
246 | SPARC_INS_EDGE16LN,
247 | SPARC_INS_EDGE16N,
248 | SPARC_INS_EDGE32,
249 | SPARC_INS_EDGE32L,
250 | SPARC_INS_EDGE32LN,
251 | SPARC_INS_EDGE32N,
252 | SPARC_INS_EDGE8,
253 | SPARC_INS_EDGE8L,
254 | SPARC_INS_EDGE8LN,
255 | SPARC_INS_EDGE8N,
256 | SPARC_INS_FABSD,
257 | SPARC_INS_FABSQ,
258 | SPARC_INS_FABSS,
259 | SPARC_INS_FADDD,
260 | SPARC_INS_FADDQ,
261 | SPARC_INS_FADDS,
262 | SPARC_INS_FALIGNDATA,
263 | SPARC_INS_FAND,
264 | SPARC_INS_FANDNOT1,
265 | SPARC_INS_FANDNOT1S,
266 | SPARC_INS_FANDNOT2,
267 | SPARC_INS_FANDNOT2S,
268 | SPARC_INS_FANDS,
269 | SPARC_INS_FCHKSM16,
270 | SPARC_INS_FCMPD,
271 | SPARC_INS_FCMPEQ16,
272 | SPARC_INS_FCMPEQ32,
273 | SPARC_INS_FCMPGT16,
274 | SPARC_INS_FCMPGT32,
275 | SPARC_INS_FCMPLE16,
276 | SPARC_INS_FCMPLE32,
277 | SPARC_INS_FCMPNE16,
278 | SPARC_INS_FCMPNE32,
279 | SPARC_INS_FCMPQ,
280 | SPARC_INS_FCMPS,
281 | SPARC_INS_FDIVD,
282 | SPARC_INS_FDIVQ,
283 | SPARC_INS_FDIVS,
284 | SPARC_INS_FDMULQ,
285 | SPARC_INS_FDTOI,
286 | SPARC_INS_FDTOQ,
287 | SPARC_INS_FDTOS,
288 | SPARC_INS_FDTOX,
289 | SPARC_INS_FEXPAND,
290 | SPARC_INS_FHADDD,
291 | SPARC_INS_FHADDS,
292 | SPARC_INS_FHSUBD,
293 | SPARC_INS_FHSUBS,
294 | SPARC_INS_FITOD,
295 | SPARC_INS_FITOQ,
296 | SPARC_INS_FITOS,
297 | SPARC_INS_FLCMPD,
298 | SPARC_INS_FLCMPS,
299 | SPARC_INS_FLUSHW,
300 | SPARC_INS_FMEAN16,
301 | SPARC_INS_FMOVD,
302 | SPARC_INS_FMOVQ,
303 | SPARC_INS_FMOVRDGEZ,
304 | SPARC_INS_FMOVRQGEZ,
305 | SPARC_INS_FMOVRSGEZ,
306 | SPARC_INS_FMOVRDGZ,
307 | SPARC_INS_FMOVRQGZ,
308 | SPARC_INS_FMOVRSGZ,
309 | SPARC_INS_FMOVRDLEZ,
310 | SPARC_INS_FMOVRQLEZ,
311 | SPARC_INS_FMOVRSLEZ,
312 | SPARC_INS_FMOVRDLZ,
313 | SPARC_INS_FMOVRQLZ,
314 | SPARC_INS_FMOVRSLZ,
315 | SPARC_INS_FMOVRDNZ,
316 | SPARC_INS_FMOVRQNZ,
317 | SPARC_INS_FMOVRSNZ,
318 | SPARC_INS_FMOVRDZ,
319 | SPARC_INS_FMOVRQZ,
320 | SPARC_INS_FMOVRSZ,
321 | SPARC_INS_FMOVS,
322 | SPARC_INS_FMUL8SUX16,
323 | SPARC_INS_FMUL8ULX16,
324 | SPARC_INS_FMUL8X16,
325 | SPARC_INS_FMUL8X16AL,
326 | SPARC_INS_FMUL8X16AU,
327 | SPARC_INS_FMULD,
328 | SPARC_INS_FMULD8SUX16,
329 | SPARC_INS_FMULD8ULX16,
330 | SPARC_INS_FMULQ,
331 | SPARC_INS_FMULS,
332 | SPARC_INS_FNADDD,
333 | SPARC_INS_FNADDS,
334 | SPARC_INS_FNAND,
335 | SPARC_INS_FNANDS,
336 | SPARC_INS_FNEGD,
337 | SPARC_INS_FNEGQ,
338 | SPARC_INS_FNEGS,
339 | SPARC_INS_FNHADDD,
340 | SPARC_INS_FNHADDS,
341 | SPARC_INS_FNOR,
342 | SPARC_INS_FNORS,
343 | SPARC_INS_FNOT1,
344 | SPARC_INS_FNOT1S,
345 | SPARC_INS_FNOT2,
346 | SPARC_INS_FNOT2S,
347 | SPARC_INS_FONE,
348 | SPARC_INS_FONES,
349 | SPARC_INS_FOR,
350 | SPARC_INS_FORNOT1,
351 | SPARC_INS_FORNOT1S,
352 | SPARC_INS_FORNOT2,
353 | SPARC_INS_FORNOT2S,
354 | SPARC_INS_FORS,
355 | SPARC_INS_FPACK16,
356 | SPARC_INS_FPACK32,
357 | SPARC_INS_FPACKFIX,
358 | SPARC_INS_FPADD16,
359 | SPARC_INS_FPADD16S,
360 | SPARC_INS_FPADD32,
361 | SPARC_INS_FPADD32S,
362 | SPARC_INS_FPADD64,
363 | SPARC_INS_FPMERGE,
364 | SPARC_INS_FPSUB16,
365 | SPARC_INS_FPSUB16S,
366 | SPARC_INS_FPSUB32,
367 | SPARC_INS_FPSUB32S,
368 | SPARC_INS_FQTOD,
369 | SPARC_INS_FQTOI,
370 | SPARC_INS_FQTOS,
371 | SPARC_INS_FQTOX,
372 | SPARC_INS_FSLAS16,
373 | SPARC_INS_FSLAS32,
374 | SPARC_INS_FSLL16,
375 | SPARC_INS_FSLL32,
376 | SPARC_INS_FSMULD,
377 | SPARC_INS_FSQRTD,
378 | SPARC_INS_FSQRTQ,
379 | SPARC_INS_FSQRTS,
380 | SPARC_INS_FSRA16,
381 | SPARC_INS_FSRA32,
382 | SPARC_INS_FSRC1,
383 | SPARC_INS_FSRC1S,
384 | SPARC_INS_FSRC2,
385 | SPARC_INS_FSRC2S,
386 | SPARC_INS_FSRL16,
387 | SPARC_INS_FSRL32,
388 | SPARC_INS_FSTOD,
389 | SPARC_INS_FSTOI,
390 | SPARC_INS_FSTOQ,
391 | SPARC_INS_FSTOX,
392 | SPARC_INS_FSUBD,
393 | SPARC_INS_FSUBQ,
394 | SPARC_INS_FSUBS,
395 | SPARC_INS_FXNOR,
396 | SPARC_INS_FXNORS,
397 | SPARC_INS_FXOR,
398 | SPARC_INS_FXORS,
399 | SPARC_INS_FXTOD,
400 | SPARC_INS_FXTOQ,
401 | SPARC_INS_FXTOS,
402 | SPARC_INS_FZERO,
403 | SPARC_INS_FZEROS,
404 | SPARC_INS_JMPL,
405 | SPARC_INS_LDD,
406 | SPARC_INS_LD,
407 | SPARC_INS_LDQ,
408 | SPARC_INS_LDSB,
409 | SPARC_INS_LDSH,
410 | SPARC_INS_LDSW,
411 | SPARC_INS_LDUB,
412 | SPARC_INS_LDUH,
413 | SPARC_INS_LDX,
414 | SPARC_INS_LZCNT,
415 | SPARC_INS_MEMBAR,
416 | SPARC_INS_MOVDTOX,
417 | SPARC_INS_MOV,
418 | SPARC_INS_MOVRGEZ,
419 | SPARC_INS_MOVRGZ,
420 | SPARC_INS_MOVRLEZ,
421 | SPARC_INS_MOVRLZ,
422 | SPARC_INS_MOVRNZ,
423 | SPARC_INS_MOVRZ,
424 | SPARC_INS_MOVSTOSW,
425 | SPARC_INS_MOVSTOUW,
426 | SPARC_INS_MULX,
427 | SPARC_INS_NOP,
428 | SPARC_INS_ORCC,
429 | SPARC_INS_ORNCC,
430 | SPARC_INS_ORN,
431 | SPARC_INS_OR,
432 | SPARC_INS_PDIST,
433 | SPARC_INS_PDISTN,
434 | SPARC_INS_POPC,
435 | SPARC_INS_RD,
436 | SPARC_INS_RESTORE,
437 | SPARC_INS_RETT,
438 | SPARC_INS_SAVE,
439 | SPARC_INS_SDIVCC,
440 | SPARC_INS_SDIVX,
441 | SPARC_INS_SDIV,
442 | SPARC_INS_SETHI,
443 | SPARC_INS_SHUTDOWN,
444 | SPARC_INS_SIAM,
445 | SPARC_INS_SLLX,
446 | SPARC_INS_SLL,
447 | SPARC_INS_SMULCC,
448 | SPARC_INS_SMUL,
449 | SPARC_INS_SRAX,
450 | SPARC_INS_SRA,
451 | SPARC_INS_SRLX,
452 | SPARC_INS_SRL,
453 | SPARC_INS_STBAR,
454 | SPARC_INS_STB,
455 | SPARC_INS_STD,
456 | SPARC_INS_ST,
457 | SPARC_INS_STH,
458 | SPARC_INS_STQ,
459 | SPARC_INS_STX,
460 | SPARC_INS_SUBCC,
461 | SPARC_INS_SUBX,
462 | SPARC_INS_SUBXCC,
463 | SPARC_INS_SUB,
464 | SPARC_INS_SWAP,
465 | SPARC_INS_TADDCCTV,
466 | SPARC_INS_TADDCC,
467 | SPARC_INS_T,
468 | SPARC_INS_TSUBCCTV,
469 | SPARC_INS_TSUBCC,
470 | SPARC_INS_UDIVCC,
471 | SPARC_INS_UDIVX,
472 | SPARC_INS_UDIV,
473 | SPARC_INS_UMULCC,
474 | SPARC_INS_UMULXHI,
475 | SPARC_INS_UMUL,
476 | SPARC_INS_UNIMP,
477 | SPARC_INS_FCMPED,
478 | SPARC_INS_FCMPEQ,
479 | SPARC_INS_FCMPES,
480 | SPARC_INS_WR,
481 | SPARC_INS_XMULX,
482 | SPARC_INS_XMULXHI,
483 | SPARC_INS_XNORCC,
484 | SPARC_INS_XNOR,
485 | SPARC_INS_XORCC,
486 | SPARC_INS_XOR,
487 |
488 | // alias instructions
489 | SPARC_INS_RET,
490 | SPARC_INS_RETL,
491 |
492 | SPARC_INS_ENDING, // <-- mark the end of the list of instructions
493 | } sparc_insn;
494 |
495 | //> Group of SPARC instructions
496 | typedef enum sparc_insn_group {
497 | SPARC_GRP_INVALID = 0, // = CS_GRP_INVALID
498 |
499 | //> Generic groups
500 | // all jump instructions (conditional+direct+indirect jumps)
501 | SPARC_GRP_JUMP, // = CS_GRP_JUMP
502 |
503 | //> Architecture-specific groups
504 | SPARC_GRP_HARDQUAD = 128,
505 | SPARC_GRP_V9,
506 | SPARC_GRP_VIS,
507 | SPARC_GRP_VIS2,
508 | SPARC_GRP_VIS3,
509 | SPARC_GRP_32BIT,
510 | SPARC_GRP_64BIT,
511 |
512 | SPARC_GRP_ENDING, // <-- mark the end of the list of groups
513 | } sparc_insn_group;
514 |
515 | #ifdef __cplusplus
516 | }
517 | #endif
518 |
519 | #endif
520 |
--------------------------------------------------------------------------------
/capstone-3.0.4-win32/include/systemz.h:
--------------------------------------------------------------------------------
1 | #ifndef CAPSTONE_SYSTEMZ_H
2 | #define CAPSTONE_SYSTEMZ_H
3 |
4 | /* Capstone Disassembly Engine */
5 | /* By Nguyen Anh Quynh , 2014 */
6 |
7 | #ifdef __cplusplus
8 | extern "C" {
9 | #endif
10 |
11 | #include
12 | #include "platform.h"
13 |
14 | #ifdef _MSC_VER
15 | #pragma warning(disable:4201)
16 | #endif
17 |
18 | //> Enums corresponding to SystemZ condition codes
19 | typedef enum sysz_cc {
20 | SYSZ_CC_INVALID = 0, // invalid CC (default)
21 |
22 | SYSZ_CC_O,
23 | SYSZ_CC_H,
24 | SYSZ_CC_NLE,
25 | SYSZ_CC_L,
26 | SYSZ_CC_NHE,
27 | SYSZ_CC_LH,
28 | SYSZ_CC_NE,
29 | SYSZ_CC_E,
30 | SYSZ_CC_NLH,
31 | SYSZ_CC_HE,
32 | SYSZ_CC_NL,
33 | SYSZ_CC_LE,
34 | SYSZ_CC_NH,
35 | SYSZ_CC_NO,
36 | } sysz_cc;
37 |
38 | //> Operand type for instruction's operands
39 | typedef enum sysz_op_type {
40 | SYSZ_OP_INVALID = 0, // = CS_OP_INVALID (Uninitialized).
41 | SYSZ_OP_REG, // = CS_OP_REG (Register operand).
42 | SYSZ_OP_IMM, // = CS_OP_IMM (Immediate operand).
43 | SYSZ_OP_MEM, // = CS_OP_MEM (Memory operand).
44 | SYSZ_OP_ACREG = 64, // Access register operand.
45 | } sysz_op_type;
46 |
47 | // Instruction's operand referring to memory
48 | // This is associated with SYSZ_OP_MEM operand type above
49 | typedef struct sysz_op_mem {
50 | uint8_t base; // base register
51 | uint8_t index; // index register
52 | uint64_t length; // BDLAddr operand
53 | int64_t disp; // displacement/offset value
54 | } sysz_op_mem;
55 |
56 | // Instruction operand
57 | typedef struct cs_sysz_op {
58 | sysz_op_type type; // operand type
59 | union {
60 | unsigned int reg; // register value for REG operand
61 | int64_t imm; // immediate value for IMM operand
62 | sysz_op_mem mem; // base/disp value for MEM operand
63 | };
64 | } cs_sysz_op;
65 |
66 | // Instruction structure
67 | typedef struct cs_sysz {
68 | sysz_cc cc; // Code condition
69 | // Number of operands of this instruction,
70 | // or 0 when instruction has no operand.
71 | uint8_t op_count;
72 | cs_sysz_op operands[6]; // operands for this instruction.
73 | } cs_sysz;
74 |
75 | //> SystemZ registers
76 | typedef enum sysz_reg {
77 | SYSZ_REG_INVALID = 0,
78 |
79 | SYSZ_REG_0,
80 | SYSZ_REG_1,
81 | SYSZ_REG_2,
82 | SYSZ_REG_3,
83 | SYSZ_REG_4,
84 | SYSZ_REG_5,
85 | SYSZ_REG_6,
86 | SYSZ_REG_7,
87 | SYSZ_REG_8,
88 | SYSZ_REG_9,
89 | SYSZ_REG_10,
90 | SYSZ_REG_11,
91 | SYSZ_REG_12,
92 | SYSZ_REG_13,
93 | SYSZ_REG_14,
94 | SYSZ_REG_15,
95 | SYSZ_REG_CC,
96 | SYSZ_REG_F0,
97 | SYSZ_REG_F1,
98 | SYSZ_REG_F2,
99 | SYSZ_REG_F3,
100 | SYSZ_REG_F4,
101 | SYSZ_REG_F5,
102 | SYSZ_REG_F6,
103 | SYSZ_REG_F7,
104 | SYSZ_REG_F8,
105 | SYSZ_REG_F9,
106 | SYSZ_REG_F10,
107 | SYSZ_REG_F11,
108 | SYSZ_REG_F12,
109 | SYSZ_REG_F13,
110 | SYSZ_REG_F14,
111 | SYSZ_REG_F15,
112 |
113 | SYSZ_REG_R0L,
114 |
115 | SYSZ_REG_ENDING,
116 | } sysz_reg;
117 |
118 | //> SystemZ instruction
119 | typedef enum sysz_insn {
120 | SYSZ_INS_INVALID = 0,
121 |
122 | SYSZ_INS_A,
123 | SYSZ_INS_ADB,
124 | SYSZ_INS_ADBR,
125 | SYSZ_INS_AEB,
126 | SYSZ_INS_AEBR,
127 | SYSZ_INS_AFI,
128 | SYSZ_INS_AG,
129 | SYSZ_INS_AGF,
130 | SYSZ_INS_AGFI,
131 | SYSZ_INS_AGFR,
132 | SYSZ_INS_AGHI,
133 | SYSZ_INS_AGHIK,
134 | SYSZ_INS_AGR,
135 | SYSZ_INS_AGRK,
136 | SYSZ_INS_AGSI,
137 | SYSZ_INS_AH,
138 | SYSZ_INS_AHI,
139 | SYSZ_INS_AHIK,
140 | SYSZ_INS_AHY,
141 | SYSZ_INS_AIH,
142 | SYSZ_INS_AL,
143 | SYSZ_INS_ALC,
144 | SYSZ_INS_ALCG,
145 | SYSZ_INS_ALCGR,
146 | SYSZ_INS_ALCR,
147 | SYSZ_INS_ALFI,
148 | SYSZ_INS_ALG,
149 | SYSZ_INS_ALGF,
150 | SYSZ_INS_ALGFI,
151 | SYSZ_INS_ALGFR,
152 | SYSZ_INS_ALGHSIK,
153 | SYSZ_INS_ALGR,
154 | SYSZ_INS_ALGRK,
155 | SYSZ_INS_ALHSIK,
156 | SYSZ_INS_ALR,
157 | SYSZ_INS_ALRK,
158 | SYSZ_INS_ALY,
159 | SYSZ_INS_AR,
160 | SYSZ_INS_ARK,
161 | SYSZ_INS_ASI,
162 | SYSZ_INS_AXBR,
163 | SYSZ_INS_AY,
164 | SYSZ_INS_BCR,
165 | SYSZ_INS_BRC,
166 | SYSZ_INS_BRCL,
167 | SYSZ_INS_CGIJ,
168 | SYSZ_INS_CGRJ,
169 | SYSZ_INS_CIJ,
170 | SYSZ_INS_CLGIJ,
171 | SYSZ_INS_CLGRJ,
172 | SYSZ_INS_CLIJ,
173 | SYSZ_INS_CLRJ,
174 | SYSZ_INS_CRJ,
175 | SYSZ_INS_BER,
176 | SYSZ_INS_JE,
177 | SYSZ_INS_JGE,
178 | SYSZ_INS_LOCE,
179 | SYSZ_INS_LOCGE,
180 | SYSZ_INS_LOCGRE,
181 | SYSZ_INS_LOCRE,
182 | SYSZ_INS_STOCE,
183 | SYSZ_INS_STOCGE,
184 | SYSZ_INS_BHR,
185 | SYSZ_INS_BHER,
186 | SYSZ_INS_JHE,
187 | SYSZ_INS_JGHE,
188 | SYSZ_INS_LOCHE,
189 | SYSZ_INS_LOCGHE,
190 | SYSZ_INS_LOCGRHE,
191 | SYSZ_INS_LOCRHE,
192 | SYSZ_INS_STOCHE,
193 | SYSZ_INS_STOCGHE,
194 | SYSZ_INS_JH,
195 | SYSZ_INS_JGH,
196 | SYSZ_INS_LOCH,
197 | SYSZ_INS_LOCGH,
198 | SYSZ_INS_LOCGRH,
199 | SYSZ_INS_LOCRH,
200 | SYSZ_INS_STOCH,
201 | SYSZ_INS_STOCGH,
202 | SYSZ_INS_CGIJNLH,
203 | SYSZ_INS_CGRJNLH,
204 | SYSZ_INS_CIJNLH,
205 | SYSZ_INS_CLGIJNLH,
206 | SYSZ_INS_CLGRJNLH,
207 | SYSZ_INS_CLIJNLH,
208 | SYSZ_INS_CLRJNLH,
209 | SYSZ_INS_CRJNLH,
210 | SYSZ_INS_CGIJE,
211 | SYSZ_INS_CGRJE,
212 | SYSZ_INS_CIJE,
213 | SYSZ_INS_CLGIJE,
214 | SYSZ_INS_CLGRJE,
215 | SYSZ_INS_CLIJE,
216 | SYSZ_INS_CLRJE,
217 | SYSZ_INS_CRJE,
218 | SYSZ_INS_CGIJNLE,
219 | SYSZ_INS_CGRJNLE,
220 | SYSZ_INS_CIJNLE,
221 | SYSZ_INS_CLGIJNLE,
222 | SYSZ_INS_CLGRJNLE,
223 | SYSZ_INS_CLIJNLE,
224 | SYSZ_INS_CLRJNLE,
225 | SYSZ_INS_CRJNLE,
226 | SYSZ_INS_CGIJH,
227 | SYSZ_INS_CGRJH,
228 | SYSZ_INS_CIJH,
229 | SYSZ_INS_CLGIJH,
230 | SYSZ_INS_CLGRJH,
231 | SYSZ_INS_CLIJH,
232 | SYSZ_INS_CLRJH,
233 | SYSZ_INS_CRJH,
234 | SYSZ_INS_CGIJNL,
235 | SYSZ_INS_CGRJNL,
236 | SYSZ_INS_CIJNL,
237 | SYSZ_INS_CLGIJNL,
238 | SYSZ_INS_CLGRJNL,
239 | SYSZ_INS_CLIJNL,
240 | SYSZ_INS_CLRJNL,
241 | SYSZ_INS_CRJNL,
242 | SYSZ_INS_CGIJHE,
243 | SYSZ_INS_CGRJHE,
244 | SYSZ_INS_CIJHE,
245 | SYSZ_INS_CLGIJHE,
246 | SYSZ_INS_CLGRJHE,
247 | SYSZ_INS_CLIJHE,
248 | SYSZ_INS_CLRJHE,
249 | SYSZ_INS_CRJHE,
250 | SYSZ_INS_CGIJNHE,
251 | SYSZ_INS_CGRJNHE,
252 | SYSZ_INS_CIJNHE,
253 | SYSZ_INS_CLGIJNHE,
254 | SYSZ_INS_CLGRJNHE,
255 | SYSZ_INS_CLIJNHE,
256 | SYSZ_INS_CLRJNHE,
257 | SYSZ_INS_CRJNHE,
258 | SYSZ_INS_CGIJL,
259 | SYSZ_INS_CGRJL,
260 | SYSZ_INS_CIJL,
261 | SYSZ_INS_CLGIJL,
262 | SYSZ_INS_CLGRJL,
263 | SYSZ_INS_CLIJL,
264 | SYSZ_INS_CLRJL,
265 | SYSZ_INS_CRJL,
266 | SYSZ_INS_CGIJNH,
267 | SYSZ_INS_CGRJNH,
268 | SYSZ_INS_CIJNH,
269 | SYSZ_INS_CLGIJNH,
270 | SYSZ_INS_CLGRJNH,
271 | SYSZ_INS_CLIJNH,
272 | SYSZ_INS_CLRJNH,
273 | SYSZ_INS_CRJNH,
274 | SYSZ_INS_CGIJLE,
275 | SYSZ_INS_CGRJLE,
276 | SYSZ_INS_CIJLE,
277 | SYSZ_INS_CLGIJLE,
278 | SYSZ_INS_CLGRJLE,
279 | SYSZ_INS_CLIJLE,
280 | SYSZ_INS_CLRJLE,
281 | SYSZ_INS_CRJLE,
282 | SYSZ_INS_CGIJNE,
283 | SYSZ_INS_CGRJNE,
284 | SYSZ_INS_CIJNE,
285 | SYSZ_INS_CLGIJNE,
286 | SYSZ_INS_CLGRJNE,
287 | SYSZ_INS_CLIJNE,
288 | SYSZ_INS_CLRJNE,
289 | SYSZ_INS_CRJNE,
290 | SYSZ_INS_CGIJLH,
291 | SYSZ_INS_CGRJLH,
292 | SYSZ_INS_CIJLH,
293 | SYSZ_INS_CLGIJLH,
294 | SYSZ_INS_CLGRJLH,
295 | SYSZ_INS_CLIJLH,
296 | SYSZ_INS_CLRJLH,
297 | SYSZ_INS_CRJLH,
298 | SYSZ_INS_BLR,
299 | SYSZ_INS_BLER,
300 | SYSZ_INS_JLE,
301 | SYSZ_INS_JGLE,
302 | SYSZ_INS_LOCLE,
303 | SYSZ_INS_LOCGLE,
304 | SYSZ_INS_LOCGRLE,
305 | SYSZ_INS_LOCRLE,
306 | SYSZ_INS_STOCLE,
307 | SYSZ_INS_STOCGLE,
308 | SYSZ_INS_BLHR,
309 | SYSZ_INS_JLH,
310 | SYSZ_INS_JGLH,
311 | SYSZ_INS_LOCLH,
312 | SYSZ_INS_LOCGLH,
313 | SYSZ_INS_LOCGRLH,
314 | SYSZ_INS_LOCRLH,
315 | SYSZ_INS_STOCLH,
316 | SYSZ_INS_STOCGLH,
317 | SYSZ_INS_JL,
318 | SYSZ_INS_JGL,
319 | SYSZ_INS_LOCL,
320 | SYSZ_INS_LOCGL,
321 | SYSZ_INS_LOCGRL,
322 | SYSZ_INS_LOCRL,
323 | SYSZ_INS_LOC,
324 | SYSZ_INS_LOCG,
325 | SYSZ_INS_LOCGR,
326 | SYSZ_INS_LOCR,
327 | SYSZ_INS_STOCL,
328 | SYSZ_INS_STOCGL,
329 | SYSZ_INS_BNER,
330 | SYSZ_INS_JNE,
331 | SYSZ_INS_JGNE,
332 | SYSZ_INS_LOCNE,
333 | SYSZ_INS_LOCGNE,
334 | SYSZ_INS_LOCGRNE,
335 | SYSZ_INS_LOCRNE,
336 | SYSZ_INS_STOCNE,
337 | SYSZ_INS_STOCGNE,
338 | SYSZ_INS_BNHR,
339 | SYSZ_INS_BNHER,
340 | SYSZ_INS_JNHE,
341 | SYSZ_INS_JGNHE,
342 | SYSZ_INS_LOCNHE,
343 | SYSZ_INS_LOCGNHE,
344 | SYSZ_INS_LOCGRNHE,
345 | SYSZ_INS_LOCRNHE,
346 | SYSZ_INS_STOCNHE,
347 | SYSZ_INS_STOCGNHE,
348 | SYSZ_INS_JNH,
349 | SYSZ_INS_JGNH,
350 | SYSZ_INS_LOCNH,
351 | SYSZ_INS_LOCGNH,
352 | SYSZ_INS_LOCGRNH,
353 | SYSZ_INS_LOCRNH,
354 | SYSZ_INS_STOCNH,
355 | SYSZ_INS_STOCGNH,
356 | SYSZ_INS_BNLR,
357 | SYSZ_INS_BNLER,
358 | SYSZ_INS_JNLE,
359 | SYSZ_INS_JGNLE,
360 | SYSZ_INS_LOCNLE,
361 | SYSZ_INS_LOCGNLE,
362 | SYSZ_INS_LOCGRNLE,
363 | SYSZ_INS_LOCRNLE,
364 | SYSZ_INS_STOCNLE,
365 | SYSZ_INS_STOCGNLE,
366 | SYSZ_INS_BNLHR,
367 | SYSZ_INS_JNLH,
368 | SYSZ_INS_JGNLH,
369 | SYSZ_INS_LOCNLH,
370 | SYSZ_INS_LOCGNLH,
371 | SYSZ_INS_LOCGRNLH,
372 | SYSZ_INS_LOCRNLH,
373 | SYSZ_INS_STOCNLH,
374 | SYSZ_INS_STOCGNLH,
375 | SYSZ_INS_JNL,
376 | SYSZ_INS_JGNL,
377 | SYSZ_INS_LOCNL,
378 | SYSZ_INS_LOCGNL,
379 | SYSZ_INS_LOCGRNL,
380 | SYSZ_INS_LOCRNL,
381 | SYSZ_INS_STOCNL,
382 | SYSZ_INS_STOCGNL,
383 | SYSZ_INS_BNOR,
384 | SYSZ_INS_JNO,
385 | SYSZ_INS_JGNO,
386 | SYSZ_INS_LOCNO,
387 | SYSZ_INS_LOCGNO,
388 | SYSZ_INS_LOCGRNO,
389 | SYSZ_INS_LOCRNO,
390 | SYSZ_INS_STOCNO,
391 | SYSZ_INS_STOCGNO,
392 | SYSZ_INS_BOR,
393 | SYSZ_INS_JO,
394 | SYSZ_INS_JGO,
395 | SYSZ_INS_LOCO,
396 | SYSZ_INS_LOCGO,
397 | SYSZ_INS_LOCGRO,
398 | SYSZ_INS_LOCRO,
399 | SYSZ_INS_STOCO,
400 | SYSZ_INS_STOCGO,
401 | SYSZ_INS_STOC,
402 | SYSZ_INS_STOCG,
403 | SYSZ_INS_BASR,
404 | SYSZ_INS_BR,
405 | SYSZ_INS_BRAS,
406 | SYSZ_INS_BRASL,
407 | SYSZ_INS_J,
408 | SYSZ_INS_JG,
409 | SYSZ_INS_BRCT,
410 | SYSZ_INS_BRCTG,
411 | SYSZ_INS_C,
412 | SYSZ_INS_CDB,
413 | SYSZ_INS_CDBR,
414 | SYSZ_INS_CDFBR,
415 | SYSZ_INS_CDGBR,
416 | SYSZ_INS_CDLFBR,
417 | SYSZ_INS_CDLGBR,
418 | SYSZ_INS_CEB,
419 | SYSZ_INS_CEBR,
420 | SYSZ_INS_CEFBR,
421 | SYSZ_INS_CEGBR,
422 | SYSZ_INS_CELFBR,
423 | SYSZ_INS_CELGBR,
424 | SYSZ_INS_CFDBR,
425 | SYSZ_INS_CFEBR,
426 | SYSZ_INS_CFI,
427 | SYSZ_INS_CFXBR,
428 | SYSZ_INS_CG,
429 | SYSZ_INS_CGDBR,
430 | SYSZ_INS_CGEBR,
431 | SYSZ_INS_CGF,
432 | SYSZ_INS_CGFI,
433 | SYSZ_INS_CGFR,
434 | SYSZ_INS_CGFRL,
435 | SYSZ_INS_CGH,
436 | SYSZ_INS_CGHI,
437 | SYSZ_INS_CGHRL,
438 | SYSZ_INS_CGHSI,
439 | SYSZ_INS_CGR,
440 | SYSZ_INS_CGRL,
441 | SYSZ_INS_CGXBR,
442 | SYSZ_INS_CH,
443 | SYSZ_INS_CHF,
444 | SYSZ_INS_CHHSI,
445 | SYSZ_INS_CHI,
446 | SYSZ_INS_CHRL,
447 | SYSZ_INS_CHSI,
448 | SYSZ_INS_CHY,
449 | SYSZ_INS_CIH,
450 | SYSZ_INS_CL,
451 | SYSZ_INS_CLC,
452 | SYSZ_INS_CLFDBR,
453 | SYSZ_INS_CLFEBR,
454 | SYSZ_INS_CLFHSI,
455 | SYSZ_INS_CLFI,
456 | SYSZ_INS_CLFXBR,
457 | SYSZ_INS_CLG,
458 | SYSZ_INS_CLGDBR,
459 | SYSZ_INS_CLGEBR,
460 | SYSZ_INS_CLGF,
461 | SYSZ_INS_CLGFI,
462 | SYSZ_INS_CLGFR,
463 | SYSZ_INS_CLGFRL,
464 | SYSZ_INS_CLGHRL,
465 | SYSZ_INS_CLGHSI,
466 | SYSZ_INS_CLGR,
467 | SYSZ_INS_CLGRL,
468 | SYSZ_INS_CLGXBR,
469 | SYSZ_INS_CLHF,
470 | SYSZ_INS_CLHHSI,
471 | SYSZ_INS_CLHRL,
472 | SYSZ_INS_CLI,
473 | SYSZ_INS_CLIH,
474 | SYSZ_INS_CLIY,
475 | SYSZ_INS_CLR,
476 | SYSZ_INS_CLRL,
477 | SYSZ_INS_CLST,
478 | SYSZ_INS_CLY,
479 | SYSZ_INS_CPSDR,
480 | SYSZ_INS_CR,
481 | SYSZ_INS_CRL,
482 | SYSZ_INS_CS,
483 | SYSZ_INS_CSG,
484 | SYSZ_INS_CSY,
485 | SYSZ_INS_CXBR,
486 | SYSZ_INS_CXFBR,
487 | SYSZ_INS_CXGBR,
488 | SYSZ_INS_CXLFBR,
489 | SYSZ_INS_CXLGBR,
490 | SYSZ_INS_CY,
491 | SYSZ_INS_DDB,
492 | SYSZ_INS_DDBR,
493 | SYSZ_INS_DEB,
494 | SYSZ_INS_DEBR,
495 | SYSZ_INS_DL,
496 | SYSZ_INS_DLG,
497 | SYSZ_INS_DLGR,
498 | SYSZ_INS_DLR,
499 | SYSZ_INS_DSG,
500 | SYSZ_INS_DSGF,
501 | SYSZ_INS_DSGFR,
502 | SYSZ_INS_DSGR,
503 | SYSZ_INS_DXBR,
504 | SYSZ_INS_EAR,
505 | SYSZ_INS_FIDBR,
506 | SYSZ_INS_FIDBRA,
507 | SYSZ_INS_FIEBR,
508 | SYSZ_INS_FIEBRA,
509 | SYSZ_INS_FIXBR,
510 | SYSZ_INS_FIXBRA,
511 | SYSZ_INS_FLOGR,
512 | SYSZ_INS_IC,
513 | SYSZ_INS_ICY,
514 | SYSZ_INS_IIHF,
515 | SYSZ_INS_IIHH,
516 | SYSZ_INS_IIHL,
517 | SYSZ_INS_IILF,
518 | SYSZ_INS_IILH,
519 | SYSZ_INS_IILL,
520 | SYSZ_INS_IPM,
521 | SYSZ_INS_L,
522 | SYSZ_INS_LA,
523 | SYSZ_INS_LAA,
524 | SYSZ_INS_LAAG,
525 | SYSZ_INS_LAAL,
526 | SYSZ_INS_LAALG,
527 | SYSZ_INS_LAN,
528 | SYSZ_INS_LANG,
529 | SYSZ_INS_LAO,
530 | SYSZ_INS_LAOG,
531 | SYSZ_INS_LARL,
532 | SYSZ_INS_LAX,
533 | SYSZ_INS_LAXG,
534 | SYSZ_INS_LAY,
535 | SYSZ_INS_LB,
536 | SYSZ_INS_LBH,
537 | SYSZ_INS_LBR,
538 | SYSZ_INS_LCDBR,
539 | SYSZ_INS_LCEBR,
540 | SYSZ_INS_LCGFR,
541 | SYSZ_INS_LCGR,
542 | SYSZ_INS_LCR,
543 | SYSZ_INS_LCXBR,
544 | SYSZ_INS_LD,
545 | SYSZ_INS_LDEB,
546 | SYSZ_INS_LDEBR,
547 | SYSZ_INS_LDGR,
548 | SYSZ_INS_LDR,
549 | SYSZ_INS_LDXBR,
550 | SYSZ_INS_LDXBRA,
551 | SYSZ_INS_LDY,
552 | SYSZ_INS_LE,
553 | SYSZ_INS_LEDBR,
554 | SYSZ_INS_LEDBRA,
555 | SYSZ_INS_LER,
556 | SYSZ_INS_LEXBR,
557 | SYSZ_INS_LEXBRA,
558 | SYSZ_INS_LEY,
559 | SYSZ_INS_LFH,
560 | SYSZ_INS_LG,
561 | SYSZ_INS_LGB,
562 | SYSZ_INS_LGBR,
563 | SYSZ_INS_LGDR,
564 | SYSZ_INS_LGF,
565 | SYSZ_INS_LGFI,
566 | SYSZ_INS_LGFR,
567 | SYSZ_INS_LGFRL,
568 | SYSZ_INS_LGH,
569 | SYSZ_INS_LGHI,
570 | SYSZ_INS_LGHR,
571 | SYSZ_INS_LGHRL,
572 | SYSZ_INS_LGR,
573 | SYSZ_INS_LGRL,
574 | SYSZ_INS_LH,
575 | SYSZ_INS_LHH,
576 | SYSZ_INS_LHI,
577 | SYSZ_INS_LHR,
578 | SYSZ_INS_LHRL,
579 | SYSZ_INS_LHY,
580 | SYSZ_INS_LLC,
581 | SYSZ_INS_LLCH,
582 | SYSZ_INS_LLCR,
583 | SYSZ_INS_LLGC,
584 | SYSZ_INS_LLGCR,
585 | SYSZ_INS_LLGF,
586 | SYSZ_INS_LLGFR,
587 | SYSZ_INS_LLGFRL,
588 | SYSZ_INS_LLGH,
589 | SYSZ_INS_LLGHR,
590 | SYSZ_INS_LLGHRL,
591 | SYSZ_INS_LLH,
592 | SYSZ_INS_LLHH,
593 | SYSZ_INS_LLHR,
594 | SYSZ_INS_LLHRL,
595 | SYSZ_INS_LLIHF,
596 | SYSZ_INS_LLIHH,
597 | SYSZ_INS_LLIHL,
598 | SYSZ_INS_LLILF,
599 | SYSZ_INS_LLILH,
600 | SYSZ_INS_LLILL,
601 | SYSZ_INS_LMG,
602 | SYSZ_INS_LNDBR,
603 | SYSZ_INS_LNEBR,
604 | SYSZ_INS_LNGFR,
605 | SYSZ_INS_LNGR,
606 | SYSZ_INS_LNR,
607 | SYSZ_INS_LNXBR,
608 | SYSZ_INS_LPDBR,
609 | SYSZ_INS_LPEBR,
610 | SYSZ_INS_LPGFR,
611 | SYSZ_INS_LPGR,
612 | SYSZ_INS_LPR,
613 | SYSZ_INS_LPXBR,
614 | SYSZ_INS_LR,
615 | SYSZ_INS_LRL,
616 | SYSZ_INS_LRV,
617 | SYSZ_INS_LRVG,
618 | SYSZ_INS_LRVGR,
619 | SYSZ_INS_LRVR,
620 | SYSZ_INS_LT,
621 | SYSZ_INS_LTDBR,
622 | SYSZ_INS_LTEBR,
623 | SYSZ_INS_LTG,
624 | SYSZ_INS_LTGF,
625 | SYSZ_INS_LTGFR,
626 | SYSZ_INS_LTGR,
627 | SYSZ_INS_LTR,
628 | SYSZ_INS_LTXBR,
629 | SYSZ_INS_LXDB,
630 | SYSZ_INS_LXDBR,
631 | SYSZ_INS_LXEB,
632 | SYSZ_INS_LXEBR,
633 | SYSZ_INS_LXR,
634 | SYSZ_INS_LY,
635 | SYSZ_INS_LZDR,
636 | SYSZ_INS_LZER,
637 | SYSZ_INS_LZXR,
638 | SYSZ_INS_MADB,
639 | SYSZ_INS_MADBR,
640 | SYSZ_INS_MAEB,
641 | SYSZ_INS_MAEBR,
642 | SYSZ_INS_MDB,
643 | SYSZ_INS_MDBR,
644 | SYSZ_INS_MDEB,
645 | SYSZ_INS_MDEBR,
646 | SYSZ_INS_MEEB,
647 | SYSZ_INS_MEEBR,
648 | SYSZ_INS_MGHI,
649 | SYSZ_INS_MH,
650 | SYSZ_INS_MHI,
651 | SYSZ_INS_MHY,
652 | SYSZ_INS_MLG,
653 | SYSZ_INS_MLGR,
654 | SYSZ_INS_MS,
655 | SYSZ_INS_MSDB,
656 | SYSZ_INS_MSDBR,
657 | SYSZ_INS_MSEB,
658 | SYSZ_INS_MSEBR,
659 | SYSZ_INS_MSFI,
660 | SYSZ_INS_MSG,
661 | SYSZ_INS_MSGF,
662 | SYSZ_INS_MSGFI,
663 | SYSZ_INS_MSGFR,
664 | SYSZ_INS_MSGR,
665 | SYSZ_INS_MSR,
666 | SYSZ_INS_MSY,
667 | SYSZ_INS_MVC,
668 | SYSZ_INS_MVGHI,
669 | SYSZ_INS_MVHHI,
670 | SYSZ_INS_MVHI,
671 | SYSZ_INS_MVI,
672 | SYSZ_INS_MVIY,
673 | SYSZ_INS_MVST,
674 | SYSZ_INS_MXBR,
675 | SYSZ_INS_MXDB,
676 | SYSZ_INS_MXDBR,
677 | SYSZ_INS_N,
678 | SYSZ_INS_NC,
679 | SYSZ_INS_NG,
680 | SYSZ_INS_NGR,
681 | SYSZ_INS_NGRK,
682 | SYSZ_INS_NI,
683 | SYSZ_INS_NIHF,
684 | SYSZ_INS_NIHH,
685 | SYSZ_INS_NIHL,
686 | SYSZ_INS_NILF,
687 | SYSZ_INS_NILH,
688 | SYSZ_INS_NILL,
689 | SYSZ_INS_NIY,
690 | SYSZ_INS_NR,
691 | SYSZ_INS_NRK,
692 | SYSZ_INS_NY,
693 | SYSZ_INS_O,
694 | SYSZ_INS_OC,
695 | SYSZ_INS_OG,
696 | SYSZ_INS_OGR,
697 | SYSZ_INS_OGRK,
698 | SYSZ_INS_OI,
699 | SYSZ_INS_OIHF,
700 | SYSZ_INS_OIHH,
701 | SYSZ_INS_OIHL,
702 | SYSZ_INS_OILF,
703 | SYSZ_INS_OILH,
704 | SYSZ_INS_OILL,
705 | SYSZ_INS_OIY,
706 | SYSZ_INS_OR,
707 | SYSZ_INS_ORK,
708 | SYSZ_INS_OY,
709 | SYSZ_INS_PFD,
710 | SYSZ_INS_PFDRL,
711 | SYSZ_INS_RISBG,
712 | SYSZ_INS_RISBHG,
713 | SYSZ_INS_RISBLG,
714 | SYSZ_INS_RLL,
715 | SYSZ_INS_RLLG,
716 | SYSZ_INS_RNSBG,
717 | SYSZ_INS_ROSBG,
718 | SYSZ_INS_RXSBG,
719 | SYSZ_INS_S,
720 | SYSZ_INS_SDB,
721 | SYSZ_INS_SDBR,
722 | SYSZ_INS_SEB,
723 | SYSZ_INS_SEBR,
724 | SYSZ_INS_SG,
725 | SYSZ_INS_SGF,
726 | SYSZ_INS_SGFR,
727 | SYSZ_INS_SGR,
728 | SYSZ_INS_SGRK,
729 | SYSZ_INS_SH,
730 | SYSZ_INS_SHY,
731 | SYSZ_INS_SL,
732 | SYSZ_INS_SLB,
733 | SYSZ_INS_SLBG,
734 | SYSZ_INS_SLBR,
735 | SYSZ_INS_SLFI,
736 | SYSZ_INS_SLG,
737 | SYSZ_INS_SLBGR,
738 | SYSZ_INS_SLGF,
739 | SYSZ_INS_SLGFI,
740 | SYSZ_INS_SLGFR,
741 | SYSZ_INS_SLGR,
742 | SYSZ_INS_SLGRK,
743 | SYSZ_INS_SLL,
744 | SYSZ_INS_SLLG,
745 | SYSZ_INS_SLLK,
746 | SYSZ_INS_SLR,
747 | SYSZ_INS_SLRK,
748 | SYSZ_INS_SLY,
749 | SYSZ_INS_SQDB,
750 | SYSZ_INS_SQDBR,
751 | SYSZ_INS_SQEB,
752 | SYSZ_INS_SQEBR,
753 | SYSZ_INS_SQXBR,
754 | SYSZ_INS_SR,
755 | SYSZ_INS_SRA,
756 | SYSZ_INS_SRAG,
757 | SYSZ_INS_SRAK,
758 | SYSZ_INS_SRK,
759 | SYSZ_INS_SRL,
760 | SYSZ_INS_SRLG,
761 | SYSZ_INS_SRLK,
762 | SYSZ_INS_SRST,
763 | SYSZ_INS_ST,
764 | SYSZ_INS_STC,
765 | SYSZ_INS_STCH,
766 | SYSZ_INS_STCY,
767 | SYSZ_INS_STD,
768 | SYSZ_INS_STDY,
769 | SYSZ_INS_STE,
770 | SYSZ_INS_STEY,
771 | SYSZ_INS_STFH,
772 | SYSZ_INS_STG,
773 | SYSZ_INS_STGRL,
774 | SYSZ_INS_STH,
775 | SYSZ_INS_STHH,
776 | SYSZ_INS_STHRL,
777 | SYSZ_INS_STHY,
778 | SYSZ_INS_STMG,
779 | SYSZ_INS_STRL,
780 | SYSZ_INS_STRV,
781 | SYSZ_INS_STRVG,
782 | SYSZ_INS_STY,
783 | SYSZ_INS_SXBR,
784 | SYSZ_INS_SY,
785 | SYSZ_INS_TM,
786 | SYSZ_INS_TMHH,
787 | SYSZ_INS_TMHL,
788 | SYSZ_INS_TMLH,
789 | SYSZ_INS_TMLL,
790 | SYSZ_INS_TMY,
791 | SYSZ_INS_X,
792 | SYSZ_INS_XC,
793 | SYSZ_INS_XG,
794 | SYSZ_INS_XGR,
795 | SYSZ_INS_XGRK,
796 | SYSZ_INS_XI,
797 | SYSZ_INS_XIHF,
798 | SYSZ_INS_XILF,
799 | SYSZ_INS_XIY,
800 | SYSZ_INS_XR,
801 | SYSZ_INS_XRK,
802 | SYSZ_INS_XY,
803 |
804 | SYSZ_INS_ENDING, // <-- mark the end of the list of instructions
805 | } sysz_insn;
806 |
807 | //> Group of SystemZ instructions
808 | typedef enum sysz_insn_group {
809 | SYSZ_GRP_INVALID = 0, // = CS_GRP_INVALID
810 |
811 | //> Generic groups
812 | // all jump instructions (conditional+direct+indirect jumps)
813 | SYSZ_GRP_JUMP, // = CS_GRP_JUMP
814 |
815 | //> Architecture-specific groups
816 | SYSZ_GRP_DISTINCTOPS = 128,
817 | SYSZ_GRP_FPEXTENSION,
818 | SYSZ_GRP_HIGHWORD,
819 | SYSZ_GRP_INTERLOCKEDACCESS1,
820 | SYSZ_GRP_LOADSTOREONCOND,
821 |
822 | SYSZ_GRP_ENDING, // <-- mark the end of the list of groups
823 | } sysz_insn_group;
824 |
825 | #ifdef __cplusplus
826 | }
827 | #endif
828 |
829 | #endif
830 |
--------------------------------------------------------------------------------
/capstone-3.0.4-win32/include/xcore.h:
--------------------------------------------------------------------------------
1 | #ifndef CAPSTONE_XCORE_H
2 | #define CAPSTONE_XCORE_H
3 |
4 | /* Capstone Disassembly Engine */
5 | /* By Nguyen Anh Quynh , 2014 */
6 |
7 | #ifdef __cplusplus
8 | extern "C" {
9 | #endif
10 |
11 | #include
12 | #include "platform.h"
13 |
14 | #ifdef _MSC_VER
15 | #pragma warning(disable:4201)
16 | #endif
17 |
18 | //> Operand type for instruction's operands
19 | typedef enum xcore_op_type {
20 | XCORE_OP_INVALID = 0, // = CS_OP_INVALID (Uninitialized).
21 | XCORE_OP_REG, // = CS_OP_REG (Register operand).
22 | XCORE_OP_IMM, // = CS_OP_IMM (Immediate operand).
23 | XCORE_OP_MEM, // = CS_OP_MEM (Memory operand).
24 | } xcore_op_type;
25 |
26 | // Instruction's operand referring to memory
27 | // This is associated with XCORE_OP_MEM operand type above
28 | typedef struct xcore_op_mem {
29 | uint8_t base; // base register
30 | uint8_t index; // index register
31 | int32_t disp; // displacement/offset value
32 | int direct; // +1: forward, -1: backward
33 | } xcore_op_mem;
34 |
35 | // Instruction operand
36 | typedef struct cs_xcore_op {
37 | xcore_op_type type; // operand type
38 | union {
39 | unsigned int reg; // register value for REG operand
40 | int32_t imm; // immediate value for IMM operand
41 | xcore_op_mem mem; // base/disp value for MEM operand
42 | };
43 | } cs_xcore_op;
44 |
45 | // Instruction structure
46 | typedef struct cs_xcore {
47 | // Number of operands of this instruction,
48 | // or 0 when instruction has no operand.
49 | uint8_t op_count;
50 | cs_xcore_op operands[8]; // operands for this instruction.
51 | } cs_xcore;
52 |
53 | //> XCore registers
54 | typedef enum xcore_reg {
55 | XCORE_REG_INVALID = 0,
56 |
57 | XCORE_REG_CP,
58 | XCORE_REG_DP,
59 | XCORE_REG_LR,
60 | XCORE_REG_SP,
61 | XCORE_REG_R0,
62 | XCORE_REG_R1,
63 | XCORE_REG_R2,
64 | XCORE_REG_R3,
65 | XCORE_REG_R4,
66 | XCORE_REG_R5,
67 | XCORE_REG_R6,
68 | XCORE_REG_R7,
69 | XCORE_REG_R8,
70 | XCORE_REG_R9,
71 | XCORE_REG_R10,
72 | XCORE_REG_R11,
73 |
74 | //> pseudo registers
75 | XCORE_REG_PC, // pc
76 |
77 | // internal thread registers
78 | // see The-XMOS-XS1-Architecture(X7879A).pdf
79 | XCORE_REG_SCP, // save pc
80 | XCORE_REG_SSR, // save status
81 | XCORE_REG_ET, // exception type
82 | XCORE_REG_ED, // exception data
83 | XCORE_REG_SED, // save exception data
84 | XCORE_REG_KEP, // kernel entry pointer
85 | XCORE_REG_KSP, // kernel stack pointer
86 | XCORE_REG_ID, // thread ID
87 |
88 | XCORE_REG_ENDING, // <-- mark the end of the list of registers
89 | } xcore_reg;
90 |
91 | //> XCore instruction
92 | typedef enum xcore_insn {
93 | XCORE_INS_INVALID = 0,
94 |
95 | XCORE_INS_ADD,
96 | XCORE_INS_ANDNOT,
97 | XCORE_INS_AND,
98 | XCORE_INS_ASHR,
99 | XCORE_INS_BAU,
100 | XCORE_INS_BITREV,
101 | XCORE_INS_BLA,
102 | XCORE_INS_BLAT,
103 | XCORE_INS_BL,
104 | XCORE_INS_BF,
105 | XCORE_INS_BT,
106 | XCORE_INS_BU,
107 | XCORE_INS_BRU,
108 | XCORE_INS_BYTEREV,
109 | XCORE_INS_CHKCT,
110 | XCORE_INS_CLRE,
111 | XCORE_INS_CLRPT,
112 | XCORE_INS_CLRSR,
113 | XCORE_INS_CLZ,
114 | XCORE_INS_CRC8,
115 | XCORE_INS_CRC32,
116 | XCORE_INS_DCALL,
117 | XCORE_INS_DENTSP,
118 | XCORE_INS_DGETREG,
119 | XCORE_INS_DIVS,
120 | XCORE_INS_DIVU,
121 | XCORE_INS_DRESTSP,
122 | XCORE_INS_DRET,
123 | XCORE_INS_ECALLF,
124 | XCORE_INS_ECALLT,
125 | XCORE_INS_EDU,
126 | XCORE_INS_EEF,
127 | XCORE_INS_EET,
128 | XCORE_INS_EEU,
129 | XCORE_INS_ENDIN,
130 | XCORE_INS_ENTSP,
131 | XCORE_INS_EQ,
132 | XCORE_INS_EXTDP,
133 | XCORE_INS_EXTSP,
134 | XCORE_INS_FREER,
135 | XCORE_INS_FREET,
136 | XCORE_INS_GETD,
137 | XCORE_INS_GET,
138 | XCORE_INS_GETN,
139 | XCORE_INS_GETR,
140 | XCORE_INS_GETSR,
141 | XCORE_INS_GETST,
142 | XCORE_INS_GETTS,
143 | XCORE_INS_INCT,
144 | XCORE_INS_INIT,
145 | XCORE_INS_INPW,
146 | XCORE_INS_INSHR,
147 | XCORE_INS_INT,
148 | XCORE_INS_IN,
149 | XCORE_INS_KCALL,
150 | XCORE_INS_KENTSP,
151 | XCORE_INS_KRESTSP,
152 | XCORE_INS_KRET,
153 | XCORE_INS_LADD,
154 | XCORE_INS_LD16S,
155 | XCORE_INS_LD8U,
156 | XCORE_INS_LDA16,
157 | XCORE_INS_LDAP,
158 | XCORE_INS_LDAW,
159 | XCORE_INS_LDC,
160 | XCORE_INS_LDW,
161 | XCORE_INS_LDIVU,
162 | XCORE_INS_LMUL,
163 | XCORE_INS_LSS,
164 | XCORE_INS_LSUB,
165 | XCORE_INS_LSU,
166 | XCORE_INS_MACCS,
167 | XCORE_INS_MACCU,
168 | XCORE_INS_MJOIN,
169 | XCORE_INS_MKMSK,
170 | XCORE_INS_MSYNC,
171 | XCORE_INS_MUL,
172 | XCORE_INS_NEG,
173 | XCORE_INS_NOT,
174 | XCORE_INS_OR,
175 | XCORE_INS_OUTCT,
176 | XCORE_INS_OUTPW,
177 | XCORE_INS_OUTSHR,
178 | XCORE_INS_OUTT,
179 | XCORE_INS_OUT,
180 | XCORE_INS_PEEK,
181 | XCORE_INS_REMS,
182 | XCORE_INS_REMU,
183 | XCORE_INS_RETSP,
184 | XCORE_INS_SETCLK,
185 | XCORE_INS_SET,
186 | XCORE_INS_SETC,
187 | XCORE_INS_SETD,
188 | XCORE_INS_SETEV,
189 | XCORE_INS_SETN,
190 | XCORE_INS_SETPSC,
191 | XCORE_INS_SETPT,
192 | XCORE_INS_SETRDY,
193 | XCORE_INS_SETSR,
194 | XCORE_INS_SETTW,
195 | XCORE_INS_SETV,
196 | XCORE_INS_SEXT,
197 | XCORE_INS_SHL,
198 | XCORE_INS_SHR,
199 | XCORE_INS_SSYNC,
200 | XCORE_INS_ST16,
201 | XCORE_INS_ST8,
202 | XCORE_INS_STW,
203 | XCORE_INS_SUB,
204 | XCORE_INS_SYNCR,
205 | XCORE_INS_TESTCT,
206 | XCORE_INS_TESTLCL,
207 | XCORE_INS_TESTWCT,
208 | XCORE_INS_TSETMR,
209 | XCORE_INS_START,
210 | XCORE_INS_WAITEF,
211 | XCORE_INS_WAITET,
212 | XCORE_INS_WAITEU,
213 | XCORE_INS_XOR,
214 | XCORE_INS_ZEXT,
215 |
216 | XCORE_INS_ENDING, // <-- mark the end of the list of instructions
217 | } xcore_insn;
218 |
219 | //> Group of XCore instructions
220 | typedef enum xcore_insn_group {
221 | XCORE_GRP_INVALID = 0, // = CS_GRP_INVALID
222 |
223 | //> Generic groups
224 | // all jump instructions (conditional+direct+indirect jumps)
225 | XCORE_GRP_JUMP, // = CS_GRP_JUMP
226 |
227 | XCORE_GRP_ENDING, // <-- mark the end of the list of groups
228 | } xcore_insn_group;
229 |
230 | #ifdef __cplusplus
231 | }
232 | #endif
233 |
234 | #endif
235 |
--------------------------------------------------------------------------------
/capstone-3.0.4-win32/test.exe:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/SCUBSRGroup/Taint-Analyse/2f14e5035aa1d03d0a63e1cd2386f7930d8728cf/capstone-3.0.4-win32/test.exe
--------------------------------------------------------------------------------
/capstone.dll:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/SCUBSRGroup/Taint-Analyse/2f14e5035aa1d03d0a63e1cd2386f7930d8728cf/capstone.dll
--------------------------------------------------------------------------------
/cccapstone-master/.gitmodules:
--------------------------------------------------------------------------------
1 | [submodule "capstone"]
2 | path = capstone
3 | url = https://github.com/aquynh/capstone.git
4 | branch = next
5 |
--------------------------------------------------------------------------------
/cccapstone-master/README.md:
--------------------------------------------------------------------------------
1 | cccapstone
2 | ==========
3 |
4 | c++ bindings for capstone disasembly framework (http://www.capstone-engine.org/ - https://github.com/aquynh/capstone)
5 |
6 |
7 | **1. clone all (bindings & capstone as well)**
8 |
9 | git clone --recursive https://github.com/zer0mem/cccapstone.git
10 |
11 | **2. basic settings**
12 |
13 | 1. add to Additional include directories capstone include : $(SolutionDir)/cccapstone/capstone/include
14 |
15 | 2. OPTIONAL (but not mandatory) include c++ bindings to source / header 3rdparty files
16 | > x86 example :
17 | --> \cccapstone\cppbindings\{ CsCapstoneHelper.hh, CsIns.hpp, Disasm.hpp, X86Disasm.hh }
18 | --> \cccapstone\capstone\include\capstone.h
19 |
20 |
21 | **----------------------------------------------------------------------------------------**
22 |
23 | **3. examples**
24 |
25 | https://github.com/zer0mem/KernelProject/blob/capstone/KernelProject/src/CapstoneCppBindingsTest.hpp
26 |
27 | **4. examples by hand (intel x86 - x64)**
28 |
29 | /*
30 | f.e. for arm (vice versa with other architectures) can be
31 | capstone disassembler created in some ways :
32 |
33 | #include
34 |
35 | 1. use predefined wrapper
36 | CArmDisasm64 dis;
37 |
38 | 2. use direct wrapper above c implementation
39 | auto dis = CCsDisasm(
40 | cs_arch::CS_ARCH_ARM64,
41 | cs_mode::CS_MODE_ARM + cs_mode::CS_MODE_BIG_ENDIAN);
42 | */
43 |
44 | CX86Disasm64 dis; // define disasembler by current needs.
45 | // cccapstone/cppbindings/Disasm.hh for more available bindings
46 |
47 | //check if no error occured
48 | if (dis.GetError())
49 | return;
50 |
51 | //set how deep should capstone reverse instruction
52 | dis.SetDetail(cs_opt_value::CS_OPT_ON);
53 |
54 | //set syntax for output disasembly string
55 | dis.SetSyntax(cs_opt_value::CS_OPT_SYNTAX_INTEL);
56 |
57 | //*OPTIONAL* - set callback, when is encountered data - not resolved code -
58 | dis.SetSkipDataCallback(cs_opt_skipdata{
59 | ".UNKOWNBYTES : ",
60 | SkipDataCallback,
61 | nullptr
62 | });
63 |
64 | //for more settings see cccapstone/cppbindings/Disasm.hpp
65 |
66 | //process disasembling
67 | auto insn = dis.Disasm(code, size);
68 | //check if disassembling succesfull
69 | if (!insn.get())
70 | return;
71 |
72 | //print basic info
73 | for (size_t i = 0; i < insn->Count; i++)
74 | printf("-> 0x%p:\t%s\t%s\n",
75 | insn->Instructions(i).address,
76 | insn->Instructions(i).mnemonic,
77 | insn->Instructions(i).op_str);
78 |
79 | //how to gather advanced info is by example in debug-print function
80 | --> print_insn_detail (https://github.com/aquynh/capstone/blob/master/tests/test_x86.c)
81 |
82 | //in future in capstone will be possible also filtering group of instructions (and far more .. :)
83 | if (insn->Instructions(i).IsInInsGroup(x86_insn_group::X86_GRP_JUMP))
84 | printf("\nControl Flow change at : %p", insn->Instructions(i).address);
85 |
86 |
87 |
88 |
--------------------------------------------------------------------------------
/cccapstone-master/cppbindings/ArmDisasm.hh:
--------------------------------------------------------------------------------
1 | #pragma once
2 |
3 | #include "Disasm.hpp"
4 | #include "CsIns.hpp"
5 |
6 | using CArm64InsClass = CCsIns;
7 | using CArmInsClass = CCsIns;
8 |
9 | class CArmDisasm64 :
10 | public CCsDisasm
11 | {
12 | public:
13 | CArmDisasm64(
14 | __in unsigned int mode = cs_mode::CS_MODE_THUMB + cs_mode::CS_MODE_LITTLE_ENDIAN
15 | ) : CCsDisasm(cs_arch::CS_ARCH_ARM64, mode)
16 | {
17 | }
18 | };
19 |
20 | class CArmDisasm :
21 | public CCsDisasm
22 | {
23 | public:
24 | CArmDisasm86(
25 | __in unsigned int mode = cs_mode::CS_MODE_THUMB + cs_mode::CS_MODE_LITTLE_ENDIAN
26 | ) : CCsDisasm(cs_arch::CS_ARCH_ARM, mode)
27 | {
28 | }
29 | };
30 |
--------------------------------------------------------------------------------
/cccapstone-master/cppbindings/CsCapstoneHelper.hh:
--------------------------------------------------------------------------------
1 | #pragma once
2 |
3 | #include
4 | #include
5 |
6 | struct CS_HANDLE :
7 | public std::shared_ptr
8 | {
9 | CS_HANDLE() :
10 | std::shared_ptr(&m_handle, cs_close)
11 | {
12 | }
13 |
14 | private:
15 | csh m_handle;
16 | };
17 |
18 | template
19 | struct CS_INSN_HOLDER
20 | {
21 | size_t Size;
22 | const void* Address;
23 | size_t Count;
24 |
25 | __forceinline
26 | CsInsClass_t
27 | Instructions(
28 | __in size_t i
29 | )
30 | {
31 | return *new CsInsClass_t(m_csh, m_csInstructions + i);
32 | }
33 |
34 | CS_INSN_HOLDER(
35 | __in CS_HANDLE& csh,
36 | __in const void* address,
37 | __in size_t size,
38 | __in size_t baseAddr
39 | ) : m_csh(csh),
40 | Address(address),
41 | Size(size),
42 | m_csInstructions(nullptr)
43 | {
44 | Count = cs_disasm(
45 | *m_csh.get(),
46 | static_cast(address),
47 | size,
48 | baseAddr,
49 | 0,
50 | &m_csInstructions);
51 | }
52 |
53 | ~CS_INSN_HOLDER()
54 | {
55 | if (m_csInstructions)
56 | cs_free(m_csInstructions, Count);
57 | }
58 |
59 | void operator=(CS_INSN_HOLDER const&) = delete;
60 | CS_INSN_HOLDER(const CS_INSN_HOLDER &) = delete;
61 |
62 | protected:
63 | template
64 | friend class CCsDisasm;
65 |
66 | cs_insn* m_csInstructions;
67 | CS_HANDLE m_csh;
68 | };
69 |
--------------------------------------------------------------------------------
/cccapstone-master/cppbindings/CsIns.hpp:
--------------------------------------------------------------------------------
1 | #pragma once
2 |
3 | #include
4 | #include "CsCapstoneHelper.hh"
5 |
6 | //x86_insn_group, x86_reg, x86_op_type, x86_insn
7 | template
8 | class CCsIns
9 | {
10 | CS_HANDLE m_csh;
11 | cs_insn* m_ins;
12 |
13 | void operator=(CCsIns const&) = delete;
14 | //CCsIns(const CCsIns &) = delete;//==> must be kicked out in the future, and CS_HANDLE not shared_ptr .. need redesign ...
15 | public:
16 | CCsIns(
17 | __in CS_HANDLE csh,
18 | __in cs_insn* ins
19 | ) : m_csh(csh),
20 | m_ins(ins)
21 | {
22 | }
23 |
24 | const cs_insn*
25 | operator->() const
26 | {
27 | return m_ins;
28 | }
29 |
30 | __forceinline
31 | bool
32 | IsInInsGroup(
33 | __in InsGroup_t groupId
34 | ) const
35 | {
36 | return cs_insn_group(*m_csh.get(), m_ins, groupId);
37 | }
38 |
39 | __forceinline
40 | bool
41 | RegRead(
42 | __in Reg_t regId
43 | ) const
44 | {
45 | return cs_reg_read(*m_csh.get(), m_ins, regId);
46 | }
47 |
48 | __forceinline
49 | bool
50 | RegWrite(
51 | __in Reg_t regId
52 | ) const
53 | {
54 | return cs_reg_write(*m_csh.get(), m_ins, regId);
55 | }
56 |
57 | __forceinline
58 | int
59 | OpcodeCount(
60 | __in Op_t opType
61 | ) const
62 | {
63 | return cs_op_count(*m_csh.get(), m_ins, opType);
64 | }
65 |
66 | __forceinline
67 | int
68 | OpcodeIndex(
69 | __in Op_t opType,
70 | __in unsigned int opcodePosition = 0
71 | ) const
72 | {
73 | return cs_op_index(*m_csh.get(), m_ins, opType, opcodePosition);
74 | }
75 |
76 | __forceinline
77 | const char*
78 | RegName(
79 | __in Reg_t reg
80 | ) const
81 | {
82 | return cs_reg_name(*m_csh.get(), reg);
83 | }
84 |
85 | __forceinline
86 | const char*
87 | InsName(
88 | __in Ins_t ins
89 | ) const
90 | {
91 | return cs_insn_name(*m_csh.get(), ins);
92 | }
93 |
94 | static
95 | __forceinline
96 | const char*
97 | RegName(
98 | __in csh& cs,
99 | __in Reg_t reg
100 | )
101 | {
102 | return cs_reg_name(cs, reg);
103 | }
104 |
105 | static
106 | __forceinline
107 | const char*
108 | InsName(
109 | __in csh& cs,
110 | __in Ins_t ins
111 | )
112 | {
113 | return cs_insn_name(cs, ins);
114 | }
115 | };
116 |
--------------------------------------------------------------------------------
/cccapstone-master/cppbindings/Disasm.hpp:
--------------------------------------------------------------------------------
1 | #pragma once
2 |
3 | #include "CsCapstoneHelper.hh"
4 |
5 | template
6 | class CCsDisasm
7 | {
8 | protected:
9 | CS_HANDLE m_csh;
10 | cs_err m_err;
11 |
12 | public:
13 | CCsDisasm(
14 | __in cs_arch arch,
15 | __in unsigned int mode
16 | )
17 | {
18 | m_err = cs_open(arch, static_cast(mode), m_csh.get());
19 | }
20 |
21 | typedef CS_INSN_HOLDER ins_holder_t;
22 |
23 | //////////////////////////////////////////////////////////////////////////
24 | // runtime opcode info
25 | //////////////////////////////////////////////////////////////////////////
26 | __forceinline
27 | ins_holder_t*
28 | Disasm(
29 | __in const void* code,
30 | __in size_t size,
31 | __in size_t baseAddr = 0
32 | )
33 | {
34 | return new ins_holder_t(m_csh, code, size, baseAddr);
35 | }
36 |
37 | __forceinline
38 | cs_err
39 | GetError()
40 | {
41 | return m_err;
42 | }
43 |
44 | __forceinline
45 | unsigned int
46 | Version(
47 | __inout int* major = nullptr,
48 | __inout int* minor = nullptr
49 | )
50 | {
51 | return cs_version(major, minor);
52 | }
53 |
54 | __forceinline
55 | static
56 | const char*
57 | ErrToStr(
58 | __in cs_err err
59 | )
60 | {
61 | return cs_strerror(err);
62 | }
63 |
64 | //////////////////////////////////////////////////////////////////////////
65 | // cs capstone engine settings
66 | //////////////////////////////////////////////////////////////////////////
67 |
68 | /*
69 | cs_opt_value::CS_OPT_SYNTAX_DEFAULT = 0, // Default asm syntax (CS_OPT_SYNTAX).
70 | cs_opt_value::CS_OPT_SYNTAX_INTEL, // X86 Intel asm syntax - default on X86 (CS_OPT_SYNTAX).
71 | cs_opt_value::CS_OPT_SYNTAX_ATT, // X86 ATT asm syntax (CS_OPT_SYNTAX).
72 | cs_opt_value::CS_OPT_SYNTAX_NOREGNAME, // Prints register name with only number (CS_OPT_SYNTAX)
73 |
74 | http://capstone-engine.org/lang_c.html
75 | */
76 | __forceinline
77 | __checkReturn
78 | bool
79 | SetSyntax(
80 | __in cs_opt_value syntax
81 | )
82 | {
83 | return !cs_option(*m_csh.get(), cs_opt_type::CS_OPT_SYNTAX, syntax);
84 | }
85 |
86 | /*
87 | How detailed info in included per insn :
88 |
89 | cs_opt_value::CS_OPT_OFF //by default
90 | cs_opt_value::CS_OPT_ON
91 | */
92 | __forceinline
93 | __checkReturn
94 | bool
95 | SetDetail(
96 | __in cs_opt_value detailedInfo
97 | )
98 | {
99 | return !cs_option(*m_csh.get(), cs_opt_type::CS_OPT_DETAIL, detailedInfo);
100 | }
101 |
102 | /*
103 | change mode at runtime :
104 |
105 | cs_mode::CS_MODE_LITTLE_ENDIAN = 0, // little endian mode (default mode)
106 | cs_mode::CS_MODE_ARM = 0, // 32-bit ARM
107 | cs_mode::CS_MODE_16 = 1 << 1, // 16-bit mode
108 | cs_mode::CS_MODE_32 = 1 << 2, // 32-bit mode
109 | cs_mode::CS_MODE_64 = 1 << 3, // 64-bit mode
110 | cs_mode::CS_MODE_THUMB = 1 << 4, // ARM's Thumb mode, including Thumb-2
111 | cs_mode::CS_MODE_MICRO = 1 << 4, // MicroMips mode (MIPS architecture)
112 | cs_mode::CS_MODE_N64 = 1 << 5, // Nintendo-64 mode (MIPS architecture)
113 | cs_mode::CS_MODE_V9 = 1 << 4, // SparcV9 mode (Sparc architecture)
114 | cs_mode::CS_MODE_BIG_ENDIAN = 1 << 31 // big endian mode
115 |
116 | http://capstone-engine.org/lang_c.html
117 | */
118 | __forceinline
119 | __checkReturn
120 | bool
121 | SetMode(
122 | __in cs_mode mode
123 | )
124 | {
125 | return !cs_option(*m_csh.get(), cs_opt_type::CS_OPT_MODE, mode);
126 | }
127 |
128 | /*
129 | possibility to redefining of mem mgr functions :
130 |
131 | void *malloc(size_t size);
132 | void *calloc(size_t nmemb, size_t size);
133 | void *realloc(void *ptr, size_t size);
134 | void free(void *ptr);
135 | int vsnprintf(char *str, size_t size, const char *format, va_list ap);
136 |
137 | http://capstone-engine.org/embed.html
138 | */
139 | __forceinline
140 | __checkReturn
141 | bool
142 | SetMemMgrFunc(
143 | __in cs_opt_mem& memMgrSetup
144 | )
145 | {
146 | return !cs_option(*m_csh.get(), cs_opt_type::CS_OPT_MEM, reinterpret_cast(&memMgrSetup));
147 | }
148 |
149 | /*
150 | what to do when hitting *broken* instruction
151 |
152 | cs_opt_value::CS_OPT_OFF = stop //by default
153 | cs_opt_value::CS_OPT_ON = continue (+ write .byte prefix)
154 |
155 | http://capstone-engine.org/skipdata.html
156 | */
157 | __forceinline
158 | __checkReturn
159 | bool
160 | SetSkipData(
161 | __in cs_opt_value skipData
162 | )
163 | {
164 | return !cs_option(*m_csh.get(), cs_opt_type::CS_OPT_SKIPDATA, skipData);
165 | }
166 |
167 | /*
168 | Define our mneomic alternative to .byte or/and callback at *broken* instructions
169 |
170 | cs_skipdata_cb_t callback :
171 | return 0 if want to stop disassembling
172 | return how many bytes to skip (cover by mnemonic)
173 |
174 | -> example : https://github.com/aquynh/capstone/blob/next/tests/test_skipdata.c
175 | http://capstone-engine.org/skipdata.html
176 | */
177 | __forceinline
178 | __checkReturn
179 | bool
180 | SetSkipDataCallback(
181 | __in cs_opt_skipdata& dataCallbackSetup
182 | )
183 | {
184 | if (!SetSkipData(CS_OPT_ON))
185 | return false;
186 | return !cs_option(*m_csh.get(), cs_opt_type::CS_OPT_SKIPDATA_SETUP, reinterpret_cast(&dataCallbackSetup));
187 | }
188 | };
189 |
--------------------------------------------------------------------------------
/cccapstone-master/cppbindings/MipsDisasm.hh:
--------------------------------------------------------------------------------
1 | #pragma once
2 |
3 | #include "Disasm.hpp"
4 | #include "CsIns.hpp"
5 |
6 | using CMipsInsClass = CCsIns;
7 |
8 | class CMicroMipsCDisasm :
9 | public CCsDisasm
10 | {
11 | public:
12 | CMicroMipsCDisasm(
13 | __in unsigned int mode = cs_mode::CS_MODE_MICRO + cs_mode::CS_MODE_BIG_ENDIAN
14 | ) : CCsDisasm(cs_arch::CS_ARCH_MIPS, mode)
15 | {
16 | }
17 | };
18 |
19 | class CN64MipsCDisasm :
20 | public CCsDisasm
21 | {
22 | public:
23 | CN64MipsCDisasm(
24 | __in unsigned int mode = cs_mode::CS_MODE_N64 + cs_mode::CS_MODE_BIG_ENDIAN
25 | ) : CCsDisasm(cs_arch::CS_ARCH_MIPS, mode)
26 | {
27 | }
28 | };
29 |
--------------------------------------------------------------------------------
/cccapstone-master/cppbindings/PPCDisasm.hh:
--------------------------------------------------------------------------------
1 | #pragma once
2 |
3 | #include "Disasm.hpp"
4 | #include "CsIns.hpp"
5 |
6 | using CPPCInsClass = CCsIns;
7 |
8 | class CPPCDisasm :
9 | public CCsDisasm
10 | {
11 | public:
12 | CPPCDisasm(
13 | __in unsigned int mode = cs_mode::CS_MODE_BIG_ENDIAN
14 | ) : CCsDisasm(cs_arch::CS_ARCH_PPC, mode)
15 | {
16 | }
17 | };
18 |
--------------------------------------------------------------------------------
/cccapstone-master/cppbindings/SparcDisasm.hh:
--------------------------------------------------------------------------------
1 | #pragma once
2 |
3 | #include "Disasm.hpp"
4 | #include "CsIns.hpp"
5 |
6 | using CSparcInsClass = CCsIns;
7 |
8 | class CSparcV9Disasm :
9 | public CCsDisasm
10 | {
11 | public:
12 | CSparcV9Disasm(
13 | __in unsigned int mode = cs_mode::CS_MODE_V9 + cs_mode::CS_MODE_BIG_ENDIAN
14 | ) : CCsDisasm(cs_arch::CS_ARCH_SPARC, mode)
15 | {
16 | }
17 | };
18 |
19 | class CSparcDisasm :
20 | public CCsDisasm
21 | {
22 | public:
23 | CSparcDisasm(
24 | __in unsigned int mode = cs_mode::CS_MODE_BIG_ENDIAN
25 | ) : CCsDisasm(cs_arch::CS_ARCH_SPARC, mode)
26 | {
27 | }
28 | };
29 |
--------------------------------------------------------------------------------
/cccapstone-master/cppbindings/SystemZDisasm.hh:
--------------------------------------------------------------------------------
1 | #pragma once
2 |
3 | #include "Disasm.hpp"
4 | #include "CsIns.hpp"
5 |
6 | using CSysZInsClass = CCsIns;
7 |
8 | class CSystemZCDisasm :
9 | public CCsDisasm
10 | {
11 | public:
12 | CSystemZCDisasm(
13 | __in cs_mode mode = cs_mode::CS_MODE_BIG_ENDIAN
14 | ) : CCsDisasm(cs_arch::CS_ARCH_SYSZ, mode)
15 | {
16 | }
17 | };
18 |
--------------------------------------------------------------------------------
/cccapstone-master/cppbindings/X86Disasm.hh:
--------------------------------------------------------------------------------
1 | #pragma once
2 |
3 | #include "Disasm.hpp"
4 | #include "CsIns.hpp"
5 |
6 | using CX86InsClass = CCsIns;
7 |
8 | class CX86Disasm64 :
9 | public CCsDisasm
10 | {
11 | public:
12 | CX86Disasm64(
13 | __in unsigned int mode = cs_mode::CS_MODE_64 + cs_mode::CS_MODE_LITTLE_ENDIAN
14 | ) : CCsDisasm(cs_arch::CS_ARCH_X86, mode)
15 | {
16 | }
17 | };
18 |
19 | class CX86Disasm86 :
20 | public CCsDisasm
21 | {
22 | public:
23 | CX86Disasm86(
24 | __in unsigned int mode = cs_mode::CS_MODE_32 + cs_mode::CS_MODE_LITTLE_ENDIAN
25 | ) : CCsDisasm(cs_arch::CS_ARCH_X86, mode)
26 | {
27 | }
28 | };
29 |
30 | class CX86Disasm16 :
31 | public CCsDisasm
32 | {
33 | public:
34 | CX86Disasm16(
35 | __in unsigned int mode = cs_mode::CS_MODE_16 + cs_mode::CS_MODE_LITTLE_ENDIAN
36 | ) : CCsDisasm(cs_arch::CS_ARCH_X86, mode)
37 | {
38 | }
39 | };
40 |
--------------------------------------------------------------------------------
/cccapstone-master/cppbindings/XCoreDisasm.hh:
--------------------------------------------------------------------------------
1 | #pragma once
2 |
3 | #include "Disasm.hpp"
4 | #include "CsIns.hpp"
5 |
6 | using CXCoreInsClass = CCsIns;
7 |
8 | class CXCoreCDisasm :
9 | public CCsDisasm
10 | {
11 | public:
12 | CXCoreCDisasm(
13 | __in cs_mode mode = cs_mode::CS_MODE_BIG_ENDIAN
14 | ) : CCsDisasm(cs_arch::CS_ARCH_XCORE, mode)
15 | {
16 | }
17 | };
18 |
--------------------------------------------------------------------------------
/common.cpp:
--------------------------------------------------------------------------------
1 | #include "common.h"
2 | bool stringCompareIgnoreCase(std::string lhs,std::string rhs)
3 | {
4 | return _stricmp(lhs.c_str(),rhs.c_str());
5 | }
--------------------------------------------------------------------------------
/common.h:
--------------------------------------------------------------------------------
1 | #ifndef __COMMON_H__
2 | #define __COMMON_H__
3 | #include
4 | #include