├── .gitignore ├── README.md ├── SQRL_load_fpga ├── SQRL_program_flash ├── SQRL_quickstart.program_scripts ├── SQRL_quickstart.bin ├── SQRL_quickstart.bit ├── bscan_spi_xc7a200t.bit ├── jtagspi.cfg ├── openocd.cfg ├── xilinx-artix7.cfg └── xilinx-xc7.cfg ├── sqrl_acorn.v └── sqrl_acorn.xdc /.gitignore: -------------------------------------------------------------------------------- 1 | /SQRL.sim 2 | /SQRL.runs 3 | /SQRL.hbs 4 | /SQRL.cache 5 | /SQRL.hw 6 | /SQRL.ip_user_files 7 | /SQRL.outputs 8 | /.Xil 9 | 10 | SQRL.xpr 11 | *.jou 12 | *.log 13 | *.out 14 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | ## SQRL Quickstart 2 | 3 | This is a small repository that will upload a basic load-out configuration for the SQRL Acorn CLE 215/215+ Artix7 FPGA board. This configuration will blink all available LEDs and output unique square wave frequencies on all available output pins from the GPIO bank underneath the heat sink on the top side of the board (see pinout for the Hirose DF52 connector below), and allows for PCIe communication using the LiteX litepcie interface. 4 | 5 | I have also created a couple scripts for uploading the bitstream files using an FT232H based board (similar to a bus pirate or a shikra). These scripts specifically work with the Shikra (https://int3.cc/products/the-shikra), but you can subsitute your own custom interface configuration in place of the shikra configuration in the load scripts that I have provided. For uploading to the onboard flash, I recommend using a memory configuration file in the .bin format (that's what I wrote my upload scripts for anyway); the specific flash memory part is s25fl256xxxxxx0-spi-x1_x2_x4 6 | 7 | To load the provided designs using an FT232H board, you will need to build openocd from the github source found here: https://github.com/ntfreak/openocd 8 | 9 | After cloning the openocd git repository and running .bootstrap, change the following line in flash configuration file found at openocd/src/flash/nor/spi.c from: 10 | 11 | FLASH_ID("sp s25fl256s", 0x13, 0x00, 0x12, 0xdc, 0xc7, 0x00190201, 0x100, 0x10000, 0x800000), 12 | 13 | to: 14 | 15 | FLASH_ID("sp s25fl256s", 0x03, 0x00, 0x02, 0xd8, 0xc7, 0x00190201, 0x100, 0x10000, 0x800000), 16 | 17 | Then run: 18 | 19 | ```sh 20 | ./configure --enable-ftdi && make && sudo make install 21 | ``` 22 | 23 | This will install openocd and allow you to use the provided scripts for loading these designs onto the FPGA or its flash memory using a shikra (or your own FT232H board) 24 | 25 | The pinout for the Hirose DF52 connector mounted to the board and output frequencies defined for the hardware configuration in this repository are provided below: 26 | 27 | TOP VIEW 28 | (outputs --->) 29 | |--------------------> 30 | |20---> GND 31 | |19---> 6.1 kHz 32 | |18---> 12.2 kHz 33 | |17---> GND 34 | |16---> 24.4 kHz 35 | |15---> 48.8 kHz 36 | |14---> GND 37 | |13---> 97.7 kHz 38 | |12---> 195 kHz 39 | |11---> GND 40 | |10---> 391 kHz 41 | |09---> 782 kHz 42 | |08---> GND 43 | |07---> 1.56 MHz 44 | |06---> 3.13 MHz 45 | |05---> GND 46 | |04---> 6.25 MHz 47 | |03---> 12.5 MHz 48 | |02---> 3.3V 49 | |01---> 3.3V 50 | |--------------------> 51 | 52 | To get 3.3V operation on pins 15, 16, 18, and 19, you will need to remove the U11 regulator (schematic found here: https://raw.githubusercontent.com/RHSResearchLLC/NiteFury-and-LiteFury/master/Hardware/uEVB.pdf) and short the input and output pins together on the U11 pad. 53 | 54 | Most Thunderbolt 3/Thunderbolt 4 USB-C enclosures that fit this board will work (e.g. Avolusion SSDTB900-PRO Thunderbolt 3, ORICO M2V01-C4 Thunderbolt 4); with a little bit of violence, a cutout can be made so that the DF52 connector can be accessed through the case. These enclosures provide plenty of power to the board, serve as a replacement heat-sink for the FPGA (remove the original heat-sink from the board first), and function as a USB-C to PCIe adapter for interfacing with any FPGA designs you choose to mesh with an appropriate PCIe controller in the FPGA fabric. See images below for SQRL in its Thunderbolt enclosure. The SQRL Acorn should work with any Thunderbolt 3 enclosure possessing a JHL6340 chip, and seems to work with Thunderbolt 4 enclosures possessing a JHL7540 chip, provided that the board fits within the enclosure. 55 | 56 | In order to interact with this device via PCIe, you will need to install LiteX (follow the installation guide here: https://github.com/enjoy-digital/litex). You will then need to install the litepcie drivers. This can be done by invoking the following commands from within the directory where you cloned the litex repository: 57 | 58 | ```sh 59 | cd litex-boards/litex_boards/targets 60 | ./sqrl_acorn.py --driver 61 | cd build/sqrl_acorn/driver/kernel/ 62 | sudo ./init.sh 63 | ``` 64 | 65 | You may have to remove the driver (``` sudo rmmod litepcie ```) and reinstall it once or twice using init.sh to get it to show up on ``` lsmod | grep litepcie ``` 66 | 67 | You can verify that your SQRL board is working correctly by using litepcie_util from within the build/sqrl_acorn/driver/user/ to run various tests or to upload new flash bitstreams. Use ``` ./litepcie_util ``` to show you the available tests and commands. 68 | 69 | If you would like to add your own custom hardware design to the bitstream, I recommend the following steps: 70 | 71 | 1. build the default sqrl_acorn bitstream from within the ``` litex/litex-boards/litex_boards/targets/ ``` directory: ``` ./sqrl_acorn.py --uart-name=crossover --with-pcie --build --driver ``` 72 | 2. navigate to the gateware directory for the sqrl acorn bitstream you just built: ``` cd build/sqrl_acorn/gateware/ ``` 73 | 3. edit ``` sqrl_acorn.v ``` and ``` sqrl_acorn.xdc ``` in that directory to include your own custom hardware design and constraints 74 | 4. run vivado in batch mode to regenerate the bitstream with new hardware added in: ``` /tools/Xilinx/Vivado/2020.1/bin/vivado -mode batch -source sqrl_acorn.tcl ``` (note: your vivado binary may be in a different directory, choose your directory path for vivado accordingly) 75 | 5. once the new bitstream has been generated, navigate to the user directory: ``` cd ../driver/user/ ``` 76 | 6. upload the new bitstream using the litepcie_util tool: ``` ./litepcie_util --flash_write ../../sqrl_acorn.bin ``` 77 | 7. reflash the fpga using the litepcie_util tool: ``` ./litepcie_util --flash_reload ``` 78 | 79 | This should result in your custom bitstream being loaded onto the Acorn CLE-215(+) via the PCIe connection. 80 | 81 | ![SQRL_on_TBolt](https://user-images.githubusercontent.com/14501817/135922715-6cb1ca1f-d871-4a02-83e2-ecb621f50c8c.jpeg) 82 | ![SQRL_in_TBolt_Case](https://user-images.githubusercontent.com/14501817/135922713-b69c604e-2131-41af-a6e5-9036626ee039.jpeg) 83 | ![SQRL_TBolt](https://user-images.githubusercontent.com/14501817/135922710-2ada5039-e62d-4d51-8792-b59952244e62.jpeg) 84 | ![SQRL_TBolt_Functional](https://user-images.githubusercontent.com/14501817/135945759-2c006591-33b9-40f0-8171-7ceb8d46266d.jpeg) 85 | ![DMA_speed](https://user-images.githubusercontent.com/14501817/141536949-80a68b07-6392-495e-8c9b-67e2dcd66f99.png) 86 | 87 | BIG shout-out to Florent Kermarrec of EnjoyDigital, Dave Reynolds of RHS Research, Nathan Lewis, @sldif and the entire FPGA Discord community for all their help getting this project up and running. 88 | -------------------------------------------------------------------------------- /SQRL_load_fpga: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | openocd -s ./SQRL_quickstart.program_scripts -f xilinx-artix7.cfg 3 | -------------------------------------------------------------------------------- /SQRL_program_flash: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | openocd -f ./SQRL_quickstart.program_scripts/openocd.cfg & 3 | sleep 1 4 | (echo "init"; echo "jtagspi_init 0 ./SQRL_quickstart.program_scripts/bscan_spi_xc7a200t.bit"; echo "jtagspi_program ./SQRL_quickstart.program_scripts/SQRL_quickstart.bin 0x0"; echo "fpga_program"; echo "exit"; echo "quit"; sleep 150) | telnet localhost 4444 5 | pkill -f openocd 6 | -------------------------------------------------------------------------------- /SQRL_quickstart.program_scripts/SQRL_quickstart.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/SMB784/SQRL_quickstart/9b165d8010178fe085d5ba1ee8814ba749c92235/SQRL_quickstart.program_scripts/SQRL_quickstart.bin -------------------------------------------------------------------------------- /SQRL_quickstart.program_scripts/SQRL_quickstart.bit: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/SMB784/SQRL_quickstart/9b165d8010178fe085d5ba1ee8814ba749c92235/SQRL_quickstart.program_scripts/SQRL_quickstart.bit -------------------------------------------------------------------------------- /SQRL_quickstart.program_scripts/bscan_spi_xc7a200t.bit: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/SMB784/SQRL_quickstart/9b165d8010178fe085d5ba1ee8814ba749c92235/SQRL_quickstart.program_scripts/bscan_spi_xc7a200t.bit -------------------------------------------------------------------------------- /SQRL_quickstart.program_scripts/jtagspi.cfg: -------------------------------------------------------------------------------- 1 | set _USER1 0x02 2 | 3 | if { [info exists JTAGSPI_IR] } { 4 | set _JTAGSPI_IR $JTAGSPI_IR 5 | } else { 6 | set _JTAGSPI_IR $_USER1 7 | } 8 | 9 | if { [info exists TARGETNAME] } { 10 | set _TARGETNAME $TARGETNAME 11 | } else { 12 | set _TARGETNAME $_CHIPNAME.proxy 13 | } 14 | 15 | if { [info exists FLASHNAME] } { 16 | set _FLASHNAME $FLASHNAME 17 | } else { 18 | set _FLASHNAME $_CHIPNAME.spi 19 | } 20 | 21 | target create $_TARGETNAME testee -chain-position $_CHIPNAME.tap 22 | flash bank $_FLASHNAME jtagspi 0 0 0 0 $_TARGETNAME $_JTAGSPI_IR 23 | 24 | proc jtagspi_init {chain_id proxy_bit} { 25 | # load proxy bitstream $proxy_bit and probe spi flash 26 | global _FLASHNAME 27 | pld load $chain_id $proxy_bit 28 | reset halt 29 | flash probe $_FLASHNAME 30 | } 31 | 32 | proc jtagspi_program {bin addr} { 33 | # write and verify binary file $bin at offset $addr 34 | global _FLASHNAME 35 | flash write_image erase $bin $addr 36 | flash verify_bank $_FLASHNAME $bin $addr 37 | } 38 | -------------------------------------------------------------------------------- /SQRL_quickstart.program_scripts/openocd.cfg: -------------------------------------------------------------------------------- 1 | #begin shikra interface 2 | adapter driver ftdi 3 | 4 | ftdi_vid_pid 0x0403 0x6014 5 | 6 | ftdi_layout_init 0x0c08 0x0f1b 7 | 8 | adapter speed 2000 9 | 10 | telnet_port 4444 11 | 12 | gdb_port 3333 13 | 14 | transport select jtag 15 | 16 | reset_config none 17 | 18 | source [find ./SQRL_quickstart.program_scripts/xilinx-xc7.cfg] 19 | source [find ./SQRL_quickstart.program_scripts/jtagspi.cfg] 20 | 21 | proc fpga_program {} { 22 | global _CHIPNAME 23 | xc7_program $_CHIPNAME.tap 24 | } 25 | 26 | -------------------------------------------------------------------------------- /SQRL_quickstart.program_scripts/xilinx-artix7.cfg: -------------------------------------------------------------------------------- 1 | #begin shikra interface 2 | adapter driver ftdi 3 | 4 | ftdi_vid_pid 0x0403 0x6014 5 | 6 | ftdi_layout_init 0x0c08 0x0f1b 7 | 8 | adapter speed 2000 9 | 10 | telnet_port 4444 11 | 12 | gdb_port 3333 13 | 14 | transport select jtag 15 | 16 | #end shikra interface 17 | # xilinx series 7 (artix, kintex, virtex) 18 | # http://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf 19 | 20 | set _CHIPNAME xc7a200t 21 | 22 | jtag newtap $_CHIPNAME tap -irlen 6 -ignore-version -expected-id 0x13636093 23 | 24 | target create $_CHIPNAME.fpga testee -chain-position $_CHIPNAME.tap 25 | 26 | pld device virtex2 $_CHIPNAME.tap 27 | 28 | echo "Before load" 29 | 30 | init 31 | 32 | pld load 0 ./SQRL_quickstart.program_scripts/SQRL_quickstart.bit 33 | 34 | echo "After load" 35 | 36 | virtex2 read_stat 0 37 | 38 | shutdown 39 | -------------------------------------------------------------------------------- /SQRL_quickstart.program_scripts/xilinx-xc7.cfg: -------------------------------------------------------------------------------- 1 | # xilinx series 7 (artix, kintex, virtex) 2 | # http://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf 3 | 4 | if { [info exists CHIPNAME] } { 5 | set _CHIPNAME $CHIPNAME 6 | } else { 7 | set _CHIPNAME xc7 8 | } 9 | 10 | # the 4 top bits (28:31) are the die stepping/revisions. ignore it. 11 | jtag newtap $_CHIPNAME tap -irlen 6 -ignore-version \ 12 | -expected-id 0x03622093 \ 13 | -expected-id 0x03620093 \ 14 | -expected-id 0x037C4093 \ 15 | -expected-id 0x0362F093 \ 16 | -expected-id 0x037C8093 \ 17 | -expected-id 0x037C7093 \ 18 | -expected-id 0x037C3093 \ 19 | -expected-id 0x0362E093 \ 20 | -expected-id 0x037C2093 \ 21 | -expected-id 0x0362D093 \ 22 | -expected-id 0x0362C093 \ 23 | -expected-id 0x03632093 \ 24 | -expected-id 0x03631093 \ 25 | -expected-id 0x03636093 \ 26 | -expected-id 0x03647093 \ 27 | -expected-id 0x0364C093 \ 28 | -expected-id 0x03651093 \ 29 | -expected-id 0x03747093 \ 30 | -expected-id 0x03656093 \ 31 | -expected-id 0x03752093 \ 32 | -expected-id 0x03751093 \ 33 | -expected-id 0x03671093 \ 34 | -expected-id 0x036B3093 \ 35 | -expected-id 0x036B7093 \ 36 | -expected-id 0x036BB093 \ 37 | -expected-id 0x036BF093 \ 38 | -expected-id 0x03667093 \ 39 | -expected-id 0x03682093 \ 40 | -expected-id 0x03687093 \ 41 | -expected-id 0x03692093 \ 42 | -expected-id 0x03691093 \ 43 | -expected-id 0x03696093 \ 44 | -expected-id 0x036D5093 \ 45 | -expected-id 0x036D9093 \ 46 | -expected-id 0x036DB093 47 | 48 | pld device virtex2 $_CHIPNAME.tap 1 49 | 50 | set XC7_JSHUTDOWN 0x0d 51 | set XC7_JPROGRAM 0x0b 52 | set XC7_JSTART 0x0c 53 | set XC7_BYPASS 0x3f 54 | 55 | proc xc7_program {tap} { 56 | global XC7_JSHUTDOWN XC7_JPROGRAM XC7_JSTART XC7_BYPASS 57 | irscan $tap $XC7_JSHUTDOWN 58 | irscan $tap $XC7_JPROGRAM 59 | runtest 60000 60 | #JSTART prevents this from working... 61 | #irscan $tap $XC7_JSTART 62 | runtest 2000 63 | irscan $tap $XC7_BYPASS 64 | runtest 2000 65 | } 66 | -------------------------------------------------------------------------------- /sqrl_acorn.xdc: -------------------------------------------------------------------------------- 1 | ################################################################################ 2 | # IO constraints 3 | ################################################################################ 4 | # clk200:0.p 5 | set_property LOC J19 [get_ports {clk200_p}] 6 | set_property IOSTANDARD DIFF_SSTL15 [get_ports {clk200_p}] 7 | 8 | # clk200:0.n 9 | set_property LOC H19 [get_ports {clk200_n}] 10 | set_property IOSTANDARD DIFF_SSTL15 [get_ports {clk200_n}] 11 | 12 | # ddram:0.a 13 | set_property LOC M15 [get_ports {ddram_a[0]}] 14 | set_property SLEW FAST [get_ports {ddram_a[0]}] 15 | set_property IOSTANDARD SSTL15 [get_ports {ddram_a[0]}] 16 | 17 | # ddram:0.a 18 | set_property LOC L21 [get_ports {ddram_a[1]}] 19 | set_property SLEW FAST [get_ports {ddram_a[1]}] 20 | set_property IOSTANDARD SSTL15 [get_ports {ddram_a[1]}] 21 | 22 | # ddram:0.a 23 | set_property LOC M16 [get_ports {ddram_a[2]}] 24 | set_property SLEW FAST [get_ports {ddram_a[2]}] 25 | set_property IOSTANDARD SSTL15 [get_ports {ddram_a[2]}] 26 | 27 | # ddram:0.a 28 | set_property LOC L18 [get_ports {ddram_a[3]}] 29 | set_property SLEW FAST [get_ports {ddram_a[3]}] 30 | set_property IOSTANDARD SSTL15 [get_ports {ddram_a[3]}] 31 | 32 | # ddram:0.a 33 | set_property LOC K21 [get_ports {ddram_a[4]}] 34 | set_property SLEW FAST [get_ports {ddram_a[4]}] 35 | set_property IOSTANDARD SSTL15 [get_ports {ddram_a[4]}] 36 | 37 | # ddram:0.a 38 | set_property LOC M18 [get_ports {ddram_a[5]}] 39 | set_property SLEW FAST [get_ports {ddram_a[5]}] 40 | set_property IOSTANDARD SSTL15 [get_ports {ddram_a[5]}] 41 | 42 | # ddram:0.a 43 | set_property LOC M21 [get_ports {ddram_a[6]}] 44 | set_property SLEW FAST [get_ports {ddram_a[6]}] 45 | set_property IOSTANDARD SSTL15 [get_ports {ddram_a[6]}] 46 | 47 | # ddram:0.a 48 | set_property LOC N20 [get_ports {ddram_a[7]}] 49 | set_property SLEW FAST [get_ports {ddram_a[7]}] 50 | set_property IOSTANDARD SSTL15 [get_ports {ddram_a[7]}] 51 | 52 | # ddram:0.a 53 | set_property LOC M20 [get_ports {ddram_a[8]}] 54 | set_property SLEW FAST [get_ports {ddram_a[8]}] 55 | set_property IOSTANDARD SSTL15 [get_ports {ddram_a[8]}] 56 | 57 | # ddram:0.a 58 | set_property LOC N19 [get_ports {ddram_a[9]}] 59 | set_property SLEW FAST [get_ports {ddram_a[9]}] 60 | set_property IOSTANDARD SSTL15 [get_ports {ddram_a[9]}] 61 | 62 | # ddram:0.a 63 | set_property LOC J21 [get_ports {ddram_a[10]}] 64 | set_property SLEW FAST [get_ports {ddram_a[10]}] 65 | set_property IOSTANDARD SSTL15 [get_ports {ddram_a[10]}] 66 | 67 | # ddram:0.a 68 | set_property LOC M22 [get_ports {ddram_a[11]}] 69 | set_property SLEW FAST [get_ports {ddram_a[11]}] 70 | set_property IOSTANDARD SSTL15 [get_ports {ddram_a[11]}] 71 | 72 | # ddram:0.a 73 | set_property LOC K22 [get_ports {ddram_a[12]}] 74 | set_property SLEW FAST [get_ports {ddram_a[12]}] 75 | set_property IOSTANDARD SSTL15 [get_ports {ddram_a[12]}] 76 | 77 | # ddram:0.a 78 | set_property LOC N18 [get_ports {ddram_a[13]}] 79 | set_property SLEW FAST [get_ports {ddram_a[13]}] 80 | set_property IOSTANDARD SSTL15 [get_ports {ddram_a[13]}] 81 | 82 | # ddram:0.a 83 | set_property LOC N22 [get_ports {ddram_a[14]}] 84 | set_property SLEW FAST [get_ports {ddram_a[14]}] 85 | set_property IOSTANDARD SSTL15 [get_ports {ddram_a[14]}] 86 | 87 | # ddram:0.a 88 | set_property LOC J22 [get_ports {ddram_a[15]}] 89 | set_property SLEW FAST [get_ports {ddram_a[15]}] 90 | set_property IOSTANDARD SSTL15 [get_ports {ddram_a[15]}] 91 | 92 | # ddram:0.ba 93 | set_property LOC L19 [get_ports {ddram_ba[0]}] 94 | set_property SLEW FAST [get_ports {ddram_ba[0]}] 95 | set_property IOSTANDARD SSTL15 [get_ports {ddram_ba[0]}] 96 | 97 | # ddram:0.ba 98 | set_property LOC J20 [get_ports {ddram_ba[1]}] 99 | set_property SLEW FAST [get_ports {ddram_ba[1]}] 100 | set_property IOSTANDARD SSTL15 [get_ports {ddram_ba[1]}] 101 | 102 | # ddram:0.ba 103 | set_property LOC L20 [get_ports {ddram_ba[2]}] 104 | set_property SLEW FAST [get_ports {ddram_ba[2]}] 105 | set_property IOSTANDARD SSTL15 [get_ports {ddram_ba[2]}] 106 | 107 | # ddram:0.ras_n 108 | set_property LOC H20 [get_ports {ddram_ras_n}] 109 | set_property SLEW FAST [get_ports {ddram_ras_n}] 110 | set_property IOSTANDARD SSTL15 [get_ports {ddram_ras_n}] 111 | 112 | # ddram:0.cas_n 113 | set_property LOC K18 [get_ports {ddram_cas_n}] 114 | set_property SLEW FAST [get_ports {ddram_cas_n}] 115 | set_property IOSTANDARD SSTL15 [get_ports {ddram_cas_n}] 116 | 117 | # ddram:0.we_n 118 | set_property LOC L16 [get_ports {ddram_we_n}] 119 | set_property SLEW FAST [get_ports {ddram_we_n}] 120 | set_property IOSTANDARD SSTL15 [get_ports {ddram_we_n}] 121 | 122 | # ddram:0.dm 123 | set_property LOC A19 [get_ports {ddram_dm[0]}] 124 | set_property SLEW FAST [get_ports {ddram_dm[0]}] 125 | set_property IOSTANDARD SSTL15 [get_ports {ddram_dm[0]}] 126 | 127 | # ddram:0.dm 128 | set_property LOC G22 [get_ports {ddram_dm[1]}] 129 | set_property SLEW FAST [get_ports {ddram_dm[1]}] 130 | set_property IOSTANDARD SSTL15 [get_ports {ddram_dm[1]}] 131 | 132 | # ddram:0.dq 133 | set_property LOC D19 [get_ports {ddram_dq[0]}] 134 | set_property SLEW FAST [get_ports {ddram_dq[0]}] 135 | set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[0]}] 136 | set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[0]}] 137 | 138 | # ddram:0.dq 139 | set_property LOC B20 [get_ports {ddram_dq[1]}] 140 | set_property SLEW FAST [get_ports {ddram_dq[1]}] 141 | set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[1]}] 142 | set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[1]}] 143 | 144 | # ddram:0.dq 145 | set_property LOC E19 [get_ports {ddram_dq[2]}] 146 | set_property SLEW FAST [get_ports {ddram_dq[2]}] 147 | set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[2]}] 148 | set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[2]}] 149 | 150 | # ddram:0.dq 151 | set_property LOC A20 [get_ports {ddram_dq[3]}] 152 | set_property SLEW FAST [get_ports {ddram_dq[3]}] 153 | set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[3]}] 154 | set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[3]}] 155 | 156 | # ddram:0.dq 157 | set_property LOC F19 [get_ports {ddram_dq[4]}] 158 | set_property SLEW FAST [get_ports {ddram_dq[4]}] 159 | set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[4]}] 160 | set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[4]}] 161 | 162 | # ddram:0.dq 163 | set_property LOC C19 [get_ports {ddram_dq[5]}] 164 | set_property SLEW FAST [get_ports {ddram_dq[5]}] 165 | set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[5]}] 166 | set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[5]}] 167 | 168 | # ddram:0.dq 169 | set_property LOC F20 [get_ports {ddram_dq[6]}] 170 | set_property SLEW FAST [get_ports {ddram_dq[6]}] 171 | set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[6]}] 172 | set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[6]}] 173 | 174 | # ddram:0.dq 175 | set_property LOC C18 [get_ports {ddram_dq[7]}] 176 | set_property SLEW FAST [get_ports {ddram_dq[7]}] 177 | set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[7]}] 178 | set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[7]}] 179 | 180 | # ddram:0.dq 181 | set_property LOC E22 [get_ports {ddram_dq[8]}] 182 | set_property SLEW FAST [get_ports {ddram_dq[8]}] 183 | set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[8]}] 184 | set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[8]}] 185 | 186 | # ddram:0.dq 187 | set_property LOC G21 [get_ports {ddram_dq[9]}] 188 | set_property SLEW FAST [get_ports {ddram_dq[9]}] 189 | set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[9]}] 190 | set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[9]}] 191 | 192 | # ddram:0.dq 193 | set_property LOC D20 [get_ports {ddram_dq[10]}] 194 | set_property SLEW FAST [get_ports {ddram_dq[10]}] 195 | set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[10]}] 196 | set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[10]}] 197 | 198 | # ddram:0.dq 199 | set_property LOC E21 [get_ports {ddram_dq[11]}] 200 | set_property SLEW FAST [get_ports {ddram_dq[11]}] 201 | set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[11]}] 202 | set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[11]}] 203 | 204 | # ddram:0.dq 205 | set_property LOC C22 [get_ports {ddram_dq[12]}] 206 | set_property SLEW FAST [get_ports {ddram_dq[12]}] 207 | set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[12]}] 208 | set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[12]}] 209 | 210 | # ddram:0.dq 211 | set_property LOC D21 [get_ports {ddram_dq[13]}] 212 | set_property SLEW FAST [get_ports {ddram_dq[13]}] 213 | set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[13]}] 214 | set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[13]}] 215 | 216 | # ddram:0.dq 217 | set_property LOC B22 [get_ports {ddram_dq[14]}] 218 | set_property SLEW FAST [get_ports {ddram_dq[14]}] 219 | set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[14]}] 220 | set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[14]}] 221 | 222 | # ddram:0.dq 223 | set_property LOC D22 [get_ports {ddram_dq[15]}] 224 | set_property SLEW FAST [get_ports {ddram_dq[15]}] 225 | set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[15]}] 226 | set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[15]}] 227 | 228 | # ddram:0.dqs_p 229 | set_property LOC F18 [get_ports {ddram_dqs_p[0]}] 230 | set_property SLEW FAST [get_ports {ddram_dqs_p[0]}] 231 | set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddram_dqs_p[0]}] 232 | 233 | # ddram:0.dqs_p 234 | set_property LOC B21 [get_ports {ddram_dqs_p[1]}] 235 | set_property SLEW FAST [get_ports {ddram_dqs_p[1]}] 236 | set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddram_dqs_p[1]}] 237 | 238 | # ddram:0.dqs_n 239 | set_property LOC E18 [get_ports {ddram_dqs_n[0]}] 240 | set_property SLEW FAST [get_ports {ddram_dqs_n[0]}] 241 | set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddram_dqs_n[0]}] 242 | 243 | # ddram:0.dqs_n 244 | set_property LOC A21 [get_ports {ddram_dqs_n[1]}] 245 | set_property SLEW FAST [get_ports {ddram_dqs_n[1]}] 246 | set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddram_dqs_n[1]}] 247 | 248 | # ddram:0.clk_p 249 | set_property LOC K17 [get_ports {ddram_clk_p}] 250 | set_property SLEW FAST [get_ports {ddram_clk_p}] 251 | set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddram_clk_p}] 252 | 253 | # ddram:0.clk_n 254 | set_property LOC J17 [get_ports {ddram_clk_n}] 255 | set_property SLEW FAST [get_ports {ddram_clk_n}] 256 | set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddram_clk_n}] 257 | 258 | # ddram:0.cke 259 | set_property LOC H22 [get_ports {ddram_cke}] 260 | set_property SLEW FAST [get_ports {ddram_cke}] 261 | set_property IOSTANDARD SSTL15 [get_ports {ddram_cke}] 262 | 263 | # ddram:0.odt 264 | set_property LOC K19 [get_ports {ddram_odt}] 265 | set_property SLEW FAST [get_ports {ddram_odt}] 266 | set_property IOSTANDARD SSTL15 [get_ports {ddram_odt}] 267 | 268 | # ddram:0.reset_n 269 | set_property LOC K16 [get_ports {ddram_reset_n}] 270 | set_property SLEW FAST [get_ports {ddram_reset_n}] 271 | set_property IOSTANDARD LVCMOS15 [get_ports {ddram_reset_n}] 272 | 273 | # pcie_x4:0.rst_n 274 | set_property LOC J1 [get_ports {pcie_x4_rst_n}] 275 | set_property IOSTANDARD LVCMOS33 [get_ports {pcie_x4_rst_n}] 276 | set_property PULLUP TRUE [get_ports {pcie_x4_rst_n}] 277 | 278 | # pcie_x4:0.clk_p 279 | set_property LOC F6 [get_ports {pcie_x4_clk_p}] 280 | 281 | # pcie_x4:0.clk_n 282 | set_property LOC E6 [get_ports {pcie_x4_clk_n}] 283 | 284 | # pcie_x4:0.rx_p 285 | set_property LOC B10 [get_ports {pcie_x4_rx_p[0]}] 286 | 287 | # pcie_x4:0.rx_p 288 | set_property LOC B8 [get_ports {pcie_x4_rx_p[1]}] 289 | 290 | # pcie_x4:0.rx_p 291 | set_property LOC D11 [get_ports {pcie_x4_rx_p[2]}] 292 | 293 | # pcie_x4:0.rx_p 294 | set_property LOC D9 [get_ports {pcie_x4_rx_p[3]}] 295 | 296 | # pcie_x4:0.rx_n 297 | set_property LOC A10 [get_ports {pcie_x4_rx_n[0]}] 298 | 299 | # pcie_x4:0.rx_n 300 | set_property LOC A8 [get_ports {pcie_x4_rx_n[1]}] 301 | 302 | # pcie_x4:0.rx_n 303 | set_property LOC C11 [get_ports {pcie_x4_rx_n[2]}] 304 | 305 | # pcie_x4:0.rx_n 306 | set_property LOC C9 [get_ports {pcie_x4_rx_n[3]}] 307 | 308 | # pcie_x4:0.tx_p 309 | set_property LOC B6 [get_ports {pcie_x4_tx_p[0]}] 310 | 311 | # pcie_x4:0.tx_p 312 | set_property LOC B4 [get_ports {pcie_x4_tx_p[1]}] 313 | 314 | # pcie_x4:0.tx_p 315 | set_property LOC D5 [get_ports {pcie_x4_tx_p[2]}] 316 | 317 | # pcie_x4:0.tx_p 318 | set_property LOC D7 [get_ports {pcie_x4_tx_p[3]}] 319 | 320 | # pcie_x4:0.tx_n 321 | set_property LOC A6 [get_ports {pcie_x4_tx_n[0]}] 322 | 323 | # pcie_x4:0.tx_n 324 | set_property LOC A4 [get_ports {pcie_x4_tx_n[1]}] 325 | 326 | # pcie_x4:0.tx_n 327 | set_property LOC C5 [get_ports {pcie_x4_tx_n[2]}] 328 | 329 | # pcie_x4:0.tx_n 330 | set_property LOC C7 [get_ports {pcie_x4_tx_n[3]}] 331 | 332 | # flash_cs_n:0 333 | set_property LOC T19 [get_ports {flash_cs_n}] 334 | set_property IOSTANDARD LVCMOS33 [get_ports {flash_cs_n}] 335 | 336 | # flash:0.mosi 337 | set_property LOC P22 [get_ports {flash_mosi}] 338 | set_property IOSTANDARD LVCMOS33 [get_ports {flash_mosi}] 339 | 340 | # flash:0.miso 341 | set_property LOC R22 [get_ports {flash_miso}] 342 | set_property IOSTANDARD LVCMOS33 [get_ports {flash_miso}] 343 | 344 | # flash:0.wp 345 | set_property LOC P21 [get_ports {flash_wp}] 346 | set_property IOSTANDARD LVCMOS33 [get_ports {flash_wp}] 347 | 348 | # flash:0.hold 349 | set_property LOC R21 [get_ports {flash_hold}] 350 | set_property IOSTANDARD LVCMOS33 [get_ports {flash_hold}] 351 | 352 | # user_led:0 353 | set_property LOC G3 [get_ports {user_led0}] 354 | set_property IOSTANDARD LVCMOS33 [get_ports {user_led0}] 355 | 356 | # user_led:1 357 | set_property LOC H3 [get_ports {user_led1}] 358 | set_property IOSTANDARD LVCMOS33 [get_ports {user_led1}] 359 | 360 | # user_led:2 361 | set_property LOC G4 [get_ports {user_led2}] 362 | set_property IOSTANDARD LVCMOS33 [get_ports {user_led2}] 363 | 364 | # user_led:3 365 | set_property LOC H4 [get_ports {user_led3}] 366 | set_property IOSTANDARD LVCMOS33 [get_ports {user_led3}] 367 | 368 | # gpio outs 3.3v 369 | 370 | set_property LOC AB8 [get_ports {gpio_0}] 371 | set_property IOSTANDARD LVCMOS33 [get_ports {gpio_0}] 372 | 373 | set_property LOC AA8 [get_ports {gpio_1}] 374 | set_property IOSTANDARD LVCMOS33 [get_ports {gpio_1}] 375 | 376 | set_property LOC Y9 [get_ports {gpio_2}] 377 | set_property IOSTANDARD LVCMOS33 [get_ports {gpio_2}] 378 | 379 | set_property LOC W9 [get_ports {gpio_3}] 380 | set_property IOSTANDARD LVCMOS33 [get_ports {gpio_3}] 381 | 382 | set_property LOC Y8 [get_ports {gpio_4}] 383 | set_property IOSTANDARD LVCMOS33 [get_ports {gpio_4}] 384 | 385 | set_property LOC Y7 [get_ports {gpio_5}] 386 | set_property IOSTANDARD LVCMOS33 [get_ports {gpio_5}] 387 | 388 | set_property LOC V9 [get_ports {gpio_6}] 389 | set_property IOSTANDARD LVCMOS33 [get_ports {gpio_6}] 390 | 391 | set_property LOC V8 [get_ports {gpio_7}] 392 | set_property IOSTANDARD LVCMOS33 [get_ports {gpio_7}] 393 | 394 | # gpio outs 2.5v (hardware hacked to 3.3v) 395 | 396 | set_property LOC K2 [get_ports {gpio_8}] 397 | set_property IOSTANDARD LVCMOS33 [get_ports {gpio_8}] 398 | 399 | set_property LOC J2 [get_ports {gpio_9}] 400 | set_property IOSTANDARD LVCMOS33 [get_ports {gpio_9}] 401 | 402 | set_property LOC J5 [get_ports {gpio_10}] 403 | set_property IOSTANDARD LVCMOS33 [get_ports {gpio_10}] 404 | 405 | set_property LOC H5 [get_ports {gpio_11}] 406 | set_property IOSTANDARD LVCMOS33 [get_ports {gpio_11}] 407 | # set_property PULLUP true [get_ports {gpio_9}] 408 | 409 | ################################################################################ 410 | # Design constraints 411 | ################################################################################ 412 | 413 | set_property INTERNAL_VREF 0.750 [get_iobanks 34] 414 | 415 | ################################################################################ 416 | # Clock constraints 417 | ################################################################################ 418 | 419 | 420 | create_clock -name sys_clk -period 10.0 [get_nets sys_clk] 421 | 422 | create_clock -name clk200_p -period 5.0 [get_nets clk200_p] 423 | 424 | create_clock -name pcie_x4_clk_p -period 10.0 [get_nets pcie_x4_clk_p] 425 | 426 | create_clock -name icap_clk -period 160.0 [get_nets icap_clk] 427 | 428 | set_clock_groups -group [get_clocks -include_generated_clocks -of [get_nets sys_clk]] -group [get_clocks -include_generated_clocks -of [get_nets crg_clkin]] -asynchronous 429 | 430 | set_clock_groups -group [get_clocks -include_generated_clocks -of [get_nets sys_clk]] -group [get_clocks -include_generated_clocks -of [get_nets pcie_clk]] -asynchronous 431 | 432 | set_clock_groups -group [get_clocks -include_generated_clocks -of [get_nets icap_clk]] -group [get_clocks -include_generated_clocks -of [get_nets sys_clk]] -asynchronous 433 | 434 | ################################################################################ 435 | # False path constraints 436 | ################################################################################ 437 | 438 | 439 | set_false_path -quiet -through [get_nets -hierarchical -filter {mr_ff == TRUE}] 440 | 441 | set_false_path -quiet -to [get_pins -filter {REF_PIN_NAME == PRE} -of_objects [get_cells -hierarchical -filter {ars_ff1 == TRUE || ars_ff2 == TRUE}]] 442 | 443 | set_max_delay 2 -quiet -from [get_pins -filter {REF_PIN_NAME == C} -of_objects [get_cells -hierarchical -filter {ars_ff1 == TRUE}]] -to [get_pins -filter {REF_PIN_NAME == D} -of_objects [get_cells -hierarchical -filter {ars_ff2 == TRUE}]] 444 | --------------------------------------------------------------------------------