├── CONTRIBUTING.md ├── LICENSE ├── README.md ├── Release_Notes.html ├── Release_Notes.md ├── _htmresc ├── favicon.png ├── mini-st_2020.css └── st_logo_2020.png ├── lis2dh12_reg.c └── lis2dh12_reg.h /CONTRIBUTING.md: -------------------------------------------------------------------------------- 1 | ## Contributing guide 2 | This document serves as a checklist before contributing to this repository. It includes links to additional information if topics are unclear to you. 3 | 4 | This guide mainly focuses on the proper use of Git. 5 | 6 | ### 1. Before opening an issue 7 | To report a bug/request please enter the issue in the right repository. 8 | 9 | Please check the following boxes before posting an issue: 10 | - [ ] `Make sure you are using the latest commit (major releases are Tagged, but corrections are available as new commits).` 11 | - [ ] `Make sure your issue is a question/feedback/suggestion RELATED TO the software provided in this repository.` Otherwise, it should be discussed on the [ST Community forum](https://community.st.com/s/). 12 | - [ ] `Make sure your issue is not already reported/fixed on GitHub or discussed in a previous issue.` Please refer to the tab issue for the list of issues and pull-requests. Do not forget to browse to the **closed** issues. 13 | 14 | ### 2. Posting the issue 15 | When you have checked the previous boxes, you will find two templates (Bug Report or Other Issue) available in the **Issues** tab of the repository. 16 | 17 | ### 3. Pull Requests 18 | STMicroelectronics is happy to receive contributions from the community, based on an initial Contributor License Agreement (CLA) procedure. 19 | 20 | * If you are an individual writing original source code and you are sure **you own the intellectual property**, then you need to sign an Individual CLA (https://cla.st.com). 21 | * If you work for a company that wants also to allow you to contribute with your work, your company needs to provide a Corporate CLA (https://cla.st.com) mentioning your GitHub account name. 22 | * If you are not sure that a CLA (Individual or Corporate) has been signed for your GitHub account, you can check here (https://cla.st.com). 23 | 24 | Please note that: 25 | * The Corporate CLA will always take precedence over the Individual CLA. 26 | * One CLA submission is sufficient for any project proposed by STMicroelectronics. 27 | 28 | #### How to proceed 29 | 30 | * We recommend to engage first a communication through an issue, in order to present your proposal and just to confirm that it corresponds to a STMicroelectronics domain or scope. 31 | * Then fork the project to your GitHub account to further develop your contribution. Please use the latest commit version. 32 | * Please submit one Pull Request for one new feature or proposal. This will facilitate the analysis and the final merge if accepted. 33 | 34 | -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | BSD 3-Clause License 2 | 3 | Copyright (c) 2019, STMicroelectronics 4 | All rights reserved. 5 | 6 | Redistribution and use in source and binary forms, with or without 7 | modification, are permitted provided that the following conditions are met: 8 | 9 | * Redistributions of source code must retain the above copyright notice, this 10 | list of conditions and the following disclaimer. 11 | 12 | * Redistributions in binary form must reproduce the above copyright notice, 13 | this list of conditions and the following disclaimer in the documentation 14 | and/or other materials provided with the distribution. 15 | 16 | * Neither the name of the copyright holder nor the names of its 17 | contributors may be used to endorse or promote products derived from 18 | this software without specific prior written permission. 19 | 20 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 23 | DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 24 | FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 | DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 26 | SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 27 | CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 28 | OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 29 | OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | ![latest tag](https://img.shields.io/github/v/tag/STMicroelectronics/lis2dh12-pid.svg?color=brightgreen) 2 | 3 | # 1 - Introduction 4 | 5 | Sensor driver for LIS2DH12 sensor written in C programming language. This repository contains the sensor driver files (.h and .c) to be included, or linked directly as a git submodule, in your project. The driver is MISRA compliant and the documentation can be generated using the [Doxygen](http://www.doxygen.org/) tool. 6 | 7 | In order to `clone` the complete content of the repository folder, use the command: 8 | 9 | ``` 10 | git clone https://github.com/STMicroelectronics/LIS2DH12-PID/ 11 | ``` 12 | 13 | Some examples of driver usage can be found [here](https://github.com/STMicroelectronics/STMems_Standard_C_drivers). 14 | 15 | ------ 16 | 17 | 18 | 19 | # 2 - Integration details 20 | 21 | The driver is platform-independent, you only need to define two functions for read and write transactions from the sensor hardware bus (ie. SPI or I²C) and an optional one to implement a delay of millisecond granularity. **A few devices integrate an extra bit in the communication protocol in order to enable multi read/write access, this bit must be managed in the read and write functions defined by the user.** Please refer to the read and write implementation in the [reference examples](https://github.com/STMicroelectronics/STMems_Standard_C_drivers/tree/master/lis2dh12_STdC/examples). 22 | 23 | 24 | ### 2.a Source code integration 25 | 26 | - Include in your project the driver files of the sensor (.h and .c) 27 | - Define in your code the read and write functions that use the I²C or SPI platform driver like the following: 28 | 29 | ``` 30 | /** Please note that is MANDATORY: return 0 -> no Error.**/ 31 | int32_t platform_write(void *handle, uint8_t reg, const uint8_t *bufp, uint16_t len) 32 | int32_t platform_read(void *handle, uint8_t reg, uint8_t *bufp, uint16_t len) 33 | 34 | /** Optional (may be required by driver) **/ 35 | void platform_delay(uint32_t millisec) 36 | ``` 37 | 38 | - Declare and initialize the structure of the device interface: 39 | 40 | ``` 41 | xxxxxxx_ctx_t dev_ctx; /** xxxxxxx is the used part number **/ 42 | dev_ctx.write_reg = platform_write; 43 | dev_ctx.read_reg = platform_read; 44 | dev_ctx.mdelay = platform_delay; 45 | 46 | ``` 47 | 48 | - If needed by the platform read and write functions, initialize the handle parameter: 49 | 50 | ``` 51 | dev_ctx.handle = &platform_handle; 52 | ``` 53 | 54 | Some integration examples can be found [here](https://github.com/STMicroelectronics/STMems_Standard_C_drivers/tree/master/lis2dh12_STdC/examples). 55 | 56 | ### 2.b Required properties 57 | 58 | > - A standard C language compiler for the target MCU 59 | > - A C library for the target MCU and the desired interface (ie. SPI, I²C) 60 | 61 | ------ 62 | 63 | **More Information: [http://www.st.com](http://st.com/MEMS)** 64 | 65 | **Copyright (C) 2021 STMicroelectronics** -------------------------------------------------------------------------------- /Release_Notes.html: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | Release Notes for LIS2DH12 Component 8 | 25 | 26 | 27 | 28 | 29 |
30 |
31 |
32 |

Release Notes for 33 | LIS2DH12 Component Driver

34 |

Copyright © 2021 STMicroelectronics
35 |

36 | 38 |
39 |

License

40 |

This software component is licensed by ST under BSD 3-Clause license, 41 | the “License”. You may not use this component except in compliance with 42 | the License. You may obtain a copy of the License at:

43 |

BSD 3-Clause 44 | license

45 |

Purpose

46 |

This directory contains the LIS2DH12 component drivers.

47 |
48 |
49 |

Update history

50 |
51 | 52 | 54 |
55 |

Main changes

56 |

First release

57 |
    58 |
  • First official release [ref. DS v6.0]
  • 59 |
60 |

61 |
62 | 63 | 65 |
66 |

Main changes

67 |
    68 |
  • Add __weak directive to read/write registers routines
  • 69 |
  • Extend stmdev_ctx_t structure with mdelay callback
  • 70 |
  • repo name changed adding ‘-pid’ extension
  • 71 |
72 |

73 |
74 | 75 | 77 |
78 |

Main changes

79 |
    80 |
  • Fixed code style (Artistic Style Version 3.4.13)
  • 81 |
  • Invert SDO_PULL_UP connect/disconnect values in API
  • 82 |
  • Add “const” to ctx arg for all APIs
  • 83 |
84 |

85 |
86 | 87 | 89 |
90 |

Main changes

91 |
    92 |
  • updated README.md file with tag reference and mdelay 93 | description
  • 94 |
95 |

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100 | 110 | 111 | 112 | -------------------------------------------------------------------------------- /Release_Notes.md: -------------------------------------------------------------------------------- 1 | --- 2 | pagetitle: Release Notes for LIS2DH12 Component 3 | lang: en 4 | header-includes: 5 | --- 6 | 7 | ::: {.row} 8 | ::: {.col-sm-12 .col-lg-4} 9 | 10 |
11 | # Release Notes for LIS2DH12 Component Driver 12 | Copyright © 2021 STMicroelectronics\ 13 | 14 | [![ST logo](_htmresc/st_logo_2020.png)](https://www.st.com){.logo} 15 |
16 | 17 | # License 18 | 19 | This software component is licensed by ST under BSD 3-Clause license, the "License". 20 | You may not use this component except in compliance with the License. You may obtain a copy of the License at: 21 | 22 | [BSD 3-Clause license](https://opensource.org/licenses/BSD-3-Clause) 23 | 24 | # Purpose 25 | 26 | This directory contains the LIS2DH12 component drivers. 27 | ::: 28 | 29 | ::: {.col-sm-12 .col-lg-8} 30 | # Update history 31 | 32 | ::: {.collapse} 33 | 34 | 35 |
36 | 37 | ## Main changes 38 | 39 | ### First release 40 | 41 | - First official release [ref. DS v6.0] 42 | 43 | ## 44 | 45 |
46 | 47 | 48 | 49 |
50 | 51 | ## Main changes 52 | 53 | - Add __weak directive to read/write registers routines 54 | - Extend stmdev_ctx_t structure with mdelay callback 55 | - repo name changed adding '-pid' extension 56 | 57 | 58 | ## 59 | 60 |
61 | 62 | 63 | 64 |
65 | 66 | ## Main changes 67 | 68 | - Fixed code style (Artistic Style Version 3.4.13) 69 | - Invert SDO_PULL_UP connect/disconnect values in API 70 | - Add "const" to ctx arg for all APIs 71 | 72 | ## 73 | 74 |
75 | 76 | 77 | 78 |
79 | 80 | ## Main changes 81 | 82 | - updated README.md file with tag reference and mdelay description 83 | 84 | ## 85 | 86 |
87 | ::: 88 | 89 | 90 | ::: 91 | ::: 92 | 93 | 105 | -------------------------------------------------------------------------------- /_htmresc/favicon.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/STMicroelectronics/lis2dh12-pid/e163fed1a0a85f6c1e34e16d40ef7cc58ba76ccb/_htmresc/favicon.png -------------------------------------------------------------------------------- /_htmresc/mini-st_2020.css: -------------------------------------------------------------------------------- 1 | @charset "UTF-8"; 2 | /* 3 | Flavor name: Custom (mini-custom) 4 | Generated online - https://minicss.org/flavors 5 | mini.css version: v3.0.1 6 | */ 7 | /* 8 | Browsers resets and base typography. 9 | */ 10 | /* Core module CSS variable definitions */ 11 | :root { 12 | --fore-color: #03234b; 13 | --secondary-fore-color: #03234b; 14 | --back-color: #ffffff; 15 | --secondary-back-color: #ffffff; 16 | --blockquote-color: #e6007e; 17 | --pre-color: #e6007e; 18 | --border-color: #3cb4e6; 19 | --secondary-border-color: #3cb4e6; 20 | --heading-ratio: 1.2; 21 | --universal-margin: 0.5rem; 22 | --universal-padding: 0.25rem; 23 | --universal-border-radius: 0.075rem; 24 | --background-margin: 1.5%; 25 | --a-link-color: #3cb4e6; 26 | --a-visited-color: #8c0078; } 27 | 28 | html { 29 | font-size: 13.5px; } 30 | 31 | a, b, del, em, i, ins, q, span, strong, u { 32 | font-size: 1em; } 33 | 34 | html, * { 35 | font-family: -apple-system, BlinkMacSystemFont, Helvetica, arial, sans-serif; 36 | line-height: 1.25; 37 | -webkit-text-size-adjust: 100%; } 38 | 39 | * { 40 | font-size: 1rem; } 41 | 42 | body { 43 | margin: 0; 44 | color: var(--fore-color); 45 | @background: var(--back-color); 46 | background: var(--back-color) linear-gradient(#ffd200, #ffd200) repeat-y left top; 47 | background-size: var(--background-margin); 48 | } 49 | 50 | details { 51 | display: block; } 52 | 53 | summary { 54 | display: list-item; } 55 | 56 | abbr[title] { 57 | border-bottom: none; 58 | text-decoration: underline dotted; } 59 | 60 | input { 61 | overflow: visible; } 62 | 63 | img { 64 | max-width: 100%; 65 | height: auto; } 66 | 67 | h1, h2, h3, h4, h5, h6 { 68 | line-height: 1.25; 69 | margin: calc(1.5 * var(--universal-margin)) var(--universal-margin); 70 | font-weight: 400; } 71 | h1 small, h2 small, h3 small, h4 small, h5 small, h6 small { 72 | color: var(--secondary-fore-color); 73 | display: block; 74 | margin-top: -0.25rem; } 75 | 76 | h1 { 77 | font-size: calc(1rem * var(--heading-ratio) * var(--heading-ratio) * var(--heading-ratio)); } 78 | 79 | h2 { 80 | font-size: calc(1rem * var(--heading-ratio) * var(--heading-ratio) ); 81 | border-style: none none solid none ; 82 | border-width: thin; 83 | border-color: var(--border-color); } 84 | h3 { 85 | font-size: calc(1rem * var(--heading-ratio) ); } 86 | 87 | h4 { 88 | font-size: calc(1rem * var(--heading-ratio)); } 89 | 90 | h5 { 91 | font-size: 1rem; } 92 | 93 | h6 { 94 | font-size: calc(1rem / var(--heading-ratio)); } 95 | 96 | p { 97 | margin: var(--universal-margin); } 98 | 99 | ol, ul { 100 | margin: var(--universal-margin); 101 | padding-left: calc(3 * var(--universal-margin)); } 102 | 103 | b, strong { 104 | font-weight: 700; } 105 | 106 | hr { 107 | box-sizing: content-box; 108 | border: 0; 109 | line-height: 1.25em; 110 | margin: var(--universal-margin); 111 | height: 0.0714285714rem; 112 | background: linear-gradient(to right, transparent, var(--border-color) 20%, var(--border-color) 80%, transparent); } 113 | 114 | blockquote { 115 | display: block; 116 | position: relative; 117 | font-style: italic; 118 | color: var(--secondary-fore-color); 119 | margin: var(--universal-margin); 120 | padding: calc(3 * var(--universal-padding)); 121 | border: 0.0714285714rem solid var(--secondary-border-color); 122 | border-left: 0.3rem solid var(--blockquote-color); 123 | border-radius: 0 var(--universal-border-radius) var(--universal-border-radius) 0; } 124 | blockquote:before { 125 | position: absolute; 126 | top: calc(0rem - var(--universal-padding)); 127 | left: 0; 128 | font-family: sans-serif; 129 | font-size: 2rem; 130 | font-weight: 800; 131 | content: "\201c"; 132 | color: var(--blockquote-color); } 133 | blockquote[cite]:after { 134 | font-style: normal; 135 | font-size: 0.75em; 136 | font-weight: 700; 137 | content: "\a— " attr(cite); 138 | white-space: pre; } 139 | 140 | code, kbd, pre, samp { 141 | font-family: Menlo, Consolas, monospace; 142 | font-size: 0.85em; } 143 | 144 | code { 145 | background: var(--secondary-back-color); 146 | border-radius: var(--universal-border-radius); 147 | padding: calc(var(--universal-padding) / 4) calc(var(--universal-padding) / 2); } 148 | 149 | kbd { 150 | background: var(--fore-color); 151 | color: var(--back-color); 152 | border-radius: var(--universal-border-radius); 153 | padding: calc(var(--universal-padding) / 4) calc(var(--universal-padding) / 2); } 154 | 155 | pre { 156 | overflow: auto; 157 | background: var(--secondary-back-color); 158 | padding: calc(1.5 * var(--universal-padding)); 159 | margin: var(--universal-margin); 160 | border: 0.0714285714rem solid var(--secondary-border-color); 161 | border-left: 0.2857142857rem solid var(--pre-color); 162 | border-radius: 0 var(--universal-border-radius) var(--universal-border-radius) 0; } 163 | 164 | sup, sub, code, kbd { 165 | line-height: 0; 166 | position: relative; 167 | vertical-align: baseline; } 168 | 169 | small, sup, sub, figcaption { 170 | font-size: 0.75em; } 171 | 172 | sup { 173 | top: -0.5em; } 174 | 175 | sub { 176 | bottom: -0.25em; } 177 | 178 | figure { 179 | margin: var(--universal-margin); } 180 | 181 | figcaption { 182 | color: var(--secondary-fore-color); } 183 | 184 | a { 185 | text-decoration: none; } 186 | a:link { 187 | color: var(--a-link-color); } 188 | a:visited { 189 | color: var(--a-visited-color); } 190 | a:hover, a:focus { 191 | text-decoration: underline; } 192 | 193 | /* 194 | Definitions for the grid system, cards and containers. 195 | */ 196 | .container { 197 | margin: 0 auto; 198 | padding: 0 calc(1.5 * var(--universal-padding)); } 199 | 200 | .row { 201 | box-sizing: border-box; 202 | display: flex; 203 | flex: 0 1 auto; 204 | flex-flow: row wrap; 205 | margin: 0 0 0 var(--background-margin); } 206 | 207 | .col-sm, 208 | [class^='col-sm-'], 209 | [class^='col-sm-offset-'], 210 | .row[class*='cols-sm-'] > * { 211 | box-sizing: border-box; 212 | flex: 0 0 auto; 213 | padding: 0 calc(var(--universal-padding) / 2); } 214 | 215 | .col-sm, 216 | .row.cols-sm > * { 217 | max-width: 100%; 218 | flex-grow: 1; 219 | flex-basis: 0; } 220 | 221 | .col-sm-1, 222 | .row.cols-sm-1 > * { 223 | max-width: 8.3333333333%; 224 | flex-basis: 8.3333333333%; } 225 | 226 | .col-sm-offset-0 { 227 | margin-left: 0; } 228 | 229 | .col-sm-2, 230 | .row.cols-sm-2 > * { 231 | max-width: 16.6666666667%; 232 | flex-basis: 16.6666666667%; } 233 | 234 | .col-sm-offset-1 { 235 | margin-left: 8.3333333333%; } 236 | 237 | .col-sm-3, 238 | .row.cols-sm-3 > * { 239 | max-width: 25%; 240 | flex-basis: 25%; } 241 | 242 | .col-sm-offset-2 { 243 | margin-left: 16.6666666667%; } 244 | 245 | .col-sm-4, 246 | .row.cols-sm-4 > * { 247 | max-width: 33.3333333333%; 248 | flex-basis: 33.3333333333%; } 249 | 250 | .col-sm-offset-3 { 251 | margin-left: 25%; } 252 | 253 | .col-sm-5, 254 | .row.cols-sm-5 > * { 255 | max-width: 41.6666666667%; 256 | flex-basis: 41.6666666667%; } 257 | 258 | .col-sm-offset-4 { 259 | margin-left: 33.3333333333%; } 260 | 261 | .col-sm-6, 262 | .row.cols-sm-6 > * { 263 | max-width: 50%; 264 | flex-basis: 50%; } 265 | 266 | .col-sm-offset-5 { 267 | margin-left: 41.6666666667%; } 268 | 269 | .col-sm-7, 270 | .row.cols-sm-7 > * { 271 | max-width: 58.3333333333%; 272 | flex-basis: 58.3333333333%; } 273 | 274 | .col-sm-offset-6 { 275 | margin-left: 50%; } 276 | 277 | .col-sm-8, 278 | .row.cols-sm-8 > * { 279 | max-width: 66.6666666667%; 280 | flex-basis: 66.6666666667%; } 281 | 282 | .col-sm-offset-7 { 283 | margin-left: 58.3333333333%; } 284 | 285 | .col-sm-9, 286 | .row.cols-sm-9 > * { 287 | max-width: 75%; 288 | flex-basis: 75%; } 289 | 290 | .col-sm-offset-8 { 291 | margin-left: 66.6666666667%; } 292 | 293 | .col-sm-10, 294 | .row.cols-sm-10 > * { 295 | max-width: 83.3333333333%; 296 | flex-basis: 83.3333333333%; } 297 | 298 | .col-sm-offset-9 { 299 | margin-left: 75%; } 300 | 301 | .col-sm-11, 302 | .row.cols-sm-11 > * { 303 | max-width: 91.6666666667%; 304 | flex-basis: 91.6666666667%; } 305 | 306 | .col-sm-offset-10 { 307 | margin-left: 83.3333333333%; } 308 | 309 | .col-sm-12, 310 | .row.cols-sm-12 > * { 311 | max-width: 100%; 312 | flex-basis: 100%; } 313 | 314 | .col-sm-offset-11 { 315 | margin-left: 91.6666666667%; } 316 | 317 | .col-sm-normal { 318 | order: initial; } 319 | 320 | .col-sm-first { 321 | order: -999; } 322 | 323 | .col-sm-last { 324 | order: 999; } 325 | 326 | @media screen and (min-width: 500px) { 327 | .col-md, 328 | [class^='col-md-'], 329 | [class^='col-md-offset-'], 330 | .row[class*='cols-md-'] > * { 331 | box-sizing: border-box; 332 | flex: 0 0 auto; 333 | padding: 0 calc(var(--universal-padding) / 2); } 334 | 335 | .col-md, 336 | .row.cols-md > * { 337 | max-width: 100%; 338 | flex-grow: 1; 339 | flex-basis: 0; } 340 | 341 | .col-md-1, 342 | .row.cols-md-1 > * { 343 | max-width: 8.3333333333%; 344 | flex-basis: 8.3333333333%; } 345 | 346 | .col-md-offset-0 { 347 | margin-left: 0; } 348 | 349 | .col-md-2, 350 | .row.cols-md-2 > * { 351 | max-width: 16.6666666667%; 352 | flex-basis: 16.6666666667%; } 353 | 354 | .col-md-offset-1 { 355 | margin-left: 8.3333333333%; } 356 | 357 | .col-md-3, 358 | .row.cols-md-3 > * { 359 | max-width: 25%; 360 | flex-basis: 25%; } 361 | 362 | .col-md-offset-2 { 363 | margin-left: 16.6666666667%; } 364 | 365 | .col-md-4, 366 | .row.cols-md-4 > * { 367 | max-width: 33.3333333333%; 368 | flex-basis: 33.3333333333%; } 369 | 370 | .col-md-offset-3 { 371 | margin-left: 25%; } 372 | 373 | .col-md-5, 374 | .row.cols-md-5 > * { 375 | max-width: 41.6666666667%; 376 | flex-basis: 41.6666666667%; } 377 | 378 | .col-md-offset-4 { 379 | margin-left: 33.3333333333%; } 380 | 381 | .col-md-6, 382 | .row.cols-md-6 > * { 383 | max-width: 50%; 384 | flex-basis: 50%; } 385 | 386 | .col-md-offset-5 { 387 | margin-left: 41.6666666667%; } 388 | 389 | .col-md-7, 390 | .row.cols-md-7 > * { 391 | max-width: 58.3333333333%; 392 | flex-basis: 58.3333333333%; } 393 | 394 | .col-md-offset-6 { 395 | margin-left: 50%; } 396 | 397 | .col-md-8, 398 | .row.cols-md-8 > * { 399 | max-width: 66.6666666667%; 400 | flex-basis: 66.6666666667%; } 401 | 402 | .col-md-offset-7 { 403 | margin-left: 58.3333333333%; } 404 | 405 | .col-md-9, 406 | .row.cols-md-9 > * { 407 | max-width: 75%; 408 | flex-basis: 75%; } 409 | 410 | .col-md-offset-8 { 411 | margin-left: 66.6666666667%; } 412 | 413 | .col-md-10, 414 | .row.cols-md-10 > * { 415 | max-width: 83.3333333333%; 416 | flex-basis: 83.3333333333%; } 417 | 418 | .col-md-offset-9 { 419 | margin-left: 75%; } 420 | 421 | .col-md-11, 422 | .row.cols-md-11 > * { 423 | max-width: 91.6666666667%; 424 | flex-basis: 91.6666666667%; } 425 | 426 | .col-md-offset-10 { 427 | margin-left: 83.3333333333%; } 428 | 429 | .col-md-12, 430 | .row.cols-md-12 > * { 431 | max-width: 100%; 432 | flex-basis: 100%; } 433 | 434 | .col-md-offset-11 { 435 | margin-left: 91.6666666667%; } 436 | 437 | .col-md-normal { 438 | order: initial; } 439 | 440 | .col-md-first { 441 | order: -999; } 442 | 443 | .col-md-last { 444 | order: 999; } } 445 | @media screen and (min-width: 1280px) { 446 | .col-lg, 447 | [class^='col-lg-'], 448 | [class^='col-lg-offset-'], 449 | .row[class*='cols-lg-'] > * { 450 | box-sizing: border-box; 451 | flex: 0 0 auto; 452 | padding: 0 calc(var(--universal-padding) / 2); } 453 | 454 | .col-lg, 455 | .row.cols-lg > * { 456 | max-width: 100%; 457 | flex-grow: 1; 458 | flex-basis: 0; } 459 | 460 | .col-lg-1, 461 | .row.cols-lg-1 > * { 462 | max-width: 8.3333333333%; 463 | flex-basis: 8.3333333333%; } 464 | 465 | .col-lg-offset-0 { 466 | margin-left: 0; } 467 | 468 | .col-lg-2, 469 | .row.cols-lg-2 > * { 470 | max-width: 16.6666666667%; 471 | flex-basis: 16.6666666667%; } 472 | 473 | .col-lg-offset-1 { 474 | margin-left: 8.3333333333%; } 475 | 476 | .col-lg-3, 477 | .row.cols-lg-3 > * { 478 | max-width: 25%; 479 | flex-basis: 25%; } 480 | 481 | .col-lg-offset-2 { 482 | margin-left: 16.6666666667%; } 483 | 484 | .col-lg-4, 485 | .row.cols-lg-4 > * { 486 | max-width: 33.3333333333%; 487 | flex-basis: 33.3333333333%; } 488 | 489 | .col-lg-offset-3 { 490 | margin-left: 25%; } 491 | 492 | .col-lg-5, 493 | .row.cols-lg-5 > * { 494 | max-width: 41.6666666667%; 495 | flex-basis: 41.6666666667%; } 496 | 497 | .col-lg-offset-4 { 498 | margin-left: 33.3333333333%; } 499 | 500 | .col-lg-6, 501 | .row.cols-lg-6 > * { 502 | max-width: 50%; 503 | flex-basis: 50%; } 504 | 505 | .col-lg-offset-5 { 506 | margin-left: 41.6666666667%; } 507 | 508 | .col-lg-7, 509 | .row.cols-lg-7 > * { 510 | max-width: 58.3333333333%; 511 | flex-basis: 58.3333333333%; } 512 | 513 | .col-lg-offset-6 { 514 | margin-left: 50%; } 515 | 516 | .col-lg-8, 517 | .row.cols-lg-8 > * { 518 | max-width: 66.6666666667%; 519 | flex-basis: 66.6666666667%; } 520 | 521 | .col-lg-offset-7 { 522 | margin-left: 58.3333333333%; } 523 | 524 | .col-lg-9, 525 | .row.cols-lg-9 > * { 526 | max-width: 75%; 527 | flex-basis: 75%; } 528 | 529 | .col-lg-offset-8 { 530 | margin-left: 66.6666666667%; } 531 | 532 | .col-lg-10, 533 | .row.cols-lg-10 > * { 534 | max-width: 83.3333333333%; 535 | flex-basis: 83.3333333333%; } 536 | 537 | .col-lg-offset-9 { 538 | margin-left: 75%; } 539 | 540 | .col-lg-11, 541 | .row.cols-lg-11 > * { 542 | max-width: 91.6666666667%; 543 | flex-basis: 91.6666666667%; } 544 | 545 | .col-lg-offset-10 { 546 | margin-left: 83.3333333333%; } 547 | 548 | .col-lg-12, 549 | .row.cols-lg-12 > * { 550 | max-width: 100%; 551 | flex-basis: 100%; } 552 | 553 | .col-lg-offset-11 { 554 | margin-left: 91.6666666667%; } 555 | 556 | .col-lg-normal { 557 | order: initial; } 558 | 559 | .col-lg-first { 560 | order: -999; } 561 | 562 | .col-lg-last { 563 | order: 999; } } 564 | /* Card component CSS variable definitions */ 565 | :root { 566 | --card-back-color: #3cb4e6; 567 | --card-fore-color: #03234b; 568 | --card-border-color: #03234b; } 569 | 570 | .card { 571 | display: flex; 572 | flex-direction: column; 573 | justify-content: space-between; 574 | align-self: center; 575 | position: relative; 576 | width: 100%; 577 | background: var(--card-back-color); 578 | color: var(--card-fore-color); 579 | border: 0.0714285714rem solid var(--card-border-color); 580 | border-radius: var(--universal-border-radius); 581 | margin: var(--universal-margin); 582 | overflow: hidden; } 583 | @media screen and (min-width: 320px) { 584 | .card { 585 | max-width: 320px; } } 586 | .card > .sectione { 587 | background: var(--card-back-color); 588 | color: var(--card-fore-color); 589 | box-sizing: border-box; 590 | margin: 0; 591 | border: 0; 592 | border-radius: 0; 593 | border-bottom: 0.0714285714rem solid var(--card-border-color); 594 | padding: var(--universal-padding); 595 | width: 100%; } 596 | .card > .sectione.media { 597 | height: 200px; 598 | padding: 0; 599 | -o-object-fit: cover; 600 | object-fit: cover; } 601 | .card > .sectione:last-child { 602 | border-bottom: 0; } 603 | 604 | /* 605 | Custom elements for card elements. 606 | */ 607 | @media screen and (min-width: 240px) { 608 | .card.small { 609 | max-width: 240px; } } 610 | @media screen and (min-width: 480px) { 611 | .card.large { 612 | max-width: 480px; } } 613 | .card.fluid { 614 | max-width: 100%; 615 | width: auto; } 616 | 617 | .card.warning { 618 | --card-back-color: #e5b8b7; 619 | --card-fore-color: #3b234b; 620 | --card-border-color: #8c0078; } 621 | 622 | .card.error { 623 | --card-back-color: #464650; 624 | --card-fore-color: #ffffff; 625 | --card-border-color: #8c0078; } 626 | 627 | .card > .sectione.dark { 628 | --card-back-color: #3b234b; 629 | --card-fore-color: #ffffff; } 630 | 631 | .card > .sectione.double-padded { 632 | padding: calc(1.5 * var(--universal-padding)); } 633 | 634 | /* 635 | Definitions for forms and input elements. 636 | */ 637 | /* Input_control module CSS variable definitions */ 638 | :root { 639 | --form-back-color: #ffe97f; 640 | --form-fore-color: #03234b; 641 | --form-border-color: #3cb4e6; 642 | --input-back-color: #ffffff; 643 | --input-fore-color: #03234b; 644 | --input-border-color: #3cb4e6; 645 | --input-focus-color: #0288d1; 646 | --input-invalid-color: #d32f2f; 647 | --button-back-color: #e2e2e2; 648 | --button-hover-back-color: #dcdcdc; 649 | --button-fore-color: #212121; 650 | --button-border-color: transparent; 651 | --button-hover-border-color: transparent; 652 | --button-group-border-color: rgba(124, 124, 124, 0.54); } 653 | 654 | form { 655 | background: var(--form-back-color); 656 | color: var(--form-fore-color); 657 | border: 0.0714285714rem solid var(--form-border-color); 658 | border-radius: var(--universal-border-radius); 659 | margin: var(--universal-margin); 660 | padding: calc(2 * var(--universal-padding)) var(--universal-padding); } 661 | 662 | fieldset { 663 | border: 0.0714285714rem solid var(--form-border-color); 664 | border-radius: var(--universal-border-radius); 665 | margin: calc(var(--universal-margin) / 4); 666 | padding: var(--universal-padding); } 667 | 668 | legend { 669 | box-sizing: border-box; 670 | display: table; 671 | max-width: 100%; 672 | white-space: normal; 673 | font-weight: 500; 674 | padding: calc(var(--universal-padding) / 2); } 675 | 676 | label { 677 | padding: calc(var(--universal-padding) / 2) var(--universal-padding); } 678 | 679 | .input-group { 680 | display: inline-block; } 681 | .input-group.fluid { 682 | display: flex; 683 | align-items: center; 684 | justify-content: center; } 685 | .input-group.fluid > input { 686 | max-width: 100%; 687 | flex-grow: 1; 688 | flex-basis: 0px; } 689 | @media screen and (max-width: 499px) { 690 | .input-group.fluid { 691 | align-items: stretch; 692 | flex-direction: column; } } 693 | .input-group.vertical { 694 | display: flex; 695 | align-items: stretch; 696 | flex-direction: column; } 697 | .input-group.vertical > input { 698 | max-width: 100%; 699 | flex-grow: 1; 700 | flex-basis: 0px; } 701 | 702 | [type="number"]::-webkit-inner-spin-button, [type="number"]::-webkit-outer-spin-button { 703 | height: auto; } 704 | 705 | [type="search"] { 706 | -webkit-appearance: textfield; 707 | outline-offset: -2px; } 708 | 709 | [type="search"]::-webkit-search-cancel-button, 710 | [type="search"]::-webkit-search-decoration { 711 | -webkit-appearance: none; } 712 | 713 | input:not([type]), [type="text"], [type="email"], [type="number"], [type="search"], 714 | [type="password"], [type="url"], [type="tel"], [type="checkbox"], [type="radio"], textarea, select { 715 | box-sizing: border-box; 716 | background: var(--input-back-color); 717 | color: var(--input-fore-color); 718 | border: 0.0714285714rem solid var(--input-border-color); 719 | border-radius: var(--universal-border-radius); 720 | margin: calc(var(--universal-margin) / 2); 721 | padding: var(--universal-padding) calc(1.5 * var(--universal-padding)); } 722 | 723 | input:not([type="button"]):not([type="submit"]):not([type="reset"]):hover, input:not([type="button"]):not([type="submit"]):not([type="reset"]):focus, textarea:hover, textarea:focus, select:hover, select:focus { 724 | border-color: var(--input-focus-color); 725 | box-shadow: none; } 726 | input:not([type="button"]):not([type="submit"]):not([type="reset"]):invalid, input:not([type="button"]):not([type="submit"]):not([type="reset"]):focus:invalid, textarea:invalid, textarea:focus:invalid, select:invalid, select:focus:invalid { 727 | border-color: var(--input-invalid-color); 728 | box-shadow: none; } 729 | input:not([type="button"]):not([type="submit"]):not([type="reset"])[readonly], textarea[readonly], select[readonly] { 730 | background: var(--secondary-back-color); } 731 | 732 | select { 733 | max-width: 100%; } 734 | 735 | option { 736 | overflow: hidden; 737 | text-overflow: ellipsis; } 738 | 739 | [type="checkbox"], [type="radio"] { 740 | -webkit-appearance: none; 741 | -moz-appearance: none; 742 | appearance: none; 743 | position: relative; 744 | height: calc(1rem + var(--universal-padding) / 2); 745 | width: calc(1rem + var(--universal-padding) / 2); 746 | vertical-align: text-bottom; 747 | padding: 0; 748 | flex-basis: calc(1rem + var(--universal-padding) / 2) !important; 749 | flex-grow: 0 !important; } 750 | [type="checkbox"]:checked:before, [type="radio"]:checked:before { 751 | position: absolute; } 752 | 753 | [type="checkbox"]:checked:before { 754 | content: '\2713'; 755 | font-family: sans-serif; 756 | font-size: calc(1rem + var(--universal-padding) / 2); 757 | top: calc(0rem - var(--universal-padding)); 758 | left: calc(var(--universal-padding) / 4); } 759 | 760 | [type="radio"] { 761 | border-radius: 100%; } 762 | [type="radio"]:checked:before { 763 | border-radius: 100%; 764 | content: ''; 765 | top: calc(0.0714285714rem + var(--universal-padding) / 2); 766 | left: calc(0.0714285714rem + var(--universal-padding) / 2); 767 | background: var(--input-fore-color); 768 | width: 0.5rem; 769 | height: 0.5rem; } 770 | 771 | :placeholder-shown { 772 | color: var(--input-fore-color); } 773 | 774 | ::-ms-placeholder { 775 | color: var(--input-fore-color); 776 | opacity: 0.54; } 777 | 778 | button::-moz-focus-inner, [type="button"]::-moz-focus-inner, [type="reset"]::-moz-focus-inner, [type="submit"]::-moz-focus-inner { 779 | border-style: none; 780 | padding: 0; } 781 | 782 | button, html [type="button"], [type="reset"], [type="submit"] { 783 | -webkit-appearance: button; } 784 | 785 | button { 786 | overflow: visible; 787 | text-transform: none; } 788 | 789 | button, [type="button"], [type="submit"], [type="reset"], 790 | a.button, label.button, .button, 791 | a[role="button"], label[role="button"], [role="button"] { 792 | display: inline-block; 793 | background: var(--button-back-color); 794 | color: var(--button-fore-color); 795 | border: 0.0714285714rem solid var(--button-border-color); 796 | border-radius: var(--universal-border-radius); 797 | padding: var(--universal-padding) calc(1.5 * var(--universal-padding)); 798 | margin: var(--universal-margin); 799 | text-decoration: none; 800 | cursor: pointer; 801 | transition: background 0.3s; } 802 | button:hover, button:focus, [type="button"]:hover, [type="button"]:focus, [type="submit"]:hover, [type="submit"]:focus, [type="reset"]:hover, [type="reset"]:focus, 803 | a.button:hover, 804 | a.button:focus, label.button:hover, label.button:focus, .button:hover, .button:focus, 805 | a[role="button"]:hover, 806 | a[role="button"]:focus, label[role="button"]:hover, label[role="button"]:focus, [role="button"]:hover, [role="button"]:focus { 807 | background: var(--button-hover-back-color); 808 | border-color: var(--button-hover-border-color); } 809 | 810 | input:disabled, input[disabled], textarea:disabled, textarea[disabled], select:disabled, select[disabled], button:disabled, button[disabled], .button:disabled, .button[disabled], [role="button"]:disabled, [role="button"][disabled] { 811 | cursor: not-allowed; 812 | opacity: 0.75; } 813 | 814 | .button-group { 815 | display: flex; 816 | border: 0.0714285714rem solid var(--button-group-border-color); 817 | border-radius: var(--universal-border-radius); 818 | margin: var(--universal-margin); } 819 | .button-group > button, .button-group [type="button"], .button-group > [type="submit"], .button-group > [type="reset"], .button-group > .button, .button-group > [role="button"] { 820 | margin: 0; 821 | max-width: 100%; 822 | flex: 1 1 auto; 823 | text-align: center; 824 | border: 0; 825 | border-radius: 0; 826 | box-shadow: none; } 827 | .button-group > :not(:first-child) { 828 | border-left: 0.0714285714rem solid var(--button-group-border-color); } 829 | @media screen and (max-width: 499px) { 830 | .button-group { 831 | flex-direction: column; } 832 | .button-group > :not(:first-child) { 833 | border: 0; 834 | border-top: 0.0714285714rem solid var(--button-group-border-color); } } 835 | 836 | /* 837 | Custom elements for forms and input elements. 838 | */ 839 | button.primary, [type="button"].primary, [type="submit"].primary, [type="reset"].primary, .button.primary, [role="button"].primary { 840 | --button-back-color: #1976d2; 841 | --button-fore-color: #f8f8f8; } 842 | button.primary:hover, button.primary:focus, [type="button"].primary:hover, [type="button"].primary:focus, [type="submit"].primary:hover, [type="submit"].primary:focus, [type="reset"].primary:hover, [type="reset"].primary:focus, .button.primary:hover, .button.primary:focus, [role="button"].primary:hover, [role="button"].primary:focus { 843 | --button-hover-back-color: #1565c0; } 844 | 845 | button.secondary, [type="button"].secondary, [type="submit"].secondary, [type="reset"].secondary, .button.secondary, [role="button"].secondary { 846 | --button-back-color: #d32f2f; 847 | --button-fore-color: #f8f8f8; } 848 | button.secondary:hover, button.secondary:focus, [type="button"].secondary:hover, [type="button"].secondary:focus, [type="submit"].secondary:hover, [type="submit"].secondary:focus, [type="reset"].secondary:hover, [type="reset"].secondary:focus, .button.secondary:hover, .button.secondary:focus, [role="button"].secondary:hover, [role="button"].secondary:focus { 849 | --button-hover-back-color: #c62828; } 850 | 851 | button.tertiary, [type="button"].tertiary, [type="submit"].tertiary, [type="reset"].tertiary, .button.tertiary, [role="button"].tertiary { 852 | --button-back-color: #308732; 853 | --button-fore-color: #f8f8f8; } 854 | button.tertiary:hover, button.tertiary:focus, [type="button"].tertiary:hover, [type="button"].tertiary:focus, [type="submit"].tertiary:hover, [type="submit"].tertiary:focus, [type="reset"].tertiary:hover, [type="reset"].tertiary:focus, .button.tertiary:hover, .button.tertiary:focus, [role="button"].tertiary:hover, [role="button"].tertiary:focus { 855 | --button-hover-back-color: #277529; } 856 | 857 | button.inverse, [type="button"].inverse, [type="submit"].inverse, [type="reset"].inverse, .button.inverse, [role="button"].inverse { 858 | --button-back-color: #212121; 859 | --button-fore-color: #f8f8f8; } 860 | button.inverse:hover, button.inverse:focus, [type="button"].inverse:hover, [type="button"].inverse:focus, [type="submit"].inverse:hover, [type="submit"].inverse:focus, [type="reset"].inverse:hover, [type="reset"].inverse:focus, .button.inverse:hover, .button.inverse:focus, [role="button"].inverse:hover, [role="button"].inverse:focus { 861 | --button-hover-back-color: #111; } 862 | 863 | button.small, [type="button"].small, [type="submit"].small, [type="reset"].small, .button.small, [role="button"].small { 864 | padding: calc(0.5 * var(--universal-padding)) calc(0.75 * var(--universal-padding)); 865 | margin: var(--universal-margin); } 866 | 867 | button.large, [type="button"].large, [type="submit"].large, [type="reset"].large, .button.large, [role="button"].large { 868 | padding: calc(1.5 * var(--universal-padding)) calc(2 * var(--universal-padding)); 869 | margin: var(--universal-margin); } 870 | 871 | /* 872 | Definitions for navigation elements. 873 | */ 874 | /* Navigation module CSS variable definitions */ 875 | :root { 876 | --header-back-color: #03234b; 877 | --header-hover-back-color: #ffd200; 878 | --header-fore-color: #ffffff; 879 | --header-border-color: #3cb4e6; 880 | --nav-back-color: #ffffff; 881 | --nav-hover-back-color: #ffe97f; 882 | --nav-fore-color: #e6007e; 883 | --nav-border-color: #3cb4e6; 884 | --nav-link-color: #3cb4e6; 885 | --footer-fore-color: #ffffff; 886 | --footer-back-color: #03234b; 887 | --footer-border-color: #3cb4e6; 888 | --footer-link-color: #3cb4e6; 889 | --drawer-back-color: #ffffff; 890 | --drawer-hover-back-color: #ffe97f; 891 | --drawer-border-color: #3cb4e6; 892 | --drawer-close-color: #e6007e; } 893 | 894 | header { 895 | height: 2.75rem; 896 | background: var(--header-back-color); 897 | color: var(--header-fore-color); 898 | border-bottom: 0.0714285714rem solid var(--header-border-color); 899 | padding: calc(var(--universal-padding) / 4) 0; 900 | white-space: nowrap; 901 | overflow-x: auto; 902 | overflow-y: hidden; } 903 | header.row { 904 | box-sizing: content-box; } 905 | header .logo { 906 | color: var(--header-fore-color); 907 | font-size: 1.75rem; 908 | padding: var(--universal-padding) calc(2 * var(--universal-padding)); 909 | text-decoration: none; } 910 | header button, header [type="button"], header .button, header [role="button"] { 911 | box-sizing: border-box; 912 | position: relative; 913 | top: calc(0rem - var(--universal-padding) / 4); 914 | height: calc(3.1875rem + var(--universal-padding) / 2); 915 | background: var(--header-back-color); 916 | line-height: calc(3.1875rem - var(--universal-padding) * 1.5); 917 | text-align: center; 918 | color: var(--header-fore-color); 919 | border: 0; 920 | border-radius: 0; 921 | margin: 0; 922 | text-transform: uppercase; } 923 | header button:hover, header button:focus, header [type="button"]:hover, header [type="button"]:focus, header .button:hover, header .button:focus, header [role="button"]:hover, header [role="button"]:focus { 924 | background: var(--header-hover-back-color); } 925 | 926 | nav { 927 | background: var(--nav-back-color); 928 | color: var(--nav-fore-color); 929 | border: 0.0714285714rem solid var(--nav-border-color); 930 | border-radius: var(--universal-border-radius); 931 | margin: var(--universal-margin); } 932 | nav * { 933 | padding: var(--universal-padding) calc(1.5 * var(--universal-padding)); } 934 | nav a, nav a:visited { 935 | display: block; 936 | color: var(--nav-link-color); 937 | border-radius: var(--universal-border-radius); 938 | transition: background 0.3s; } 939 | nav a:hover, nav a:focus, nav a:visited:hover, nav a:visited:focus { 940 | text-decoration: none; 941 | background: var(--nav-hover-back-color); } 942 | nav .sublink-1 { 943 | position: relative; 944 | margin-left: calc(2 * var(--universal-padding)); } 945 | nav .sublink-1:before { 946 | position: absolute; 947 | left: calc(var(--universal-padding) - 1 * var(--universal-padding)); 948 | top: -0.0714285714rem; 949 | content: ''; 950 | height: 100%; 951 | border: 0.0714285714rem solid var(--nav-border-color); 952 | border-left: 0; } 953 | nav .sublink-2 { 954 | position: relative; 955 | margin-left: calc(4 * var(--universal-padding)); } 956 | nav .sublink-2:before { 957 | position: absolute; 958 | left: calc(var(--universal-padding) - 3 * var(--universal-padding)); 959 | top: -0.0714285714rem; 960 | content: ''; 961 | height: 100%; 962 | border: 0.0714285714rem solid var(--nav-border-color); 963 | border-left: 0; } 964 | 965 | footer { 966 | background: var(--footer-back-color); 967 | color: var(--footer-fore-color); 968 | border-top: 0.0714285714rem solid var(--footer-border-color); 969 | padding: calc(2 * var(--universal-padding)) var(--universal-padding); 970 | font-size: 0.875rem; } 971 | footer a, footer a:visited { 972 | color: var(--footer-link-color); } 973 | 974 | header.sticky { 975 | position: -webkit-sticky; 976 | position: sticky; 977 | z-index: 1101; 978 | top: 0; } 979 | 980 | footer.sticky { 981 | position: -webkit-sticky; 982 | position: sticky; 983 | z-index: 1101; 984 | bottom: 0; } 985 | 986 | .drawer-toggle:before { 987 | display: inline-block; 988 | position: relative; 989 | vertical-align: bottom; 990 | content: '\00a0\2261\00a0'; 991 | font-family: sans-serif; 992 | font-size: 1.5em; } 993 | @media screen and (min-width: 500px) { 994 | .drawer-toggle:not(.persistent) { 995 | display: none; } } 996 | 997 | [type="checkbox"].drawer { 998 | height: 1px; 999 | width: 1px; 1000 | margin: -1px; 1001 | overflow: hidden; 1002 | position: absolute; 1003 | clip: rect(0 0 0 0); 1004 | -webkit-clip-path: inset(100%); 1005 | clip-path: inset(100%); } 1006 | [type="checkbox"].drawer + * { 1007 | display: block; 1008 | box-sizing: border-box; 1009 | position: fixed; 1010 | top: 0; 1011 | width: 320px; 1012 | height: 100vh; 1013 | overflow-y: auto; 1014 | background: var(--drawer-back-color); 1015 | border: 0.0714285714rem solid var(--drawer-border-color); 1016 | border-radius: 0; 1017 | margin: 0; 1018 | z-index: 1110; 1019 | right: -320px; 1020 | transition: right 0.3s; } 1021 | [type="checkbox"].drawer + * .drawer-close { 1022 | position: absolute; 1023 | top: var(--universal-margin); 1024 | right: var(--universal-margin); 1025 | z-index: 1111; 1026 | width: 2rem; 1027 | height: 2rem; 1028 | border-radius: var(--universal-border-radius); 1029 | padding: var(--universal-padding); 1030 | margin: 0; 1031 | cursor: pointer; 1032 | transition: background 0.3s; } 1033 | [type="checkbox"].drawer + * .drawer-close:before { 1034 | display: block; 1035 | content: '\00D7'; 1036 | color: var(--drawer-close-color); 1037 | position: relative; 1038 | font-family: sans-serif; 1039 | font-size: 2rem; 1040 | line-height: 1; 1041 | text-align: center; } 1042 | [type="checkbox"].drawer + * .drawer-close:hover, [type="checkbox"].drawer + * .drawer-close:focus { 1043 | background: var(--drawer-hover-back-color); } 1044 | @media screen and (max-width: 320px) { 1045 | [type="checkbox"].drawer + * { 1046 | width: 100%; } } 1047 | [type="checkbox"].drawer:checked + * { 1048 | right: 0; } 1049 | @media screen and (min-width: 500px) { 1050 | [type="checkbox"].drawer:not(.persistent) + * { 1051 | position: static; 1052 | height: 100%; 1053 | z-index: 1100; } 1054 | [type="checkbox"].drawer:not(.persistent) + * .drawer-close { 1055 | display: none; } } 1056 | 1057 | /* 1058 | Definitions for the responsive table component. 1059 | */ 1060 | /* Table module CSS variable definitions. */ 1061 | :root { 1062 | --table-border-color: #03234b; 1063 | --table-border-separator-color: #03234b; 1064 | --table-head-back-color: #03234b; 1065 | --table-head-fore-color: #ffffff; 1066 | --table-body-back-color: #ffffff; 1067 | --table-body-fore-color: #03234b; 1068 | --table-body-alt-back-color: #f4f4f4; } 1069 | 1070 | table { 1071 | border-collapse: separate; 1072 | border-spacing: 0; 1073 | margin: 0; 1074 | display: flex; 1075 | flex: 0 1 auto; 1076 | flex-flow: row wrap; 1077 | padding: var(--universal-padding); 1078 | padding-top: 0; } 1079 | table caption { 1080 | font-size: 1rem; 1081 | margin: calc(2 * var(--universal-margin)) 0; 1082 | max-width: 100%; 1083 | flex: 0 0 100%; } 1084 | table thead, table tbody { 1085 | display: flex; 1086 | flex-flow: row wrap; 1087 | border: 0.0714285714rem solid var(--table-border-color); } 1088 | table thead { 1089 | z-index: 999; 1090 | border-radius: var(--universal-border-radius) var(--universal-border-radius) 0 0; 1091 | border-bottom: 0.0714285714rem solid var(--table-border-separator-color); } 1092 | table tbody { 1093 | border-top: 0; 1094 | margin-top: calc(0 - var(--universal-margin)); 1095 | border-radius: 0 0 var(--universal-border-radius) var(--universal-border-radius); } 1096 | table tr { 1097 | display: flex; 1098 | padding: 0; } 1099 | table th, table td { 1100 | padding: calc(0.5 * var(--universal-padding)); 1101 | font-size: 0.9rem; } 1102 | table th { 1103 | text-align: left; 1104 | background: var(--table-head-back-color); 1105 | color: var(--table-head-fore-color); } 1106 | table td { 1107 | background: var(--table-body-back-color); 1108 | color: var(--table-body-fore-color); 1109 | border-top: 0.0714285714rem solid var(--table-border-color); } 1110 | 1111 | table:not(.horizontal) { 1112 | overflow: auto; 1113 | max-height: 100%; } 1114 | table:not(.horizontal) thead, table:not(.horizontal) tbody { 1115 | max-width: 100%; 1116 | flex: 0 0 100%; } 1117 | table:not(.horizontal) tr { 1118 | flex-flow: row wrap; 1119 | flex: 0 0 100%; } 1120 | table:not(.horizontal) th, table:not(.horizontal) td { 1121 | flex: 1 0 0%; 1122 | overflow: hidden; 1123 | text-overflow: ellipsis; } 1124 | table:not(.horizontal) thead { 1125 | position: sticky; 1126 | top: 0; } 1127 | table:not(.horizontal) tbody tr:first-child td { 1128 | border-top: 0; } 1129 | 1130 | table.horizontal { 1131 | border: 0; } 1132 | table.horizontal thead, table.horizontal tbody { 1133 | border: 0; 1134 | flex: .2 0 0; 1135 | flex-flow: row nowrap; } 1136 | table.horizontal tbody { 1137 | overflow: auto; 1138 | justify-content: space-between; 1139 | flex: .8 0 0; 1140 | margin-left: 0; 1141 | padding-bottom: calc(var(--universal-padding) / 4); } 1142 | table.horizontal tr { 1143 | flex-direction: column; 1144 | flex: 1 0 auto; } 1145 | table.horizontal th, table.horizontal td { 1146 | width: auto; 1147 | border: 0; 1148 | border-bottom: 0.0714285714rem solid var(--table-border-color); } 1149 | table.horizontal th:not(:first-child), table.horizontal td:not(:first-child) { 1150 | border-top: 0; } 1151 | table.horizontal th { 1152 | text-align: right; 1153 | border-left: 0.0714285714rem solid var(--table-border-color); 1154 | border-right: 0.0714285714rem solid var(--table-border-separator-color); } 1155 | table.horizontal thead tr:first-child { 1156 | padding-left: 0; } 1157 | table.horizontal th:first-child, table.horizontal td:first-child { 1158 | border-top: 0.0714285714rem solid var(--table-border-color); } 1159 | table.horizontal tbody tr:last-child td { 1160 | border-right: 0.0714285714rem solid var(--table-border-color); } 1161 | table.horizontal tbody tr:last-child td:first-child { 1162 | border-top-right-radius: 0.25rem; } 1163 | table.horizontal tbody tr:last-child td:last-child { 1164 | border-bottom-right-radius: 0.25rem; } 1165 | table.horizontal thead tr:first-child th:first-child { 1166 | border-top-left-radius: 0.25rem; } 1167 | table.horizontal thead tr:first-child th:last-child { 1168 | border-bottom-left-radius: 0.25rem; } 1169 | 1170 | @media screen and (max-width: 499px) { 1171 | table, table.horizontal { 1172 | border-collapse: collapse; 1173 | border: 0; 1174 | width: 100%; 1175 | display: table; } 1176 | table thead, table th, table.horizontal thead, table.horizontal th { 1177 | border: 0; 1178 | height: 1px; 1179 | width: 1px; 1180 | margin: -1px; 1181 | overflow: hidden; 1182 | padding: 0; 1183 | position: absolute; 1184 | clip: rect(0 0 0 0); 1185 | -webkit-clip-path: inset(100%); 1186 | clip-path: inset(100%); } 1187 | table tbody, table.horizontal tbody { 1188 | border: 0; 1189 | display: table-row-group; } 1190 | table tr, table.horizontal tr { 1191 | display: block; 1192 | border: 0.0714285714rem solid var(--table-border-color); 1193 | border-radius: var(--universal-border-radius); 1194 | background: #ffffff; 1195 | padding: var(--universal-padding); 1196 | margin: var(--universal-margin); 1197 | margin-bottom: calc(1 * var(--universal-margin)); } 1198 | table th, table td, table.horizontal th, table.horizontal td { 1199 | width: auto; } 1200 | table td, table.horizontal td { 1201 | display: block; 1202 | border: 0; 1203 | text-align: right; } 1204 | table td:before, table.horizontal td:before { 1205 | content: attr(data-label); 1206 | float: left; 1207 | font-weight: 600; } 1208 | table th:first-child, table td:first-child, table.horizontal th:first-child, table.horizontal td:first-child { 1209 | border-top: 0; } 1210 | table tbody tr:last-child td, table.horizontal tbody tr:last-child td { 1211 | border-right: 0; } } 1212 | table tr:nth-of-type(2n) > td { 1213 | background: var(--table-body-alt-back-color); } 1214 | 1215 | @media screen and (max-width: 500px) { 1216 | table tr:nth-of-type(2n) { 1217 | background: var(--table-body-alt-back-color); } } 1218 | :root { 1219 | --table-body-hover-back-color: #90caf9; } 1220 | 1221 | table.hoverable tr:hover, table.hoverable tr:hover > td, table.hoverable tr:focus, table.hoverable tr:focus > td { 1222 | background: var(--table-body-hover-back-color); } 1223 | 1224 | @media screen and (max-width: 500px) { 1225 | table.hoverable tr:hover, table.hoverable tr:hover > td, table.hoverable tr:focus, table.hoverable tr:focus > td { 1226 | background: var(--table-body-hover-back-color); } } 1227 | /* 1228 | Definitions for contextual background elements, toasts and tooltips. 1229 | */ 1230 | /* Contextual module CSS variable definitions */ 1231 | :root { 1232 | --mark-back-color: #3cb4e6; 1233 | --mark-fore-color: #ffffff; } 1234 | 1235 | mark { 1236 | background: var(--mark-back-color); 1237 | color: var(--mark-fore-color); 1238 | font-size: 0.95em; 1239 | line-height: 1em; 1240 | border-radius: var(--universal-border-radius); 1241 | padding: calc(var(--universal-padding) / 4) var(--universal-padding); } 1242 | mark.inline-block { 1243 | display: inline-block; 1244 | font-size: 1em; 1245 | line-height: 1.4; 1246 | padding: calc(var(--universal-padding) / 2) var(--universal-padding); } 1247 | 1248 | :root { 1249 | --toast-back-color: #424242; 1250 | --toast-fore-color: #fafafa; } 1251 | 1252 | .toast { 1253 | position: fixed; 1254 | bottom: calc(var(--universal-margin) * 3); 1255 | left: 50%; 1256 | transform: translate(-50%, -50%); 1257 | z-index: 1111; 1258 | color: var(--toast-fore-color); 1259 | background: var(--toast-back-color); 1260 | border-radius: calc(var(--universal-border-radius) * 16); 1261 | padding: var(--universal-padding) calc(var(--universal-padding) * 3); } 1262 | 1263 | :root { 1264 | --tooltip-back-color: #212121; 1265 | --tooltip-fore-color: #fafafa; } 1266 | 1267 | .tooltip { 1268 | position: relative; 1269 | display: inline-block; } 1270 | .tooltip:before, .tooltip:after { 1271 | position: absolute; 1272 | opacity: 0; 1273 | clip: rect(0 0 0 0); 1274 | -webkit-clip-path: inset(100%); 1275 | clip-path: inset(100%); 1276 | transition: all 0.3s; 1277 | z-index: 1010; 1278 | left: 50%; } 1279 | .tooltip:not(.bottom):before, .tooltip:not(.bottom):after { 1280 | bottom: 75%; } 1281 | .tooltip.bottom:before, .tooltip.bottom:after { 1282 | top: 75%; } 1283 | .tooltip:hover:before, .tooltip:hover:after, .tooltip:focus:before, .tooltip:focus:after { 1284 | opacity: 1; 1285 | clip: auto; 1286 | -webkit-clip-path: inset(0%); 1287 | clip-path: inset(0%); } 1288 | .tooltip:before { 1289 | content: ''; 1290 | background: transparent; 1291 | border: var(--universal-margin) solid transparent; 1292 | left: calc(50% - var(--universal-margin)); } 1293 | .tooltip:not(.bottom):before { 1294 | border-top-color: #212121; } 1295 | .tooltip.bottom:before { 1296 | border-bottom-color: #212121; } 1297 | .tooltip:after { 1298 | content: attr(aria-label); 1299 | color: var(--tooltip-fore-color); 1300 | background: var(--tooltip-back-color); 1301 | border-radius: var(--universal-border-radius); 1302 | padding: var(--universal-padding); 1303 | white-space: nowrap; 1304 | transform: translateX(-50%); } 1305 | .tooltip:not(.bottom):after { 1306 | margin-bottom: calc(2 * var(--universal-margin)); } 1307 | .tooltip.bottom:after { 1308 | margin-top: calc(2 * var(--universal-margin)); } 1309 | 1310 | :root { 1311 | --modal-overlay-color: rgba(0, 0, 0, 0.45); 1312 | --modal-close-color: #e6007e; 1313 | --modal-close-hover-color: #ffe97f; } 1314 | 1315 | [type="checkbox"].modal { 1316 | height: 1px; 1317 | width: 1px; 1318 | margin: -1px; 1319 | overflow: hidden; 1320 | position: absolute; 1321 | clip: rect(0 0 0 0); 1322 | -webkit-clip-path: inset(100%); 1323 | clip-path: inset(100%); } 1324 | [type="checkbox"].modal + div { 1325 | position: fixed; 1326 | top: 0; 1327 | left: 0; 1328 | display: none; 1329 | width: 100vw; 1330 | height: 100vh; 1331 | background: var(--modal-overlay-color); } 1332 | [type="checkbox"].modal + div .card { 1333 | margin: 0 auto; 1334 | max-height: 50vh; 1335 | overflow: auto; } 1336 | [type="checkbox"].modal + div .card .modal-close { 1337 | position: absolute; 1338 | top: 0; 1339 | right: 0; 1340 | width: 1.75rem; 1341 | height: 1.75rem; 1342 | border-radius: var(--universal-border-radius); 1343 | padding: var(--universal-padding); 1344 | margin: 0; 1345 | cursor: pointer; 1346 | transition: background 0.3s; } 1347 | [type="checkbox"].modal + div .card .modal-close:before { 1348 | display: block; 1349 | content: '\00D7'; 1350 | color: var(--modal-close-color); 1351 | position: relative; 1352 | font-family: sans-serif; 1353 | font-size: 1.75rem; 1354 | line-height: 1; 1355 | text-align: center; } 1356 | [type="checkbox"].modal + div .card .modal-close:hover, [type="checkbox"].modal + div .card .modal-close:focus { 1357 | background: var(--modal-close-hover-color); } 1358 | [type="checkbox"].modal:checked + div { 1359 | display: flex; 1360 | flex: 0 1 auto; 1361 | z-index: 1200; } 1362 | [type="checkbox"].modal:checked + div .card .modal-close { 1363 | z-index: 1211; } 1364 | 1365 | :root { 1366 | --collapse-label-back-color: #03234b; 1367 | --collapse-label-fore-color: #ffffff; 1368 | --collapse-label-hover-back-color: #3cb4e6; 1369 | --collapse-selected-label-back-color: #3cb4e6; 1370 | --collapse-border-color: var(--collapse-label-back-color); 1371 | --collapse-selected-border-color: #ceecf8; 1372 | --collapse-content-back-color: #ffffff; 1373 | --collapse-selected-label-border-color: #3cb4e6; } 1374 | 1375 | .collapse { 1376 | width: calc(100% - 2 * var(--universal-margin)); 1377 | opacity: 1; 1378 | display: flex; 1379 | flex-direction: column; 1380 | margin: var(--universal-margin); 1381 | border-radius: var(--universal-border-radius); } 1382 | .collapse > [type="radio"], .collapse > [type="checkbox"] { 1383 | height: 1px; 1384 | width: 1px; 1385 | margin: -1px; 1386 | overflow: hidden; 1387 | position: absolute; 1388 | clip: rect(0 0 0 0); 1389 | -webkit-clip-path: inset(100%); 1390 | clip-path: inset(100%); } 1391 | .collapse > label { 1392 | flex-grow: 1; 1393 | display: inline-block; 1394 | height: 1.25rem; 1395 | cursor: pointer; 1396 | transition: background 0.2s; 1397 | color: var(--collapse-label-fore-color); 1398 | background: var(--collapse-label-back-color); 1399 | border: 0.0714285714rem solid var(--collapse-selected-border-color); 1400 | padding: calc(1.25 * var(--universal-padding)); } 1401 | .collapse > label:hover, .collapse > label:focus { 1402 | background: var(--collapse-label-hover-back-color); } 1403 | .collapse > label + div { 1404 | flex-basis: auto; 1405 | height: 1px; 1406 | width: 1px; 1407 | margin: -1px; 1408 | overflow: hidden; 1409 | position: absolute; 1410 | clip: rect(0 0 0 0); 1411 | -webkit-clip-path: inset(100%); 1412 | clip-path: inset(100%); 1413 | transition: max-height 0.3s; 1414 | max-height: 1px; } 1415 | .collapse > :checked + label { 1416 | background: var(--collapse-selected-label-back-color); 1417 | border-color: var(--collapse-selected-label-border-color); } 1418 | .collapse > :checked + label + div { 1419 | box-sizing: border-box; 1420 | position: relative; 1421 | width: 100%; 1422 | height: auto; 1423 | overflow: auto; 1424 | margin: 0; 1425 | background: var(--collapse-content-back-color); 1426 | border: 0.0714285714rem solid var(--collapse-selected-border-color); 1427 | border-top: 0; 1428 | padding: var(--universal-padding); 1429 | clip: auto; 1430 | -webkit-clip-path: inset(0%); 1431 | clip-path: inset(0%); 1432 | max-height: 100%; } 1433 | .collapse > label:not(:first-of-type) { 1434 | border-top: 0; } 1435 | .collapse > label:first-of-type { 1436 | border-radius: var(--universal-border-radius) var(--universal-border-radius) 0 0; } 1437 | .collapse > label:last-of-type:not(:first-of-type) { 1438 | border-radius: 0 0 var(--universal-border-radius) var(--universal-border-radius); } 1439 | .collapse > label:last-of-type:first-of-type { 1440 | border-radius: var(--universal-border-radius); } 1441 | .collapse > :checked:last-of-type:not(:first-of-type) + label { 1442 | border-radius: 0; } 1443 | .collapse > :checked:last-of-type + label + div { 1444 | border-radius: 0 0 var(--universal-border-radius) var(--universal-border-radius); } 1445 | 1446 | /* 1447 | Custom elements for contextual background elements, toasts and tooltips. 1448 | */ 1449 | mark.tertiary { 1450 | --mark-back-color: #3cb4e6; } 1451 | 1452 | mark.tag { 1453 | padding: calc(var(--universal-padding)/2) var(--universal-padding); 1454 | border-radius: 1em; } 1455 | 1456 | /* 1457 | Definitions for progress elements and spinners. 1458 | */ 1459 | /* Progress module CSS variable definitions */ 1460 | :root { 1461 | --progress-back-color: #3cb4e6; 1462 | --progress-fore-color: #555; } 1463 | 1464 | progress { 1465 | display: block; 1466 | vertical-align: baseline; 1467 | -webkit-appearance: none; 1468 | -moz-appearance: none; 1469 | appearance: none; 1470 | height: 0.75rem; 1471 | width: calc(100% - 2 * var(--universal-margin)); 1472 | margin: var(--universal-margin); 1473 | border: 0; 1474 | border-radius: calc(2 * var(--universal-border-radius)); 1475 | background: var(--progress-back-color); 1476 | color: var(--progress-fore-color); } 1477 | progress::-webkit-progress-value { 1478 | background: var(--progress-fore-color); 1479 | border-top-left-radius: calc(2 * var(--universal-border-radius)); 1480 | border-bottom-left-radius: calc(2 * var(--universal-border-radius)); } 1481 | progress::-webkit-progress-bar { 1482 | background: var(--progress-back-color); } 1483 | progress::-moz-progress-bar { 1484 | background: var(--progress-fore-color); 1485 | border-top-left-radius: calc(2 * var(--universal-border-radius)); 1486 | border-bottom-left-radius: calc(2 * var(--universal-border-radius)); } 1487 | progress[value="1000"]::-webkit-progress-value { 1488 | border-radius: calc(2 * var(--universal-border-radius)); } 1489 | progress[value="1000"]::-moz-progress-bar { 1490 | border-radius: calc(2 * var(--universal-border-radius)); } 1491 | progress.inline { 1492 | display: inline-block; 1493 | vertical-align: middle; 1494 | width: 60%; } 1495 | 1496 | :root { 1497 | --spinner-back-color: #ddd; 1498 | --spinner-fore-color: #555; } 1499 | 1500 | @keyframes spinner-donut-anim { 1501 | 0% { 1502 | transform: rotate(0deg); } 1503 | 100% { 1504 | transform: rotate(360deg); } } 1505 | .spinner { 1506 | display: inline-block; 1507 | margin: var(--universal-margin); 1508 | border: 0.25rem solid var(--spinner-back-color); 1509 | border-left: 0.25rem solid var(--spinner-fore-color); 1510 | border-radius: 50%; 1511 | width: 1.25rem; 1512 | height: 1.25rem; 1513 | animation: spinner-donut-anim 1.2s linear infinite; } 1514 | 1515 | /* 1516 | Custom elements for progress bars and spinners. 1517 | */ 1518 | progress.primary { 1519 | --progress-fore-color: #1976d2; } 1520 | 1521 | progress.secondary { 1522 | --progress-fore-color: #d32f2f; } 1523 | 1524 | progress.tertiary { 1525 | --progress-fore-color: #308732; } 1526 | 1527 | .spinner.primary { 1528 | --spinner-fore-color: #1976d2; } 1529 | 1530 | .spinner.secondary { 1531 | --spinner-fore-color: #d32f2f; } 1532 | 1533 | .spinner.tertiary { 1534 | --spinner-fore-color: #308732; } 1535 | 1536 | /* 1537 | Definitions for icons - powered by Feather (https://feathericons.com/). 1538 | */ 1539 | span[class^='icon-'] { 1540 | display: inline-block; 1541 | height: 1em; 1542 | width: 1em; 1543 | vertical-align: -0.125em; 1544 | background-size: contain; 1545 | margin: 0 calc(var(--universal-margin) / 4); } 1546 | span[class^='icon-'].secondary { 1547 | -webkit-filter: invert(25%); 1548 | filter: invert(25%); } 1549 | span[class^='icon-'].inverse { 1550 | -webkit-filter: invert(100%); 1551 | filter: invert(100%); } 1552 | 1553 | span.icon-alert { 1554 | background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='8' x2='12' y2='12'%3E%3C/line%3E%3Cline x1='12' y1='16' x2='12' y2='16'%3E%3C/line%3E%3C/svg%3E"); } 1555 | span.icon-bookmark { 1556 | background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M19 21l-7-5-7 5V5a2 2 0 0 1 2-2h10a2 2 0 0 1 2 2z'%3E%3C/path%3E%3C/svg%3E"); } 1557 | span.icon-calendar { 1558 | background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='3' y='4' width='18' height='18' rx='2' ry='2'%3E%3C/rect%3E%3Cline x1='16' y1='2' x2='16' y2='6'%3E%3C/line%3E%3Cline x1='8' y1='2' x2='8' y2='6'%3E%3C/line%3E%3Cline x1='3' y1='10' x2='21' y2='10'%3E%3C/line%3E%3C/svg%3E"); } 1559 | span.icon-credit { 1560 | background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='1' y='4' width='22' height='16' rx='2' ry='2'%3E%3C/rect%3E%3Cline x1='1' y1='10' x2='23' y2='10'%3E%3C/line%3E%3C/svg%3E"); } 1561 | span.icon-edit { 1562 | background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M20 14.66V20a2 2 0 0 1-2 2H4a2 2 0 0 1-2-2V6a2 2 0 0 1 2-2h5.34'%3E%3C/path%3E%3Cpolygon points='18 2 22 6 12 16 8 16 8 12 18 2'%3E%3C/polygon%3E%3C/svg%3E"); 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} 1569 | span.icon-info { 1570 | background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='16' x2='12' y2='12'%3E%3C/line%3E%3Cline x1='12' y1='8' x2='12' y2='8'%3E%3C/line%3E%3C/svg%3E"); } 1571 | span.icon-lock { 1572 | background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='3' y='11' width='18' height='11' rx='2' ry='2'%3E%3C/rect%3E%3Cpath d='M7 11V7a5 5 0 0 1 10 0v4'%3E%3C/path%3E%3C/svg%3E"); } 1573 | span.icon-mail { 1574 | background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M4 4h16c1.1 0 2 .9 2 2v12c0 1.1-.9 2-2 2H4c-1.1 0-2-.9-2-2V6c0-1.1.9-2 2-2z'%3E%3C/path%3E%3Cpolyline points='22,6 12,13 2,6'%3E%3C/polyline%3E%3C/svg%3E"); } 1575 | span.icon-location { 1576 | background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M21 10c0 7-9 13-9 13s-9-6-9-13a9 9 0 0 1 18 0z'%3E%3C/path%3E%3Ccircle cx='12' cy='10' r='3'%3E%3C/circle%3E%3C/svg%3E"); } 1577 | span.icon-phone { 1578 | background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M22 16.92v3a2 2 0 0 1-2.18 2 19.79 19.79 0 0 1-8.63-3.07 19.5 19.5 0 0 1-6-6 19.79 19.79 0 0 1-3.07-8.67A2 2 0 0 1 4.11 2h3a2 2 0 0 1 2 1.72 12.84 12.84 0 0 0 .7 2.81 2 2 0 0 1-.45 2.11L8.09 9.91a16 16 0 0 0 6 6l1.27-1.27a2 2 0 0 1 2.11-.45 12.84 12.84 0 0 0 2.81.7A2 2 0 0 1 22 16.92z'%3E%3C/path%3E%3C/svg%3E"); } 1579 | span.icon-rss { 1580 | background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M4 11a9 9 0 0 1 9 9'%3E%3C/path%3E%3Cpath d='M4 4a16 16 0 0 1 16 16'%3E%3C/path%3E%3Ccircle cx='5' cy='19' r='1'%3E%3C/circle%3E%3C/svg%3E"); } 1581 | span.icon-search { 1582 | background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='11' cy='11' r='8'%3E%3C/circle%3E%3Cline x1='21' y1='21' x2='16.65' y2='16.65'%3E%3C/line%3E%3C/svg%3E"); } 1583 | span.icon-settings { 1584 | background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='3'%3E%3C/circle%3E%3Cpath d='M19.4 15a1.65 1.65 0 0 0 .33 1.82l.06.06a2 2 0 0 1 0 2.83 2 2 0 0 1-2.83 0l-.06-.06a1.65 1.65 0 0 0-1.82-.33 1.65 1.65 0 0 0-1 1.51V21a2 2 0 0 1-2 2 2 2 0 0 1-2-2v-.09A1.65 1.65 0 0 0 9 19.4a1.65 1.65 0 0 0-1.82.33l-.06.06a2 2 0 0 1-2.83 0 2 2 0 0 1 0-2.83l.06-.06a1.65 1.65 0 0 0 .33-1.82 1.65 1.65 0 0 0-1.51-1H3a2 2 0 0 1-2-2 2 2 0 0 1 2-2h.09A1.65 1.65 0 0 0 4.6 9a1.65 1.65 0 0 0-.33-1.82l-.06-.06a2 2 0 0 1 0-2.83 2 2 0 0 1 2.83 0l.06.06a1.65 1.65 0 0 0 1.82.33H9a1.65 1.65 0 0 0 1-1.51V3a2 2 0 0 1 2-2 2 2 0 0 1 2 2v.09a1.65 1.65 0 0 0 1 1.51 1.65 1.65 0 0 0 1.82-.33l.06-.06a2 2 0 0 1 2.83 0 2 2 0 0 1 0 2.83l-.06.06a1.65 1.65 0 0 0-.33 1.82V9a1.65 1.65 0 0 0 1.51 1H21a2 2 0 0 1 2 2 2 2 0 0 1-2 2h-.09a1.65 1.65 0 0 0-1.51 1z'%3E%3C/path%3E%3C/svg%3E"); } 1585 | span.icon-share { 1586 | background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='18' cy='5' r='3'%3E%3C/circle%3E%3Ccircle cx='6' cy='12' r='3'%3E%3C/circle%3E%3Ccircle cx='18' cy='19' r='3'%3E%3C/circle%3E%3Cline x1='8.59' y1='13.51' x2='15.42' y2='17.49'%3E%3C/line%3E%3Cline x1='15.41' y1='6.51' x2='8.59' y2='10.49'%3E%3C/line%3E%3C/svg%3E"); } 1587 | span.icon-cart { 1588 | background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='9' cy='21' r='1'%3E%3C/circle%3E%3Ccircle cx='20' cy='21' r='1'%3E%3C/circle%3E%3Cpath d='M1 1h4l2.68 13.39a2 2 0 0 0 2 1.61h9.72a2 2 0 0 0 2-1.61L23 6H6'%3E%3C/path%3E%3C/svg%3E"); } 1589 | span.icon-upload { 1590 | background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M21 15v4a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2v-4'%3E%3C/path%3E%3Cpolyline points='17 8 12 3 7 8'%3E%3C/polyline%3E%3Cline x1='12' y1='3' x2='12' y2='15'%3E%3C/line%3E%3C/svg%3E"); } 1591 | span.icon-user { 1592 | background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M20 21v-2a4 4 0 0 0-4-4H8a4 4 0 0 0-4 4v2'%3E%3C/path%3E%3Ccircle cx='12' cy='7' r='4'%3E%3C/circle%3E%3C/svg%3E"); } 1593 | 1594 | /* 1595 | Definitions for STMicroelectronics icons (https://brandportal.st.com/document/26). 1596 | */ 1597 | span.icon-st-update { 1598 | background-image: url("Update.svg"); } 1599 | span.icon-st-add { 1600 | background-image: url("Add button.svg"); } 1601 | 1602 | /* 1603 | Definitions for utilities and helper classes. 1604 | */ 1605 | /* Utility module CSS variable definitions */ 1606 | :root { 1607 | --generic-border-color: rgba(0, 0, 0, 0.3); 1608 | --generic-box-shadow: 0 0.2857142857rem 0.2857142857rem 0 rgba(0, 0, 0, 0.125), 0 0.1428571429rem 0.1428571429rem -0.1428571429rem rgba(0, 0, 0, 0.125); } 1609 | 1610 | .hidden { 1611 | display: none !important; } 1612 | 1613 | .visually-hidden { 1614 | position: absolute !important; 1615 | width: 1px !important; 1616 | height: 1px !important; 1617 | margin: -1px !important; 1618 | border: 0 !important; 1619 | padding: 0 !important; 1620 | clip: rect(0 0 0 0) !important; 1621 | -webkit-clip-path: inset(100%) !important; 1622 | clip-path: inset(100%) !important; 1623 | overflow: hidden !important; } 1624 | 1625 | .bordered { 1626 | border: 0.0714285714rem solid var(--generic-border-color) !important; } 1627 | 1628 | .rounded { 1629 | border-radius: var(--universal-border-radius) !important; } 1630 | 1631 | .circular { 1632 | border-radius: 50% !important; } 1633 | 1634 | .shadowed { 1635 | box-shadow: var(--generic-box-shadow) !important; } 1636 | 1637 | .responsive-margin { 1638 | margin: calc(var(--universal-margin) / 4) !important; } 1639 | @media screen and (min-width: 500px) { 1640 | .responsive-margin { 1641 | margin: calc(var(--universal-margin) / 2) !important; } } 1642 | @media screen and (min-width: 1280px) { 1643 | .responsive-margin { 1644 | margin: var(--universal-margin) !important; } } 1645 | 1646 | .responsive-padding { 1647 | padding: calc(var(--universal-padding) / 4) !important; } 1648 | @media screen and (min-width: 500px) { 1649 | .responsive-padding { 1650 | padding: calc(var(--universal-padding) / 2) !important; } } 1651 | @media screen and (min-width: 1280px) { 1652 | .responsive-padding { 1653 | padding: var(--universal-padding) !important; } } 1654 | 1655 | @media screen and (max-width: 499px) { 1656 | .hidden-sm { 1657 | display: none !important; } } 1658 | @media screen and (min-width: 500px) and (max-width: 1279px) { 1659 | .hidden-md { 1660 | display: none !important; } } 1661 | @media screen and (min-width: 1280px) { 1662 | .hidden-lg { 1663 | display: none !important; } } 1664 | @media screen and (max-width: 499px) { 1665 | .visually-hidden-sm { 1666 | position: absolute !important; 1667 | width: 1px !important; 1668 | height: 1px !important; 1669 | margin: -1px !important; 1670 | border: 0 !important; 1671 | padding: 0 !important; 1672 | clip: rect(0 0 0 0) !important; 1673 | -webkit-clip-path: inset(100%) !important; 1674 | clip-path: inset(100%) !important; 1675 | overflow: hidden !important; } } 1676 | @media screen and (min-width: 500px) and (max-width: 1279px) { 1677 | .visually-hidden-md { 1678 | position: absolute !important; 1679 | width: 1px !important; 1680 | height: 1px !important; 1681 | margin: -1px !important; 1682 | border: 0 !important; 1683 | padding: 0 !important; 1684 | clip: rect(0 0 0 0) !important; 1685 | -webkit-clip-path: inset(100%) !important; 1686 | clip-path: inset(100%) !important; 1687 | overflow: hidden !important; } } 1688 | @media screen and (min-width: 1280px) { 1689 | .visually-hidden-lg { 1690 | position: absolute !important; 1691 | width: 1px !important; 1692 | height: 1px !important; 1693 | margin: -1px !important; 1694 | border: 0 !important; 1695 | padding: 0 !important; 1696 | clip: rect(0 0 0 0) !important; 1697 | -webkit-clip-path: inset(100%) !important; 1698 | clip-path: inset(100%) !important; 1699 | overflow: hidden !important; } } 1700 | 1701 | /*# sourceMappingURL=mini-custom.css.map */ 1702 | 1703 | img[alt="ST logo"] { display: block; margin: auto; width: 75%; max-width: 250px; min-width: 71px; } 1704 | img[alt="Cube logo"] { float: right; width: 30%; max-width: 10rem; min-width: 8rem; padding-right: 1rem;} 1705 | 1706 | .figure { 1707 | display: block; 1708 | margin-left: auto; 1709 | margin-right: auto; 1710 | text-align: center; 1711 | } -------------------------------------------------------------------------------- /_htmresc/st_logo_2020.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/STMicroelectronics/lis2dh12-pid/e163fed1a0a85f6c1e34e16d40ef7cc58ba76ccb/_htmresc/st_logo_2020.png -------------------------------------------------------------------------------- /lis2dh12_reg.c: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file lis2dh12_reg.c 4 | * @author Sensors Software Solution Team 5 | * @brief LIS2DH12 driver file 6 | ****************************************************************************** 7 | * @attention 8 | * 9 | *

© Copyright (c) 2021 STMicroelectronics. 10 | * All rights reserved.

11 | * 12 | * This software component is licensed by ST under BSD 3-Clause license, 13 | * the "License"; You may not use this file except in compliance with the 14 | * License. You may obtain a copy of the License at: 15 | * opensource.org/licenses/BSD-3-Clause 16 | * 17 | ****************************************************************************** 18 | */ 19 | 20 | #include "lis2dh12_reg.h" 21 | 22 | /** 23 | * @defgroup LIS2DH12 24 | * @brief This file provides a set of functions needed to drive the 25 | * lis2dh12 enanced inertial module. 26 | * @{ 27 | * 28 | */ 29 | 30 | /** 31 | * @defgroup LIS2DH12_Interfaces_Functions 32 | * @brief This section provide a set of functions used to read and 33 | * write a generic register of the device. 34 | * MANDATORY: return 0 -> no Error. 35 | * @{ 36 | * 37 | */ 38 | 39 | /** 40 | * @brief Read generic device register 41 | * 42 | * @param ctx read / write interface definitions(ptr) 43 | * @param reg register to read 44 | * @param data pointer to buffer that store the data read(ptr) 45 | * @param len number of consecutive register to read 46 | * @retval interface status (MANDATORY: return 0 -> no Error) 47 | * 48 | */ 49 | int32_t __weak lis2dh12_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, 50 | uint8_t *data, 51 | uint16_t len) 52 | { 53 | int32_t ret; 54 | 55 | if (ctx == NULL) 56 | { 57 | return -1; 58 | } 59 | 60 | ret = ctx->read_reg(ctx->handle, reg, data, len); 61 | 62 | return ret; 63 | } 64 | 65 | /** 66 | * @brief Write generic device register 67 | * 68 | * @param ctx read / write interface definitions(ptr) 69 | * @param reg register to write 70 | * @param data pointer to data to write in register reg(ptr) 71 | * @param len number of consecutive register to write 72 | * @retval interface status (MANDATORY: return 0 -> no Error) 73 | * 74 | */ 75 | int32_t __weak lis2dh12_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, 76 | uint8_t *data, 77 | uint16_t len) 78 | { 79 | int32_t ret; 80 | 81 | if (ctx == NULL) 82 | { 83 | return -1; 84 | } 85 | 86 | ret = ctx->write_reg(ctx->handle, reg, data, len); 87 | 88 | return ret; 89 | } 90 | 91 | /** 92 | * @} 93 | * 94 | */ 95 | 96 | /** 97 | * @defgroup LIS2DH12_Sensitivity 98 | * @brief These functions convert raw-data into engineering units. 99 | * @{ 100 | * 101 | */ 102 | 103 | float_t lis2dh12_from_fs2_hr_to_mg(int16_t lsb) 104 | { 105 | return ((float_t)lsb / 16.0f) * 1.0f; 106 | } 107 | 108 | float_t lis2dh12_from_fs4_hr_to_mg(int16_t lsb) 109 | { 110 | return ((float_t)lsb / 16.0f) * 2.0f; 111 | } 112 | 113 | float_t lis2dh12_from_fs8_hr_to_mg(int16_t lsb) 114 | { 115 | return ((float_t)lsb / 16.0f) * 4.0f; 116 | } 117 | 118 | float_t lis2dh12_from_fs16_hr_to_mg(int16_t lsb) 119 | { 120 | return ((float_t)lsb / 16.0f) * 12.0f; 121 | } 122 | 123 | float_t lis2dh12_from_lsb_hr_to_celsius(int16_t lsb) 124 | { 125 | return (((float_t)lsb / 64.0f) / 4.0f) + 25.0f; 126 | } 127 | 128 | float_t lis2dh12_from_fs2_nm_to_mg(int16_t lsb) 129 | { 130 | return ((float_t)lsb / 64.0f) * 4.0f; 131 | } 132 | 133 | float_t lis2dh12_from_fs4_nm_to_mg(int16_t lsb) 134 | { 135 | return ((float_t)lsb / 64.0f) * 8.0f; 136 | } 137 | 138 | float_t lis2dh12_from_fs8_nm_to_mg(int16_t lsb) 139 | { 140 | return ((float_t)lsb / 64.0f) * 16.0f; 141 | } 142 | 143 | float_t lis2dh12_from_fs16_nm_to_mg(int16_t lsb) 144 | { 145 | return ((float_t)lsb / 64.0f) * 48.0f; 146 | } 147 | 148 | float_t lis2dh12_from_lsb_nm_to_celsius(int16_t lsb) 149 | { 150 | return (((float_t)lsb / 64.0f) / 4.0f) + 25.0f; 151 | } 152 | 153 | float_t lis2dh12_from_fs2_lp_to_mg(int16_t lsb) 154 | { 155 | return ((float_t)lsb / 256.0f) * 16.0f; 156 | } 157 | 158 | float_t lis2dh12_from_fs4_lp_to_mg(int16_t lsb) 159 | { 160 | return ((float_t)lsb / 256.0f) * 32.0f; 161 | } 162 | 163 | float_t lis2dh12_from_fs8_lp_to_mg(int16_t lsb) 164 | { 165 | return ((float_t)lsb / 256.0f) * 64.0f; 166 | } 167 | 168 | float_t lis2dh12_from_fs16_lp_to_mg(int16_t lsb) 169 | { 170 | return ((float_t)lsb / 256.0f) * 192.0f; 171 | } 172 | 173 | float_t lis2dh12_from_lsb_lp_to_celsius(int16_t lsb) 174 | { 175 | return (((float_t)lsb / 256.0f) * 1.0f) + 25.0f; 176 | } 177 | 178 | /** 179 | * @} 180 | * 181 | */ 182 | 183 | /** 184 | * @defgroup LIS2DH12_Data_generation 185 | * @brief This section group all the functions concerning data generation. 186 | * @{ 187 | * 188 | */ 189 | 190 | /** 191 | * @brief Temperature status register.[get] 192 | * 193 | * @param ctx read / write interface definitions 194 | * @param buff buffer that stores data read 195 | * @retval interface status (MANDATORY: return 0 -> no Error) 196 | * 197 | */ 198 | int32_t lis2dh12_temp_status_reg_get(const stmdev_ctx_t *ctx, uint8_t *buff) 199 | { 200 | int32_t ret; 201 | 202 | ret = lis2dh12_read_reg(ctx, LIS2DH12_STATUS_REG_AUX, buff, 1); 203 | 204 | return ret; 205 | } 206 | /** 207 | * @brief Temperature data available.[get] 208 | * 209 | * @param ctx read / write interface definitions 210 | * @param val change the values of tda in reg STATUS_REG_AUX 211 | * @retval interface status (MANDATORY: return 0 -> no Error) 212 | * 213 | */ 214 | int32_t lis2dh12_temp_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) 215 | { 216 | lis2dh12_status_reg_aux_t status_reg_aux; 217 | int32_t ret; 218 | 219 | ret = lis2dh12_read_reg(ctx, LIS2DH12_STATUS_REG_AUX, 220 | (uint8_t *)&status_reg_aux, 1); 221 | *val = status_reg_aux.tda; 222 | 223 | return ret; 224 | } 225 | /** 226 | * @brief Temperature data overrun.[get] 227 | * 228 | * @param ctx read / write interface definitions 229 | * @param val change the values of tor in reg STATUS_REG_AUX 230 | * @retval interface status (MANDATORY: return 0 -> no Error) 231 | * 232 | */ 233 | int32_t lis2dh12_temp_data_ovr_get(const stmdev_ctx_t *ctx, uint8_t *val) 234 | { 235 | lis2dh12_status_reg_aux_t status_reg_aux; 236 | int32_t ret; 237 | 238 | ret = lis2dh12_read_reg(ctx, LIS2DH12_STATUS_REG_AUX, 239 | (uint8_t *)&status_reg_aux, 1); 240 | *val = status_reg_aux.tor; 241 | 242 | return ret; 243 | } 244 | /** 245 | * @brief Temperature output value.[get] 246 | * 247 | * @param ctx read / write interface definitions 248 | * @param buff buffer that stores data read 249 | * @retval interface status (MANDATORY: return 0 -> no Error) 250 | * 251 | */ 252 | int32_t lis2dh12_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val) 253 | { 254 | uint8_t buff[2]; 255 | int32_t ret; 256 | 257 | ret = lis2dh12_read_reg(ctx, LIS2DH12_OUT_TEMP_L, buff, 2); 258 | *val = (int16_t)buff[1]; 259 | *val = (*val * 256) + (int16_t)buff[0]; 260 | 261 | return ret; 262 | } 263 | /** 264 | * @brief Temperature sensor enable.[set] 265 | * 266 | * @param ctx read / write interface definitions 267 | * @param val change the values of temp_en in reg TEMP_CFG_REG 268 | * @retval interface status (MANDATORY: return 0 -> no Error) 269 | * 270 | */ 271 | int32_t lis2dh12_temperature_meas_set(const stmdev_ctx_t *ctx, 272 | lis2dh12_temp_en_t val) 273 | { 274 | lis2dh12_temp_cfg_reg_t temp_cfg_reg; 275 | int32_t ret; 276 | 277 | ret = lis2dh12_read_reg(ctx, LIS2DH12_TEMP_CFG_REG, 278 | (uint8_t *)&temp_cfg_reg, 1); 279 | 280 | if (ret == 0) 281 | { 282 | temp_cfg_reg.temp_en = (uint8_t) val; 283 | ret = lis2dh12_write_reg(ctx, LIS2DH12_TEMP_CFG_REG, 284 | (uint8_t *)&temp_cfg_reg, 1); 285 | } 286 | 287 | return ret; 288 | } 289 | 290 | /** 291 | * @brief Temperature sensor enable.[get] 292 | * 293 | * @param ctx read / write interface definitions 294 | * @param val get the values of temp_en in reg TEMP_CFG_REG 295 | * @retval interface status (MANDATORY: return 0 -> no Error) 296 | * 297 | */ 298 | int32_t lis2dh12_temperature_meas_get(const stmdev_ctx_t *ctx, 299 | lis2dh12_temp_en_t *val) 300 | { 301 | lis2dh12_temp_cfg_reg_t temp_cfg_reg; 302 | int32_t ret; 303 | 304 | ret = lis2dh12_read_reg(ctx, LIS2DH12_TEMP_CFG_REG, 305 | (uint8_t *)&temp_cfg_reg, 1); 306 | 307 | switch (temp_cfg_reg.temp_en) 308 | { 309 | case LIS2DH12_TEMP_DISABLE: 310 | *val = LIS2DH12_TEMP_DISABLE; 311 | break; 312 | 313 | case LIS2DH12_TEMP_ENABLE: 314 | *val = LIS2DH12_TEMP_ENABLE; 315 | break; 316 | 317 | default: 318 | *val = LIS2DH12_TEMP_DISABLE; 319 | break; 320 | } 321 | 322 | return ret; 323 | } 324 | 325 | /** 326 | * @brief Operating mode selection.[set] 327 | * 328 | * @param ctx read / write interface definitions 329 | * @param val change the values of lpen in reg CTRL_REG1 330 | * and HR in reg CTRL_REG4 331 | * @retval interface status (MANDATORY: return 0 -> no Error) 332 | * 333 | */ 334 | int32_t lis2dh12_operating_mode_set(const stmdev_ctx_t *ctx, 335 | lis2dh12_op_md_t val) 336 | { 337 | lis2dh12_ctrl_reg1_t ctrl_reg1; 338 | lis2dh12_ctrl_reg4_t ctrl_reg4; 339 | int32_t ret; 340 | 341 | ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG1, 342 | (uint8_t *)&ctrl_reg1, 1); 343 | 344 | if (ret == 0) 345 | { 346 | ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG4, 347 | (uint8_t *)&ctrl_reg4, 1); 348 | } 349 | 350 | if (ret == 0) 351 | { 352 | if (val == LIS2DH12_HR_12bit) 353 | { 354 | ctrl_reg1.lpen = 0; 355 | ctrl_reg4.hr = 1; 356 | } 357 | 358 | if (val == LIS2DH12_NM_10bit) 359 | { 360 | ctrl_reg1.lpen = 0; 361 | ctrl_reg4.hr = 0; 362 | } 363 | 364 | if (val == LIS2DH12_LP_8bit) 365 | { 366 | ctrl_reg1.lpen = 1; 367 | ctrl_reg4.hr = 0; 368 | } 369 | 370 | ret = lis2dh12_write_reg(ctx, LIS2DH12_CTRL_REG1, 371 | (uint8_t *)&ctrl_reg1, 1); 372 | } 373 | 374 | if (ret == 0) 375 | { 376 | ret = lis2dh12_write_reg(ctx, LIS2DH12_CTRL_REG4, 377 | (uint8_t *)&ctrl_reg4, 1); 378 | } 379 | 380 | return ret; 381 | } 382 | 383 | /** 384 | * @brief Operating mode selection.[get] 385 | * 386 | * @param ctx read / write interface definitions 387 | * @param val change the values of lpen in reg CTRL_REG1 388 | * @retval interface status (MANDATORY: return 0 -> no Error) 389 | * 390 | */ 391 | int32_t lis2dh12_operating_mode_get(const stmdev_ctx_t *ctx, 392 | lis2dh12_op_md_t *val) 393 | { 394 | lis2dh12_ctrl_reg1_t ctrl_reg1; 395 | lis2dh12_ctrl_reg4_t ctrl_reg4; 396 | int32_t ret; 397 | 398 | ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG1, 399 | (uint8_t *)&ctrl_reg1, 1); 400 | 401 | if (ret == 0) 402 | { 403 | ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG4, 404 | (uint8_t *)&ctrl_reg4, 1); 405 | 406 | if (ctrl_reg1.lpen == PROPERTY_ENABLE) 407 | { 408 | *val = LIS2DH12_LP_8bit; 409 | } 410 | 411 | else if (ctrl_reg4.hr == PROPERTY_ENABLE) 412 | { 413 | *val = LIS2DH12_HR_12bit; 414 | } 415 | 416 | else 417 | { 418 | *val = LIS2DH12_NM_10bit; 419 | } 420 | } 421 | 422 | return ret; 423 | } 424 | 425 | /** 426 | * @brief Output data rate selection.[set] 427 | * 428 | * @param ctx read / write interface definitions 429 | * @param val change the values of odr in reg CTRL_REG1 430 | * @retval interface status (MANDATORY: return 0 -> no Error) 431 | * 432 | */ 433 | int32_t lis2dh12_data_rate_set(const stmdev_ctx_t *ctx, lis2dh12_odr_t val) 434 | { 435 | lis2dh12_ctrl_reg1_t ctrl_reg1; 436 | int32_t ret; 437 | 438 | ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG1, 439 | (uint8_t *)&ctrl_reg1, 1); 440 | 441 | if (ret == 0) 442 | { 443 | ctrl_reg1.odr = (uint8_t)val; 444 | ret = lis2dh12_write_reg(ctx, LIS2DH12_CTRL_REG1, 445 | (uint8_t *)&ctrl_reg1, 1); 446 | } 447 | 448 | return ret; 449 | } 450 | 451 | /** 452 | * @brief Output data rate selection.[get] 453 | * 454 | * @param ctx read / write interface definitions 455 | * @param val get the values of odr in reg CTRL_REG1 456 | * @retval interface status (MANDATORY: return 0 -> no Error) 457 | * 458 | */ 459 | int32_t lis2dh12_data_rate_get(const stmdev_ctx_t *ctx, lis2dh12_odr_t *val) 460 | { 461 | lis2dh12_ctrl_reg1_t ctrl_reg1; 462 | int32_t ret; 463 | 464 | ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG1, 465 | (uint8_t *)&ctrl_reg1, 1); 466 | 467 | switch (ctrl_reg1.odr) 468 | { 469 | case LIS2DH12_POWER_DOWN: 470 | *val = LIS2DH12_POWER_DOWN; 471 | break; 472 | 473 | case LIS2DH12_ODR_1Hz: 474 | *val = LIS2DH12_ODR_1Hz; 475 | break; 476 | 477 | case LIS2DH12_ODR_10Hz: 478 | *val = LIS2DH12_ODR_10Hz; 479 | break; 480 | 481 | case LIS2DH12_ODR_25Hz: 482 | *val = LIS2DH12_ODR_25Hz; 483 | break; 484 | 485 | case LIS2DH12_ODR_50Hz: 486 | *val = LIS2DH12_ODR_50Hz; 487 | break; 488 | 489 | case LIS2DH12_ODR_100Hz: 490 | *val = LIS2DH12_ODR_100Hz; 491 | break; 492 | 493 | case LIS2DH12_ODR_200Hz: 494 | *val = LIS2DH12_ODR_200Hz; 495 | break; 496 | 497 | case LIS2DH12_ODR_400Hz: 498 | *val = LIS2DH12_ODR_400Hz; 499 | break; 500 | 501 | case LIS2DH12_ODR_1kHz620_LP: 502 | *val = LIS2DH12_ODR_1kHz620_LP; 503 | break; 504 | 505 | case LIS2DH12_ODR_5kHz376_LP_1kHz344_NM_HP: 506 | *val = LIS2DH12_ODR_5kHz376_LP_1kHz344_NM_HP; 507 | break; 508 | 509 | default: 510 | *val = LIS2DH12_POWER_DOWN; 511 | break; 512 | } 513 | 514 | return ret; 515 | } 516 | 517 | /** 518 | * @brief High pass data from internal filter sent to output register 519 | * and FIFO. 520 | * 521 | * @param ctx read / write interface definitions 522 | * @param val change the values of fds in reg CTRL_REG2 523 | * @retval interface status (MANDATORY: return 0 -> no Error) 524 | * 525 | */ 526 | int32_t lis2dh12_high_pass_on_outputs_set(const stmdev_ctx_t *ctx, 527 | uint8_t val) 528 | { 529 | lis2dh12_ctrl_reg2_t ctrl_reg2; 530 | int32_t ret; 531 | 532 | ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG2, 533 | (uint8_t *)&ctrl_reg2, 1); 534 | 535 | if (ret == 0) 536 | { 537 | ctrl_reg2.fds = val; 538 | ret = lis2dh12_write_reg(ctx, LIS2DH12_CTRL_REG2, 539 | (uint8_t *)&ctrl_reg2, 1); 540 | } 541 | 542 | return ret; 543 | } 544 | 545 | /** 546 | * @brief High pass data from internal filter sent to output register 547 | * and FIFO.[get] 548 | * 549 | * @param ctx read / write interface definitions 550 | * @param val change the values of fds in reg CTRL_REG2 551 | * @retval interface status (MANDATORY: return 0 -> no Error) 552 | * 553 | */ 554 | int32_t lis2dh12_high_pass_on_outputs_get(const stmdev_ctx_t *ctx, 555 | uint8_t *val) 556 | { 557 | lis2dh12_ctrl_reg2_t ctrl_reg2; 558 | int32_t ret; 559 | 560 | ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG2, 561 | (uint8_t *)&ctrl_reg2, 1); 562 | *val = (uint8_t)ctrl_reg2.fds; 563 | 564 | return ret; 565 | } 566 | 567 | /** 568 | * @brief High-pass filter cutoff frequency selection.[set] 569 | * 570 | * HPCF[2:1]\ft @1Hz @10Hz @25Hz @50Hz @100Hz @200Hz @400Hz @1kHz6 ft@5kHz 571 | * AGGRESSIVE 0.02Hz 0.2Hz 0.5Hz 1Hz 2Hz 4Hz 8Hz 32Hz 100Hz 572 | * STRONG 0.008Hz 0.08Hz 0.2Hz 0.5Hz 1Hz 2Hz 4Hz 16Hz 50Hz 573 | * MEDIUM 0.004Hz 0.04Hz 0.1Hz 0.2Hz 0.5Hz 1Hz 2Hz 8Hz 25Hz 574 | * LIGHT 0.002Hz 0.02Hz 0.05Hz 0.1Hz 0.2Hz 0.5Hz 1Hz 4Hz 12Hz 575 | * 576 | * @param ctx read / write interface definitions 577 | * @param val change the values of hpcf in reg CTRL_REG2 578 | * @retval interface status (MANDATORY: return 0 -> no Error) 579 | * 580 | */ 581 | int32_t lis2dh12_high_pass_bandwidth_set(const stmdev_ctx_t *ctx, 582 | lis2dh12_hpcf_t val) 583 | { 584 | lis2dh12_ctrl_reg2_t ctrl_reg2; 585 | int32_t ret; 586 | 587 | ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG2, 588 | (uint8_t *)&ctrl_reg2, 1); 589 | 590 | if (ret == 0) 591 | { 592 | ctrl_reg2.hpcf = (uint8_t)val; 593 | ret = lis2dh12_write_reg(ctx, LIS2DH12_CTRL_REG2, 594 | (uint8_t *)&ctrl_reg2, 1); 595 | } 596 | 597 | return ret; 598 | } 599 | 600 | /** 601 | * @brief High-pass filter cutoff frequency selection.[get] 602 | * 603 | * HPCF[2:1]\ft @1Hz @10Hz @25Hz @50Hz @100Hz @200Hz @400Hz @1kHz6 ft@5kHz 604 | * AGGRESSIVE 0.02Hz 0.2Hz 0.5Hz 1Hz 2Hz 4Hz 8Hz 32Hz 100Hz 605 | * STRONG 0.008Hz 0.08Hz 0.2Hz 0.5Hz 1Hz 2Hz 4Hz 16Hz 50Hz 606 | * MEDIUM 0.004Hz 0.04Hz 0.1Hz 0.2Hz 0.5Hz 1Hz 2Hz 8Hz 25Hz 607 | * LIGHT 0.002Hz 0.02Hz 0.05Hz 0.1Hz 0.2Hz 0.5Hz 1Hz 4Hz 12Hz 608 | * 609 | * @param ctx read / write interface definitions 610 | * @param val get the values of hpcf in reg CTRL_REG2 611 | * @retval interface status (MANDATORY: return 0 -> no Error) 612 | * 613 | */ 614 | int32_t lis2dh12_high_pass_bandwidth_get(const stmdev_ctx_t *ctx, 615 | lis2dh12_hpcf_t *val) 616 | { 617 | lis2dh12_ctrl_reg2_t ctrl_reg2; 618 | int32_t ret; 619 | 620 | ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG2, 621 | (uint8_t *)&ctrl_reg2, 1); 622 | 623 | switch (ctrl_reg2.hpcf) 624 | { 625 | case LIS2DH12_AGGRESSIVE: 626 | *val = LIS2DH12_AGGRESSIVE; 627 | break; 628 | 629 | case LIS2DH12_STRONG: 630 | *val = LIS2DH12_STRONG; 631 | break; 632 | 633 | case LIS2DH12_MEDIUM: 634 | *val = LIS2DH12_MEDIUM; 635 | break; 636 | 637 | case LIS2DH12_LIGHT: 638 | *val = LIS2DH12_LIGHT; 639 | break; 640 | 641 | default: 642 | *val = LIS2DH12_LIGHT; 643 | break; 644 | } 645 | 646 | return ret; 647 | } 648 | 649 | /** 650 | * @brief High-pass filter mode selection.[set] 651 | * 652 | * @param ctx read / write interface definitions 653 | * @param val change the values of hpm in reg CTRL_REG2 654 | * @retval interface status (MANDATORY: return 0 -> no Error) 655 | * 656 | */ 657 | int32_t lis2dh12_high_pass_mode_set(const stmdev_ctx_t *ctx, 658 | lis2dh12_hpm_t val) 659 | { 660 | lis2dh12_ctrl_reg2_t ctrl_reg2; 661 | int32_t ret; 662 | 663 | ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG2, 664 | (uint8_t *)&ctrl_reg2, 1); 665 | 666 | if (ret == 0) 667 | { 668 | ctrl_reg2.hpm = (uint8_t)val; 669 | ret = lis2dh12_write_reg(ctx, LIS2DH12_CTRL_REG2, 670 | (uint8_t *)&ctrl_reg2, 1); 671 | } 672 | 673 | return ret; 674 | } 675 | 676 | /** 677 | * @brief High-pass filter mode selection.[get] 678 | * 679 | * @param ctx read / write interface definitions 680 | * @param val get the values of hpm in reg CTRL_REG2 681 | * @retval interface status (MANDATORY: return 0 -> no Error) 682 | * 683 | */ 684 | int32_t lis2dh12_high_pass_mode_get(const stmdev_ctx_t *ctx, 685 | lis2dh12_hpm_t *val) 686 | { 687 | lis2dh12_ctrl_reg2_t ctrl_reg2; 688 | int32_t ret; 689 | 690 | ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG2, 691 | (uint8_t *)&ctrl_reg2, 1); 692 | 693 | switch (ctrl_reg2.hpm) 694 | { 695 | case LIS2DH12_NORMAL_WITH_RST: 696 | *val = LIS2DH12_NORMAL_WITH_RST; 697 | break; 698 | 699 | case LIS2DH12_REFERENCE_MODE: 700 | *val = LIS2DH12_REFERENCE_MODE; 701 | break; 702 | 703 | case LIS2DH12_NORMAL: 704 | *val = LIS2DH12_NORMAL; 705 | break; 706 | 707 | case LIS2DH12_AUTORST_ON_INT: 708 | *val = LIS2DH12_AUTORST_ON_INT; 709 | break; 710 | 711 | default: 712 | *val = LIS2DH12_NORMAL_WITH_RST; 713 | break; 714 | } 715 | 716 | return ret; 717 | } 718 | 719 | /** 720 | * @brief Full-scale configuration.[set] 721 | * 722 | * @param ctx read / write interface definitions 723 | * @param val change the values of fs in reg CTRL_REG4 724 | * @retval interface status (MANDATORY: return 0 -> no Error) 725 | * 726 | */ 727 | int32_t lis2dh12_full_scale_set(const stmdev_ctx_t *ctx, lis2dh12_fs_t val) 728 | { 729 | lis2dh12_ctrl_reg4_t ctrl_reg4; 730 | int32_t ret; 731 | 732 | ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG4, 733 | (uint8_t *)&ctrl_reg4, 1); 734 | 735 | if (ret == 0) 736 | { 737 | ctrl_reg4.fs = (uint8_t)val; 738 | ret = lis2dh12_write_reg(ctx, LIS2DH12_CTRL_REG4, 739 | (uint8_t *)&ctrl_reg4, 1); 740 | } 741 | 742 | return ret; 743 | } 744 | 745 | /** 746 | * @brief Full-scale configuration.[get] 747 | * 748 | * @param ctx read / write interface definitions 749 | * @param val get the values of fs in reg CTRL_REG4 750 | * @retval interface status (MANDATORY: return 0 -> no Error) 751 | * 752 | */ 753 | int32_t lis2dh12_full_scale_get(const stmdev_ctx_t *ctx, lis2dh12_fs_t *val) 754 | { 755 | lis2dh12_ctrl_reg4_t ctrl_reg4; 756 | int32_t ret; 757 | 758 | ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG4, 759 | (uint8_t *)&ctrl_reg4, 1); 760 | 761 | switch (ctrl_reg4.fs) 762 | { 763 | case LIS2DH12_2g: 764 | *val = LIS2DH12_2g; 765 | break; 766 | 767 | case LIS2DH12_4g: 768 | *val = LIS2DH12_4g; 769 | break; 770 | 771 | case LIS2DH12_8g: 772 | *val = LIS2DH12_8g; 773 | break; 774 | 775 | case LIS2DH12_16g: 776 | *val = LIS2DH12_16g; 777 | break; 778 | 779 | default: 780 | *val = LIS2DH12_2g; 781 | break; 782 | } 783 | 784 | return ret; 785 | } 786 | 787 | /** 788 | * @brief Block Data Update.[set] 789 | * 790 | * @param ctx read / write interface definitions 791 | * @param val change the values of bdu in reg CTRL_REG4 792 | * @retval interface status (MANDATORY: return 0 -> no Error) 793 | * 794 | */ 795 | int32_t lis2dh12_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val) 796 | { 797 | lis2dh12_ctrl_reg4_t ctrl_reg4; 798 | int32_t ret; 799 | 800 | ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG4, 801 | (uint8_t *)&ctrl_reg4, 1); 802 | 803 | if (ret == 0) 804 | { 805 | ctrl_reg4.bdu = val; 806 | ret = lis2dh12_write_reg(ctx, LIS2DH12_CTRL_REG4, 807 | (uint8_t *)&ctrl_reg4, 1); 808 | } 809 | 810 | return ret; 811 | } 812 | 813 | /** 814 | * @brief Block Data Update.[get] 815 | * 816 | * @param ctx read / write interface definitions 817 | * @param val change the values of bdu in reg CTRL_REG4 818 | * @retval interface status (MANDATORY: return 0 -> no Error) 819 | * 820 | */ 821 | int32_t lis2dh12_block_data_update_get(const stmdev_ctx_t *ctx, 822 | uint8_t *val) 823 | { 824 | lis2dh12_ctrl_reg4_t ctrl_reg4; 825 | int32_t ret; 826 | 827 | ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG4, 828 | (uint8_t *)&ctrl_reg4, 1); 829 | *val = (uint8_t)ctrl_reg4.bdu; 830 | 831 | return ret; 832 | } 833 | 834 | /** 835 | * @brief Reference value for interrupt generation.[set] 836 | * LSB = ~16@2g / ~31@4g / ~63@8g / ~127@16g 837 | * 838 | * @param ctx read / write interface definitions 839 | * @param buff buffer that contains data to write 840 | * @retval interface status (MANDATORY: return 0 -> no Error) 841 | * 842 | */ 843 | int32_t lis2dh12_filter_reference_set(const stmdev_ctx_t *ctx, 844 | uint8_t *buff) 845 | { 846 | int32_t ret; 847 | 848 | ret = lis2dh12_write_reg(ctx, LIS2DH12_REFERENCE, buff, 1); 849 | 850 | return ret; 851 | } 852 | 853 | /** 854 | * @brief Reference value for interrupt generation.[get] 855 | * LSB = ~16@2g / ~31@4g / ~63@8g / ~127@16g 856 | * 857 | * @param ctx read / write interface definitions 858 | * @param buff buffer that stores data read 859 | * @retval interface status (MANDATORY: return 0 -> no Error) 860 | * 861 | */ 862 | int32_t lis2dh12_filter_reference_get(const stmdev_ctx_t *ctx, 863 | uint8_t *buff) 864 | { 865 | int32_t ret; 866 | 867 | ret = lis2dh12_read_reg(ctx, LIS2DH12_REFERENCE, buff, 1); 868 | 869 | return ret; 870 | } 871 | /** 872 | * @brief Acceleration set of data available.[get] 873 | * 874 | * @param ctx read / write interface definitions 875 | * @param val change the values of zyxda in reg STATUS_REG 876 | * @retval interface status (MANDATORY: return 0 -> no Error) 877 | * 878 | */ 879 | int32_t lis2dh12_xl_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) 880 | { 881 | lis2dh12_status_reg_t status_reg; 882 | int32_t ret; 883 | 884 | ret = lis2dh12_read_reg(ctx, LIS2DH12_STATUS_REG, 885 | (uint8_t *)&status_reg, 1); 886 | *val = status_reg.zyxda; 887 | 888 | return ret; 889 | } 890 | /** 891 | * @brief Acceleration set of data overrun.[get] 892 | * 893 | * @param ctx read / write interface definitions 894 | * @param val change the values of zyxor in reg STATUS_REG 895 | * @retval interface status (MANDATORY: return 0 -> no Error) 896 | * 897 | */ 898 | int32_t lis2dh12_xl_data_ovr_get(const stmdev_ctx_t *ctx, uint8_t *val) 899 | { 900 | lis2dh12_status_reg_t status_reg; 901 | int32_t ret; 902 | 903 | ret = lis2dh12_read_reg(ctx, LIS2DH12_STATUS_REG, 904 | (uint8_t *)&status_reg, 1); 905 | *val = status_reg.zyxor; 906 | 907 | return ret; 908 | } 909 | /** 910 | * @brief Acceleration output value.[get] 911 | * 912 | * @param ctx read / write interface definitions 913 | * @param buff buffer that stores data read 914 | * @retval interface status (MANDATORY: return 0 -> no Error) 915 | * 916 | */ 917 | int32_t lis2dh12_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val) 918 | { 919 | uint8_t buff[6]; 920 | int32_t ret; 921 | 922 | ret = lis2dh12_read_reg(ctx, LIS2DH12_OUT_X_L, buff, 6); 923 | val[0] = (int16_t)buff[1]; 924 | val[0] = (val[0] * 256) + (int16_t)buff[0]; 925 | val[1] = (int16_t)buff[3]; 926 | val[1] = (val[1] * 256) + (int16_t)buff[2]; 927 | val[2] = (int16_t)buff[5]; 928 | val[2] = (val[2] * 256) + (int16_t)buff[4]; 929 | 930 | return ret; 931 | } 932 | /** 933 | * @} 934 | * 935 | */ 936 | 937 | /** 938 | * @defgroup LIS2DH12_Common 939 | * @brief This section group common useful functions 940 | * @{ 941 | * 942 | */ 943 | 944 | /** 945 | * @brief DeviceWhoamI .[get] 946 | * 947 | * @param ctx read / write interface definitions 948 | * @param buff buffer that stores data read 949 | * @retval interface status (MANDATORY: return 0 -> no Error) 950 | * 951 | */ 952 | int32_t lis2dh12_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff) 953 | { 954 | int32_t ret; 955 | 956 | ret = lis2dh12_read_reg(ctx, LIS2DH12_WHO_AM_I, buff, 1); 957 | 958 | return ret; 959 | } 960 | /** 961 | * @brief Self Test.[set] 962 | * 963 | * @param ctx read / write interface definitions 964 | * @param val change the values of st in reg CTRL_REG4 965 | * @retval interface status (MANDATORY: return 0 -> no Error) 966 | * 967 | */ 968 | int32_t lis2dh12_self_test_set(const stmdev_ctx_t *ctx, lis2dh12_st_t val) 969 | { 970 | lis2dh12_ctrl_reg4_t ctrl_reg4; 971 | int32_t ret; 972 | 973 | ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG4, 974 | (uint8_t *)&ctrl_reg4, 1); 975 | 976 | if (ret == 0) 977 | { 978 | ctrl_reg4.st = (uint8_t)val; 979 | ret = lis2dh12_write_reg(ctx, LIS2DH12_CTRL_REG4, 980 | (uint8_t *)&ctrl_reg4, 1); 981 | } 982 | 983 | return ret; 984 | } 985 | 986 | /** 987 | * @brief Self Test.[get] 988 | * 989 | * @param ctx read / write interface definitions 990 | * @param val Get the values of st in reg CTRL_REG4 991 | * @retval interface status (MANDATORY: return 0 -> no Error) 992 | * 993 | */ 994 | int32_t lis2dh12_self_test_get(const stmdev_ctx_t *ctx, lis2dh12_st_t *val) 995 | { 996 | lis2dh12_ctrl_reg4_t ctrl_reg4; 997 | int32_t ret; 998 | 999 | ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG4, 1000 | (uint8_t *)&ctrl_reg4, 1); 1001 | 1002 | switch (ctrl_reg4.st) 1003 | { 1004 | case LIS2DH12_ST_DISABLE: 1005 | *val = LIS2DH12_ST_DISABLE; 1006 | break; 1007 | 1008 | case LIS2DH12_ST_POSITIVE: 1009 | *val = LIS2DH12_ST_POSITIVE; 1010 | break; 1011 | 1012 | case LIS2DH12_ST_NEGATIVE: 1013 | *val = LIS2DH12_ST_NEGATIVE; 1014 | break; 1015 | 1016 | default: 1017 | *val = LIS2DH12_ST_DISABLE; 1018 | break; 1019 | } 1020 | 1021 | return ret; 1022 | } 1023 | 1024 | /** 1025 | * @brief Big/Little Endian data selection.[set] 1026 | * 1027 | * @param ctx read / write interface definitions 1028 | * @param val change the values of ble in reg CTRL_REG4 1029 | * @retval interface status (MANDATORY: return 0 -> no Error) 1030 | * 1031 | */ 1032 | int32_t lis2dh12_data_format_set(const stmdev_ctx_t *ctx, 1033 | lis2dh12_ble_t val) 1034 | { 1035 | lis2dh12_ctrl_reg4_t ctrl_reg4; 1036 | int32_t ret; 1037 | 1038 | ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG4, 1039 | (uint8_t *)&ctrl_reg4, 1); 1040 | 1041 | if (ret == 0) 1042 | { 1043 | ctrl_reg4.ble = (uint8_t)val; 1044 | ret = lis2dh12_write_reg(ctx, LIS2DH12_CTRL_REG4, 1045 | (uint8_t *)&ctrl_reg4, 1); 1046 | } 1047 | 1048 | return ret; 1049 | } 1050 | 1051 | /** 1052 | * @brief Big/Little Endian data selection.[get] 1053 | * 1054 | * @param ctx read / write interface definitions 1055 | * @param val get the values of ble in reg CTRL_REG4 1056 | * @retval interface status (MANDATORY: return 0 -> no Error) 1057 | * 1058 | */ 1059 | int32_t lis2dh12_data_format_get(const stmdev_ctx_t *ctx, 1060 | lis2dh12_ble_t *val) 1061 | { 1062 | lis2dh12_ctrl_reg4_t ctrl_reg4; 1063 | int32_t ret; 1064 | 1065 | ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG4, 1066 | (uint8_t *)&ctrl_reg4, 1); 1067 | 1068 | switch (ctrl_reg4.ble) 1069 | { 1070 | case LIS2DH12_LSB_AT_LOW_ADD: 1071 | *val = LIS2DH12_LSB_AT_LOW_ADD; 1072 | break; 1073 | 1074 | case LIS2DH12_MSB_AT_LOW_ADD: 1075 | *val = LIS2DH12_MSB_AT_LOW_ADD; 1076 | break; 1077 | 1078 | default: 1079 | *val = LIS2DH12_LSB_AT_LOW_ADD; 1080 | break; 1081 | } 1082 | 1083 | return ret; 1084 | } 1085 | 1086 | /** 1087 | * @brief Reboot memory content. Reload the calibration parameters.[set] 1088 | * 1089 | * @param ctx read / write interface definitions 1090 | * @param val change the values of boot in reg CTRL_REG5 1091 | * @retval interface status (MANDATORY: return 0 -> no Error) 1092 | * 1093 | */ 1094 | int32_t lis2dh12_boot_set(const stmdev_ctx_t *ctx, uint8_t val) 1095 | { 1096 | lis2dh12_ctrl_reg5_t ctrl_reg5; 1097 | int32_t ret; 1098 | 1099 | ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG5, 1100 | (uint8_t *)&ctrl_reg5, 1); 1101 | 1102 | if (ret == 0) 1103 | { 1104 | ctrl_reg5.boot = val; 1105 | ret = lis2dh12_write_reg(ctx, LIS2DH12_CTRL_REG5, 1106 | (uint8_t *)&ctrl_reg5, 1); 1107 | } 1108 | 1109 | return ret; 1110 | } 1111 | 1112 | /** 1113 | * @brief Reboot memory content. Reload the calibration parameters.[get] 1114 | * 1115 | * @param ctx read / write interface definitions 1116 | * @param val change the values of boot in reg CTRL_REG5 1117 | * @retval interface status (MANDATORY: return 0 -> no Error) 1118 | * 1119 | */ 1120 | int32_t lis2dh12_boot_get(const stmdev_ctx_t *ctx, uint8_t *val) 1121 | { 1122 | lis2dh12_ctrl_reg5_t ctrl_reg5; 1123 | int32_t ret; 1124 | 1125 | ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG5, 1126 | (uint8_t *)&ctrl_reg5, 1); 1127 | *val = (uint8_t)ctrl_reg5.boot; 1128 | 1129 | return ret; 1130 | } 1131 | 1132 | /** 1133 | * @brief Info about device status.[get] 1134 | * 1135 | * @param ctx read / write interface definitions 1136 | * @param val register STATUS_REG 1137 | * @retval interface status (MANDATORY: return 0 -> no Error) 1138 | * 1139 | */ 1140 | int32_t lis2dh12_status_get(const stmdev_ctx_t *ctx, 1141 | lis2dh12_status_reg_t *val) 1142 | { 1143 | int32_t ret; 1144 | 1145 | ret = lis2dh12_read_reg(ctx, LIS2DH12_STATUS_REG, (uint8_t *) val, 1); 1146 | 1147 | return ret; 1148 | } 1149 | /** 1150 | * @} 1151 | * 1152 | */ 1153 | 1154 | /** 1155 | * @defgroup LIS2DH12_Interrupts_generator_1 1156 | * @brief This section group all the functions that manage the first 1157 | * interrupts generator 1158 | * @{ 1159 | * 1160 | */ 1161 | 1162 | /** 1163 | * @brief Interrupt generator 1 configuration register.[set] 1164 | * 1165 | * @param ctx read / write interface definitions 1166 | * @param val register INT1_CFG 1167 | * @retval interface status (MANDATORY: return 0 -> no Error) 1168 | * 1169 | */ 1170 | int32_t lis2dh12_int1_gen_conf_set(const stmdev_ctx_t *ctx, 1171 | lis2dh12_int1_cfg_t *val) 1172 | { 1173 | int32_t ret; 1174 | 1175 | ret = lis2dh12_write_reg(ctx, LIS2DH12_INT1_CFG, (uint8_t *) val, 1); 1176 | 1177 | return ret; 1178 | } 1179 | 1180 | /** 1181 | * @brief Interrupt generator 1 configuration register.[get] 1182 | * 1183 | * @param ctx read / write interface definitions 1184 | * @param val register INT1_CFG 1185 | * @retval interface status (MANDATORY: return 0 -> no Error) 1186 | * 1187 | */ 1188 | int32_t lis2dh12_int1_gen_conf_get(const stmdev_ctx_t *ctx, 1189 | lis2dh12_int1_cfg_t *val) 1190 | { 1191 | int32_t ret; 1192 | 1193 | ret = lis2dh12_read_reg(ctx, LIS2DH12_INT1_CFG, (uint8_t *) val, 1); 1194 | 1195 | return ret; 1196 | } 1197 | 1198 | /** 1199 | * @brief Interrupt generator 1 source register.[get] 1200 | * 1201 | * @param ctx read / write interface definitions 1202 | * @param val Registers INT1_SRC 1203 | * @retval interface status (MANDATORY: return 0 -> no Error) 1204 | * 1205 | */ 1206 | int32_t lis2dh12_int1_gen_source_get(const stmdev_ctx_t *ctx, 1207 | lis2dh12_int1_src_t *val) 1208 | { 1209 | int32_t ret; 1210 | 1211 | ret = lis2dh12_read_reg(ctx, LIS2DH12_INT1_SRC, (uint8_t *) val, 1); 1212 | 1213 | return ret; 1214 | } 1215 | /** 1216 | * @brief User-defined threshold value for xl interrupt event on 1217 | * generator 1.[set] 1218 | * LSb = 16mg@2g / 32mg@4g / 62mg@8g / 186mg@16g 1219 | * 1220 | * @param ctx read / write interface definitions 1221 | * @param val change the values of ths in reg INT1_THS 1222 | * @retval interface status (MANDATORY: return 0 -> no Error) 1223 | * 1224 | */ 1225 | int32_t lis2dh12_int1_gen_threshold_set(const stmdev_ctx_t *ctx, 1226 | uint8_t val) 1227 | { 1228 | lis2dh12_int1_ths_t int1_ths; 1229 | int32_t ret; 1230 | 1231 | ret = lis2dh12_read_reg(ctx, LIS2DH12_INT1_THS, (uint8_t *)&int1_ths, 1); 1232 | 1233 | if (ret == 0) 1234 | { 1235 | int1_ths.ths = val; 1236 | ret = lis2dh12_write_reg(ctx, LIS2DH12_INT1_THS, (uint8_t *)&int1_ths, 1); 1237 | } 1238 | 1239 | return ret; 1240 | } 1241 | 1242 | /** 1243 | * @brief User-defined threshold value for xl interrupt event on 1244 | * generator 1.[get] 1245 | * LSb = 16mg@2g / 32mg@4g / 62mg@8g / 186mg@16g 1246 | * 1247 | * @param ctx read / write interface definitions 1248 | * @param val change the values of ths in reg INT1_THS 1249 | * @retval interface status (MANDATORY: return 0 -> no Error) 1250 | * 1251 | */ 1252 | int32_t lis2dh12_int1_gen_threshold_get(const stmdev_ctx_t *ctx, 1253 | uint8_t *val) 1254 | { 1255 | lis2dh12_int1_ths_t int1_ths; 1256 | int32_t ret; 1257 | 1258 | ret = lis2dh12_read_reg(ctx, LIS2DH12_INT1_THS, (uint8_t *)&int1_ths, 1); 1259 | *val = (uint8_t)int1_ths.ths; 1260 | 1261 | return ret; 1262 | } 1263 | 1264 | /** 1265 | * @brief The minimum duration (LSb = 1/ODR) of the Interrupt 1 event to be 1266 | * recognized.[set] 1267 | * 1268 | * @param ctx read / write interface definitions 1269 | * @param val change the values of d in reg INT1_DURATION 1270 | * @retval interface status (MANDATORY: return 0 -> no Error) 1271 | * 1272 | */ 1273 | int32_t lis2dh12_int1_gen_duration_set(const stmdev_ctx_t *ctx, uint8_t val) 1274 | { 1275 | lis2dh12_int1_duration_t int1_duration; 1276 | int32_t ret; 1277 | 1278 | ret = lis2dh12_read_reg(ctx, LIS2DH12_INT1_DURATION, 1279 | (uint8_t *)&int1_duration, 1); 1280 | 1281 | if (ret == 0) 1282 | { 1283 | int1_duration.d = val; 1284 | ret = lis2dh12_write_reg(ctx, LIS2DH12_INT1_DURATION, 1285 | (uint8_t *)&int1_duration, 1); 1286 | } 1287 | 1288 | return ret; 1289 | } 1290 | 1291 | /** 1292 | * @brief The minimum duration (LSb = 1/ODR) of the Interrupt 1 event to be 1293 | * recognized.[get] 1294 | * 1295 | * @param ctx read / write interface definitions 1296 | * @param val change the values of d in reg INT1_DURATION 1297 | * @retval interface status (MANDATORY: return 0 -> no Error) 1298 | * 1299 | */ 1300 | int32_t lis2dh12_int1_gen_duration_get(const stmdev_ctx_t *ctx, 1301 | uint8_t *val) 1302 | { 1303 | lis2dh12_int1_duration_t int1_duration; 1304 | int32_t ret; 1305 | 1306 | ret = lis2dh12_read_reg(ctx, LIS2DH12_INT1_DURATION, 1307 | (uint8_t *)&int1_duration, 1); 1308 | *val = (uint8_t)int1_duration.d; 1309 | 1310 | return ret; 1311 | } 1312 | 1313 | /** 1314 | * @} 1315 | * 1316 | */ 1317 | 1318 | /** 1319 | * @defgroup LIS2DH12_Interrupts_generator_2 1320 | * @brief This section group all the functions that manage the second 1321 | * interrupts generator 1322 | * @{ 1323 | * 1324 | */ 1325 | 1326 | /** 1327 | * @brief Interrupt generator 2 configuration register.[set] 1328 | * 1329 | * @param ctx read / write interface definitions 1330 | * @param val registers INT2_CFG 1331 | * @retval interface status (MANDATORY: return 0 -> no Error) 1332 | * 1333 | */ 1334 | int32_t lis2dh12_int2_gen_conf_set(const stmdev_ctx_t *ctx, 1335 | lis2dh12_int2_cfg_t *val) 1336 | { 1337 | int32_t ret; 1338 | 1339 | ret = lis2dh12_write_reg(ctx, LIS2DH12_INT2_CFG, (uint8_t *) val, 1); 1340 | 1341 | return ret; 1342 | } 1343 | 1344 | /** 1345 | * @brief Interrupt generator 2 configuration register.[get] 1346 | * 1347 | * @param ctx read / write interface definitions 1348 | * @param val registers INT2_CFG 1349 | * @retval interface status (MANDATORY: return 0 -> no Error) 1350 | * 1351 | */ 1352 | int32_t lis2dh12_int2_gen_conf_get(const stmdev_ctx_t *ctx, 1353 | lis2dh12_int2_cfg_t *val) 1354 | { 1355 | int32_t ret; 1356 | 1357 | ret = lis2dh12_read_reg(ctx, LIS2DH12_INT2_CFG, (uint8_t *) val, 1); 1358 | 1359 | return ret; 1360 | } 1361 | /** 1362 | * @brief Interrupt generator 2 source register.[get] 1363 | * 1364 | * @param ctx read / write interface definitions 1365 | * @param val registers INT2_SRC 1366 | * @retval interface status (MANDATORY: return 0 -> no Error) 1367 | * 1368 | */ 1369 | int32_t lis2dh12_int2_gen_source_get(const stmdev_ctx_t *ctx, 1370 | lis2dh12_int2_src_t *val) 1371 | { 1372 | int32_t ret; 1373 | 1374 | ret = lis2dh12_read_reg(ctx, LIS2DH12_INT2_SRC, (uint8_t *) val, 1); 1375 | 1376 | return ret; 1377 | } 1378 | /** 1379 | * @brief User-defined threshold value for xl interrupt event on 1380 | * generator 2.[set] 1381 | * LSb = 16mg@2g / 32mg@4g / 62mg@8g / 186mg@16g 1382 | * 1383 | * @param ctx read / write interface definitions 1384 | * @param val change the values of ths in reg INT2_THS 1385 | * @retval interface status (MANDATORY: return 0 -> no Error) 1386 | * 1387 | */ 1388 | int32_t lis2dh12_int2_gen_threshold_set(const stmdev_ctx_t *ctx, 1389 | uint8_t val) 1390 | { 1391 | lis2dh12_int2_ths_t int2_ths; 1392 | int32_t ret; 1393 | 1394 | ret = lis2dh12_read_reg(ctx, LIS2DH12_INT2_THS, (uint8_t *)&int2_ths, 1); 1395 | 1396 | if (ret == 0) 1397 | { 1398 | int2_ths.ths = val; 1399 | ret = lis2dh12_write_reg(ctx, LIS2DH12_INT2_THS, (uint8_t *)&int2_ths, 1); 1400 | } 1401 | 1402 | return ret; 1403 | } 1404 | 1405 | /** 1406 | * @brief User-defined threshold value for xl interrupt event on 1407 | * generator 2.[get] 1408 | * LSb = 16mg@2g / 32mg@4g / 62mg@8g / 186mg@16g 1409 | * 1410 | * @param ctx read / write interface definitions 1411 | * @param val change the values of ths in reg INT2_THS 1412 | * @retval interface status (MANDATORY: return 0 -> no Error) 1413 | * 1414 | */ 1415 | int32_t lis2dh12_int2_gen_threshold_get(const stmdev_ctx_t *ctx, 1416 | uint8_t *val) 1417 | { 1418 | lis2dh12_int2_ths_t int2_ths; 1419 | int32_t ret; 1420 | 1421 | ret = lis2dh12_read_reg(ctx, LIS2DH12_INT2_THS, (uint8_t *)&int2_ths, 1); 1422 | *val = (uint8_t)int2_ths.ths; 1423 | 1424 | return ret; 1425 | } 1426 | 1427 | /** 1428 | * @brief The minimum duration (LSb = 1/ODR) of the Interrupt 1 event to be 1429 | * recognized .[set] 1430 | * 1431 | * @param ctx read / write interface definitions 1432 | * @param val change the values of d in reg INT2_DURATION 1433 | * @retval interface status (MANDATORY: return 0 -> no Error) 1434 | * 1435 | */ 1436 | int32_t lis2dh12_int2_gen_duration_set(const stmdev_ctx_t *ctx, uint8_t val) 1437 | { 1438 | lis2dh12_int2_duration_t int2_duration; 1439 | int32_t ret; 1440 | 1441 | ret = lis2dh12_read_reg(ctx, LIS2DH12_INT2_DURATION, 1442 | (uint8_t *)&int2_duration, 1); 1443 | 1444 | if (ret == 0) 1445 | { 1446 | int2_duration.d = val; 1447 | ret = lis2dh12_write_reg(ctx, LIS2DH12_INT2_DURATION, 1448 | (uint8_t *)&int2_duration, 1); 1449 | } 1450 | 1451 | return ret; 1452 | } 1453 | 1454 | /** 1455 | * @brief The minimum duration (LSb = 1/ODR) of the Interrupt 1 event to be 1456 | * recognized.[get] 1457 | * 1458 | * @param ctx read / write interface definitions 1459 | * @param val change the values of d in reg INT2_DURATION 1460 | * @retval interface status (MANDATORY: return 0 -> no Error) 1461 | * 1462 | */ 1463 | int32_t lis2dh12_int2_gen_duration_get(const stmdev_ctx_t *ctx, 1464 | uint8_t *val) 1465 | { 1466 | lis2dh12_int2_duration_t int2_duration; 1467 | int32_t ret; 1468 | 1469 | ret = lis2dh12_read_reg(ctx, LIS2DH12_INT2_DURATION, 1470 | (uint8_t *)&int2_duration, 1); 1471 | *val = (uint8_t)int2_duration.d; 1472 | 1473 | return ret; 1474 | } 1475 | 1476 | /** 1477 | * @} 1478 | * 1479 | */ 1480 | 1481 | /** 1482 | * @defgroup LIS2DH12_Interrupt_pins 1483 | * @brief This section group all the functions that manage interrupt pins 1484 | * @{ 1485 | * 1486 | */ 1487 | 1488 | /** 1489 | * @brief High-pass filter on interrupts/tap generator.[set] 1490 | * 1491 | * @param ctx read / write interface definitions 1492 | * @param val change the values of hp in reg CTRL_REG2 1493 | * @retval interface status (MANDATORY: return 0 -> no Error) 1494 | * 1495 | */ 1496 | int32_t lis2dh12_high_pass_int_conf_set(const stmdev_ctx_t *ctx, 1497 | lis2dh12_hp_t val) 1498 | { 1499 | lis2dh12_ctrl_reg2_t ctrl_reg2; 1500 | int32_t ret; 1501 | 1502 | ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG2, 1503 | (uint8_t *)&ctrl_reg2, 1); 1504 | 1505 | if (ret == 0) 1506 | { 1507 | ctrl_reg2.hp = (uint8_t)val; 1508 | ret = lis2dh12_write_reg(ctx, LIS2DH12_CTRL_REG2, 1509 | (uint8_t *)&ctrl_reg2, 1); 1510 | } 1511 | 1512 | return ret; 1513 | } 1514 | 1515 | /** 1516 | * @brief High-pass filter on interrupts/tap generator.[get] 1517 | * 1518 | * @param ctx read / write interface definitions 1519 | * @param val Get the values of hp in reg CTRL_REG2 1520 | * @retval interface status (MANDATORY: return 0 -> no Error) 1521 | * 1522 | */ 1523 | int32_t lis2dh12_high_pass_int_conf_get(const stmdev_ctx_t *ctx, 1524 | lis2dh12_hp_t *val) 1525 | { 1526 | lis2dh12_ctrl_reg2_t ctrl_reg2; 1527 | int32_t ret; 1528 | 1529 | ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG2, 1530 | (uint8_t *)&ctrl_reg2, 1); 1531 | 1532 | switch (ctrl_reg2.hp) 1533 | { 1534 | case LIS2DH12_DISC_FROM_INT_GENERATOR: 1535 | *val = LIS2DH12_DISC_FROM_INT_GENERATOR; 1536 | break; 1537 | 1538 | case LIS2DH12_ON_INT1_GEN: 1539 | *val = LIS2DH12_ON_INT1_GEN; 1540 | break; 1541 | 1542 | case LIS2DH12_ON_INT2_GEN: 1543 | *val = LIS2DH12_ON_INT2_GEN; 1544 | break; 1545 | 1546 | case LIS2DH12_ON_TAP_GEN: 1547 | *val = LIS2DH12_ON_TAP_GEN; 1548 | break; 1549 | 1550 | case LIS2DH12_ON_INT1_INT2_GEN: 1551 | *val = LIS2DH12_ON_INT1_INT2_GEN; 1552 | break; 1553 | 1554 | case LIS2DH12_ON_INT1_TAP_GEN: 1555 | *val = LIS2DH12_ON_INT1_TAP_GEN; 1556 | break; 1557 | 1558 | case LIS2DH12_ON_INT2_TAP_GEN: 1559 | *val = LIS2DH12_ON_INT2_TAP_GEN; 1560 | break; 1561 | 1562 | case LIS2DH12_ON_INT1_INT2_TAP_GEN: 1563 | *val = LIS2DH12_ON_INT1_INT2_TAP_GEN; 1564 | break; 1565 | 1566 | default: 1567 | *val = LIS2DH12_DISC_FROM_INT_GENERATOR; 1568 | break; 1569 | } 1570 | 1571 | return ret; 1572 | } 1573 | 1574 | /** 1575 | * @brief Int1 pin routing configuration register.[set] 1576 | * 1577 | * @param ctx read / write interface definitions 1578 | * @param val registers CTRL_REG3 1579 | * @retval interface status (MANDATORY: return 0 -> no Error) 1580 | * 1581 | */ 1582 | int32_t lis2dh12_pin_int1_config_set(const stmdev_ctx_t *ctx, 1583 | lis2dh12_ctrl_reg3_t *val) 1584 | { 1585 | int32_t ret; 1586 | 1587 | ret = lis2dh12_write_reg(ctx, LIS2DH12_CTRL_REG3, (uint8_t *) val, 1); 1588 | 1589 | return ret; 1590 | } 1591 | 1592 | /** 1593 | * @brief Int1 pin routing configuration register.[get] 1594 | * 1595 | * @param ctx read / write interface definitions 1596 | * @param val registers CTRL_REG3 1597 | * @retval interface status (MANDATORY: return 0 -> no Error) 1598 | * 1599 | */ 1600 | int32_t lis2dh12_pin_int1_config_get(const stmdev_ctx_t *ctx, 1601 | lis2dh12_ctrl_reg3_t *val) 1602 | { 1603 | int32_t ret; 1604 | 1605 | ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG3, (uint8_t *) val, 1); 1606 | 1607 | return ret; 1608 | } 1609 | /** 1610 | * @brief int2_pin_detect_4d: [set] 4D enable: 4D detection is enabled 1611 | * on INT2 pin when 6D bit on 1612 | * INT2_CFG (34h) is set to 1. 1613 | * 1614 | * @param ctx read / write interface definitions 1615 | * @param val change the values of d4d_int2 in reg CTRL_REG5 1616 | * @retval interface status (MANDATORY: return 0 -> no Error) 1617 | * 1618 | */ 1619 | int32_t lis2dh12_int2_pin_detect_4d_set(const stmdev_ctx_t *ctx, 1620 | uint8_t val) 1621 | { 1622 | lis2dh12_ctrl_reg5_t ctrl_reg5; 1623 | int32_t ret; 1624 | 1625 | ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG5, 1626 | (uint8_t *)&ctrl_reg5, 1); 1627 | 1628 | if (ret == 0) 1629 | { 1630 | ctrl_reg5.d4d_int2 = val; 1631 | ret = lis2dh12_write_reg(ctx, LIS2DH12_CTRL_REG5, 1632 | (uint8_t *)&ctrl_reg5, 1); 1633 | } 1634 | 1635 | return ret; 1636 | } 1637 | 1638 | /** 1639 | * @brief 4D enable: 4D detection is enabled on INT2 pin when 6D bit on 1640 | * INT2_CFG (34h) is set to 1.[get] 1641 | * 1642 | * @param ctx read / write interface definitions 1643 | * @param val change the values of d4d_int2 in reg CTRL_REG5 1644 | * @retval interface status (MANDATORY: return 0 -> no Error) 1645 | * 1646 | */ 1647 | int32_t lis2dh12_int2_pin_detect_4d_get(const stmdev_ctx_t *ctx, 1648 | uint8_t *val) 1649 | { 1650 | lis2dh12_ctrl_reg5_t ctrl_reg5; 1651 | int32_t ret; 1652 | 1653 | ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG5, 1654 | (uint8_t *)&ctrl_reg5, 1); 1655 | *val = (uint8_t)ctrl_reg5.d4d_int2; 1656 | 1657 | return ret; 1658 | } 1659 | 1660 | /** 1661 | * @brief Latch interrupt request on INT2_SRC (35h) register, with 1662 | * INT2_SRC (35h) register cleared by reading INT2_SRC(35h) 1663 | * itself.[set] 1664 | * 1665 | * @param ctx read / write interface definitions 1666 | * @param val change the values of lir_int2 in reg CTRL_REG5 1667 | * @retval interface status (MANDATORY: return 0 -> no Error) 1668 | * 1669 | */ 1670 | int32_t lis2dh12_int2_pin_notification_mode_set(const stmdev_ctx_t *ctx, 1671 | lis2dh12_lir_int2_t val) 1672 | { 1673 | lis2dh12_ctrl_reg5_t ctrl_reg5; 1674 | int32_t ret; 1675 | 1676 | ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG5, 1677 | (uint8_t *)&ctrl_reg5, 1); 1678 | 1679 | if (ret == 0) 1680 | { 1681 | ctrl_reg5.lir_int2 = (uint8_t)val; 1682 | ret = lis2dh12_write_reg(ctx, LIS2DH12_CTRL_REG5, 1683 | (uint8_t *)&ctrl_reg5, 1); 1684 | } 1685 | 1686 | return ret; 1687 | } 1688 | 1689 | /** 1690 | * @brief Latch interrupt request on INT2_SRC (35h) register, with 1691 | * INT2_SRC (35h) register cleared by reading INT2_SRC(35h) 1692 | * itself.[get] 1693 | * 1694 | * @param ctx read / write interface definitions 1695 | * @param val Get the values of lir_int2 in reg CTRL_REG5 1696 | * @retval interface status (MANDATORY: return 0 -> no Error) 1697 | * 1698 | */ 1699 | int32_t lis2dh12_int2_pin_notification_mode_get(const stmdev_ctx_t *ctx, 1700 | lis2dh12_lir_int2_t *val) 1701 | { 1702 | lis2dh12_ctrl_reg5_t ctrl_reg5; 1703 | int32_t ret; 1704 | 1705 | ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG5, 1706 | (uint8_t *)&ctrl_reg5, 1); 1707 | 1708 | switch (ctrl_reg5.lir_int2) 1709 | { 1710 | case LIS2DH12_INT2_PULSED: 1711 | *val = LIS2DH12_INT2_PULSED; 1712 | break; 1713 | 1714 | case LIS2DH12_INT2_LATCHED: 1715 | *val = LIS2DH12_INT2_LATCHED; 1716 | break; 1717 | 1718 | default: 1719 | *val = LIS2DH12_INT2_PULSED; 1720 | break; 1721 | } 1722 | 1723 | return ret; 1724 | } 1725 | 1726 | /** 1727 | * @brief 4D enable: 4D detection is enabled on INT1 pin when 6D bit 1728 | * on INT1_CFG(30h) is set to 1.[set] 1729 | * 1730 | * @param ctx read / write interface definitions 1731 | * @param val change the values of d4d_int1 in reg CTRL_REG5 1732 | * @retval interface status (MANDATORY: return 0 -> no Error) 1733 | * 1734 | */ 1735 | int32_t lis2dh12_int1_pin_detect_4d_set(const stmdev_ctx_t *ctx, 1736 | uint8_t val) 1737 | { 1738 | lis2dh12_ctrl_reg5_t ctrl_reg5; 1739 | int32_t ret; 1740 | 1741 | ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG5, 1742 | (uint8_t *)&ctrl_reg5, 1); 1743 | 1744 | if (ret == 0) 1745 | { 1746 | ctrl_reg5.d4d_int1 = val; 1747 | ret = lis2dh12_write_reg(ctx, LIS2DH12_CTRL_REG5, 1748 | (uint8_t *)&ctrl_reg5, 1); 1749 | } 1750 | 1751 | return ret; 1752 | } 1753 | 1754 | /** 1755 | * @brief 4D enable: 4D detection is enabled on INT1 pin when 6D bit on 1756 | * INT1_CFG(30h) is set to 1.[get] 1757 | * 1758 | * @param ctx read / write interface definitions 1759 | * @param val change the values of d4d_int1 in reg CTRL_REG5 1760 | * @retval interface status (MANDATORY: return 0 -> no Error) 1761 | * 1762 | */ 1763 | int32_t lis2dh12_int1_pin_detect_4d_get(const stmdev_ctx_t *ctx, 1764 | uint8_t *val) 1765 | { 1766 | lis2dh12_ctrl_reg5_t ctrl_reg5; 1767 | int32_t ret; 1768 | 1769 | ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG5, 1770 | (uint8_t *)&ctrl_reg5, 1); 1771 | *val = (uint8_t)ctrl_reg5.d4d_int1; 1772 | 1773 | return ret; 1774 | } 1775 | 1776 | /** 1777 | * @brief Latch interrupt request on INT1_SRC (31h), with INT1_SRC(31h) 1778 | * register cleared by reading INT1_SRC (31h) itself.[set] 1779 | * 1780 | * @param ctx read / write interface definitions 1781 | * @param val change the values of lir_int1 in reg CTRL_REG5 1782 | * @retval interface status (MANDATORY: return 0 -> no Error) 1783 | * 1784 | */ 1785 | int32_t lis2dh12_int1_pin_notification_mode_set(const stmdev_ctx_t *ctx, 1786 | lis2dh12_lir_int1_t val) 1787 | { 1788 | lis2dh12_ctrl_reg5_t ctrl_reg5; 1789 | int32_t ret; 1790 | 1791 | ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG5, 1792 | (uint8_t *)&ctrl_reg5, 1); 1793 | 1794 | if (ret == 0) 1795 | { 1796 | ctrl_reg5.lir_int1 = (uint8_t)val; 1797 | ret = lis2dh12_write_reg(ctx, LIS2DH12_CTRL_REG5, 1798 | (uint8_t *)&ctrl_reg5, 1); 1799 | } 1800 | 1801 | return ret; 1802 | } 1803 | 1804 | /** 1805 | * @brief Latch interrupt request on INT1_SRC (31h), with INT1_SRC(31h) 1806 | * register cleared by reading INT1_SRC (31h) itself.[get] 1807 | * 1808 | * @param ctx read / write interface definitions 1809 | * @param val Get the values of lir_int1 in reg CTRL_REG5 1810 | * @retval interface status (MANDATORY: return 0 -> no Error) 1811 | * 1812 | */ 1813 | int32_t lis2dh12_int1_pin_notification_mode_get(const stmdev_ctx_t *ctx, 1814 | lis2dh12_lir_int1_t *val) 1815 | { 1816 | lis2dh12_ctrl_reg5_t ctrl_reg5; 1817 | int32_t ret; 1818 | 1819 | ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG5, 1820 | (uint8_t *)&ctrl_reg5, 1); 1821 | 1822 | switch (ctrl_reg5.lir_int1) 1823 | { 1824 | case LIS2DH12_INT1_PULSED: 1825 | *val = LIS2DH12_INT1_PULSED; 1826 | break; 1827 | 1828 | case LIS2DH12_INT1_LATCHED: 1829 | *val = LIS2DH12_INT1_LATCHED; 1830 | break; 1831 | 1832 | default: 1833 | *val = LIS2DH12_INT1_PULSED; 1834 | break; 1835 | } 1836 | 1837 | return ret; 1838 | } 1839 | 1840 | /** 1841 | * @brief Int2 pin routing configuration register.[set] 1842 | * 1843 | * @param ctx read / write interface definitions 1844 | * @param val registers CTRL_REG6 1845 | * @retval interface status (MANDATORY: return 0 -> no Error) 1846 | * 1847 | */ 1848 | int32_t lis2dh12_pin_int2_config_set(const stmdev_ctx_t *ctx, 1849 | lis2dh12_ctrl_reg6_t *val) 1850 | { 1851 | int32_t ret; 1852 | 1853 | ret = lis2dh12_write_reg(ctx, LIS2DH12_CTRL_REG6, (uint8_t *) val, 1); 1854 | 1855 | return ret; 1856 | } 1857 | 1858 | /** 1859 | * @brief Int2 pin routing configuration register.[get] 1860 | * 1861 | * @param ctx read / write interface definitions 1862 | * @param val registers CTRL_REG6 1863 | * @retval interface status (MANDATORY: return 0 -> no Error) 1864 | * 1865 | */ 1866 | int32_t lis2dh12_pin_int2_config_get(const stmdev_ctx_t *ctx, 1867 | lis2dh12_ctrl_reg6_t *val) 1868 | { 1869 | int32_t ret; 1870 | 1871 | ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG6, (uint8_t *) val, 1); 1872 | 1873 | return ret; 1874 | } 1875 | /** 1876 | * @} 1877 | * 1878 | */ 1879 | 1880 | /** 1881 | * @defgroup LIS2DH12_Fifo 1882 | * @brief This section group all the functions concerning the fifo usage 1883 | * @{ 1884 | * 1885 | */ 1886 | 1887 | /** 1888 | * @brief FIFO enable.[set] 1889 | * 1890 | * @param ctx read / write interface definitions 1891 | * @param val change the values of fifo_en in reg CTRL_REG5 1892 | * @retval interface status (MANDATORY: return 0 -> no Error) 1893 | * 1894 | */ 1895 | int32_t lis2dh12_fifo_set(const stmdev_ctx_t *ctx, uint8_t val) 1896 | { 1897 | lis2dh12_ctrl_reg5_t ctrl_reg5; 1898 | int32_t ret; 1899 | 1900 | ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG5, 1901 | (uint8_t *)&ctrl_reg5, 1); 1902 | 1903 | if (ret == 0) 1904 | { 1905 | ctrl_reg5.fifo_en = val; 1906 | ret = lis2dh12_write_reg(ctx, LIS2DH12_CTRL_REG5, 1907 | (uint8_t *)&ctrl_reg5, 1); 1908 | } 1909 | 1910 | return ret; 1911 | } 1912 | 1913 | /** 1914 | * @brief FIFO enable.[get] 1915 | * 1916 | * @param ctx read / write interface definitions 1917 | * @param val change the values of fifo_en in reg CTRL_REG5 1918 | * @retval interface status (MANDATORY: return 0 -> no Error) 1919 | * 1920 | */ 1921 | int32_t lis2dh12_fifo_get(const stmdev_ctx_t *ctx, uint8_t *val) 1922 | { 1923 | lis2dh12_ctrl_reg5_t ctrl_reg5; 1924 | int32_t ret; 1925 | 1926 | ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG5, 1927 | (uint8_t *)&ctrl_reg5, 1); 1928 | *val = (uint8_t)ctrl_reg5.fifo_en; 1929 | 1930 | return ret; 1931 | } 1932 | 1933 | /** 1934 | * @brief FIFO watermark level selection.[set] 1935 | * 1936 | * @param ctx read / write interface definitions 1937 | * @param val change the values of fth in reg FIFO_CTRL_REG 1938 | * @retval interface status (MANDATORY: return 0 -> no Error) 1939 | * 1940 | */ 1941 | int32_t lis2dh12_fifo_watermark_set(const stmdev_ctx_t *ctx, uint8_t val) 1942 | { 1943 | lis2dh12_fifo_ctrl_reg_t fifo_ctrl_reg; 1944 | int32_t ret; 1945 | 1946 | ret = lis2dh12_read_reg(ctx, LIS2DH12_FIFO_CTRL_REG, 1947 | (uint8_t *)&fifo_ctrl_reg, 1); 1948 | 1949 | if (ret == 0) 1950 | { 1951 | fifo_ctrl_reg.fth = val; 1952 | ret = lis2dh12_write_reg(ctx, LIS2DH12_FIFO_CTRL_REG, 1953 | (uint8_t *)&fifo_ctrl_reg, 1); 1954 | } 1955 | 1956 | return ret; 1957 | } 1958 | 1959 | /** 1960 | * @brief FIFO watermark level selection.[get] 1961 | * 1962 | * @param ctx read / write interface definitions 1963 | * @param val change the values of fth in reg FIFO_CTRL_REG 1964 | * @retval interface status (MANDATORY: return 0 -> no Error) 1965 | * 1966 | */ 1967 | int32_t lis2dh12_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val) 1968 | { 1969 | lis2dh12_fifo_ctrl_reg_t fifo_ctrl_reg; 1970 | int32_t ret; 1971 | 1972 | ret = lis2dh12_read_reg(ctx, LIS2DH12_FIFO_CTRL_REG, 1973 | (uint8_t *)&fifo_ctrl_reg, 1); 1974 | *val = (uint8_t)fifo_ctrl_reg.fth; 1975 | 1976 | return ret; 1977 | } 1978 | 1979 | /** 1980 | * @brief Trigger FIFO selection.[set] 1981 | * 1982 | * @param ctx read / write interface definitions 1983 | * @param val change the values of tr in reg FIFO_CTRL_REG 1984 | * @retval interface status (MANDATORY: return 0 -> no Error) 1985 | * 1986 | */ 1987 | int32_t lis2dh12_fifo_trigger_event_set(const stmdev_ctx_t *ctx, 1988 | lis2dh12_tr_t val) 1989 | { 1990 | lis2dh12_fifo_ctrl_reg_t fifo_ctrl_reg; 1991 | int32_t ret; 1992 | 1993 | ret = lis2dh12_read_reg(ctx, LIS2DH12_FIFO_CTRL_REG, 1994 | (uint8_t *)&fifo_ctrl_reg, 1); 1995 | 1996 | if (ret == 0) 1997 | { 1998 | fifo_ctrl_reg.tr = (uint8_t)val; 1999 | ret = lis2dh12_write_reg(ctx, LIS2DH12_FIFO_CTRL_REG, 2000 | (uint8_t *)&fifo_ctrl_reg, 1); 2001 | } 2002 | 2003 | return ret; 2004 | } 2005 | 2006 | /** 2007 | * @brief Trigger FIFO selection.[get] 2008 | * 2009 | * @param ctx read / write interface definitions 2010 | * @param val Get the values of tr in reg FIFO_CTRL_REG 2011 | * @retval interface status (MANDATORY: return 0 -> no Error) 2012 | * 2013 | */ 2014 | int32_t lis2dh12_fifo_trigger_event_get(const stmdev_ctx_t *ctx, 2015 | lis2dh12_tr_t *val) 2016 | { 2017 | lis2dh12_fifo_ctrl_reg_t fifo_ctrl_reg; 2018 | int32_t ret; 2019 | 2020 | ret = lis2dh12_read_reg(ctx, LIS2DH12_FIFO_CTRL_REG, 2021 | (uint8_t *)&fifo_ctrl_reg, 1); 2022 | 2023 | switch (fifo_ctrl_reg.tr) 2024 | { 2025 | case LIS2DH12_INT1_GEN: 2026 | *val = LIS2DH12_INT1_GEN; 2027 | break; 2028 | 2029 | case LIS2DH12_INT2_GEN: 2030 | *val = LIS2DH12_INT2_GEN; 2031 | break; 2032 | 2033 | default: 2034 | *val = LIS2DH12_INT1_GEN; 2035 | break; 2036 | } 2037 | 2038 | return ret; 2039 | } 2040 | 2041 | /** 2042 | * @brief FIFO mode selection.[set] 2043 | * 2044 | * @param ctx read / write interface definitions 2045 | * @param val change the values of fm in reg FIFO_CTRL_REG 2046 | * @retval interface status (MANDATORY: return 0 -> no Error) 2047 | * 2048 | */ 2049 | int32_t lis2dh12_fifo_mode_set(const stmdev_ctx_t *ctx, lis2dh12_fm_t val) 2050 | { 2051 | lis2dh12_fifo_ctrl_reg_t fifo_ctrl_reg; 2052 | int32_t ret; 2053 | 2054 | ret = lis2dh12_read_reg(ctx, LIS2DH12_FIFO_CTRL_REG, 2055 | (uint8_t *)&fifo_ctrl_reg, 1); 2056 | 2057 | if (ret == 0) 2058 | { 2059 | fifo_ctrl_reg.fm = (uint8_t)val; 2060 | ret = lis2dh12_write_reg(ctx, LIS2DH12_FIFO_CTRL_REG, 2061 | (uint8_t *)&fifo_ctrl_reg, 1); 2062 | } 2063 | 2064 | return ret; 2065 | } 2066 | 2067 | /** 2068 | * @brief FIFO mode selection.[get] 2069 | * 2070 | * @param ctx read / write interface definitions 2071 | * @param val Get the values of fm in reg FIFO_CTRL_REG 2072 | * @retval interface status (MANDATORY: return 0 -> no Error) 2073 | * 2074 | */ 2075 | int32_t lis2dh12_fifo_mode_get(const stmdev_ctx_t *ctx, lis2dh12_fm_t *val) 2076 | { 2077 | lis2dh12_fifo_ctrl_reg_t fifo_ctrl_reg; 2078 | int32_t ret; 2079 | 2080 | ret = lis2dh12_read_reg(ctx, LIS2DH12_FIFO_CTRL_REG, 2081 | (uint8_t *)&fifo_ctrl_reg, 1); 2082 | 2083 | switch (fifo_ctrl_reg.fm) 2084 | { 2085 | case LIS2DH12_BYPASS_MODE: 2086 | *val = LIS2DH12_BYPASS_MODE; 2087 | break; 2088 | 2089 | case LIS2DH12_FIFO_MODE: 2090 | *val = LIS2DH12_FIFO_MODE; 2091 | break; 2092 | 2093 | case LIS2DH12_DYNAMIC_STREAM_MODE: 2094 | *val = LIS2DH12_DYNAMIC_STREAM_MODE; 2095 | break; 2096 | 2097 | case LIS2DH12_STREAM_TO_FIFO_MODE: 2098 | *val = LIS2DH12_STREAM_TO_FIFO_MODE; 2099 | break; 2100 | 2101 | default: 2102 | *val = LIS2DH12_BYPASS_MODE; 2103 | break; 2104 | } 2105 | 2106 | return ret; 2107 | } 2108 | 2109 | /** 2110 | * @brief FIFO status register.[get] 2111 | * 2112 | * @param ctx read / write interface definitions 2113 | * @param val registers FIFO_SRC_REG 2114 | * @retval interface status (MANDATORY: return 0 -> no Error) 2115 | * 2116 | */ 2117 | int32_t lis2dh12_fifo_status_get(const stmdev_ctx_t *ctx, 2118 | lis2dh12_fifo_src_reg_t *val) 2119 | { 2120 | int32_t ret; 2121 | 2122 | ret = lis2dh12_read_reg(ctx, LIS2DH12_FIFO_SRC_REG, (uint8_t *) val, 1); 2123 | 2124 | return ret; 2125 | } 2126 | /** 2127 | * @brief FIFO stored data level.[get] 2128 | * 2129 | * @param ctx read / write interface definitions 2130 | * @param val change the values of fss in reg FIFO_SRC_REG 2131 | * @retval interface status (MANDATORY: return 0 -> no Error) 2132 | * 2133 | */ 2134 | int32_t lis2dh12_fifo_data_level_get(const stmdev_ctx_t *ctx, uint8_t *val) 2135 | { 2136 | lis2dh12_fifo_src_reg_t fifo_src_reg; 2137 | int32_t ret; 2138 | 2139 | ret = lis2dh12_read_reg(ctx, LIS2DH12_FIFO_SRC_REG, 2140 | (uint8_t *)&fifo_src_reg, 1); 2141 | *val = (uint8_t)fifo_src_reg.fss; 2142 | 2143 | return ret; 2144 | } 2145 | /** 2146 | * @brief Empty FIFO status flag.[get] 2147 | * 2148 | * @param ctx read / write interface definitions 2149 | * @param val change the values of empty in reg FIFO_SRC_REG 2150 | * @retval interface status (MANDATORY: return 0 -> no Error) 2151 | * 2152 | */ 2153 | int32_t lis2dh12_fifo_empty_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) 2154 | { 2155 | lis2dh12_fifo_src_reg_t fifo_src_reg; 2156 | int32_t ret; 2157 | 2158 | ret = lis2dh12_read_reg(ctx, LIS2DH12_FIFO_SRC_REG, 2159 | (uint8_t *)&fifo_src_reg, 1); 2160 | *val = (uint8_t)fifo_src_reg.empty; 2161 | 2162 | return ret; 2163 | } 2164 | /** 2165 | * @brief FIFO overrun status flag.[get] 2166 | * 2167 | * @param ctx read / write interface definitions 2168 | * @param val change the values of ovrn_fifo in reg FIFO_SRC_REG 2169 | * @retval interface status (MANDATORY: return 0 -> no Error) 2170 | * 2171 | */ 2172 | int32_t lis2dh12_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) 2173 | { 2174 | lis2dh12_fifo_src_reg_t fifo_src_reg; 2175 | int32_t ret; 2176 | 2177 | ret = lis2dh12_read_reg(ctx, LIS2DH12_FIFO_SRC_REG, 2178 | (uint8_t *)&fifo_src_reg, 1); 2179 | *val = (uint8_t)fifo_src_reg.ovrn_fifo; 2180 | 2181 | return ret; 2182 | } 2183 | /** 2184 | * @brief FIFO watermark status.[get] 2185 | * 2186 | * @param ctx read / write interface definitions 2187 | * @param val change the values of wtm in reg FIFO_SRC_REG 2188 | * @retval interface status (MANDATORY: return 0 -> no Error) 2189 | * 2190 | */ 2191 | int32_t lis2dh12_fifo_fth_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) 2192 | { 2193 | lis2dh12_fifo_src_reg_t fifo_src_reg; 2194 | int32_t ret; 2195 | 2196 | ret = lis2dh12_read_reg(ctx, LIS2DH12_FIFO_SRC_REG, 2197 | (uint8_t *)&fifo_src_reg, 1); 2198 | *val = (uint8_t)fifo_src_reg.wtm; 2199 | 2200 | return ret; 2201 | } 2202 | /** 2203 | * @} 2204 | * 2205 | */ 2206 | 2207 | /** 2208 | * @defgroup LIS2DH12_Tap_generator 2209 | * @brief This section group all the functions that manage the tap and 2210 | * double tap event generation 2211 | * @{ 2212 | * 2213 | */ 2214 | 2215 | /** 2216 | * @brief Tap/Double Tap generator configuration register.[set] 2217 | * 2218 | * @param ctx read / write interface definitions 2219 | * @param val registers CLICK_CFG 2220 | * @retval interface status (MANDATORY: return 0 -> no Error) 2221 | * 2222 | */ 2223 | int32_t lis2dh12_tap_conf_set(const stmdev_ctx_t *ctx, 2224 | lis2dh12_click_cfg_t *val) 2225 | { 2226 | int32_t ret; 2227 | 2228 | ret = lis2dh12_write_reg(ctx, LIS2DH12_CLICK_CFG, (uint8_t *) val, 1); 2229 | 2230 | return ret; 2231 | } 2232 | 2233 | /** 2234 | * @brief Tap/Double Tap generator configuration register.[get] 2235 | * 2236 | * @param ctx read / write interface definitions 2237 | * @param val registers CLICK_CFG 2238 | * @retval interface status (MANDATORY: return 0 -> no Error) 2239 | * 2240 | */ 2241 | int32_t lis2dh12_tap_conf_get(const stmdev_ctx_t *ctx, 2242 | lis2dh12_click_cfg_t *val) 2243 | { 2244 | int32_t ret; 2245 | 2246 | ret = lis2dh12_read_reg(ctx, LIS2DH12_CLICK_CFG, (uint8_t *) val, 1); 2247 | 2248 | return ret; 2249 | } 2250 | /** 2251 | * @brief Tap/Double Tap generator source register.[get] 2252 | * 2253 | * @param ctx read / write interface definitions 2254 | * @param val registers CLICK_SRC 2255 | * @retval interface status (MANDATORY: return 0 -> no Error) 2256 | * 2257 | */ 2258 | int32_t lis2dh12_tap_source_get(const stmdev_ctx_t *ctx, 2259 | lis2dh12_click_src_t *val) 2260 | { 2261 | int32_t ret; 2262 | 2263 | ret = lis2dh12_read_reg(ctx, LIS2DH12_CLICK_SRC, (uint8_t *) val, 1); 2264 | 2265 | return ret; 2266 | } 2267 | /** 2268 | * @brief User-defined threshold value for Tap/Double Tap event.[set] 2269 | * 1 LSB = full scale/128 2270 | * 2271 | * @param ctx read / write interface definitions 2272 | * @param val change the values of ths in reg CLICK_THS 2273 | * @retval interface status (MANDATORY: return 0 -> no Error) 2274 | * 2275 | */ 2276 | int32_t lis2dh12_tap_threshold_set(const stmdev_ctx_t *ctx, uint8_t val) 2277 | { 2278 | lis2dh12_click_ths_t click_ths; 2279 | int32_t ret; 2280 | 2281 | ret = lis2dh12_read_reg(ctx, LIS2DH12_CLICK_THS, 2282 | (uint8_t *)&click_ths, 1); 2283 | 2284 | if (ret == 0) 2285 | { 2286 | click_ths.ths = val; 2287 | ret = lis2dh12_write_reg(ctx, LIS2DH12_CLICK_THS, 2288 | (uint8_t *)&click_ths, 1); 2289 | } 2290 | 2291 | return ret; 2292 | } 2293 | 2294 | /** 2295 | * @brief User-defined threshold value for Tap/Double Tap event.[get] 2296 | * 1 LSB = full scale/128 2297 | * 2298 | * @param ctx read / write interface definitions 2299 | * @param val change the values of ths in reg CLICK_THS 2300 | * @retval interface status (MANDATORY: return 0 -> no Error) 2301 | * 2302 | */ 2303 | int32_t lis2dh12_tap_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) 2304 | { 2305 | lis2dh12_click_ths_t click_ths; 2306 | int32_t ret; 2307 | 2308 | ret = lis2dh12_read_reg(ctx, LIS2DH12_CLICK_THS, 2309 | (uint8_t *)&click_ths, 1); 2310 | *val = (uint8_t)click_ths.ths; 2311 | 2312 | return ret; 2313 | } 2314 | 2315 | /** 2316 | * @brief If the LIR_Click bit is not set, the interrupt is kept high 2317 | * for the duration of the latency window. 2318 | * If the LIR_Click bit is set, the interrupt is kept high until the 2319 | * CLICK_SRC(39h) register is read.[set] 2320 | * 2321 | * @param ctx read / write interface definitions 2322 | * @param val change the values of lir_click in reg CLICK_THS 2323 | * @retval interface status (MANDATORY: return 0 -> no Error) 2324 | * 2325 | */ 2326 | int32_t lis2dh12_tap_notification_mode_set(const stmdev_ctx_t *ctx, 2327 | lis2dh12_lir_click_t val) 2328 | { 2329 | lis2dh12_click_ths_t click_ths; 2330 | int32_t ret; 2331 | 2332 | ret = lis2dh12_read_reg(ctx, LIS2DH12_CLICK_THS, 2333 | (uint8_t *)&click_ths, 1); 2334 | 2335 | if (ret == 0) 2336 | { 2337 | click_ths.lir_click = (uint8_t)val; 2338 | ret = lis2dh12_write_reg(ctx, LIS2DH12_CLICK_THS, 2339 | (uint8_t *)&click_ths, 1); 2340 | } 2341 | 2342 | return ret; 2343 | } 2344 | 2345 | /** 2346 | * @brief If the LIR_Click bit is not set, the interrupt is kept high 2347 | * for the duration of the latency window. 2348 | * If the LIR_Click bit is set, the interrupt is kept high until the 2349 | * CLICK_SRC(39h) register is read.[get] 2350 | * 2351 | * @param ctx read / write interface definitions 2352 | * @param val Get the values of lir_click in reg CLICK_THS 2353 | * @retval interface status (MANDATORY: return 0 -> no Error) 2354 | * 2355 | */ 2356 | int32_t lis2dh12_tap_notification_mode_get(const stmdev_ctx_t *ctx, 2357 | lis2dh12_lir_click_t *val) 2358 | { 2359 | lis2dh12_click_ths_t click_ths; 2360 | int32_t ret; 2361 | 2362 | ret = lis2dh12_read_reg(ctx, LIS2DH12_CLICK_THS, 2363 | (uint8_t *)&click_ths, 1); 2364 | 2365 | switch (click_ths.lir_click) 2366 | { 2367 | case LIS2DH12_TAP_PULSED: 2368 | *val = LIS2DH12_TAP_PULSED; 2369 | break; 2370 | 2371 | case LIS2DH12_TAP_LATCHED: 2372 | *val = LIS2DH12_TAP_LATCHED; 2373 | break; 2374 | 2375 | default: 2376 | *val = LIS2DH12_TAP_PULSED; 2377 | break; 2378 | } 2379 | 2380 | return ret; 2381 | } 2382 | 2383 | /** 2384 | * @brief The maximum time (1 LSB = 1/ODR) interval that can elapse 2385 | * between the start of the click-detection procedure and when the 2386 | * acceleration falls back below the threshold.[set] 2387 | * 2388 | * @param ctx read / write interface definitions 2389 | * @param val change the values of tli in reg TIME_LIMIT 2390 | * @retval interface status (MANDATORY: return 0 -> no Error) 2391 | * 2392 | */ 2393 | int32_t lis2dh12_shock_dur_set(const stmdev_ctx_t *ctx, uint8_t val) 2394 | { 2395 | lis2dh12_time_limit_t time_limit; 2396 | int32_t ret; 2397 | 2398 | ret = lis2dh12_read_reg(ctx, LIS2DH12_TIME_LIMIT, 2399 | (uint8_t *)&time_limit, 1); 2400 | 2401 | if (ret == 0) 2402 | { 2403 | time_limit.tli = val; 2404 | ret = lis2dh12_write_reg(ctx, LIS2DH12_TIME_LIMIT, 2405 | (uint8_t *)&time_limit, 1); 2406 | } 2407 | 2408 | return ret; 2409 | } 2410 | 2411 | /** 2412 | * @brief The maximum time (1 LSB = 1/ODR) interval that can elapse between 2413 | * the start of the click-detection procedure and when the 2414 | * acceleration falls back below the threshold.[get] 2415 | * 2416 | * @param ctx read / write interface definitions 2417 | * @param val change the values of tli in reg TIME_LIMIT 2418 | * @retval interface status (MANDATORY: return 0 -> no Error) 2419 | * 2420 | */ 2421 | int32_t lis2dh12_shock_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) 2422 | { 2423 | lis2dh12_time_limit_t time_limit; 2424 | int32_t ret; 2425 | 2426 | ret = lis2dh12_read_reg(ctx, LIS2DH12_TIME_LIMIT, 2427 | (uint8_t *)&time_limit, 1); 2428 | *val = (uint8_t)time_limit.tli; 2429 | 2430 | return ret; 2431 | } 2432 | 2433 | /** 2434 | * @brief The time (1 LSB = 1/ODR) interval that starts after the first 2435 | * click detection where the click-detection procedure is 2436 | * disabled, in cases where the device is configured for 2437 | * double-click detection.[set] 2438 | * 2439 | * @param ctx read / write interface definitions 2440 | * @param val change the values of tla in reg TIME_LATENCY 2441 | * @retval interface status (MANDATORY: return 0 -> no Error) 2442 | * 2443 | */ 2444 | int32_t lis2dh12_quiet_dur_set(const stmdev_ctx_t *ctx, uint8_t val) 2445 | { 2446 | lis2dh12_time_latency_t time_latency; 2447 | int32_t ret; 2448 | 2449 | ret = lis2dh12_read_reg(ctx, LIS2DH12_TIME_LATENCY, 2450 | (uint8_t *)&time_latency, 1); 2451 | 2452 | if (ret == 0) 2453 | { 2454 | time_latency.tla = val; 2455 | ret = lis2dh12_write_reg(ctx, LIS2DH12_TIME_LATENCY, 2456 | (uint8_t *)&time_latency, 1); 2457 | } 2458 | 2459 | return ret; 2460 | } 2461 | 2462 | /** 2463 | * @brief The time (1 LSB = 1/ODR) interval that starts after the first 2464 | * click detection where the click-detection procedure is 2465 | * disabled, in cases where the device is configured for 2466 | * double-click detection.[get] 2467 | * 2468 | * @param ctx read / write interface definitions 2469 | * @param val change the values of tla in reg TIME_LATENCY 2470 | * @retval interface status (MANDATORY: return 0 -> no Error) 2471 | * 2472 | */ 2473 | int32_t lis2dh12_quiet_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) 2474 | { 2475 | lis2dh12_time_latency_t time_latency; 2476 | int32_t ret; 2477 | 2478 | ret = lis2dh12_read_reg(ctx, LIS2DH12_TIME_LATENCY, 2479 | (uint8_t *)&time_latency, 1); 2480 | *val = (uint8_t)time_latency.tla; 2481 | 2482 | return ret; 2483 | } 2484 | 2485 | /** 2486 | * @brief The maximum interval of time (1 LSB = 1/ODR) that can elapse 2487 | * after the end of the latency interval in which the click-detection 2488 | * procedure can start, in cases where the device is configured 2489 | * for double-click detection.[set] 2490 | * 2491 | * @param ctx read / write interface definitions 2492 | * @param val change the values of tw in reg TIME_WINDOW 2493 | * @retval interface status (MANDATORY: return 0 -> no Error) 2494 | * 2495 | */ 2496 | int32_t lis2dh12_double_tap_timeout_set(const stmdev_ctx_t *ctx, 2497 | uint8_t val) 2498 | { 2499 | lis2dh12_time_window_t time_window; 2500 | int32_t ret; 2501 | 2502 | ret = lis2dh12_read_reg(ctx, LIS2DH12_TIME_WINDOW, 2503 | (uint8_t *)&time_window, 1); 2504 | 2505 | if (ret == 0) 2506 | { 2507 | time_window.tw = val; 2508 | ret = lis2dh12_write_reg(ctx, LIS2DH12_TIME_WINDOW, 2509 | (uint8_t *)&time_window, 1); 2510 | } 2511 | 2512 | return ret; 2513 | } 2514 | 2515 | /** 2516 | * @brief The maximum interval of time (1 LSB = 1/ODR) that can elapse 2517 | * after the end of the latency interval in which the 2518 | * click-detection procedure can start, in cases where the device 2519 | * is configured for double-click detection.[get] 2520 | * 2521 | * @param ctx read / write interface definitions 2522 | * @param val change the values of tw in reg TIME_WINDOW 2523 | * @retval interface status (MANDATORY: return 0 -> no Error) 2524 | * 2525 | */ 2526 | int32_t lis2dh12_double_tap_timeout_get(const stmdev_ctx_t *ctx, 2527 | uint8_t *val) 2528 | { 2529 | lis2dh12_time_window_t time_window; 2530 | int32_t ret; 2531 | 2532 | ret = lis2dh12_read_reg(ctx, LIS2DH12_TIME_WINDOW, 2533 | (uint8_t *)&time_window, 1); 2534 | *val = (uint8_t)time_window.tw; 2535 | 2536 | return ret; 2537 | } 2538 | 2539 | /** 2540 | * @} 2541 | * 2542 | */ 2543 | 2544 | /** 2545 | * @defgroup LIS2DH12_Activity_inactivity 2546 | * @brief This section group all the functions concerning activity 2547 | * inactivity functionality 2548 | * @{ 2549 | * 2550 | */ 2551 | 2552 | /** 2553 | * @brief Sleep-to-wake, return-to-sleep activation threshold in 2554 | * low-power mode.[set] 2555 | * 1 LSb = 16mg@2g / 32mg@4g / 62mg@8g / 186mg@16g 2556 | * 2557 | * @param ctx read / write interface definitions 2558 | * @param val change the values of acth in reg ACT_THS 2559 | * @retval interface status (MANDATORY: return 0 -> no Error) 2560 | * 2561 | */ 2562 | int32_t lis2dh12_act_threshold_set(const stmdev_ctx_t *ctx, uint8_t val) 2563 | { 2564 | lis2dh12_act_ths_t act_ths; 2565 | int32_t ret; 2566 | 2567 | ret = lis2dh12_read_reg(ctx, LIS2DH12_ACT_THS, (uint8_t *)&act_ths, 1); 2568 | 2569 | if (ret == 0) 2570 | { 2571 | act_ths.acth = val; 2572 | ret = lis2dh12_write_reg(ctx, LIS2DH12_ACT_THS, (uint8_t *)&act_ths, 1); 2573 | } 2574 | 2575 | return ret; 2576 | } 2577 | 2578 | /** 2579 | * @brief Sleep-to-wake, return-to-sleep activation threshold in low-power 2580 | * mode.[get] 2581 | * 1 LSb = 16mg@2g / 32mg@4g / 62mg@8g / 186mg@16g 2582 | * 2583 | * @param ctx read / write interface definitions 2584 | * @param val change the values of acth in reg ACT_THS 2585 | * @retval interface status (MANDATORY: return 0 -> no Error) 2586 | * 2587 | */ 2588 | int32_t lis2dh12_act_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) 2589 | { 2590 | lis2dh12_act_ths_t act_ths; 2591 | int32_t ret; 2592 | 2593 | ret = lis2dh12_read_reg(ctx, LIS2DH12_ACT_THS, (uint8_t *)&act_ths, 1); 2594 | *val = (uint8_t)act_ths.acth; 2595 | 2596 | return ret; 2597 | } 2598 | 2599 | /** 2600 | * @brief Sleep-to-wake, return-to-sleep.[set] 2601 | * duration = (8*1[LSb]+1)/ODR 2602 | * 2603 | * @param ctx read / write interface definitions 2604 | * @param val change the values of actd in reg ACT_DUR 2605 | * @retval interface status (MANDATORY: return 0 -> no Error) 2606 | * 2607 | */ 2608 | int32_t lis2dh12_act_timeout_set(const stmdev_ctx_t *ctx, uint8_t val) 2609 | { 2610 | lis2dh12_act_dur_t act_dur; 2611 | int32_t ret; 2612 | 2613 | ret = lis2dh12_read_reg(ctx, LIS2DH12_ACT_DUR, (uint8_t *)&act_dur, 1); 2614 | 2615 | if (ret == 0) 2616 | { 2617 | act_dur.actd = val; 2618 | ret = lis2dh12_write_reg(ctx, LIS2DH12_ACT_DUR, (uint8_t *)&act_dur, 1); 2619 | } 2620 | 2621 | return ret; 2622 | } 2623 | 2624 | /** 2625 | * @brief Sleep-to-wake, return-to-sleep.[get] 2626 | * duration = (8*1[LSb]+1)/ODR 2627 | * 2628 | * @param ctx read / write interface definitions 2629 | * @param val change the values of actd in reg ACT_DUR 2630 | * @retval interface status (MANDATORY: return 0 -> no Error) 2631 | * 2632 | */ 2633 | int32_t lis2dh12_act_timeout_get(const stmdev_ctx_t *ctx, uint8_t *val) 2634 | { 2635 | lis2dh12_act_dur_t act_dur; 2636 | int32_t ret; 2637 | 2638 | ret = lis2dh12_read_reg(ctx, LIS2DH12_ACT_DUR, (uint8_t *)&act_dur, 1); 2639 | *val = (uint8_t)act_dur.actd; 2640 | 2641 | return ret; 2642 | } 2643 | 2644 | /** 2645 | * @} 2646 | * 2647 | */ 2648 | 2649 | /** 2650 | * @defgroup LIS2DH12_Serial_interface 2651 | * @brief This section group all the functions concerning serial 2652 | * interface management 2653 | * @{ 2654 | * 2655 | */ 2656 | 2657 | /** 2658 | * @brief Connect/Disconnect SDO/SA0 internal pull-up.[set] 2659 | * 2660 | * @param ctx read / write interface definitions 2661 | * @param val change the values of sdo_pu_disc in reg CTRL_REG0 2662 | * @retval interface status (MANDATORY: return 0 -> no Error) 2663 | * 2664 | */ 2665 | int32_t lis2dh12_pin_sdo_sa0_mode_set(const stmdev_ctx_t *ctx, 2666 | lis2dh12_sdo_pu_disc_t val) 2667 | { 2668 | lis2dh12_ctrl_reg0_t ctrl_reg0; 2669 | int32_t ret; 2670 | 2671 | ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG0, 2672 | (uint8_t *)&ctrl_reg0, 1); 2673 | 2674 | if (ret == 0) 2675 | { 2676 | ctrl_reg0.sdo_pu_disc = (uint8_t)val; 2677 | ret = lis2dh12_write_reg(ctx, LIS2DH12_CTRL_REG0, 2678 | (uint8_t *)&ctrl_reg0, 1); 2679 | } 2680 | 2681 | return ret; 2682 | } 2683 | 2684 | /** 2685 | * @brief Connect/Disconnect SDO/SA0 internal pull-up.[get] 2686 | * 2687 | * @param ctx read / write interface definitions 2688 | * @param val Get the values of sdo_pu_disc in reg CTRL_REG0 2689 | * @retval interface status (MANDATORY: return 0 -> no Error) 2690 | * 2691 | */ 2692 | int32_t lis2dh12_pin_sdo_sa0_mode_get(const stmdev_ctx_t *ctx, 2693 | lis2dh12_sdo_pu_disc_t *val) 2694 | { 2695 | lis2dh12_ctrl_reg0_t ctrl_reg0; 2696 | int32_t ret; 2697 | 2698 | ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG0, 2699 | (uint8_t *)&ctrl_reg0, 1); 2700 | 2701 | switch (ctrl_reg0.sdo_pu_disc) 2702 | { 2703 | case LIS2DH12_PULL_UP_DISCONNECT: 2704 | *val = LIS2DH12_PULL_UP_DISCONNECT; 2705 | break; 2706 | 2707 | case LIS2DH12_PULL_UP_CONNECT: 2708 | *val = LIS2DH12_PULL_UP_CONNECT; 2709 | break; 2710 | 2711 | default: 2712 | *val = LIS2DH12_PULL_UP_DISCONNECT; 2713 | break; 2714 | } 2715 | 2716 | return ret; 2717 | } 2718 | 2719 | /** 2720 | * @brief SPI Serial Interface Mode selection.[set] 2721 | * 2722 | * @param ctx read / write interface definitions 2723 | * @param val change the values of sim in reg CTRL_REG4 2724 | * @retval interface status (MANDATORY: return 0 -> no Error) 2725 | * 2726 | */ 2727 | int32_t lis2dh12_spi_mode_set(const stmdev_ctx_t *ctx, lis2dh12_sim_t val) 2728 | { 2729 | lis2dh12_ctrl_reg4_t ctrl_reg4; 2730 | int32_t ret; 2731 | 2732 | ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG4, 2733 | (uint8_t *)&ctrl_reg4, 1); 2734 | 2735 | if (ret == 0) 2736 | { 2737 | ctrl_reg4.sim = (uint8_t)val; 2738 | ret = lis2dh12_write_reg(ctx, LIS2DH12_CTRL_REG4, 2739 | (uint8_t *)&ctrl_reg4, 1); 2740 | } 2741 | 2742 | return ret; 2743 | } 2744 | 2745 | /** 2746 | * @brief SPI Serial Interface Mode selection.[get] 2747 | * 2748 | * @param ctx read / write interface definitions 2749 | * @param val Get the values of sim in reg CTRL_REG4 2750 | * @retval interface status (MANDATORY: return 0 -> no Error) 2751 | * 2752 | */ 2753 | int32_t lis2dh12_spi_mode_get(const stmdev_ctx_t *ctx, lis2dh12_sim_t *val) 2754 | { 2755 | lis2dh12_ctrl_reg4_t ctrl_reg4; 2756 | int32_t ret; 2757 | 2758 | ret = lis2dh12_read_reg(ctx, LIS2DH12_CTRL_REG4, 2759 | (uint8_t *)&ctrl_reg4, 1); 2760 | 2761 | switch (ctrl_reg4.sim) 2762 | { 2763 | case LIS2DH12_SPI_4_WIRE: 2764 | *val = LIS2DH12_SPI_4_WIRE; 2765 | break; 2766 | 2767 | case LIS2DH12_SPI_3_WIRE: 2768 | *val = LIS2DH12_SPI_3_WIRE; 2769 | break; 2770 | 2771 | default: 2772 | *val = LIS2DH12_SPI_4_WIRE; 2773 | break; 2774 | } 2775 | 2776 | return ret; 2777 | } 2778 | 2779 | /** 2780 | * @} 2781 | * 2782 | */ 2783 | 2784 | /** 2785 | * @} 2786 | * 2787 | */ 2788 | 2789 | 2790 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 2791 | -------------------------------------------------------------------------------- /lis2dh12_reg.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file lis2dh12_reg.h 4 | * @author Sensors Software Solution Team 5 | * @brief This file contains all the functions prototypes for the 6 | * lis2dh12_reg.c driver. 7 | ****************************************************************************** 8 | * @attention 9 | * 10 | *

© Copyright (c) 2021 STMicroelectronics. 11 | * All rights reserved.

12 | * 13 | * This software component is licensed by ST under BSD 3-Clause license, 14 | * the "License"; You may not use this file except in compliance with the 15 | * License. You may obtain a copy of the License at: 16 | * opensource.org/licenses/BSD-3-Clause 17 | * 18 | ****************************************************************************** 19 | */ 20 | 21 | /* Define to prevent recursive inclusion -------------------------------------*/ 22 | #ifndef LIS2DH12_REGS_H 23 | #define LIS2DH12_REGS_H 24 | 25 | #ifdef __cplusplus 26 | extern "C" { 27 | #endif 28 | 29 | /* Includes ------------------------------------------------------------------*/ 30 | #include 31 | #include 32 | #include 33 | 34 | /** @addtogroup LIS2DH12 35 | * @{ 36 | * 37 | */ 38 | 39 | /** @defgroup Endianness definitions 40 | * @{ 41 | * 42 | */ 43 | 44 | #ifndef DRV_BYTE_ORDER 45 | #ifndef __BYTE_ORDER__ 46 | 47 | #define DRV_LITTLE_ENDIAN 1234 48 | #define DRV_BIG_ENDIAN 4321 49 | 50 | /** if _BYTE_ORDER is not defined, choose the endianness of your architecture 51 | * by uncommenting the define which fits your platform endianness 52 | */ 53 | //#define DRV_BYTE_ORDER DRV_BIG_ENDIAN 54 | #define DRV_BYTE_ORDER DRV_LITTLE_ENDIAN 55 | 56 | #else /* defined __BYTE_ORDER__ */ 57 | 58 | #define DRV_LITTLE_ENDIAN __ORDER_LITTLE_ENDIAN__ 59 | #define DRV_BIG_ENDIAN __ORDER_BIG_ENDIAN__ 60 | #define DRV_BYTE_ORDER __BYTE_ORDER__ 61 | 62 | #endif /* __BYTE_ORDER__*/ 63 | #endif /* DRV_BYTE_ORDER */ 64 | 65 | /** 66 | * @} 67 | * 68 | */ 69 | 70 | /** @defgroup STMicroelectronics sensors common types 71 | * @{ 72 | * 73 | */ 74 | 75 | #ifndef MEMS_SHARED_TYPES 76 | #define MEMS_SHARED_TYPES 77 | 78 | typedef struct 79 | { 80 | #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 81 | uint8_t bit0 : 1; 82 | uint8_t bit1 : 1; 83 | uint8_t bit2 : 1; 84 | uint8_t bit3 : 1; 85 | uint8_t bit4 : 1; 86 | uint8_t bit5 : 1; 87 | uint8_t bit6 : 1; 88 | uint8_t bit7 : 1; 89 | #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 90 | uint8_t bit7 : 1; 91 | uint8_t bit6 : 1; 92 | uint8_t bit5 : 1; 93 | uint8_t bit4 : 1; 94 | uint8_t bit3 : 1; 95 | uint8_t bit2 : 1; 96 | uint8_t bit1 : 1; 97 | uint8_t bit0 : 1; 98 | #endif /* DRV_BYTE_ORDER */ 99 | } bitwise_t; 100 | 101 | #define PROPERTY_DISABLE (0U) 102 | #define PROPERTY_ENABLE (1U) 103 | 104 | /** @addtogroup Interfaces_Functions 105 | * @brief This section provide a set of functions used to read and 106 | * write a generic register of the device. 107 | * MANDATORY: return 0 -> no Error. 108 | * @{ 109 | * 110 | */ 111 | typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); 112 | typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); 113 | typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); 114 | 115 | typedef struct 116 | { 117 | /** Component mandatory fields **/ 118 | stmdev_write_ptr write_reg; 119 | stmdev_read_ptr read_reg; 120 | /** Component optional fields **/ 121 | stmdev_mdelay_ptr mdelay; 122 | /** Customizable optional pointer **/ 123 | void *handle; 124 | } stmdev_ctx_t; 125 | 126 | /** 127 | * @} 128 | * 129 | */ 130 | 131 | #endif /* MEMS_SHARED_TYPES */ 132 | 133 | #ifndef MEMS_UCF_SHARED_TYPES 134 | #define MEMS_UCF_SHARED_TYPES 135 | 136 | /** @defgroup Generic address-data structure definition 137 | * @brief This structure is useful to load a predefined configuration 138 | * of a sensor. 139 | * You can create a sensor configuration by your own or using 140 | * Unico / Unicleo tools available on STMicroelectronics 141 | * web site. 142 | * 143 | * @{ 144 | * 145 | */ 146 | 147 | typedef struct 148 | { 149 | uint8_t address; 150 | uint8_t data; 151 | } ucf_line_t; 152 | 153 | /** 154 | * @} 155 | * 156 | */ 157 | 158 | #endif /* MEMS_UCF_SHARED_TYPES */ 159 | 160 | /** 161 | * @} 162 | * 163 | */ 164 | 165 | /** @defgroup LIS2DH12_Infos 166 | * @{ 167 | * 168 | */ 169 | 170 | /** I2C Device Address 8 bit format if SA0=0 -> 31 if SA0=1 -> 33 **/ 171 | #define LIS2DH12_I2C_ADD_L 0x31U 172 | #define LIS2DH12_I2C_ADD_H 0x33U 173 | 174 | /** Device Identification (Who am I) **/ 175 | #define LIS2DH12_ID 0x33U 176 | 177 | /** 178 | * @} 179 | * 180 | */ 181 | 182 | #define LIS2DH12_STATUS_REG_AUX 0x07U 183 | typedef struct 184 | { 185 | #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 186 | uint8_t not_used_01 : 2; 187 | uint8_t tda : 1; 188 | uint8_t not_used_02 : 3; 189 | uint8_t tor : 1; 190 | uint8_t not_used_03 : 1; 191 | #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 192 | uint8_t not_used_03 : 1; 193 | uint8_t tor : 1; 194 | uint8_t not_used_02 : 3; 195 | uint8_t tda : 1; 196 | uint8_t not_used_01 : 2; 197 | #endif /* DRV_BYTE_ORDER */ 198 | } lis2dh12_status_reg_aux_t; 199 | 200 | #define LIS2DH12_OUT_TEMP_L 0x0CU 201 | #define LIS2DH12_OUT_TEMP_H 0x0DU 202 | #define LIS2DH12_WHO_AM_I 0x0FU 203 | 204 | #define LIS2DH12_CTRL_REG0 0x1EU 205 | typedef struct 206 | { 207 | #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 208 | uint8_t not_used_01 : 7; 209 | uint8_t sdo_pu_disc : 1; 210 | #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 211 | uint8_t sdo_pu_disc : 1; 212 | uint8_t not_used_01 : 7; 213 | #endif /* DRV_BYTE_ORDER */ 214 | } lis2dh12_ctrl_reg0_t; 215 | 216 | #define LIS2DH12_TEMP_CFG_REG 0x1FU 217 | typedef struct 218 | { 219 | #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 220 | uint8_t not_used_01 : 6; 221 | uint8_t temp_en : 2; 222 | #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 223 | uint8_t temp_en : 2; 224 | uint8_t not_used_01 : 6; 225 | #endif /* DRV_BYTE_ORDER */ 226 | } lis2dh12_temp_cfg_reg_t; 227 | 228 | #define LIS2DH12_CTRL_REG1 0x20U 229 | typedef struct 230 | { 231 | #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 232 | uint8_t xen : 1; 233 | uint8_t yen : 1; 234 | uint8_t zen : 1; 235 | uint8_t lpen : 1; 236 | uint8_t odr : 4; 237 | #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 238 | uint8_t odr : 4; 239 | uint8_t lpen : 1; 240 | uint8_t zen : 1; 241 | uint8_t yen : 1; 242 | uint8_t xen : 1; 243 | #endif /* DRV_BYTE_ORDER */ 244 | } lis2dh12_ctrl_reg1_t; 245 | 246 | #define LIS2DH12_CTRL_REG2 0x21U 247 | typedef struct 248 | { 249 | #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 250 | uint8_t hp : 3; /* HPCLICK + HP_IA2 + HP_IA1 -> HP */ 251 | uint8_t fds : 1; 252 | uint8_t hpcf : 2; 253 | uint8_t hpm : 2; 254 | #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 255 | uint8_t hpm : 2; 256 | uint8_t hpcf : 2; 257 | uint8_t fds : 1; 258 | uint8_t hp : 3; /* HPCLICK + HP_IA2 + HP_IA1 -> HP */ 259 | #endif /* DRV_BYTE_ORDER */ 260 | } lis2dh12_ctrl_reg2_t; 261 | 262 | #define LIS2DH12_CTRL_REG3 0x22U 263 | typedef struct 264 | { 265 | #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 266 | uint8_t not_used_01 : 1; 267 | uint8_t i1_overrun : 1; 268 | uint8_t i1_wtm : 1; 269 | uint8_t not_used_02 : 1; 270 | uint8_t i1_zyxda : 1; 271 | uint8_t i1_ia2 : 1; 272 | uint8_t i1_ia1 : 1; 273 | uint8_t i1_click : 1; 274 | #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 275 | uint8_t i1_click : 1; 276 | uint8_t i1_ia1 : 1; 277 | uint8_t i1_ia2 : 1; 278 | uint8_t i1_zyxda : 1; 279 | uint8_t not_used_02 : 1; 280 | uint8_t i1_wtm : 1; 281 | uint8_t i1_overrun : 1; 282 | uint8_t not_used_01 : 1; 283 | #endif /* DRV_BYTE_ORDER */ 284 | } lis2dh12_ctrl_reg3_t; 285 | 286 | #define LIS2DH12_CTRL_REG4 0x23U 287 | typedef struct 288 | { 289 | #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 290 | uint8_t sim : 1; 291 | uint8_t st : 2; 292 | uint8_t hr : 1; 293 | uint8_t fs : 2; 294 | uint8_t ble : 1; 295 | uint8_t bdu : 1; 296 | #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 297 | uint8_t bdu : 1; 298 | uint8_t ble : 1; 299 | uint8_t fs : 2; 300 | uint8_t hr : 1; 301 | uint8_t st : 2; 302 | uint8_t sim : 1; 303 | #endif /* DRV_BYTE_ORDER */ 304 | } lis2dh12_ctrl_reg4_t; 305 | 306 | #define LIS2DH12_CTRL_REG5 0x24U 307 | typedef struct 308 | { 309 | #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 310 | uint8_t d4d_int2 : 1; 311 | uint8_t lir_int2 : 1; 312 | uint8_t d4d_int1 : 1; 313 | uint8_t lir_int1 : 1; 314 | uint8_t not_used_01 : 2; 315 | uint8_t fifo_en : 1; 316 | uint8_t boot : 1; 317 | #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 318 | uint8_t boot : 1; 319 | uint8_t fifo_en : 1; 320 | uint8_t not_used_01 : 2; 321 | uint8_t lir_int1 : 1; 322 | uint8_t d4d_int1 : 1; 323 | uint8_t lir_int2 : 1; 324 | uint8_t d4d_int2 : 1; 325 | #endif /* DRV_BYTE_ORDER */ 326 | } lis2dh12_ctrl_reg5_t; 327 | 328 | #define LIS2DH12_CTRL_REG6 0x25U 329 | typedef struct 330 | { 331 | #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 332 | uint8_t not_used_01 : 1; 333 | uint8_t int_polarity : 1; 334 | uint8_t not_used_02 : 1; 335 | uint8_t i2_act : 1; 336 | uint8_t i2_boot : 1; 337 | uint8_t i2_ia2 : 1; 338 | uint8_t i2_ia1 : 1; 339 | uint8_t i2_click : 1; 340 | #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 341 | uint8_t i2_click : 1; 342 | uint8_t i2_ia1 : 1; 343 | uint8_t i2_ia2 : 1; 344 | uint8_t i2_boot : 1; 345 | uint8_t i2_act : 1; 346 | uint8_t not_used_02 : 1; 347 | uint8_t int_polarity : 1; 348 | uint8_t not_used_01 : 1; 349 | #endif /* DRV_BYTE_ORDER */ 350 | } lis2dh12_ctrl_reg6_t; 351 | 352 | #define LIS2DH12_REFERENCE 0x26U 353 | #define LIS2DH12_STATUS_REG 0x27U 354 | typedef struct 355 | { 356 | #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 357 | uint8_t xda : 1; 358 | uint8_t yda : 1; 359 | uint8_t zda : 1; 360 | uint8_t zyxda : 1; 361 | uint8_t _xor : 1; 362 | uint8_t yor : 1; 363 | uint8_t zor : 1; 364 | uint8_t zyxor : 1; 365 | #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 366 | uint8_t zyxor : 1; 367 | uint8_t zor : 1; 368 | uint8_t yor : 1; 369 | uint8_t _xor : 1; 370 | uint8_t zyxda : 1; 371 | uint8_t zda : 1; 372 | uint8_t yda : 1; 373 | uint8_t xda : 1; 374 | #endif /* DRV_BYTE_ORDER */ 375 | } lis2dh12_status_reg_t; 376 | 377 | #define LIS2DH12_OUT_X_L 0x28U 378 | #define LIS2DH12_OUT_X_H 0x29U 379 | #define LIS2DH12_OUT_Y_L 0x2AU 380 | #define LIS2DH12_OUT_Y_H 0x2BU 381 | #define LIS2DH12_OUT_Z_L 0x2CU 382 | #define LIS2DH12_OUT_Z_H 0x2DU 383 | #define LIS2DH12_FIFO_CTRL_REG 0x2EU 384 | typedef struct 385 | { 386 | #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 387 | uint8_t fth : 5; 388 | uint8_t tr : 1; 389 | uint8_t fm : 2; 390 | #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 391 | uint8_t fm : 2; 392 | uint8_t tr : 1; 393 | uint8_t fth : 5; 394 | #endif /* DRV_BYTE_ORDER */ 395 | } lis2dh12_fifo_ctrl_reg_t; 396 | 397 | #define LIS2DH12_FIFO_SRC_REG 0x2FU 398 | typedef struct 399 | { 400 | #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 401 | uint8_t fss : 5; 402 | uint8_t empty : 1; 403 | uint8_t ovrn_fifo : 1; 404 | uint8_t wtm : 1; 405 | #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 406 | uint8_t wtm : 1; 407 | uint8_t ovrn_fifo : 1; 408 | uint8_t empty : 1; 409 | uint8_t fss : 5; 410 | #endif /* DRV_BYTE_ORDER */ 411 | } lis2dh12_fifo_src_reg_t; 412 | 413 | #define LIS2DH12_INT1_CFG 0x30U 414 | typedef struct 415 | { 416 | #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 417 | uint8_t xlie : 1; 418 | uint8_t xhie : 1; 419 | uint8_t ylie : 1; 420 | uint8_t yhie : 1; 421 | uint8_t zlie : 1; 422 | uint8_t zhie : 1; 423 | uint8_t _6d : 1; 424 | uint8_t aoi : 1; 425 | #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 426 | uint8_t aoi : 1; 427 | uint8_t _6d : 1; 428 | uint8_t zhie : 1; 429 | uint8_t zlie : 1; 430 | uint8_t yhie : 1; 431 | uint8_t ylie : 1; 432 | uint8_t xhie : 1; 433 | uint8_t xlie : 1; 434 | #endif /* DRV_BYTE_ORDER */ 435 | } lis2dh12_int1_cfg_t; 436 | 437 | #define LIS2DH12_INT1_SRC 0x31U 438 | typedef struct 439 | { 440 | #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 441 | uint8_t xl : 1; 442 | uint8_t xh : 1; 443 | uint8_t yl : 1; 444 | uint8_t yh : 1; 445 | uint8_t zl : 1; 446 | uint8_t zh : 1; 447 | uint8_t ia : 1; 448 | uint8_t not_used_01 : 1; 449 | #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 450 | uint8_t not_used_01 : 1; 451 | uint8_t ia : 1; 452 | uint8_t zh : 1; 453 | uint8_t zl : 1; 454 | uint8_t yh : 1; 455 | uint8_t yl : 1; 456 | uint8_t xh : 1; 457 | uint8_t xl : 1; 458 | #endif /* DRV_BYTE_ORDER */ 459 | } lis2dh12_int1_src_t; 460 | 461 | #define LIS2DH12_INT1_THS 0x32U 462 | typedef struct 463 | { 464 | #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 465 | uint8_t ths : 7; 466 | uint8_t not_used_01 : 1; 467 | #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 468 | uint8_t not_used_01 : 1; 469 | uint8_t ths : 7; 470 | #endif /* DRV_BYTE_ORDER */ 471 | } lis2dh12_int1_ths_t; 472 | 473 | #define LIS2DH12_INT1_DURATION 0x33U 474 | typedef struct 475 | { 476 | #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 477 | uint8_t d : 7; 478 | uint8_t not_used_01 : 1; 479 | #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 480 | uint8_t not_used_01 : 1; 481 | uint8_t d : 7; 482 | #endif /* DRV_BYTE_ORDER */ 483 | } lis2dh12_int1_duration_t; 484 | 485 | #define LIS2DH12_INT2_CFG 0x34U 486 | typedef struct 487 | { 488 | #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 489 | uint8_t xlie : 1; 490 | uint8_t xhie : 1; 491 | uint8_t ylie : 1; 492 | uint8_t yhie : 1; 493 | uint8_t zlie : 1; 494 | uint8_t zhie : 1; 495 | uint8_t _6d : 1; 496 | uint8_t aoi : 1; 497 | #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 498 | uint8_t aoi : 1; 499 | uint8_t _6d : 1; 500 | uint8_t zhie : 1; 501 | uint8_t zlie : 1; 502 | uint8_t yhie : 1; 503 | uint8_t ylie : 1; 504 | uint8_t xhie : 1; 505 | uint8_t xlie : 1; 506 | #endif /* DRV_BYTE_ORDER */ 507 | } lis2dh12_int2_cfg_t; 508 | 509 | #define LIS2DH12_INT2_SRC 0x35U 510 | typedef struct 511 | { 512 | #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 513 | uint8_t xl : 1; 514 | uint8_t xh : 1; 515 | uint8_t yl : 1; 516 | uint8_t yh : 1; 517 | uint8_t zl : 1; 518 | uint8_t zh : 1; 519 | uint8_t ia : 1; 520 | uint8_t not_used_01 : 1; 521 | #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 522 | uint8_t not_used_01 : 1; 523 | uint8_t ia : 1; 524 | uint8_t zh : 1; 525 | uint8_t zl : 1; 526 | uint8_t yh : 1; 527 | uint8_t yl : 1; 528 | uint8_t xh : 1; 529 | uint8_t xl : 1; 530 | #endif /* DRV_BYTE_ORDER */ 531 | } lis2dh12_int2_src_t; 532 | 533 | #define LIS2DH12_INT2_THS 0x36U 534 | typedef struct 535 | { 536 | #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 537 | uint8_t ths : 7; 538 | uint8_t not_used_01 : 1; 539 | #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 540 | uint8_t not_used_01 : 1; 541 | uint8_t ths : 7; 542 | #endif /* DRV_BYTE_ORDER */ 543 | } lis2dh12_int2_ths_t; 544 | 545 | #define LIS2DH12_INT2_DURATION 0x37U 546 | typedef struct 547 | { 548 | #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 549 | uint8_t d : 7; 550 | uint8_t not_used_01 : 1; 551 | #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 552 | uint8_t not_used_01 : 1; 553 | uint8_t d : 7; 554 | #endif /* DRV_BYTE_ORDER */ 555 | } lis2dh12_int2_duration_t; 556 | 557 | #define LIS2DH12_CLICK_CFG 0x38U 558 | typedef struct 559 | { 560 | #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 561 | uint8_t xs : 1; 562 | uint8_t xd : 1; 563 | uint8_t ys : 1; 564 | uint8_t yd : 1; 565 | uint8_t zs : 1; 566 | uint8_t zd : 1; 567 | uint8_t not_used_01 : 2; 568 | #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 569 | uint8_t not_used_01 : 2; 570 | uint8_t zd : 1; 571 | uint8_t zs : 1; 572 | uint8_t yd : 1; 573 | uint8_t ys : 1; 574 | uint8_t xd : 1; 575 | uint8_t xs : 1; 576 | #endif /* DRV_BYTE_ORDER */ 577 | } lis2dh12_click_cfg_t; 578 | 579 | #define LIS2DH12_CLICK_SRC 0x39U 580 | typedef struct 581 | { 582 | #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 583 | uint8_t x : 1; 584 | uint8_t y : 1; 585 | uint8_t z : 1; 586 | uint8_t sign : 1; 587 | uint8_t sclick : 1; 588 | uint8_t dclick : 1; 589 | uint8_t ia : 1; 590 | uint8_t not_used_01 : 1; 591 | #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 592 | uint8_t not_used_01 : 1; 593 | uint8_t ia : 1; 594 | uint8_t dclick : 1; 595 | uint8_t sclick : 1; 596 | uint8_t sign : 1; 597 | uint8_t z : 1; 598 | uint8_t y : 1; 599 | uint8_t x : 1; 600 | #endif /* DRV_BYTE_ORDER */ 601 | } lis2dh12_click_src_t; 602 | 603 | #define LIS2DH12_CLICK_THS 0x3AU 604 | typedef struct 605 | { 606 | #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 607 | uint8_t ths : 7; 608 | uint8_t lir_click : 1; 609 | #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 610 | uint8_t lir_click : 1; 611 | uint8_t ths : 7; 612 | #endif /* DRV_BYTE_ORDER */ 613 | } lis2dh12_click_ths_t; 614 | 615 | #define LIS2DH12_TIME_LIMIT 0x3BU 616 | typedef struct 617 | { 618 | #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 619 | uint8_t tli : 7; 620 | uint8_t not_used_01 : 1; 621 | #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 622 | uint8_t not_used_01 : 1; 623 | uint8_t tli : 7; 624 | #endif /* DRV_BYTE_ORDER */ 625 | } lis2dh12_time_limit_t; 626 | 627 | #define LIS2DH12_TIME_LATENCY 0x3CU 628 | typedef struct 629 | { 630 | uint8_t tla : 8; 631 | } lis2dh12_time_latency_t; 632 | 633 | #define LIS2DH12_TIME_WINDOW 0x3DU 634 | typedef struct 635 | { 636 | uint8_t tw : 8; 637 | } lis2dh12_time_window_t; 638 | 639 | #define LIS2DH12_ACT_THS 0x3EU 640 | typedef struct 641 | { 642 | #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 643 | uint8_t acth : 7; 644 | uint8_t not_used_01 : 1; 645 | #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 646 | uint8_t not_used_01 : 1; 647 | uint8_t acth : 7; 648 | #endif /* DRV_BYTE_ORDER */ 649 | } lis2dh12_act_ths_t; 650 | 651 | #define LIS2DH12_ACT_DUR 0x3FU 652 | typedef struct 653 | { 654 | uint8_t actd : 8; 655 | } lis2dh12_act_dur_t; 656 | 657 | /** 658 | * @defgroup LIS2DH12_Register_Union 659 | * @brief This union group all the registers having a bit-field 660 | * description. 661 | * This union is useful but it's not needed by the driver. 662 | * 663 | * REMOVING this union you are compliant with: 664 | * MISRA-C 2012 [Rule 19.2] -> " Union are not allowed " 665 | * 666 | * @{ 667 | * 668 | */ 669 | typedef union 670 | { 671 | lis2dh12_status_reg_aux_t status_reg_aux; 672 | lis2dh12_ctrl_reg0_t ctrl_reg0; 673 | lis2dh12_temp_cfg_reg_t temp_cfg_reg; 674 | lis2dh12_ctrl_reg1_t ctrl_reg1; 675 | lis2dh12_ctrl_reg2_t ctrl_reg2; 676 | lis2dh12_ctrl_reg3_t ctrl_reg3; 677 | lis2dh12_ctrl_reg4_t ctrl_reg4; 678 | lis2dh12_ctrl_reg5_t ctrl_reg5; 679 | lis2dh12_ctrl_reg6_t ctrl_reg6; 680 | lis2dh12_status_reg_t status_reg; 681 | lis2dh12_fifo_ctrl_reg_t fifo_ctrl_reg; 682 | lis2dh12_fifo_src_reg_t fifo_src_reg; 683 | lis2dh12_int1_cfg_t int1_cfg; 684 | lis2dh12_int1_src_t int1_src; 685 | lis2dh12_int1_ths_t int1_ths; 686 | lis2dh12_int1_duration_t int1_duration; 687 | lis2dh12_int2_cfg_t int2_cfg; 688 | lis2dh12_int2_src_t int2_src; 689 | lis2dh12_int2_ths_t int2_ths; 690 | lis2dh12_int2_duration_t int2_duration; 691 | lis2dh12_click_cfg_t click_cfg; 692 | lis2dh12_click_src_t click_src; 693 | lis2dh12_click_ths_t click_ths; 694 | lis2dh12_time_limit_t time_limit; 695 | lis2dh12_time_latency_t time_latency; 696 | lis2dh12_time_window_t time_window; 697 | lis2dh12_act_ths_t act_ths; 698 | lis2dh12_act_dur_t act_dur; 699 | bitwise_t bitwise; 700 | uint8_t byte; 701 | } lis2dh12_reg_t; 702 | 703 | /** 704 | * @} 705 | * 706 | */ 707 | 708 | #ifndef __weak 709 | #define __weak __attribute__((weak)) 710 | #endif /* __weak */ 711 | 712 | /* 713 | * These are the basic platform dependent I/O routines to read 714 | * and write device registers connected on a standard bus. 715 | * The driver keeps offering a default implementation based on function 716 | * pointers to read/write routines for backward compatibility. 717 | * The __weak directive allows the final application to overwrite 718 | * them with a custom implementation. 719 | */ 720 | 721 | int32_t lis2dh12_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, 722 | uint8_t *data, 723 | uint16_t len); 724 | int32_t lis2dh12_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, 725 | uint8_t *data, 726 | uint16_t len); 727 | 728 | float_t lis2dh12_from_fs2_hr_to_mg(int16_t lsb); 729 | float_t lis2dh12_from_fs4_hr_to_mg(int16_t lsb); 730 | float_t lis2dh12_from_fs8_hr_to_mg(int16_t lsb); 731 | float_t lis2dh12_from_fs16_hr_to_mg(int16_t lsb); 732 | float_t lis2dh12_from_lsb_hr_to_celsius(int16_t lsb); 733 | 734 | float_t lis2dh12_from_fs2_nm_to_mg(int16_t lsb); 735 | float_t lis2dh12_from_fs4_nm_to_mg(int16_t lsb); 736 | float_t lis2dh12_from_fs8_nm_to_mg(int16_t lsb); 737 | float_t lis2dh12_from_fs16_nm_to_mg(int16_t lsb); 738 | float_t lis2dh12_from_lsb_nm_to_celsius(int16_t lsb); 739 | 740 | float_t lis2dh12_from_fs2_lp_to_mg(int16_t lsb); 741 | float_t lis2dh12_from_fs4_lp_to_mg(int16_t lsb); 742 | float_t lis2dh12_from_fs8_lp_to_mg(int16_t lsb); 743 | float_t lis2dh12_from_fs16_lp_to_mg(int16_t lsb); 744 | float_t lis2dh12_from_lsb_lp_to_celsius(int16_t lsb); 745 | 746 | int32_t lis2dh12_temp_status_reg_get(const stmdev_ctx_t *ctx, 747 | uint8_t *buff); 748 | int32_t lis2dh12_temp_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); 749 | 750 | int32_t lis2dh12_temp_data_ovr_get(const stmdev_ctx_t *ctx, uint8_t *val); 751 | 752 | int32_t lis2dh12_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val); 753 | 754 | typedef enum 755 | { 756 | LIS2DH12_TEMP_DISABLE = 0, 757 | LIS2DH12_TEMP_ENABLE = 3, 758 | } lis2dh12_temp_en_t; 759 | int32_t lis2dh12_temperature_meas_set(const stmdev_ctx_t *ctx, 760 | lis2dh12_temp_en_t val); 761 | int32_t lis2dh12_temperature_meas_get(const stmdev_ctx_t *ctx, 762 | lis2dh12_temp_en_t *val); 763 | 764 | typedef enum 765 | { 766 | LIS2DH12_HR_12bit = 0, 767 | LIS2DH12_NM_10bit = 1, 768 | LIS2DH12_LP_8bit = 2, 769 | } lis2dh12_op_md_t; 770 | int32_t lis2dh12_operating_mode_set(const stmdev_ctx_t *ctx, 771 | lis2dh12_op_md_t val); 772 | int32_t lis2dh12_operating_mode_get(const stmdev_ctx_t *ctx, 773 | lis2dh12_op_md_t *val); 774 | 775 | typedef enum 776 | { 777 | LIS2DH12_POWER_DOWN = 0x00, 778 | LIS2DH12_ODR_1Hz = 0x01, 779 | LIS2DH12_ODR_10Hz = 0x02, 780 | LIS2DH12_ODR_25Hz = 0x03, 781 | LIS2DH12_ODR_50Hz = 0x04, 782 | LIS2DH12_ODR_100Hz = 0x05, 783 | LIS2DH12_ODR_200Hz = 0x06, 784 | LIS2DH12_ODR_400Hz = 0x07, 785 | LIS2DH12_ODR_1kHz620_LP = 0x08, 786 | LIS2DH12_ODR_5kHz376_LP_1kHz344_NM_HP = 0x09, 787 | } lis2dh12_odr_t; 788 | int32_t lis2dh12_data_rate_set(const stmdev_ctx_t *ctx, lis2dh12_odr_t val); 789 | int32_t lis2dh12_data_rate_get(const stmdev_ctx_t *ctx, 790 | lis2dh12_odr_t *val); 791 | 792 | int32_t lis2dh12_high_pass_on_outputs_set(const stmdev_ctx_t *ctx, 793 | uint8_t val); 794 | int32_t lis2dh12_high_pass_on_outputs_get(const stmdev_ctx_t *ctx, 795 | uint8_t *val); 796 | 797 | typedef enum 798 | { 799 | LIS2DH12_AGGRESSIVE = 0, 800 | LIS2DH12_STRONG = 1, 801 | LIS2DH12_MEDIUM = 2, 802 | LIS2DH12_LIGHT = 3, 803 | } lis2dh12_hpcf_t; 804 | int32_t lis2dh12_high_pass_bandwidth_set(const stmdev_ctx_t *ctx, 805 | lis2dh12_hpcf_t val); 806 | int32_t lis2dh12_high_pass_bandwidth_get(const stmdev_ctx_t *ctx, 807 | lis2dh12_hpcf_t *val); 808 | 809 | typedef enum 810 | { 811 | LIS2DH12_NORMAL_WITH_RST = 0, 812 | LIS2DH12_REFERENCE_MODE = 1, 813 | LIS2DH12_NORMAL = 2, 814 | LIS2DH12_AUTORST_ON_INT = 3, 815 | } lis2dh12_hpm_t; 816 | int32_t lis2dh12_high_pass_mode_set(const stmdev_ctx_t *ctx, 817 | lis2dh12_hpm_t val); 818 | int32_t lis2dh12_high_pass_mode_get(const stmdev_ctx_t *ctx, 819 | lis2dh12_hpm_t *val); 820 | 821 | typedef enum 822 | { 823 | LIS2DH12_2g = 0, 824 | LIS2DH12_4g = 1, 825 | LIS2DH12_8g = 2, 826 | LIS2DH12_16g = 3, 827 | } lis2dh12_fs_t; 828 | int32_t lis2dh12_full_scale_set(const stmdev_ctx_t *ctx, lis2dh12_fs_t val); 829 | int32_t lis2dh12_full_scale_get(const stmdev_ctx_t *ctx, 830 | lis2dh12_fs_t *val); 831 | 832 | int32_t lis2dh12_block_data_update_set(const stmdev_ctx_t *ctx, 833 | uint8_t val); 834 | int32_t lis2dh12_block_data_update_get(const stmdev_ctx_t *ctx, 835 | uint8_t *val); 836 | 837 | int32_t lis2dh12_filter_reference_set(const stmdev_ctx_t *ctx, 838 | uint8_t *buff); 839 | int32_t lis2dh12_filter_reference_get(const stmdev_ctx_t *ctx, 840 | uint8_t *buff); 841 | 842 | int32_t lis2dh12_xl_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); 843 | 844 | int32_t lis2dh12_xl_data_ovr_get(const stmdev_ctx_t *ctx, uint8_t *val); 845 | 846 | int32_t lis2dh12_acceleration_raw_get(const stmdev_ctx_t *ctx, 847 | int16_t *val); 848 | 849 | int32_t lis2dh12_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff); 850 | 851 | typedef enum 852 | { 853 | LIS2DH12_ST_DISABLE = 0, 854 | LIS2DH12_ST_POSITIVE = 1, 855 | LIS2DH12_ST_NEGATIVE = 2, 856 | } lis2dh12_st_t; 857 | int32_t lis2dh12_self_test_set(const stmdev_ctx_t *ctx, lis2dh12_st_t val); 858 | int32_t lis2dh12_self_test_get(const stmdev_ctx_t *ctx, lis2dh12_st_t *val); 859 | 860 | typedef enum 861 | { 862 | LIS2DH12_LSB_AT_LOW_ADD = 0, 863 | LIS2DH12_MSB_AT_LOW_ADD = 1, 864 | } lis2dh12_ble_t; 865 | int32_t lis2dh12_data_format_set(const stmdev_ctx_t *ctx, 866 | lis2dh12_ble_t val); 867 | int32_t lis2dh12_data_format_get(const stmdev_ctx_t *ctx, 868 | lis2dh12_ble_t *val); 869 | 870 | int32_t lis2dh12_boot_set(const stmdev_ctx_t *ctx, uint8_t val); 871 | int32_t lis2dh12_boot_get(const stmdev_ctx_t *ctx, uint8_t *val); 872 | 873 | int32_t lis2dh12_status_get(const stmdev_ctx_t *ctx, 874 | lis2dh12_status_reg_t *val); 875 | 876 | int32_t lis2dh12_int1_gen_conf_set(const stmdev_ctx_t *ctx, 877 | lis2dh12_int1_cfg_t *val); 878 | int32_t lis2dh12_int1_gen_conf_get(const stmdev_ctx_t *ctx, 879 | lis2dh12_int1_cfg_t *val); 880 | 881 | int32_t lis2dh12_int1_gen_source_get(const stmdev_ctx_t *ctx, 882 | lis2dh12_int1_src_t *val); 883 | 884 | int32_t lis2dh12_int1_gen_threshold_set(const stmdev_ctx_t *ctx, 885 | uint8_t val); 886 | int32_t lis2dh12_int1_gen_threshold_get(const stmdev_ctx_t *ctx, 887 | uint8_t *val); 888 | 889 | int32_t lis2dh12_int1_gen_duration_set(const stmdev_ctx_t *ctx, 890 | uint8_t val); 891 | int32_t lis2dh12_int1_gen_duration_get(const stmdev_ctx_t *ctx, 892 | uint8_t *val); 893 | 894 | int32_t lis2dh12_int2_gen_conf_set(const stmdev_ctx_t *ctx, 895 | lis2dh12_int2_cfg_t *val); 896 | int32_t lis2dh12_int2_gen_conf_get(const stmdev_ctx_t *ctx, 897 | lis2dh12_int2_cfg_t *val); 898 | 899 | int32_t lis2dh12_int2_gen_source_get(const stmdev_ctx_t *ctx, 900 | lis2dh12_int2_src_t *val); 901 | 902 | int32_t lis2dh12_int2_gen_threshold_set(const stmdev_ctx_t *ctx, 903 | uint8_t val); 904 | int32_t lis2dh12_int2_gen_threshold_get(const stmdev_ctx_t *ctx, 905 | uint8_t *val); 906 | 907 | int32_t lis2dh12_int2_gen_duration_set(const stmdev_ctx_t *ctx, 908 | uint8_t val); 909 | int32_t lis2dh12_int2_gen_duration_get(const stmdev_ctx_t *ctx, 910 | uint8_t *val); 911 | 912 | typedef enum 913 | { 914 | LIS2DH12_DISC_FROM_INT_GENERATOR = 0, 915 | LIS2DH12_ON_INT1_GEN = 1, 916 | LIS2DH12_ON_INT2_GEN = 2, 917 | LIS2DH12_ON_TAP_GEN = 4, 918 | LIS2DH12_ON_INT1_INT2_GEN = 3, 919 | LIS2DH12_ON_INT1_TAP_GEN = 5, 920 | LIS2DH12_ON_INT2_TAP_GEN = 6, 921 | LIS2DH12_ON_INT1_INT2_TAP_GEN = 7, 922 | } lis2dh12_hp_t; 923 | int32_t lis2dh12_high_pass_int_conf_set(const stmdev_ctx_t *ctx, 924 | lis2dh12_hp_t val); 925 | int32_t lis2dh12_high_pass_int_conf_get(const stmdev_ctx_t *ctx, 926 | lis2dh12_hp_t *val); 927 | 928 | int32_t lis2dh12_pin_int1_config_set(const stmdev_ctx_t *ctx, 929 | lis2dh12_ctrl_reg3_t *val); 930 | int32_t lis2dh12_pin_int1_config_get(const stmdev_ctx_t *ctx, 931 | lis2dh12_ctrl_reg3_t *val); 932 | 933 | int32_t lis2dh12_int2_pin_detect_4d_set(const stmdev_ctx_t *ctx, 934 | uint8_t val); 935 | int32_t lis2dh12_int2_pin_detect_4d_get(const stmdev_ctx_t *ctx, 936 | uint8_t *val); 937 | 938 | typedef enum 939 | { 940 | LIS2DH12_INT2_PULSED = 0, 941 | LIS2DH12_INT2_LATCHED = 1, 942 | } lis2dh12_lir_int2_t; 943 | int32_t lis2dh12_int2_pin_notification_mode_set(const stmdev_ctx_t *ctx, 944 | lis2dh12_lir_int2_t val); 945 | int32_t lis2dh12_int2_pin_notification_mode_get(const stmdev_ctx_t *ctx, 946 | lis2dh12_lir_int2_t *val); 947 | 948 | int32_t lis2dh12_int1_pin_detect_4d_set(const stmdev_ctx_t *ctx, 949 | uint8_t val); 950 | int32_t lis2dh12_int1_pin_detect_4d_get(const stmdev_ctx_t *ctx, 951 | uint8_t *val); 952 | 953 | typedef enum 954 | { 955 | LIS2DH12_INT1_PULSED = 0, 956 | LIS2DH12_INT1_LATCHED = 1, 957 | } lis2dh12_lir_int1_t; 958 | int32_t lis2dh12_int1_pin_notification_mode_set(const stmdev_ctx_t *ctx, 959 | lis2dh12_lir_int1_t val); 960 | int32_t lis2dh12_int1_pin_notification_mode_get(const stmdev_ctx_t *ctx, 961 | lis2dh12_lir_int1_t *val); 962 | 963 | int32_t lis2dh12_pin_int2_config_set(const stmdev_ctx_t *ctx, 964 | lis2dh12_ctrl_reg6_t *val); 965 | int32_t lis2dh12_pin_int2_config_get(const stmdev_ctx_t *ctx, 966 | lis2dh12_ctrl_reg6_t *val); 967 | 968 | int32_t lis2dh12_fifo_set(const stmdev_ctx_t *ctx, uint8_t val); 969 | int32_t lis2dh12_fifo_get(const stmdev_ctx_t *ctx, uint8_t *val); 970 | 971 | int32_t lis2dh12_fifo_watermark_set(const stmdev_ctx_t *ctx, uint8_t val); 972 | int32_t lis2dh12_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val); 973 | 974 | typedef enum 975 | { 976 | LIS2DH12_INT1_GEN = 0, 977 | LIS2DH12_INT2_GEN = 1, 978 | } lis2dh12_tr_t; 979 | int32_t lis2dh12_fifo_trigger_event_set(const stmdev_ctx_t *ctx, 980 | lis2dh12_tr_t val); 981 | int32_t lis2dh12_fifo_trigger_event_get(const stmdev_ctx_t *ctx, 982 | lis2dh12_tr_t *val); 983 | 984 | typedef enum 985 | { 986 | LIS2DH12_BYPASS_MODE = 0, 987 | LIS2DH12_FIFO_MODE = 1, 988 | LIS2DH12_DYNAMIC_STREAM_MODE = 2, 989 | LIS2DH12_STREAM_TO_FIFO_MODE = 3, 990 | } lis2dh12_fm_t; 991 | int32_t lis2dh12_fifo_mode_set(const stmdev_ctx_t *ctx, lis2dh12_fm_t val); 992 | int32_t lis2dh12_fifo_mode_get(const stmdev_ctx_t *ctx, lis2dh12_fm_t *val); 993 | 994 | int32_t lis2dh12_fifo_status_get(const stmdev_ctx_t *ctx, 995 | lis2dh12_fifo_src_reg_t *val); 996 | 997 | int32_t lis2dh12_fifo_data_level_get(const stmdev_ctx_t *ctx, uint8_t *val); 998 | 999 | int32_t lis2dh12_fifo_empty_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); 1000 | 1001 | int32_t lis2dh12_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); 1002 | 1003 | int32_t lis2dh12_fifo_fth_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); 1004 | 1005 | int32_t lis2dh12_tap_conf_set(const stmdev_ctx_t *ctx, 1006 | lis2dh12_click_cfg_t *val); 1007 | int32_t lis2dh12_tap_conf_get(const stmdev_ctx_t *ctx, 1008 | lis2dh12_click_cfg_t *val); 1009 | 1010 | int32_t lis2dh12_tap_source_get(const stmdev_ctx_t *ctx, 1011 | lis2dh12_click_src_t *val); 1012 | 1013 | int32_t lis2dh12_tap_threshold_set(const stmdev_ctx_t *ctx, uint8_t val); 1014 | int32_t lis2dh12_tap_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val); 1015 | 1016 | typedef enum 1017 | { 1018 | LIS2DH12_TAP_PULSED = 0, 1019 | LIS2DH12_TAP_LATCHED = 1, 1020 | } lis2dh12_lir_click_t; 1021 | int32_t lis2dh12_tap_notification_mode_set(const stmdev_ctx_t *ctx, 1022 | lis2dh12_lir_click_t val); 1023 | int32_t lis2dh12_tap_notification_mode_get(const stmdev_ctx_t *ctx, 1024 | lis2dh12_lir_click_t *val); 1025 | 1026 | int32_t lis2dh12_shock_dur_set(const stmdev_ctx_t *ctx, uint8_t val); 1027 | int32_t lis2dh12_shock_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); 1028 | 1029 | int32_t lis2dh12_quiet_dur_set(const stmdev_ctx_t *ctx, uint8_t val); 1030 | int32_t lis2dh12_quiet_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); 1031 | 1032 | int32_t lis2dh12_double_tap_timeout_set(const stmdev_ctx_t *ctx, 1033 | uint8_t val); 1034 | int32_t lis2dh12_double_tap_timeout_get(const stmdev_ctx_t *ctx, 1035 | uint8_t *val); 1036 | 1037 | int32_t lis2dh12_act_threshold_set(const stmdev_ctx_t *ctx, uint8_t val); 1038 | int32_t lis2dh12_act_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val); 1039 | 1040 | int32_t lis2dh12_act_timeout_set(const stmdev_ctx_t *ctx, uint8_t val); 1041 | int32_t lis2dh12_act_timeout_get(const stmdev_ctx_t *ctx, uint8_t *val); 1042 | 1043 | typedef enum 1044 | { 1045 | LIS2DH12_PULL_UP_CONNECT = 0, 1046 | LIS2DH12_PULL_UP_DISCONNECT = 1, 1047 | } lis2dh12_sdo_pu_disc_t; 1048 | int32_t lis2dh12_pin_sdo_sa0_mode_set(const stmdev_ctx_t *ctx, 1049 | lis2dh12_sdo_pu_disc_t val); 1050 | int32_t lis2dh12_pin_sdo_sa0_mode_get(const stmdev_ctx_t *ctx, 1051 | lis2dh12_sdo_pu_disc_t *val); 1052 | 1053 | typedef enum 1054 | { 1055 | LIS2DH12_SPI_4_WIRE = 0, 1056 | LIS2DH12_SPI_3_WIRE = 1, 1057 | } lis2dh12_sim_t; 1058 | int32_t lis2dh12_spi_mode_set(const stmdev_ctx_t *ctx, lis2dh12_sim_t val); 1059 | int32_t lis2dh12_spi_mode_get(const stmdev_ctx_t *ctx, lis2dh12_sim_t *val); 1060 | 1061 | /** 1062 | * @} 1063 | * 1064 | */ 1065 | 1066 | #ifdef __cplusplus 1067 | } 1068 | #endif 1069 | 1070 | #endif /* LIS2DH12_REGS_H */ 1071 | 1072 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 1073 | --------------------------------------------------------------------------------