├── .gitmodules ├── CODE_OF_CONDUCT.md ├── CONTRIBUTING.md ├── Drivers └── CMSIS │ ├── Include │ ├── cmsis_armcc.h │ ├── cmsis_armclang.h │ ├── cmsis_armclang_ltm.h │ ├── cmsis_compiler.h │ ├── cmsis_gcc.h │ ├── cmsis_iccarm.h │ ├── cmsis_version.h │ ├── core_armv81mml.h │ ├── core_armv8mbl.h │ ├── core_armv8mml.h │ ├── core_cm0.h │ ├── core_cm0plus.h │ ├── core_cm1.h │ ├── core_cm23.h │ ├── core_cm3.h │ ├── core_cm33.h │ ├── core_cm35p.h │ ├── core_cm4.h │ ├── core_cm7.h │ ├── core_sc000.h │ ├── core_sc300.h │ ├── mpu_armv7.h │ ├── mpu_armv8.h │ └── tz_context.h │ └── LICENSE.txt ├── LICENSE.md ├── Projects └── NUCLEO-WL55JC │ ├── Applications │ └── OpenBootloader │ │ ├── Core │ │ ├── Inc │ │ │ ├── main.h │ │ │ ├── stm32wlxx_hal_conf.h │ │ │ └── stm32wlxx_it.h │ │ └── Src │ │ │ ├── main.c │ │ │ ├── stm32wlxx_hal_msp.c │ │ │ ├── stm32wlxx_it.c │ │ │ └── system_stm32wlxx.c │ │ ├── EWARM │ │ ├── OpenBootloader.ewd │ │ ├── OpenBootloader.ewp │ │ ├── OpenBootloader.eww │ │ ├── startup_stm32wl55xx_cm4.s │ │ └── stm32wl55xx_flash_cm4.icf │ │ ├── MDK-ARM │ │ ├── OpenBootloader.uvoptx │ │ ├── OpenBootloader.uvprojx │ │ ├── startup_stm32wl55xx_cm4.s │ │ └── stm32wl55xx_flash_cm4.sct │ │ ├── OpenBootloader │ │ ├── App │ │ │ ├── app_openbootloader.c │ │ │ └── app_openbootloader.h │ │ └── Target │ │ │ ├── common_interface.c │ │ │ ├── common_interface.h │ │ │ ├── engibytes_interface.c │ │ │ ├── engibytes_interface.h │ │ │ ├── flash_interface.c │ │ │ ├── flash_interface.h │ │ │ ├── interfaces_conf.h │ │ │ ├── iwdg_interface.c │ │ │ ├── iwdg_interface.h │ │ │ ├── openbootloader_conf.h │ │ │ ├── optionbytes_interface.c │ │ │ ├── optionbytes_interface.h │ │ │ ├── otp_interface.c │ │ │ ├── otp_interface.h │ │ │ ├── platform.h │ │ │ ├── ram_interface.c │ │ │ ├── ram_interface.h │ │ │ ├── spi_interface.c │ │ │ ├── spi_interface.h │ │ │ ├── systemmemory_interface.c │ │ │ ├── systemmemory_interface.h │ │ │ ├── usart_interface.c │ │ │ └── usart_interface.h │ │ ├── README.md │ │ └── STM32CubeIDE │ │ ├── .cproject │ │ ├── .project │ │ ├── Application │ │ ├── Core │ │ │ ├── syscalls.c │ │ │ └── sysmem.c │ │ └── Startup │ │ │ └── startup_stm32wl55jcix.s │ │ └── STM32WL55JCIX_FLASH.ld │ └── LICENSE.md └── README.md /.gitmodules: -------------------------------------------------------------------------------- 1 | [submodule "Drivers/CMSIS/Device/ST/STM32WLxx"] 2 | path = Drivers/CMSIS/Device/ST/STM32WLxx 3 | url = https://github.com/STMicroelectronics/cmsis_device_wl.git 4 | branch = main 5 | [submodule "Drivers/STM32WLxx_HAL_Driver"] 6 | path = Drivers/STM32WLxx_HAL_Driver 7 | url = https://github.com/STMicroelectronics/stm32wlxx_hal_driver.git 8 | branch = main 9 | [submodule "Middlewares/ST/OpenBootloader"] 10 | path = Middlewares/ST/OpenBootloader 11 | url = https://github.com/STMicroelectronics/stm32-mw-openbl.git 12 | branch = main 13 | -------------------------------------------------------------------------------- /CODE_OF_CONDUCT.md: -------------------------------------------------------------------------------- 1 | # Contributor Covenant Code of Conduct 2 | 3 | ## Our Pledge 4 | 5 | In the interest of fostering an open and welcoming environment, we as 6 | contributors and maintainers pledge to making participation in our project and 7 | our community a harassment-free experience for everyone, regardless of age, body 8 | size, disability, ethnicity, sex characteristics, gender identity and expression, 9 | level of experience, education, socio-economic status, nationality, personal 10 | appearance, race, religion, or sexual identity and orientation. 11 | 12 | ## Our Standards 13 | 14 | Examples of behavior that contributes to creating a positive environment 15 | include: 16 | 17 | * Using welcoming and inclusive language 18 | * Being respectful of differing viewpoints and experiences 19 | * Gracefully accepting constructive criticism 20 | * Focusing on what is best for the community 21 | * Showing empathy towards other community members 22 | 23 | Examples of unacceptable behavior by participants include: 24 | 25 | * The use of sexualized language or imagery and unwelcome sexual attention or 26 | advances 27 | * Trolling, insulting/derogatory comments, and personal or political attacks 28 | * Public or private harassment 29 | * Publishing others' private information, such as a physical or electronic 30 | address, without explicit permission 31 | * Other conduct which could reasonably be considered inappropriate in a 32 | professional setting 33 | 34 | ## Our Responsibilities 35 | 36 | Project maintainers are responsible for clarifying the standards of acceptable 37 | behavior and are expected to take appropriate and fair corrective action in 38 | response to any instances of unacceptable behavior. 39 | 40 | Project maintainers have the right and responsibility to remove, edit, or 41 | reject comments, commits, code, wiki edits, issues, and other contributions 42 | that are not aligned to this Code of Conduct, or to ban temporarily or 43 | permanently any contributor for other behaviors that they deem inappropriate, 44 | threatening, offensive, or harmful. 45 | 46 | ## Scope 47 | 48 | This Code of Conduct applies both within project spaces and in public spaces 49 | when an individual is representing the project or its community. Examples of 50 | representing a project or community include using an official project e-mail 51 | address, posting via an official social media account, or acting as an appointed 52 | representative at an online or offline event. Representation of a project may be 53 | further defined and clarified by project maintainers. 54 | 55 | ## Enforcement 56 | 57 | Instances of abusive, harassing, or otherwise unacceptable behavior may be 58 | reported by contacting the project team via this [link](https://www.st.com/content/st_com/en/contact-us.html). 59 | All complaints will be reviewed and investigated and will result in a response that 60 | is deemed necessary and appropriate to the circumstances. The project team is 61 | obligated to maintain confidentiality with regard to the reporter of an incident. 62 | Further details of specific enforcement policies may be posted separately. 63 | 64 | Project maintainers who do not follow or enforce the Code of Conduct in good 65 | faith may face temporary or permanent repercussions as determined by other 66 | members of the project's leadership. 67 | 68 | ## Attribution 69 | 70 | This Code of Conduct is adapted from the [Contributor Covenant](https://www.contributor-covenant.org), version 1.4, 71 | available [here](https://www.contributor-covenant.org/version/1/4/code-of-conduct.html). 72 | 73 | For answers to common questions about this code of conduct, refer to the FAQ section [here](https://www.contributor-covenant.org/faq). 74 | -------------------------------------------------------------------------------- /CONTRIBUTING.md: -------------------------------------------------------------------------------- 1 | # Contributing guide 2 | 3 | This guide serves as a checklist before contributing to this repository. It mainly focuses on the steps to follow to submit an issue or a pull-request. 4 | 5 | ## 1. Issues 6 | 7 | ### 1.1 Before opening an issue 8 | 9 | Please check the following points before posting an issue: 10 | * Make sure you are using the latest commit (major releases are tagged, but corrections are available as new commits). 11 | * Make sure your issue is a question/feedback/suggestions **related to** the software provided in this repository. Otherwise, please refer to section [3](CONTRIBUTING.md#3-support-requests-and-questions) below. 12 | * Make sure your issue is not already reported/fixed on GitHub or discussed on a previous issue. Do not forget to browse into the **closed** issues. 13 | 14 | ### 1.2 Posting the issue 15 | 16 | When you have checked the previous points, create a new report from the **Issues** tab of this repository. A template is available [here](../../issues/new/choose) to help you report the issue you are facing or the enhancement you would like to propose. 17 | 18 | ## 2. Pull Requests 19 | 20 | Pull-requests are **not** accepted on this repository. Please use **issues** to report any bug or request. 21 | 22 | ## 3. Support requests and questions 23 | 24 | For support requests or any other question related to the product, the tools, the environment, you can submit a post to the **ST Community** on the appropriate topic [page](https://community.st.com/s/topiccatalog). 25 | -------------------------------------------------------------------------------- /Drivers/CMSIS/Include/cmsis_compiler.h: -------------------------------------------------------------------------------- 1 | /**************************************************************************//** 2 | * @file cmsis_compiler.h 3 | * @brief CMSIS compiler generic header file 4 | * @version V5.1.0 5 | * @date 09. October 2018 6 | ******************************************************************************/ 7 | /* 8 | * Copyright (c) 2009-2018 Arm Limited. All rights reserved. 9 | * 10 | * SPDX-License-Identifier: Apache-2.0 11 | * 12 | * Licensed under the Apache License, Version 2.0 (the License); you may 13 | * not use this file except in compliance with the License. 14 | * You may obtain a copy of the License at 15 | * 16 | * www.apache.org/licenses/LICENSE-2.0 17 | * 18 | * Unless required by applicable law or agreed to in writing, software 19 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 20 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 | * See the License for the specific language governing permissions and 22 | * limitations under the License. 23 | */ 24 | 25 | #ifndef __CMSIS_COMPILER_H 26 | #define __CMSIS_COMPILER_H 27 | 28 | #include 29 | 30 | /* 31 | * Arm Compiler 4/5 32 | */ 33 | #if defined ( __CC_ARM ) 34 | #include "cmsis_armcc.h" 35 | 36 | 37 | /* 38 | * Arm Compiler 6.6 LTM (armclang) 39 | */ 40 | #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100) 41 | #include "cmsis_armclang_ltm.h" 42 | 43 | /* 44 | * Arm Compiler above 6.10.1 (armclang) 45 | */ 46 | #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100) 47 | #include "cmsis_armclang.h" 48 | 49 | 50 | /* 51 | * GNU Compiler 52 | */ 53 | #elif defined ( __GNUC__ ) 54 | #include "cmsis_gcc.h" 55 | 56 | 57 | /* 58 | * IAR Compiler 59 | */ 60 | #elif defined ( __ICCARM__ ) 61 | #include 62 | 63 | 64 | /* 65 | * TI Arm Compiler 66 | */ 67 | #elif defined ( __TI_ARM__ ) 68 | #include 69 | 70 | #ifndef __ASM 71 | #define __ASM __asm 72 | #endif 73 | #ifndef __INLINE 74 | #define __INLINE inline 75 | #endif 76 | #ifndef __STATIC_INLINE 77 | #define __STATIC_INLINE static inline 78 | #endif 79 | #ifndef __STATIC_FORCEINLINE 80 | #define __STATIC_FORCEINLINE __STATIC_INLINE 81 | #endif 82 | #ifndef __NO_RETURN 83 | #define __NO_RETURN __attribute__((noreturn)) 84 | #endif 85 | #ifndef __USED 86 | #define __USED __attribute__((used)) 87 | #endif 88 | #ifndef __WEAK 89 | #define __WEAK __attribute__((weak)) 90 | #endif 91 | #ifndef __PACKED 92 | #define __PACKED __attribute__((packed)) 93 | #endif 94 | #ifndef __PACKED_STRUCT 95 | #define __PACKED_STRUCT struct __attribute__((packed)) 96 | #endif 97 | #ifndef __PACKED_UNION 98 | #define __PACKED_UNION union __attribute__((packed)) 99 | #endif 100 | #ifndef __UNALIGNED_UINT32 /* deprecated */ 101 | struct __attribute__((packed)) T_UINT32 { uint32_t v; }; 102 | #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) 103 | #endif 104 | #ifndef __UNALIGNED_UINT16_WRITE 105 | __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; 106 | #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) 107 | #endif 108 | #ifndef __UNALIGNED_UINT16_READ 109 | __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; 110 | #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) 111 | #endif 112 | #ifndef __UNALIGNED_UINT32_WRITE 113 | __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; 114 | #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) 115 | #endif 116 | #ifndef __UNALIGNED_UINT32_READ 117 | __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; 118 | #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) 119 | #endif 120 | #ifndef __ALIGNED 121 | #define __ALIGNED(x) __attribute__((aligned(x))) 122 | #endif 123 | #ifndef __RESTRICT 124 | #define __RESTRICT __restrict 125 | #endif 126 | #ifndef __COMPILER_BARRIER 127 | #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. 128 | #define __COMPILER_BARRIER() (void)0 129 | #endif 130 | 131 | 132 | /* 133 | * TASKING Compiler 134 | */ 135 | #elif defined ( __TASKING__ ) 136 | /* 137 | * The CMSIS functions have been implemented as intrinsics in the compiler. 138 | * Please use "carm -?i" to get an up to date list of all intrinsics, 139 | * Including the CMSIS ones. 140 | */ 141 | 142 | #ifndef __ASM 143 | #define __ASM __asm 144 | #endif 145 | #ifndef __INLINE 146 | #define __INLINE inline 147 | #endif 148 | #ifndef __STATIC_INLINE 149 | #define __STATIC_INLINE static inline 150 | #endif 151 | #ifndef __STATIC_FORCEINLINE 152 | #define __STATIC_FORCEINLINE __STATIC_INLINE 153 | #endif 154 | #ifndef __NO_RETURN 155 | #define __NO_RETURN __attribute__((noreturn)) 156 | #endif 157 | #ifndef __USED 158 | #define __USED __attribute__((used)) 159 | #endif 160 | #ifndef __WEAK 161 | #define __WEAK __attribute__((weak)) 162 | #endif 163 | #ifndef __PACKED 164 | #define __PACKED __packed__ 165 | #endif 166 | #ifndef __PACKED_STRUCT 167 | #define __PACKED_STRUCT struct __packed__ 168 | #endif 169 | #ifndef __PACKED_UNION 170 | #define __PACKED_UNION union __packed__ 171 | #endif 172 | #ifndef __UNALIGNED_UINT32 /* deprecated */ 173 | struct __packed__ T_UINT32 { uint32_t v; }; 174 | #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) 175 | #endif 176 | #ifndef __UNALIGNED_UINT16_WRITE 177 | __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; 178 | #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) 179 | #endif 180 | #ifndef __UNALIGNED_UINT16_READ 181 | __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; 182 | #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) 183 | #endif 184 | #ifndef __UNALIGNED_UINT32_WRITE 185 | __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; 186 | #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) 187 | #endif 188 | #ifndef __UNALIGNED_UINT32_READ 189 | __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; 190 | #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) 191 | #endif 192 | #ifndef __ALIGNED 193 | #define __ALIGNED(x) __align(x) 194 | #endif 195 | #ifndef __RESTRICT 196 | #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. 197 | #define __RESTRICT 198 | #endif 199 | #ifndef __COMPILER_BARRIER 200 | #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. 201 | #define __COMPILER_BARRIER() (void)0 202 | #endif 203 | 204 | 205 | /* 206 | * COSMIC Compiler 207 | */ 208 | #elif defined ( __CSMC__ ) 209 | #include 210 | 211 | #ifndef __ASM 212 | #define __ASM _asm 213 | #endif 214 | #ifndef __INLINE 215 | #define __INLINE inline 216 | #endif 217 | #ifndef __STATIC_INLINE 218 | #define __STATIC_INLINE static inline 219 | #endif 220 | #ifndef __STATIC_FORCEINLINE 221 | #define __STATIC_FORCEINLINE __STATIC_INLINE 222 | #endif 223 | #ifndef __NO_RETURN 224 | // NO RETURN is automatically detected hence no warning here 225 | #define __NO_RETURN 226 | #endif 227 | #ifndef __USED 228 | #warning No compiler specific solution for __USED. __USED is ignored. 229 | #define __USED 230 | #endif 231 | #ifndef __WEAK 232 | #define __WEAK __weak 233 | #endif 234 | #ifndef __PACKED 235 | #define __PACKED @packed 236 | #endif 237 | #ifndef __PACKED_STRUCT 238 | #define __PACKED_STRUCT @packed struct 239 | #endif 240 | #ifndef __PACKED_UNION 241 | #define __PACKED_UNION @packed union 242 | #endif 243 | #ifndef __UNALIGNED_UINT32 /* deprecated */ 244 | @packed struct T_UINT32 { uint32_t v; }; 245 | #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) 246 | #endif 247 | #ifndef __UNALIGNED_UINT16_WRITE 248 | __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; 249 | #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) 250 | #endif 251 | #ifndef __UNALIGNED_UINT16_READ 252 | __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; 253 | #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) 254 | #endif 255 | #ifndef __UNALIGNED_UINT32_WRITE 256 | __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; 257 | #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) 258 | #endif 259 | #ifndef __UNALIGNED_UINT32_READ 260 | __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; 261 | #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) 262 | #endif 263 | #ifndef __ALIGNED 264 | #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. 265 | #define __ALIGNED(x) 266 | #endif 267 | #ifndef __RESTRICT 268 | #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. 269 | #define __RESTRICT 270 | #endif 271 | #ifndef __COMPILER_BARRIER 272 | #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. 273 | #define __COMPILER_BARRIER() (void)0 274 | #endif 275 | 276 | 277 | #else 278 | #error Unknown compiler. 279 | #endif 280 | 281 | 282 | #endif /* __CMSIS_COMPILER_H */ 283 | 284 | -------------------------------------------------------------------------------- /Drivers/CMSIS/Include/cmsis_version.h: -------------------------------------------------------------------------------- 1 | /**************************************************************************//** 2 | * @file cmsis_version.h 3 | * @brief CMSIS Core(M) Version definitions 4 | * @version V5.0.3 5 | * @date 24. June 2019 6 | ******************************************************************************/ 7 | /* 8 | * Copyright (c) 2009-2019 ARM Limited. All rights reserved. 9 | * 10 | * SPDX-License-Identifier: Apache-2.0 11 | * 12 | * Licensed under the Apache License, Version 2.0 (the License); you may 13 | * not use this file except in compliance with the License. 14 | * You may obtain a copy of the License at 15 | * 16 | * www.apache.org/licenses/LICENSE-2.0 17 | * 18 | * Unless required by applicable law or agreed to in writing, software 19 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 20 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 | * See the License for the specific language governing permissions and 22 | * limitations under the License. 23 | */ 24 | 25 | #if defined ( __ICCARM__ ) 26 | #pragma system_include /* treat file as system include file for MISRA check */ 27 | #elif defined (__clang__) 28 | #pragma clang system_header /* treat file as system include file */ 29 | #endif 30 | 31 | #ifndef __CMSIS_VERSION_H 32 | #define __CMSIS_VERSION_H 33 | 34 | /* CMSIS Version definitions */ 35 | #define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ 36 | #define __CM_CMSIS_VERSION_SUB ( 3U) /*!< [15:0] CMSIS Core(M) sub version */ 37 | #define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ 38 | __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ 39 | #endif 40 | -------------------------------------------------------------------------------- /Drivers/CMSIS/Include/mpu_armv7.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * @file mpu_armv7.h 3 | * @brief CMSIS MPU API for Armv7-M MPU 4 | * @version V5.1.0 5 | * @date 08. March 2019 6 | ******************************************************************************/ 7 | /* 8 | * Copyright (c) 2017-2019 Arm Limited. All rights reserved. 9 | * 10 | * SPDX-License-Identifier: Apache-2.0 11 | * 12 | * Licensed under the Apache License, Version 2.0 (the License); you may 13 | * not use this file except in compliance with the License. 14 | * You may obtain a copy of the License at 15 | * 16 | * www.apache.org/licenses/LICENSE-2.0 17 | * 18 | * Unless required by applicable law or agreed to in writing, software 19 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 20 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 | * See the License for the specific language governing permissions and 22 | * limitations under the License. 23 | */ 24 | 25 | #if defined ( __ICCARM__ ) 26 | #pragma system_include /* treat file as system include file for MISRA check */ 27 | #elif defined (__clang__) 28 | #pragma clang system_header /* treat file as system include file */ 29 | #endif 30 | 31 | #ifndef ARM_MPU_ARMV7_H 32 | #define ARM_MPU_ARMV7_H 33 | 34 | #define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes 35 | #define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes 36 | #define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes 37 | #define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes 38 | #define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes 39 | #define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte 40 | #define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes 41 | #define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes 42 | #define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes 43 | #define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes 44 | #define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes 45 | #define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes 46 | #define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes 47 | #define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes 48 | #define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes 49 | #define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte 50 | #define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes 51 | #define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes 52 | #define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes 53 | #define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes 54 | #define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes 55 | #define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes 56 | #define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes 57 | #define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes 58 | #define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes 59 | #define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte 60 | #define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes 61 | #define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes 62 | 63 | #define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access 64 | #define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only 65 | #define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only 66 | #define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access 67 | #define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only 68 | #define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access 69 | 70 | /** MPU Region Base Address Register Value 71 | * 72 | * \param Region The region to be configured, number 0 to 15. 73 | * \param BaseAddress The base address for the region. 74 | */ 75 | #define ARM_MPU_RBAR(Region, BaseAddress) \ 76 | (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \ 77 | ((Region) & MPU_RBAR_REGION_Msk) | \ 78 | (MPU_RBAR_VALID_Msk)) 79 | 80 | /** 81 | * MPU Memory Access Attributes 82 | * 83 | * \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. 84 | * \param IsShareable Region is shareable between multiple bus masters. 85 | * \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. 86 | * \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. 87 | */ 88 | #define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \ 89 | ((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \ 90 | (((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \ 91 | (((IsCacheable) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \ 92 | (((IsBufferable) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk)) 93 | 94 | /** 95 | * MPU Region Attribute and Size Register Value 96 | * 97 | * \param DisableExec Instruction access disable bit, 1= disable instruction fetches. 98 | * \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. 99 | * \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_. 100 | * \param SubRegionDisable Sub-region disable field. 101 | * \param Size Region size of the region to be configured, for example 4K, 8K. 102 | */ 103 | #define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \ 104 | ((((DisableExec) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \ 105 | (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \ 106 | (((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \ 107 | (((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \ 108 | (((Size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \ 109 | (((MPU_RASR_ENABLE_Msk)))) 110 | 111 | /** 112 | * MPU Region Attribute and Size Register Value 113 | * 114 | * \param DisableExec Instruction access disable bit, 1= disable instruction fetches. 115 | * \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. 116 | * \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. 117 | * \param IsShareable Region is shareable between multiple bus masters. 118 | * \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. 119 | * \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. 120 | * \param SubRegionDisable Sub-region disable field. 121 | * \param Size Region size of the region to be configured, for example 4K, 8K. 122 | */ 123 | #define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \ 124 | ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size) 125 | 126 | /** 127 | * MPU Memory Access Attribute for strongly ordered memory. 128 | * - TEX: 000b 129 | * - Shareable 130 | * - Non-cacheable 131 | * - Non-bufferable 132 | */ 133 | #define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U) 134 | 135 | /** 136 | * MPU Memory Access Attribute for device memory. 137 | * - TEX: 000b (if shareable) or 010b (if non-shareable) 138 | * - Shareable or non-shareable 139 | * - Non-cacheable 140 | * - Bufferable (if shareable) or non-bufferable (if non-shareable) 141 | * 142 | * \param IsShareable Configures the device memory as shareable or non-shareable. 143 | */ 144 | #define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U)) 145 | 146 | /** 147 | * MPU Memory Access Attribute for normal memory. 148 | * - TEX: 1BBb (reflecting outer cacheability rules) 149 | * - Shareable or non-shareable 150 | * - Cacheable or non-cacheable (reflecting inner cacheability rules) 151 | * - Bufferable or non-bufferable (reflecting inner cacheability rules) 152 | * 153 | * \param OuterCp Configures the outer cache policy. 154 | * \param InnerCp Configures the inner cache policy. 155 | * \param IsShareable Configures the memory as shareable or non-shareable. 156 | */ 157 | #define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U)) 158 | 159 | /** 160 | * MPU Memory Access Attribute non-cacheable policy. 161 | */ 162 | #define ARM_MPU_CACHEP_NOCACHE 0U 163 | 164 | /** 165 | * MPU Memory Access Attribute write-back, write and read allocate policy. 166 | */ 167 | #define ARM_MPU_CACHEP_WB_WRA 1U 168 | 169 | /** 170 | * MPU Memory Access Attribute write-through, no write allocate policy. 171 | */ 172 | #define ARM_MPU_CACHEP_WT_NWA 2U 173 | 174 | /** 175 | * MPU Memory Access Attribute write-back, no write allocate policy. 176 | */ 177 | #define ARM_MPU_CACHEP_WB_NWA 3U 178 | 179 | 180 | /** 181 | * Struct for a single MPU Region 182 | */ 183 | typedef struct { 184 | uint32_t RBAR; //!< The region base address register value (RBAR) 185 | uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR 186 | } ARM_MPU_Region_t; 187 | 188 | /** Enable the MPU. 189 | * \param MPU_Control Default access permissions for unconfigured regions. 190 | */ 191 | __STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) 192 | { 193 | MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; 194 | #ifdef SCB_SHCSR_MEMFAULTENA_Msk 195 | SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; 196 | #endif 197 | __DSB(); 198 | __ISB(); 199 | } 200 | 201 | /** Disable the MPU. 202 | */ 203 | __STATIC_INLINE void ARM_MPU_Disable(void) 204 | { 205 | __DMB(); 206 | #ifdef SCB_SHCSR_MEMFAULTENA_Msk 207 | SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; 208 | #endif 209 | MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; 210 | } 211 | 212 | /** Clear and disable the given MPU region. 213 | * \param rnr Region number to be cleared. 214 | */ 215 | __STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) 216 | { 217 | MPU->RNR = rnr; 218 | MPU->RASR = 0U; 219 | } 220 | 221 | /** Configure an MPU region. 222 | * \param rbar Value for RBAR register. 223 | * \param rsar Value for RSAR register. 224 | */ 225 | __STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr) 226 | { 227 | MPU->RBAR = rbar; 228 | MPU->RASR = rasr; 229 | } 230 | 231 | /** Configure the given MPU region. 232 | * \param rnr Region number to be configured. 233 | * \param rbar Value for RBAR register. 234 | * \param rsar Value for RSAR register. 235 | */ 236 | __STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr) 237 | { 238 | MPU->RNR = rnr; 239 | MPU->RBAR = rbar; 240 | MPU->RASR = rasr; 241 | } 242 | 243 | /** Memcopy with strictly ordered memory access, e.g. for register targets. 244 | * \param dst Destination data is copied to. 245 | * \param src Source data is copied from. 246 | * \param len Amount of data words to be copied. 247 | */ 248 | __STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) 249 | { 250 | uint32_t i; 251 | for (i = 0U; i < len; ++i) 252 | { 253 | dst[i] = src[i]; 254 | } 255 | } 256 | 257 | /** Load the given number of MPU regions from a table. 258 | * \param table Pointer to the MPU configuration table. 259 | * \param cnt Amount of regions to be configured. 260 | */ 261 | __STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) 262 | { 263 | const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; 264 | while (cnt > MPU_TYPE_RALIASES) { 265 | ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize); 266 | table += MPU_TYPE_RALIASES; 267 | cnt -= MPU_TYPE_RALIASES; 268 | } 269 | ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize); 270 | } 271 | 272 | #endif 273 | -------------------------------------------------------------------------------- /Drivers/CMSIS/Include/mpu_armv8.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * @file mpu_armv8.h 3 | * @brief CMSIS MPU API for Armv8-M and Armv8.1-M MPU 4 | * @version V5.1.0 5 | * @date 08. March 2019 6 | ******************************************************************************/ 7 | /* 8 | * Copyright (c) 2017-2019 Arm Limited. All rights reserved. 9 | * 10 | * SPDX-License-Identifier: Apache-2.0 11 | * 12 | * Licensed under the Apache License, Version 2.0 (the License); you may 13 | * not use this file except in compliance with the License. 14 | * You may obtain a copy of the License at 15 | * 16 | * www.apache.org/licenses/LICENSE-2.0 17 | * 18 | * Unless required by applicable law or agreed to in writing, software 19 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 20 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 | * See the License for the specific language governing permissions and 22 | * limitations under the License. 23 | */ 24 | 25 | #if defined ( __ICCARM__ ) 26 | #pragma system_include /* treat file as system include file for MISRA check */ 27 | #elif defined (__clang__) 28 | #pragma clang system_header /* treat file as system include file */ 29 | #endif 30 | 31 | #ifndef ARM_MPU_ARMV8_H 32 | #define ARM_MPU_ARMV8_H 33 | 34 | /** \brief Attribute for device memory (outer only) */ 35 | #define ARM_MPU_ATTR_DEVICE ( 0U ) 36 | 37 | /** \brief Attribute for non-cacheable, normal memory */ 38 | #define ARM_MPU_ATTR_NON_CACHEABLE ( 4U ) 39 | 40 | /** \brief Attribute for normal memory (outer and inner) 41 | * \param NT Non-Transient: Set to 1 for non-transient data. 42 | * \param WB Write-Back: Set to 1 to use write-back update policy. 43 | * \param RA Read Allocation: Set to 1 to use cache allocation on read miss. 44 | * \param WA Write Allocation: Set to 1 to use cache allocation on write miss. 45 | */ 46 | #define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \ 47 | (((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U)) 48 | 49 | /** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */ 50 | #define ARM_MPU_ATTR_DEVICE_nGnRnE (0U) 51 | 52 | /** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */ 53 | #define ARM_MPU_ATTR_DEVICE_nGnRE (1U) 54 | 55 | /** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */ 56 | #define ARM_MPU_ATTR_DEVICE_nGRE (2U) 57 | 58 | /** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */ 59 | #define ARM_MPU_ATTR_DEVICE_GRE (3U) 60 | 61 | /** \brief Memory Attribute 62 | * \param O Outer memory attributes 63 | * \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes 64 | */ 65 | #define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U))) 66 | 67 | /** \brief Normal memory non-shareable */ 68 | #define ARM_MPU_SH_NON (0U) 69 | 70 | /** \brief Normal memory outer shareable */ 71 | #define ARM_MPU_SH_OUTER (2U) 72 | 73 | /** \brief Normal memory inner shareable */ 74 | #define ARM_MPU_SH_INNER (3U) 75 | 76 | /** \brief Memory access permissions 77 | * \param RO Read-Only: Set to 1 for read-only memory. 78 | * \param NP Non-Privileged: Set to 1 for non-privileged memory. 79 | */ 80 | #define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U)) 81 | 82 | /** \brief Region Base Address Register value 83 | * \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned. 84 | * \param SH Defines the Shareability domain for this memory region. 85 | * \param RO Read-Only: Set to 1 for a read-only memory region. 86 | * \param NP Non-Privileged: Set to 1 for a non-privileged memory region. 87 | * \oaram XN eXecute Never: Set to 1 for a non-executable memory region. 88 | */ 89 | #define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \ 90 | ((BASE & MPU_RBAR_BASE_Msk) | \ 91 | ((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \ 92 | ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \ 93 | ((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk)) 94 | 95 | /** \brief Region Limit Address Register value 96 | * \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. 97 | * \param IDX The attribute index to be associated with this memory region. 98 | */ 99 | #define ARM_MPU_RLAR(LIMIT, IDX) \ 100 | ((LIMIT & MPU_RLAR_LIMIT_Msk) | \ 101 | ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ 102 | (MPU_RLAR_EN_Msk)) 103 | 104 | #if defined(MPU_RLAR_PXN_Pos) 105 | 106 | /** \brief Region Limit Address Register with PXN value 107 | * \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. 108 | * \param PXN Privileged execute never. Defines whether code can be executed from this privileged region. 109 | * \param IDX The attribute index to be associated with this memory region. 110 | */ 111 | #define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \ 112 | ((LIMIT & MPU_RLAR_LIMIT_Msk) | \ 113 | ((PXN << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \ 114 | ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ 115 | (MPU_RLAR_EN_Msk)) 116 | 117 | #endif 118 | 119 | /** 120 | * Struct for a single MPU Region 121 | */ 122 | typedef struct { 123 | uint32_t RBAR; /*!< Region Base Address Register value */ 124 | uint32_t RLAR; /*!< Region Limit Address Register value */ 125 | } ARM_MPU_Region_t; 126 | 127 | /** Enable the MPU. 128 | * \param MPU_Control Default access permissions for unconfigured regions. 129 | */ 130 | __STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) 131 | { 132 | MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; 133 | #ifdef SCB_SHCSR_MEMFAULTENA_Msk 134 | SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; 135 | #endif 136 | __DSB(); 137 | __ISB(); 138 | } 139 | 140 | /** Disable the MPU. 141 | */ 142 | __STATIC_INLINE void ARM_MPU_Disable(void) 143 | { 144 | __DMB(); 145 | #ifdef SCB_SHCSR_MEMFAULTENA_Msk 146 | SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; 147 | #endif 148 | MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; 149 | } 150 | 151 | #ifdef MPU_NS 152 | /** Enable the Non-secure MPU. 153 | * \param MPU_Control Default access permissions for unconfigured regions. 154 | */ 155 | __STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control) 156 | { 157 | MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; 158 | #ifdef SCB_SHCSR_MEMFAULTENA_Msk 159 | SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; 160 | #endif 161 | __DSB(); 162 | __ISB(); 163 | } 164 | 165 | /** Disable the Non-secure MPU. 166 | */ 167 | __STATIC_INLINE void ARM_MPU_Disable_NS(void) 168 | { 169 | __DMB(); 170 | #ifdef SCB_SHCSR_MEMFAULTENA_Msk 171 | SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; 172 | #endif 173 | MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk; 174 | } 175 | #endif 176 | 177 | /** Set the memory attribute encoding to the given MPU. 178 | * \param mpu Pointer to the MPU to be configured. 179 | * \param idx The attribute index to be set [0-7] 180 | * \param attr The attribute value to be set. 181 | */ 182 | __STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr) 183 | { 184 | const uint8_t reg = idx / 4U; 185 | const uint32_t pos = ((idx % 4U) * 8U); 186 | const uint32_t mask = 0xFFU << pos; 187 | 188 | if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) { 189 | return; // invalid index 190 | } 191 | 192 | mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask)); 193 | } 194 | 195 | /** Set the memory attribute encoding. 196 | * \param idx The attribute index to be set [0-7] 197 | * \param attr The attribute value to be set. 198 | */ 199 | __STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr) 200 | { 201 | ARM_MPU_SetMemAttrEx(MPU, idx, attr); 202 | } 203 | 204 | #ifdef MPU_NS 205 | /** Set the memory attribute encoding to the Non-secure MPU. 206 | * \param idx The attribute index to be set [0-7] 207 | * \param attr The attribute value to be set. 208 | */ 209 | __STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr) 210 | { 211 | ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr); 212 | } 213 | #endif 214 | 215 | /** Clear and disable the given MPU region of the given MPU. 216 | * \param mpu Pointer to MPU to be used. 217 | * \param rnr Region number to be cleared. 218 | */ 219 | __STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr) 220 | { 221 | mpu->RNR = rnr; 222 | mpu->RLAR = 0U; 223 | } 224 | 225 | /** Clear and disable the given MPU region. 226 | * \param rnr Region number to be cleared. 227 | */ 228 | __STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) 229 | { 230 | ARM_MPU_ClrRegionEx(MPU, rnr); 231 | } 232 | 233 | #ifdef MPU_NS 234 | /** Clear and disable the given Non-secure MPU region. 235 | * \param rnr Region number to be cleared. 236 | */ 237 | __STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr) 238 | { 239 | ARM_MPU_ClrRegionEx(MPU_NS, rnr); 240 | } 241 | #endif 242 | 243 | /** Configure the given MPU region of the given MPU. 244 | * \param mpu Pointer to MPU to be used. 245 | * \param rnr Region number to be configured. 246 | * \param rbar Value for RBAR register. 247 | * \param rlar Value for RLAR register. 248 | */ 249 | __STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar) 250 | { 251 | mpu->RNR = rnr; 252 | mpu->RBAR = rbar; 253 | mpu->RLAR = rlar; 254 | } 255 | 256 | /** Configure the given MPU region. 257 | * \param rnr Region number to be configured. 258 | * \param rbar Value for RBAR register. 259 | * \param rlar Value for RLAR register. 260 | */ 261 | __STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar) 262 | { 263 | ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar); 264 | } 265 | 266 | #ifdef MPU_NS 267 | /** Configure the given Non-secure MPU region. 268 | * \param rnr Region number to be configured. 269 | * \param rbar Value for RBAR register. 270 | * \param rlar Value for RLAR register. 271 | */ 272 | __STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar) 273 | { 274 | ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar); 275 | } 276 | #endif 277 | 278 | /** Memcopy with strictly ordered memory access, e.g. for register targets. 279 | * \param dst Destination data is copied to. 280 | * \param src Source data is copied from. 281 | * \param len Amount of data words to be copied. 282 | */ 283 | __STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) 284 | { 285 | uint32_t i; 286 | for (i = 0U; i < len; ++i) 287 | { 288 | dst[i] = src[i]; 289 | } 290 | } 291 | 292 | /** Load the given number of MPU regions from a table to the given MPU. 293 | * \param mpu Pointer to the MPU registers to be used. 294 | * \param rnr First region number to be configured. 295 | * \param table Pointer to the MPU configuration table. 296 | * \param cnt Amount of regions to be configured. 297 | */ 298 | __STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) 299 | { 300 | const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; 301 | if (cnt == 1U) { 302 | mpu->RNR = rnr; 303 | ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize); 304 | } else { 305 | uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U); 306 | uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES; 307 | 308 | mpu->RNR = rnrBase; 309 | while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) { 310 | uint32_t c = MPU_TYPE_RALIASES - rnrOffset; 311 | ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize); 312 | table += c; 313 | cnt -= c; 314 | rnrOffset = 0U; 315 | rnrBase += MPU_TYPE_RALIASES; 316 | mpu->RNR = rnrBase; 317 | } 318 | 319 | ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize); 320 | } 321 | } 322 | 323 | /** Load the given number of MPU regions from a table. 324 | * \param rnr First region number to be configured. 325 | * \param table Pointer to the MPU configuration table. 326 | * \param cnt Amount of regions to be configured. 327 | */ 328 | __STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) 329 | { 330 | ARM_MPU_LoadEx(MPU, rnr, table, cnt); 331 | } 332 | 333 | #ifdef MPU_NS 334 | /** Load the given number of MPU regions from a table to the Non-secure MPU. 335 | * \param rnr First region number to be configured. 336 | * \param table Pointer to the MPU configuration table. 337 | * \param cnt Amount of regions to be configured. 338 | */ 339 | __STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) 340 | { 341 | ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt); 342 | } 343 | #endif 344 | 345 | #endif 346 | 347 | -------------------------------------------------------------------------------- /Drivers/CMSIS/Include/tz_context.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * @file tz_context.h 3 | * @brief Context Management for Armv8-M TrustZone 4 | * @version V1.0.1 5 | * @date 10. January 2018 6 | ******************************************************************************/ 7 | /* 8 | * Copyright (c) 2017-2018 Arm Limited. All rights reserved. 9 | * 10 | * SPDX-License-Identifier: Apache-2.0 11 | * 12 | * Licensed under the Apache License, Version 2.0 (the License); you may 13 | * not use this file except in compliance with the License. 14 | * You may obtain a copy of the License at 15 | * 16 | * www.apache.org/licenses/LICENSE-2.0 17 | * 18 | * Unless required by applicable law or agreed to in writing, software 19 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 20 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 | * See the License for the specific language governing permissions and 22 | * limitations under the License. 23 | */ 24 | 25 | #if defined ( __ICCARM__ ) 26 | #pragma system_include /* treat file as system include file for MISRA check */ 27 | #elif defined (__clang__) 28 | #pragma clang system_header /* treat file as system include file */ 29 | #endif 30 | 31 | #ifndef TZ_CONTEXT_H 32 | #define TZ_CONTEXT_H 33 | 34 | #include 35 | 36 | #ifndef TZ_MODULEID_T 37 | #define TZ_MODULEID_T 38 | /// \details Data type that identifies secure software modules called by a process. 39 | typedef uint32_t TZ_ModuleId_t; 40 | #endif 41 | 42 | /// \details TZ Memory ID identifies an allocated memory slot. 43 | typedef uint32_t TZ_MemoryId_t; 44 | 45 | /// Initialize secure context memory system 46 | /// \return execution status (1: success, 0: error) 47 | uint32_t TZ_InitContextSystem_S (void); 48 | 49 | /// Allocate context memory for calling secure software modules in TrustZone 50 | /// \param[in] module identifies software modules called from non-secure mode 51 | /// \return value != 0 id TrustZone memory slot identifier 52 | /// \return value 0 no memory available or internal error 53 | TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module); 54 | 55 | /// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S 56 | /// \param[in] id TrustZone memory slot identifier 57 | /// \return execution status (1: success, 0: error) 58 | uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id); 59 | 60 | /// Load secure context (called on RTOS thread context switch) 61 | /// \param[in] id TrustZone memory slot identifier 62 | /// \return execution status (1: success, 0: error) 63 | uint32_t TZ_LoadContext_S (TZ_MemoryId_t id); 64 | 65 | /// Store secure context (called on RTOS thread context switch) 66 | /// \param[in] id TrustZone memory slot identifier 67 | /// \return execution status (1: success, 0: error) 68 | uint32_t TZ_StoreContext_S (TZ_MemoryId_t id); 69 | 70 | #endif // TZ_CONTEXT_H 71 | -------------------------------------------------------------------------------- /Drivers/CMSIS/LICENSE.txt: -------------------------------------------------------------------------------- 1 | Apache License 2 | Version 2.0, January 2004 3 | http://www.apache.org/licenses/ 4 | 5 | TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION 6 | 7 | 1. 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We also recommend that a 185 | file or class name and description of purpose be included on the 186 | same "printed page" as the copyright notice for easier 187 | identification within third-party archives. 188 | 189 | Copyright {yyyy} {name of copyright owner} 190 | 191 | Licensed under the Apache License, Version 2.0 (the "License"); 192 | you may not use this file except in compliance with the License. 193 | You may obtain a copy of the License at 194 | 195 | http://www.apache.org/licenses/LICENSE-2.0 196 | 197 | Unless required by applicable law or agreed to in writing, software 198 | distributed under the License is distributed on an "AS IS" BASIS, 199 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 200 | See the License for the specific language governing permissions and 201 | limitations under the License. 202 | -------------------------------------------------------------------------------- /LICENSE.md: -------------------------------------------------------------------------------- 1 | | Component | License | Copyright | 2 | |:--------- |:------- |:----------| 3 | | CMSIS | Apache License 2.0 | Copyright (c) 2009-2018 ARM Limited. All rights reserved. | 4 | | CMSIS Device | Apache License 2.0 | ARM Limited - STMicroelectronics | 5 | | STM32WL HAL | BSD 3-Clause | STMicroelectronics | 6 | | STM32 Open Bootloader | ST SLA0044 | STMicroelectronics | -------------------------------------------------------------------------------- /Projects/NUCLEO-WL55JC/Applications/OpenBootloader/Core/Inc/main.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file main.h 4 | * @author MCD Application Team 5 | * @brief Header for main.c module 6 | ****************************************************************************** 7 | * @attention 8 | * 9 | * Copyright (c) 2022 STMicroelectronics. 10 | * All rights reserved. 11 | * 12 | * This software is licensed under terms that can be found in the LICENSE file 13 | * in the root directory of this software component. 14 | * If no LICENSE file comes with this software, it is provided AS-IS. 15 | * 16 | ****************************************************************************** 17 | */ 18 | 19 | /* Define to prevent recursive inclusion -------------------------------------*/ 20 | #ifndef MAIN_H 21 | #define MAIN_H 22 | 23 | #ifdef __cplusplus 24 | extern "C" { 25 | #endif 26 | 27 | /* Includes ------------------------------------------------------------------*/ 28 | /* Exported types ------------------------------------------------------------*/ 29 | /* Exported constants --------------------------------------------------------*/ 30 | /* Exported macro ------------------------------------------------------------*/ 31 | /* Exported functions ------------------------------------------------------- */ 32 | void Error_Handler(void); 33 | void System_DeInit(void); 34 | 35 | #ifdef __cplusplus 36 | } 37 | #endif 38 | 39 | #endif /* MAIN_H */ 40 | -------------------------------------------------------------------------------- /Projects/NUCLEO-WL55JC/Applications/OpenBootloader/Core/Inc/stm32wlxx_hal_conf.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32wlxx_hal_conf.h 4 | * @author MCD Application Team 5 | * @brief HAL configuration file. 6 | ****************************************************************************** 7 | * @attention 8 | * 9 | *

© Copyright (c) 2020 STMicroelectronics. 10 | * All rights reserved.

11 | * 12 | * This software component is licensed by ST under BSD 3-Clause license, 13 | * the "License"; You may not use this file except in compliance with the 14 | * License. You may obtain a copy of the License at: 15 | * opensource.org/licenses/BSD-3-Clause 16 | * 17 | ****************************************************************************** 18 | */ 19 | 20 | /* Define to prevent recursive inclusion -------------------------------------*/ 21 | #ifndef STM32WLxx_HAL_CONF_H 22 | #define STM32WLxx_HAL_CONF_H 23 | 24 | #ifdef __cplusplus 25 | extern "C" { 26 | #endif 27 | 28 | /* Exported types ------------------------------------------------------------*/ 29 | /* Exported constants --------------------------------------------------------*/ 30 | 31 | /* ########################## Module Selection ############################## */ 32 | /** 33 | * @brief This is the list of modules to be used in the HAL driver 34 | */ 35 | #define HAL_MODULE_ENABLED 36 | /*#define HAL_ADC_MODULE_ENABLED */ 37 | /*#define HAL_COMP_MODULE_ENABLED */ 38 | /*#define HAL_CRC_MODULE_ENABLED */ 39 | /*#define HAL_CRYP_MODULE_ENABLED */ 40 | /*#define HAL_DAC_MODULE_ENABLED */ 41 | /*#define HAL_GTZC_MODULE_ENABLED */ 42 | /*#define HAL_HSEM_MODULE_ENABLED */ 43 | /*#define HAL_I2C_MODULE_ENABLED */ 44 | /*#define HAL_I2S_MODULE_ENABLED */ 45 | /*#define HAL_IPCC_MODULE_ENABLED */ 46 | /*#define HAL_IRDA_MODULE_ENABLED */ 47 | #define HAL_IWDG_MODULE_ENABLED 48 | /*#define HAL_LPTIM_MODULE_ENABLED */ 49 | /*#define HAL_PKA_MODULE_ENABLED */ 50 | /*#define HAL_RNG_MODULE_ENABLED */ 51 | /*#define HAL_RTC_MODULE_ENABLED */ 52 | /*#define HAL_SMARTCARD_MODULE_ENABLED */ 53 | /*#define HAL_SMBUS_MODULE_ENABLED */ 54 | #define HAL_SPI_MODULE_ENABLED 55 | /*#define HAL_SUBGHZ_MODULE_ENABLED */ 56 | /*#define HAL_TIM_MODULE_ENABLED */ 57 | #define HAL_UART_MODULE_ENABLED 58 | #define HAL_USART_MODULE_ENABLED 59 | /*#define HAL_WWDG_MODULE_ENABLED */ 60 | #define HAL_EXTI_MODULE_ENABLED 61 | #define HAL_CORTEX_MODULE_ENABLED 62 | #define HAL_DMA_MODULE_ENABLED 63 | #define HAL_FLASH_MODULE_ENABLED 64 | #define HAL_GPIO_MODULE_ENABLED 65 | #define HAL_PWR_MODULE_ENABLED 66 | #define HAL_RCC_MODULE_ENABLED 67 | 68 | /* ########################## Register Callbacks selection ############################## */ 69 | /** 70 | * @brief This is the list of modules where register callback can be used 71 | */ 72 | #define USE_HAL_ADC_REGISTER_CALLBACKS 0u 73 | #define USE_HAL_COMP_REGISTER_CALLBACKS 0u 74 | #define USE_HAL_CRYP_REGISTER_CALLBACKS 0u 75 | #define USE_HAL_DAC_REGISTER_CALLBACKS 0u 76 | #define USE_HAL_I2C_REGISTER_CALLBACKS 0u 77 | #define USE_HAL_I2S_REGISTER_CALLBACKS 0u 78 | #define USE_HAL_IRDA_REGISTER_CALLBACKS 0u 79 | #define USE_HAL_LPTIM_REGISTER_CALLBACKS 0u 80 | #define USE_HAL_PKA_REGISTER_CALLBACKS 0u 81 | #define USE_HAL_RNG_REGISTER_CALLBACKS 0u 82 | #define USE_HAL_RTC_REGISTER_CALLBACKS 0u 83 | #define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0u 84 | #define USE_HAL_SMBUS_REGISTER_CALLBACKS 0u 85 | #define USE_HAL_SPI_REGISTER_CALLBACKS 0u 86 | #define USE_HAL_SUBGHZ_REGISTER_CALLBACKS 0u 87 | #define USE_HAL_TIM_REGISTER_CALLBACKS 0u 88 | #define USE_HAL_UART_REGISTER_CALLBACKS 0u 89 | #define USE_HAL_USART_REGISTER_CALLBACKS 0u 90 | #define USE_HAL_WWDG_REGISTER_CALLBACKS 0u 91 | 92 | /* ########################## Oscillator Values adaptation ####################*/ 93 | /** 94 | * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. 95 | * This value is used by the RCC HAL module to compute the system frequency 96 | * (when HSE is used as system clock source, directly or through the PLL). 97 | */ 98 | 99 | #if !defined (HSE_VALUE) 100 | #define HSE_VALUE 32000000UL /*!< Value of the External oscillator in Hz */ 101 | #endif /* HSE_VALUE */ 102 | 103 | #if !defined (HSE_STARTUP_TIMEOUT) 104 | #define HSE_STARTUP_TIMEOUT 100UL /*!< Time out for HSE start up, in ms */ 105 | #endif /* HSE_STARTUP_TIMEOUT */ 106 | 107 | /** 108 | * @brief Internal Multiple Speed oscillator (MSI) default value. 109 | * This value is the default MSI range value after Reset. 110 | */ 111 | #if !defined (MSI_VALUE) 112 | #define MSI_VALUE 4000000UL /*!< Value of the Internal oscillator in Hz*/ 113 | #endif /* MSI_VALUE */ 114 | 115 | /** 116 | * @brief Internal High Speed oscillator (HSI) value. 117 | * This value is used by the RCC HAL module to compute the system frequency 118 | * (when HSI is used as system clock source, directly or through the PLL). 119 | */ 120 | #if !defined (HSI_VALUE) 121 | #define HSI_VALUE 16000000UL /*!< Value of the Internal oscillator in Hz*/ 122 | #endif /* HSI_VALUE */ 123 | 124 | /** 125 | * @brief Internal Low Speed oscillator (LSI) value. 126 | */ 127 | #if !defined (LSI_VALUE) 128 | #define LSI_VALUE 32000UL /*!< LSI Typical Value in Hz*/ 129 | #endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz 130 | The real value may vary depending on the variations 131 | in voltage and temperature. */ 132 | 133 | /** 134 | * @brief External Low Speed oscillator (LSE) value. 135 | * This value is used by the UART, RTC HAL module to compute the system frequency 136 | */ 137 | #if !defined (LSE_VALUE) 138 | #define LSE_VALUE 32768UL /*!< Value of the External oscillator in Hz*/ 139 | #endif /* LSE_VALUE */ 140 | 141 | /** 142 | * @brief Internal Multiple Speed oscillator (HSI48) default value. 143 | * This value is the default HSI48 range value after Reset. 144 | */ 145 | #if !defined (HSI48_VALUE) 146 | #define HSI48_VALUE 48000000UL /*!< Value of the Internal oscillator in Hz*/ 147 | #endif /* HSI48_VALUE */ 148 | 149 | #if !defined (LSE_STARTUP_TIMEOUT) 150 | #define LSE_STARTUP_TIMEOUT 5000UL /*!< Time out for LSE start up, in ms */ 151 | #endif /* LSE_STARTUP_TIMEOUT */ 152 | 153 | /* Tip: To avoid modifying this file each time you need to use different HSE, 154 | === you can define the HSE value in your toolchain compiler preprocessor. */ 155 | 156 | /* ########################### System Configuration ######################### */ 157 | /** 158 | * @brief This is the HAL system configuration section 159 | */ 160 | #define VDD_VALUE 3300U /*!< Value of VDD in mv */ 161 | #define TICK_INT_PRIORITY ((1uL <<__NVIC_PRIO_BITS) - 1uL) /*!< tick interrupt priority (lowest by default) */ 162 | #define USE_RTOS 0U 163 | #define PREFETCH_ENABLE 0U 164 | #define INSTRUCTION_CACHE_ENABLE 1U 165 | #define DATA_CACHE_ENABLE 1U 166 | 167 | /* ########################## Assert Selection ############################## */ 168 | /** 169 | * @brief Uncomment the line below to expanse the "assert_param" macro in the 170 | * HAL drivers code 171 | */ 172 | /* #define USE_FULL_ASSERT 1 */ 173 | 174 | /* ################## SPI peripheral configuration ########################## */ 175 | 176 | /* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver 177 | * Activated: CRC code is present inside driver 178 | * Deactivated: CRC code cleaned from driver 179 | */ 180 | 181 | #define USE_SPI_CRC 1U 182 | 183 | /* ################## CRYP peripheral configuration ########################## */ 184 | 185 | #define USE_HAL_CRYP_SUSPEND_RESUME 1U 186 | 187 | /* Includes ------------------------------------------------------------------*/ 188 | /** 189 | * @brief Include module's header file 190 | */ 191 | #ifdef HAL_DMA_MODULE_ENABLED 192 | #include "stm32wlxx_hal_dma.h" 193 | #endif /* HAL_DMA_MODULE_ENABLED */ 194 | 195 | #ifdef HAL_ADC_MODULE_ENABLED 196 | #include "stm32wlxx_hal_adc.h" 197 | #endif /* HAL_ADC_MODULE_ENABLED */ 198 | 199 | #ifdef HAL_COMP_MODULE_ENABLED 200 | #include "stm32wlxx_hal_comp.h" 201 | #endif /* HAL_COMP_MODULE_ENABLED */ 202 | 203 | #ifdef HAL_CORTEX_MODULE_ENABLED 204 | #include "stm32wlxx_hal_cortex.h" 205 | #endif /* HAL_CORTEX_MODULE_ENABLED */ 206 | 207 | #ifdef HAL_CRC_MODULE_ENABLED 208 | #include "stm32wlxx_hal_crc.h" 209 | #endif /* HAL_CRC_MODULE_ENABLED */ 210 | 211 | #ifdef HAL_CRYP_MODULE_ENABLED 212 | #include "stm32wlxx_hal_cryp.h" 213 | #endif /* HAL_CRYP_MODULE_ENABLED */ 214 | 215 | #ifdef HAL_DAC_MODULE_ENABLED 216 | #include "stm32wlxx_hal_dac.h" 217 | #endif /* HAL_DAC_MODULE_ENABLED */ 218 | 219 | #ifdef HAL_EXTI_MODULE_ENABLED 220 | #include "stm32wlxx_hal_exti.h" 221 | #endif /* HAL_EXTI_MODULE_ENABLED */ 222 | 223 | #ifdef HAL_FLASH_MODULE_ENABLED 224 | #include "stm32wlxx_hal_flash.h" 225 | #endif /* HAL_FLASH_MODULE_ENABLED */ 226 | 227 | #ifdef HAL_GPIO_MODULE_ENABLED 228 | #include "stm32wlxx_hal_gpio.h" 229 | #endif /* HAL_GPIO_MODULE_ENABLED */ 230 | 231 | #ifdef HAL_GTZC_MODULE_ENABLED 232 | #include "stm32wlxx_hal_gtzc.h" 233 | #endif /* HAL_GTZC_MODULE_ENABLED */ 234 | 235 | #ifdef HAL_HSEM_MODULE_ENABLED 236 | #include "stm32wlxx_hal_hsem.h" 237 | #endif /* HAL_HSEM_MODULE_ENABLED */ 238 | 239 | #ifdef HAL_I2C_MODULE_ENABLED 240 | #include "stm32wlxx_hal_i2c.h" 241 | #endif /* HAL_I2C_MODULE_ENABLED */ 242 | 243 | #ifdef HAL_I2S_MODULE_ENABLED 244 | #include "stm32wlxx_hal_i2s.h" 245 | #endif /* HAL_I2S_MODULE_ENABLED */ 246 | 247 | #ifdef HAL_IPCC_MODULE_ENABLED 248 | #include "stm32wlxx_hal_ipcc.h" 249 | #endif /* HAL_IPCC_MODULE_ENABLED */ 250 | 251 | #ifdef HAL_IRDA_MODULE_ENABLED 252 | #include "stm32wlxx_hal_irda.h" 253 | #endif /* HAL_IRDA_MODULE_ENABLED */ 254 | 255 | #ifdef HAL_IWDG_MODULE_ENABLED 256 | #include "stm32wlxx_hal_iwdg.h" 257 | #endif /* HAL_IWDG_MODULE_ENABLED */ 258 | 259 | #ifdef HAL_LPTIM_MODULE_ENABLED 260 | #include "stm32wlxx_hal_lptim.h" 261 | #endif /* HAL_LPTIM_MODULE_ENABLED */ 262 | 263 | #ifdef HAL_PKA_MODULE_ENABLED 264 | #include "stm32wlxx_hal_pka.h" 265 | #endif /* HAL_PKA_MODULE_ENABLED */ 266 | 267 | #ifdef HAL_PWR_MODULE_ENABLED 268 | #include "stm32wlxx_hal_pwr.h" 269 | #endif /* HAL_PWR_MODULE_ENABLED */ 270 | 271 | #ifdef HAL_RCC_MODULE_ENABLED 272 | #include "stm32wlxx_hal_rcc.h" 273 | #endif /* HAL_RCC_MODULE_ENABLED */ 274 | 275 | #ifdef HAL_RNG_MODULE_ENABLED 276 | #include "stm32wlxx_hal_rng.h" 277 | #endif /* HAL_RNG_MODULE_ENABLED */ 278 | 279 | #ifdef HAL_RTC_MODULE_ENABLED 280 | #include "stm32wlxx_hal_rtc.h" 281 | #endif /* HAL_RTC_MODULE_ENABLED */ 282 | 283 | #ifdef HAL_SMARTCARD_MODULE_ENABLED 284 | #include "stm32wlxx_hal_smartcard.h" 285 | #endif /* HAL_SMARTCARD_MODULE_ENABLED */ 286 | 287 | #ifdef HAL_SMBUS_MODULE_ENABLED 288 | #include "stm32wlxx_hal_smbus.h" 289 | #endif /* HAL_SMBUS_MODULE_ENABLED */ 290 | 291 | #ifdef HAL_SPI_MODULE_ENABLED 292 | #include "stm32wlxx_hal_spi.h" 293 | #endif /* HAL_SPI_MODULE_ENABLED */ 294 | 295 | #ifdef HAL_SUBGHZ_MODULE_ENABLED 296 | #include "stm32wlxx_hal_subghz.h" 297 | #endif /* HAL_SUBGHZ_MODULE_ENABLED */ 298 | 299 | #ifdef HAL_TIM_MODULE_ENABLED 300 | #include "stm32wlxx_hal_tim.h" 301 | #endif /* HAL_TIM_MODULE_ENABLED */ 302 | 303 | #ifdef HAL_UART_MODULE_ENABLED 304 | #include "stm32wlxx_hal_uart.h" 305 | #endif /* HAL_UART_MODULE_ENABLED */ 306 | 307 | #ifdef HAL_USART_MODULE_ENABLED 308 | #include "stm32wlxx_hal_usart.h" 309 | #endif /* HAL_USART_MODULE_ENABLED */ 310 | 311 | #ifdef HAL_WWDG_MODULE_ENABLED 312 | #include "stm32wlxx_hal_wwdg.h" 313 | #endif /* HAL_WWDG_MODULE_ENABLED */ 314 | 315 | /* Exported macro ------------------------------------------------------------*/ 316 | #ifdef USE_FULL_ASSERT 317 | /** 318 | * @brief The assert_param macro is used for function's parameters check. 319 | * @param expr If expr is false, it calls assert_failed function 320 | * which reports the name of the source file and the source 321 | * line number of the call that failed. 322 | * If expr is true, it returns no value. 323 | * @retval None 324 | */ 325 | #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) 326 | /* Exported functions ------------------------------------------------------- */ 327 | void assert_failed(uint8_t *file, uint32_t line); 328 | #else 329 | #define assert_param(expr) ((void)0U) 330 | #endif /* USE_FULL_ASSERT */ 331 | 332 | #ifdef __cplusplus 333 | } 334 | #endif 335 | 336 | #endif /* STM32WLxx_HAL_CONF_H */ 337 | 338 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 339 | -------------------------------------------------------------------------------- /Projects/NUCLEO-WL55JC/Applications/OpenBootloader/Core/Inc/stm32wlxx_it.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32wlxx_it.h 4 | * @author MCD Application Team 5 | * @brief This file contains the headers of the interrupt handlers. 6 | ****************************************************************************** 7 | * @attention 8 | * 9 | * Copyright (c) 2022 STMicroelectronics. 10 | * All rights reserved. 11 | * 12 | * This software is licensed under terms that can be found in the LICENSE file 13 | * in the root directory of this software component. 14 | * If no LICENSE file comes with this software, it is provided AS-IS. 15 | * 16 | ****************************************************************************** 17 | */ 18 | 19 | /* Define to prevent recursive inclusion -------------------------------------*/ 20 | #ifndef __STM32WLxx_IT_H 21 | #define __STM32WLxx_IT_H 22 | 23 | #ifdef __cplusplus 24 | extern "C" { 25 | #endif 26 | 27 | /* Private includes ----------------------------------------------------------*/ 28 | /* Exported types ------------------------------------------------------------*/ 29 | /* Exported constants --------------------------------------------------------*/ 30 | /* Exported macro ------------------------------------------------------------*/ 31 | /* Exported functions prototypes ---------------------------------------------*/ 32 | void NMI_Handler(void); 33 | void HardFault_Handler(void); 34 | void MemManage_Handler(void); 35 | void BusFault_Handler(void); 36 | void UsageFault_Handler(void); 37 | void SVC_Handler(void); 38 | void DebugMon_Handler(void); 39 | void PendSV_Handler(void); 40 | void SysTick_Handler(void); 41 | 42 | void SPI1_IRQHandler(void); 43 | 44 | #ifdef __cplusplus 45 | } 46 | #endif 47 | 48 | #endif /* __STM32WLxx_IT_H */ 49 | -------------------------------------------------------------------------------- /Projects/NUCLEO-WL55JC/Applications/OpenBootloader/Core/Src/main.c: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file main.c 4 | * @author MCD Application Team 5 | * @brief Main program body 6 | ****************************************************************************** 7 | * @attention 8 | * 9 | * Copyright (c) 2022 STMicroelectronics. 10 | * All rights reserved. 11 | * 12 | * This software is licensed under terms that can be found in the LICENSE file 13 | * in the root directory of this software component. 14 | * If no LICENSE file comes with this software, it is provided AS-IS. 15 | * 16 | ****************************************************************************** 17 | */ 18 | 19 | /* Includes ------------------------------------------------------------------*/ 20 | #include "platform.h" 21 | #include "interfaces_conf.h" 22 | #include "main.h" 23 | #include "app_openbootloader.h" 24 | 25 | /* Private typedef -----------------------------------------------------------*/ 26 | /* Private define ------------------------------------------------------------*/ 27 | /* Private macro -------------------------------------------------------------*/ 28 | /* Private variables ---------------------------------------------------------*/ 29 | /* Private function prototypes -----------------------------------------------*/ 30 | static void SystemClock_Config(void); 31 | 32 | /* Private functions ---------------------------------------------------------*/ 33 | 34 | /** 35 | * @brief Main program 36 | * @param None 37 | * @retval None 38 | */ 39 | int main(void) 40 | { 41 | /* STM32WLxx HAL library initialization: 42 | - Configure the Flash pre-fetch, Flash preread and Buffer caches 43 | - Systick timer is configured by default as source of time base, but user 44 | can eventually implement his proper time base source (a general purpose 45 | timer for example or other time source), keeping in mind that Time base 46 | duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and 47 | handled in milliseconds basis. 48 | - Low Level Initialization 49 | */ 50 | HAL_Init(); 51 | 52 | /* Configure the System clock */ 53 | SystemClock_Config(); 54 | 55 | OpenBootloader_Init(); 56 | 57 | /* Infinite loop */ 58 | while (1) 59 | { 60 | OpenBootloader_ProtocolDetection(); 61 | } 62 | } 63 | 64 | /** 65 | * @brief System Clock Configuration 66 | * The system Clock is configured as follow : 67 | * System Clock source = PLL (HSI) 68 | * SYSCLK(Hz) = 48000000 69 | * HCLK(Hz) = 48000000 70 | * HCLK1 Prescaler = 1 71 | * HCKL2 Prescaler = 1 72 | * HCKL3 Prescaler = 1 73 | * APB1 Prescaler = 1 74 | * APB2 Prescaler = 1 75 | * HSI Frequency(Hz) = 16000000 76 | * PLL_M = 1 77 | * PLL_N = 6 78 | * PLL_P = 2 79 | * PLL_Q = 2 80 | * PLL_R = 2 81 | * Flash Latency(WS) = 2 82 | * @param None 83 | * @retval None 84 | */ 85 | void SystemClock_Config(void) 86 | { 87 | RCC_OscInitTypeDef RCC_OscInitStruct = {0}; 88 | RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 89 | 90 | /* Configure the main internal regulator output voltage */ 91 | __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); 92 | 93 | /* Initializes the CPU, AHB and APB busses clocks */ 94 | RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; 95 | RCC_OscInitStruct.HSIState = RCC_HSI_ON; 96 | RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; 97 | RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; 98 | RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; 99 | RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV1; 100 | RCC_OscInitStruct.PLL.PLLN = 6; 101 | RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; 102 | RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2; 103 | RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2; 104 | 105 | if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 106 | { 107 | Error_Handler(); 108 | } 109 | 110 | /* Configure the SYSCLKSource, HCLK, PCLK1 and PCLK2 clocks dividers */ 111 | RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK3 | RCC_CLOCKTYPE_HCLK2 112 | | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK 113 | | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2; 114 | RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; 115 | RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; 116 | RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; 117 | RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; 118 | RCC_ClkInitStruct.AHBCLK2Divider = RCC_SYSCLK_DIV1; 119 | RCC_ClkInitStruct.AHBCLK3Divider = RCC_SYSCLK_DIV1; 120 | 121 | if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) 122 | { 123 | Error_Handler(); 124 | } 125 | } 126 | 127 | /** 128 | * @brief This function is used to de-initialized the clock. 129 | * @retval None 130 | */ 131 | void System_DeInit(void) 132 | { 133 | USARTx_DeInit(); 134 | SPIx_DeInit(); 135 | HAL_RCC_DeInit(); 136 | HAL_NVIC_DisableIRQ(SPIx_IRQn); 137 | } 138 | 139 | /** 140 | * @brief This function is executed in case of error occurrence. 141 | * @retval None 142 | */ 143 | void Error_Handler(void) 144 | { 145 | while (1) 146 | { 147 | } 148 | } 149 | 150 | #ifdef USE_FULL_ASSERT 151 | 152 | /** 153 | * @brief Reports the name of the source file and the source line number 154 | * where the assert_param error has occurred. 155 | * @param file: pointer to the source file name 156 | * @param line: assert_param error line source number 157 | * @retval None 158 | */ 159 | void assert_failed(uint8_t *file, uint32_t line) 160 | { 161 | while (1) 162 | { 163 | } 164 | } 165 | #endif 166 | -------------------------------------------------------------------------------- /Projects/NUCLEO-WL55JC/Applications/OpenBootloader/Core/Src/stm32wlxx_hal_msp.c: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32wlxx_hal_msp.c 4 | * @author MCD Application Team 5 | * @brief HAL MSP module. 6 | * This file provides code for the MSP Initialization 7 | * and de-Initialization codes. 8 | ****************************************************************************** 9 | * @attention 10 | * 11 | * Copyright (c) 2022 STMicroelectronics. 12 | * All rights reserved. 13 | * 14 | * This software is licensed under terms that can be found in the LICENSE file 15 | * in the root directory of this software component. 16 | * If no LICENSE file comes with this software, it is provided AS-IS. 17 | * 18 | ****************************************************************************** 19 | */ 20 | 21 | /* Includes ------------------------------------------------------------------*/ 22 | #include "main.h" 23 | #include "interfaces_conf.h" 24 | #include "stm32wlxx_ll_gpio.h" 25 | 26 | /* Private typedef -----------------------------------------------------------*/ 27 | /* Private define ------------------------------------------------------------*/ 28 | /* Private macro -------------------------------------------------------------*/ 29 | /* Private variables ---------------------------------------------------------*/ 30 | /* Private function prototypes -----------------------------------------------*/ 31 | /* External functions --------------------------------------------------------*/ 32 | 33 | /** 34 | * @brief Initializes the Global MSP. 35 | * @param None 36 | * @retval None 37 | */ 38 | void HAL_MspInit(void) 39 | { 40 | } 41 | 42 | /** 43 | * @brief De-Initializes the Global MSP. 44 | * @param None 45 | * @retval None 46 | */ 47 | void HAL_MspDeInit(void) 48 | { 49 | } 50 | 51 | 52 | -------------------------------------------------------------------------------- /Projects/NUCLEO-WL55JC/Applications/OpenBootloader/Core/Src/stm32wlxx_it.c: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32wlxx_it.c 4 | * @author MCD Application Team 5 | * @brief Main Interrupt Service Routines. 6 | * This file provides template for all exceptions handler and 7 | * peripherals interrupt service routine. 8 | ****************************************************************************** 9 | * @attention 10 | * 11 | * Copyright (c) 2022 STMicroelectronics. 12 | * All rights reserved. 13 | * 14 | * This software is licensed under terms that can be found in the LICENSE file 15 | * in the root directory of this software component. 16 | * If no LICENSE file comes with this software, it is provided AS-IS. 17 | * 18 | ****************************************************************************** 19 | */ 20 | 21 | /* Includes ------------------------------------------------------------------*/ 22 | #include "main.h" 23 | #include "stm32wlxx_it.h" 24 | #include "spi_interface.h" 25 | 26 | /* Private includes ----------------------------------------------------------*/ 27 | /* Private typedef -----------------------------------------------------------*/ 28 | /* Private define ------------------------------------------------------------*/ 29 | /* Private macro -------------------------------------------------------------*/ 30 | /* Private variables ---------------------------------------------------------*/ 31 | /* Private function prototypes -----------------------------------------------*/ 32 | /* Private user code ---------------------------------------------------------*/ 33 | /* External variables --------------------------------------------------------*/ 34 | 35 | /******************************************************************************/ 36 | /* Cortex-M4 Processor Interruption and Exception Handlers */ 37 | /******************************************************************************/ 38 | 39 | /** 40 | * @brief This function handles Non maskable interrupt. 41 | */ 42 | void NMI_Handler(void) 43 | { 44 | while (1) 45 | { 46 | } 47 | } 48 | 49 | /** 50 | * @brief This function handles Hard fault interrupt. 51 | */ 52 | void HardFault_Handler(void) 53 | { 54 | while (1) 55 | { 56 | } 57 | } 58 | 59 | /** 60 | * @brief This function handles Memory management fault. 61 | */ 62 | void MemManage_Handler(void) 63 | { 64 | while (1) 65 | { 66 | } 67 | } 68 | 69 | /** 70 | * @brief This function handles Prefetch fault, memory access fault. 71 | */ 72 | void BusFault_Handler(void) 73 | { 74 | while (1) 75 | { 76 | } 77 | } 78 | 79 | /** 80 | * @brief This function handles Undefined instruction or illegal state. 81 | */ 82 | void UsageFault_Handler(void) 83 | { 84 | while (1) 85 | { 86 | } 87 | } 88 | 89 | /** 90 | * @brief This function handles System service call via SWI instruction. 91 | */ 92 | void SVC_Handler(void) 93 | { 94 | } 95 | 96 | /** 97 | * @brief This function handles Debug monitor. 98 | */ 99 | void DebugMon_Handler(void) 100 | { 101 | } 102 | 103 | /** 104 | * @brief This function handles Pendable request for system service. 105 | */ 106 | void PendSV_Handler(void) 107 | { 108 | } 109 | 110 | /** 111 | * @brief This function handles System tick timer. 112 | */ 113 | void SysTick_Handler(void) 114 | { 115 | HAL_IncTick(); 116 | } 117 | 118 | /******************************************************************************/ 119 | /* STM32WLxx Peripheral Interrupt Handlers */ 120 | /* Add here the Interrupt Handlers for the used peripherals. */ 121 | /* For the available peripheral interrupt handler names, */ 122 | /* please refer to the startup file (startup_stm32wlxx.s). */ 123 | /******************************************************************************/ 124 | 125 | /** 126 | * @brief This function handles SPIx global interrupt. 127 | */ 128 | void SPI1_IRQHandler(void) 129 | { 130 | OPENBL_SPI_IRQHandler(); 131 | } 132 | 133 | -------------------------------------------------------------------------------- /Projects/NUCLEO-WL55JC/Applications/OpenBootloader/Core/Src/system_stm32wlxx.c: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file system_stm32wlxx.c 4 | * @author MCD Application Team 5 | * @brief CMSIS Cortex Device Peripheral Access Layer System Source File 6 | * 7 | ****************************************************************************** 8 | * @attention 9 | * 10 | * Copyright (c) 2020(-2021) STMicroelectronics. 11 | * All rights reserved. 12 | * 13 | * This software is licensed under terms that can be found in the LICENSE file 14 | * in the root directory of this software component. 15 | * If no LICENSE file comes with this software, it is provided AS-IS. 16 | * 17 | ****************************************************************************** 18 | * This file provides two functions and one global variable to be called from 19 | * user application: 20 | * - SystemInit(): This function is called at startup just after reset and 21 | * before branch to main program. This call is made inside 22 | * the "startup_stm32wlxx.s" file. 23 | * 24 | * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used 25 | * by the user application to setup the SysTick 26 | * timer or configure other parameters. 27 | * 28 | * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must 29 | * be called whenever the core clock is changed 30 | * during program execution. 31 | * 32 | * After each device reset the MSI (4 MHz) is used as system clock source. 33 | * Then SystemInit() function is called, in "startup_stm32wlxx.s" file, to 34 | * configure the system clock before to branch to main program. 35 | * 36 | * This file configures the system clock as follows: 37 | *============================================================================= 38 | *----------------------------------------------------------------------------- 39 | * System Clock source | MSI 40 | *----------------------------------------------------------------------------- 41 | * SYSCLK(Hz) | 4000000 42 | *----------------------------------------------------------------------------- 43 | * HCLK(Hz) | 4000000 44 | *----------------------------------------------------------------------------- 45 | * AHB Prescaler | 1 46 | *----------------------------------------------------------------------------- 47 | * APB1 Prescaler | 1 48 | *----------------------------------------------------------------------------- 49 | * APB2 Prescaler | 1 50 | *----------------------------------------------------------------------------- 51 | * PLL_M | 1 52 | *----------------------------------------------------------------------------- 53 | * PLL_N | 8 54 | *----------------------------------------------------------------------------- 55 | * PLL_P | 7 56 | *----------------------------------------------------------------------------- 57 | * PLL_Q | 2 58 | *----------------------------------------------------------------------------- 59 | * PLL_R | 2 60 | *----------------------------------------------------------------------------- 61 | * PLLSAI1_P | NA 62 | *----------------------------------------------------------------------------- 63 | * PLLSAI1_Q | NA 64 | *----------------------------------------------------------------------------- 65 | * PLLSAI1_R | NA 66 | *----------------------------------------------------------------------------- 67 | * Require 48MHz for USB OTG FS, | Disabled 68 | * SDIO and RNG clock | 69 | *----------------------------------------------------------------------------- 70 | *============================================================================= 71 | */ 72 | 73 | /** @addtogroup CMSIS 74 | * @{ 75 | */ 76 | 77 | /** @addtogroup stm32WLxx_system 78 | * @{ 79 | */ 80 | 81 | /** @addtogroup stm32WLxx_System_Private_Includes 82 | * @{ 83 | */ 84 | 85 | #include "stm32wlxx.h" 86 | 87 | #if !defined (HSE_VALUE) 88 | #define HSE_VALUE (32000000UL) /*!< Value of the External oscillator in Hz */ 89 | #endif /* HSE_VALUE */ 90 | 91 | #if !defined (MSI_VALUE) 92 | #define MSI_VALUE (4000000UL) /*!< Value of the Internal oscillator in Hz*/ 93 | #endif /* MSI_VALUE */ 94 | 95 | #if !defined (HSI_VALUE) 96 | #define HSI_VALUE (16000000UL) /*!< Value of the Internal oscillator in Hz*/ 97 | #endif /* HSI_VALUE */ 98 | 99 | #if !defined (LSI_VALUE) 100 | #define LSI_VALUE (32000UL) /*!< Value of LSI in Hz*/ 101 | #endif /* LSI_VALUE */ 102 | 103 | #if !defined (LSE_VALUE) 104 | #define LSE_VALUE (32768UL) /*!< Value of LSE in Hz*/ 105 | #endif /* LSE_VALUE */ 106 | 107 | /** 108 | * @} 109 | */ 110 | 111 | /** @addtogroup STM32WLxx_System_Private_TypesDefinitions 112 | * @{ 113 | */ 114 | 115 | /** 116 | * @} 117 | */ 118 | 119 | /** @addtogroup STM32WLxx_System_Private_Defines 120 | * @{ 121 | */ 122 | 123 | /* Note: Following vector table addresses must be defined in line with linker 124 | configuration. */ 125 | /*!< Uncomment the following line if you need to relocate CPU1 CM4 and/or CPU2 126 | CM0+ vector table anywhere in Sram or Flash. Else vector table will be kept 127 | at address 0x00 which correspond to automatic remap of boot address selected */ 128 | /* #define USER_VECT_TAB_ADDRESS */ 129 | #if defined(USER_VECT_TAB_ADDRESS) 130 | #ifdef CORE_CM0PLUS 131 | /*!< Uncomment this line for user vector table remap in Sram else user remap 132 | will be done in Flash. */ 133 | /* #define VECT_TAB_SRAM */ 134 | #if defined(VECT_TAB_SRAM) 135 | #define VECT_TAB_BASE_ADDRESS SRAM2_BASE /*!< Vector Table base address field. 136 | This value must be a multiple of 0x100. */ 137 | #define VECT_TAB_OFFSET 0x00008000U /*!< Vector Table base offset field. 138 | This value must be a multiple of 0x100. */ 139 | #else 140 | #define VECT_TAB_BASE_ADDRESS FLASH_BASE /*!< Vector Table base address field. 141 | This value must be a multiple of 0x100. */ 142 | #define VECT_TAB_OFFSET 0x00020000U /*!< Vector Table base offset field. 143 | This value must be a multiple of 0x100. */ 144 | #endif 145 | #else /* CORE_CM4 */ 146 | /*!< Uncomment this line for user vector table remap in Sram else user remap 147 | will be done in Flash. */ 148 | /* #define VECT_TAB_SRAM */ 149 | #if defined(VECT_TAB_SRAM) 150 | #define VECT_TAB_BASE_ADDRESS SRAM1_BASE /*!< Vector Table base address field. 151 | This value must be a multiple of 0x200. */ 152 | #define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. 153 | This value must be a multiple of 0x200. */ 154 | #else 155 | #define VECT_TAB_BASE_ADDRESS FLASH_BASE /*!< Vector Table base address field. 156 | This value must be a multiple of 0x200. */ 157 | #define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. 158 | This value must be a multiple of 0x200. */ 159 | #endif 160 | #endif 161 | #endif 162 | 163 | /** 164 | * @} 165 | */ 166 | 167 | /** @addtogroup STM32WLxx_System_Private_Macros 168 | * @{ 169 | */ 170 | 171 | /** 172 | * @} 173 | */ 174 | 175 | /** @addtogroup STM32WLxx_System_Private_Variables 176 | * @{ 177 | */ 178 | /* The SystemCoreClock variable is updated in three ways: 179 | 1) from within HAL_Init() 180 | 2) by calling CMSIS function SystemCoreClockUpdate() 181 | 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency 182 | */ 183 | uint32_t SystemCoreClock = 4000000UL; /*CPU1: M4 on MSI clock after startup (4MHz)*/ 184 | 185 | const uint32_t AHBPrescTable[16UL] = {1UL, 3UL, 5UL, 1UL, 1UL, 6UL, 10UL, 32UL, 2UL, 4UL, 8UL, 16UL, 64UL, 128UL, 256UL, 512UL}; 186 | 187 | const uint32_t APBPrescTable[8UL] = {0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL}; 188 | 189 | const uint32_t MSIRangeTable[16UL] = {100000UL, 200000UL, 400000UL, 800000UL, 1000000UL, 2000000UL, \ 190 | 4000000UL, 8000000UL, 16000000UL, 24000000UL, 32000000UL, 48000000UL, 0UL, 0UL, 0UL, 0UL}; /* 0UL values are incorrect cases */ 191 | /** 192 | * @} 193 | */ 194 | 195 | /** @addtogroup STM32WLxx_System_Private_FunctionPrototypes 196 | * @{ 197 | */ 198 | /** 199 | * @} 200 | */ 201 | 202 | /** @addtogroup STM32WLxx_System_Private_Functions 203 | * @{ 204 | */ 205 | 206 | /** 207 | * @brief Setup the microcontroller system. 208 | * @param None 209 | * @retval None 210 | */ 211 | void SystemInit(void) 212 | { 213 | #if defined(USER_VECT_TAB_ADDRESS) 214 | /* Configure the Vector Table location add offset address ------------------*/ 215 | SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; 216 | #endif 217 | 218 | /* FPU settings ------------------------------------------------------------*/ 219 | #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) 220 | SCB->CPACR |= ((3UL << (10UL*2UL))|(3UL << (11UL*2UL))); /* set CP10 and CP11 Full Access */ 221 | #endif 222 | } 223 | 224 | /** 225 | * @brief Update SystemCoreClock variable according to Clock Register Values. 226 | * The SystemCoreClock variable contains the core clock (HCLK), it can 227 | * be used by the user application to setup the SysTick timer or configure 228 | * other parameters. 229 | * 230 | * @note Each time the core clock (HCLK) changes, this function must be called 231 | * to update SystemCoreClock variable value. Otherwise, any configuration 232 | * based on this variable will be incorrect. 233 | * 234 | * @note - The system frequency computed by this function is not the real 235 | * frequency in the chip. It is calculated based on the predefined 236 | * constant and the selected clock source: 237 | * 238 | * - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*) 239 | * 240 | * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**) 241 | * 242 | * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***) 243 | * 244 | * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***) 245 | * or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors. 246 | * 247 | * (*) MSI_VALUE is a constant defined in stm32wlxx_hal.h file (default value 248 | * 4 MHz) but the real value may vary depending on the variations 249 | * in voltage and temperature. 250 | * 251 | * (**) HSI_VALUE is a constant defined in stm32wlxx_hal_conf.h file (default value 252 | * 16 MHz) but the real value may vary depending on the variations 253 | * in voltage and temperature. 254 | * 255 | * (***) HSE_VALUE is a constant defined in stm32wlxx_hal_conf.h file (default value 256 | * 32 MHz), user has to ensure that HSE_VALUE is same as the real 257 | * frequency of the crystal used. Otherwise, this function may 258 | * have wrong result. 259 | * 260 | * - The result of this function could be not correct when using fractional 261 | * value for HSE crystal. 262 | * 263 | * @param None 264 | * @retval None 265 | */ 266 | void SystemCoreClockUpdate(void) 267 | { 268 | uint32_t tmp, msirange, pllvco, pllr, pllsource , pllm; 269 | 270 | /* Get MSI Range frequency--------------------------------------------------*/ 271 | 272 | /* Get MSI Range frequency--------------------------------------------------*/ 273 | if((RCC->CR & RCC_CR_MSIRGSEL) == 0U) 274 | { /* MSISRANGE from RCC_CSR applies */ 275 | msirange = (RCC->CSR & RCC_CSR_MSISRANGE) >> 8U; 276 | } 277 | else 278 | { /* MSIRANGE from RCC_CR applies */ 279 | msirange = (RCC->CR & RCC_CR_MSIRANGE) >> 4U; 280 | } 281 | /*MSI frequency range in HZ*/ 282 | msirange = MSIRangeTable[msirange]; 283 | 284 | 285 | /*SystemCoreClock=HAL_RCC_GetSysClockFreq();*/ 286 | /* Get SYSCLK source -------------------------------------------------------*/ 287 | switch (RCC->CFGR & RCC_CFGR_SWS) 288 | { 289 | case 0x00: /* MSI used as system clock source */ 290 | SystemCoreClock = msirange; 291 | break; 292 | 293 | case 0x04: /* HSI used as system clock source */ 294 | /* HSI used as system clock source */ 295 | SystemCoreClock = HSI_VALUE; 296 | break; 297 | 298 | case 0x08: /* HSE used as system clock source */ 299 | SystemCoreClock = HSE_VALUE; 300 | break; 301 | 302 | case 0x0C: /* PLL used as system clock source */ 303 | /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN 304 | SYSCLK = PLL_VCO / PLLR 305 | */ 306 | pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC); 307 | pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1UL ; 308 | 309 | switch (pllsource) 310 | { 311 | case 0x02: /* HSI used as PLL clock source */ 312 | pllvco = (HSI_VALUE / pllm); 313 | break; 314 | 315 | case 0x03: /* HSE used as PLL clock source */ 316 | pllvco = (HSE_VALUE / pllm); 317 | break; 318 | 319 | default: /* MSI used as PLL clock source */ 320 | pllvco = (msirange / pllm); 321 | break; 322 | } 323 | 324 | pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); 325 | pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1UL); 326 | 327 | SystemCoreClock = pllvco/pllr; 328 | break; 329 | 330 | default: 331 | SystemCoreClock = msirange; 332 | break; 333 | } 334 | 335 | /* Compute HCLK clock frequency --------------------------------------------*/ 336 | #if defined(DUAL_CORE) && defined(CORE_CM0PLUS) 337 | /* Get HCLK2 prescaler */ 338 | tmp = AHBPrescTable[((RCC->EXTCFGR & RCC_EXTCFGR_C2HPRE) >> RCC_EXTCFGR_C2HPRE_Pos)]; 339 | #else 340 | /* Get HCLK1 prescaler */ 341 | tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)]; 342 | #endif 343 | 344 | /* Core clock frequency */ 345 | SystemCoreClock = SystemCoreClock / tmp; 346 | } 347 | /** 348 | * @} 349 | */ 350 | 351 | /** 352 | * @} 353 | */ 354 | 355 | /** 356 | * @} 357 | */ 358 | 359 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 360 | -------------------------------------------------------------------------------- /Projects/NUCLEO-WL55JC/Applications/OpenBootloader/EWARM/OpenBootloader.eww: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | $WS_DIR$\OpenBootloader.ewp 5 | 6 | 7 | 8 | -------------------------------------------------------------------------------- /Projects/NUCLEO-WL55JC/Applications/OpenBootloader/EWARM/stm32wl55xx_flash_cm4.icf: -------------------------------------------------------------------------------- 1 | /*###ICF### Section handled by ICF editor, don't touch! ****/ 2 | /*-Editor annotation file-*/ 3 | /* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ 4 | /*-Specials-*/ 5 | define symbol __ICFEDIT_intvec_start__ = 0x08000000; 6 | 7 | /*-Memory Regions-*/ 8 | /***** FLASH part dedicated to M4 *****/ 9 | define symbol __ICFEDIT_region_ROM_start__ = 0x08000000; 10 | define symbol __ICFEDIT_region_ROM_end__ = 0x080037FF; 11 | /***** Non-backup SRAM1 dedicated to M4 *****/ 12 | define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; 13 | define symbol __ICFEDIT_region_RAM_end__ = 0x200017FF; 14 | /***** Backup SRAM2 dedicated to M4 *****/ 15 | define symbol __ICFEDIT_region_RAM2_start__ = 0x20008000; 16 | define symbol __ICFEDIT_region_RAM2_end__ = 0x2000BFFF; 17 | 18 | /*-Sizes-*/ 19 | define symbol __ICFEDIT_size_cstack__ = 0x400; 20 | define symbol __ICFEDIT_size_heap__ = 0x200; 21 | /**** End of ICF editor section. ###ICF###*/ 22 | 23 | 24 | define memory mem with size = 4G; 25 | define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; 26 | define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; 27 | define region RAM2_region = mem:[from __ICFEDIT_region_RAM2_start__ to __ICFEDIT_region_RAM2_end__]; 28 | 29 | define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; 30 | define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; 31 | 32 | initialize by copy { readwrite }; 33 | do not initialize { section .noinit }; 34 | 35 | place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; 36 | 37 | place in ROM_region { readonly }; 38 | place in RAM_region { readwrite, 39 | block CSTACK, block HEAP }; 40 | place in RAM2_region { }; -------------------------------------------------------------------------------- /Projects/NUCLEO-WL55JC/Applications/OpenBootloader/MDK-ARM/stm32wl55xx_flash_cm4.sct: -------------------------------------------------------------------------------- 1 | ; ************************************************************* 2 | ; *** Scatter-Loading Description File generated by uVision *** 3 | ; ************************************************************* 4 | 5 | LR_IROM1 0x08000000 0x000037FF { ; load region size_region 6 | ; FLASH part dedicated to M4 7 | ER_IROM1 0x08000000 0x000037FF { ; load address = execution address 8 | *.o (RESET, +First) 9 | *(InRoot$$Sections) 10 | .ANY (+RO) 11 | } 12 | ; Non-backup SRAM1 dedicated to M4 13 | RW_IRAM1 0x20000000 0x000017FF { ; RW data 14 | .ANY (+RW +ZI) 15 | *.o (.ramfunc) ; Used to place functions in RAM 16 | } 17 | ; Backup SRAM2 dedicated to M4 18 | RW_IRAM2 0x20008000 EMPTY 0x00004000 { ; to be modified accordingly to user project. Can be NoInit data for backup usage, RW, ZI region, etc... 19 | } 20 | } 21 | -------------------------------------------------------------------------------- /Projects/NUCLEO-WL55JC/Applications/OpenBootloader/OpenBootloader/App/app_openbootloader.c: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file app_openbootloader.c 4 | * @author MCD Application Team 5 | * @brief OpenBootloader application entry point 6 | ****************************************************************************** 7 | * @attention 8 | * 9 | * Copyright (c) 2022 STMicroelectronics. 10 | * All rights reserved. 11 | * 12 | * This software is licensed under terms that can be found in the LICENSE file 13 | * in the root directory of this software component. 14 | * If no LICENSE file comes with this software, it is provided AS-IS. 15 | * 16 | ****************************************************************************** 17 | */ 18 | 19 | /* Includes ------------------------------------------------------------------*/ 20 | #include "main.h" 21 | #include "app_openbootloader.h" 22 | #include "usart_interface.h" 23 | #include "spi_interface.h" 24 | 25 | #include "flash_interface.h" 26 | #include "ram_interface.h" 27 | #include "systemmemory_interface.h" 28 | #include "optionbytes_interface.h" 29 | #include "otp_interface.h" 30 | #include "engibytes_interface.h" 31 | 32 | #include "iwdg_interface.h" 33 | 34 | #include "openbl_usart_cmd.h" 35 | #include "openbl_spi_cmd.h" 36 | 37 | #include "openbl_core.h" 38 | #include "openbl_mem.h" 39 | 40 | /* Private typedef -----------------------------------------------------------*/ 41 | /* Private define ------------------------------------------------------------*/ 42 | /* Private macro -------------------------------------------------------------*/ 43 | /* Private variables ---------------------------------------------------------*/ 44 | static OPENBL_HandleTypeDef USART_Handle; 45 | static OPENBL_HandleTypeDef SPI_Handle; 46 | static OPENBL_HandleTypeDef IWDG_Handle; 47 | 48 | static OPENBL_OpsTypeDef USART_Ops = 49 | { 50 | OPENBL_USART_Configuration, 51 | OPENBL_USART_DeInit, 52 | OPENBL_USART_ProtocolDetection, 53 | OPENBL_USART_GetCommandOpcode, 54 | OPENBL_USART_SendByte 55 | }; 56 | 57 | 58 | static OPENBL_OpsTypeDef SPI_Ops = 59 | { 60 | OPENBL_SPI_Configuration, 61 | OPENBL_SPI_DeInit, 62 | OPENBL_SPI_ProtocolDetection, 63 | OPENBL_SPI_GetCommandOpcode, 64 | OPENBL_SPI_SendAcknowledgeByte 65 | }; 66 | 67 | 68 | 69 | 70 | static OPENBL_OpsTypeDef IWDG_Ops = 71 | { 72 | OPENBL_IWDG_Configuration, 73 | NULL, 74 | NULL, 75 | NULL, 76 | NULL 77 | }; 78 | 79 | /* Exported variables --------------------------------------------------------*/ 80 | uint16_t SpecialCmdList[SPECIAL_CMD_MAX_NUMBER] = 81 | { 82 | SPECIAL_CMD_DEFAULT 83 | }; 84 | 85 | uint16_t ExtendedSpecialCmdList[EXTENDED_SPECIAL_CMD_MAX_NUMBER] = 86 | { 87 | SPECIAL_CMD_DEFAULT 88 | }; 89 | 90 | /* External variables --------------------------------------------------------*/ 91 | /* Private function prototypes -----------------------------------------------*/ 92 | /* Private functions ---------------------------------------------------------*/ 93 | 94 | /** 95 | * @brief Initialize open Bootloader. 96 | * @param None. 97 | * @retval None. 98 | */ 99 | void OpenBootloader_Init(void) 100 | { 101 | /* Register USART interfaces */ 102 | USART_Handle.p_Ops = &USART_Ops; 103 | USART_Handle.p_Cmd = OPENBL_USART_GetCommandsList(); 104 | 105 | OPENBL_RegisterInterface(&USART_Handle); 106 | 107 | 108 | /* Register SPI interfaces */ 109 | SPI_Handle.p_Ops = &SPI_Ops; 110 | SPI_Handle.p_Cmd = OPENBL_SPI_GetCommandsList(); 111 | 112 | OPENBL_RegisterInterface(&SPI_Handle); 113 | 114 | 115 | /* Register IWDG interfaces */ 116 | IWDG_Handle.p_Ops = &IWDG_Ops; 117 | IWDG_Handle.p_Cmd = NULL; 118 | 119 | OPENBL_RegisterInterface(&IWDG_Handle); 120 | 121 | /* Initialize interfaces */ 122 | OPENBL_Init(); 123 | 124 | /* Initialize memories */ 125 | OPENBL_MEM_RegisterMemory(&FLASH_Descriptor); 126 | OPENBL_MEM_RegisterMemory(&RAM_Descriptor); 127 | OPENBL_MEM_RegisterMemory(&ICP1_Descriptor); 128 | OPENBL_MEM_RegisterMemory(&OB1_Descriptor); 129 | OPENBL_MEM_RegisterMemory(&OTP_Descriptor); 130 | OPENBL_MEM_RegisterMemory(&EB_Descriptor); 131 | } 132 | 133 | /** 134 | * @brief DeInitialize open Bootloader. 135 | * @param None. 136 | * @retval None. 137 | */ 138 | void OpenBootloader_DeInit(void) 139 | { 140 | System_DeInit(); 141 | } 142 | 143 | /** 144 | * @brief This function is used to select which protocol will be used when communicating with the host. 145 | * @param None. 146 | * @retval None. 147 | */ 148 | void OpenBootloader_ProtocolDetection(void) 149 | { 150 | static uint32_t interface_detected = 0; 151 | 152 | if (interface_detected == 0) 153 | { 154 | interface_detected = OPENBL_InterfaceDetection(); 155 | 156 | /* De-initialize the interfaces that are not detected */ 157 | if (interface_detected == 1U) 158 | { 159 | OPENBL_InterfacesDeInit(); 160 | } 161 | } 162 | 163 | if (interface_detected == 1) 164 | { 165 | OPENBL_CommandProcess(); 166 | } 167 | } 168 | -------------------------------------------------------------------------------- /Projects/NUCLEO-WL55JC/Applications/OpenBootloader/OpenBootloader/App/app_openbootloader.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file app_openbootloader.h 4 | * @author MCD Application Team 5 | * @brief Header for app_openbootloader.c module 6 | ****************************************************************************** 7 | * @attention 8 | * 9 | * Copyright (c) 2022 STMicroelectronics. 10 | * All rights reserved. 11 | * 12 | * This software is licensed under terms that can be found in the LICENSE file 13 | * in the root directory of this software component. 14 | * If no LICENSE file comes with this software, it is provided AS-IS. 15 | * 16 | ****************************************************************************** 17 | */ 18 | 19 | /* Define to prevent recursive inclusion -------------------------------------*/ 20 | #ifndef APP_OPENBOOTLOADER_H 21 | #define APP_OPENBOOTLOADER_H 22 | 23 | #ifdef __cplusplus 24 | extern "C" { 25 | #endif 26 | 27 | /* Includes ------------------------------------------------------------------*/ 28 | #include "openbl_core.h" 29 | #include "openbl_mem.h" 30 | 31 | /* Exported types ------------------------------------------------------------*/ 32 | /* Exported constants --------------------------------------------------------*/ 33 | #define SPECIAL_CMD_MAX_NUMBER 0x01U /* Special command max length array */ 34 | #define EXTENDED_SPECIAL_CMD_MAX_NUMBER 0x01U /* Extended special command max length array */ 35 | #define SPECIAL_CMD_DEFAULT 0x0102U /* Default special command */ 36 | 37 | /* Exported macro ------------------------------------------------------------*/ 38 | /* Exported functions ------------------------------------------------------- */ 39 | void OpenBootloader_Init(void); 40 | void OpenBootloader_DeInit(void); 41 | void OpenBootloader_ProtocolDetection(void); 42 | 43 | /* External variables --------------------------------------------------------*/ 44 | extern OPENBL_MemoryTypeDef FLASH_Descriptor; 45 | extern OPENBL_MemoryTypeDef RAM_Descriptor; 46 | extern OPENBL_MemoryTypeDef ICP1_Descriptor; 47 | extern OPENBL_MemoryTypeDef OB1_Descriptor; 48 | extern OPENBL_MemoryTypeDef OTP_Descriptor; 49 | extern OPENBL_MemoryTypeDef EB_Descriptor; 50 | 51 | extern uint16_t SpecialCmdList[SPECIAL_CMD_MAX_NUMBER]; 52 | extern uint16_t ExtendedSpecialCmdList[EXTENDED_SPECIAL_CMD_MAX_NUMBER]; 53 | 54 | #ifdef __cplusplus 55 | } 56 | #endif 57 | 58 | #endif /* APP_OPENBOOTLOADER_H */ 59 | -------------------------------------------------------------------------------- /Projects/NUCLEO-WL55JC/Applications/OpenBootloader/OpenBootloader/Target/common_interface.c: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file common_interface.c 4 | * @author MCD Application Team 5 | * @brief Contains common functions used by different interfaces 6 | ****************************************************************************** 7 | * @attention 8 | * 9 | * Copyright (c) 2022 STMicroelectronics. 10 | * All rights reserved. 11 | * 12 | * This software is licensed under terms that can be found in the LICENSE file 13 | * in the root directory of this software component. 14 | * If no LICENSE file comes with this software, it is provided AS-IS. 15 | * 16 | ****************************************************************************** 17 | */ 18 | 19 | /* Includes ------------------------------------------------------------------*/ 20 | #include "platform.h" 21 | #include "flash_interface.h" 22 | #include "openbootloader_conf.h" 23 | #include "common_interface.h" 24 | 25 | /* Private typedef -----------------------------------------------------------*/ 26 | /* Private define ------------------------------------------------------------*/ 27 | /* Private macro -------------------------------------------------------------*/ 28 | /* Private variables ---------------------------------------------------------*/ 29 | static Function_Pointer ResetCallback; 30 | 31 | /* Private function prototypes -----------------------------------------------*/ 32 | /* Private functions ---------------------------------------------------------*/ 33 | /* Exported functions --------------------------------------------------------*/ 34 | 35 | /** 36 | * @brief Assigns the given value to the Main Stack Pointer (MSP). 37 | * @param TopOfMainStack Main Stack Pointer value to set. 38 | * @retval None. 39 | */ 40 | void Common_SetMsp(uint32_t TopOfMainStack) 41 | { 42 | __set_MSP(TopOfMainStack); 43 | } 44 | 45 | /** 46 | * @brief Enable IRQ Interrupts. 47 | * @retval None. 48 | */ 49 | void Common_EnableIrq(void) 50 | { 51 | __enable_irq(); 52 | } 53 | 54 | /** 55 | * @brief Disable IRQ Interrupts. 56 | * @retval None. 57 | */ 58 | void Common_DisableIrq(void) 59 | { 60 | __disable_irq(); 61 | } 62 | 63 | /** 64 | * @brief Checks whether the target Protection Status is set or not. 65 | * @retval Returns SET if protection is enabled else return RESET. 66 | */ 67 | FlagStatus Common_GetProtectionStatus(void) 68 | { 69 | FlagStatus status; 70 | 71 | if (OPENBL_FLASH_GetReadOutProtectionLevel() != RDP_LEVEL_0) 72 | { 73 | status = SET; 74 | } 75 | else 76 | { 77 | status = RESET; 78 | } 79 | 80 | return status; 81 | } 82 | 83 | /** 84 | * @brief Register a callback function to be called at the end of commands processing. 85 | * @retval None. 86 | */ 87 | void Common_SetPostProcessingCallback(Function_Pointer Callback) 88 | { 89 | ResetCallback = Callback; 90 | } 91 | 92 | /** 93 | * @brief Start post processing task. 94 | * @retval None. 95 | */ 96 | void Common_StartPostProcessing() 97 | { 98 | if (ResetCallback != NULL) 99 | { 100 | ResetCallback(); 101 | 102 | /* In case there is no system reset, we must reset the callback */ 103 | ResetCallback = NULL; 104 | } 105 | } 106 | -------------------------------------------------------------------------------- /Projects/NUCLEO-WL55JC/Applications/OpenBootloader/OpenBootloader/Target/common_interface.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file common_interface.h 4 | * @author MCD Application Team 5 | * @brief Header for common_interface.c module 6 | ****************************************************************************** 7 | * @attention 8 | * 9 | * Copyright (c) 2022 STMicroelectronics. 10 | * All rights reserved. 11 | * 12 | * This software is licensed under terms that can be found in the LICENSE file 13 | * in the root directory of this software component. 14 | * If no LICENSE file comes with this software, it is provided AS-IS. 15 | * 16 | ****************************************************************************** 17 | */ 18 | 19 | /* Define to prevent recursive inclusion -------------------------------------*/ 20 | #ifndef COMMON_INTERFACE_H 21 | #define COMMON_INTERFACE_H 22 | 23 | #ifdef __cplusplus 24 | extern "C" { 25 | #endif 26 | 27 | /* Includes ------------------------------------------------------------------*/ 28 | /* Exported types ------------------------------------------------------------*/ 29 | typedef void (*Function_Pointer)(void); 30 | typedef void (Send_BusyByte_Func)(void); 31 | 32 | /* Exported constants --------------------------------------------------------*/ 33 | /* Exported macro ------------------------------------------------------------*/ 34 | /* Exported functions ------------------------------------------------------- */ 35 | void Common_SetMsp(uint32_t TopOfMainStack); 36 | void Common_EnableIrq(void); 37 | void Common_DisableIrq(void); 38 | FlagStatus Common_GetProtectionStatus(void); 39 | void Common_SetPostProcessingCallback(Function_Pointer Callback); 40 | void Common_StartPostProcessing(void); 41 | 42 | #ifdef __cplusplus 43 | } 44 | #endif 45 | 46 | #endif /* COMMON_INTERFACE_H */ 47 | -------------------------------------------------------------------------------- /Projects/NUCLEO-WL55JC/Applications/OpenBootloader/OpenBootloader/Target/engibytes_interface.c: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file engibytes_interface.c 4 | * @author MCD Application Team 5 | * @brief Contains Engi Bytes access functions 6 | ****************************************************************************** 7 | * @attention 8 | * 9 | * Copyright (c) 2022 STMicroelectronics. 10 | * All rights reserved. 11 | * 12 | * This software is licensed under terms that can be found in the LICENSE file 13 | * in the root directory of this software component. 14 | * If no LICENSE file comes with this software, it is provided AS-IS. 15 | * 16 | ****************************************************************************** 17 | */ 18 | 19 | /* Includes ------------------------------------------------------------------*/ 20 | #include "platform.h" 21 | #include "openbl_mem.h" 22 | #include "app_openbootloader.h" 23 | #include "common_interface.h" 24 | #include "engibytes_interface.h" 25 | 26 | /* Private typedef -----------------------------------------------------------*/ 27 | /* Private define ------------------------------------------------------------*/ 28 | /* Private macro -------------------------------------------------------------*/ 29 | /* Private variables ---------------------------------------------------------*/ 30 | /* Private function prototypes -----------------------------------------------*/ 31 | /* Exported variables --------------------------------------------------------*/ 32 | OPENBL_MemoryTypeDef EB_Descriptor = 33 | { 34 | EB_START_ADDRESS, 35 | EB_END_ADDRESS, 36 | EB_SIZE, 37 | EB_AREA, 38 | OPENBL_EB_Read, 39 | NULL, 40 | NULL, 41 | NULL, 42 | NULL, 43 | NULL, 44 | NULL 45 | }; 46 | 47 | /* Exported functions --------------------------------------------------------*/ 48 | 49 | /** 50 | * @brief This function is used to read data from a given address. 51 | * @param Address The address to be read. 52 | * @retval Returns the read value. 53 | */ 54 | uint8_t OPENBL_EB_Read(uint32_t Address) 55 | { 56 | return (*(uint8_t *)(Address)); 57 | } 58 | -------------------------------------------------------------------------------- /Projects/NUCLEO-WL55JC/Applications/OpenBootloader/OpenBootloader/Target/engibytes_interface.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file engibytes_interface.h 4 | * @author MCD Application Team 5 | * @brief Header for engibytes_interface.c module 6 | ****************************************************************************** 7 | * @attention 8 | * 9 | * Copyright (c) 2022 STMicroelectronics. 10 | * All rights reserved. 11 | * 12 | * This software is licensed under terms that can be found in the LICENSE file 13 | * in the root directory of this software component. 14 | * If no LICENSE file comes with this software, it is provided AS-IS. 15 | * 16 | ****************************************************************************** 17 | */ 18 | 19 | /* Define to prevent recursive inclusion -------------------------------------*/ 20 | #ifndef ENGIBYTES_INTERFACE_H 21 | #define ENGIBYTES_INTERFACE_H 22 | 23 | #ifdef __cplusplus 24 | extern "C" { 25 | #endif 26 | 27 | /* Includes ------------------------------------------------------------------*/ 28 | /* Exported types ------------------------------------------------------------*/ 29 | /* Exported constants --------------------------------------------------------*/ 30 | /* Exported macro ------------------------------------------------------------*/ 31 | /* Exported functions ------------------------------------------------------- */ 32 | uint8_t OPENBL_EB_Read(uint32_t Address); 33 | 34 | #ifdef __cplusplus 35 | } 36 | #endif 37 | 38 | #endif /* ENGIBYTES_INTERFACE_H */ 39 | -------------------------------------------------------------------------------- /Projects/NUCLEO-WL55JC/Applications/OpenBootloader/OpenBootloader/Target/flash_interface.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file flash_interface.h 4 | * @author MCD Application Team 5 | * @brief Header for flash_interface.c module 6 | ****************************************************************************** 7 | * @attention 8 | * 9 | * Copyright (c) 2022 STMicroelectronics. 10 | * All rights reserved. 11 | * 12 | * This software is licensed under terms that can be found in the LICENSE file 13 | * in the root directory of this software component. 14 | * If no LICENSE file comes with this software, it is provided AS-IS. 15 | * 16 | ****************************************************************************** 17 | */ 18 | 19 | /* Define to prevent recursive inclusion -------------------------------------*/ 20 | #ifndef FLASH_INTERFACE_H 21 | #define FLASH_INTERFACE_H 22 | 23 | #ifdef __cplusplus 24 | extern "C" { 25 | #endif 26 | 27 | /* Includes ------------------------------------------------------------------*/ 28 | #include "common_interface.h" 29 | 30 | /* Exported types ------------------------------------------------------------*/ 31 | /* Exported constants --------------------------------------------------------*/ 32 | #define FLASH_BUSY_STATE_ENABLED ((uint32_t)0xAAAA0000) 33 | #define FLASH_BUSY_STATE_DISABLED ((uint32_t)0x0000DDDD) 34 | #define PROGRAM_TIMEOUT ((uint32_t)0x00FFFFFF) 35 | 36 | /* Exported macro ------------------------------------------------------------*/ 37 | /* Exported functions ------------------------------------------------------- */ 38 | void OPENBL_FLASH_JumpToAddress(uint32_t Address); 39 | void OPENBL_FLASH_Lock(void); 40 | void OPENBL_FLASH_OB_Unlock(void); 41 | void OPENBL_FLASH_OB_Launch(void); 42 | uint8_t OPENBL_FLASH_Read(uint32_t Address); 43 | void OPENBL_FLASH_SetReadOutProtectionLevel(uint32_t Level); 44 | void OPENBL_FLASH_Write(uint32_t Address, uint8_t *Data, uint32_t DataLength); 45 | void OPENBL_FLASH_Unlock(void); 46 | ErrorStatus OPENBL_FLASH_MassErase(uint8_t *p_Data, uint32_t DataLength); 47 | ErrorStatus OPENBL_FLASH_Erase(uint8_t *p_Data, uint32_t DataLength); 48 | ErrorStatus OPENBL_FLASH_SetWriteProtection(FunctionalState State, uint8_t *ListOfPages, uint32_t Length); 49 | 50 | uint32_t OPENBL_FLASH_GetReadOutProtectionLevel(void); 51 | #ifdef __cplusplus 52 | } 53 | #endif 54 | 55 | #endif /* FLASH_INTERFACE_H */ 56 | -------------------------------------------------------------------------------- /Projects/NUCLEO-WL55JC/Applications/OpenBootloader/OpenBootloader/Target/interfaces_conf.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file interfaces_conf.h 4 | * @author MCD Application Team 5 | * @brief Contains Interfaces configuration 6 | ****************************************************************************** 7 | * @attention 8 | * 9 | * Copyright (c) 2022 STMicroelectronics. 10 | * All rights reserved. 11 | * 12 | * This software is licensed under terms that can be found in the LICENSE file 13 | * in the root directory of this software component. 14 | * If no LICENSE file comes with this software, it is provided AS-IS. 15 | * 16 | ****************************************************************************** 17 | */ 18 | 19 | /* Define to prevent recursive inclusion -------------------------------------*/ 20 | #ifndef INTERFACES_CONF_H 21 | #define INTERFACES_CONF_H 22 | 23 | #ifdef __cplusplus 24 | extern "C" { 25 | #endif 26 | 27 | /* Includes ------------------------------------------------------------------*/ 28 | #include "stm32wlxx_ll_usart.h" 29 | #include "stm32wlxx_ll_spi.h" 30 | 31 | #define MEMORIES_SUPPORTED 6U 32 | 33 | /* ------------------------- Definitions for USART -------------------------- */ 34 | #define USARTx USART1 35 | #define USARTx_CLK_ENABLE() __HAL_RCC_USART1_CLK_ENABLE() 36 | #define USARTx_CLK_DISABLE() __HAL_RCC_USART1_CLK_DISABLE() 37 | #define USARTx_GPIO_CLK_TX_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE() 38 | #define USARTx_GPIO_CLK_RX_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE() 39 | #define USARTx_DeInit() LL_USART_DeInit(USARTx) 40 | 41 | #define USARTx_TX_PIN GPIO_PIN_9 42 | #define USARTx_TX_GPIO_PORT GPIOA 43 | #define USARTx_RX_PIN GPIO_PIN_10 44 | #define USARTx_RX_GPIO_PORT GPIOA 45 | #define USARTx_ALTERNATE GPIO_AF7_USART1 46 | 47 | /* -------------------------- Definitions for SPI --------------------------- */ 48 | #define SPIx SPI1 49 | #define SPIx_CLK_ENABLE() __HAL_RCC_SPI1_CLK_ENABLE() 50 | #define SPIx_CLK_DISABLE() __HAL_RCC_SPI1_CLK_DISABLE() 51 | #define SPIx_GPIO_CLK_SCK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE() 52 | #define SPIx_GPIO_CLK_MISO_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE() 53 | #define SPIx_GPIO_CLK_MOSI_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE() 54 | #define SPIx_GPIO_CLK_NSS_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE() 55 | #define SPIx_DeInit() LL_SPI_DeInit(SPIx) 56 | #define SPIx_IRQn SPI1_IRQn 57 | 58 | #define SPIx_MOSI_PIN GPIO_PIN_7 59 | #define SPIx_MOSI_PIN_PORT GPIOA 60 | #define SPIx_MISO_PIN GPIO_PIN_6 61 | #define SPIx_MISO_PIN_PORT GPIOA 62 | #define SPIx_SCK_PIN GPIO_PIN_5 63 | #define SPIx_SCK_PIN_PORT GPIOA 64 | #define SPIx_NSS_PIN GPIO_PIN_4 65 | #define SPIx_NSS_PIN_PORT GPIOA 66 | #define SPIx_ALTERNATE GPIO_AF5_SPI1 67 | 68 | #endif /* INTERFACES_CONF_H */ 69 | -------------------------------------------------------------------------------- /Projects/NUCLEO-WL55JC/Applications/OpenBootloader/OpenBootloader/Target/iwdg_interface.c: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file iwdg_interface.c 4 | * @author MCD Application Team 5 | * @brief Contains IWDG HW configuration 6 | ****************************************************************************** 7 | * @attention 8 | * 9 | * Copyright (c) 2022 STMicroelectronics. 10 | * All rights reserved. 11 | * 12 | * This software is licensed under terms that can be found in the LICENSE file 13 | * in the root directory of this software component. 14 | * If no LICENSE file comes with this software, it is provided AS-IS. 15 | * 16 | ****************************************************************************** 17 | */ 18 | 19 | /* Includes ------------------------------------------------------------------*/ 20 | #include "platform.h" 21 | #include "main.h" 22 | #include "iwdg_interface.h" 23 | 24 | /* Private typedef -----------------------------------------------------------*/ 25 | /* Private define ------------------------------------------------------------*/ 26 | /* Private macro -------------------------------------------------------------*/ 27 | /* Private variables ---------------------------------------------------------*/ 28 | static IWDG_HandleTypeDef IWDGHandle; 29 | 30 | /* Private function prototypes -----------------------------------------------*/ 31 | /* Private functions ---------------------------------------------------------*/ 32 | /* Exported functions --------------------------------------------------------*/ 33 | 34 | /** 35 | * @brief This function is used to configure the watchdog. 36 | * @retval None. 37 | */ 38 | void OPENBL_IWDG_Configuration(void) 39 | { 40 | IWDGHandle.Instance = IWDG; 41 | IWDGHandle.Init.Prescaler = IWDG_PRESCALER_256; 42 | IWDGHandle.Init.Window = IWDG_WINDOW_DISABLE; 43 | IWDGHandle.Init.Reload = IWDG_KEY_RELOAD; 44 | 45 | /* In case the user has enabled the IWDG through HW before entering the Open Bootloader */ 46 | IWDG->KR = IWDG_KEY_WRITE_ACCESS_ENABLE; 47 | IWDG->PR = IWDG_PRESCALER_256; 48 | IWDG->KR = IWDG_KEY_RELOAD; 49 | } 50 | 51 | /** 52 | * @brief This function is used to refresh the watchdog. 53 | * @retval None. 54 | */ 55 | void OPENBL_IWDG_Refresh(void) 56 | { 57 | /* Refresh IWDG: reload counter */ 58 | if (HAL_IWDG_Refresh(&IWDGHandle) != HAL_OK) 59 | { 60 | Error_Handler(); 61 | } 62 | } 63 | -------------------------------------------------------------------------------- /Projects/NUCLEO-WL55JC/Applications/OpenBootloader/OpenBootloader/Target/iwdg_interface.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file iwdg_interface.h 4 | * @author MCD Application Team 5 | * @brief Header for iwdg_interface.c module 6 | ****************************************************************************** 7 | * @attention 8 | * 9 | * Copyright (c) 2022 STMicroelectronics. 10 | * All rights reserved. 11 | * 12 | * This software is licensed under terms that can be found in the LICENSE file 13 | * in the root directory of this software component. 14 | * If no LICENSE file comes with this software, it is provided AS-IS. 15 | * 16 | ****************************************************************************** 17 | */ 18 | 19 | /* Define to prevent recursive inclusion -------------------------------------*/ 20 | #ifndef IWDG_INTERFACE_H 21 | #define IWDG_INTERFACE_H 22 | 23 | #ifdef __cplusplus 24 | extern "C" { 25 | #endif 26 | 27 | /* Includes ------------------------------------------------------------------*/ 28 | /* Exported types ------------------------------------------------------------*/ 29 | /* Exported constants --------------------------------------------------------*/ 30 | /* Exported macro ------------------------------------------------------------*/ 31 | /* Exported functions ------------------------------------------------------- */ 32 | void OPENBL_IWDG_Configuration(void); 33 | void OPENBL_IWDG_Refresh(void); 34 | 35 | #ifdef __cplusplus 36 | } 37 | #endif 38 | 39 | #endif /* IWDG_INTERFACE_H */ 40 | -------------------------------------------------------------------------------- /Projects/NUCLEO-WL55JC/Applications/OpenBootloader/OpenBootloader/Target/openbootloader_conf.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file openbootloader_conf.h 4 | * @author MCD Application Team 5 | * @brief Contains Open Bootloader configuration 6 | ****************************************************************************** 7 | * @attention 8 | * 9 | * Copyright (c) 2022 STMicroelectronics. 10 | * All rights reserved. 11 | * 12 | * This software is licensed under terms that can be found in the LICENSE file 13 | * in the root directory of this software component. 14 | * If no LICENSE file comes with this software, it is provided AS-IS. 15 | * 16 | ****************************************************************************** 17 | */ 18 | 19 | /* Define to prevent recursive inclusion -------------------------------------*/ 20 | #ifndef OPENBOOTLOADER_CONF_H 21 | #define OPENBOOTLOADER_CONF_H 22 | 23 | #ifdef __cplusplus 24 | extern "C" { 25 | #endif 26 | 27 | /* Includes ------------------------------------------------------------------*/ 28 | #include "platform.h" 29 | 30 | /* Exported types ------------------------------------------------------------*/ 31 | /* Exported constants --------------------------------------------------------*/ 32 | 33 | /* -------------------------------- Device ID ------------------------------- */ 34 | #define DEVICE_ID_MSB 0x04U /* MSB byte of device ID */ 35 | #define DEVICE_ID_LSB 0x97U /* LSB byte of device ID */ 36 | 37 | /* -------------------------- Definitions for Memories ---------------------- */ 38 | #define FLASH_BL_SIZE (256U * 1024U) /* Size of FLASH 256 kByte */ 39 | #define FLASH_START_ADDRESS 0x08000000U /* start of Flash */ 40 | #define FLASH_END_ADDRESS (FLASH_START_ADDRESS + FLASH_BL_SIZE) /* end of Flash */ 41 | 42 | #define RAM_SIZE (64U * 1024U) /* Size of RAM 64 kByte */ 43 | #define RAM_START_ADDRESS 0x20000000U /* start of SRAM */ 44 | #define RAM_END_ADDRESS (RAM_START_ADDRESS + RAM_SIZE) /* end of SRAM */ 45 | 46 | #define ICP1_SIZE (28U * 1024U) /* Size of ICP 28 kByte */ 47 | #define ICP1_START_ADDRESS 0x1FFF0000U /* System memory registers address */ 48 | #define ICP1_END_ADDRESS (ICP1_START_ADDRESS + ICP1_SIZE) /* System memory registers end address */ 49 | 50 | #define OB1_SIZE 112U /* Size of OB 112 Byte */ 51 | #define OB1_START_ADDRESS 0x1FFF7800U /* Option bytes registers address */ 52 | #define OB1_END_ADDRESS (OB1_START_ADDRESS + OB1_SIZE) /* Option bytes end address */ 53 | 54 | #define OTP_BL_SIZE 1024U /* Size of OTP 1024 Byte */ 55 | #define OTP_START_ADDRESS 0x1FFF7000U /* OTP registers address */ 56 | #define OTP_END_ADDRESS (OTP_START_ADDRESS + OTP_BL_SIZE) /* OTP end address */ 57 | 58 | #define EB_SIZE 1024U /* Size of Engi bytes 1024 Byte */ 59 | #define EB_START_ADDRESS 0x1FFF7400U /* Engi bytes start address */ 60 | #define EB_END_ADDRESS (EB_START_ADDRESS + EB_SIZE) /* Engi bytes end address */ 61 | 62 | #define OPENBL_RAM_SIZE (6U * 1024U) /* RAM used by the Open Bootloader 6 kBytes */ 63 | 64 | #define OPENBL_DEFAULT_MEM FLASH_START_ADDRESS /* Address used for the Erase, Writep and readp command */ 65 | 66 | #define RDP_LEVEL_0 OB_RDP_LEVEL_0 67 | #define RDP_LEVEL_1 OB_RDP_LEVEL_1 68 | #define RDP_LEVEL_2 OB_RDP_LEVEL_2 69 | 70 | #define AREA_ERROR 0x0U /* Error Address Area */ 71 | #define FLASH_AREA 0x1U /* Flash Address Area */ 72 | #define RAM_AREA 0x2U /* RAM Address area */ 73 | #define OB_AREA 0x3U /* Option bytes Address area */ 74 | #define OTP_AREA 0x4U /* OTP Address area */ 75 | #define ICP_AREA 0x5U /* System memory area */ 76 | #define EB_AREA 0x6U /* Engi bytes Address area */ 77 | 78 | #define FLASH_MASS_ERASE 0xFFFF 79 | #define FLASH_BANK1_ERASE 0xFFFE 80 | #define FLASH_BANK2_ERASE 0xFFFD 81 | 82 | #define INTERFACES_SUPPORTED 3U 83 | 84 | /* Exported macro ------------------------------------------------------------*/ 85 | /* Exported functions ------------------------------------------------------- */ 86 | 87 | #ifdef __cplusplus 88 | } 89 | #endif 90 | 91 | #endif /* OPENBOOTLOADER_CONF_H */ 92 | -------------------------------------------------------------------------------- /Projects/NUCLEO-WL55JC/Applications/OpenBootloader/OpenBootloader/Target/optionbytes_interface.c: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file optionbytes_interface.c 4 | * @author MCD Application Team 5 | * @brief Contains Option Bytes access functions 6 | ****************************************************************************** 7 | * @attention 8 | * 9 | * Copyright (c) 2022 STMicroelectronics. 10 | * All rights reserved. 11 | * 12 | * This software is licensed under terms that can be found in the LICENSE file 13 | * in the root directory of this software component. 14 | * If no LICENSE file comes with this software, it is provided AS-IS. 15 | * 16 | ****************************************************************************** 17 | */ 18 | 19 | /* Includes ------------------------------------------------------------------*/ 20 | #include "platform.h" 21 | #include "openbl_mem.h" 22 | #include "app_openbootloader.h" 23 | #include "common_interface.h" 24 | #include "optionbytes_interface.h" 25 | 26 | /* Private typedef -----------------------------------------------------------*/ 27 | /* Private define ------------------------------------------------------------*/ 28 | /* Private macro -------------------------------------------------------------*/ 29 | /* Private variables ---------------------------------------------------------*/ 30 | /* Private function prototypes -----------------------------------------------*/ 31 | /* Exported variables --------------------------------------------------------*/ 32 | OPENBL_MemoryTypeDef OB1_Descriptor = 33 | { 34 | OB1_START_ADDRESS, 35 | OB1_END_ADDRESS, 36 | OB1_SIZE, 37 | OB_AREA, 38 | OPENBL_OB_Read, 39 | OPENBL_OB_Write, 40 | NULL, 41 | NULL, 42 | NULL, 43 | NULL, 44 | NULL 45 | }; 46 | 47 | /* Exported functions --------------------------------------------------------*/ 48 | 49 | /** 50 | * @brief Launch the option byte loading. 51 | * @retval None. 52 | */ 53 | void OPENBL_OB_Launch(void) 54 | { 55 | /* Set the option start bit */ 56 | HAL_FLASH_OB_Launch(); 57 | 58 | /* Set the option lock bit and Lock the flash */ 59 | HAL_FLASH_OB_Lock(); 60 | HAL_FLASH_Lock(); 61 | } 62 | 63 | /** 64 | * @brief This function is used to read data from a given address. 65 | * @param Address The address to be read. 66 | * @retval Returns the read value. 67 | */ 68 | uint8_t OPENBL_OB_Read(uint32_t Address) 69 | { 70 | return (*(uint8_t *)(Address)); 71 | } 72 | 73 | /** 74 | * @brief This function is used to write data in Option bytes. 75 | * @param Address The address where that data will be written. 76 | * @param Data The data to be written. 77 | * @param DataLength The length of the data to be written. 78 | * @retval None. 79 | */ 80 | void OPENBL_OB_Write(uint32_t Address, uint8_t *Data, uint32_t DataLength) 81 | { 82 | uint32_t timeout = 0U; 83 | 84 | /* Unlock the FLASH & Option Bytes Registers access */ 85 | HAL_FLASH_Unlock(); 86 | HAL_FLASH_OB_Unlock(); 87 | 88 | /* Clear error programming flags */ 89 | __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_ALL_ERRORS); 90 | 91 | /* Write USER OPT + RDP level */ 92 | if (DataLength >= 1U) 93 | { 94 | WRITE_REG(FLASH->OPTR, (*(Data) | (*(Data + 1U) << 8U) | (*(Data + 2U) << 16U) | (*(Data + 3U) << 24U))); 95 | } 96 | 97 | /* Write PCROP1ASR */ 98 | if (DataLength > 8U) 99 | { 100 | WRITE_REG(FLASH->PCROP1ASR, (*(Data + 8U))); 101 | } 102 | 103 | /* Write PCROP1AER */ 104 | if (DataLength > 16U) 105 | { 106 | WRITE_REG(FLASH->PCROP1AER, (*(Data + 16U) | (*(Data + 19U) << 24U))); 107 | } 108 | 109 | /* Write WRP1AR */ 110 | if (DataLength > 24U) 111 | { 112 | WRITE_REG(FLASH->WRP1AR, (*(Data + 24U) | (*(Data + 26U) << 16U))); 113 | } 114 | 115 | /* Write WRP1BR */ 116 | if (DataLength > 32U) 117 | { 118 | WRITE_REG(FLASH->WRP1BR, (*(Data + 32U) | (*(Data + 34U) << 16U))); 119 | } 120 | 121 | /* Write PCROP1BSR */ 122 | if (DataLength > 40U) 123 | { 124 | WRITE_REG(FLASH->PCROP1BSR, (*(Data + 40U))); 125 | } 126 | 127 | /* Write PCROP1BER */ 128 | if (DataLength > 48U) 129 | { 130 | WRITE_REG(FLASH->PCROP1BER, (*(Data + 48U))); 131 | } 132 | 133 | /* Write IPCCBR */ 134 | if (DataLength > 104U) 135 | { 136 | WRITE_REG(FLASH->IPCCBR, (*(Data + 104U) | (*(Data + 105U) << 8U))); 137 | } 138 | 139 | /* Check the BSY bit for potential FLASH on going operation */ 140 | while (__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY)) 141 | { 142 | if ((timeout++) >= OPENBL_OB_TIMEOUT) 143 | { 144 | NVIC_SystemReset(); 145 | } 146 | } 147 | timeout = 0U; 148 | 149 | /* Check the PESD bit*/ 150 | while (__HAL_FLASH_GET_FLAG(FLASH_FLAG_PESD)) 151 | { 152 | if ((timeout++) >= OPENBL_OB_TIMEOUT) 153 | { 154 | NVIC_SystemReset(); 155 | } 156 | } 157 | timeout = 0U; 158 | 159 | /* Trigger options bytes programming operation */ 160 | SET_BIT(FLASH->CR, FLASH_CR_OPTSTRT); 161 | 162 | /* Check the BSY bit for potential FLASH on going operation */ 163 | while (__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY)) 164 | { 165 | if ((timeout++) >= OPENBL_OB_TIMEOUT) 166 | { 167 | NVIC_SystemReset(); 168 | } 169 | } 170 | 171 | /* Register system reset callback */ 172 | Common_SetPostProcessingCallback(OPENBL_OB_Launch); 173 | } 174 | -------------------------------------------------------------------------------- /Projects/NUCLEO-WL55JC/Applications/OpenBootloader/OpenBootloader/Target/optionbytes_interface.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file optionbytes_interface.h 4 | * @author MCD Application Team 5 | * @brief Header for optionbytes_interface.c module 6 | ****************************************************************************** 7 | * @attention 8 | * 9 | * Copyright (c) 2022 STMicroelectronics. 10 | * All rights reserved. 11 | * 12 | * This software is licensed under terms that can be found in the LICENSE file 13 | * in the root directory of this software component. 14 | * If no LICENSE file comes with this software, it is provided AS-IS. 15 | * 16 | ****************************************************************************** 17 | */ 18 | 19 | /* Define to prevent recursive inclusion -------------------------------------*/ 20 | #ifndef OPTIONBYTES_INTERFACE_H 21 | #define OPTIONBYTES_INTERFACE_H 22 | 23 | #ifdef __cplusplus 24 | extern "C" { 25 | #endif 26 | 27 | /* Includes ------------------------------------------------------------------*/ 28 | /* Exported types ------------------------------------------------------------*/ 29 | /* Exported constants --------------------------------------------------------*/ 30 | #define OPENBL_OB_TIMEOUT 0x700000U 31 | 32 | /* Exported macro ------------------------------------------------------------*/ 33 | /* Exported functions ------------------------------------------------------- */ 34 | uint8_t OPENBL_OB_Read(uint32_t Address); 35 | void OPENBL_OB_Write(uint32_t Address, uint8_t *Data, uint32_t DataLength); 36 | void OPENBL_OB_Launch(void); 37 | 38 | #ifdef __cplusplus 39 | } 40 | #endif 41 | 42 | #endif /* OPTIONBYTES_INTERFACE_H */ 43 | -------------------------------------------------------------------------------- /Projects/NUCLEO-WL55JC/Applications/OpenBootloader/OpenBootloader/Target/otp_interface.c: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file otp_interface.c 4 | * @author MCD Application Team 5 | * @brief Contains One-time programmable access functions 6 | ****************************************************************************** 7 | * @attention 8 | * 9 | * Copyright (c) 2022 STMicroelectronics. 10 | * All rights reserved. 11 | * 12 | * This software is licensed under terms that can be found in the LICENSE file 13 | * in the root directory of this software component. 14 | * If no LICENSE file comes with this software, it is provided AS-IS. 15 | * 16 | ****************************************************************************** 17 | */ 18 | 19 | /* Includes ------------------------------------------------------------------*/ 20 | #include "platform.h" 21 | #include "openbl_mem.h" 22 | #include "app_openbootloader.h" 23 | #include "common_interface.h" 24 | #include "otp_interface.h" 25 | 26 | /* Private typedef -----------------------------------------------------------*/ 27 | /* Private define ------------------------------------------------------------*/ 28 | #define OTP_PROG_STEP_SIZE ((uint8_t)0x8U) 29 | 30 | /* Private macro -------------------------------------------------------------*/ 31 | /* Private variables ---------------------------------------------------------*/ 32 | /* Private function prototypes -----------------------------------------------*/ 33 | static void OPENBL_OTP_Program(uint32_t Address, uint64_t Data); 34 | 35 | /* Exported variables --------------------------------------------------------*/ 36 | OPENBL_MemoryTypeDef OTP_Descriptor = 37 | { 38 | OTP_START_ADDRESS, 39 | OTP_END_ADDRESS, 40 | OTP_BL_SIZE, 41 | OTP_AREA, 42 | OPENBL_OTP_Read, 43 | OPENBL_OTP_Write, 44 | NULL, 45 | NULL, 46 | NULL, 47 | NULL, 48 | NULL 49 | }; 50 | 51 | /* Exported functions --------------------------------------------------------*/ 52 | 53 | /** 54 | * @brief This function is used to read data from a given address. 55 | * @param Address The address to be read. 56 | * @retval Returns the read value. 57 | */ 58 | uint8_t OPENBL_OTP_Read(uint32_t Address) 59 | { 60 | return (*(uint8_t *)(Address)); 61 | } 62 | 63 | /** 64 | * @brief This function is used to write data in OTP. 65 | * @param Address The address where that data will be written. 66 | * @param pData The data to be written. 67 | * @param DataLength The length of the data to be written. 68 | * @retval None. 69 | */ 70 | void OPENBL_OTP_Write(uint32_t Address, uint8_t *pData, uint32_t DataLength) 71 | { 72 | uint32_t index; 73 | uint8_t remaining_data[OTP_PROG_STEP_SIZE] = {0x0}; 74 | uint8_t remaining; 75 | 76 | if ((pData != NULL) && (DataLength != 0U)) 77 | { 78 | /* Unlock the flash memory for write operation */ 79 | HAL_FLASH_Unlock(); 80 | 81 | /* Program double-word by double-word (8 bytes) */ 82 | while ((DataLength >> 3U) > 0U) 83 | { 84 | OPENBL_OTP_Program(Address, (uint64_t)(*((uint64_t *)((uint32_t)pData)))); 85 | 86 | Address += OTP_PROG_STEP_SIZE; 87 | pData += OTP_PROG_STEP_SIZE; 88 | DataLength -= OTP_PROG_STEP_SIZE; 89 | } 90 | 91 | /* If remaining count, go back to fill the rest with 0xFF */ 92 | if (DataLength > 0U) 93 | { 94 | remaining = OTP_PROG_STEP_SIZE - DataLength; 95 | 96 | /* copy the remaining bytes */ 97 | for (index = 0U; index < DataLength; index++) 98 | { 99 | remaining_data[index] = *(pData + index); 100 | } 101 | 102 | /* Fill the upper bytes with 0xFF */ 103 | for (index = 0U; index < remaining; index++) 104 | { 105 | remaining_data[index + DataLength] = 0xFFU; 106 | } 107 | 108 | /* FLASH word program */ 109 | OPENBL_OTP_Program(Address, (uint64_t)(*((uint64_t *)((uint32_t)remaining_data)))); 110 | } 111 | 112 | /* Lock the Flash to disable the flash control register access */ 113 | HAL_FLASH_Lock(); 114 | } 115 | 116 | /* Lock the Flash to disable the flash control register access */ 117 | HAL_FLASH_Lock(); 118 | } 119 | 120 | /* Private functions ---------------------------------------------------------*/ 121 | 122 | /** 123 | * @brief Program double word at a specified FLASH address. 124 | * @param Address specifies the address to be programmed. 125 | * @param Data specifies the data to be programmed. 126 | * @retval None. 127 | */ 128 | static void OPENBL_OTP_Program(uint32_t Address, uint64_t Data) 129 | { 130 | /* Clear all FLASH errors flags before starting write operation */ 131 | __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_ALL_ERRORS); 132 | 133 | HAL_FLASH_Program(FLASH_TYPEPROGRAM_DOUBLEWORD, Address, Data); 134 | } 135 | -------------------------------------------------------------------------------- /Projects/NUCLEO-WL55JC/Applications/OpenBootloader/OpenBootloader/Target/otp_interface.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file otp_interface.h 4 | * @author MCD Application Team 5 | * @brief Header for otp_interface.c module 6 | ****************************************************************************** 7 | * @attention 8 | * 9 | * Copyright (c) 2022 STMicroelectronics. 10 | * All rights reserved. 11 | * 12 | * This software is licensed under terms that can be found in the LICENSE file 13 | * in the root directory of this software component. 14 | * If no LICENSE file comes with this software, it is provided AS-IS. 15 | * 16 | ****************************************************************************** 17 | */ 18 | 19 | /* Define to prevent recursive inclusion -------------------------------------*/ 20 | #ifndef OTP_INTERFACE_H 21 | #define OTP_INTERFACE_H 22 | 23 | #ifdef __cplusplus 24 | extern "C" { 25 | #endif 26 | 27 | /* Includes ------------------------------------------------------------------*/ 28 | /* Exported types ------------------------------------------------------------*/ 29 | /* Exported constants --------------------------------------------------------*/ 30 | /* Exported macro ------------------------------------------------------------*/ 31 | /* Exported functions ------------------------------------------------------- */ 32 | uint8_t OPENBL_OTP_Read(uint32_t Address); 33 | void OPENBL_OTP_Write(uint32_t Address, uint8_t *Data, uint32_t DataLength); 34 | 35 | #ifdef __cplusplus 36 | } 37 | #endif 38 | 39 | #endif /* OPTIONBYTES_INTERFACE_H */ 40 | -------------------------------------------------------------------------------- /Projects/NUCLEO-WL55JC/Applications/OpenBootloader/OpenBootloader/Target/platform.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file platform.h 4 | * @author MCD Application Team 5 | * @brief Header for patterns 6 | ****************************************************************************** 7 | * @attention 8 | * 9 | * Copyright (c) 2022 STMicroelectronics. 10 | * All rights reserved. 11 | * 12 | * This software is licensed under terms that can be found in the LICENSE file 13 | * in the root directory of this software component. 14 | * If no LICENSE file comes with this software, it is provided AS-IS. 15 | * 16 | ****************************************************************************** 17 | */ 18 | 19 | /* Define to prevent recursive inclusion -------------------------------------*/ 20 | #ifndef PLATFORM_H 21 | #define PLATFORM_H 22 | 23 | #ifdef __cplusplus 24 | extern "C" { 25 | #endif 26 | 27 | /* Includes ------------------------------------------------------------------*/ 28 | #include "stm32wlxx_hal.h" 29 | 30 | /* Exported types ------------------------------------------------------------*/ 31 | /* Exported constants --------------------------------------------------------*/ 32 | /* Exported macro ------------------------------------------------------------*/ 33 | /* Exported functions ------------------------------------------------------- */ 34 | 35 | #ifdef __cplusplus 36 | } 37 | #endif 38 | 39 | #endif /* PLATFORM_H */ 40 | -------------------------------------------------------------------------------- /Projects/NUCLEO-WL55JC/Applications/OpenBootloader/OpenBootloader/Target/ram_interface.c: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file ram_interface.c 4 | * @author MCD Application Team 5 | * @brief Contains RAM access functions 6 | ****************************************************************************** 7 | * @attention 8 | * 9 | * Copyright (c) 2022 STMicroelectronics. 10 | * All rights reserved. 11 | * 12 | * This software is licensed under terms that can be found in the LICENSE file 13 | * in the root directory of this software component. 14 | * If no LICENSE file comes with this software, it is provided AS-IS. 15 | * 16 | ****************************************************************************** 17 | */ 18 | 19 | /* Includes ------------------------------------------------------------------*/ 20 | #include "platform.h" 21 | #include "openbl_mem.h" 22 | #include "app_openbootloader.h" 23 | #include "common_interface.h" 24 | #include "ram_interface.h" 25 | 26 | /* Private typedef -----------------------------------------------------------*/ 27 | /* Private define ------------------------------------------------------------*/ 28 | /* Private macro -------------------------------------------------------------*/ 29 | /* Private variables ---------------------------------------------------------*/ 30 | /* Private function prototypes -----------------------------------------------*/ 31 | /* Exported variables --------------------------------------------------------*/ 32 | OPENBL_MemoryTypeDef RAM_Descriptor = 33 | { 34 | RAM_START_ADDRESS + OPENBL_RAM_SIZE, /* OPENBL_RAM_SIZE is added to the RAM start address to protect OpenBootloader RAM area */ 35 | RAM_END_ADDRESS, 36 | RAM_SIZE, 37 | RAM_AREA, 38 | OPENBL_RAM_Read, 39 | OPENBL_RAM_Write, 40 | NULL, 41 | NULL, 42 | OPENBL_RAM_JumpToAddress, 43 | NULL, 44 | NULL 45 | }; 46 | 47 | /* Exported functions --------------------------------------------------------*/ 48 | 49 | /** 50 | * @brief This function is used to read data from a given address. 51 | * @param Address The address to be read. 52 | * @retval Returns the read value. 53 | */ 54 | uint8_t OPENBL_RAM_Read(uint32_t Address) 55 | { 56 | return (*(uint8_t *)(Address)); 57 | } 58 | 59 | /** 60 | * @brief This function is used to write data in RAM memory. 61 | * @param Address The address where that data will be written. 62 | * @param pData The data to be written. 63 | * @param DataLength The length of the data to be written. 64 | * @retval None. 65 | */ 66 | void OPENBL_RAM_Write(uint32_t Address, uint8_t *pData, uint32_t DataLength) 67 | { 68 | uint32_t index; 69 | uint32_t aligned_length = DataLength; 70 | 71 | if (aligned_length & 0x3) 72 | { 73 | aligned_length = (aligned_length & 0xFCU) + 4U; 74 | } 75 | 76 | for (index = 0U; index < aligned_length; index += 4U) 77 | { 78 | *(__IO uint32_t *)(Address + index) = *(__IO uint32_t *)(pData + index); 79 | } 80 | } 81 | 82 | /** 83 | * @brief This function is used to jump to a given address. 84 | * @param Address The address where the function will jump. 85 | * @retval None. 86 | */ 87 | void OPENBL_RAM_JumpToAddress(uint32_t Address) 88 | { 89 | Function_Pointer jump_to_address; 90 | 91 | /* De-initialize all HW resources used by the Open Bootloader to their reset values */ 92 | OPENBL_DeInit(); 93 | 94 | /* Enable IRQ */ 95 | Common_EnableIrq(); 96 | 97 | jump_to_address = (Function_Pointer)(*(__IO uint32_t *)(Address + 4U)); 98 | 99 | /* Initialize user application's stack pointer */ 100 | Common_SetMsp(*(__IO uint32_t *) Address); 101 | 102 | jump_to_address(); 103 | } 104 | -------------------------------------------------------------------------------- /Projects/NUCLEO-WL55JC/Applications/OpenBootloader/OpenBootloader/Target/ram_interface.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file ram_interface.h 4 | * @author MCD Application Team 5 | * @brief Header for ram_interface.c module 6 | ****************************************************************************** 7 | * @attention 8 | * 9 | * Copyright (c) 2022 STMicroelectronics. 10 | * All rights reserved. 11 | * 12 | * This software is licensed under terms that can be found in the LICENSE file 13 | * in the root directory of this software component. 14 | * If no LICENSE file comes with this software, it is provided AS-IS. 15 | * 16 | ****************************************************************************** 17 | */ 18 | 19 | /* Define to prevent recursive inclusion -------------------------------------*/ 20 | #ifndef RAM_INTERFACE_H 21 | #define RAM_INTERFACE_H 22 | 23 | #ifdef __cplusplus 24 | extern "C" { 25 | #endif 26 | 27 | /* Includes ------------------------------------------------------------------*/ 28 | /* Exported types ------------------------------------------------------------*/ 29 | /* Exported constants --------------------------------------------------------*/ 30 | /* Exported macro ------------------------------------------------------------*/ 31 | /* Exported functions ------------------------------------------------------- */ 32 | void OPENBL_RAM_JumpToAddress(uint32_t Address); 33 | uint8_t OPENBL_RAM_Read(uint32_t Address); 34 | void OPENBL_RAM_Write(uint32_t Address, uint8_t *Data, uint32_t DataLength); 35 | 36 | #ifdef __cplusplus 37 | } 38 | #endif 39 | 40 | #endif /* RAM_INTERFACE_H */ 41 | -------------------------------------------------------------------------------- /Projects/NUCLEO-WL55JC/Applications/OpenBootloader/OpenBootloader/Target/spi_interface.c: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file spi_interface.c 4 | * @author MCD Application Team 5 | * @brief Contains SPI HW configuration 6 | ****************************************************************************** 7 | * @attention 8 | * 9 | * Copyright (c) 2022 STMicroelectronics. 10 | * All rights reserved. 11 | * 12 | * This software is licensed under terms that can be found in the LICENSE file 13 | * in the root directory of this software component. 14 | * If no LICENSE file comes with this software, it is provided AS-IS. 15 | * 16 | ****************************************************************************** 17 | */ 18 | 19 | /* Includes ------------------------------------------------------------------*/ 20 | #include "platform.h" 21 | #include "interfaces_conf.h" 22 | #include "openbl_core.h" 23 | #include "openbl_spi_cmd.h" 24 | #include "spi_interface.h" 25 | #include "iwdg_interface.h" 26 | 27 | /* Private typedef -----------------------------------------------------------*/ 28 | /* Private define ------------------------------------------------------------*/ 29 | #define SPI_DUMMY_BYTE 0x00U /* Dummy byte */ 30 | #define SPI_SYNC_BYTE 0x5AU /* Synchronization byte */ 31 | #define SPI_BUSY_BYTE 0xA5U /* Busy byte */ 32 | 33 | /* Private macro -------------------------------------------------------------*/ 34 | /* Private variables ---------------------------------------------------------*/ 35 | static volatile uint8_t SpiRxNotEmpty = 0U; 36 | static uint8_t BusyState; 37 | static uint8_t SpiDetected = 0U; 38 | 39 | /* Exported variables --------------------------------------------------------*/ 40 | /* Private function prototypes -----------------------------------------------*/ 41 | static void OPENBL_SPI_Init(void); 42 | #if defined (__ICCARM__) 43 | __ramfunc void OPENBL_SPI_ClearFlag_OVR(void); 44 | #else 45 | __attribute__((section(".ramfunc"))) void OPENBL_SPI_ClearFlag_OVR(void); 46 | #endif /* (__ICCARM__) */ 47 | 48 | /* Private functions ---------------------------------------------------------*/ 49 | 50 | /** 51 | * @brief This function is used to initialize the SPI peripheral 52 | * @retval None. 53 | */ 54 | static void OPENBL_SPI_Init(void) 55 | { 56 | LL_SPI_InitTypeDef SPI_InitStruct = {0}; 57 | 58 | SPI_InitStruct.TransferDirection = LL_SPI_FULL_DUPLEX; 59 | SPI_InitStruct.Mode = LL_SPI_MODE_SLAVE; 60 | SPI_InitStruct.DataWidth = LL_SPI_DATAWIDTH_8BIT; 61 | SPI_InitStruct.ClockPolarity = LL_SPI_POLARITY_LOW; 62 | SPI_InitStruct.ClockPhase = LL_SPI_PHASE_1EDGE; 63 | SPI_InitStruct.NSS = LL_SPI_NSS_SOFT; 64 | SPI_InitStruct.BaudRate = LL_SPI_BAUDRATEPRESCALER_DIV2; 65 | SPI_InitStruct.BitOrder = LL_SPI_MSB_FIRST; 66 | SPI_InitStruct.CRCCalculation = LL_SPI_CRCCALCULATION_DISABLE; 67 | SPI_InitStruct.CRCPoly = 7U; 68 | 69 | LL_SPI_Init(SPIx, &SPI_InitStruct); 70 | LL_SPI_SetRxFIFOThreshold(SPIx, LL_SPI_RX_FIFO_TH_QUARTER); 71 | 72 | HAL_NVIC_SetPriority(SPIx_IRQn, 0U, 0U); 73 | HAL_NVIC_EnableIRQ(SPIx_IRQn); 74 | 75 | LL_SPI_Enable(SPIx); 76 | } 77 | 78 | /* Exported functions --------------------------------------------------------*/ 79 | 80 | /** 81 | * @brief This function is used to configure SPI pins and then initialize the used SPI instance. 82 | * @retval None. 83 | */ 84 | void OPENBL_SPI_Configuration(void) 85 | { 86 | GPIO_InitTypeDef GPIO_InitStruct = {0}; 87 | 88 | /* Enable all resources clocks --------------------------------------------*/ 89 | /* Enable used GPIOx clocks */ 90 | SPIx_GPIO_CLK_SCK_ENABLE(); 91 | SPIx_GPIO_CLK_MISO_ENABLE(); 92 | SPIx_GPIO_CLK_MOSI_ENABLE(); 93 | SPIx_GPIO_CLK_NSS_ENABLE(); 94 | 95 | /* Enable SPI clock */ 96 | SPIx_CLK_ENABLE(); 97 | 98 | /* SPI1 pins configuration -----------------------------------------------*/ 99 | /* 100 | +-------------+ 101 | | SPI1 | 102 | +-----+-------------+ 103 | | MOSI| PA7 | 104 | +-----+-------------+ 105 | | MISO| PA6 | 106 | +-----+-------------+ 107 | | SCK | PA5 | 108 | +-----+-------------+ 109 | | NSS | PA4 | 110 | +-----+-------------+ */ 111 | 112 | GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 113 | GPIO_InitStruct.Pull = GPIO_PULLDOWN; 114 | GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 115 | GPIO_InitStruct.Alternate = SPIx_ALTERNATE; 116 | 117 | /* SPI MOSI pin configuration */ 118 | GPIO_InitStruct.Pin = SPIx_MOSI_PIN; 119 | HAL_GPIO_Init(SPIx_MOSI_PIN_PORT, &GPIO_InitStruct); 120 | 121 | /* SPI MISO pin configuration */ 122 | GPIO_InitStruct.Pin = SPIx_MISO_PIN; 123 | HAL_GPIO_Init(SPIx_MISO_PIN_PORT, &GPIO_InitStruct); 124 | 125 | /* SPI SCK pin configuration */ 126 | GPIO_InitStruct.Pin = SPIx_SCK_PIN; 127 | HAL_GPIO_Init(SPIx_SCK_PIN_PORT, &GPIO_InitStruct); 128 | 129 | /* SPI NSS pin configuration */ 130 | GPIO_InitStruct.Pin = SPIx_NSS_PIN; 131 | HAL_GPIO_Init(SPIx_NSS_PIN_PORT, &GPIO_InitStruct); 132 | 133 | OPENBL_SPI_Init(); 134 | } 135 | 136 | /** 137 | * @brief This function is used to De-initialize the SPI pins and instance. 138 | * @retval None. 139 | */ 140 | void OPENBL_SPI_DeInit(void) 141 | { 142 | /* Only de-initialize the SPI if it is not the current detected interface */ 143 | if (SpiDetected == 0U) 144 | { 145 | LL_SPI_Disable(SPIx); 146 | 147 | SPIx_CLK_DISABLE(); 148 | } 149 | } 150 | 151 | /** 152 | * @brief This function is used to detect if there is any activity on SPI protocol. 153 | * @retval None. 154 | */ 155 | uint8_t OPENBL_SPI_ProtocolDetection(void) 156 | { 157 | /* Check if there is any activity on SPI */ 158 | if (LL_SPI_IsActiveFlag_RXNE(SPIx) != 0) 159 | { 160 | /* Check that Synchronization byte has been received on SPI */ 161 | if (LL_SPI_ReceiveData8(SPIx) == SPI_SYNC_BYTE) 162 | { 163 | SpiDetected = 1U; 164 | 165 | /* Enable the interrupt of Rx not empty buffer */ 166 | LL_SPI_EnableIT_RXNE(SPIx); 167 | 168 | /* Send synchronization byte */ 169 | OPENBL_SPI_SendByte(SYNC_BYTE); 170 | 171 | /* Send acknowledgment */ 172 | OPENBL_SPI_SendAcknowledgeByte(ACK_BYTE); 173 | } 174 | else 175 | { 176 | SpiDetected = 0U; 177 | } 178 | } 179 | else 180 | { 181 | SpiDetected = 0U; 182 | } 183 | 184 | return SpiDetected; 185 | } 186 | 187 | /** 188 | * @brief This function is used to get the command opcode from the host. 189 | * @retval Returns the command. 190 | */ 191 | uint8_t OPENBL_SPI_GetCommandOpcode(void) 192 | { 193 | uint8_t command_opc; 194 | 195 | /* Disable busy byte */ 196 | BusyState = 0U; 197 | 198 | /* Check if there is any activity on SPI */ 199 | while (OPENBL_SPI_ReadByte() != SPI_SYNC_BYTE) 200 | {} 201 | 202 | /* Get the command opcode */ 203 | command_opc = OPENBL_SPI_ReadByte(); 204 | 205 | /* Check the data integrity */ 206 | if ((command_opc ^ OPENBL_SPI_ReadByte()) != 0xFFU) 207 | { 208 | command_opc = ERROR_COMMAND; 209 | } 210 | 211 | return command_opc; 212 | } 213 | 214 | /** 215 | * @brief This function is used to read one byte from SPI pipe. 216 | * Read operation is synchronized on SPI Rx buffer not empty interrupt. 217 | * @retval Returns the read byte. 218 | */ 219 | #if defined (__ICCARM__) 220 | __ramfunc uint8_t OPENBL_SPI_ReadByte(void) 221 | #else 222 | __attribute__((section(".ramfunc"))) uint8_t OPENBL_SPI_ReadByte(void) 223 | #endif /* (__ICCARM__) */ 224 | { 225 | uint8_t data; 226 | 227 | /* Wait until SPI Rx buffer not empty interrupt */ 228 | while (SpiRxNotEmpty == 0U) 229 | { 230 | /* Refresh IWDG: reload counter */ 231 | IWDG->KR = IWDG_KEY_RELOAD; 232 | } 233 | 234 | /* Reset the RX not empty token */ 235 | SpiRxNotEmpty = 0U; 236 | 237 | /* Read the SPI data register */ 238 | data = SPIx->DR; 239 | 240 | /* Enable the interrupt of Rx not empty buffer */ 241 | SPIx->CR2 |= SPI_CR2_RXNEIE; 242 | 243 | return data; 244 | } 245 | 246 | /** 247 | * @brief This function is used to send one busy byte each receive interrupt through SPI pipe. 248 | * Read operation is synchronized on SPI Rx buffer not empty interrupt. 249 | * @retval Returns the read byte. 250 | */ 251 | #if defined (__ICCARM__) 252 | __ramfunc void OPENBL_SPI_SendBusyByte(void) 253 | #else 254 | __attribute__((section(".ramfunc"))) void OPENBL_SPI_SendBusyByte(void) 255 | #endif /* (__ICCARM__) */ 256 | { 257 | /* Wait until SPI Rx buffer not empty interrupt */ 258 | while (SpiRxNotEmpty == 0U) 259 | { 260 | /* Refresh IWDG: reload counter */ 261 | IWDG->KR = IWDG_KEY_RELOAD; 262 | } 263 | 264 | /* Reset the RX not empty token */ 265 | SpiRxNotEmpty = 0U; 266 | 267 | /* Transmit the busy byte */ 268 | *((__IO uint8_t *)&SPIx->DR) = SPI_BUSY_BYTE; 269 | 270 | /* Read bytes from the host to avoid the overrun */ 271 | OPENBL_SPI_ClearFlag_OVR(); 272 | 273 | /* Enable the interrupt of Rx not empty buffer */ 274 | SPIx->CR2 |= SPI_CR2_RXNEIE; 275 | } 276 | 277 | /** 278 | * @brief This function is used to send one byte through SPI pipe. 279 | * @retval None. 280 | */ 281 | #if defined (__ICCARM__) 282 | __ramfunc void OPENBL_SPI_SendByte(uint8_t Byte) 283 | #else 284 | __attribute__((section(".ramfunc"))) void OPENBL_SPI_SendByte(uint8_t Byte) 285 | #endif /* (__ICCARM__) */ 286 | { 287 | /* Wait until SPI transmit buffer is empty */ 288 | while ((SPIx->SR & SPI_SR_TXE) == 0U) 289 | {} 290 | 291 | /* Transmit the data */ 292 | *((__IO uint8_t *)&SPIx->DR) = Byte; 293 | } 294 | 295 | /** 296 | * @brief This function is used to send acknowledge byte through SPI pipe. 297 | * @retval None. 298 | */ 299 | void OPENBL_SPI_SendAcknowledgeByte(uint8_t Byte) 300 | { 301 | /* Check the AN4286 for the acknowledge procedure */ 302 | OPENBL_SPI_SendByte(SPI_DUMMY_BYTE); 303 | 304 | OPENBL_SPI_SendByte(Byte); 305 | 306 | /* Wait for the host to send ACK synchronization byte */ 307 | while (OPENBL_SPI_ReadByte() != ACK_BYTE) 308 | {} 309 | 310 | OPENBL_SPI_SendByte(SPI_DUMMY_BYTE); 311 | } 312 | 313 | /** 314 | * @brief Handle SPI interrupt request. 315 | * @retval None. 316 | */ 317 | #if defined (__ICCARM__) 318 | __ramfunc void OPENBL_SPI_IRQHandler(void) 319 | #else 320 | __attribute__((section(".ramfunc"))) void OPENBL_SPI_IRQHandler(void) 321 | #endif /* (__ICCARM__) */ 322 | { 323 | /* Check that SPI Rx buffer not empty interrupt has been raised */ 324 | if (((SPIx->SR & SPI_SR_OVR) == RESET) 325 | && ((SPIx->SR & SPI_SR_RXNE) != RESET) 326 | && ((SPIx->CR2 & SPI_CR2_RXNEIE) != RESET)) 327 | { 328 | if (BusyState == 0U) 329 | { 330 | /* Set the RX not empty token */ 331 | SpiRxNotEmpty = 1U; 332 | 333 | /* Disable the interrupt of Rx not empty buffer */ 334 | SPIx->CR2 &= ~ SPI_CR2_RXNEIE; 335 | } 336 | else 337 | { 338 | /* Set the RX not empty token */ 339 | SpiRxNotEmpty = 1U; 340 | 341 | /* Disable the interrupt of Rx not empty buffer */ 342 | SPIx->CR2 &= ~ SPI_CR2_RXNEIE; 343 | 344 | /* Send busy byte */ 345 | OPENBL_SPI_SendBusyByte(); 346 | } 347 | } 348 | 349 | while (((SPIx->SR & SPI_SR_OVR) != RESET) 350 | && ((SPIx->SR & SPI_SR_RXNE) != RESET) 351 | && ((SPIx->CR2 & SPI_CR2_RXNEIE) != RESET)) 352 | { 353 | /* Read bytes from the host to avoid the overrun */ 354 | OPENBL_SPI_ClearFlag_OVR(); 355 | } 356 | } 357 | 358 | /** 359 | * @brief This function enables the send of busy state. 360 | * @retval None. 361 | */ 362 | void OPENBL_SPI_EnableBusyState(void) 363 | { 364 | BusyState = 1U; 365 | } 366 | 367 | /** 368 | * @brief This function disables the send of busy state. 369 | * @retval None. 370 | */ 371 | void OPENBL_SPI_DisableBusyState(void) 372 | { 373 | BusyState = 0U; 374 | } 375 | 376 | /** 377 | * @brief Clear overrun error flag 378 | * @note Clearing this flag is done by a read access to the SPIx_DR 379 | * register followed by a read access to the SPIx_SR register 380 | * @retval None 381 | */ 382 | #if defined (__ICCARM__) 383 | __ramfunc void OPENBL_SPI_ClearFlag_OVR(void) 384 | #else 385 | __attribute__((section(".ramfunc"))) void OPENBL_SPI_ClearFlag_OVR(void) 386 | #endif /* (__ICCARM__) */ 387 | { 388 | __IO uint32_t tmpreg; 389 | 390 | tmpreg = SPIx->DR; 391 | (void) tmpreg; 392 | tmpreg = SPIx->SR; 393 | (void) tmpreg; 394 | } 395 | 396 | /** 397 | * @brief This function is used to process and execute the special commands. 398 | * The user must define the special commands routine here. 399 | * @param SpecialCmd Pointer to the OPENBL_SpecialCmdTypeDef structure. 400 | * @retval Returns NACK status in case of error else returns ACK status. 401 | */ 402 | void OPENBL_SPI_SpecialCommandProcess(OPENBL_SpecialCmdTypeDef *SpecialCmd) 403 | { 404 | switch (SpecialCmd->OpCode) 405 | { 406 | /* Unknown command opcode */ 407 | default: 408 | if (SpecialCmd->CmdType == OPENBL_SPECIAL_CMD) 409 | { 410 | /* Send NULL data size */ 411 | OPENBL_SPI_SendByte(0x00U); 412 | OPENBL_SPI_SendByte(0x00U); 413 | 414 | /* Send NULL status size */ 415 | OPENBL_SPI_SendByte(0x00U); 416 | OPENBL_SPI_SendByte(0x00U); 417 | } 418 | else if (SpecialCmd->CmdType == OPENBL_EXTENDED_SPECIAL_CMD) 419 | { 420 | /* Send NULL status size */ 421 | OPENBL_SPI_SendByte(0x00U); 422 | OPENBL_SPI_SendByte(0x00U); 423 | } 424 | break; 425 | } 426 | } 427 | -------------------------------------------------------------------------------- /Projects/NUCLEO-WL55JC/Applications/OpenBootloader/OpenBootloader/Target/spi_interface.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file spi_interface.h 4 | * @author MCD Application Team 5 | * @brief Header for spi_interface.c module 6 | ****************************************************************************** 7 | * @attention 8 | * 9 | * Copyright (c) 2022 STMicroelectronics. 10 | * All rights reserved. 11 | * 12 | * This software is licensed under terms that can be found in the LICENSE file 13 | * in the root directory of this software component. 14 | * If no LICENSE file comes with this software, it is provided AS-IS. 15 | * 16 | ****************************************************************************** 17 | */ 18 | 19 | /* Define to prevent recursive inclusion -------------------------------------*/ 20 | #ifndef SPI_INTERFACE_H 21 | #define SPI_INTERFACE_H 22 | 23 | #ifdef __cplusplus 24 | extern "C" { 25 | #endif 26 | 27 | /* Includes ------------------------------------------------------------------*/ 28 | #include 29 | #include "openbl_core.h" 30 | 31 | /* Exported types ------------------------------------------------------------*/ 32 | /* Exported constants --------------------------------------------------------*/ 33 | /* Exported macro ------------------------------------------------------------*/ 34 | /* Exported functions --------------------------------------------------------*/ 35 | void OPENBL_SPI_Configuration(void); 36 | void OPENBL_SPI_DeInit(void); 37 | uint8_t OPENBL_SPI_ProtocolDetection(void); 38 | uint8_t OPENBL_SPI_GetCommandOpcode(void); 39 | void OPENBL_SPI_SendAcknowledgeByte(uint8_t Byte); 40 | void OPENBL_SPI_SpecialCommandProcess(OPENBL_SpecialCmdTypeDef *Frame); 41 | 42 | void OPENBL_SPI_EnableBusyState(void); 43 | void OPENBL_SPI_DisableBusyState(void); 44 | 45 | #if defined (__ICCARM__) 46 | __ramfunc uint8_t OPENBL_SPI_ReadByte(void); 47 | __ramfunc void OPENBL_SPI_SendByte(uint8_t Byte); 48 | __ramfunc void OPENBL_SPI_IRQHandler(void); 49 | __ramfunc void OPENBL_SPI_SendBusyByte(void); 50 | #else 51 | __attribute__((section(".ramfunc"))) uint8_t OPENBL_SPI_ReadByte(void); 52 | __attribute__((section(".ramfunc"))) void OPENBL_SPI_SendByte(uint8_t Byte); 53 | __attribute__((section(".ramfunc"))) void OPENBL_SPI_IRQHandler(void); 54 | __attribute__((section(".ramfunc"))) void OPENBL_SPI_SendBusyByte(void); 55 | #endif /* (__ICCARM__) */ 56 | 57 | #ifdef __cplusplus 58 | } 59 | #endif 60 | 61 | #endif /* SPI_INTERFACE_H */ 62 | -------------------------------------------------------------------------------- /Projects/NUCLEO-WL55JC/Applications/OpenBootloader/OpenBootloader/Target/systemmemory_interface.c: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file systemmemory_interface.c 4 | * @author MCD Application Team 5 | * @brief Contains System Memory access functions 6 | ****************************************************************************** 7 | * @attention 8 | * 9 | * Copyright (c) 2022 STMicroelectronics. 10 | * All rights reserved. 11 | * 12 | * This software is licensed under terms that can be found in the LICENSE file 13 | * in the root directory of this software component. 14 | * If no LICENSE file comes with this software, it is provided AS-IS. 15 | * 16 | ****************************************************************************** 17 | */ 18 | 19 | /* Includes ------------------------------------------------------------------*/ 20 | #include "platform.h" 21 | #include "openbl_mem.h" 22 | #include "app_openbootloader.h" 23 | #include "common_interface.h" 24 | #include "systemmemory_interface.h" 25 | 26 | /* Private typedef -----------------------------------------------------------*/ 27 | /* Private define ------------------------------------------------------------*/ 28 | /* Private macro -------------------------------------------------------------*/ 29 | /* Private variables ---------------------------------------------------------*/ 30 | /* Private function prototypes -----------------------------------------------*/ 31 | /* Exported variables --------------------------------------------------------*/ 32 | OPENBL_MemoryTypeDef ICP1_Descriptor = 33 | { 34 | ICP1_START_ADDRESS, 35 | ICP1_END_ADDRESS, 36 | ICP1_SIZE, 37 | ICP_AREA, 38 | OPENBL_ICP_Read, 39 | NULL, 40 | NULL, 41 | NULL, 42 | NULL, 43 | NULL, 44 | NULL 45 | }; 46 | 47 | /* Exported functions --------------------------------------------------------*/ 48 | 49 | /** 50 | * @brief This function is used to read data from a given address. 51 | * @param Address The address to be read. 52 | * @retval Returns the read value. 53 | */ 54 | uint8_t OPENBL_ICP_Read(uint32_t Address) 55 | { 56 | return (*(uint8_t *)(Address)); 57 | } 58 | -------------------------------------------------------------------------------- /Projects/NUCLEO-WL55JC/Applications/OpenBootloader/OpenBootloader/Target/systemmemory_interface.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file systemmemory_interface.h 4 | * @author MCD Application Team 5 | * @brief Header for systemmemory_interface.c module 6 | ****************************************************************************** 7 | * @attention 8 | * 9 | * Copyright (c) 2022 STMicroelectronics. 10 | * All rights reserved. 11 | * 12 | * This software is licensed under terms that can be found in the LICENSE file 13 | * in the root directory of this software component. 14 | * If no LICENSE file comes with this software, it is provided AS-IS. 15 | * 16 | ****************************************************************************** 17 | */ 18 | 19 | /* Define to prevent recursive inclusion -------------------------------------*/ 20 | #ifndef SYSTEMMEMORY_INTERFACE_H 21 | #define SYSTEMMEMORY_INTERFACE_H 22 | 23 | #ifdef __cplusplus 24 | extern "C" { 25 | #endif 26 | 27 | /* Includes ------------------------------------------------------------------*/ 28 | /* Exported types ------------------------------------------------------------*/ 29 | /* Exported constants --------------------------------------------------------*/ 30 | /* Exported macro ------------------------------------------------------------*/ 31 | /* Exported functions ------------------------------------------------------- */ 32 | uint8_t OPENBL_ICP_Read(uint32_t Address); 33 | 34 | #ifdef __cplusplus 35 | } 36 | #endif 37 | 38 | #endif /* SYSTEMMEMORY_INTERFACE_H */ 39 | -------------------------------------------------------------------------------- /Projects/NUCLEO-WL55JC/Applications/OpenBootloader/OpenBootloader/Target/usart_interface.c: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file usart_interface.c 4 | * @author MCD Application Team 5 | * @brief Contains USART HW configuration 6 | ****************************************************************************** 7 | * @attention 8 | * 9 | * Copyright (c) 2022 STMicroelectronics. 10 | * All rights reserved. 11 | * 12 | * This software is licensed under terms that can be found in the LICENSE file 13 | * in the root directory of this software component. 14 | * If no LICENSE file comes with this software, it is provided AS-IS. 15 | * 16 | ****************************************************************************** 17 | */ 18 | 19 | /* Includes ------------------------------------------------------------------*/ 20 | #include "platform.h" 21 | #include "openbl_core.h" 22 | #include "openbl_usart_cmd.h" 23 | #include "usart_interface.h" 24 | #include "iwdg_interface.h" 25 | #include "interfaces_conf.h" 26 | 27 | /* Private typedef -----------------------------------------------------------*/ 28 | /* Private define ------------------------------------------------------------*/ 29 | /* Private macro -------------------------------------------------------------*/ 30 | /* Private variables ---------------------------------------------------------*/ 31 | static uint8_t UsartDetected = 0U; 32 | 33 | /* Exported variables --------------------------------------------------------*/ 34 | /* Private function prototypes -----------------------------------------------*/ 35 | static void OPENBL_USART_Init(void); 36 | 37 | /* Private functions ---------------------------------------------------------*/ 38 | 39 | /** 40 | * @brief This function is used to initialize the used USART instance. 41 | * @retval None. 42 | */ 43 | static void OPENBL_USART_Init(void) 44 | { 45 | LL_USART_InitTypeDef USART_InitStruct; 46 | 47 | USART_InitStruct.PrescalerValue = LL_USART_PRESCALER_DIV1; 48 | USART_InitStruct.BaudRate = 115200U; 49 | USART_InitStruct.DataWidth = LL_USART_DATAWIDTH_9B; 50 | USART_InitStruct.StopBits = LL_USART_STOPBITS_1; 51 | USART_InitStruct.Parity = LL_USART_PARITY_EVEN; 52 | USART_InitStruct.HardwareFlowControl = LL_USART_HWCONTROL_NONE; 53 | USART_InitStruct.TransferDirection = LL_USART_DIRECTION_TX_RX; 54 | USART_InitStruct.OverSampling = LL_USART_OVERSAMPLING_16; 55 | 56 | if (IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx)) 57 | { 58 | LL_USART_EnableAutoBaudRate(USARTx); 59 | LL_USART_SetAutoBaudRateMode(USARTx, LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME); 60 | } 61 | else 62 | { 63 | LL_USART_DisableAutoBaudRate(USARTx); 64 | USART_InitStruct.BaudRate = 115200U; 65 | } 66 | 67 | LL_USART_Init(USARTx, &USART_InitStruct); 68 | LL_USART_Enable(USARTx); 69 | } 70 | 71 | /* Exported functions --------------------------------------------------------*/ 72 | 73 | /** 74 | * @brief This function is used to configure USART pins and then initialize the used USART instance. 75 | * @retval None. 76 | */ 77 | void OPENBL_USART_Configuration(void) 78 | { 79 | GPIO_InitTypeDef GPIO_InitStruct; 80 | 81 | /* Enable all resources clocks --------------------------------------------*/ 82 | /* Enable used GPIOx clocks */ 83 | USARTx_GPIO_CLK_TX_ENABLE(); 84 | USARTx_GPIO_CLK_RX_ENABLE(); 85 | 86 | /* Enable USART clock */ 87 | USARTx_CLK_ENABLE(); 88 | 89 | /* USARTx pins configuration -----------------------------------------------*/ 90 | /* 91 | +-------------+ 92 | | USART1 | 93 | +-----+-------------+ 94 | | TX | PA9 | 95 | +-----+-------------+ 96 | | RX | PA10 | 97 | +-----+-------------+ */ 98 | GPIO_InitStruct.Pin = USARTx_TX_PIN; 99 | GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 100 | GPIO_InitStruct.Pull = GPIO_PULLUP; 101 | GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 102 | GPIO_InitStruct.Alternate = USARTx_ALTERNATE; 103 | HAL_GPIO_Init(USARTx_TX_GPIO_PORT, &GPIO_InitStruct); 104 | 105 | GPIO_InitStruct.Pin = USARTx_RX_PIN; 106 | HAL_GPIO_Init(USARTx_RX_GPIO_PORT, &GPIO_InitStruct); 107 | 108 | OPENBL_USART_Init(); 109 | } 110 | 111 | /** 112 | * @brief This function is used to De-initialize the USART pins and instance. 113 | * @retval None. 114 | */ 115 | void OPENBL_USART_DeInit(void) 116 | { 117 | /* Only de-initialize the USART if it is not the current detected interface */ 118 | if (UsartDetected == 0U) 119 | { 120 | LL_USART_Disable(USARTx); 121 | 122 | USARTx_CLK_DISABLE(); 123 | } 124 | } 125 | 126 | /** 127 | * @brief This function is used to detect if there is any activity on USART protocol. 128 | * @retval Returns 1 if interface is detected else 0. 129 | */ 130 | uint8_t OPENBL_USART_ProtocolDetection(void) 131 | { 132 | /* Check if the USARTx is addressed */ 133 | if (((USARTx->ISR & LL_USART_ISR_ABRF) != 0) && ((USARTx->ISR & LL_USART_ISR_ABRE) == 0)) 134 | { 135 | /* Read byte in order to flush the 0x7F synchronization byte */ 136 | OPENBL_USART_ReadByte(); 137 | 138 | /* Acknowledge the host */ 139 | OPENBL_USART_SendByte(ACK_BYTE); 140 | 141 | UsartDetected = 1U; 142 | } 143 | else 144 | { 145 | UsartDetected = 0U; 146 | } 147 | 148 | return UsartDetected; 149 | } 150 | 151 | /** 152 | * @brief This function is used to get the command opcode from the host. 153 | * @retval Returns the command. 154 | */ 155 | uint8_t OPENBL_USART_GetCommandOpcode(void) 156 | { 157 | uint8_t command_opc; 158 | 159 | /* Get the command opcode */ 160 | command_opc = OPENBL_USART_ReadByte(); 161 | 162 | /* Check the data integrity */ 163 | if ((command_opc ^ OPENBL_USART_ReadByte()) != 0xFFU) 164 | { 165 | command_opc = ERROR_COMMAND; 166 | } 167 | 168 | return command_opc; 169 | } 170 | 171 | /** 172 | * @brief This function is used to read one byte from USART pipe. 173 | * @retval Returns the read byte. 174 | */ 175 | uint8_t OPENBL_USART_ReadByte(void) 176 | { 177 | while (!LL_USART_IsActiveFlag_RXNE(USARTx)) 178 | { 179 | OPENBL_IWDG_Refresh(); 180 | } 181 | 182 | return LL_USART_ReceiveData8(USARTx); 183 | } 184 | 185 | /** 186 | * @brief This function is used to send one byte through USART pipe. 187 | * @param Byte The byte to be sent. 188 | * @retval None. 189 | */ 190 | void OPENBL_USART_SendByte(uint8_t Byte) 191 | { 192 | LL_USART_TransmitData8(USARTx, (Byte & 0xFFU)); 193 | 194 | while (!LL_USART_IsActiveFlag_TC(USARTx)) 195 | { 196 | } 197 | } 198 | 199 | /** 200 | * @brief This function is used to process and execute the special commands. 201 | * The user must define the special commands routine here. 202 | * @param SpecialCmd Pointer to the OPENBL_SpecialCmdTypeDef structure. 203 | * @retval Returns NACK status in case of error else returns ACK status. 204 | */ 205 | void OPENBL_USART_SpecialCommandProcess(OPENBL_SpecialCmdTypeDef *SpecialCmd) 206 | { 207 | switch (SpecialCmd->OpCode) 208 | { 209 | /* Unknown command opcode */ 210 | default: 211 | if (SpecialCmd->CmdType == OPENBL_SPECIAL_CMD) 212 | { 213 | /* Send NULL data size */ 214 | OPENBL_USART_SendByte(0x00U); 215 | OPENBL_USART_SendByte(0x00U); 216 | 217 | /* Send NULL status size */ 218 | OPENBL_USART_SendByte(0x00U); 219 | OPENBL_USART_SendByte(0x00U); 220 | } 221 | else if (SpecialCmd->CmdType == OPENBL_EXTENDED_SPECIAL_CMD) 222 | { 223 | /* Send NULL status size */ 224 | OPENBL_USART_SendByte(0x00U); 225 | OPENBL_USART_SendByte(0x00U); 226 | } 227 | break; 228 | } 229 | } 230 | -------------------------------------------------------------------------------- /Projects/NUCLEO-WL55JC/Applications/OpenBootloader/OpenBootloader/Target/usart_interface.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file usart_interface.h 4 | * @author MCD Application Team 5 | * @brief Header for usart_interface.c module 6 | ****************************************************************************** 7 | * @attention 8 | * 9 | * Copyright (c) 2022 STMicroelectronics. 10 | * All rights reserved. 11 | * 12 | * This software is licensed under terms that can be found in the LICENSE file 13 | * in the root directory of this software component. 14 | * If no LICENSE file comes with this software, it is provided AS-IS. 15 | * 16 | ****************************************************************************** 17 | */ 18 | 19 | /* Define to prevent recursive inclusion -------------------------------------*/ 20 | #ifndef USART_INTERFACE_H 21 | #define USART_INTERFACE_H 22 | 23 | #ifdef __cplusplus 24 | extern "C" { 25 | #endif 26 | 27 | /* Includes ------------------------------------------------------------------*/ 28 | #include 29 | #include "openbl_core.h" 30 | 31 | /* Exported types ------------------------------------------------------------*/ 32 | /* Exported constants --------------------------------------------------------*/ 33 | /* Exported macro ------------------------------------------------------------*/ 34 | /* Exported functions ------------------------------------------------------- */ 35 | void OPENBL_USART_Configuration(void); 36 | void OPENBL_USART_DeInit(void); 37 | uint8_t OPENBL_USART_ProtocolDetection(void); 38 | uint8_t OPENBL_USART_GetCommandOpcode(void); 39 | uint8_t OPENBL_USART_ReadByte(void); 40 | void OPENBL_USART_SendByte(uint8_t Byte); 41 | void OPENBL_USART_SpecialCommandProcess(OPENBL_SpecialCmdTypeDef *Frame); 42 | 43 | #ifdef __cplusplus 44 | } 45 | #endif 46 | 47 | #endif /* USART_INTERFACE_H */ 48 | -------------------------------------------------------------------------------- /Projects/NUCLEO-WL55JC/Applications/OpenBootloader/README.md: -------------------------------------------------------------------------------- 1 | ## Open Bootloader Application Description 2 | 3 | This application exploits Open Bootloader Middleware to demonstrate how to develop an IAP application 4 | and how use it. 5 | 6 | At the beginning of the main program the HAL_Init() function is called to reset 7 | all the peripherals, initialize the Flash interface and the Systick. 8 | The SystemClock_Config() function is used to configure the system clock (SYSCLK) 9 | to run at 48MHz. 10 | 11 | Then, these protocols and memories interfaces are configured: 12 | - USART1 13 | - SPI1 14 | - FLASH interface 15 | - RAM interface 16 | - Option bytes interface 17 | - System memory interface 18 | - OTP interface 19 | - Engineering bytes interface 20 | 21 | Then, the Open Bootloader application will wait for incoming communication on one of the supported protocols. 22 | 23 | Once a communication is established through one of the supported protocols, 24 | the Open Bootloader application will wait for commands sent by the host. 25 | 26 | #### Notes 27 | 28 | 1. In case of Mass Erase operation, the Open Bootloader FLASH area must be protected otherwise the Open Bootloader 29 | will be erased. 30 | 31 | 2. In the `OpenBootloader_Init()` function in `app_openbootloader.c` file, the user can: 32 | - Select the list of supported commands for a specific interface by defining its own list of commands. 33 | 34 | Here is an example of how to customize USART interface commands list, here only read/write commands are supported: 35 | 36 | OPENBL_CommandsTypeDef USART_Cmd = 37 | { 38 | NULL, 39 | NULL, 40 | NULL, 41 | OPENBL_USART_ReadMemory, 42 | OPENBL_USART_WriteMemory, 43 | NULL, 44 | NULL, 45 | NULL, 46 | NULL, 47 | NULL, 48 | NULL, 49 | NULL, 50 | NULL, 51 | NULL, 52 | NULL, 53 | NULL, 54 | NULL, 55 | NULL, 56 | NULL, 57 | NULL 58 | }; 59 | 60 | USART_Handle.p_Ops = &USART_Ops; 61 | USART_Handle.p_Cmd = &USART_Cmd; /* Initialize the USART handle with the list of supported commands */ 62 | OPENBL_USART_SetCommandsList(&USART_Cmd); /* Register the list of supported commands in MW side */ 63 | 64 | - Use the default list of supported commands for a specific interface by reusing the commands list defined in MW side. 65 | 66 | Here is an example of how to use USART interface default commands list: 67 | 68 | /* Register USART interfaces */ 69 | USART_Handle.p_Ops = &USART_Ops; 70 | USART_Handle.p_Cmd = OPENBL_USART_GetCommandsList(); /* Initialize the USART handle with the default list of supported commands */ 71 | 72 | ### Keywords 73 | 74 | Open Bootloader, USART, SPI 75 | 76 | ### Directory contents 77 | 78 | - Core/Src/main.c Main program file 79 | - Core/Src/stm32wlxx_hal_msp.c MSP Initialization file 80 | - Core/Src/stm32wlxx_it.c Interrupt handlers file 81 | - Core/Src/system_stm32wlxx.c STM32WLxx system clock configuration file 82 | - Core/Inc/main.h Main program header file 83 | - Core/Inc/stm32wlxx_hal_conf.h HAL Library Configuration file 84 | - Core/Inc/stm32wlxx_it.h Interrupt handlers header file 85 | - OpenBootloader/App/app_openbootloader.c Open Bootloader application entry point 86 | - OpenBootloader/App/app_openbootloader.h Header for Open Bootloader application entry file 87 | - OpenBootloader/Target/common_interface.c Contains common functions used by different interfaces 88 | - OpenBootloader/Target/common_interface.h Header for common functions file 89 | - OpenBootloader/Target/engibytes_interface.c Contains Engibytes interface 90 | - OpenBootloader/Target/engibytes_interface.h Header for Engibytes functions file 91 | - OpenBootloader/Target/flash_interface.c Contains FLASH interface 92 | - OpenBootloader/Target/flash_interface.h Header of FLASH interface file 93 | - OpenBootloader/Target/iwdg_interface.c Contains IWDG interface 94 | - OpenBootloader/Target/iwdg_interface.h Header of IWDG interface file 95 | - OpenBootloader/Target/optionbytes_interface.c Contains OptionBytes interface 96 | - OpenBootloader/Target/optionbytes_interface.h Header of OptionBytes interface file 97 | - OpenBootloader/Target/openbootloader_conf.h Header file that contains Open Bootloader HW dependent configuration 98 | - OpenBootloader/Target/otp_interface.c Contains OTP interface 99 | - OpenBootloader/Target/otp_interface.h Header of OTP interface file 100 | - OpenBootloader/Target/ram_interface.c Contains RAM interface 101 | - OpenBootloader/Target/ram_interface.h Header of RAM interface file 102 | - OpenBootloader/Target/spi_interface.c Contains SPI interface 103 | - OpenBootloader/Target/spi_interface.h Header of SPI interface file 104 | - OpenBootloader/Target/systemmemory_interface.c Contains ICP interface 105 | - OpenBootloader/Target/systemmemory_interface.h Header of ICP interface file 106 | - OpenBootloader/Target/usart_interface.c Contains USART interface 107 | - OpenBootloader/Target/usart_interface.h Header of USART interface file 108 | 109 | ### Hardware and Software environment 110 | 111 | - This application runs on STM32WL55xx devices. 112 | 113 | - This example has been tested with a NUCLEO-WL55JC RevC board and can be 114 | easily tailored to any other supported device and development board. 115 | 116 | - NUCLEO-WL55JC RevC set-up to use USART: 117 | - To use the USART1 for communication you have to connect: 118 | - Tx pin of your host adapter to PA9 pin (CN5: 2)(D9) 119 | - Rx pin of your host adapter to PA10 pin (CN8: 3)(A2) 120 | 121 | - NUCLEO-WL55JC RevC set-up to use SPI 122 | - To use the SPI1 for communication you have to connect: 123 | - SCK pin of your host adapter to PA5 pin (CN5: 6)(D13) 124 | - MISO pin of your host adapter to PA6 pin (CN5: 5)(D12) 125 | - MOSI pin of your host adapter to PA7 pin (CN5: 4)(D11) 126 | - NSS pin of your host adapter to PA4 pin (CN5: 3)(D10) 127 | 128 | ### How to use it ? 129 | 130 | In order to make the program work, you must do the following: 131 | 132 | - Open your preferred toolchain using the adequate version 133 | - Rebuild all files and load your image into target memory 134 | - Run the application 135 | - Run STM32CubeProgrammer and connect to Open Bootloader using USART1
136 | Or 137 | - Connect your SPI host adapter and connect to Open Bootloader using SPI1
138 | -------------------------------------------------------------------------------- /Projects/NUCLEO-WL55JC/Applications/OpenBootloader/STM32CubeIDE/.project: -------------------------------------------------------------------------------- 1 | 2 | 3 | OpenBootloader 4 | 5 | 6 | 7 | 8 | 9 | org.eclipse.cdt.managedbuilder.core.genmakebuilder 10 | clean,full,incremental, 11 | 12 | 13 | 14 | 15 | org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder 16 | full,incremental, 17 | 18 | 19 | 20 | 21 | 22 | com.st.stm32cube.ide.mcu.MCUProjectNature 23 | org.eclipse.cdt.core.cnature 24 | com.st.stm32cube.ide.mcu.MCUCubeIdeServicesRevAev2ProjectNature 25 | com.st.stm32cube.ide.mcu.MCUNonUnderRootProjectNature 26 | com.st.stm32cube.ide.mcu.MCUCubeExampleProjectNature 27 | com.st.stm32cube.ide.mcu.MCUEndUserDisabledMultiCpuProjectNature 28 | com.st.stm32cube.ide.mcu.MCUMultiCpuProjectNature 29 | com.st.stm32cube.ide.mcu.MCURootProjectNature 30 | org.eclipse.cdt.managedbuilder.core.managedBuildNature 31 | org.eclipse.cdt.managedbuilder.core.ScannerConfigNature 32 | 33 | 34 | 35 | Doc/README.md 36 | 1 37 | PARENT-1-PROJECT_LOC/README.md 38 | 39 | 40 | Application/Core/main.c 41 | 1 42 | PARENT-1-PROJECT_LOC/Core/Src/main.c 43 | 44 | 45 | Application/Core/stm32wlxx_it.c 46 | 1 47 | PARENT-1-PROJECT_LOC/Core/Src/stm32wlxx_it.c 48 | 49 | 50 | Drivers/CMSIS/system_stm32wlxx.c 51 | 1 52 | PARENT-1-PROJECT_LOC/Core/Src/system_stm32wlxx.c 53 | 54 | 55 | Drivers/STM32WLxx_HAL_Driver/stm32wlxx_hal.c 56 | 1 57 | PARENT-5-PROJECT_LOC/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.c 58 | 59 | 60 | Drivers/STM32WLxx_HAL_Driver/stm32wlxx_hal_cortex.c 61 | 1 62 | PARENT-5-PROJECT_LOC/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.c 63 | 64 | 65 | Drivers/STM32WLxx_HAL_Driver/stm32wlxx_hal_dma.c 66 | 1 67 | PARENT-5-PROJECT_LOC/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma.c 68 | 69 | 70 | Drivers/STM32WLxx_HAL_Driver/stm32wlxx_hal_dma_ex.c 71 | 1 72 | PARENT-5-PROJECT_LOC/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma_ex.c 73 | 74 | 75 | Drivers/STM32WLxx_HAL_Driver/stm32wlxx_hal_exti.c 76 | 1 77 | PARENT-5-PROJECT_LOC/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_exti.c 78 | 79 | 80 | Drivers/STM32WLxx_HAL_Driver/stm32wlxx_hal_flash.c 81 | 1 82 | PARENT-5-PROJECT_LOC/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash.c 83 | 84 | 85 | Drivers/STM32WLxx_HAL_Driver/stm32wlxx_hal_flash_ex.c 86 | 1 87 | PARENT-5-PROJECT_LOC/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.c 88 | 89 | 90 | Drivers/STM32WLxx_HAL_Driver/stm32wlxx_hal_gpio.c 91 | 1 92 | PARENT-5-PROJECT_LOC/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_gpio.c 93 | 94 | 95 | Drivers/STM32WLxx_HAL_Driver/stm32wlxx_hal_iwdg.c 96 | 1 97 | PARENT-5-PROJECT_LOC/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_iwdg.c 98 | 99 | 100 | Drivers/STM32WLxx_HAL_Driver/stm32wlxx_hal_pwr.c 101 | 1 102 | PARENT-5-PROJECT_LOC/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr.c 103 | 104 | 105 | Drivers/STM32WLxx_HAL_Driver/stm32wlxx_hal_pwr_ex.c 106 | 1 107 | PARENT-5-PROJECT_LOC/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c 108 | 109 | 110 | Drivers/STM32WLxx_HAL_Driver/stm32wlxx_hal_rcc.c 111 | 1 112 | PARENT-5-PROJECT_LOC/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc.c 113 | 114 | 115 | Drivers/STM32WLxx_HAL_Driver/stm32wlxx_hal_rcc_ex.c 116 | 1 117 | PARENT-5-PROJECT_LOC/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc_ex.c 118 | 119 | 120 | Drivers/STM32WLxx_HAL_Driver/stm32wlxx_hal_spi.c 121 | 1 122 | PARENT-5-PROJECT_LOC/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_spi.c 123 | 124 | 125 | Drivers/STM32WLxx_HAL_Driver/stm32wlxx_hal_spi_ex.c 126 | 1 127 | PARENT-5-PROJECT_LOC/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_spi_ex.c 128 | 129 | 130 | Drivers/STM32WLxx_HAL_Driver/stm32wlxx_hal_usart.c 131 | 1 132 | PARENT-5-PROJECT_LOC/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_usart.c 133 | 134 | 135 | Drivers/STM32WLxx_HAL_Driver/stm32wlxx_hal_usart_ex.c 136 | 1 137 | PARENT-5-PROJECT_LOC/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_usart_ex.c 138 | 139 | 140 | Drivers/STM32WLxx_HAL_Driver/stm32wlxx_ll_gpio.c 141 | 1 142 | PARENT-5-PROJECT_LOC/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_ll_gpio.c 143 | 144 | 145 | Drivers/STM32WLxx_HAL_Driver/stm32wlxx_ll_rcc.c 146 | 1 147 | PARENT-5-PROJECT_LOC/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_ll_rcc.c 148 | 149 | 150 | Drivers/STM32WLxx_HAL_Driver/stm32wlxx_ll_spi.c 151 | 1 152 | PARENT-5-PROJECT_LOC/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_ll_spi.c 153 | 154 | 155 | Drivers/STM32WLxx_HAL_Driver/stm32wlxx_ll_usart.c 156 | 1 157 | PARENT-5-PROJECT_LOC/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_ll_usart.c 158 | 159 | 160 | Middlewares/Core/openbl_core.c 161 | 1 162 | PARENT-5-PROJECT_LOC/Middlewares/ST/OpenBootloader/Core/openbl_core.c 163 | 164 | 165 | Application/OpenBootloader/App/app_openbootloader.c 166 | 1 167 | PARENT-1-PROJECT_LOC/OpenBootloader/App/app_openbootloader.c 168 | 169 | 170 | Application/OpenBootloader/Target/common_interface.c 171 | 1 172 | PARENT-1-PROJECT_LOC/OpenBootloader/Target/common_interface.c 173 | 174 | 175 | Application/OpenBootloader/Target/engibytes_interface.c 176 | 1 177 | PARENT-1-PROJECT_LOC/OpenBootloader/Target/engibytes_interface.c 178 | 179 | 180 | Application/OpenBootloader/Target/flash_interface.c 181 | 1 182 | PARENT-1-PROJECT_LOC/OpenBootloader/Target/flash_interface.c 183 | 184 | 185 | Application/OpenBootloader/Target/iwdg_interface.c 186 | 1 187 | PARENT-1-PROJECT_LOC/OpenBootloader/Target/iwdg_interface.c 188 | 189 | 190 | Application/OpenBootloader/Target/optionbytes_interface.c 191 | 1 192 | PARENT-1-PROJECT_LOC/OpenBootloader/Target/optionbytes_interface.c 193 | 194 | 195 | Application/OpenBootloader/Target/otp_interface.c 196 | 1 197 | PARENT-1-PROJECT_LOC/OpenBootloader/Target/otp_interface.c 198 | 199 | 200 | Application/OpenBootloader/Target/ram_interface.c 201 | 1 202 | PARENT-1-PROJECT_LOC/OpenBootloader/Target/ram_interface.c 203 | 204 | 205 | Application/OpenBootloader/Target/spi_interface.c 206 | 1 207 | PARENT-1-PROJECT_LOC/OpenBootloader/Target/spi_interface.c 208 | 209 | 210 | Application/OpenBootloader/Target/systemmemory_interface.c 211 | 1 212 | PARENT-1-PROJECT_LOC/OpenBootloader/Target/systemmemory_interface.c 213 | 214 | 215 | Application/OpenBootloader/Target/usart_interface.c 216 | 1 217 | PARENT-1-PROJECT_LOC/OpenBootloader/Target/usart_interface.c 218 | 219 | 220 | Middlewares/Modules/MEM/openbl_mem.c 221 | 1 222 | PARENT-5-PROJECT_LOC/Middlewares/ST/OpenBootloader/Modules/Mem/openbl_mem.c 223 | 224 | 225 | Middlewares/Modules/SPI/openbl_spi_cmd.c 226 | 1 227 | PARENT-5-PROJECT_LOC/Middlewares/ST/OpenBootloader/Modules/SPI/openbl_spi_cmd.c 228 | 229 | 230 | Middlewares/Modules/USART/openbl_usart_cmd.c 231 | 1 232 | PARENT-5-PROJECT_LOC/Middlewares/ST/OpenBootloader/Modules/USART/openbl_usart_cmd.c 233 | 234 | 235 | 236 | -------------------------------------------------------------------------------- /Projects/NUCLEO-WL55JC/Applications/OpenBootloader/STM32CubeIDE/Application/Core/syscalls.c: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file syscalls.c 4 | * @author Auto-generated by STM32CubeIDE 5 | * @brief STM32CubeIDE Minimal System calls file 6 | * 7 | * For more information about which c-functions 8 | * need which of these lowlevel functions 9 | * please consult the Newlib libc-manual 10 | ****************************************************************************** 11 | * @attention 12 | * 13 | * Copyright (c) 2022 STMicroelectronics. 14 | * All rights reserved. 15 | * 16 | * This software is licensed under terms that can be found in the LICENSE file 17 | * in the root directory of this software component. 18 | * If no LICENSE file comes with this software, it is provided AS-IS. 19 | * 20 | ****************************************************************************** 21 | */ 22 | 23 | /* Includes */ 24 | #include 25 | #include 26 | #include 27 | #include 28 | #include 29 | #include 30 | #include 31 | #include 32 | 33 | 34 | /* Variables */ 35 | extern int __io_putchar(int ch) __attribute__((weak)); 36 | extern int __io_getchar(void) __attribute__((weak)); 37 | 38 | 39 | char *__env[1] = { 0 }; 40 | char **environ = __env; 41 | 42 | 43 | /* Functions */ 44 | void initialise_monitor_handles() 45 | { 46 | } 47 | 48 | int _getpid(void) 49 | { 50 | return 1; 51 | } 52 | 53 | int _kill(int pid, int sig) 54 | { 55 | errno = EINVAL; 56 | return -1; 57 | } 58 | 59 | void _exit (int status) 60 | { 61 | _kill(status, -1); 62 | while (1) {} /* Make sure we hang here */ 63 | } 64 | 65 | __attribute__((weak)) int _read(int file, char *ptr, int len) 66 | { 67 | int DataIdx; 68 | 69 | for (DataIdx = 0; DataIdx < len; DataIdx++) 70 | { 71 | *ptr++ = __io_getchar(); 72 | } 73 | 74 | return len; 75 | } 76 | 77 | __attribute__((weak)) int _write(int file, char *ptr, int len) 78 | { 79 | int DataIdx; 80 | 81 | for (DataIdx = 0; DataIdx < len; DataIdx++) 82 | { 83 | __io_putchar(*ptr++); 84 | } 85 | return len; 86 | } 87 | 88 | int _close(int file) 89 | { 90 | return -1; 91 | } 92 | 93 | 94 | int _fstat(int file, struct stat *st) 95 | { 96 | st->st_mode = S_IFCHR; 97 | return 0; 98 | } 99 | 100 | int _isatty(int file) 101 | { 102 | return 1; 103 | } 104 | 105 | int _lseek(int file, int ptr, int dir) 106 | { 107 | return 0; 108 | } 109 | 110 | int _open(char *path, int flags, ...) 111 | { 112 | /* Pretend like we always fail */ 113 | return -1; 114 | } 115 | 116 | int _wait(int *status) 117 | { 118 | errno = ECHILD; 119 | return -1; 120 | } 121 | 122 | int _unlink(char *name) 123 | { 124 | errno = ENOENT; 125 | return -1; 126 | } 127 | 128 | int _times(struct tms *buf) 129 | { 130 | return -1; 131 | } 132 | 133 | int _stat(char *file, struct stat *st) 134 | { 135 | st->st_mode = S_IFCHR; 136 | return 0; 137 | } 138 | 139 | int _link(char *old, char *new) 140 | { 141 | errno = EMLINK; 142 | return -1; 143 | } 144 | 145 | int _fork(void) 146 | { 147 | errno = EAGAIN; 148 | return -1; 149 | } 150 | 151 | int _execve(char *name, char **argv, char **env) 152 | { 153 | errno = ENOMEM; 154 | return -1; 155 | } 156 | -------------------------------------------------------------------------------- /Projects/NUCLEO-WL55JC/Applications/OpenBootloader/STM32CubeIDE/Application/Core/sysmem.c: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file sysmem.c 4 | * @author Generated by STM32CubeIDE 5 | * @brief STM32CubeIDE System Memory calls file 6 | * 7 | * For more information about which C functions 8 | * need which of these lowlevel functions 9 | * please consult the newlib libc manual 10 | ****************************************************************************** 11 | * @attention 12 | * 13 | * Copyright (c) 2022 STMicroelectronics. 14 | * All rights reserved. 15 | * 16 | * This software is licensed under terms that can be found in the LICENSE file 17 | * in the root directory of this software component. 18 | * If no LICENSE file comes with this software, it is provided AS-IS. 19 | * 20 | ****************************************************************************** 21 | */ 22 | 23 | /* Includes */ 24 | #include 25 | #include 26 | 27 | /** 28 | * Pointer to the current high watermark of the heap usage 29 | */ 30 | static uint8_t *__sbrk_heap_end = NULL; 31 | 32 | /** 33 | * @brief _sbrk() allocates memory to the newlib heap and is used by malloc 34 | * and others from the C library 35 | * 36 | * @verbatim 37 | * ############################################################################ 38 | * # .data # .bss # newlib heap # MSP stack # 39 | * # # # # Reserved by _Min_Stack_Size # 40 | * ############################################################################ 41 | * ^-- RAM start ^-- _end _estack, RAM end --^ 42 | * @endverbatim 43 | * 44 | * This implementation starts allocating at the '_end' linker symbol 45 | * The '_Min_Stack_Size' linker symbol reserves a memory for the MSP stack 46 | * The implementation considers '_estack' linker symbol to be RAM end 47 | * NOTE: If the MSP stack, at any point during execution, grows larger than the 48 | * reserved size, please increase the '_Min_Stack_Size'. 49 | * 50 | * @param incr Memory size 51 | * @return Pointer to allocated memory 52 | */ 53 | void *_sbrk(ptrdiff_t incr) 54 | { 55 | extern uint8_t _end; /* Symbol defined in the linker script */ 56 | extern uint8_t _estack; /* Symbol defined in the linker script */ 57 | extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */ 58 | const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size; 59 | const uint8_t *max_heap = (uint8_t *)stack_limit; 60 | uint8_t *prev_heap_end; 61 | 62 | /* Initialize heap end at first call */ 63 | if (NULL == __sbrk_heap_end) 64 | { 65 | __sbrk_heap_end = &_end; 66 | } 67 | 68 | /* Protect heap from growing into the reserved MSP stack */ 69 | if (__sbrk_heap_end + incr > max_heap) 70 | { 71 | errno = ENOMEM; 72 | return (void *)-1; 73 | } 74 | 75 | prev_heap_end = __sbrk_heap_end; 76 | __sbrk_heap_end += incr; 77 | 78 | return (void *)prev_heap_end; 79 | } 80 | -------------------------------------------------------------------------------- /Projects/NUCLEO-WL55JC/Applications/OpenBootloader/STM32CubeIDE/STM32WL55JCIX_FLASH.ld: -------------------------------------------------------------------------------- 1 | /* 2 | ** LinkerScript 3 | ** Note: For specific memory allocation, linker and startup files must be customized. 4 | ** Refer to STM32CubeIDE user guide (UM2609), chapter "Modify the linker script". 5 | */ 6 | 7 | /* Entry Point */ 8 | ENTRY(Reset_Handler) 9 | 10 | /* Highest address of the user mode stack */ 11 | _estack = ORIGIN(RAM1) + LENGTH(RAM1); /* end of "SRAM1" Ram type memory */ 12 | 13 | _Min_Heap_Size = 0x200 ; /* required amount of heap */ 14 | _Min_Stack_Size = 0x400 ; /* required amount of stack */ 15 | 16 | /* Memories definition */ 17 | MEMORY 18 | { 19 | ROM (rx) : ORIGIN = 0x08000000, LENGTH = 28K /* Flash memory dedicated to CM4 */ 20 | RAM1 (xrw) : ORIGIN = 0x20000000, LENGTH = 6K /* Non-backup SRAM1 dedicated to CM4 */ 21 | RAM2 (xrw) : ORIGIN = 0x20008000, LENGTH = 6K /* Backup SRAM2 dedicated to CM4 */ 22 | } 23 | 24 | /* Sections */ 25 | SECTIONS 26 | { 27 | /* The startup code into "ROM" Rom type memory */ 28 | .isr_vector : 29 | { 30 | . = ALIGN(8); 31 | KEEP(*(.isr_vector)) /* Startup code */ 32 | . = ALIGN(8); 33 | } >ROM 34 | 35 | /* The program code and other data into "ROM" Rom type memory */ 36 | .text : 37 | { 38 | . = ALIGN(8); 39 | *(.text) /* .text sections (code) */ 40 | *(.text*) /* .text* sections (code) */ 41 | *(.glue_7) /* glue arm to thumb code */ 42 | *(.glue_7t) /* glue thumb to arm code */ 43 | *(.eh_frame) 44 | 45 | KEEP (*(.init)) 46 | KEEP (*(.fini)) 47 | 48 | . = ALIGN(8); 49 | _etext = .; /* define a global symbols at end of code */ 50 | } >ROM 51 | 52 | /* Constant data into "ROM" Rom type memory */ 53 | .rodata : 54 | { 55 | . = ALIGN(8); 56 | *(.rodata) /* .rodata sections (constants, strings, etc.) */ 57 | *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ 58 | . = ALIGN(8); 59 | } >ROM 60 | 61 | .ARM.extab : { 62 | . = ALIGN(8); 63 | *(.ARM.extab* .gnu.linkonce.armextab.*) 64 | . = ALIGN(8); 65 | } >ROM 66 | 67 | .ARM : { 68 | . = ALIGN(8); 69 | __exidx_start = .; 70 | *(.ARM.exidx*) 71 | __exidx_end = .; 72 | . = ALIGN(8); 73 | } >ROM 74 | 75 | .preinit_array : 76 | { 77 | . = ALIGN(8); 78 | PROVIDE_HIDDEN (__preinit_array_start = .); 79 | KEEP (*(.preinit_array*)) 80 | PROVIDE_HIDDEN (__preinit_array_end = .); 81 | . = ALIGN(8); 82 | } >ROM 83 | 84 | .init_array : 85 | { 86 | . = ALIGN(8); 87 | PROVIDE_HIDDEN (__init_array_start = .); 88 | KEEP (*(SORT(.init_array.*))) 89 | KEEP (*(.init_array*)) 90 | PROVIDE_HIDDEN (__init_array_end = .); 91 | . = ALIGN(8); 92 | } >ROM 93 | 94 | .fini_array : 95 | { 96 | . = ALIGN(8); 97 | PROVIDE_HIDDEN (__fini_array_start = .); 98 | KEEP (*(SORT(.fini_array.*))) 99 | KEEP (*(.fini_array*)) 100 | PROVIDE_HIDDEN (__fini_array_end = .); 101 | . = ALIGN(8); 102 | } >ROM 103 | 104 | /* Used by the startup to initialize data */ 105 | _sidata = LOADADDR(.data); 106 | 107 | /* Initialized data sections into "SRAM1" Ram type memory */ 108 | .data : 109 | { 110 | . = ALIGN(8); 111 | _sdata = .; /* create a global symbol at data start */ 112 | *(.data) /* .data sections */ 113 | *(.data*) /* .data* sections */ 114 | 115 | *(.ramfunc) /* Used to place RAM functions in RAM memory */ 116 | 117 | . = ALIGN(8); 118 | _edata = .; /* define a global symbol at data end */ 119 | 120 | } >RAM1 AT> ROM 121 | 122 | /* Uninitialized data section into "SRAM1" Ram type memory */ 123 | . = ALIGN(8); 124 | .bss : 125 | { 126 | /* This is used by the startup in order to initialize the .bss section */ 127 | _sbss = .; /* define a global symbol at bss start */ 128 | __bss_start__ = _sbss; 129 | *(.bss) 130 | *(.bss*) 131 | *(COMMON) 132 | 133 | . = ALIGN(8); 134 | _ebss = .; /* define a global symbol at bss end */ 135 | __bss_end__ = _ebss; 136 | } >RAM1 137 | 138 | /* Data section into "SRAM1" Ram type memory: Non-backup SRAM1 dedicated to CM4 */ 139 | . = ALIGN(8); 140 | RAM1_region : 141 | { 142 | _sRAM1_region = .; /* define a global symbol at section start */ 143 | *(.RAM1_region) 144 | 145 | . = ALIGN(8); 146 | _eRAM1_region = .; /* define a global symbol at section end */ 147 | } >RAM1 148 | 149 | /* Data section into "SRAM2" Ram type memory: Backup SRAM2 dedicated to CM4 */ 150 | . = ALIGN(8); 151 | RAM2_region : 152 | { 153 | _sRAM2_region = .; /* define a global symbol at section start */ 154 | *(.RAM2_region) 155 | 156 | . = ALIGN(8); 157 | _eRAM2_region = .; /* define a global symbol at section end */ 158 | } >RAM2 159 | 160 | /* User_heap_stack section, used to check that there is enough "SRAM1" Ram type memory left */ 161 | ._user_heap_stack : 162 | { 163 | . = ALIGN(8); 164 | PROVIDE ( end = . ); 165 | PROVIDE ( _end = . ); 166 | . = . + _Min_Heap_Size; 167 | . = . + _Min_Stack_Size; 168 | . = ALIGN(8); 169 | } >RAM1 170 | 171 | /* Remove information from the compiler libraries */ 172 | /DISCARD/ : 173 | { 174 | libc.a ( * ) 175 | libm.a ( * ) 176 | libgcc.a ( * ) 177 | } 178 | 179 | .ARM.attributes 0 : { *(.ARM.attributes) } 180 | } 181 | -------------------------------------------------------------------------------- /Projects/NUCLEO-WL55JC/LICENSE.md: -------------------------------------------------------------------------------- 1 | # SLA0044 Rev5/February 2018 2 | 3 | ## Software license agreement 4 | 5 | ### ULTIMATE LIBERTY SOFTWARE LICENSE AGREEMENT 6 | 7 | BY INSTALLING, COPYING, DOWNLOADING, ACCESSING OR OTHERWISE USING THIS SOFTWARE 8 | OR ANY PART THEREOF (AND THE RELATED DOCUMENTATION) FROM STMICROELECTRONICS 9 | INTERNATIONAL N.V, SWISS BRANCH AND/OR ITS AFFILIATED COMPANIES 10 | (STMICROELECTRONICS), THE RECIPIENT, ON BEHALF OF HIMSELF OR HERSELF, OR ON 11 | BEHALF OF ANY ENTITY BY WHICH SUCH RECIPIENT IS EMPLOYED AND/OR ENGAGED AGREES 12 | TO BE BOUND BY THIS SOFTWARE LICENSE AGREEMENT. 13 | 14 | Under STMicroelectronics’ intellectual property rights, the redistribution, 15 | reproduction and use in source and binary forms of the software or any part 16 | thereof, with or without modification, are permitted provided that the following 17 | conditions are met: 18 | 19 | 1. Redistribution of source code (modified or not) must retain any copyright 20 | notice, this list of conditions and the disclaimer set forth below as items 10 21 | and 11. 22 | 23 | 2. Redistributions in binary form, except as embedded into microcontroller or 24 | microprocessor device manufactured by or for STMicroelectronics or a software 25 | update for such device, must reproduce any copyright notice provided with the 26 | binary code, this list of conditions, and the disclaimer set forth below as 27 | items 10 and 11, in documentation and/or other materials provided with the 28 | distribution. 29 | 30 | 3. Neither the name of STMicroelectronics nor the names of other contributors to 31 | this software may be used to endorse or promote products derived from this 32 | software or part thereof without specific written permission. 33 | 34 | 4. This software or any part thereof, including modifications and/or derivative 35 | works of this software, must be used and execute solely and exclusively on or in 36 | combination with a microcontroller or microprocessor device manufactured by or 37 | for STMicroelectronics. 38 | 39 | 5. No use, reproduction or redistribution of this software partially or totally 40 | may be done in any manner that would subject this software to any Open Source 41 | Terms. “Open Source Terms” shall mean any open source license which requires as 42 | part of distribution of software that the source code of such software is 43 | distributed therewith or otherwise made available, or open source license that 44 | substantially complies with the Open Source definition specified at 45 | www.opensource.org and any other comparable open source license such as for 46 | example GNU General Public License (GPL), Eclipse Public License (EPL), Apache 47 | Software License, BSD license or MIT license. 48 | 49 | 6. STMicroelectronics has no obligation to provide any maintenance, support or 50 | updates for the software. 51 | 52 | 7. The software is and will remain the exclusive property of STMicroelectronics 53 | and its licensors. The recipient will not take any action that jeopardizes 54 | STMicroelectronics and its licensors' proprietary rights or acquire any rights 55 | in the software, except the limited rights specified hereunder. 56 | 57 | 8. The recipient shall comply with all applicable laws and regulations affecting 58 | the use of the software or any part thereof including any applicable export 59 | control law or regulation. 60 | 61 | 9. Redistribution and use of this software or any part thereof other than as 62 | permitted under this license is void and will automatically terminate your 63 | rights under this license. 64 | 65 | 10. THIS SOFTWARE IS PROVIDED BY STMICROELECTRONICS AND CONTRIBUTORS "AS IS" AND 66 | ANY EXPRESS, IMPLIED OR STATUTORY WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 67 | IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 68 | NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS, WHICH ARE 69 | DISCLAIMED TO THE FULLEST EXTENT PERMITTED BY LAW. IN NO EVENT SHALL 70 | STMICROELECTRONICS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 71 | INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 72 | LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 73 | PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 74 | LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE 75 | OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 76 | ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 77 | 78 | 11. EXCEPT AS EXPRESSLY PERMITTED HEREUNDER, NO LICENSE OR OTHER RIGHTS, WHETHER 79 | EXPRESS OR IMPLIED, ARE GRANTED UNDER ANY PATENT OR OTHER INTELLECTUAL PROPERTY 80 | RIGHTS OF STMICROELECTRONICS OR ANY THIRD PARTY. 81 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # STM32WL Open Bootloader Applications 2 | 3 | ![latest tag](https://img.shields.io/github/v/tag/STMicroelectronics/stm32wl-openbl-apps.svg?color=brightgreen) 4 | 5 | ![openbl](https://img.shields.io/badge/openbl-v6.0.1-blue.svg) 6 | 7 | ## Overview 8 | 9 | **Open Bootloader** is an In-Application programming (IAP) provided in the STM32Cube MCU Packages and GitHub. It is fully compatible with STM32 System Bootloader so that it have the same supported interfaces and commands. It's also using the same Tools such as STM32CubeProgrammer. 10 | 11 | **Open Bootloader** is provided as an example that can be used by any customer who wants to build and customize his own Bootloader starting from a good basis. It allows all possible bootloader operations (Read, write, erase, jump...) into internal (Flash, SRAM, OTP...) or external memory using one of the available communication interfaces (USART, I2C, SPI, USB-DFU, FDCAN...). 12 | 13 | **Open Bootloader** supplies services to the Host (can be STM32CubeProgrammer or another user made host) in order to perform all possible Bootloader operations. 14 | 15 | **Open Bootloader** relies on STM32Cube HAL/LL drivers for hardware system initialization such as the clocks and the communication interfaces configuration. 16 | 17 | **Open Bootloader** code can be loaded at any address of user Flash memory with taking necessary precautions to avoid erasing or corrupting it by error (for example use write protection mechanism). 18 | 19 | **Open Bootloader** is executed by Cortex-M processor on the non-secure domain and uses the following resources: 20 | - Non secure internal flash memory/SRAM1 21 | - Interrupts 22 | - Clocks and power 23 | - Communication interfaces 24 | - GPIOs 25 | - Systick 26 | - IWDG 27 | 28 | **Open Bootloader** can be customized by changing its location (ie. load it in last user Flash sector or other sectors), its supported protocols, its supported interfaces, and its supported operations. 29 | 30 | ## Documentation 31 | 32 | Since Open Bootloader supports exactly same protocol interfaces as STM32 System Bootloader, following list of documents provide details of how to use each protocol: 33 | - [AN3155](https://www.st.com/resource/en/application_note/CD00264342.pdf): USART protocol used in the STM32 Bootloader 34 | - [AN5405](https://www.st.com/resource/en/application_note/dm00660346.pdf): FDCAN protocol used in the STM32 Bootloader 35 | - [AN4221](https://www.st.com/resource/en/application_note/DM00072315.pdf): I2C protocol used in the STM32 Bootloader 36 | - [AN3156](https://www.st.com/resource/en/application_note/cd00264379.pdf): USB DFU protocol used in the STM32 Bootloader 37 | - [AN4286](https://www.st.com/resource/en/application_note/DM00081379.pdf): SPI protocol used in the STM32 Bootloader 38 | 39 | A useful introductory video series, in six parts, explaining how to use Open Bootloader step by step, can be found here: 40 | - [Part 1](https://www.youtube.com/watch?v=_gejWsAn5kg): Introduction 41 | - [Part 2](https://www.youtube.com/watch?v=kYr7UMieRTo): Using a NUCLEO-G474RE 42 | - [Part 3](https://www.youtube.com/watch?v=JUBac27tOis): Loading an application 43 | - [Part 4](https://www.youtube.com/watch?v=7sMDBSlZ7bU): Adding support for the I2C interface 44 | - [Part 5](https://www.youtube.com/watch?v=rr1W5h94qLU): STLINK-V3SET I2C setup 45 | - [Part 6](https://www.youtube.com/watch?v=IZ6BpDIm6O0): Loading an application over I2C 46 | 47 | ## List of Supported Commands 48 | 49 | All STM32 System Bootloader commands can be supported by Open Bootloader, which includes: 50 | - Get Version 51 | - Get Device ID 52 | - Get Available Command List 53 | - Write Memory 54 | - Read Memory 55 | - Write Protection setting 56 | - Read Protection setting 57 | - Jump to Application 58 | - Flash Erase 59 | - Special Command 60 | - Extended Special Command 61 | 62 | The user can customize the list of supported commands for a specific interface by removing the commands that he don't need. 63 | More details about how to do that can be found in the `Notes` section of the `README.md` file of the application. 64 | 65 | ## How to use 66 | 67 | In order to make the program work, you need to do the following: 68 | - Open your preferred toolchain using the adequate version 69 | - Rebuild all files and load your image into target memory 70 | - Run the application 71 | - Run the Host (can be STM32CubeProgrammer or similar hosts) and connect to Open Bootloader using one of the available communication interfaces (USART, I2C, SPI, USB-DFU, FDCAN...) 72 | 73 | Following physical connections can be used with STM32CubeProgrammer host: 74 | - USB interface can be used directly if USB connector is available on the board. 75 | - USART interface can be used with STLinkV2 or STLinkV3 or USB-UART bridges. 76 | - I2C, SPI interfaces can be used with STLinkV3 or with USB-I2C/SPI bridges. 77 | - FDCAN interface can be used with USB-CAN bridges. 78 | 79 | *Note* 80 | - Before using an interface, make sure its IOs are not used by other components on the board that may interfere with Open Bootloader communication. 81 | - The list of used IOs for each interface can be found in the section `Hardware and Software environment` of the `README.md` file of the application. 82 | 83 | --- 84 | 85 | #### *Note* 86 | 87 | * To clone this repository along with the linked submodules, option `--recursive` has to be specified as shown below. 88 | 89 | ``` 90 | git clone --recursive https://github.com/STMicroelectronics/stm32wl-openbl-apps.git 91 | ``` 92 | 93 | * To get the latest updates, issue the following **two** commands (with the repository `stm32wl-openbl-apps` as the **current working directory**). 94 | 95 | ``` 96 | git pull 97 | git submodule update --init --recursive 98 | ``` 99 | 100 | #### *Note* 101 | 102 | * If GitHub "Download ZIP" option is used instead of the `git clone` command, then the required components have to be collected manually by the user. 103 | 104 | ## Supported Development Toolchains and Compilers 105 | 106 | * IAR Embedded Workbench for ARM (EWARM) toolchain v8.50.9 107 | * RealView Microcontroller Development Kit (MDK-ARM) toolchain v5.32 108 | * STM32CubeIDE v1.8.0 109 | 110 | ## Supported boards 111 | 112 | Product | Board | Application Version 113 | -------------|---------------|---------- 114 | STM32WL55xx | NUCLEO-WL55JC | v1.0.0 115 | 116 | ## Troubleshooting 117 | 118 | Please refer to the [CONTRIBUTING.md](CONTRIBUTING.md) guide. 119 | --------------------------------------------------------------------------------