├── .gitignore
├── .gitmodules
├── Lv_test.uvoptx
├── Lv_test.uvprojx
├── README.md
├── RTE
├── CMSIS
│ ├── RTX_Conf_CM.c
│ ├── RTX_Config.c
│ └── RTX_Config.h
├── Device
│ └── STM32F103RC
│ │ ├── RTE_Device.h
│ │ ├── startup_stm32f10x_hd.s
│ │ ├── stm32f10x_conf.h
│ │ └── system_stm32f10x.c
├── _LittlevGL
│ └── RTE_Components.h
└── _Target_1
│ └── RTE_Components.h
├── encoder
├── drv_encoder.c
├── drv_encoder.h
├── encoder.c
├── encoder.h
└── lv_drv_conf.h
├── ili9341
├── commands.h
├── config.h
├── control.h
├── core.c
├── core.h
├── dma.c
├── dma.h
├── lv_driver.c
└── lv_driver.h
├── images
├── Scarsfun11a.png
├── stm32f4stampV1_1.jpg
└── test_board.png
├── lv_conf.h
├── main.c
├── misc
├── delay.c
├── delay.h
├── led.c
└── led.h
└── pwm
├── pwm.c
└── pwm.h
/.gitignore:
--------------------------------------------------------------------------------
1 | /Objects/
2 | /lvgl.bkp/
3 | /DebugConfig/
4 | /Objects/
5 | /Listings/
6 | *.uvguix.MAX
7 | *.scvd
8 |
--------------------------------------------------------------------------------
/.gitmodules:
--------------------------------------------------------------------------------
1 | [submodule "lvgl"]
2 | path = lvgl
3 | url = https://github.com/littlevgl/lvgl
4 |
--------------------------------------------------------------------------------
/Lv_test.uvprojx:
--------------------------------------------------------------------------------
1 |
2 |
3 |
4 | 2.1
5 |
6 | ### uVision Project, (C) Keil Software
7 |
8 |
9 |
10 | LittlevGL
11 | 0x4
12 | ARM-ADS
13 | 5060750::V5.06 update 6 (build 750)::ARMCC
14 | 0
15 |
16 |
17 | STM32F103RC
18 | STMicroelectronics
19 | Keil.STM32F1xx_DFP.2.3.0
20 | http://www.keil.com/pack/
21 | IRAM(0x20000000,0x0000C000) IROM(0x08000000,0x00040000) CPUTYPE("Cortex-M3") CLOCK(12000000) ELITTLE
22 |
23 |
24 | UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F10x_512 -FS08000000 -FL080000 -FP0($$Device:STM32F103RC$Flash\STM32F10x_512.FLM))
25 | 0
26 | $$Device:STM32F103RC$Device\Include\stm32f10x.h
27 |
28 |
29 |
30 |
31 |
32 |
33 |
34 |
35 |
36 | $$Device:STM32F103RC$SVD\STM32F103xx.svd
37 | 0
38 | 0
39 |
40 |
41 |
42 |
43 |
44 |
45 | 0
46 | 0
47 | 0
48 | 0
49 | 1
50 |
51 | .\Objects\
52 | Lv_test
53 | 1
54 | 0
55 | 0
56 | 1
57 | 1
58 | .\Listings\
59 | 1
60 | 0
61 | 0
62 |
63 | 0
64 | 0
65 |
66 |
67 | 0
68 | 0
69 | 0
70 | 0
71 |
72 |
73 | 0
74 | 0
75 |
76 |
77 | 0
78 | 0
79 | 0
80 | 0
81 |
82 |
83 | 0
84 | 0
85 |
86 |
87 | 0
88 | 0
89 | 0
90 | 0
91 |
92 | 0
93 |
94 |
95 |
96 | 0
97 | 0
98 | 0
99 | 0
100 | 0
101 | 1
102 | 0
103 | 0
104 | 0
105 | 0
106 | 3
107 |
108 |
109 | 1
110 |
111 |
112 | SARMCM3.DLL
113 | -REMAP
114 | DCM.DLL
115 | -pCM3
116 | SARMCM3.DLL
117 |
118 | TCM.DLL
119 | -pCM3
120 |
121 |
122 |
123 | 1
124 | 0
125 | 0
126 | 0
127 | 16
128 |
129 |
130 |
131 |
132 | 1
133 | 0
134 | 0
135 | 1
136 | 1
137 | 4096
138 |
139 | 1
140 | BIN\UL2CM3.DLL
141 | "" ()
142 |
143 |
144 |
145 |
146 | 0
147 |
148 |
149 |
150 | 0
151 | 1
152 | 1
153 | 1
154 | 1
155 | 1
156 | 1
157 | 1
158 | 0
159 | 1
160 | 1
161 | 0
162 | 1
163 | 1
164 | 0
165 | 0
166 | 1
167 | 1
168 | 1
169 | 1
170 | 1
171 | 1
172 | 1
173 | 1
174 | 1
175 | 0
176 | 0
177 | "Cortex-M3"
178 |
179 | 0
180 | 0
181 | 0
182 | 1
183 | 1
184 | 0
185 | 0
186 | 0
187 | 0
188 | 0
189 | 0
190 | 8
191 | 1
192 | 0
193 | 0
194 | 0
195 | 3
196 | 3
197 | 0
198 | 0
199 | 0
200 | 0
201 | 0
202 | 0
203 | 0
204 | 0
205 | 0
206 | 0
207 | 1
208 | 0
209 | 0
210 | 0
211 | 0
212 | 1
213 | 0
214 |
215 |
216 | 0
217 | 0x0
218 | 0x0
219 |
220 |
221 | 0
222 | 0x0
223 | 0x0
224 |
225 |
226 | 0
227 | 0x0
228 | 0x0
229 |
230 |
231 | 0
232 | 0x0
233 | 0x0
234 |
235 |
236 | 0
237 | 0x0
238 | 0x0
239 |
240 |
241 | 0
242 | 0x0
243 | 0x0
244 |
245 |
246 | 0
247 | 0x20000000
248 | 0xc000
249 |
250 |
251 | 1
252 | 0x8000000
253 | 0x40000
254 |
255 |
256 | 0
257 | 0x0
258 | 0x0
259 |
260 |
261 | 1
262 | 0x0
263 | 0x0
264 |
265 |
266 | 1
267 | 0x0
268 | 0x0
269 |
270 |
271 | 1
272 | 0x0
273 | 0x0
274 |
275 |
276 | 1
277 | 0x8000000
278 | 0x40000
279 |
280 |
281 | 1
282 | 0x0
283 | 0x0
284 |
285 |
286 | 0
287 | 0x0
288 | 0x0
289 |
290 |
291 | 0
292 | 0x0
293 | 0x0
294 |
295 |
296 | 0
297 | 0x0
298 | 0x0
299 |
300 |
301 | 0
302 | 0x20000000
303 | 0xc000
304 |
305 |
306 | 0
307 | 0x0
308 | 0x0
309 |
310 |
311 |
312 |
313 |
314 | 1
315 | 3
316 | 0
317 | 0
318 | 1
319 | 0
320 | 0
321 | 0
322 | 0
323 | 0
324 | 2
325 | 0
326 | 0
327 | 1
328 | 1
329 | 0
330 | 3
331 | 3
332 | 1
333 | 1
334 | 0
335 | 0
336 | 0
337 |
338 |
339 |
340 |
341 |
342 |
343 |
344 |
345 | 1
346 | 0
347 | 0
348 | 0
349 | 0
350 | 0
351 | 0
352 | 0
353 | 0
354 | 0
355 |
356 |
357 |
358 |
359 |
360 |
361 |
362 |
363 | 1
364 | 0
365 | 0
366 | 0
367 | 1
368 | 0
369 | 0x08000000
370 | 0x20000000
371 |
372 |
373 |
374 |
375 | --verbose
376 |
377 |
378 |
379 |
380 |
381 |
382 |
383 | src
384 |
385 |
386 | main.c
387 | 1
388 | .\main.c
389 |
390 |
391 |
392 |
393 | ili9341
394 |
395 |
396 | core.c
397 | 1
398 | .\ili9341\core.c
399 |
400 |
401 | dma.c
402 | 1
403 | .\ili9341\dma.c
404 |
405 |
406 | lv_driver.c
407 | 1
408 | .\ili9341\lv_driver.c
409 |
410 |
411 |
412 |
413 | misc
414 |
415 |
416 | led.c
417 | 1
418 | .\misc\led.c
419 |
420 |
421 |
422 |
423 | encoder
424 |
425 |
426 | drv_encoder.c
427 | 1
428 | .\encoder\drv_encoder.c
429 |
430 |
431 | encoder.c
432 | 1
433 | .\encoder\encoder.c
434 |
435 |
436 |
437 |
438 | pwm
439 |
440 |
441 | pwm.c
442 | 1
443 | .\pwm\pwm.c
444 |
445 |
446 |
447 |
448 | lvgl
449 |
450 |
451 | lv_disp.c
452 | 1
453 | .\lvgl\src\lv_core\lv_disp.c
454 |
455 |
456 | lv_group.c
457 | 1
458 | .\lvgl\src\lv_core\lv_group.c
459 |
460 |
461 | lv_indev.c
462 | 1
463 | .\lvgl\src\lv_core\lv_indev.c
464 |
465 |
466 | lv_obj.c
467 | 1
468 | .\lvgl\src\lv_core\lv_obj.c
469 |
470 |
471 | lv_refr.c
472 | 1
473 | .\lvgl\src\lv_core\lv_refr.c
474 |
475 |
476 | lv_style.c
477 | 1
478 | .\lvgl\src\lv_core\lv_style.c
479 |
480 |
481 | lv_draw.c
482 | 1
483 | .\lvgl\src\lv_draw\lv_draw.c
484 |
485 |
486 | lv_draw_arc.c
487 | 1
488 | .\lvgl\src\lv_draw\lv_draw_arc.c
489 |
490 |
491 | lv_draw_basic.c
492 | 1
493 | .\lvgl\src\lv_draw\lv_draw_basic.c
494 |
495 |
496 | lv_draw_img.c
497 | 1
498 | .\lvgl\src\lv_draw\lv_draw_img.c
499 |
500 |
501 | lv_draw_label.c
502 | 1
503 | .\lvgl\src\lv_draw\lv_draw_label.c
504 |
505 |
506 | lv_draw_line.c
507 | 1
508 | .\lvgl\src\lv_draw\lv_draw_line.c
509 |
510 |
511 | lv_draw_rect.c
512 | 1
513 | .\lvgl\src\lv_draw\lv_draw_rect.c
514 |
515 |
516 | lv_draw_triangle.c
517 | 1
518 | .\lvgl\src\lv_draw\lv_draw_triangle.c
519 |
520 |
521 | lv_img_cache.c
522 | 1
523 | .\lvgl\src\lv_draw\lv_img_cache.c
524 |
525 |
526 | lv_img_decoder.c
527 | 1
528 | .\lvgl\src\lv_draw\lv_img_decoder.c
529 |
530 |
531 | lv_font.c
532 | 1
533 | .\lvgl\src\lv_font\lv_font.c
534 |
535 |
536 | lv_font_fmt_txt.c
537 | 1
538 | .\lvgl\src\lv_font\lv_font_fmt_txt.c
539 |
540 |
541 | lv_font_roboto_12.c
542 | 1
543 | .\lvgl\src\lv_font\lv_font_roboto_12.c
544 |
545 |
546 | lv_font_roboto_16.c
547 | 1
548 | .\lvgl\src\lv_font\lv_font_roboto_16.c
549 |
550 |
551 | lv_font_roboto_22.c
552 | 1
553 | .\lvgl\src\lv_font\lv_font_roboto_22.c
554 |
555 |
556 | lv_font_roboto_28.c
557 | 1
558 | .\lvgl\src\lv_font\lv_font_roboto_28.c
559 |
560 |
561 | lv_font_unscii_8.c
562 | 1
563 | .\lvgl\src\lv_font\lv_font_unscii_8.c
564 |
565 |
566 | lv_hal_disp.c
567 | 1
568 | .\lvgl\src\lv_hal\lv_hal_disp.c
569 |
570 |
571 | lv_hal_indev.c
572 | 1
573 | .\lvgl\src\lv_hal\lv_hal_indev.c
574 |
575 |
576 | lv_hal_tick.c
577 | 1
578 | .\lvgl\src\lv_hal\lv_hal_tick.c
579 |
580 |
581 | lv_anim.c
582 | 1
583 | .\lvgl\src\lv_misc\lv_anim.c
584 |
585 |
586 | lv_area.c
587 | 1
588 | .\lvgl\src\lv_misc\lv_area.c
589 |
590 |
591 | lv_circ.c
592 | 1
593 | .\lvgl\src\lv_misc\lv_circ.c
594 |
595 |
596 | lv_color.c
597 | 1
598 | .\lvgl\src\lv_misc\lv_color.c
599 |
600 |
601 | lv_fs.c
602 | 1
603 | .\lvgl\src\lv_misc\lv_fs.c
604 |
605 |
606 | lv_gc.c
607 | 1
608 | .\lvgl\src\lv_misc\lv_gc.c
609 |
610 |
611 | lv_ll.c
612 | 1
613 | .\lvgl\src\lv_misc\lv_ll.c
614 |
615 |
616 | lv_log.c
617 | 1
618 | .\lvgl\src\lv_misc\lv_log.c
619 |
620 |
621 | lv_math.c
622 | 1
623 | .\lvgl\src\lv_misc\lv_math.c
624 |
625 |
626 | lv_mem.c
627 | 1
628 | .\lvgl\src\lv_misc\lv_mem.c
629 |
630 |
631 | lv_task.c
632 | 1
633 | .\lvgl\src\lv_misc\lv_task.c
634 |
635 |
636 | lv_templ.c
637 | 1
638 | .\lvgl\src\lv_misc\lv_templ.c
639 |
640 |
641 | lv_txt.c
642 | 1
643 | .\lvgl\src\lv_misc\lv_txt.c
644 |
645 |
646 | lv_utils.c
647 | 1
648 | .\lvgl\src\lv_misc\lv_utils.c
649 |
650 |
651 | lv_arc.c
652 | 1
653 | .\lvgl\src\lv_objx\lv_arc.c
654 |
655 |
656 | lv_bar.c
657 | 1
658 | .\lvgl\src\lv_objx\lv_bar.c
659 |
660 |
661 | lv_btn.c
662 | 1
663 | .\lvgl\src\lv_objx\lv_btn.c
664 |
665 |
666 | lv_btnm.c
667 | 1
668 | .\lvgl\src\lv_objx\lv_btnm.c
669 |
670 |
671 | lv_calendar.c
672 | 1
673 | .\lvgl\src\lv_objx\lv_calendar.c
674 |
675 |
676 | lv_canvas.c
677 | 1
678 | .\lvgl\src\lv_objx\lv_canvas.c
679 |
680 |
681 | lv_cb.c
682 | 1
683 | .\lvgl\src\lv_objx\lv_cb.c
684 |
685 |
686 | lv_chart.c
687 | 1
688 | .\lvgl\src\lv_objx\lv_chart.c
689 |
690 |
691 | lv_cont.c
692 | 1
693 | .\lvgl\src\lv_objx\lv_cont.c
694 |
695 |
696 | lv_ddlist.c
697 | 1
698 | .\lvgl\src\lv_objx\lv_ddlist.c
699 |
700 |
701 | lv_gauge.c
702 | 1
703 | .\lvgl\src\lv_objx\lv_gauge.c
704 |
705 |
706 | lv_img.c
707 | 1
708 | .\lvgl\src\lv_objx\lv_img.c
709 |
710 |
711 | lv_imgbtn.c
712 | 1
713 | .\lvgl\src\lv_objx\lv_imgbtn.c
714 |
715 |
716 | lv_kb.c
717 | 1
718 | .\lvgl\src\lv_objx\lv_kb.c
719 |
720 |
721 | lv_label.c
722 | 1
723 | .\lvgl\src\lv_objx\lv_label.c
724 |
725 |
726 | lv_led.c
727 | 1
728 | .\lvgl\src\lv_objx\lv_led.c
729 |
730 |
731 | lv_line.c
732 | 1
733 | .\lvgl\src\lv_objx\lv_line.c
734 |
735 |
736 | lv_list.c
737 | 1
738 | .\lvgl\src\lv_objx\lv_list.c
739 |
740 |
741 | lv_lmeter.c
742 | 1
743 | .\lvgl\src\lv_objx\lv_lmeter.c
744 |
745 |
746 | lv_mbox.c
747 | 1
748 | .\lvgl\src\lv_objx\lv_mbox.c
749 |
750 |
751 | lv_objx_templ.c
752 | 1
753 | .\lvgl\src\lv_objx\lv_objx_templ.c
754 |
755 |
756 | lv_page.c
757 | 1
758 | .\lvgl\src\lv_objx\lv_page.c
759 |
760 |
761 | lv_preload.c
762 | 1
763 | .\lvgl\src\lv_objx\lv_preload.c
764 |
765 |
766 | lv_roller.c
767 | 1
768 | .\lvgl\src\lv_objx\lv_roller.c
769 |
770 |
771 | lv_slider.c
772 | 1
773 | .\lvgl\src\lv_objx\lv_slider.c
774 |
775 |
776 | lv_spinbox.c
777 | 1
778 | .\lvgl\src\lv_objx\lv_spinbox.c
779 |
780 |
781 | lv_sw.c
782 | 1
783 | .\lvgl\src\lv_objx\lv_sw.c
784 |
785 |
786 | lv_ta.c
787 | 1
788 | .\lvgl\src\lv_objx\lv_ta.c
789 |
790 |
791 | lv_table.c
792 | 1
793 | .\lvgl\src\lv_objx\lv_table.c
794 |
795 |
796 | lv_tabview.c
797 | 1
798 | .\lvgl\src\lv_objx\lv_tabview.c
799 |
800 |
801 | lv_tileview.c
802 | 1
803 | .\lvgl\src\lv_objx\lv_tileview.c
804 |
805 |
806 | lv_win.c
807 | 1
808 | .\lvgl\src\lv_objx\lv_win.c
809 |
810 |
811 | lv_theme.c
812 | 1
813 | .\lvgl\src\lv_themes\lv_theme.c
814 |
815 |
816 | lv_theme_alien.c
817 | 1
818 | .\lvgl\src\lv_themes\lv_theme_alien.c
819 |
820 |
821 | lv_theme_default.c
822 | 1
823 | .\lvgl\src\lv_themes\lv_theme_default.c
824 |
825 |
826 | lv_theme_material.c
827 | 1
828 | .\lvgl\src\lv_themes\lv_theme_material.c
829 |
830 |
831 | lv_theme_mono.c
832 | 1
833 | .\lvgl\src\lv_themes\lv_theme_mono.c
834 |
835 |
836 | lv_theme_nemo.c
837 | 1
838 | .\lvgl\src\lv_themes\lv_theme_nemo.c
839 |
840 |
841 | lv_theme_night.c
842 | 1
843 | .\lvgl\src\lv_themes\lv_theme_night.c
844 |
845 |
846 | lv_theme_templ.c
847 | 1
848 | .\lvgl\src\lv_themes\lv_theme_templ.c
849 |
850 |
851 | lv_theme_zen.c
852 | 1
853 | .\lvgl\src\lv_themes\lv_theme_zen.c
854 |
855 |
856 | lv_async.c
857 | 1
858 | .\lvgl\src\lv_misc\lv_async.c
859 |
860 |
861 |
862 |
863 | ::CMSIS
864 |
865 |
866 | ::Device
867 |
868 |
869 |
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931 |
932 |
933 |
934 |
935 |
936 |
937 |
938 |
939 | RTE\CMSIS\RTX_Conf_CM.c
940 |
941 |
942 |
943 |
944 |
945 | RTE\CMSIS\RTX_Config.c
946 |
947 |
948 |
949 |
950 |
951 |
952 |
953 | RTE\CMSIS\RTX_Config.h
954 |
955 |
956 |
957 |
958 |
959 |
960 |
961 | RTE\Device\STM32F103RC\RTE_Device.h
962 |
963 |
964 |
965 |
966 |
967 |
968 |
969 | RTE\Device\STM32F103RC\startup_stm32f10x_hd.s
970 |
971 |
972 |
973 |
974 |
975 |
976 |
977 | RTE\Device\STM32F103RC\stm32f10x_conf.h
978 |
979 |
980 |
981 |
982 |
983 |
984 |
985 | RTE\Device\STM32F103RC\system_stm32f10x.c
986 |
987 |
988 |
989 |
990 |
991 |
992 |
993 | RTE\Device\STM32F103RE\RTE_Device.h
994 |
995 |
996 |
997 |
998 |
999 | RTE\Device\STM32F103RE\startup_stm32f10x_hd.s
1000 |
1001 |
1002 |
1003 |
1004 |
1005 | RTE\Device\STM32F103RE\stm32f10x_conf.h
1006 |
1007 |
1008 |
1009 |
1010 |
1011 | RTE\Device\STM32F103RE\system_stm32f10x.c
1012 |
1013 |
1014 |
1015 |
1016 |
1017 |
1018 |
1019 |
1020 |
--------------------------------------------------------------------------------
/README.md:
--------------------------------------------------------------------------------
1 | # ScarsFun Simple LittleVgl test project
2 |
3 | ### LittleVgl V6.0
4 |
5 | * Custom STM32F103RC breakout Board (72Mhz, 64K ram, 256K Flash) .
6 | * ILI9341 display over SPI with DMA. rotary encoder.
7 | * KEIL RTXv5 RTOS.
8 | * SPL (STM32 Standard Peripheral Libraries).
9 | * LVGL event driven refresh. Standby after 10 Secs Encoder inactivity.
10 |
11 |
12 | LittleVgl: https://littlevgl.com
13 |
14 | 
15 | 
16 | 
17 |
18 |
19 |
--------------------------------------------------------------------------------
/RTE/CMSIS/RTX_Conf_CM.c:
--------------------------------------------------------------------------------
1 | /*----------------------------------------------------------------------------
2 | * CMSIS-RTOS - RTX
3 | *----------------------------------------------------------------------------
4 | * Name: RTX_Conf_CM.C
5 | * Purpose: Configuration of CMSIS RTX Kernel for Cortex-M
6 | * Rev.: V4.70.1
7 | *----------------------------------------------------------------------------
8 | *
9 | * Copyright (c) 1999-2009 KEIL, 2009-2016 ARM Germany GmbH. All rights reserved.
10 | *
11 | * SPDX-License-Identifier: Apache-2.0
12 | *
13 | * Licensed under the Apache License, Version 2.0 (the License); you may
14 | * not use this file except in compliance with the License.
15 | * You may obtain a copy of the License at
16 | *
17 | * www.apache.org/licenses/LICENSE-2.0
18 | *
19 | * Unless required by applicable law or agreed to in writing, software
20 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT
21 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
22 | * See the License for the specific language governing permissions and
23 | * limitations under the License.
24 | *---------------------------------------------------------------------------*/
25 |
26 | #include "cmsis_os.h"
27 |
28 |
29 | /*----------------------------------------------------------------------------
30 | * RTX User configuration part BEGIN
31 | *---------------------------------------------------------------------------*/
32 |
33 | //-------- <<< Use Configuration Wizard in Context Menu >>> -----------------
34 | //
35 | // Thread Configuration
36 | // =======================
37 | //
38 | // Number of concurrent running user threads <1-250>
39 | // Defines max. number of user threads that will run at the same time.
40 | // Default: 6
41 | #ifndef OS_TASKCNT
42 | #define OS_TASKCNT 5
43 | #endif
44 |
45 | // Default Thread stack size [bytes] <64-4096:8><#/4>
46 | // Defines default stack size for threads with osThreadDef stacksz = 0
47 | // Default: 200
48 | #ifndef OS_STKSIZE
49 | #define OS_STKSIZE 50 // this stack size value is in words
50 | #endif
51 |
52 | // Main Thread stack size [bytes] <64-32768:8><#/4>
53 | // Defines stack size for main thread.
54 | // Default: 200
55 | #ifndef OS_MAINSTKSIZE
56 | #define OS_MAINSTKSIZE 250 // this stack size value is in words
57 | #endif
58 |
59 | // Number of threads with user-provided stack size <0-250>
60 | // Defines the number of threads with user-provided stack size.
61 | // Default: 0
62 | #ifndef OS_PRIVCNT
63 | #define OS_PRIVCNT 1
64 | #endif
65 |
66 | // Total stack size [bytes] for threads with user-provided stack size <0-1048576:8><#/4>
67 | // Defines the combined stack size for threads with user-provided stack size.
68 | // Default: 0
69 | #ifndef OS_PRIVSTKSIZE
70 | #define OS_PRIVSTKSIZE 374 // this stack size value is in words
71 | #endif
72 |
73 | // Stack overflow checking
74 | // Enable stack overflow checks at thread switch.
75 | // Enabling this option increases slightly the execution time of a thread switch.
76 | #ifndef OS_STKCHECK
77 | #define OS_STKCHECK 1
78 | #endif
79 |
80 | // Stack usage watermark
81 | // Initialize thread stack with watermark pattern for analyzing stack usage (current/maximum) in System and Thread Viewer.
82 | // Enabling this option increases significantly the execution time of osThreadCreate.
83 | #ifndef OS_STKINIT
84 | #define OS_STKINIT 1
85 | #endif
86 |
87 | // Processor mode for thread execution
88 | // <0=> Unprivileged mode
89 | // <1=> Privileged mode
90 | // Default: Privileged mode
91 | #ifndef OS_RUNPRIV
92 | #define OS_RUNPRIV 1
93 | #endif
94 |
95 | //
96 |
97 | // RTX Kernel Timer Tick Configuration
98 | // ======================================
99 | // Use Cortex-M SysTick timer as RTX Kernel Timer
100 | // Cortex-M processors provide in most cases a SysTick timer that can be used as
101 | // as time-base for RTX.
102 | #ifndef OS_SYSTICK
103 | #define OS_SYSTICK 1
104 | #endif
105 | //
106 | // RTOS Kernel Timer input clock frequency [Hz] <1-1000000000>
107 | // Defines the input frequency of the RTOS Kernel Timer.
108 | // When the Cortex-M SysTick timer is used, the input clock
109 | // is on most systems identical with the core clock.
110 | #ifndef OS_CLOCK
111 | #define OS_CLOCK 72000000
112 | #endif
113 |
114 | // RTX Timer tick interval value [us] <1-1000000>
115 | // The RTX Timer tick interval value is used to calculate timeout values.
116 | // When the Cortex-M SysTick timer is enabled, the value also configures the SysTick timer.
117 | // Default: 1000 (1ms)
118 | #ifndef OS_TICK
119 | #define OS_TICK 1000
120 | #endif
121 |
122 | //
123 |
124 | // System Configuration
125 | // =======================
126 | //
127 | // Round-Robin Thread switching
128 | // ===============================
129 | //
130 | // Enables Round-Robin Thread switching.
131 | #ifndef OS_ROBIN
132 | #define OS_ROBIN 1
133 | #endif
134 |
135 | // Round-Robin Timeout [ticks] <1-1000>
136 | // Defines how long a thread will execute before a thread switch.
137 | // Default: 5
138 | #ifndef OS_ROBINTOUT
139 | #define OS_ROBINTOUT 5
140 | #endif
141 |
142 | //
143 |
144 | // User Timers
145 | // ==============
146 | // Enables user Timers
147 | #ifndef OS_TIMERS
148 | #define OS_TIMERS 1
149 | #endif
150 |
151 | // Timer Thread Priority
152 | // <1=> Low
153 | // <2=> Below Normal <3=> Normal <4=> Above Normal
154 | // <5=> High
155 | // <6=> Realtime (highest)
156 | // Defines priority for Timer Thread
157 | // Default: High
158 | #ifndef OS_TIMERPRIO
159 | #define OS_TIMERPRIO 3
160 | #endif
161 |
162 | // Timer Thread stack size [bytes] <64-4096:8><#/4>
163 | // Defines stack size for Timer thread.
164 | // Default: 200
165 | #ifndef OS_TIMERSTKSZ
166 | #define OS_TIMERSTKSZ 50 // this stack size value is in words
167 | #endif
168 |
169 | // Timer Callback Queue size <1-32>
170 | // Number of concurrent active timer callback functions.
171 | // Default: 4
172 | #ifndef OS_TIMERCBQS
173 | #define OS_TIMERCBQS 4
174 | #endif
175 |
176 | //
177 |
178 | // ISR FIFO Queue size<4=> 4 entries <8=> 8 entries
179 | // <12=> 12 entries <16=> 16 entries
180 | // <24=> 24 entries <32=> 32 entries
181 | // <48=> 48 entries <64=> 64 entries
182 | // <96=> 96 entries
183 | // ISR functions store requests to this buffer,
184 | // when they are called from the interrupt handler.
185 | // Default: 16 entries
186 | #ifndef OS_FIFOSZ
187 | #define OS_FIFOSZ 16
188 | #endif
189 |
190 | //
191 |
192 | //------------- <<< end of configuration section >>> -----------------------
193 |
194 | // Standard library system mutexes
195 | // ===============================
196 | // Define max. number system mutexes that are used to protect
197 | // the arm standard runtime library. For microlib they are not used.
198 | #ifndef OS_MUTEXCNT
199 | #define OS_MUTEXCNT 8
200 | #endif
201 |
202 | /*----------------------------------------------------------------------------
203 | * RTX User configuration part END
204 | *---------------------------------------------------------------------------*/
205 |
206 | #define OS_TRV ((uint32_t)(((double)OS_CLOCK*(double)OS_TICK)/1E6)-1)
207 |
208 |
209 | /*----------------------------------------------------------------------------
210 | * Global Functions
211 | *---------------------------------------------------------------------------*/
212 |
213 | /*--------------------------- os_idle_demon ---------------------------------*/
214 |
215 | /// \brief The idle demon is running when no other thread is ready to run
216 | void os_idle_demon (void) {
217 |
218 | for (;;) {
219 | /* HERE: include optional user code to be executed when no thread runs.*/
220 | }
221 | }
222 |
223 | #if (OS_SYSTICK == 0) // Functions for alternative timer as RTX kernel timer
224 |
225 | /*--------------------------- os_tick_init ----------------------------------*/
226 |
227 | /// \brief Initializes an alternative hardware timer as RTX kernel timer
228 | /// \return IRQ number of the alternative hardware timer
229 | int os_tick_init (void) {
230 | return (-1); /* Return IRQ number of timer (0..239) */
231 | }
232 |
233 | /*--------------------------- os_tick_val -----------------------------------*/
234 |
235 | /// \brief Get alternative hardware timer's current value (0 .. OS_TRV)
236 | /// \return Current value of the alternative hardware timer
237 | uint32_t os_tick_val (void) {
238 | return (0);
239 | }
240 |
241 | /*--------------------------- os_tick_ovf -----------------------------------*/
242 |
243 | /// \brief Get alternative hardware timer's overflow flag
244 | /// \return Overflow flag\n
245 | /// - 1 : overflow
246 | /// - 0 : no overflow
247 | uint32_t os_tick_ovf (void) {
248 | return (0);
249 | }
250 |
251 | /*--------------------------- os_tick_irqack --------------------------------*/
252 |
253 | /// \brief Acknowledge alternative hardware timer interrupt
254 | void os_tick_irqack (void) {
255 | /* ... */
256 | }
257 |
258 | #endif // (OS_SYSTICK == 0)
259 |
260 | /*--------------------------- os_error --------------------------------------*/
261 |
262 | /* OS Error Codes */
263 | #define OS_ERROR_STACK_OVF 1
264 | #define OS_ERROR_FIFO_OVF 2
265 | #define OS_ERROR_MBX_OVF 3
266 | #define OS_ERROR_TIMER_OVF 4
267 |
268 | extern osThreadId svcThreadGetId (void);
269 |
270 | /// \brief Called when a runtime error is detected
271 | /// \param[in] error_code actual error code that has been detected
272 | void os_error (uint32_t error_code) {
273 |
274 | /* HERE: include optional code to be executed on runtime error. */
275 | switch (error_code) {
276 | case OS_ERROR_STACK_OVF:
277 | /* Stack overflow detected for the currently running task. */
278 | /* Thread can be identified by calling svcThreadGetId(). */
279 | break;
280 | case OS_ERROR_FIFO_OVF:
281 | /* ISR FIFO Queue buffer overflow detected. */
282 | break;
283 | case OS_ERROR_MBX_OVF:
284 | /* Mailbox overflow detected. */
285 | break;
286 | case OS_ERROR_TIMER_OVF:
287 | /* User Timer Callback Queue overflow detected. */
288 | break;
289 | default:
290 | break;
291 | }
292 | for (;;);
293 | }
294 |
295 |
296 | /*----------------------------------------------------------------------------
297 | * RTX Configuration Functions
298 | *---------------------------------------------------------------------------*/
299 |
300 | #include "RTX_CM_lib.h"
301 |
302 | /*----------------------------------------------------------------------------
303 | * end of file
304 | *---------------------------------------------------------------------------*/
305 |
--------------------------------------------------------------------------------
/RTE/CMSIS/RTX_Config.c:
--------------------------------------------------------------------------------
1 | /*
2 | * Copyright (c) 2013-2018 Arm Limited. All rights reserved.
3 | *
4 | * SPDX-License-Identifier: Apache-2.0
5 | *
6 | * Licensed under the Apache License, Version 2.0 (the License); you may
7 | * not use this file except in compliance with the License.
8 | * You may obtain a copy of the License at
9 | *
10 | * www.apache.org/licenses/LICENSE-2.0
11 | *
12 | * Unless required by applicable law or agreed to in writing, software
13 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT
14 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
15 | * See the License for the specific language governing permissions and
16 | * limitations under the License.
17 | *
18 | * -----------------------------------------------------------------------------
19 | *
20 | * $Revision: V5.1.0
21 | *
22 | * Project: CMSIS-RTOS RTX
23 | * Title: RTX Configuration
24 | *
25 | * -----------------------------------------------------------------------------
26 | */
27 |
28 | #include "cmsis_compiler.h"
29 | #include "rtx_os.h"
30 |
31 | // OS Idle Thread
32 | __WEAK __NO_RETURN void osRtxIdleThread (void *argument) {
33 | (void)argument;
34 |
35 | for (;;) {}
36 | }
37 |
38 | // OS Error Callback function
39 | __WEAK uint32_t osRtxErrorNotify (uint32_t code, void *object_id) {
40 | (void)object_id;
41 |
42 | switch (code) {
43 | case osRtxErrorStackUnderflow:
44 | // Stack overflow detected for thread (thread_id=object_id)
45 | break;
46 | case osRtxErrorISRQueueOverflow:
47 | // ISR Queue overflow detected when inserting object (object_id)
48 | break;
49 | case osRtxErrorTimerQueueOverflow:
50 | // User Timer Callback Queue overflow detected for timer (timer_id=object_id)
51 | break;
52 | case osRtxErrorClibSpace:
53 | // Standard C/C++ library libspace not available: increase OS_THREAD_LIBSPACE_NUM
54 | break;
55 | case osRtxErrorClibMutex:
56 | // Standard C/C++ library mutex initialization failed
57 | break;
58 | default:
59 | // Reserved
60 | break;
61 | }
62 | for (;;) {}
63 | //return 0U;
64 | }
65 |
--------------------------------------------------------------------------------
/RTE/CMSIS/RTX_Config.h:
--------------------------------------------------------------------------------
1 | /*
2 | * Copyright (c) 2013-2018 Arm Limited. All rights reserved.
3 | *
4 | * SPDX-License-Identifier: Apache-2.0
5 | *
6 | * Licensed under the Apache License, Version 2.0 (the License); you may
7 | * not use this file except in compliance with the License.
8 | * You may obtain a copy of the License at
9 | *
10 | * www.apache.org/licenses/LICENSE-2.0
11 | *
12 | * Unless required by applicable law or agreed to in writing, software
13 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT
14 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
15 | * See the License for the specific language governing permissions and
16 | * limitations under the License.
17 | *
18 | * -----------------------------------------------------------------------------
19 | *
20 | * $Revision: V5.4.0
21 | *
22 | * Project: CMSIS-RTOS RTX
23 | * Title: RTX Configuration definitions
24 | *
25 | * -----------------------------------------------------------------------------
26 | */
27 |
28 | #ifndef RTX_CONFIG_H_
29 | #define RTX_CONFIG_H_
30 |
31 | #ifdef _RTE_
32 | #include "RTE_Components.h"
33 | #ifdef RTE_RTX_CONFIG_H
34 | #include RTE_RTX_CONFIG_H
35 | #endif
36 | #endif
37 |
38 | //-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
39 |
40 | // System Configuration
41 | // =======================
42 |
43 | // Global Dynamic Memory size [bytes] <0-1073741824:8>
44 | // Defines the combined global dynamic memory size.
45 | // Default: 4096
46 | #ifndef OS_DYNAMIC_MEM_SIZE
47 | #define OS_DYNAMIC_MEM_SIZE 4096
48 | #endif
49 |
50 | // Kernel Tick Frequency [Hz] <1-1000000>
51 | // Defines base time unit for delays and timeouts.
52 | // Default: 1000 (1ms tick)
53 | #ifndef OS_TICK_FREQ
54 | #define OS_TICK_FREQ 1000
55 | #endif
56 |
57 | // Round-Robin Thread switching
58 | // Enables Round-Robin Thread switching.
59 | #ifndef OS_ROBIN_ENABLE
60 | #define OS_ROBIN_ENABLE 1
61 | #endif
62 |
63 | // Round-Robin Timeout <1-1000>
64 | // Defines how many ticks a thread will execute before a thread switch.
65 | // Default: 5
66 | #ifndef OS_ROBIN_TIMEOUT
67 | #define OS_ROBIN_TIMEOUT 5
68 | #endif
69 |
70 | //
71 |
72 | // ISR FIFO Queue
73 | // <4=> 4 entries <8=> 8 entries <12=> 12 entries <16=> 16 entries
74 | // <24=> 24 entries <32=> 32 entries <48=> 48 entries <64=> 64 entries
75 | // <96=> 96 entries <128=> 128 entries <196=> 196 entries <256=> 256 entries
76 | // RTOS Functions called from ISR store requests to this buffer.
77 | // Default: 16 entries
78 | #ifndef OS_ISR_FIFO_QUEUE
79 | #define OS_ISR_FIFO_QUEUE 16
80 | #endif
81 |
82 | // Object Memory usage counters
83 | // Enables object memory usage counters (requires RTX source variant).
84 | #ifndef OS_OBJ_MEM_USAGE
85 | #define OS_OBJ_MEM_USAGE 0
86 | #endif
87 |
88 | //
89 |
90 | // Thread Configuration
91 | // =======================
92 |
93 | // Object specific Memory allocation
94 | // Enables object specific memory allocation.
95 | #ifndef OS_THREAD_OBJ_MEM
96 | #define OS_THREAD_OBJ_MEM 1
97 | #endif
98 |
99 | // Number of user Threads <1-1000>
100 | // Defines maximum number of user threads that can be active at the same time.
101 | // Applies to user threads with system provided memory for control blocks.
102 | #ifndef OS_THREAD_NUM
103 | #define OS_THREAD_NUM 5
104 | #endif
105 |
106 | // Number of user Threads with default Stack size <0-1000>
107 | // Defines maximum number of user threads with default stack size.
108 | // Applies to user threads with zero stack size specified.
109 | #ifndef OS_THREAD_DEF_STACK_NUM
110 | #define OS_THREAD_DEF_STACK_NUM 3
111 | #endif
112 |
113 | // Total Stack size [bytes] for user Threads with user-provided Stack size <0-1073741824:8>
114 | // Defines the combined stack size for user threads with user-provided stack size.
115 | // Applies to user threads with user-provided stack size and system provided memory for stack.
116 | // Default: 0
117 | #ifndef OS_THREAD_USER_STACK_SIZE
118 | #define OS_THREAD_USER_STACK_SIZE 2048
119 | #endif
120 |
121 | //
122 |
123 | // Default Thread Stack size [bytes] <96-1073741824:8>
124 | // Defines stack size for threads with zero stack size specified.
125 | // Default: 256
126 | #ifndef OS_STACK_SIZE
127 | #define OS_STACK_SIZE 256
128 | #endif
129 |
130 | // Idle Thread Stack size [bytes] <72-1073741824:8>
131 | // Defines stack size for Idle thread.
132 | // Default: 256
133 | #ifndef OS_IDLE_THREAD_STACK_SIZE
134 | #define OS_IDLE_THREAD_STACK_SIZE 256
135 | #endif
136 |
137 | // Idle Thread TrustZone Module Identifier
138 | // Defines TrustZone Thread Context Management Identifier.
139 | // Applies only to cores with TrustZone technology.
140 | // Default: 0 (not used)
141 | #ifndef OS_IDLE_THREAD_TZ_MOD_ID
142 | #define OS_IDLE_THREAD_TZ_MOD_ID 0
143 | #endif
144 |
145 | // Stack overrun checking
146 | // Enables stack overrun check at thread switch.
147 | // Enabling this option increases slightly the execution time of a thread switch.
148 | #ifndef OS_STACK_CHECK
149 | #define OS_STACK_CHECK 1
150 | #endif
151 |
152 | // Stack usage watermark
153 | // Initializes thread stack with watermark pattern for analyzing stack usage.
154 | // Enabling this option increases significantly the execution time of thread creation.
155 | #ifndef OS_STACK_WATERMARK
156 | #define OS_STACK_WATERMARK 1
157 | #endif
158 |
159 | // Processor mode for Thread execution
160 | // <0=> Unprivileged mode
161 | // <1=> Privileged mode
162 | // Default: Privileged mode
163 | #ifndef OS_PRIVILEGE_MODE
164 | #define OS_PRIVILEGE_MODE 1
165 | #endif
166 |
167 | //
168 |
169 | // Timer Configuration
170 | // ======================
171 |
172 | // Object specific Memory allocation
173 | // Enables object specific memory allocation.
174 | #ifndef OS_TIMER_OBJ_MEM
175 | #define OS_TIMER_OBJ_MEM 0
176 | #endif
177 |
178 | // Number of Timer objects <1-1000>
179 | // Defines maximum number of objects that can be active at the same time.
180 | // Applies to objects with system provided memory for control blocks.
181 | #ifndef OS_TIMER_NUM
182 | #define OS_TIMER_NUM 1
183 | #endif
184 |
185 | //
186 |
187 | // Timer Thread Priority
188 | // <8=> Low
189 | // <16=> Below Normal <24=> Normal <32=> Above Normal
190 | // <40=> High
191 | // <48=> Realtime
192 | // Defines priority for timer thread
193 | // Default: High
194 | #ifndef OS_TIMER_THREAD_PRIO
195 | #define OS_TIMER_THREAD_PRIO 40
196 | #endif
197 |
198 | // Timer Thread Stack size [bytes] <0-1073741824:8>
199 | // Defines stack size for Timer thread.
200 | // May be set to 0 when timers are not used.
201 | // Default: 256
202 | #ifndef OS_TIMER_THREAD_STACK_SIZE
203 | #define OS_TIMER_THREAD_STACK_SIZE 256
204 | #endif
205 |
206 | // Timer Thread TrustZone Module Identifier
207 | // Defines TrustZone Thread Context Management Identifier.
208 | // Applies only to cores with TrustZone technology.
209 | // Default: 0 (not used)
210 | #ifndef OS_TIMER_THREAD_TZ_MOD_ID
211 | #define OS_TIMER_THREAD_TZ_MOD_ID 0
212 | #endif
213 |
214 | // Timer Callback Queue entries <0-256>
215 | // Number of concurrent active timer callback functions.
216 | // May be set to 0 when timers are not used.
217 | // Default: 4
218 | #ifndef OS_TIMER_CB_QUEUE
219 | #define OS_TIMER_CB_QUEUE 4
220 | #endif
221 |
222 | //
223 |
224 | // Event Flags Configuration
225 | // ============================
226 |
227 | // Object specific Memory allocation
228 | // Enables object specific memory allocation.
229 | #ifndef OS_EVFLAGS_OBJ_MEM
230 | #define OS_EVFLAGS_OBJ_MEM 0
231 | #endif
232 |
233 | // Number of Event Flags objects <1-1000>
234 | // Defines maximum number of objects that can be active at the same time.
235 | // Applies to objects with system provided memory for control blocks.
236 | #ifndef OS_EVFLAGS_NUM
237 | #define OS_EVFLAGS_NUM 1
238 | #endif
239 |
240 | //
241 |
242 | //
243 |
244 | // Mutex Configuration
245 | // ======================
246 |
247 | // Object specific Memory allocation
248 | // Enables object specific memory allocation.
249 | #ifndef OS_MUTEX_OBJ_MEM
250 | #define OS_MUTEX_OBJ_MEM 0
251 | #endif
252 |
253 | // Number of Mutex objects <1-1000>
254 | // Defines maximum number of objects that can be active at the same time.
255 | // Applies to objects with system provided memory for control blocks.
256 | #ifndef OS_MUTEX_NUM
257 | #define OS_MUTEX_NUM 1
258 | #endif
259 |
260 | //
261 |
262 | //
263 |
264 | // Semaphore Configuration
265 | // ==========================
266 |
267 | // Object specific Memory allocation
268 | // Enables object specific memory allocation.
269 | #ifndef OS_SEMAPHORE_OBJ_MEM
270 | #define OS_SEMAPHORE_OBJ_MEM 0
271 | #endif
272 |
273 | // Number of Semaphore objects <1-1000>
274 | // Defines maximum number of objects that can be active at the same time.
275 | // Applies to objects with system provided memory for control blocks.
276 | #ifndef OS_SEMAPHORE_NUM
277 | #define OS_SEMAPHORE_NUM 1
278 | #endif
279 |
280 | //
281 |
282 | //
283 |
284 | // Memory Pool Configuration
285 | // ============================
286 |
287 | // Object specific Memory allocation
288 | // Enables object specific memory allocation.
289 | #ifndef OS_MEMPOOL_OBJ_MEM
290 | #define OS_MEMPOOL_OBJ_MEM 0
291 | #endif
292 |
293 | // Number of Memory Pool objects <1-1000>
294 | // Defines maximum number of objects that can be active at the same time.
295 | // Applies to objects with system provided memory for control blocks.
296 | #ifndef OS_MEMPOOL_NUM
297 | #define OS_MEMPOOL_NUM 1
298 | #endif
299 |
300 | // Data Storage Memory size [bytes] <0-1073741824:8>
301 | // Defines the combined data storage memory size.
302 | // Applies to objects with system provided memory for data storage.
303 | // Default: 0
304 | #ifndef OS_MEMPOOL_DATA_SIZE
305 | #define OS_MEMPOOL_DATA_SIZE 0
306 | #endif
307 |
308 | //
309 |
310 | //
311 |
312 | // Message Queue Configuration
313 | // ==============================
314 |
315 | // Object specific Memory allocation
316 | // Enables object specific memory allocation.
317 | #ifndef OS_MSGQUEUE_OBJ_MEM
318 | #define OS_MSGQUEUE_OBJ_MEM 0
319 | #endif
320 |
321 | // Number of Message Queue objects <1-1000>
322 | // Defines maximum number of objects that can be active at the same time.
323 | // Applies to objects with system provided memory for control blocks.
324 | #ifndef OS_MSGQUEUE_NUM
325 | #define OS_MSGQUEUE_NUM 1
326 | #endif
327 |
328 | // Data Storage Memory size [bytes] <0-1073741824:8>
329 | // Defines the combined data storage memory size.
330 | // Applies to objects with system provided memory for data storage.
331 | // Default: 0
332 | #ifndef OS_MSGQUEUE_DATA_SIZE
333 | #define OS_MSGQUEUE_DATA_SIZE 0
334 | #endif
335 |
336 | //
337 |
338 | //
339 |
340 | // Event Recorder Configuration
341 | // ===============================
342 |
343 | // Global Initialization
344 | // Initialize Event Recorder during 'osKernelInitialize'.
345 | #ifndef OS_EVR_INIT
346 | #define OS_EVR_INIT 0
347 | #endif
348 |
349 | // Start recording
350 | // Start event recording after initialization.
351 | #ifndef OS_EVR_START
352 | #define OS_EVR_START 1
353 | #endif
354 |
355 | // Global Event Filter Setup
356 | // Initial event filter settings applied to all components.
357 | // Error events
358 | // API function call events
359 | // Operation events
360 | // Detailed operation events
361 | //
362 | #ifndef OS_EVR_LEVEL
363 | #define OS_EVR_LEVEL 0x00U
364 | #endif
365 |
366 | // RTOS Event Filter Setup
367 | // Event filter settings for RTX components.
368 | // Only applicable if events for the respective component are generated.
369 |
370 | // Memory Management
371 | // Filter enable settings for Memory Management events.
372 | // Error events
373 | // API function call events
374 | // Operation events
375 | // Detailed operation events
376 | //
377 | #ifndef OS_EVR_MEMORY_FILTER
378 | #define OS_EVR_MEMORY_FILTER 0x81U
379 | #endif
380 |
381 | // Kernel
382 | // Filter enable settings for Kernel events.
383 | // Error events
384 | // API function call events
385 | // Operation events
386 | // Detailed operation events
387 | //
388 | #ifndef OS_EVR_KERNEL_FILTER
389 | #define OS_EVR_KERNEL_FILTER 0x81U
390 | #endif
391 |
392 | // Thread
393 | // Filter enable settings for Thread events.
394 | // Error events
395 | // API function call events
396 | // Operation events
397 | // Detailed operation events
398 | //
399 | #ifndef OS_EVR_THREAD_FILTER
400 | #define OS_EVR_THREAD_FILTER 0x85U
401 | #endif
402 |
403 | // Timer
404 | // Filter enable settings for Timer events.
405 | // Error events
406 | // API function call events
407 | // Operation events
408 | // Detailed operation events
409 | //
410 | #ifndef OS_EVR_TIMER_FILTER
411 | #define OS_EVR_TIMER_FILTER 0x81U
412 | #endif
413 |
414 | // Event Flags
415 | // Filter enable settings for Event Flags events.
416 | // Error events
417 | // API function call events
418 | // Operation events
419 | // Detailed operation events
420 | //
421 | #ifndef OS_EVR_EVFLAGS_FILTER
422 | #define OS_EVR_EVFLAGS_FILTER 0x81U
423 | #endif
424 |
425 | // Mutex
426 | // Filter enable settings for Mutex events.
427 | // Error events
428 | // API function call events
429 | // Operation events
430 | // Detailed operation events
431 | //
432 | #ifndef OS_EVR_MUTEX_FILTER
433 | #define OS_EVR_MUTEX_FILTER 0x81U
434 | #endif
435 |
436 | // Semaphore
437 | // Filter enable settings for Semaphore events.
438 | // Error events
439 | // API function call events
440 | // Operation events
441 | // Detailed operation events
442 | //
443 | #ifndef OS_EVR_SEMAPHORE_FILTER
444 | #define OS_EVR_SEMAPHORE_FILTER 0x81U
445 | #endif
446 |
447 | // Memory Pool
448 | // Filter enable settings for Memory Pool events.
449 | // Error events
450 | // API function call events
451 | // Operation events
452 | // Detailed operation events
453 | //
454 | #ifndef OS_EVR_MEMPOOL_FILTER
455 | #define OS_EVR_MEMPOOL_FILTER 0x81U
456 | #endif
457 |
458 | // Message Queue
459 | // Filter enable settings for Message Queue events.
460 | // Error events
461 | // API function call events
462 | // Operation events
463 | // Detailed operation events
464 | //
465 | #ifndef OS_EVR_MSGQUEUE_FILTER
466 | #define OS_EVR_MSGQUEUE_FILTER 0x81U
467 | #endif
468 |
469 | //
470 |
471 | //
472 |
473 | // RTOS Event Generation
474 | // Enables event generation for RTX components (requires RTX source variant).
475 |
476 | // Memory Management
477 | // Enables Memory Management event generation.
478 | #ifndef OS_EVR_MEMORY
479 | #define OS_EVR_MEMORY 1
480 | #endif
481 |
482 | // Kernel
483 | // Enables Kernel event generation.
484 | #ifndef OS_EVR_KERNEL
485 | #define OS_EVR_KERNEL 1
486 | #endif
487 |
488 | // Thread
489 | // Enables Thread event generation.
490 | #ifndef OS_EVR_THREAD
491 | #define OS_EVR_THREAD 1
492 | #endif
493 |
494 | // Timer
495 | // Enables Timer event generation.
496 | #ifndef OS_EVR_TIMER
497 | #define OS_EVR_TIMER 1
498 | #endif
499 |
500 | // Event Flags
501 | // Enables Event Flags event generation.
502 | #ifndef OS_EVR_EVFLAGS
503 | #define OS_EVR_EVFLAGS 1
504 | #endif
505 |
506 | // Mutex
507 | // Enables Mutex event generation.
508 | #ifndef OS_EVR_MUTEX
509 | #define OS_EVR_MUTEX 1
510 | #endif
511 |
512 | // Semaphore
513 | // Enables Semaphore event generation.
514 | #ifndef OS_EVR_SEMAPHORE
515 | #define OS_EVR_SEMAPHORE 1
516 | #endif
517 |
518 | // Memory Pool
519 | // Enables Memory Pool event generation.
520 | #ifndef OS_EVR_MEMPOOL
521 | #define OS_EVR_MEMPOOL 1
522 | #endif
523 |
524 | // Message Queue
525 | // Enables Message Queue event generation.
526 | #ifndef OS_EVR_MSGQUEUE
527 | #define OS_EVR_MSGQUEUE 1
528 | #endif
529 |
530 | //
531 |
532 | //
533 |
534 | // Number of Threads which use standard C/C++ library libspace
535 | // (when thread specific memory allocation is not used).
536 | #if (OS_THREAD_OBJ_MEM == 0)
537 | #define OS_THREAD_LIBSPACE_NUM 4
538 | #else
539 | #define OS_THREAD_LIBSPACE_NUM OS_THREAD_NUM
540 | #endif
541 |
542 | //------------- <<< end of configuration section >>> ---------------------------
543 |
544 | #endif // RTX_CONFIG_H_
545 |
--------------------------------------------------------------------------------
/RTE/Device/STM32F103RC/startup_stm32f10x_hd.s:
--------------------------------------------------------------------------------
1 | ;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
2 | ;* File Name : startup_stm32f10x_hd.s
3 | ;* Author : MCD Application Team
4 | ;* Version : V3.5.0
5 | ;* Date : 11-March-2011
6 | ;* Description : STM32F10x High Density Devices vector table for MDK-ARM
7 | ;* toolchain.
8 | ;* This module performs:
9 | ;* - Set the initial SP
10 | ;* - Set the initial PC == Reset_Handler
11 | ;* - Set the vector table entries with the exceptions ISR address
12 | ;* - Configure the clock system and also configure the external
13 | ;* SRAM mounted on STM3210E-EVAL board to be used as data
14 | ;* memory (optional, to be enabled by user)
15 | ;* - Branches to __main in the C library (which eventually
16 | ;* calls main()).
17 | ;* After Reset the CortexM3 processor is in Thread mode,
18 | ;* priority is Privileged, and the Stack is set to Main.
19 | ;* <<< Use Configuration Wizard in Context Menu >>>
20 | ;*******************************************************************************
21 | ; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
22 | ; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
23 | ; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
24 | ; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
25 | ; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
26 | ; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
27 | ;*******************************************************************************
28 |
29 | ; Amount of memory (in bytes) allocated for Stack
30 | ; Tailor this value to your application needs
31 | ; Stack Configuration
32 | ; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
33 | ;
34 |
35 | Stack_Size EQU 0x00000800
36 |
37 | AREA STACK, NOINIT, READWRITE, ALIGN=3
38 | Stack_Mem SPACE Stack_Size
39 | __initial_sp
40 |
41 | ; Heap Configuration
42 | ; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
43 | ;
44 |
45 | Heap_Size EQU 0x00000400
46 |
47 | AREA HEAP, NOINIT, READWRITE, ALIGN=3
48 | __heap_base
49 | Heap_Mem SPACE Heap_Size
50 | __heap_limit
51 |
52 | PRESERVE8
53 | THUMB
54 |
55 |
56 | ; Vector Table Mapped to Address 0 at Reset
57 | AREA RESET, DATA, READONLY
58 | EXPORT __Vectors
59 | EXPORT __Vectors_End
60 | EXPORT __Vectors_Size
61 |
62 | __Vectors DCD __initial_sp ; Top of Stack
63 | DCD Reset_Handler ; Reset Handler
64 | DCD NMI_Handler ; NMI Handler
65 | DCD HardFault_Handler ; Hard Fault Handler
66 | DCD MemManage_Handler ; MPU Fault Handler
67 | DCD BusFault_Handler ; Bus Fault Handler
68 | DCD UsageFault_Handler ; Usage Fault Handler
69 | DCD 0 ; Reserved
70 | DCD 0 ; Reserved
71 | DCD 0 ; Reserved
72 | DCD 0 ; Reserved
73 | DCD SVC_Handler ; SVCall Handler
74 | DCD DebugMon_Handler ; Debug Monitor Handler
75 | DCD 0 ; Reserved
76 | DCD PendSV_Handler ; PendSV Handler
77 | DCD SysTick_Handler ; SysTick Handler
78 |
79 | ; External Interrupts
80 | DCD WWDG_IRQHandler ; Window Watchdog
81 | DCD PVD_IRQHandler ; PVD through EXTI Line detect
82 | DCD TAMPER_IRQHandler ; Tamper
83 | DCD RTC_IRQHandler ; RTC
84 | DCD FLASH_IRQHandler ; Flash
85 | DCD RCC_IRQHandler ; RCC
86 | DCD EXTI0_IRQHandler ; EXTI Line 0
87 | DCD EXTI1_IRQHandler ; EXTI Line 1
88 | DCD EXTI2_IRQHandler ; EXTI Line 2
89 | DCD EXTI3_IRQHandler ; EXTI Line 3
90 | DCD EXTI4_IRQHandler ; EXTI Line 4
91 | DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
92 | DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
93 | DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
94 | DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
95 | DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
96 | DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
97 | DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
98 | DCD ADC1_2_IRQHandler ; ADC1 & ADC2
99 | DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
100 | DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
101 | DCD CAN1_RX1_IRQHandler ; CAN1 RX1
102 | DCD CAN1_SCE_IRQHandler ; CAN1 SCE
103 | DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
104 | DCD TIM1_BRK_IRQHandler ; TIM1 Break
105 | DCD TIM1_UP_IRQHandler ; TIM1 Update
106 | DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
107 | DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
108 | DCD TIM2_IRQHandler ; TIM2
109 | DCD TIM3_IRQHandler ; TIM3
110 | DCD TIM4_IRQHandler ; TIM4
111 | DCD I2C1_EV_IRQHandler ; I2C1 Event
112 | DCD I2C1_ER_IRQHandler ; I2C1 Error
113 | DCD I2C2_EV_IRQHandler ; I2C2 Event
114 | DCD I2C2_ER_IRQHandler ; I2C2 Error
115 | DCD SPI1_IRQHandler ; SPI1
116 | DCD SPI2_IRQHandler ; SPI2
117 | DCD USART1_IRQHandler ; USART1
118 | DCD USART2_IRQHandler ; USART2
119 | DCD USART3_IRQHandler ; USART3
120 | DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
121 | DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
122 | DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
123 | DCD TIM8_BRK_IRQHandler ; TIM8 Break
124 | DCD TIM8_UP_IRQHandler ; TIM8 Update
125 | DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation
126 | DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
127 | DCD ADC3_IRQHandler ; ADC3
128 | DCD FSMC_IRQHandler ; FSMC
129 | DCD SDIO_IRQHandler ; SDIO
130 | DCD TIM5_IRQHandler ; TIM5
131 | DCD SPI3_IRQHandler ; SPI3
132 | DCD UART4_IRQHandler ; UART4
133 | DCD UART5_IRQHandler ; UART5
134 | DCD TIM6_IRQHandler ; TIM6
135 | DCD TIM7_IRQHandler ; TIM7
136 | DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
137 | DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
138 | DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
139 | DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5
140 | __Vectors_End
141 |
142 | __Vectors_Size EQU __Vectors_End - __Vectors
143 |
144 | AREA |.text|, CODE, READONLY
145 |
146 | ; Reset handler
147 | Reset_Handler PROC
148 | EXPORT Reset_Handler [WEAK]
149 | IMPORT __main
150 | IMPORT SystemInit
151 | LDR R0, =SystemInit
152 | BLX R0
153 | LDR R0, =__main
154 | BX R0
155 | ENDP
156 |
157 | ; Dummy Exception Handlers (infinite loops which can be modified)
158 |
159 | NMI_Handler PROC
160 | EXPORT NMI_Handler [WEAK]
161 | B .
162 | ENDP
163 | HardFault_Handler\
164 | PROC
165 | EXPORT HardFault_Handler [WEAK]
166 | B .
167 | ENDP
168 | MemManage_Handler\
169 | PROC
170 | EXPORT MemManage_Handler [WEAK]
171 | B .
172 | ENDP
173 | BusFault_Handler\
174 | PROC
175 | EXPORT BusFault_Handler [WEAK]
176 | B .
177 | ENDP
178 | UsageFault_Handler\
179 | PROC
180 | EXPORT UsageFault_Handler [WEAK]
181 | B .
182 | ENDP
183 | SVC_Handler PROC
184 | EXPORT SVC_Handler [WEAK]
185 | B .
186 | ENDP
187 | DebugMon_Handler\
188 | PROC
189 | EXPORT DebugMon_Handler [WEAK]
190 | B .
191 | ENDP
192 | PendSV_Handler PROC
193 | EXPORT PendSV_Handler [WEAK]
194 | B .
195 | ENDP
196 | SysTick_Handler PROC
197 | EXPORT SysTick_Handler [WEAK]
198 | B .
199 | ENDP
200 |
201 | Default_Handler PROC
202 |
203 | EXPORT WWDG_IRQHandler [WEAK]
204 | EXPORT PVD_IRQHandler [WEAK]
205 | EXPORT TAMPER_IRQHandler [WEAK]
206 | EXPORT RTC_IRQHandler [WEAK]
207 | EXPORT FLASH_IRQHandler [WEAK]
208 | EXPORT RCC_IRQHandler [WEAK]
209 | EXPORT EXTI0_IRQHandler [WEAK]
210 | EXPORT EXTI1_IRQHandler [WEAK]
211 | EXPORT EXTI2_IRQHandler [WEAK]
212 | EXPORT EXTI3_IRQHandler [WEAK]
213 | EXPORT EXTI4_IRQHandler [WEAK]
214 | EXPORT DMA1_Channel1_IRQHandler [WEAK]
215 | EXPORT DMA1_Channel2_IRQHandler [WEAK]
216 | EXPORT DMA1_Channel3_IRQHandler [WEAK]
217 | EXPORT DMA1_Channel4_IRQHandler [WEAK]
218 | EXPORT DMA1_Channel5_IRQHandler [WEAK]
219 | EXPORT DMA1_Channel6_IRQHandler [WEAK]
220 | EXPORT DMA1_Channel7_IRQHandler [WEAK]
221 | EXPORT ADC1_2_IRQHandler [WEAK]
222 | EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK]
223 | EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK]
224 | EXPORT CAN1_RX1_IRQHandler [WEAK]
225 | EXPORT CAN1_SCE_IRQHandler [WEAK]
226 | EXPORT EXTI9_5_IRQHandler [WEAK]
227 | EXPORT TIM1_BRK_IRQHandler [WEAK]
228 | EXPORT TIM1_UP_IRQHandler [WEAK]
229 | EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
230 | EXPORT TIM1_CC_IRQHandler [WEAK]
231 | EXPORT TIM2_IRQHandler [WEAK]
232 | EXPORT TIM3_IRQHandler [WEAK]
233 | EXPORT TIM4_IRQHandler [WEAK]
234 | EXPORT I2C1_EV_IRQHandler [WEAK]
235 | EXPORT I2C1_ER_IRQHandler [WEAK]
236 | EXPORT I2C2_EV_IRQHandler [WEAK]
237 | EXPORT I2C2_ER_IRQHandler [WEAK]
238 | EXPORT SPI1_IRQHandler [WEAK]
239 | EXPORT SPI2_IRQHandler [WEAK]
240 | EXPORT USART1_IRQHandler [WEAK]
241 | EXPORT USART2_IRQHandler [WEAK]
242 | EXPORT USART3_IRQHandler [WEAK]
243 | EXPORT EXTI15_10_IRQHandler [WEAK]
244 | EXPORT RTCAlarm_IRQHandler [WEAK]
245 | EXPORT USBWakeUp_IRQHandler [WEAK]
246 | EXPORT TIM8_BRK_IRQHandler [WEAK]
247 | EXPORT TIM8_UP_IRQHandler [WEAK]
248 | EXPORT TIM8_TRG_COM_IRQHandler [WEAK]
249 | EXPORT TIM8_CC_IRQHandler [WEAK]
250 | EXPORT ADC3_IRQHandler [WEAK]
251 | EXPORT FSMC_IRQHandler [WEAK]
252 | EXPORT SDIO_IRQHandler [WEAK]
253 | EXPORT TIM5_IRQHandler [WEAK]
254 | EXPORT SPI3_IRQHandler [WEAK]
255 | EXPORT UART4_IRQHandler [WEAK]
256 | EXPORT UART5_IRQHandler [WEAK]
257 | EXPORT TIM6_IRQHandler [WEAK]
258 | EXPORT TIM7_IRQHandler [WEAK]
259 | EXPORT DMA2_Channel1_IRQHandler [WEAK]
260 | EXPORT DMA2_Channel2_IRQHandler [WEAK]
261 | EXPORT DMA2_Channel3_IRQHandler [WEAK]
262 | EXPORT DMA2_Channel4_5_IRQHandler [WEAK]
263 |
264 | WWDG_IRQHandler
265 | PVD_IRQHandler
266 | TAMPER_IRQHandler
267 | RTC_IRQHandler
268 | FLASH_IRQHandler
269 | RCC_IRQHandler
270 | EXTI0_IRQHandler
271 | EXTI1_IRQHandler
272 | EXTI2_IRQHandler
273 | EXTI3_IRQHandler
274 | EXTI4_IRQHandler
275 | DMA1_Channel1_IRQHandler
276 | DMA1_Channel2_IRQHandler
277 | DMA1_Channel3_IRQHandler
278 | DMA1_Channel4_IRQHandler
279 | DMA1_Channel5_IRQHandler
280 | DMA1_Channel6_IRQHandler
281 | DMA1_Channel7_IRQHandler
282 | ADC1_2_IRQHandler
283 | USB_HP_CAN1_TX_IRQHandler
284 | USB_LP_CAN1_RX0_IRQHandler
285 | CAN1_RX1_IRQHandler
286 | CAN1_SCE_IRQHandler
287 | EXTI9_5_IRQHandler
288 | TIM1_BRK_IRQHandler
289 | TIM1_UP_IRQHandler
290 | TIM1_TRG_COM_IRQHandler
291 | TIM1_CC_IRQHandler
292 | TIM2_IRQHandler
293 | TIM3_IRQHandler
294 | TIM4_IRQHandler
295 | I2C1_EV_IRQHandler
296 | I2C1_ER_IRQHandler
297 | I2C2_EV_IRQHandler
298 | I2C2_ER_IRQHandler
299 | SPI1_IRQHandler
300 | SPI2_IRQHandler
301 | USART1_IRQHandler
302 | USART2_IRQHandler
303 | USART3_IRQHandler
304 | EXTI15_10_IRQHandler
305 | RTCAlarm_IRQHandler
306 | USBWakeUp_IRQHandler
307 | TIM8_BRK_IRQHandler
308 | TIM8_UP_IRQHandler
309 | TIM8_TRG_COM_IRQHandler
310 | TIM8_CC_IRQHandler
311 | ADC3_IRQHandler
312 | FSMC_IRQHandler
313 | SDIO_IRQHandler
314 | TIM5_IRQHandler
315 | SPI3_IRQHandler
316 | UART4_IRQHandler
317 | UART5_IRQHandler
318 | TIM6_IRQHandler
319 | TIM7_IRQHandler
320 | DMA2_Channel1_IRQHandler
321 | DMA2_Channel2_IRQHandler
322 | DMA2_Channel3_IRQHandler
323 | DMA2_Channel4_5_IRQHandler
324 | B .
325 |
326 | ENDP
327 |
328 | ALIGN
329 |
330 | ;*******************************************************************************
331 | ; User Stack and Heap initialization
332 | ;*******************************************************************************
333 | IF :DEF:__MICROLIB
334 |
335 | EXPORT __initial_sp
336 | EXPORT __heap_base
337 | EXPORT __heap_limit
338 |
339 | ELSE
340 |
341 | IMPORT __use_two_region_memory
342 | EXPORT __user_initial_stackheap
343 |
344 | __user_initial_stackheap
345 |
346 | LDR R0, = Heap_Mem
347 | LDR R1, =(Stack_Mem + Stack_Size)
348 | LDR R2, = (Heap_Mem + Heap_Size)
349 | LDR R3, = Stack_Mem
350 | BX LR
351 |
352 | ALIGN
353 |
354 | ENDIF
355 |
356 | END
357 |
358 | ;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
359 |
--------------------------------------------------------------------------------
/RTE/Device/STM32F103RC/stm32f10x_conf.h:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file Project/STM32F10x_StdPeriph_Template/stm32f10x_conf.h
4 | * @author MCD Application Team
5 | * @version V3.5.0
6 | * @date 08-April-2011
7 | * @brief Library configuration file.
8 | ******************************************************************************
9 | * @attention
10 | *
11 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
12 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
13 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
14 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
15 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
16 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
17 | *
18 | * © COPYRIGHT 2011 STMicroelectronics
19 | ******************************************************************************
20 | */
21 |
22 | /* Define to prevent recursive inclusion -------------------------------------*/
23 | #ifndef __STM32F10x_CONF_H
24 | #define __STM32F10x_CONF_H
25 |
26 | /* Run Time Environment will set specific #define for each selected module below */
27 | #include "RTE_Components.h"
28 |
29 | #ifdef RTE_DEVICE_STDPERIPH_ADC
30 | #include "stm32f10x_adc.h"
31 | #endif
32 | #ifdef RTE_DEVICE_STDPERIPH_BKP
33 | #include "stm32f10x_bkp.h"
34 | #endif
35 | #ifdef RTE_DEVICE_STDPERIPH_CAN
36 | #include "stm32f10x_can.h"
37 | #endif
38 | #ifdef RTE_DEVICE_STDPERIPH_CEC
39 | #include "stm32f10x_cec.h"
40 | #endif
41 | #ifdef RTE_DEVICE_STDPERIPH_CRC
42 | #include "stm32f10x_crc.h"
43 | #endif
44 | #ifdef RTE_DEVICE_STDPERIPH_DAC
45 | #include "stm32f10x_dac.h"
46 | #endif
47 | #ifdef RTE_DEVICE_STDPERIPH_DBGMCU
48 | #include "stm32f10x_dbgmcu.h"
49 | #endif
50 | #ifdef RTE_DEVICE_STDPERIPH_DMA
51 | #include "stm32f10x_dma.h"
52 | #endif
53 | #ifdef RTE_DEVICE_STDPERIPH_EXTI
54 | #include "stm32f10x_exti.h"
55 | #endif
56 | #ifdef RTE_DEVICE_STDPERIPH_FLASH
57 | #include "stm32f10x_flash.h"
58 | #endif
59 | #ifdef RTE_DEVICE_STDPERIPH_FSMC
60 | #include "stm32f10x_fsmc.h"
61 | #endif
62 | #ifdef RTE_DEVICE_STDPERIPH_GPIO
63 | #include "stm32f10x_gpio.h"
64 | #endif
65 | #ifdef RTE_DEVICE_STDPERIPH_I2C
66 | #include "stm32f10x_i2c.h"
67 | #endif
68 | #ifdef RTE_DEVICE_STDPERIPH_IWDG
69 | #include "stm32f10x_iwdg.h"
70 | #endif
71 | #ifdef RTE_DEVICE_STDPERIPH_PWR
72 | #include "stm32f10x_pwr.h"
73 | #endif
74 | #ifdef RTE_DEVICE_STDPERIPH_RCC
75 | #include "stm32f10x_rcc.h"
76 | #endif
77 | #ifdef RTE_DEVICE_STDPERIPH_RTC
78 | #include "stm32f10x_rtc.h"
79 | #endif
80 | #ifdef RTE_DEVICE_STDPERIPH_SDIO
81 | #include "stm32f10x_sdio.h"
82 | #endif
83 | #ifdef RTE_DEVICE_STDPERIPH_SPI
84 | #include "stm32f10x_spi.h"
85 | #endif
86 | #ifdef RTE_DEVICE_STDPERIPH_TIM
87 | #include "stm32f10x_tim.h"
88 | #endif
89 | #ifdef RTE_DEVICE_STDPERIPH_USART
90 | #include "stm32f10x_usart.h"
91 | #endif
92 | #ifdef RTE_DEVICE_STDPERIPH_WWDG
93 | #include "stm32f10x_wwdg.h"
94 | #endif
95 | #ifdef RTE_DEVICE_STDPERIPH_FRAMEWORK
96 | #include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
97 | #endif
98 |
99 | /* Exported types ------------------------------------------------------------*/
100 | /* Exported constants --------------------------------------------------------*/
101 | /* Uncomment the line below to expanse the "assert_param" macro in the
102 | Standard Peripheral Library drivers code */
103 | /* #define USE_FULL_ASSERT 1 */
104 |
105 | /* Exported macro ------------------------------------------------------------*/
106 | #ifdef USE_FULL_ASSERT
107 |
108 | /**
109 | * @brief The assert_param macro is used for function's parameters check.
110 | * @param expr: If expr is false, it calls assert_failed function which reports
111 | * the name of the source file and the source line number of the call
112 | * that failed. If expr is true, it returns no value.
113 | * @retval None
114 | */
115 | #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
116 | /* Exported functions ------------------------------------------------------- */
117 | void assert_failed(uint8_t* file, uint32_t line);
118 | #else
119 | #define assert_param(expr) ((void)0)
120 | #endif /* USE_FULL_ASSERT */
121 |
122 | #endif /* __STM32F10x_CONF_H */
123 |
124 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
125 |
--------------------------------------------------------------------------------
/RTE/Device/STM32F103RC/system_stm32f10x.c:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file system_stm32f10x.c
4 | * @author MCD Application Team
5 | * @version V3.5.0
6 | * @date 11-March-2011
7 | * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
8 | *
9 | * 1. This file provides two functions and one global variable to be called from
10 | * user application:
11 | * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
12 | * factors, AHB/APBx prescalers and Flash settings).
13 | * This function is called at startup just after reset and
14 | * before branch to main program. This call is made inside
15 | * the "startup_stm32f10x_xx.s" file.
16 | *
17 | * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
18 | * by the user application to setup the SysTick
19 | * timer or configure other parameters.
20 | *
21 | * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
22 | * be called whenever the core clock is changed
23 | * during program execution.
24 | *
25 | * 2. After each device reset the HSI (8 MHz) is used as system clock source.
26 | * Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
27 | * configure the system clock before to branch to main program.
28 | *
29 | * 3. If the system clock source selected by user fails to startup, the SystemInit()
30 | * function will do nothing and HSI still used as system clock source. User can
31 | * add some code to deal with this issue inside the SetSysClock() function.
32 | *
33 | * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
34 | * the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file.
35 | * When HSE is used as system clock source, directly or through PLL, and you
36 | * are using different crystal you have to adapt the HSE value to your own
37 | * configuration.
38 | *
39 | ******************************************************************************
40 | * @attention
41 | *
42 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
43 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
44 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
45 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
46 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
47 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
48 | *
49 | * © COPYRIGHT 2011 STMicroelectronics
50 | ******************************************************************************
51 | */
52 |
53 | /** @addtogroup CMSIS
54 | * @{
55 | */
56 |
57 | /** @addtogroup stm32f10x_system
58 | * @{
59 | */
60 |
61 | /** @addtogroup STM32F10x_System_Private_Includes
62 | * @{
63 | */
64 |
65 | #include "stm32f10x.h"
66 |
67 | /**
68 | * @}
69 | */
70 |
71 | /** @addtogroup STM32F10x_System_Private_TypesDefinitions
72 | * @{
73 | */
74 |
75 | /**
76 | * @}
77 | */
78 |
79 | /** @addtogroup STM32F10x_System_Private_Defines
80 | * @{
81 | */
82 |
83 | /*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
84 | frequency (after reset the HSI is used as SYSCLK source)
85 |
86 | IMPORTANT NOTE:
87 | ==============
88 | 1. After each device reset the HSI is used as System clock source.
89 |
90 | 2. Please make sure that the selected System clock doesn't exceed your device's
91 | maximum frequency.
92 |
93 | 3. If none of the define below is enabled, the HSI is used as System clock
94 | source.
95 |
96 | 4. The System clock configuration functions provided within this file assume that:
97 | - For Low, Medium and High density Value line devices an external 8MHz
98 | crystal is used to drive the System clock.
99 | - For Low, Medium and High density devices an external 8MHz crystal is
100 | used to drive the System clock.
101 | - For Connectivity line devices an external 25MHz crystal is used to drive
102 | the System clock.
103 | If you are using different crystal you have to adapt those functions accordingly.
104 | */
105 |
106 | #if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
107 | /* #define SYSCLK_FREQ_HSE HSE_VALUE */
108 | #define SYSCLK_FREQ_24MHz 24000000
109 | #else
110 | /* #define SYSCLK_FREQ_HSE HSE_VALUE */
111 | /* #define SYSCLK_FREQ_24MHz 24000000 */
112 | /* #define SYSCLK_FREQ_36MHz 36000000 */
113 | /* #define SYSCLK_FREQ_48MHz 48000000 */
114 | /* #define SYSCLK_FREQ_56MHz 56000000 */
115 | #define SYSCLK_FREQ_72MHz 72000000
116 | #endif
117 |
118 | /*!< Uncomment the following line if you need to use external SRAM mounted
119 | on STM3210E-EVAL board (STM32 High density and XL-density devices) or on
120 | STM32100E-EVAL board (STM32 High-density value line devices) as data memory */
121 | #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
122 | /* #define DATA_IN_ExtSRAM */
123 | #endif
124 |
125 | /*!< Uncomment the following line if you need to relocate your vector Table in
126 | Internal SRAM. */
127 | /* #define VECT_TAB_SRAM */
128 | #define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field.
129 | This value must be a multiple of 0x200. */
130 |
131 |
132 | /**
133 | * @}
134 | */
135 |
136 | /** @addtogroup STM32F10x_System_Private_Macros
137 | * @{
138 | */
139 |
140 | /**
141 | * @}
142 | */
143 |
144 | /** @addtogroup STM32F10x_System_Private_Variables
145 | * @{
146 | */
147 |
148 | /*******************************************************************************
149 | * Clock Definitions
150 | *******************************************************************************/
151 | #ifdef SYSCLK_FREQ_HSE
152 | uint32_t SystemCoreClock = SYSCLK_FREQ_HSE; /*!< System Clock Frequency (Core Clock) */
153 | #elif defined SYSCLK_FREQ_24MHz
154 | uint32_t SystemCoreClock = SYSCLK_FREQ_24MHz; /*!< System Clock Frequency (Core Clock) */
155 | #elif defined SYSCLK_FREQ_36MHz
156 | uint32_t SystemCoreClock = SYSCLK_FREQ_36MHz; /*!< System Clock Frequency (Core Clock) */
157 | #elif defined SYSCLK_FREQ_48MHz
158 | uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz; /*!< System Clock Frequency (Core Clock) */
159 | #elif defined SYSCLK_FREQ_56MHz
160 | uint32_t SystemCoreClock = SYSCLK_FREQ_56MHz; /*!< System Clock Frequency (Core Clock) */
161 | #elif defined SYSCLK_FREQ_72MHz
162 | uint32_t SystemCoreClock = SYSCLK_FREQ_72MHz; /*!< System Clock Frequency (Core Clock) */
163 | #else /*!< HSI Selected as System Clock source */
164 | uint32_t SystemCoreClock = HSI_VALUE; /*!< System Clock Frequency (Core Clock) */
165 | #endif
166 |
167 | __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
168 | /**
169 | * @}
170 | */
171 |
172 | /** @addtogroup STM32F10x_System_Private_FunctionPrototypes
173 | * @{
174 | */
175 |
176 | static void SetSysClock(void);
177 |
178 | #ifdef SYSCLK_FREQ_HSE
179 | static void SetSysClockToHSE(void);
180 | #elif defined SYSCLK_FREQ_24MHz
181 | static void SetSysClockTo24(void);
182 | #elif defined SYSCLK_FREQ_36MHz
183 | static void SetSysClockTo36(void);
184 | #elif defined SYSCLK_FREQ_48MHz
185 | static void SetSysClockTo48(void);
186 | #elif defined SYSCLK_FREQ_56MHz
187 | static void SetSysClockTo56(void);
188 | #elif defined SYSCLK_FREQ_72MHz
189 | static void SetSysClockTo72(void);
190 | #endif
191 |
192 | #ifdef DATA_IN_ExtSRAM
193 | static void SystemInit_ExtMemCtl(void);
194 | #endif /* DATA_IN_ExtSRAM */
195 |
196 | /**
197 | * @}
198 | */
199 |
200 | /** @addtogroup STM32F10x_System_Private_Functions
201 | * @{
202 | */
203 |
204 | /**
205 | * @brief Setup the microcontroller system
206 | * Initialize the Embedded Flash Interface, the PLL and update the
207 | * SystemCoreClock variable.
208 | * @note This function should be used only after reset.
209 | * @param None
210 | * @retval None
211 | */
212 | void SystemInit (void)
213 | {
214 | /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
215 | /* Set HSION bit */
216 | RCC->CR |= (uint32_t)0x00000001;
217 |
218 | /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
219 | #ifndef STM32F10X_CL
220 | RCC->CFGR &= (uint32_t)0xF8FF0000;
221 | #else
222 | RCC->CFGR &= (uint32_t)0xF0FF0000;
223 | #endif /* STM32F10X_CL */
224 |
225 | /* Reset HSEON, CSSON and PLLON bits */
226 | RCC->CR &= (uint32_t)0xFEF6FFFF;
227 |
228 | /* Reset HSEBYP bit */
229 | RCC->CR &= (uint32_t)0xFFFBFFFF;
230 |
231 | /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
232 | RCC->CFGR &= (uint32_t)0xFF80FFFF;
233 |
234 | #ifdef STM32F10X_CL
235 | /* Reset PLL2ON and PLL3ON bits */
236 | RCC->CR &= (uint32_t)0xEBFFFFFF;
237 |
238 | /* Disable all interrupts and clear pending bits */
239 | RCC->CIR = 0x00FF0000;
240 |
241 | /* Reset CFGR2 register */
242 | RCC->CFGR2 = 0x00000000;
243 | #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
244 | /* Disable all interrupts and clear pending bits */
245 | RCC->CIR = 0x009F0000;
246 |
247 | /* Reset CFGR2 register */
248 | RCC->CFGR2 = 0x00000000;
249 | #else
250 | /* Disable all interrupts and clear pending bits */
251 | RCC->CIR = 0x009F0000;
252 | #endif /* STM32F10X_CL */
253 |
254 | #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
255 | #ifdef DATA_IN_ExtSRAM
256 | SystemInit_ExtMemCtl();
257 | #endif /* DATA_IN_ExtSRAM */
258 | #endif
259 |
260 | /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
261 | /* Configure the Flash Latency cycles and enable prefetch buffer */
262 | SetSysClock();
263 |
264 | #ifdef VECT_TAB_SRAM
265 | SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
266 | #else
267 | SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
268 | #endif
269 | }
270 |
271 | /**
272 | * @brief Update SystemCoreClock variable according to Clock Register Values.
273 | * The SystemCoreClock variable contains the core clock (HCLK), it can
274 | * be used by the user application to setup the SysTick timer or configure
275 | * other parameters.
276 | *
277 | * @note Each time the core clock (HCLK) changes, this function must be called
278 | * to update SystemCoreClock variable value. Otherwise, any configuration
279 | * based on this variable will be incorrect.
280 | *
281 | * @note - The system frequency computed by this function is not the real
282 | * frequency in the chip. It is calculated based on the predefined
283 | * constant and the selected clock source:
284 | *
285 | * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
286 | *
287 | * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
288 | *
289 | * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
290 | * or HSI_VALUE(*) multiplied by the PLL factors.
291 | *
292 | * (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
293 | * 8 MHz) but the real value may vary depending on the variations
294 | * in voltage and temperature.
295 | *
296 | * (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
297 | * 8 MHz or 25 MHz, depedning on the product used), user has to ensure
298 | * that HSE_VALUE is same as the real frequency of the crystal used.
299 | * Otherwise, this function may have wrong result.
300 | *
301 | * - The result of this function could be not correct when using fractional
302 | * value for HSE crystal.
303 | * @param None
304 | * @retval None
305 | */
306 | void SystemCoreClockUpdate (void)
307 | {
308 | uint32_t tmp = 0, pllmull = 0, pllsource = 0;
309 |
310 | #ifdef STM32F10X_CL
311 | uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
312 | #endif /* STM32F10X_CL */
313 |
314 | #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
315 | uint32_t prediv1factor = 0;
316 | #endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
317 |
318 | /* Get SYSCLK source -------------------------------------------------------*/
319 | tmp = RCC->CFGR & RCC_CFGR_SWS;
320 |
321 | switch (tmp)
322 | {
323 | case 0x00: /* HSI used as system clock */
324 | SystemCoreClock = HSI_VALUE;
325 | break;
326 | case 0x04: /* HSE used as system clock */
327 | SystemCoreClock = HSE_VALUE;
328 | break;
329 | case 0x08: /* PLL used as system clock */
330 |
331 | /* Get PLL clock source and multiplication factor ----------------------*/
332 | pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
333 | pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
334 |
335 | #ifndef STM32F10X_CL
336 | pllmull = ( pllmull >> 18) + 2;
337 |
338 | if (pllsource == 0x00)
339 | {
340 | /* HSI oscillator clock divided by 2 selected as PLL clock entry */
341 | SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
342 | }
343 | else
344 | {
345 | #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
346 | prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
347 | /* HSE oscillator clock selected as PREDIV1 clock entry */
348 | SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
349 | #else
350 | /* HSE selected as PLL clock entry */
351 | if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
352 | {/* HSE oscillator clock divided by 2 */
353 | SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
354 | }
355 | else
356 | {
357 | SystemCoreClock = HSE_VALUE * pllmull;
358 | }
359 | #endif
360 | }
361 | #else
362 | pllmull = pllmull >> 18;
363 |
364 | if (pllmull != 0x0D)
365 | {
366 | pllmull += 2;
367 | }
368 | else
369 | { /* PLL multiplication factor = PLL input clock * 6.5 */
370 | pllmull = 13 / 2;
371 | }
372 |
373 | if (pllsource == 0x00)
374 | {
375 | /* HSI oscillator clock divided by 2 selected as PLL clock entry */
376 | SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
377 | }
378 | else
379 | {/* PREDIV1 selected as PLL clock entry */
380 |
381 | /* Get PREDIV1 clock source and division factor */
382 | prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
383 | prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
384 |
385 | if (prediv1source == 0)
386 | {
387 | /* HSE oscillator clock selected as PREDIV1 clock entry */
388 | SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
389 | }
390 | else
391 | {/* PLL2 clock selected as PREDIV1 clock entry */
392 |
393 | /* Get PREDIV2 division factor and PLL2 multiplication factor */
394 | prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
395 | pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2;
396 | SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
397 | }
398 | }
399 | #endif /* STM32F10X_CL */
400 | break;
401 |
402 | default:
403 | SystemCoreClock = HSI_VALUE;
404 | break;
405 | }
406 |
407 | /* Compute HCLK clock frequency ----------------*/
408 | /* Get HCLK prescaler */
409 | tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
410 | /* HCLK clock frequency */
411 | SystemCoreClock >>= tmp;
412 | }
413 |
414 | /**
415 | * @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
416 | * @param None
417 | * @retval None
418 | */
419 | static void SetSysClock(void)
420 | {
421 | #ifdef SYSCLK_FREQ_HSE
422 | SetSysClockToHSE();
423 | #elif defined SYSCLK_FREQ_24MHz
424 | SetSysClockTo24();
425 | #elif defined SYSCLK_FREQ_36MHz
426 | SetSysClockTo36();
427 | #elif defined SYSCLK_FREQ_48MHz
428 | SetSysClockTo48();
429 | #elif defined SYSCLK_FREQ_56MHz
430 | SetSysClockTo56();
431 | #elif defined SYSCLK_FREQ_72MHz
432 | SetSysClockTo72();
433 | #endif
434 |
435 | /* If none of the define above is enabled, the HSI is used as System clock
436 | source (default after reset) */
437 | }
438 |
439 | /**
440 | * @brief Setup the external memory controller. Called in startup_stm32f10x.s
441 | * before jump to __main
442 | * @param None
443 | * @retval None
444 | */
445 | #ifdef DATA_IN_ExtSRAM
446 | /**
447 | * @brief Setup the external memory controller.
448 | * Called in startup_stm32f10x_xx.s/.c before jump to main.
449 | * This function configures the external SRAM mounted on STM3210E-EVAL
450 | * board (STM32 High density devices). This SRAM will be used as program
451 | * data memory (including heap and stack).
452 | * @param None
453 | * @retval None
454 | */
455 | void SystemInit_ExtMemCtl(void)
456 | {
457 | /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
458 | required, then adjust the Register Addresses */
459 |
460 | /* Enable FSMC clock */
461 | RCC->AHBENR = 0x00000114;
462 |
463 | /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
464 | RCC->APB2ENR = 0x000001E0;
465 |
466 | /* --------------- SRAM Data lines, NOE and NWE configuration ---------------*/
467 | /*---------------- SRAM Address lines configuration -------------------------*/
468 | /*---------------- NOE and NWE configuration --------------------------------*/
469 | /*---------------- NE3 configuration ----------------------------------------*/
470 | /*---------------- NBL0, NBL1 configuration ---------------------------------*/
471 |
472 | GPIOD->CRL = 0x44BB44BB;
473 | GPIOD->CRH = 0xBBBBBBBB;
474 |
475 | GPIOE->CRL = 0xB44444BB;
476 | GPIOE->CRH = 0xBBBBBBBB;
477 |
478 | GPIOF->CRL = 0x44BBBBBB;
479 | GPIOF->CRH = 0xBBBB4444;
480 |
481 | GPIOG->CRL = 0x44BBBBBB;
482 | GPIOG->CRH = 0x44444B44;
483 |
484 | /*---------------- FSMC Configuration ---------------------------------------*/
485 | /*---------------- Enable FSMC Bank1_SRAM Bank ------------------------------*/
486 |
487 | FSMC_Bank1->BTCR[4] = 0x00001011;
488 | FSMC_Bank1->BTCR[5] = 0x00000200;
489 | }
490 | #endif /* DATA_IN_ExtSRAM */
491 |
492 | #ifdef SYSCLK_FREQ_HSE
493 | /**
494 | * @brief Selects HSE as System clock source and configure HCLK, PCLK2
495 | * and PCLK1 prescalers.
496 | * @note This function should be used only after reset.
497 | * @param None
498 | * @retval None
499 | */
500 | static void SetSysClockToHSE(void)
501 | {
502 | __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
503 |
504 | /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
505 | /* Enable HSE */
506 | RCC->CR |= ((uint32_t)RCC_CR_HSEON);
507 |
508 | /* Wait till HSE is ready and if Time out is reached exit */
509 | do
510 | {
511 | HSEStatus = RCC->CR & RCC_CR_HSERDY;
512 | StartUpCounter++;
513 | } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
514 |
515 | if ((RCC->CR & RCC_CR_HSERDY) != RESET)
516 | {
517 | HSEStatus = (uint32_t)0x01;
518 | }
519 | else
520 | {
521 | HSEStatus = (uint32_t)0x00;
522 | }
523 |
524 | if (HSEStatus == (uint32_t)0x01)
525 | {
526 |
527 | #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
528 | /* Enable Prefetch Buffer */
529 | FLASH->ACR |= FLASH_ACR_PRFTBE;
530 |
531 | /* Flash 0 wait state */
532 | FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
533 |
534 | #ifndef STM32F10X_CL
535 | FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
536 | #else
537 | if (HSE_VALUE <= 24000000)
538 | {
539 | FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
540 | }
541 | else
542 | {
543 | FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
544 | }
545 | #endif /* STM32F10X_CL */
546 | #endif
547 |
548 | /* HCLK = SYSCLK */
549 | RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
550 |
551 | /* PCLK2 = HCLK */
552 | RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
553 |
554 | /* PCLK1 = HCLK */
555 | RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
556 |
557 | /* Select HSE as system clock source */
558 | RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
559 | RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;
560 |
561 | /* Wait till HSE is used as system clock source */
562 | while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
563 | {
564 | }
565 | }
566 | else
567 | { /* If HSE fails to start-up, the application will have wrong clock
568 | configuration. User can add here some code to deal with this error */
569 | }
570 | }
571 | #elif defined SYSCLK_FREQ_24MHz
572 | /**
573 | * @brief Sets System clock frequency to 24MHz and configure HCLK, PCLK2
574 | * and PCLK1 prescalers.
575 | * @note This function should be used only after reset.
576 | * @param None
577 | * @retval None
578 | */
579 | static void SetSysClockTo24(void)
580 | {
581 | __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
582 |
583 | /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
584 | /* Enable HSE */
585 | RCC->CR |= ((uint32_t)RCC_CR_HSEON);
586 |
587 | /* Wait till HSE is ready and if Time out is reached exit */
588 | do
589 | {
590 | HSEStatus = RCC->CR & RCC_CR_HSERDY;
591 | StartUpCounter++;
592 | } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
593 |
594 | if ((RCC->CR & RCC_CR_HSERDY) != RESET)
595 | {
596 | HSEStatus = (uint32_t)0x01;
597 | }
598 | else
599 | {
600 | HSEStatus = (uint32_t)0x00;
601 | }
602 |
603 | if (HSEStatus == (uint32_t)0x01)
604 | {
605 | #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
606 | /* Enable Prefetch Buffer */
607 | FLASH->ACR |= FLASH_ACR_PRFTBE;
608 |
609 | /* Flash 0 wait state */
610 | FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
611 | FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
612 | #endif
613 |
614 | /* HCLK = SYSCLK */
615 | RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
616 |
617 | /* PCLK2 = HCLK */
618 | RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
619 |
620 | /* PCLK1 = HCLK */
621 | RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
622 |
623 | #ifdef STM32F10X_CL
624 | /* Configure PLLs ------------------------------------------------------*/
625 | /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */
626 | RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
627 | RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
628 | RCC_CFGR_PLLMULL6);
629 |
630 | /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
631 | /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
632 | RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
633 | RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
634 | RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
635 | RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
636 |
637 | /* Enable PLL2 */
638 | RCC->CR |= RCC_CR_PLL2ON;
639 | /* Wait till PLL2 is ready */
640 | while((RCC->CR & RCC_CR_PLL2RDY) == 0)
641 | {
642 | }
643 | #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
644 | /* PLL configuration: = (HSE / 2) * 6 = 24 MHz */
645 | RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
646 | RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
647 | #else
648 | /* PLL configuration: = (HSE / 2) * 6 = 24 MHz */
649 | RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
650 | RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
651 | #endif /* STM32F10X_CL */
652 |
653 | /* Enable PLL */
654 | RCC->CR |= RCC_CR_PLLON;
655 |
656 | /* Wait till PLL is ready */
657 | while((RCC->CR & RCC_CR_PLLRDY) == 0)
658 | {
659 | }
660 |
661 | /* Select PLL as system clock source */
662 | RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
663 | RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
664 |
665 | /* Wait till PLL is used as system clock source */
666 | while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
667 | {
668 | }
669 | }
670 | else
671 | { /* If HSE fails to start-up, the application will have wrong clock
672 | configuration. User can add here some code to deal with this error */
673 | }
674 | }
675 | #elif defined SYSCLK_FREQ_36MHz
676 | /**
677 | * @brief Sets System clock frequency to 36MHz and configure HCLK, PCLK2
678 | * and PCLK1 prescalers.
679 | * @note This function should be used only after reset.
680 | * @param None
681 | * @retval None
682 | */
683 | static void SetSysClockTo36(void)
684 | {
685 | __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
686 |
687 | /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
688 | /* Enable HSE */
689 | RCC->CR |= ((uint32_t)RCC_CR_HSEON);
690 |
691 | /* Wait till HSE is ready and if Time out is reached exit */
692 | do
693 | {
694 | HSEStatus = RCC->CR & RCC_CR_HSERDY;
695 | StartUpCounter++;
696 | } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
697 |
698 | if ((RCC->CR & RCC_CR_HSERDY) != RESET)
699 | {
700 | HSEStatus = (uint32_t)0x01;
701 | }
702 | else
703 | {
704 | HSEStatus = (uint32_t)0x00;
705 | }
706 |
707 | if (HSEStatus == (uint32_t)0x01)
708 | {
709 | /* Enable Prefetch Buffer */
710 | FLASH->ACR |= FLASH_ACR_PRFTBE;
711 |
712 | /* Flash 1 wait state */
713 | FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
714 | FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
715 |
716 | /* HCLK = SYSCLK */
717 | RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
718 |
719 | /* PCLK2 = HCLK */
720 | RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
721 |
722 | /* PCLK1 = HCLK */
723 | RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
724 |
725 | #ifdef STM32F10X_CL
726 | /* Configure PLLs ------------------------------------------------------*/
727 |
728 | /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */
729 | RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
730 | RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
731 | RCC_CFGR_PLLMULL9);
732 |
733 | /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
734 | /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
735 |
736 | RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
737 | RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
738 | RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
739 | RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
740 |
741 | /* Enable PLL2 */
742 | RCC->CR |= RCC_CR_PLL2ON;
743 | /* Wait till PLL2 is ready */
744 | while((RCC->CR & RCC_CR_PLL2RDY) == 0)
745 | {
746 | }
747 |
748 | #else
749 | /* PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
750 | RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
751 | RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
752 | #endif /* STM32F10X_CL */
753 |
754 | /* Enable PLL */
755 | RCC->CR |= RCC_CR_PLLON;
756 |
757 | /* Wait till PLL is ready */
758 | while((RCC->CR & RCC_CR_PLLRDY) == 0)
759 | {
760 | }
761 |
762 | /* Select PLL as system clock source */
763 | RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
764 | RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
765 |
766 | /* Wait till PLL is used as system clock source */
767 | while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
768 | {
769 | }
770 | }
771 | else
772 | { /* If HSE fails to start-up, the application will have wrong clock
773 | configuration. User can add here some code to deal with this error */
774 | }
775 | }
776 | #elif defined SYSCLK_FREQ_48MHz
777 | /**
778 | * @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2
779 | * and PCLK1 prescalers.
780 | * @note This function should be used only after reset.
781 | * @param None
782 | * @retval None
783 | */
784 | static void SetSysClockTo48(void)
785 | {
786 | __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
787 |
788 | /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
789 | /* Enable HSE */
790 | RCC->CR |= ((uint32_t)RCC_CR_HSEON);
791 |
792 | /* Wait till HSE is ready and if Time out is reached exit */
793 | do
794 | {
795 | HSEStatus = RCC->CR & RCC_CR_HSERDY;
796 | StartUpCounter++;
797 | } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
798 |
799 | if ((RCC->CR & RCC_CR_HSERDY) != RESET)
800 | {
801 | HSEStatus = (uint32_t)0x01;
802 | }
803 | else
804 | {
805 | HSEStatus = (uint32_t)0x00;
806 | }
807 |
808 | if (HSEStatus == (uint32_t)0x01)
809 | {
810 | /* Enable Prefetch Buffer */
811 | FLASH->ACR |= FLASH_ACR_PRFTBE;
812 |
813 | /* Flash 1 wait state */
814 | FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
815 | FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
816 |
817 | /* HCLK = SYSCLK */
818 | RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
819 |
820 | /* PCLK2 = HCLK */
821 | RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
822 |
823 | /* PCLK1 = HCLK */
824 | RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
825 |
826 | #ifdef STM32F10X_CL
827 | /* Configure PLLs ------------------------------------------------------*/
828 | /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
829 | /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
830 |
831 | RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
832 | RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
833 | RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
834 | RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
835 |
836 | /* Enable PLL2 */
837 | RCC->CR |= RCC_CR_PLL2ON;
838 | /* Wait till PLL2 is ready */
839 | while((RCC->CR & RCC_CR_PLL2RDY) == 0)
840 | {
841 | }
842 |
843 |
844 | /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */
845 | RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
846 | RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
847 | RCC_CFGR_PLLMULL6);
848 | #else
849 | /* PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
850 | RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
851 | RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
852 | #endif /* STM32F10X_CL */
853 |
854 | /* Enable PLL */
855 | RCC->CR |= RCC_CR_PLLON;
856 |
857 | /* Wait till PLL is ready */
858 | while((RCC->CR & RCC_CR_PLLRDY) == 0)
859 | {
860 | }
861 |
862 | /* Select PLL as system clock source */
863 | RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
864 | RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
865 |
866 | /* Wait till PLL is used as system clock source */
867 | while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
868 | {
869 | }
870 | }
871 | else
872 | { /* If HSE fails to start-up, the application will have wrong clock
873 | configuration. User can add here some code to deal with this error */
874 | }
875 | }
876 |
877 | #elif defined SYSCLK_FREQ_56MHz
878 | /**
879 | * @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2
880 | * and PCLK1 prescalers.
881 | * @note This function should be used only after reset.
882 | * @param None
883 | * @retval None
884 | */
885 | static void SetSysClockTo56(void)
886 | {
887 | __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
888 |
889 | /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
890 | /* Enable HSE */
891 | RCC->CR |= ((uint32_t)RCC_CR_HSEON);
892 |
893 | /* Wait till HSE is ready and if Time out is reached exit */
894 | do
895 | {
896 | HSEStatus = RCC->CR & RCC_CR_HSERDY;
897 | StartUpCounter++;
898 | } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
899 |
900 | if ((RCC->CR & RCC_CR_HSERDY) != RESET)
901 | {
902 | HSEStatus = (uint32_t)0x01;
903 | }
904 | else
905 | {
906 | HSEStatus = (uint32_t)0x00;
907 | }
908 |
909 | if (HSEStatus == (uint32_t)0x01)
910 | {
911 | /* Enable Prefetch Buffer */
912 | FLASH->ACR |= FLASH_ACR_PRFTBE;
913 |
914 | /* Flash 2 wait state */
915 | FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
916 | FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
917 |
918 | /* HCLK = SYSCLK */
919 | RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
920 |
921 | /* PCLK2 = HCLK */
922 | RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
923 |
924 | /* PCLK1 = HCLK */
925 | RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
926 |
927 | #ifdef STM32F10X_CL
928 | /* Configure PLLs ------------------------------------------------------*/
929 | /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
930 | /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
931 |
932 | RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
933 | RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
934 | RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
935 | RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
936 |
937 | /* Enable PLL2 */
938 | RCC->CR |= RCC_CR_PLL2ON;
939 | /* Wait till PLL2 is ready */
940 | while((RCC->CR & RCC_CR_PLL2RDY) == 0)
941 | {
942 | }
943 |
944 |
945 | /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */
946 | RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
947 | RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
948 | RCC_CFGR_PLLMULL7);
949 | #else
950 | /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
951 | RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
952 | RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
953 |
954 | #endif /* STM32F10X_CL */
955 |
956 | /* Enable PLL */
957 | RCC->CR |= RCC_CR_PLLON;
958 |
959 | /* Wait till PLL is ready */
960 | while((RCC->CR & RCC_CR_PLLRDY) == 0)
961 | {
962 | }
963 |
964 | /* Select PLL as system clock source */
965 | RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
966 | RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
967 |
968 | /* Wait till PLL is used as system clock source */
969 | while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
970 | {
971 | }
972 | }
973 | else
974 | { /* If HSE fails to start-up, the application will have wrong clock
975 | configuration. User can add here some code to deal with this error */
976 | }
977 | }
978 |
979 | #elif defined SYSCLK_FREQ_72MHz
980 | /**
981 | * @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2
982 | * and PCLK1 prescalers.
983 | * @note This function should be used only after reset.
984 | * @param None
985 | * @retval None
986 | */
987 | static void SetSysClockTo72(void)
988 | {
989 | __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
990 |
991 | /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
992 | /* Enable HSE */
993 | RCC->CR |= ((uint32_t)RCC_CR_HSEON);
994 |
995 | /* Wait till HSE is ready and if Time out is reached exit */
996 | do
997 | {
998 | HSEStatus = RCC->CR & RCC_CR_HSERDY;
999 | StartUpCounter++;
1000 | } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
1001 |
1002 | if ((RCC->CR & RCC_CR_HSERDY) != RESET)
1003 | {
1004 | HSEStatus = (uint32_t)0x01;
1005 | }
1006 | else
1007 | {
1008 | HSEStatus = (uint32_t)0x00;
1009 | }
1010 |
1011 | if (HSEStatus == (uint32_t)0x01)
1012 | {
1013 | /* Enable Prefetch Buffer */
1014 | FLASH->ACR |= FLASH_ACR_PRFTBE;
1015 |
1016 | /* Flash 2 wait state */
1017 | FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
1018 | FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
1019 |
1020 |
1021 | /* HCLK = SYSCLK */
1022 | RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
1023 |
1024 | /* PCLK2 = HCLK */
1025 | RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
1026 |
1027 | /* PCLK1 = HCLK */
1028 | RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
1029 |
1030 | #ifdef STM32F10X_CL
1031 | /* Configure PLLs ------------------------------------------------------*/
1032 | /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
1033 | /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
1034 |
1035 | RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
1036 | RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
1037 | RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
1038 | RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
1039 |
1040 | /* Enable PLL2 */
1041 | RCC->CR |= RCC_CR_PLL2ON;
1042 | /* Wait till PLL2 is ready */
1043 | while((RCC->CR & RCC_CR_PLL2RDY) == 0)
1044 | {
1045 | }
1046 |
1047 |
1048 | /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */
1049 | RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
1050 | RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
1051 | RCC_CFGR_PLLMULL9);
1052 | #else
1053 | /* PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
1054 | RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
1055 | RCC_CFGR_PLLMULL));
1056 | RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
1057 | #endif /* STM32F10X_CL */
1058 |
1059 | /* Enable PLL */
1060 | RCC->CR |= RCC_CR_PLLON;
1061 |
1062 | /* Wait till PLL is ready */
1063 | while((RCC->CR & RCC_CR_PLLRDY) == 0)
1064 | {
1065 | }
1066 |
1067 | /* Select PLL as system clock source */
1068 | RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
1069 | RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
1070 |
1071 | /* Wait till PLL is used as system clock source */
1072 | while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
1073 | {
1074 | }
1075 | }
1076 | else
1077 | { /* If HSE fails to start-up, the application will have wrong clock
1078 | configuration. User can add here some code to deal with this error */
1079 | }
1080 | }
1081 | #endif
1082 |
1083 | /**
1084 | * @}
1085 | */
1086 |
1087 | /**
1088 | * @}
1089 | */
1090 |
1091 | /**
1092 | * @}
1093 | */
1094 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
1095 |
--------------------------------------------------------------------------------
/RTE/_LittlevGL/RTE_Components.h:
--------------------------------------------------------------------------------
1 |
2 | /*
3 | * Auto generated Run-Time-Environment Configuration File
4 | * *** Do not modify ! ***
5 | *
6 | * Project: 'Lv_test'
7 | * Target: 'LittlevGL'
8 | */
9 |
10 | #ifndef RTE_COMPONENTS_H
11 | #define RTE_COMPONENTS_H
12 |
13 |
14 | /*
15 | * Define the Device Header File:
16 | */
17 | #define CMSIS_device_header "stm32f10x.h"
18 |
19 | /* ARM::CMSIS:RTOS2:Keil RTX5:Library:5.5.0 */
20 | #define RTE_CMSIS_RTOS2 /* CMSIS-RTOS2 */
21 | #define RTE_CMSIS_RTOS2_RTX5 /* CMSIS-RTOS2 Keil RTX5 */
22 | /* Keil::Device:StdPeriph Drivers:DMA:3.5.0 */
23 | #define RTE_DEVICE_STDPERIPH_DMA
24 | /* Keil::Device:StdPeriph Drivers:Framework:3.5.1 */
25 | #define RTE_DEVICE_STDPERIPH_FRAMEWORK
26 | /* Keil::Device:StdPeriph Drivers:GPIO:3.5.0 */
27 | #define RTE_DEVICE_STDPERIPH_GPIO
28 | /* Keil::Device:StdPeriph Drivers:RCC:3.5.0 */
29 | #define RTE_DEVICE_STDPERIPH_RCC
30 | /* Keil::Device:StdPeriph Drivers:SPI:3.5.0 */
31 | #define RTE_DEVICE_STDPERIPH_SPI
32 | /* Keil::Device:StdPeriph Drivers:TIM:3.5.0 */
33 | #define RTE_DEVICE_STDPERIPH_TIM
34 |
35 |
36 | #endif /* RTE_COMPONENTS_H */
37 |
--------------------------------------------------------------------------------
/RTE/_Target_1/RTE_Components.h:
--------------------------------------------------------------------------------
1 |
2 | /*
3 | * Auto generated Run-Time-Environment Component Configuration File
4 | * *** Do not modify ! ***
5 | *
6 | * Project: 'Lv_test'
7 | * Target: 'Target 1'
8 | */
9 |
10 | #ifndef RTE_COMPONENTS_H
11 | #define RTE_COMPONENTS_H
12 |
13 |
14 | /*
15 | * Define the Device Header File:
16 | */
17 | #define CMSIS_device_header "stm32f10x.h"
18 |
19 | #define RTE_CMSIS_RTOS2 /* CMSIS-RTOS2 */
20 | #define RTE_CMSIS_RTOS2_RTX5 /* CMSIS-RTOS2 Keil RTX5 */
21 | #define RTE_DEVICE_STDPERIPH_DMA
22 | #define RTE_DEVICE_STDPERIPH_FRAMEWORK
23 | #define RTE_DEVICE_STDPERIPH_GPIO
24 | #define RTE_DEVICE_STDPERIPH_RCC
25 | #define RTE_DEVICE_STDPERIPH_SPI
26 | #define RTE_DEVICE_STDPERIPH_TIM
27 |
28 | #endif /* RTE_COMPONENTS_H */
29 |
--------------------------------------------------------------------------------
/encoder/drv_encoder.c:
--------------------------------------------------------------------------------
1 | #include "cmsis_os2.h"
2 | #include
3 | #include
4 | #include
5 | #include
6 | #include
7 | #include
8 | #include "drv_encoder.h"
9 |
10 | #define NOREADY 0
11 | #define READY 1
12 | #define INIT 3
13 |
14 | volatile uint8_t encoder_status = INIT;
15 | volatile int16_t encoder_steps = 0;
16 | uint16_t PrescalerValue = 0;
17 |
18 | extern osEventFlagsId_t LVGL_rfr_evt_id;
19 |
20 | void TIM4_init(void)
21 | {
22 | GPIO_InitTypeDef gpio_cfg;
23 | TIM_TimeBaseInitTypeDef TIMER_InitStructure;
24 | TIM_ICInitTypeDef TIM_ICInitStructure;
25 | RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB, ENABLE);
26 | // PB7 (TIM4_CH2) (encoder pin A), PB6 (TIM4_CH1) (encoder pin B)
27 | gpio_cfg.GPIO_Mode = GPIO_Mode_IPU;
28 | gpio_cfg.GPIO_Pin = GPIO_Pin_6 | GPIO_Pin_7 | GPIO_Pin_5;
29 | gpio_cfg.GPIO_Speed = GPIO_Speed_2MHz;
30 | GPIO_Init(GPIOB, &gpio_cfg);
31 |
32 | RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM4, ENABLE);
33 | TIM_TimeBaseStructInit(&TIMER_InitStructure);
34 | // Impostiamo TIM_Period = 1. Il timer conta fino a 1. L'interrupt verrà richiamato ad ogni modifica della posizione dell'encoder
35 | TIMER_InitStructure.TIM_Period = 1;
36 | TIMER_InitStructure.TIM_CounterMode = TIM_CounterMode_Up | TIM_CounterMode_Down;
37 | TIM_TimeBaseInit(TIM4, &TIMER_InitStructure);
38 | /* -----------------------------------------------------------------------
39 | TIM3 Configuration: Encoder mode1:
40 |
41 | In this example TIM3 input clock (TIM3CLK) is set to APB1 clock (PCLK1).
42 | TIM3CLK = PCLK1
43 | PCLK1 = HCLK
44 | => TIM3CLK = HCLK = SystemCoreClock
45 |
46 | To get TIM3 counter clock at 6 MHz, the prescaler is computed as follows:
47 | Prescaler = (TIM3CLK / TIM3 counter clock) - 1
48 | Prescaler = ((SystemCoreClock) /6 MHz) - 1
49 | TIM3 is configured to interface with an encoder:
50 | - The encoder mode is encoder mode1: Counter counts up/down on TI2 rising edge
51 | depending on TI1 level
52 | - The Autoreload value is set to 399, so the encoder round is 400 TIM counter clock.
53 |
54 | Note:
55 | SystemCoreClock variable holds HCLK frequency and is defined in system_stm32f0xx.c file.
56 | Each time the core clock (HCLK) changes, user had to call SystemCoreClockUpdate()
57 | function to update SystemCoreClock variable value. Otherwise, any configuration
58 | based on this variable will be incorrect.
59 | ----------------------------------------------------------------------- */
60 |
61 | // PrescalerValue = (uint16_t) ((SystemCoreClock ) / 6000000) - 1;
62 | // TIM_PrescalerConfig(TIM4, PrescalerValue, TIM_PSCReloadMode_Immediate);
63 |
64 | //debounce filter
65 | TIM_ICInitStructure.TIM_Channel=TIM_Channel_1;
66 | TIM_ICInitStructure.TIM_ICFilter=0x0F;
67 | TIM_ICInit(TIM4,&TIM_ICInitStructure);
68 | TIM_ICInitStructure.TIM_Channel=TIM_Channel_2;
69 | TIM_ICInitStructure.TIM_ICFilter=0x0F;
70 | TIM_ICInit(TIM4,&TIM_ICInitStructure);
71 |
72 |
73 | TIM_EncoderInterfaceConfig(TIM4, TIM_EncoderMode_TI1, TIM_ICPolarity_Rising, TIM_ICPolarity_Rising);
74 | TIM_ITConfig(TIM4, TIM_IT_Update, ENABLE);
75 | TIM_Cmd(TIM4, ENABLE);
76 |
77 | NVIC_EnableIRQ(TIM4_IRQn);
78 | }
79 |
80 | void TIM4_IRQHandler(void)
81 | {
82 | static uint32_t delay;
83 |
84 | if (TIM_GetITStatus(TIM4, TIM_IT_Update) != RESET) {
85 | // Il primo trigger viene scartato. encoder_status == INIT può essere una sola volta
86 | if (encoder_status == INIT)
87 | encoder_status = NOREADY;
88 | else
89 | encoder_status = READY;
90 | //Il registro TIM3_CR1 bit TIM_CR1_DIR sarà la direzione di rotazione dell'encoder
91 | encoder_steps += (TIM4->CR1 & TIM_CR1_DIR ? -1 : 1);
92 | // debounce delay
93 | for (delay = 0; delay <= 500; delay++)
94 | __asm("nop");
95 | osEventFlagsSet(LVGL_rfr_evt_id, 0x0001); // LVGL Refresh
96 | TIM_ClearITPendingBit(TIM4, TIM_IT_Update);
97 | }
98 | }
99 |
100 | uint16_t TIM4_read(void)
101 | {
102 | int16_t count;
103 | if (encoder_status) {
104 | encoder_status = NOREADY;
105 | count = encoder_steps;
106 | encoder_steps = 0;
107 | return count;
108 | }
109 | else return 0;
110 | }
111 |
112 | uint8_t enc_pressed(void)
113 | {
114 | return GPIO_ReadInputDataBit ( GPIOB, GPIO_Pin_5);
115 | }
116 |
--------------------------------------------------------------------------------
/encoder/drv_encoder.h:
--------------------------------------------------------------------------------
1 |
2 | void TIM4_init(void);
3 | uint16_t TIM4_read(void);
4 | uint8_t enc_pressed (void);
5 |
6 |
--------------------------------------------------------------------------------
/encoder/encoder.c:
--------------------------------------------------------------------------------
1 | /**
2 | * @file XPT2046.c
3 | *
4 | */
5 |
6 | /*********************
7 | * INCLUDES
8 | *********************/
9 | #include "encoder.h"
10 | #include "drv_encoder.h"
11 | #include
12 | #if USE_ENCODER
13 |
14 | #include
15 | #include LV_DRV_INDEV_INCLUDE
16 | #include LV_DRV_DELAY_INCLUDE
17 |
18 | /*********************
19 | * DEFINES
20 | *********************/
21 |
22 | /**********************
23 | * TYPEDEFS
24 | **********************/
25 |
26 | /**********************
27 | * STATIC PROTOTYPES
28 | **********************/
29 |
30 | /**********************
31 | * STATIC VARIABLES
32 | **********************/
33 |
34 |
35 | /**********************
36 | * MACROS
37 | **********************/
38 |
39 | /**********************
40 | * GLOBAL FUNCTIONS
41 | **********************/
42 |
43 | /**
44 | * Initialize the ENCODER
45 | */
46 | void encoder_init(void)
47 | {
48 | TIM4_init();
49 | }
50 |
51 | /**
52 |
53 | */
54 | bool encoder_read (lv_indev_drv_t * drv, lv_indev_data_t*data)
55 | {
56 | data->enc_diff = TIM4_read();
57 | if(!enc_pressed()){
58 | data->state = LV_INDEV_STATE_PR;
59 | }
60 | else{
61 | data->state = LV_INDEV_STATE_REL;
62 | }
63 | // printf("ENC=%d BTN=%d\r\n",data->enc_diff, data->state);
64 | return false; /*No buffering so no more data read*/
65 | }
66 |
67 | /**********************
68 | * STATIC FUNCTIONS
69 | **********************/
70 | #endif
71 |
--------------------------------------------------------------------------------
/encoder/encoder.h:
--------------------------------------------------------------------------------
1 | /**
2 | * @file XPT2046.h
3 | *
4 | */
5 |
6 | #ifndef ENCODER_H
7 | #define ENCODER_H
8 |
9 | #ifdef __cplusplus
10 | extern "C" {
11 | #endif
12 |
13 | /*********************
14 | * INCLUDES
15 | *********************/
16 | #ifdef LV_CONF_INCLUDE_SIMPLE
17 | #include "lv_drv_conf.h"
18 | #else
19 | #include "lv_drv_conf.h"
20 | #endif
21 |
22 | #if USE_ENCODER
23 |
24 | #include
25 | #include
26 | #include "../lvgl/src/lv_hal/lv_hal_indev.h"
27 |
28 | /*********************
29 | * DEFINES
30 | *********************/
31 |
32 | /**********************
33 | * TYPEDEFS
34 | **********************/
35 |
36 | /**********************
37 | * GLOBAL PROTOTYPES
38 | **********************/
39 | void encoder_init(void);
40 | bool encoder_read(lv_indev_drv_t * drv, lv_indev_data_t*data);
41 |
42 | /**********************
43 | * MACROS
44 | **********************/
45 |
46 | #endif /* USE_XPT2046 */
47 |
48 | #ifdef __cplusplus
49 | } /* extern "C" */
50 | #endif
51 |
52 | #endif /* XPT2046_H */
53 |
--------------------------------------------------------------------------------
/encoder/lv_drv_conf.h:
--------------------------------------------------------------------------------
1 | /**
2 | * @file lv_drv_conf.h
3 | *
4 | */
5 |
6 | /*
7 | * COPY THIS FILE AS lv_drv_conf.h
8 | */
9 |
10 | #if 1 /*Set it to "1" to enable the content*/
11 |
12 | #ifndef LV_DRV_CONF_H
13 | #define LV_DRV_CONF_H
14 |
15 | #include "../lv_conf.h"
16 |
17 | /*********************
18 | * DELAY INTERFACE
19 | *********************/
20 | #define LV_DRV_DELAY_INCLUDE "../misc/delay.h" /*Dummy include by default*/
21 | #define LV_DRV_DELAY_US(us) delay_us(us) /*Delay the given number of microseconds*/
22 | #define LV_DRV_DELAY_MS(ms) delay_ms(ms) /*Delay the given number of milliseconds*/
23 |
24 | /*********************
25 | * DISPLAY INTERFACE
26 | *********************/
27 |
28 | /*------------
29 | * Common
30 | *------------*/
31 | #define LV_DRV_DISP_INCLUDE /*Dummy include by default*/
32 | #define LV_DRV_DISP_CMD_DATA(val) /*pin_x_set(val)*/ /*Set the command/data pin to 'val'*/
33 | #define LV_DRV_DISP_RST(val) /*pin_x_set(val)*/ /*Set the reset pin to 'val'*/
34 |
35 | /*---------
36 | * SPI
37 | *---------*/
38 | #define LV_DRV_DISP_SPI_CS(val) /*spi_cs_set(val)*/ /*Set the SPI's Chip select to 'val'*/
39 | #define LV_DRV_DISP_SPI_WR_BYTE(data) /*spi_wr(data)*/ /*Write a byte the SPI bus*/
40 | #define LV_DRV_DISP_SPI_WR_ARRAY(adr, n) /*spi_wr_mem(adr, n)*/ /*Write 'n' bytes to SPI bus from 'adr'*/
41 |
42 | /*------------------
43 | * Parallel port
44 | *-----------------*/
45 | #define LV_DRV_DISP_PAR_CS(val) /*par_cs_set(val)*/ /*Set the Parallel port's Chip select to 'val'*/
46 | #define LV_DRV_DISP_PAR_SLOW /*par_slow()*/ /*Set low speed on the parallel port*/
47 | #define LV_DRV_DISP_PAR_FAST /*par_fast()*/ /*Set high speed on the parallel port*/
48 | #define LV_DRV_DISP_PAR_WR_WORD(data) /*par_wr(data)*/ /*Write a word to the parallel port*/
49 | #define LV_DRV_DISP_PAR_WR_ARRAY(adr, n) /*par_wr_mem(adr,n)*/ /*Write 'n' bytes to Parallel ports from 'adr'*/
50 |
51 | /***************************
52 | * INPUT DEVICE INTERFACE
53 | ***************************/
54 |
55 | /*----------
56 | * Common
57 | *----------*/
58 | #define LV_DRV_INDEV_INCLUDE "drv_encoder.h" /*Dummy include by default*/
59 | #define LV_DRV_INDEV_RST(val) /*pin_x_set(val)*/ /*Set the reset pin to 'val'*/
60 | #define LV_DRV_INDEV_IRQ_READ encoder_read() /*pn_x_read()*/ /*Read the IRQ pin*/
61 |
62 | /*---------
63 | * SPI
64 | *---------*/
65 | #define LV_DRV_INDEV_SPI_CS(val) /*spi_cs_set(val)*/ /*Set the SPI's Chip select to 'val'*/
66 | #define LV_DRV_INDEV_SPI_XCHG_BYTE(data) 0 /*spi_xchg(val)*/ /*Write 'val' to SPI and give the read value*/
67 |
68 | /*---------
69 | * I2C
70 | *---------*/
71 | #define LV_DRV_INDEV_I2C_START /*i2c_start()*/ /*Make an I2C start*/
72 | #define LV_DRV_INDEV_I2C_STOP /*i2c_stop()*/ /*Make an I2C stop*/
73 | #define LV_DRV_INDEV_I2C_RESTART /*i2c_restart()*/ /*Make an I2C restart*/
74 | #define LV_DRV_INDEV_I2C_WR(data) /*i2c_wr(data)*/ /*Write a byte to the I1C bus*/
75 | #define LV_DRV_INDEV_I2C_READ(last_read) 0 /*i2c_rd()*/ /*Read a byte from the I2C bud*/
76 |
77 |
78 | /*********************
79 | * DISPLAY DRIVERS
80 | *********************/
81 |
82 | /*-------------------
83 | * Monitor of PC
84 | *-------------------*/
85 | #ifndef USE_MONITOR
86 | # define USE_MONITOR 0
87 | #endif
88 |
89 | #if USE_MONITOR
90 | # define MONITOR_HOR_RES LV_HOR_RES
91 | # define MONITOR_VER_RES LV_VER_RES
92 |
93 | /* Scale window by this factor (useful when simulating small screens) */
94 | # define MONITOR_ZOOM 1
95 |
96 | /* Used to test true double buffering with only address changing.
97 | * Set LV_VDB_SIZE = (LV_HOR_RES * LV_VER_RES) and LV_VDB_DOUBLE = 1 and LV_COLOR_DEPTH = 32" */
98 | # define MONITOR_DOUBLE_BUFFERED 0
99 |
100 | /*Eclipse: Visual Studio: */
101 | # define MONITOR_SDL_INCLUDE_PATH
102 |
103 | /*Different rendering might be used if running in a Virtual machine*/
104 | # define MONITOR_VIRTUAL_MACHINE 0
105 |
106 | /*Open two windows to test multi display support*/
107 | # define MONITOR_DUAL 0
108 | #endif
109 |
110 | /*-----------------------------------
111 | * Native Windows (including mouse)
112 | *----------------------------------*/
113 | #ifndef USE_WINDOWS
114 | # define USE_WINDOWS 0
115 | #endif
116 |
117 | #define USE_WINDOWS 0
118 | #if USE_WINDOWS
119 | # define WINDOW_HOR_RES 480
120 | # define WINDOW_VER_RES 320
121 | #endif
122 |
123 | /*----------------
124 | * SSD1963
125 | *--------------*/
126 | #ifndef USE_SSD1963
127 | # define USE_SSD1963 0
128 | #endif
129 |
130 | #if USE_SSD1963
131 | # define SSD1963_HOR_RES LV_HOR_RES
132 | # define SSD1963_VER_RES LV_VER_RES
133 | # define SSD1963_HT 531
134 | # define SSD1963_HPS 43
135 | # define SSD1963_LPS 8
136 | # define SSD1963_HPW 10
137 | # define SSD1963_VT 288
138 | # define SSD1963_VPS 12
139 | # define SSD1963_FPS 4
140 | # define SSD1963_VPW 10
141 | # define SSD1963_HS_NEG 0 /*Negative hsync*/
142 | # define SSD1963_VS_NEG 0 /*Negative vsync*/
143 | # define SSD1963_ORI 0 /*0, 90, 180, 270*/
144 | # define SSD1963_COLOR_DEPTH 16
145 | #endif
146 |
147 | /*----------------
148 | * R61581
149 | *--------------*/
150 | #ifndef USE_R61581
151 | # define USE_R61581 0
152 | #endif
153 |
154 | #if USE_R61581
155 | # define R61581_HOR_RES LV_HOR_RES
156 | # define R61581_VER_RES LV_VER_RES
157 | # define R61581_HSPL 0 /*HSYNC signal polarity*/
158 | # define R61581_HSL 10 /*HSYNC length (Not Implemented)*/
159 | # define R61581_HFP 10 /*Horitontal Front poarch (Not Implemented)*/
160 | # define R61581_HBP 10 /*Horitontal Back poarch (Not Implemented */
161 | # define R61581_VSPL 0 /*VSYNC signal polarity*/
162 | # define R61581_VSL 10 /*VSYNC length (Not Implemented)*/
163 | # define R61581_VFP 8 /*Vertical Front poarch*/
164 | # define R61581_VBP 8 /*Vertical Back poarch */
165 | # define R61581_DPL 0 /*DCLK signal polarity*/
166 | # define R61581_EPL 1 /*ENABLE signal polarity*/
167 | # define R61581_ORI 0 /*0, 180*/
168 | # define R61581_LV_COLOR_DEPTH 16 /*Fix 16 bit*/
169 | #endif
170 |
171 | /*------------------------------
172 | * ST7565 (Monochrome, low res.)
173 | *-----------------------------*/
174 | #ifndef USE_ST7565
175 | # define USE_ST7565 0
176 | #endif
177 |
178 | #if USE_ST7565
179 | /*No settings*/
180 | #endif /*USE_ST7565*/
181 |
182 | /*-----------------------------------------
183 | * Linux frame buffer device (/dev/fbx)
184 | *-----------------------------------------*/
185 | #ifndef USE_FBDEV
186 | # define USE_FBDEV 0
187 | #endif
188 |
189 | #if USE_FBDEV
190 | # define FBDEV_PATH "/dev/fb0"
191 | #endif
192 |
193 | /*********************
194 | * INPUT DEVICES
195 | *********************/
196 |
197 | /*--------------
198 | * XPT2046
199 | *--------------*/
200 | #ifndef USE_XPT2046
201 | # define USE_XPT2046 0
202 | #endif
203 |
204 | #if USE_XPT2046
205 | # define XPT2046_HOR_RES 480
206 | # define XPT2046_VER_RES 320
207 | # define XPT2046_X_MIN 200
208 | # define XPT2046_Y_MIN 200
209 | # define XPT2046_X_MAX 3800
210 | # define XPT2046_Y_MAX 3800
211 | # define XPT2046_AVG 4
212 | # define XPT2046_INV 0
213 | #endif
214 |
215 | /*-----------------
216 | * FT5406EE8
217 | *-----------------*/
218 | #ifndef USE_FT5406EE8
219 | # define USE_FT5406EE8 0
220 | #endif
221 |
222 | #if USE_FT5406EE8
223 | # define FT5406EE8_I2C_ADR 0x38 /*7 bit address*/
224 | #endif
225 |
226 | /*---------------
227 | * AD TOUCH
228 | *--------------*/
229 | #ifndef USE_AD_TOUCH
230 | # define USE_AD_TOUCH 0
231 | #endif
232 |
233 | #if USE_AD_TOUCH
234 | /*No settings*/
235 | #endif
236 |
237 |
238 | /*---------------------------------------
239 | * Mouse or touchpad on PC (using SDL)
240 | *-------------------------------------*/
241 | #ifndef USE_MOUSE
242 | # define USE_MOUSE 0
243 | #endif
244 |
245 | #if USE_MOUSE
246 | /*No settings*/
247 | #endif
248 |
249 | /*-------------------------------------------
250 | * Mousewheel as encoder on PC (using SDL)
251 | *------------------------------------------*/
252 | #ifndef USE_MOUSEWHEEL
253 | # define USE_MOUSEWHEEL 0
254 | #endif
255 |
256 | #if USE_MOUSEWHEEL
257 | /*No settings*/
258 | #endif
259 |
260 | /*-------------------------------------------------
261 | * Touchscreen as libinput interface (for Linux based systems)
262 | *------------------------------------------------*/
263 | #ifndef USE_LIBINPUT
264 | # define USE_LIBINPUT 0
265 | #endif
266 |
267 | #if USE_LIBINPUT
268 | # define LIBINPUT_NAME "/dev/input/event0" /*You can use the "evtest" Linux tool to get the list of devices and test them*/
269 | #endif /*USE_LIBINPUT*/
270 |
271 | /*-------------------------------------------------
272 | * Mouse or touchpad as evdev interface (for Linux based systems)
273 | *------------------------------------------------*/
274 | #ifndef USE_EVDEV
275 | # define USE_EVDEV 0
276 | #endif
277 |
278 | #if USE_EVDEV
279 | # define EVDEV_NAME "/dev/input/event0" /*You can use the "evtest" Linux tool to get the list of devices and test them*/
280 | # define EVDEV_SWAP_AXES 0 /*Swap the x and y axes of the touchscreen*/
281 |
282 | # define EVDEV_SCALE 0 /* Scale input, e.g. if touchscreen resolution does not match display resolution */
283 | # if EVDEV_SCALE
284 | # define EVDEV_SCALE_HOR_RES (4096) /* Horizontal resolution of touchscreen */
285 | # define EVDEV_SCALE_VER_RES (4096) /* Vertical resolution of touchscreen */
286 | # endif /*EVDEV_SCALE*/
287 |
288 | # define EVDEV_CALIBRATE 0 /*Scale and offset the touchscreen coordinates by using maximum and minimum values for each axis*/
289 | # if EVDEV_CALIBRATE
290 | # define EVDEV_HOR_MIN 3800 /*If EVDEV_XXX_MIN > EVDEV_XXX_MAX the XXX axis is automatically inverted*/
291 | # define EVDEV_HOR_MAX 200
292 | # define EVDEV_VER_MIN 200
293 | # define EVDEV_VER_MAX 3800
294 | # endif /*EVDEV_SCALE*/
295 | #endif /*USE_EVDEV*/
296 |
297 | /*-------------------------------
298 | * Keyboard of a PC (using SDL)
299 | *------------------------------*/
300 | #ifndef USE_KEYBOARD
301 | # define USE_KEYBOARD 0
302 | #endif
303 |
304 | #if USE_KEYBOARD
305 | /*No settings*/
306 | #endif
307 |
308 | /*-------------------------------
309 | * encoder
310 | *------------------------------*/
311 | #ifndef USE_ENCODER
312 | #define USE_ENCODER 1
313 | #endif
314 | #if USE_ENCODER
315 | /*No settings*/
316 | #endif
317 |
318 |
319 | #endif /*LV_DRV_CONF_H*/
320 |
321 | #endif /*End of "Content enable"*/
322 |
--------------------------------------------------------------------------------
/ili9341/commands.h:
--------------------------------------------------------------------------------
1 | #ifndef TEST2_COMMANDS_H
2 | #define TEST2_COMMANDS_H
3 |
4 | //
5 |
6 | /* Level 1 Commands */
7 | #define ILI9341_SWRESET 0x01 /* Software Reset */
8 | #define ILI9341_READ_DISPLAY_ID 0x04 /* Read display identification information */
9 | #define ILI9341_RDDST 0x09 /* Read Display Status */
10 | #define ILI9341_RDDPM 0x0A /* Read Display Power Mode */
11 | #define ILI9341_RDDMADCTL 0x0B /* Read Display MADCTL */
12 | #define ILI9341_RDDCOLMOD 0x0C /* Read Display Pixel Format */
13 | #define ILI9341_RDDIM 0x0D /* Read Display Image Format */
14 | #define ILI9341_RDDSM 0x0E /* Read Display Signal Mode */
15 | #define ILI9341_RDDSDR 0x0F /* Read Display Self-Diagnostic Result */
16 | #define ILI9341_SPLIN 0x10 /* Enter Sleep Mode */
17 | #define ILI9341_SLEEP_OUT 0x11 /* Sleep out register */
18 | #define ILI9341_PTLON 0x12 /* Partial Mode ON */
19 | #define ILI9341_NORMAL_MODE_ON 0x13 /* Normal Display Mode ON */
20 | #define ILI9341_DINVOFF 0x20 /* Display Inversion OFF */
21 | #define ILI9341_DINVON 0x21 /* Display Inversion ON */
22 | #define ILI9341_GAMMA 0x26 /* Gamma register */
23 | #define ILI9341_DISPLAY_OFF 0x28 /* Display off register */
24 | #define ILI9341_DISPLAY_ON 0x29 /* Display on register */
25 | #define ILI9341_COLUMN_ADDR 0x2A /* Colomn address register */
26 | #define ILI9341_PAGE_ADDR 0x2B /* Page address register */
27 | #define ILI9341_GRAM 0x2C /* GRAM register */
28 | #define ILI9341_RGBSET 0x2D /* Color SET */
29 | #define ILI9341_RAMRD 0x2E /* Memory Read */
30 | #define ILI9341_PLTAR 0x30 /* Partial Area */
31 | #define ILI9341_VSCRDEF 0x33 /* Vertical Scrolling Definition */
32 | #define ILI9341_TEOFF 0x34 /* Tearing Effect Line OFF */
33 | #define ILI9341_TEON 0x35 /* Tearing Effect Line ON */
34 | #define ILI9341_MAC 0x36 /* Memory Access Control register*/
35 | #define ILI9341_VSCRSADD 0x37 /* Vertical Scrolling Start Address */
36 | #define ILI9341_IDMOFF 0x38 /* Idle Mode OFF */
37 | #define ILI9341_IDMON 0x39 /* Idle Mode ON */
38 | #define ILI9341_PIXEL_FORMAT 0x3A /* Pixel Format register */
39 | #define ILI9341_WRITE_MEM_CONTINUE 0x3C /* Write Memory Continue */
40 | #define ILI9341_READ_MEM_CONTINUE 0x3E /* Read Memory Continue */
41 | #define ILI9341_SET_TEAR_SCANLINE 0x44 /* Set Tear Scanline */
42 | #define ILI9341_GET_SCANLINE 0x45 /* Get Scanline */
43 | #define ILI9341_WDB 0x51 /* Write Brightness Display register */
44 | #define ILI9341_RDDISBV 0x52 /* Read Display Brightness */
45 | #define ILI9341_WCD 0x53 /* Write Control Display register*/
46 | #define ILI9341_RDCTRLD 0x54 /* Read CTRL Display */
47 | #define ILI9341_WRCABC 0x55 /* Write Content Adaptive Brightness Control */
48 | #define ILI9341_RDCABC 0x56 /* Read Content Adaptive Brightness Control */
49 | #define ILI9341_WRITE_CABC 0x5E /* Write CABC Minimum Brightness */
50 | #define ILI9341_READ_CABC 0x5F /* Read CABC Minimum Brightness */
51 | #define ILI9341_READ_ID1 0xDA /* Read ID1 */
52 | #define ILI9341_READ_ID2 0xDB /* Read ID2 */
53 | #define ILI9341_READ_ID3 0xDC /* Read ID3 */
54 |
55 | /* Level 2 Commands */
56 | #define ILI9341_RGB_INTERFACE 0xB0 /* RGB Interface Signal Control */
57 | #define ILI9341_FRMCTR1 0xB1 /* Frame Rate Control (In Normal Mode) */
58 | #define ILI9341_FRMCTR2 0xB2 /* Frame Rate Control (In Idle Mode) */
59 | #define ILI9341_FRMCTR3 0xB3 /* Frame Rate Control (In Partial Mode) */
60 | #define ILI9341_INVTR 0xB4 /* Display Inversion Control */
61 | #define ILI9341_BPC 0xB5 /* Blanking Porch Control register */
62 | #define ILI9341_DFC 0xB6 /* Display Function Control register */
63 | #define ILI9341_ETMOD 0xB7 /* Entry Mode Set */
64 | #define ILI9341_BACKLIGHT1 0xB8 /* Backlight Control 1 */
65 | #define ILI9341_BACKLIGHT2 0xB9 /* Backlight Control 2 */
66 | #define ILI9341_BACKLIGHT3 0xBA /* Backlight Control 3 */
67 | #define ILI9341_BACKLIGHT4 0xBB /* Backlight Control 4 */
68 | #define ILI9341_BACKLIGHT5 0xBC /* Backlight Control 5 */
69 | #define ILI9341_BACKLIGHT7 0xBE /* Backlight Control 7 */
70 | #define ILI9341_BACKLIGHT8 0xBF /* Backlight Control 8 */
71 | #define ILI9341_POWER1 0xC0 /* Power Control 1 register */
72 | #define ILI9341_POWER2 0xC1 /* Power Control 2 register */
73 | #define ILI9341_VCOM1 0xC5 /* VCOM Control 1 register */
74 | #define ILI9341_VCOM2 0xC7 /* VCOM Control 2 register */
75 | #define ILI9341_NVMWR 0xD0 /* NV Memory Write */
76 | #define ILI9341_NVMPKEY 0xD1 /* NV Memory Protection Key */
77 | #define ILI9341_RDNVM 0xD2 /* NV Memory Status Read */
78 | #define ILI9341_READ_ID4 0xD3 /* Read ID4 */
79 | #define ILI9341_PGAMMA 0xE0 /* Positive Gamma Correction register */
80 | #define ILI9341_NGAMMA 0xE1 /* Negative Gamma Correction register */
81 | #define ILI9341_DGAMCTRL1 0xE2 /* Digital Gamma Control 1 */
82 | #define ILI9341_DGAMCTRL2 0xE3 /* Digital Gamma Control 2 */
83 | #define ILI9341_INTERFACE 0xF6 /* Interface control register */
84 |
85 | /* Extend register commands */
86 | #define ILI9341_POWERA 0xCB /* Power control A register */
87 | #define ILI9341_POWERB 0xCF /* Power control B register */
88 | #define ILI9341_DTCA 0xE8 /* Driver timing control A */
89 | #define ILI9341_DTCB 0xEA /* Driver timing control B */
90 | #define ILI9341_POWER_SEQ 0xED /* Power on sequence register */
91 | #define ILI9341_3GAMMA_EN 0xF2 /* 3 Gamma enable register */
92 | #define ILI9341_PRC 0xF7 /* Pump ratio control register */
93 |
94 | //
95 |
96 | //
97 |
98 | #define ORIENTATION_PORTRAIT 0x48
99 | #define ORIENTATION_LANDSCAPE 0x28
100 | #define ORIENTATION_PORTRAIT_MIRROR 0x88
101 | #define ORIENTATION_LANDSCAPE_MIRROR 0xE8
102 |
103 | //
104 |
105 | //
106 | #define ILI9341_PIXEL_WIDTH 240
107 | #define ILI9341_PIXEL_HEIGHT 320
108 | #define ILI9341_PIXEL_COUNT ILI9341_PIXEL_WIDTH * ILI9341_PIXEL_HEIGHT
109 | //
110 |
111 | #endif //TEST2_COMMANDS_H
112 |
--------------------------------------------------------------------------------
/ili9341/config.h:
--------------------------------------------------------------------------------
1 | #ifndef TEST1_CONFIG_H
2 | #define TEST1_CONFIG_H
3 |
4 | //
5 |
6 | #define TFT_LED_PIN GPIO_Pin_0
7 | #define TFT_RESET_PIN GPIO_Pin_2
8 | #define TFT_DC_PIN GPIO_Pin_3
9 | #define TFT_CS_PIN GPIO_Pin_4
10 |
11 | #define SPI_MASTER SPI1
12 | #define SPI_MASTER_CLK RCC_APB2Periph_SPI1
13 | #define SPI_MASTER_GPIO GPIOA
14 | #define SPI_MASTER_GPIO_CLK RCC_APB2Periph_GPIOA
15 | #define SPI_MASTER_PIN_NSS GPIO_Pin_4
16 | #define SPI_MASTER_PIN_SCK GPIO_Pin_5
17 | #define SPI_MASTER_PIN_MISO GPIO_Pin_6
18 | #define SPI_MASTER_PIN_MOSI GPIO_Pin_7
19 |
20 | //
21 |
22 | //
23 |
24 | #define BLACK 0x0000 /* 0, 0, 0 */
25 | #define NAVY 0x000F /* 0, 0, 128 */
26 | #define DGREEN 0x03E0 /* 0, 128, 0 */
27 | #define DCYAN 0x03EF /* 0, 128, 128 */
28 | #define MAROON 0x7800 /* 128, 0, 0 */
29 | #define PURPLE 0x780F /* 128, 0, 128 */
30 | #define OLIVE 0x7BE0 /* 128, 128, 0 */
31 | #define LGRAY 0xC618 /* 192, 192, 192 */
32 | #define DGRAY 0x7BEF /* 128, 128, 128 */
33 | #define BLUE 0x001F /* 0, 0, 255 */
34 | #define GREEN 0x07E0 /* 0, 255, 0 */
35 | #define CYAN 0x07FF /* 0, 255, 255 */
36 | #define RED 0xF800 /* 255, 0, 0 */
37 | #define MAGENTA 0xF81F /* 255, 0, 255 */
38 | #define YELLOW 0xFFE0 /* 255, 255, 0 */
39 | #define WHITE 0xFFFF /* 255, 255, 255 */
40 | #define ORANGE 0xFD20 /* 255, 165, 0 */
41 | #define GREENYELLOW 0xAFE5 /* 173, 255, 47 */
42 | #define BROWN 0XBC40 //
43 | #define BRRED 0XFC07 //
44 |
45 | //
46 |
47 | #endif //TEST1_CONFIG_H
48 |
--------------------------------------------------------------------------------
/ili9341/control.h:
--------------------------------------------------------------------------------
1 | #ifndef TEST2_CONTROL_H
2 | #define TEST2_CONTROL_H
3 |
4 | #include "config.h"
5 | #include "commands.h"
6 |
7 | //
8 | #define TFT_DC_SET GPIO_SetBits(GPIOA, TFT_DC_PIN);
9 | #define TFT_DC_RESET GPIO_ResetBits(GPIOA, TFT_DC_PIN);
10 |
11 | #define TFT_RST_SET GPIO_SetBits(GPIOA, TFT_RESET_PIN);
12 | #define TFT_RST_RESET GPIO_ResetBits(GPIOA, TFT_RESET_PIN);
13 |
14 | #define TFT_CS_SET GPIO_SetBits(GPIOA, TFT_CS_PIN);
15 | #define TFT_CS_RESET GPIO_ResetBits(GPIOA, TFT_CS_PIN);
16 |
17 | #define TFT_LED_SET GPIO_SetBits(GPIOA, TFT_LED_PIN);
18 | #define TFT_LED_RESET GPIO_ResetBits(GPIOA, TFT_LED_PIN);
19 | //
20 |
21 | #endif //TEST2_CONTROL_H
22 |
--------------------------------------------------------------------------------
/ili9341/core.c:
--------------------------------------------------------------------------------
1 | #include "core.h"
2 | //#include "cmsis_os2.h" // CMSIS RTOS header file
3 | #include "../misc/delay.h"
4 |
5 |
6 | static u16 screen_width = ILI9341_PIXEL_WIDTH,
7 | screen_height = ILI9341_PIXEL_HEIGHT;
8 |
9 | static const uint8_t init_commands[] = {
10 | 4, 0xEF, 0x03, 0x80, 0x02,
11 | 4, 0xCF, 0x00, 0xC1, 0x30,
12 | 5, 0xED, 0x64, 0x03, 0x12, 0x81,
13 | 4, 0xE8, 0x85, 0x00, 0x78,
14 | 6, 0xCB, 0x39, 0x2C, 0x00, 0x34, 0x02,
15 | 2, 0xF7, 0x20,
16 | 3, 0xEA, 0x00, 0x00,
17 | 2, ILI9341_POWER1, 0x23, // Power control VRH[5:0]
18 | 2, ILI9341_POWER2, 0x10, // Power control SAP[2:0];BT[3:0]
19 | 3, ILI9341_VCOM1, 0x3e, 0x28, // VCM control
20 | 2, ILI9341_VCOM2, 0x86, // VCM control2
21 | 2, ILI9341_MAC, 0x48, // Memory Access Control
22 | 2, 0x37, 0x00, // Vertical scroll zero
23 | 2, ILI9341_PIXEL_FORMAT, 0x55,
24 | 3, 0xB1, 0x00, 0x18,
25 | 4, 0xB6, 0x08, 0x82, 0x27, // Display Function Control
26 | 2, 0xF2, 0x00, // 3Gamma Function Disable
27 | 2, 0x26, 0x01, // Gamma curve selected
28 | 16, 0xE0, 0x0F, 0x31, 0x2B, 0x0C, 0x0E, 0x08, // Set Gamma
29 | 0x4E, 0xF1, 0x37, 0x07, 0x10, 0x03, 0x0E, 0x09, 0x00,
30 | 16, 0xE1, 0x00, 0x0E, 0x14, 0x03, 0x11, 0x07, // Set Gamma
31 | 0x31, 0xC1, 0x48, 0x08, 0x0F, 0x0C, 0x31, 0x36, 0x0F,
32 | 2, 0x11, 0x80, // Exit Sleep
33 | 2, 0x29, 0x80, // Display on
34 |
35 | };
36 |
37 | //
38 |
39 | //
40 |
41 | static void ILI9341_pinsInit() {
42 | SPI_InitTypeDef spiStructure;
43 | GPIO_InitTypeDef gpioStructure;
44 |
45 | RCC_PCLK2Config(RCC_HCLK_Div2);
46 | RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE);
47 | RCC_APB2PeriphClockCmd(RCC_APB2ENR_AFIOEN, ENABLE);
48 | RCC_APB2PeriphClockCmd(SPI_MASTER_GPIO_CLK | SPI_MASTER_CLK, ENABLE);
49 |
50 | // GPIO speed by default
51 | gpioStructure.GPIO_Speed = GPIO_Speed_50MHz;
52 |
53 | // GPIO for CS/DC/LED/RESET
54 | gpioStructure.GPIO_Pin = TFT_CS_PIN | TFT_DC_PIN | TFT_RESET_PIN | TFT_LED_PIN;
55 | gpioStructure.GPIO_Mode = GPIO_Mode_Out_PP;
56 | GPIO_Init(GPIOA, &gpioStructure);
57 |
58 | // GPIO for SPI
59 | gpioStructure.GPIO_Pin = SPI_MASTER_PIN_SCK | SPI_MASTER_PIN_MOSI;
60 | gpioStructure.GPIO_Mode = GPIO_Mode_AF_PP;
61 | GPIO_Init(SPI_MASTER_GPIO, &gpioStructure);
62 |
63 | // GPIO for SPI
64 | gpioStructure.GPIO_Pin = SPI_MASTER_PIN_MISO;
65 | gpioStructure.GPIO_Mode = GPIO_Mode_IPD;
66 | GPIO_Init(SPI_MASTER_GPIO, &gpioStructure);
67 |
68 | SPI_StructInit(&spiStructure);
69 | spiStructure.SPI_Mode = SPI_Mode_Master;
70 | spiStructure.SPI_NSS = SPI_NSS_Soft;
71 | spiStructure.SPI_CPOL = SPI_CPOL_High;
72 | spiStructure.SPI_CPHA = SPI_CPHA_2Edge;
73 | spiStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2; // SPI SPEED
74 | SPI_Init(SPI_MASTER, &spiStructure);
75 |
76 | SPI_Cmd(SPI_MASTER, ENABLE);
77 | }
78 |
79 | void ILI9341_reset() {
80 | TFT_RST_RESET;
81 | osDelay(10);
82 | //delay_ms(10);
83 | TFT_RST_SET;
84 | osDelay(50);
85 | //delay_ms(50);
86 | }
87 |
88 | void ILI9341_exitStandby() {
89 | dmaSendCmd(ILI9341_SLEEP_OUT);
90 | osDelay(150);
91 | //delay_ms(150);
92 | dmaSendCmd(ILI9341_DISPLAY_ON);
93 | }
94 |
95 | static void ILI9341_configure() {
96 | u8 count;
97 | u8 *address = (u8 *) init_commands;
98 |
99 | TFT_CS_RESET;
100 | while (1) {
101 | count = *(address++);
102 | if (count-- == 0) break;
103 | dmaSendCmdCont(*(address++));
104 | dmaSendDataCont8(address, count);
105 | address += count;
106 | }
107 | TFT_CS_SET;
108 |
109 | ILI9341_setOrientation(ORIENTATION_LANDSCAPE);
110 | }
111 |
112 | void ILI9341_init(void) {
113 | ILI9341_pinsInit();
114 | dmaInit();
115 |
116 | ILI9341_reset();
117 | ILI9341_exitStandby();
118 | ILI9341_configure();
119 |
120 | TFT_LED_SET;
121 | }
122 |
123 | //
124 |
125 | //
126 |
127 | void ILI9341_setOrientation(u8 o) {
128 | if (o == ORIENTATION_LANDSCAPE || o == ORIENTATION_LANDSCAPE_MIRROR) {
129 | screen_height = ILI9341_PIXEL_WIDTH;
130 | screen_width = ILI9341_PIXEL_HEIGHT;
131 | } else {
132 | screen_height = ILI9341_PIXEL_HEIGHT;
133 | screen_width = ILI9341_PIXEL_WIDTH;
134 | }
135 | TFT_CS_RESET;
136 | dmaSendCmdCont(ILI9341_MAC);
137 | dmaSendDataCont8(&o, 1);
138 | TFT_CS_SET;
139 | }
140 |
141 | inline void ILI9341_setAddressWindow(u16 x1, u16 y1, u16 x2, u16 y2) {
142 | u16 pointData[2];
143 |
144 | TFT_CS_RESET;
145 | dmaSendCmdCont(ILI9341_COLUMN_ADDR);
146 | pointData[0] = x1;
147 | pointData[1] = x2;
148 | ILI9341_setSpi16();
149 | dmaSendDataCont16(pointData, 2);
150 | ILI9341_setSpi8();
151 |
152 | dmaSendCmdCont(ILI9341_PAGE_ADDR);
153 | pointData[0] = y1;
154 | pointData[1] = y2;
155 | ILI9341_setSpi16();
156 | dmaSendDataCont16(pointData, 2);
157 | ILI9341_setSpi8();
158 | TFT_CS_SET;
159 | }
160 |
161 |
162 |
163 | inline void ILI9341_fillRect(u16 x1, u16 y1, u16 w, u16 h, u16 color) {
164 | u32 count = w * h;
165 | ILI9341_setAddressWindowToWrite(x1, y1, (u16) (x1 + w - 1), (u16) (y1 + h - 1));
166 | ILI9341_setSpi16();
167 | dmaFill16(color, count);
168 | ILI9341_setSpi8();
169 | }
170 |
171 | inline u16 ILI9341_getWidth(void) {
172 | return screen_width;
173 | }
174 |
175 | inline u16 ILI9341_getHeight(void) {
176 | return screen_height;
177 | }
178 |
179 | //
180 |
181 | //
182 |
183 | inline void ILI9341_setSpi8(void) {
184 | SPI_MASTER->CR1 &= ~SPI_CR1_SPE; // DISABLE SPI
185 | SPI_MASTER->CR1 &= ~SPI_CR1_DFF; // SPI 8
186 | SPI_MASTER->CR1 |= SPI_CR1_SPE; // ENABLE SPI
187 | }
188 |
189 | inline void ILI9341_setSpi16(void) {
190 | SPI_MASTER->CR1 &= ~SPI_CR1_SPE; // DISABLE SPI
191 | SPI_MASTER->CR1 |= SPI_CR1_DFF; // SPI 16
192 | SPI_MASTER->CR1 |= SPI_CR1_SPE; // ENABLE SPI
193 | }
194 |
195 |
196 | //
197 |
--------------------------------------------------------------------------------
/ili9341/core.h:
--------------------------------------------------------------------------------
1 | #ifndef TEST1_ILI9341_CORE_H
2 | #define TEST1_ILI9341_CORE_H
3 |
4 | #include
5 | #include
6 | #include "commands.h"
7 | #include "dma.h"
8 |
9 | #include "../lvgl/lvgl.h"
10 |
11 | #define ILI9341_setAddressWindowToWrite(x1,y1,x2,y2) \
12 | ILI9341_setAddressWindow(x1, y1, x2, y2); \
13 | dmaSendCmd(ILI9341_GRAM)
14 |
15 | #define ILI9341_setAddressWindowToRead(x1,y1,x2,y2) \
16 | ILI9341_setAddressWindow(x1, y1, x2, y2); \
17 | dmaSendCmd(ILI9341_RAMRD)
18 |
19 | u16 ILI9341_getWidth(void);
20 | u16 ILI9341_getHeight(void);
21 |
22 | void ILI9341_init(void);
23 |
24 | void ILI9341_setSpi8(void);
25 | void ILI9341_setSpi16(void);
26 |
27 | void ILI9341_setOrientation(u8 o);
28 | void ILI9341_setAddressWindow(u16 x1, u16 y1, u16 x2, u16 y2);
29 |
30 | /*---------------------------------------
31 | * littleVGL function
32 | *----------------------------------------*/
33 |
34 |
35 | void ILI9341_fillRect(u16 x1, u16 y1, u16 w, u16 h, u16 color);
36 |
37 | #endif //TEST1_ILI9341_CORE_H
38 |
--------------------------------------------------------------------------------
/ili9341/dma.c:
--------------------------------------------------------------------------------
1 | #include "dma.h"
2 |
3 | DMA_InitTypeDef dmaStructure;
4 |
5 | #define DMA_BUF_SIZE 1024
6 | u16 dmaBufIndex = 0;
7 | u16 dmaBuffer[DMA_BUF_SIZE];
8 |
9 | void dmaInit(void) {
10 | RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA1, ENABLE);
11 |
12 | // TX
13 | NVIC_EnableIRQ(DMA1_Channel3_IRQn);
14 | DMA_ITConfig(DMA1_Channel3, DMA_IT_TC, ENABLE);
15 |
16 | // RX
17 | NVIC_EnableIRQ(DMA1_Channel2_IRQn);
18 | DMA_ITConfig(DMA1_Channel2, DMA_IT_TC, ENABLE);
19 |
20 | SPI_I2S_DMACmd(SPI_MASTER, SPI_I2S_DMAReq_Tx, ENABLE);
21 | SPI_I2S_DMACmd(SPI_MASTER, SPI_I2S_DMAReq_Rx, ENABLE);
22 | }
23 |
24 | //
25 |
26 | inline static void dmaReceive8(u8 *data, u32 n) {
27 | dmaStructure.DMA_MemoryBaseAddr = (u32) data;
28 | dmaStructure.DMA_BufferSize = n;
29 |
30 | dmaStructure.DMA_Mode = DMA_Mode_Normal;
31 | dmaStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
32 | dmaStructure.DMA_DIR = DMA_DIR_PeripheralSRC;
33 | dmaStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
34 | dmaStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
35 |
36 | dmaStartRx();
37 | }
38 |
39 | inline static void dmaSend8(u8 *data, u32 n) {
40 | DMA_StructInit(&dmaStructure);
41 | dmaStructure.DMA_PeripheralBaseAddr = (u32) &(SPI_MASTER->DR);
42 | dmaStructure.DMA_Priority = DMA_Priority_Medium;
43 |
44 | dmaStructure.DMA_MemoryBaseAddr = (u32) data;
45 | dmaStructure.DMA_BufferSize = n;
46 |
47 | dmaStructure.DMA_Mode = DMA_Mode_Normal;
48 | dmaStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
49 | dmaStructure.DMA_DIR = DMA_DIR_PeripheralDST;
50 | dmaStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
51 | dmaStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
52 |
53 | dmaStartTx();
54 | }
55 |
56 | inline static void dmaSendCircular16(u16 *data, u32 n) {
57 | DMA_StructInit(&dmaStructure);
58 | dmaStructure.DMA_PeripheralBaseAddr = (u32) &(SPI_MASTER->DR);
59 | dmaStructure.DMA_Priority = DMA_Priority_Medium;
60 |
61 | dmaStructure.DMA_MemoryBaseAddr = (u32) data;
62 | dmaStructure.DMA_BufferSize = n;
63 |
64 | dmaStructure.DMA_Mode = DMA_Mode_Circular;
65 | dmaStructure.DMA_MemoryInc = DMA_MemoryInc_Disable;
66 | dmaStructure.DMA_DIR = DMA_DIR_PeripheralDST;
67 | dmaStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_HalfWord;
68 | dmaStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_HalfWord;
69 |
70 | dmaStartTx();
71 | }
72 |
73 | inline static void dmaSend16(u16 *data, u32 n) {
74 | DMA_StructInit(&dmaStructure);
75 | dmaStructure.DMA_PeripheralBaseAddr = (u32) &(SPI_MASTER->DR);
76 | dmaStructure.DMA_Priority = DMA_Priority_Medium;
77 |
78 | dmaStructure.DMA_MemoryBaseAddr = (u32) data;
79 | dmaStructure.DMA_BufferSize = n;
80 |
81 | dmaStructure.DMA_Mode = DMA_Mode_Normal;
82 | dmaStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
83 | dmaStructure.DMA_DIR = DMA_DIR_PeripheralDST;
84 | dmaStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_HalfWord;
85 | dmaStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_HalfWord;
86 |
87 | dmaStartTx();
88 | }
89 |
90 | //
91 |
92 | //
93 |
94 | inline void dmaSendCmd(u8 cmd) {
95 | TFT_CS_RESET;
96 | TFT_DC_RESET;
97 | dmaSend8(&cmd, 1);
98 | dmaWait();
99 | TFT_CS_SET;
100 | }
101 |
102 | inline void dmaSendCmdCont(u8 cmd) {
103 | TFT_DC_RESET;
104 | dmaSend8(&cmd, 1);
105 | dmaWait();
106 | }
107 |
108 | inline void dmaReceiveDataCont8(u8 *data) {
109 | u8 dummy = 0xFF;
110 | dmaSend8(&dummy, 1);
111 | dmaReceive8(data, 1);
112 | dmaWait();
113 | }
114 |
115 | inline void dmaSendData8(u8 *data, u32 n) {
116 | TFT_CS_RESET;
117 | TFT_DC_SET;
118 | dmaSend8(data, n);
119 | dmaWait();
120 | TFT_CS_SET;
121 | }
122 |
123 | inline void dmaSendDataCont8(u8 *data, u32 n) {
124 | TFT_DC_SET;
125 | dmaSend8(data, n);
126 | dmaWait();
127 | }
128 |
129 | inline void dmaSendData16(u16 *data, u32 n) {
130 | TFT_CS_RESET;
131 | TFT_DC_SET;
132 | dmaSend16(data, n);
133 | dmaWait();
134 | TFT_CS_SET;
135 | }
136 |
137 | inline void dmaSendDataCont16(u16 *data, u32 n) {
138 | TFT_DC_SET;
139 | dmaSend16(data, n);
140 | dmaWait();
141 | }
142 |
143 | inline void dmaSendDataBuf16(void) {
144 | if(dmaBufIndex == 0) return;
145 | TFT_DC_SET;
146 | dmaSend16(dmaBuffer, dmaBufIndex);
147 | dmaBufIndex = 0;
148 | dmaWait();
149 | }
150 |
151 | inline void dmaSendDataContBuf16(u16 *data, u32 n) {
152 | while (n--) {
153 | dmaBuffer[dmaBufIndex] = *data++;
154 | if (dmaBufIndex == DMA_BUF_SIZE - 1) {
155 | dmaSendDataBuf16();
156 | }
157 | dmaBufIndex++;
158 | }
159 | }
160 |
161 |
162 | void dmaSendDataCircular16(u16 *data, u32 n) {
163 | TFT_DC_SET;
164 | dmaSendCircular16(data, n);
165 | dmaWait();
166 | }
167 |
168 | //
169 |
170 | inline void dmaFill16(u16 color, u32 n) {
171 | TFT_CS_RESET;
172 | dmaSendCmdCont(ILI9341_GRAM);
173 | while (n != 0) {
174 | u16 ts = (u16) (n > UINT16_MAX ? UINT16_MAX : n);
175 | dmaSendDataCircular16(&color, ts);
176 | n -= ts;
177 | }
178 | TFT_CS_SET;
179 | }
180 |
181 | //
182 |
183 | void DMA1_Channel2_IRQHandler(void) {
184 | if (DMA_GetITStatus(DMA1_IT_TC2) == SET) {
185 | DMA_Cmd(DMA1_Channel2, DISABLE);
186 | DMA_ClearITPendingBit(DMA1_IT_TC2);
187 | }
188 | }
189 |
190 | void DMA1_Channel3_IRQHandler(void) {
191 | if (DMA_GetITStatus(DMA1_IT_TC3) == SET) {
192 | DMA_Cmd(DMA1_Channel3, DISABLE);
193 | DMA_ClearITPendingBit(DMA1_IT_TC3);
194 | }
195 | }
196 |
197 | //
198 |
--------------------------------------------------------------------------------
/ili9341/dma.h:
--------------------------------------------------------------------------------
1 | #ifndef TEST1_DMA_H
2 | #define TEST1_DMA_H
3 |
4 | #include "control.h"
5 | #include
6 |
7 | #define dmaWait() while(SPI_I2S_GetFlagStatus(SPI_MASTER,SPI_I2S_FLAG_BSY) == SET);
8 |
9 | #define dmaStartRx() DMA_Init(DMA1_Channel2, &dmaStructure); \
10 | DMA_Cmd(DMA1_Channel2, ENABLE);
11 |
12 | #define dmaStartTx() DMA_Init(DMA1_Channel3, &dmaStructure); \
13 | DMA_Cmd(DMA1_Channel3, ENABLE);
14 |
15 | void dmaInit(void);
16 | void dmaDeInit(void);
17 |
18 | void dmaSendDat(u8 dat);
19 |
20 | void dmaSendCmd(u8 cmd);
21 | void dmaSendCmdCont(u8 cmd);
22 |
23 | void dmaReceiveDataCont8(u8 *data);
24 |
25 | void dmaSendData8(u8 *data, u32 n);
26 | void dmaSendData16(u16 *data, u32 n);
27 |
28 | void dmaSendDataCont8(u8 *data, u32 n);
29 | void dmaSendDataCont16(u16 *data, u32 n);
30 |
31 | void dmaSendDataBuf16(void);
32 | void dmaSendDataContBuf16(u16 *data, u32 n);
33 |
34 | void dmaFill16(u16 color, u32 n);
35 |
36 | #endif //TEST1_DMA_H
37 |
--------------------------------------------------------------------------------
/ili9341/lv_driver.c:
--------------------------------------------------------------------------------
1 | #include "core.h"
2 | //#include
3 |
4 | // void ILI9341_flush(struct _disp_drv_t * drv, const lv_area_t * area, lv_color_t * color_map)
5 | void ILI9341_flush(lv_disp_drv_t * drv, const lv_area_t * area, lv_color_t * color_map)
6 | {
7 | ILI9341_setAddressWindowToWrite((u16)area->x1, (u16)area->y1, (u16)area->x2, (u16)area->y2);
8 | uint32_t size = (area->x2 - area->x1 + 1) * (area->y2 - area->y1 + 1);
9 | ILI9341_setSpi16();
10 | dmaSendData16((void*)color_map, size);
11 | ILI9341_setSpi8();
12 | lv_disp_flush_ready(drv);
13 | //printf("flush \n\r");
14 | }
15 |
16 |
--------------------------------------------------------------------------------
/ili9341/lv_driver.h:
--------------------------------------------------------------------------------
1 | #include "../lvgl/lvgl.h"
2 | #include "../lv_conf.h"
3 |
4 | void ILI9341_flush(struct _disp_drv_t *, const lv_area_t * , lv_color_t * );
5 | void ILI9341_flush(lv_disp_drv_t *, const lv_area_t * , lv_color_t * );
6 |
--------------------------------------------------------------------------------
/images/Scarsfun11a.png:
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https://raw.githubusercontent.com/ScarsFun/lvgl_STM32F103_encoder_rtx5/056252d7c0b21a913dffe0712e2272f7ac2e8dcf/images/Scarsfun11a.png
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/images/stm32f4stampV1_1.jpg:
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https://raw.githubusercontent.com/ScarsFun/lvgl_STM32F103_encoder_rtx5/056252d7c0b21a913dffe0712e2272f7ac2e8dcf/images/stm32f4stampV1_1.jpg
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/images/test_board.png:
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https://raw.githubusercontent.com/ScarsFun/lvgl_STM32F103_encoder_rtx5/056252d7c0b21a913dffe0712e2272f7ac2e8dcf/images/test_board.png
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/lv_conf.h:
--------------------------------------------------------------------------------
1 | /**
2 | * @file lv_conf.h
3 | *
4 | */
5 |
6 | /*
7 | * COPY THIS FILE AS `lv_conf.h` NEXT TO the `lvgl` FOLDER
8 | */
9 |
10 | #if 1 /*Set it to "1" to enable content*/
11 |
12 | #ifndef LV_CONF_H
13 | #define LV_CONF_H
14 | /* clang-format off */
15 |
16 | #include
17 |
18 | /*====================
19 | Graphical settings
20 | *====================*/
21 |
22 | /* Maximal horizontal and vertical resolution to support by the library.*/
23 | #define LV_HOR_RES_MAX (320)
24 | #define LV_VER_RES_MAX (240)
25 |
26 | /* Color depth:
27 | * - 1: 1 byte per pixel
28 | * - 8: RGB233
29 | * - 16: RGB565
30 | * - 32: ARGB8888
31 | */
32 | #define LV_COLOR_DEPTH 16
33 |
34 | /* Swap the 2 bytes of RGB565 color.
35 | * Useful if the display has a 8 bit interface (e.g. SPI)*/
36 | #define LV_COLOR_16_SWAP 0
37 |
38 | /* 1: Enable screen transparency.
39 | * Useful for OSD or other overlapping GUIs.
40 | * Requires `LV_COLOR_DEPTH = 32` colors and the screen's style should be modified: `style.body.opa = ...`*/
41 | #define LV_COLOR_SCREEN_TRANSP 0
42 |
43 | /*Images pixels with this color will not be drawn (with chroma keying)*/
44 | #define LV_COLOR_TRANSP LV_COLOR_LIME /*LV_COLOR_LIME: pure green*/
45 |
46 | /* Enable anti-aliasing (lines, and radiuses will be smoothed) */
47 | #define LV_ANTIALIAS 1
48 |
49 | /* Default display refresh period.
50 | * Can be changed in the display driver (`lv_disp_drv_t`).*/
51 | #define LV_DISP_DEF_REFR_PERIOD 30 /*[ms]*/
52 |
53 | /* Dot Per Inch: used to initialize default sizes.
54 | * E.g. a button with width = LV_DPI / 2 -> half inch wide
55 | * (Not so important, you can adjust it to modify default sizes and spaces)*/
56 | #define LV_DPI 100 /*[px]*/
57 |
58 | /* Type of coordinates. Should be `int16_t` (or `int32_t` for extreme cases) */
59 | typedef int16_t lv_coord_t;
60 |
61 | /*=========================
62 | Memory manager settings
63 | *=========================*/
64 |
65 | /* LittelvGL's internal memory manager's settings.
66 | * The graphical objects and other related data are stored here. */
67 |
68 | /* 1: use custom malloc/free, 0: use the built-in `lv_mem_alloc` and `lv_mem_free` */
69 | #define LV_MEM_CUSTOM 0
70 | #if LV_MEM_CUSTOM == 0
71 | /* Size of the memory used by `lv_mem_alloc` in bytes (>= 2kB)*/
72 | # define LV_MEM_SIZE (16U * 1024U)
73 |
74 | /* Complier prefix for a big array declaration */
75 | # define LV_MEM_ATTR
76 |
77 | /* Set an address for the memory pool instead of allocating it as an array.
78 | * Can be in external SRAM too. */
79 | # define LV_MEM_ADR 0
80 |
81 | /* Automatically defrag. on free. Defrag. means joining the adjacent free cells. */
82 | # define LV_MEM_AUTO_DEFRAG 1
83 | #else /*LV_MEM_CUSTOM*/
84 | # define LV_MEM_CUSTOM_INCLUDE /*Header for the dynamic memory function*/
85 | # define LV_MEM_CUSTOM_ALLOC malloc /*Wrapper to malloc*/
86 | # define LV_MEM_CUSTOM_FREE free /*Wrapper to free*/
87 | #endif /*LV_MEM_CUSTOM*/
88 |
89 | /* Garbage Collector settings
90 | * Used if lvgl is binded to higher level language and the memory is managed by that language */
91 | #define LV_ENABLE_GC 0
92 | #if LV_ENABLE_GC != 0
93 | # define LV_GC_INCLUDE "gc.h" /*Include Garbage Collector related things*/
94 | # define LV_MEM_CUSTOM_REALLOC your_realloc /*Wrapper to realloc*/
95 | # define LV_MEM_CUSTOM_GET_SIZE your_mem_get_size /*Wrapper to lv_mem_get_size*/
96 | #endif /* LV_ENABLE_GC */
97 |
98 | /*=======================
99 | Input device settings
100 | *=======================*/
101 |
102 | /* Input device default settings.
103 | * Can be changed in the Input device driver (`lv_indev_drv_t`)*/
104 |
105 | /* Input device read period in milliseconds */
106 | #define LV_INDEV_DEF_READ_PERIOD 30
107 |
108 | /* Drag threshold in pixels */
109 | #define LV_INDEV_DEF_DRAG_LIMIT 10
110 |
111 | /* Drag throw slow-down in [%]. Greater value -> faster slow-down */
112 | #define LV_INDEV_DEF_DRAG_THROW 20
113 |
114 | /* Long press time in milliseconds.
115 | * Time to send `LV_EVENT_LONG_PRESSSED`) */
116 | #define LV_INDEV_DEF_LONG_PRESS_TIME 400
117 |
118 | /* Repeated trigger period in long press [ms]
119 | * Time between `LV_EVENT_LONG_PRESSED_REPEAT */
120 | #define LV_INDEV_DEF_LONG_PRESS_REP_TIME 100
121 |
122 | /*==================
123 | * Feature usage
124 | *==================*/
125 |
126 | /*1: Enable the Animations */
127 | #define LV_USE_ANIMATION 0
128 | #if LV_USE_ANIMATION
129 |
130 | /*Declare the type of the user data of animations (can be e.g. `void *`, `int`, `struct`)*/
131 | typedef void * lv_anim_user_data_t;
132 |
133 | #endif
134 |
135 | /* 1: Enable shadow drawing*/
136 | #define LV_USE_SHADOW 1
137 |
138 | /* 1: Enable object groups (for keyboard/encoder navigation) */
139 | #define LV_USE_GROUP 1
140 | #if LV_USE_GROUP
141 | typedef void * lv_group_user_data_t;
142 | #endif /*LV_USE_GROUP*/
143 |
144 | /* 1: Enable GPU interface*/
145 | #define LV_USE_GPU 0
146 |
147 | /* 1: Enable file system (might be required for images */
148 | #define LV_USE_FILESYSTEM 1
149 | #if LV_USE_FILESYSTEM
150 | /*Declare the type of the user data of file system drivers (can be e.g. `void *`, `int`, `struct`)*/
151 | typedef void * lv_fs_drv_user_data_t;
152 | #endif
153 |
154 | /*1: Add a `user_data` to drivers and objects*/
155 | #define LV_USE_USER_DATA 1
156 |
157 | /*========================
158 | * Image decoder and cache
159 | *========================*/
160 |
161 | /* 1: Enable indexed (palette) images */
162 | #define LV_IMG_CF_INDEXED 1
163 |
164 | /* 1: Enable alpha indexed images */
165 | #define LV_IMG_CF_ALPHA 1
166 |
167 | /* Default image cache size. Image caching keeps the images opened.
168 | * If only the built-in image formats are used there is no real advantage of caching.
169 | * (I.e. no new image decoder is added)
170 | * With complex image decoders (e.g. PNG or JPG) caching can save the continuous open/decode of images.
171 | * However the opened images might consume additional RAM.
172 | * LV_IMG_CACHE_DEF_SIZE must be >= 1 */
173 | #define LV_IMG_CACHE_DEF_SIZE 1
174 |
175 | /*Declare the type of the user data of image decoder (can be e.g. `void *`, `int`, `struct`)*/
176 | typedef void * lv_img_decoder_user_data_t;
177 |
178 | /*=====================
179 | * Compiler settings
180 | *====================*/
181 | /* Define a custom attribute to `lv_tick_inc` function */
182 | #define LV_ATTRIBUTE_TICK_INC
183 |
184 | /* Define a custom attribute to `lv_task_handler` function */
185 | #define LV_ATTRIBUTE_TASK_HANDLER
186 |
187 | /* With size optimization (-Os) the compiler might not align data to
188 | * 4 or 8 byte boundary. This alignment will be explicitly applied where needed.
189 | * E.g. __attribute__((aligned(4))) */
190 | #define LV_ATTRIBUTE_MEM_ALIGN
191 |
192 | /* Attribute to mark large constant arrays for example
193 | * font's bitmaps */
194 | #define LV_ATTRIBUTE_LARGE_CONST
195 |
196 | /*===================
197 | * HAL settings
198 | *==================*/
199 |
200 | /* 1: use a custom tick source.
201 | * It removes the need to manually update the tick with `lv_tick_inc`) */
202 | #define LV_TICK_CUSTOM 0
203 | #if LV_TICK_CUSTOM == 1
204 | #define LV_TICK_CUSTOM_INCLUDE "something.h" /*Header for the sys time function*/
205 | #define LV_TICK_CUSTOM_SYS_TIME_EXPR (millis()) /*Expression evaluating to current systime in ms*/
206 | #endif /*LV_TICK_CUSTOM*/
207 |
208 | typedef void * lv_disp_drv_user_data_t; /*Type of user data in the display driver*/
209 | typedef void * lv_indev_drv_user_data_t; /*Type of user data in the input device driver*/
210 |
211 | /*================
212 | * Log settings
213 | *===============*/
214 |
215 | /*1: Enable the log module*/
216 | #define LV_USE_LOG 0
217 | #if LV_USE_LOG
218 | /* How important log should be added:
219 | * LV_LOG_LEVEL_TRACE A lot of logs to give detailed information
220 | * LV_LOG_LEVEL_INFO Log important events
221 | * LV_LOG_LEVEL_WARN Log if something unwanted happened but didn't cause a problem
222 | * LV_LOG_LEVEL_ERROR Only critical issue, when the system may fail
223 | * LV_LOG_LEVEL_NONE Do not log anything
224 | */
225 | # define LV_LOG_LEVEL LV_LOG_LEVEL_WARN
226 |
227 | /* 1: Print the log with 'printf';
228 | * 0: user need to register a callback with `lv_log_register_print`*/
229 | # define LV_LOG_PRINTF 0
230 | #endif /*LV_USE_LOG*/
231 |
232 | /*================
233 | * THEME USAGE
234 | *================*/
235 | #define LV_THEME_LIVE_UPDATE 0 /*1: Allow theme switching at run time. Uses 8..10 kB of RAM*/
236 |
237 | #define LV_USE_THEME_TEMPL 0 /*Just for test*/
238 | #define LV_USE_THEME_DEFAULT 0 /*Built mainly from the built-in styles. Consumes very few RAM*/
239 | #define LV_USE_THEME_ALIEN 0 /*Dark futuristic theme*/
240 | #define LV_USE_THEME_NIGHT 0 /*Dark elegant theme*/
241 | #define LV_USE_THEME_MONO 0 /*Mono color theme for monochrome displays*/
242 | #define LV_USE_THEME_MATERIAL 0 /*Flat theme with bold colors and light shadows*/
243 | #define LV_USE_THEME_ZEN 1 /*Peaceful, mainly light theme */
244 | #define LV_USE_THEME_NEMO 0 /*Water-like theme based on the movie "Finding Nemo"*/
245 |
246 | /*==================
247 | * FONT USAGE
248 | *===================*/
249 |
250 | /* The built-in fonts contains the ASCII range and some Symbols with 4 bit-per-pixel.
251 | * The symbols are available via `LV_SYMBOL_...` defines
252 | * More info about fonts: https://docs.littlevgl.com/#Fonts
253 | * To create a new font go to: https://littlevgl.com/ttf-font-to-c-array
254 | */
255 |
256 | /* Robot fonts with bpp = 4
257 | * https://fonts.google.com/specimen/Roboto */
258 | #define LV_FONT_ROBOTO_12 0
259 | #define LV_FONT_ROBOTO_16 1
260 | #define LV_FONT_ROBOTO_22 0
261 | #define LV_FONT_ROBOTO_28 1
262 |
263 | /*Pixel perfect monospace font
264 | * http://pelulamu.net/unscii/ */
265 | #define LV_FONT_UNSCII_8 0
266 |
267 | /* Optionally declare your custom fonts here.
268 | * You can use these fonts as default font too
269 | * and they will be available globally. E.g.
270 | * #define LV_FONT_CUSTOM_DECLARE LV_FONT_DECLARE(my_font_1) \
271 | * LV_FONT_DECLARE(my_font_2)
272 | */
273 | #define LV_FONT_CUSTOM_DECLARE
274 |
275 | /*Always set a default font from the built-in fonts*/
276 | #define LV_FONT_DEFAULT &lv_font_roboto_16
277 |
278 | /*Declare the type of the user data of fonts (can be e.g. `void *`, `int`, `struct`)*/
279 | typedef void * lv_font_user_data_t;
280 |
281 | /*=================
282 | * Text settings
283 | *=================*/
284 |
285 | /* Select a character encoding for strings.
286 | * Your IDE or editor should have the same character encoding
287 | * - LV_TXT_ENC_UTF8
288 | * - LV_TXT_ENC_ASCII
289 | * */
290 | #define LV_TXT_ENC LV_TXT_ENC_UTF8
291 |
292 | /*Can break (wrap) texts on these chars*/
293 | #define LV_TXT_BREAK_CHARS " ,.;:-_"
294 |
295 | /*===================
296 | * LV_OBJ SETTINGS
297 | *==================*/
298 |
299 | /*Declare the type of the user data of object (can be e.g. `void *`, `int`, `struct`)*/
300 | typedef void * lv_obj_user_data_t;
301 |
302 | /*1: enable `lv_obj_realaign()` based on `lv_obj_align()` parameters*/
303 | #define LV_USE_OBJ_REALIGN 1
304 |
305 | /* Enable to make the object clickable on a larger area.
306 | * LV_EXT_CLICK_AREA_OFF or 0: Disable this feature
307 | * LV_EXT_CLICK_AREA_TINY: The extra area can be adjusted horizontally and vertically (0..255 px)
308 | * LV_EXT_CLICK_AREA_FULL: The extra area can be adjusted in all 4 directions (-32k..+32k px)
309 | */
310 | #define LV_USE_EXT_CLICK_AREA LV_EXT_CLICK_AREA_OFF
311 |
312 | /*==================
313 | * LV OBJ X USAGE
314 | *================*/
315 | /*
316 | * Documentation of the object types: https://docs.littlevgl.com/#Object-types
317 | */
318 |
319 | /*Arc (dependencies: -)*/
320 | #define LV_USE_ARC 1
321 |
322 | /*Bar (dependencies: -)*/
323 | #define LV_USE_BAR 1
324 |
325 | /*Button (dependencies: lv_cont*/
326 | #define LV_USE_BTN 1
327 | #if LV_USE_BTN != 0
328 | /*Enable button-state animations - draw a circle on click (dependencies: LV_USE_ANIMATION)*/
329 | # define LV_BTN_INK_EFFECT 0
330 | #endif
331 |
332 | /*Button matrix (dependencies: -)*/
333 | #define LV_USE_BTNM 1
334 |
335 | /*Calendar (dependencies: -)*/
336 | #define LV_USE_CALENDAR 1
337 |
338 | /*Canvas (dependencies: lv_img)*/
339 | #define LV_USE_CANVAS 1
340 |
341 | /*Check box (dependencies: lv_btn, lv_label)*/
342 | #define LV_USE_CB 1
343 |
344 | /*Chart (dependencies: -)*/
345 | #define LV_USE_CHART 1
346 | #if LV_USE_CHART
347 | # define LV_CHART_AXIS_TICK_LABEL_MAX_LEN 20
348 | #endif
349 |
350 | /*Container (dependencies: -*/
351 | #define LV_USE_CONT 1
352 |
353 | /*Drop down list (dependencies: lv_page, lv_label, lv_symbol_def.h)*/
354 | #define LV_USE_DDLIST 1
355 | #if LV_USE_DDLIST != 0
356 | /*Open and close default animation time [ms] (0: no animation)*/
357 | # define LV_DDLIST_DEF_ANIM_TIME 200
358 | #endif
359 |
360 | /*Gauge (dependencies:lv_bar, lv_lmeter)*/
361 | #define LV_USE_GAUGE 1
362 |
363 | /*Image (dependencies: lv_label*/
364 | #define LV_USE_IMG 1
365 |
366 | /*Image Button (dependencies: lv_btn*/
367 | #define LV_USE_IMGBTN 1
368 | #if LV_USE_IMGBTN
369 | /*1: The imgbtn requires left, mid and right parts and the width can be set freely*/
370 | # define LV_IMGBTN_TILED 0
371 | #endif
372 |
373 | /*Keyboard (dependencies: lv_btnm)*/
374 | #define LV_USE_KB 1
375 |
376 | /*Label (dependencies: -*/
377 | #define LV_USE_LABEL 1
378 | #if LV_USE_LABEL != 0
379 | /*Hor, or ver. scroll speed [px/sec] in 'LV_LABEL_LONG_ROLL/ROLL_CIRC' mode*/
380 | # define LV_LABEL_DEF_SCROLL_SPEED 25
381 |
382 | /* Waiting period at beginning/end of animation cycle */
383 | # define LV_LABEL_WAIT_CHAR_COUNT 3
384 |
385 | /*Enable selecting text of the label */
386 | # define LV_LABEL_TEXT_SEL 0
387 |
388 | /*Store extra some info in labels (12 bytes) to speed up drawing of very long texts*/
389 | # define LV_LABEL_LONG_TXT_HINT 0
390 | #endif
391 |
392 | /*LED (dependencies: -)*/
393 | #define LV_USE_LED 1
394 |
395 | /*Line (dependencies: -*/
396 | #define LV_USE_LINE 1
397 |
398 | /*List (dependencies: lv_page, lv_btn, lv_label, (lv_img optionally for icons ))*/
399 | #define LV_USE_LIST 1
400 | #if LV_USE_LIST != 0
401 | /*Default animation time of focusing to a list element [ms] (0: no animation) */
402 | # define LV_LIST_DEF_ANIM_TIME 100
403 | #endif
404 |
405 | /*Line meter (dependencies: *;)*/
406 | #define LV_USE_LMETER 1
407 |
408 | /*Message box (dependencies: lv_rect, lv_btnm, lv_label)*/
409 | #define LV_USE_MBOX 1
410 |
411 | /*Page (dependencies: lv_cont)*/
412 | #define LV_USE_PAGE 1
413 | #if LV_USE_PAGE != 0
414 | /*Focus default animation time [ms] (0: no animation)*/
415 | # define LV_PAGE_DEF_ANIM_TIME 400
416 | #endif
417 |
418 | /*Preload (dependencies: lv_arc, lv_anim)*/
419 | #define LV_USE_PRELOAD 0
420 | #if LV_USE_PRELOAD != 0
421 | # define LV_PRELOAD_DEF_ARC_LENGTH 60 /*[deg]*/
422 | # define LV_PRELOAD_DEF_SPIN_TIME 1000 /*[ms]*/
423 | # define LV_PRELOAD_DEF_ANIM LV_PRELOAD_TYPE_SPINNING_ARC
424 | #endif
425 |
426 | /*Roller (dependencies: lv_ddlist)*/
427 | #define LV_USE_ROLLER 1
428 | #if LV_USE_ROLLER != 0
429 | /*Focus animation time [ms] (0: no animation)*/
430 | # define LV_ROLLER_DEF_ANIM_TIME 200
431 |
432 | /*Number of extra "pages" when the roller is infinite*/
433 | # define LV_ROLLER_INF_PAGES 7
434 | #endif
435 |
436 | /*Slider (dependencies: lv_bar)*/
437 | #define LV_USE_SLIDER 1
438 |
439 | /*Spinbox (dependencies: lv_ta)*/
440 | #define LV_USE_SPINBOX 1
441 |
442 | /*Switch (dependencies: lv_slider)*/
443 | #define LV_USE_SW 1
444 |
445 | /*Text area (dependencies: lv_label, lv_page)*/
446 | #define LV_USE_TA 1
447 | #if LV_USE_TA != 0
448 | # define LV_TA_DEF_CURSOR_BLINK_TIME 400 /*ms*/
449 | # define LV_TA_DEF_PWD_SHOW_TIME 1500 /*ms*/
450 | #endif
451 |
452 | /*Table (dependencies: lv_label)*/
453 | #define LV_USE_TABLE 1
454 | #if LV_USE_TABLE
455 | # define LV_TABLE_COL_MAX 12
456 | #endif
457 |
458 | /*Tab (dependencies: lv_page, lv_btnm)*/
459 | #define LV_USE_TABVIEW 1
460 | # if LV_USE_TABVIEW != 0
461 | /*Time of slide animation [ms] (0: no animation)*/
462 | # define LV_TABVIEW_DEF_ANIM_TIME 300
463 | #endif
464 |
465 | /*Tileview (dependencies: lv_page) */
466 | #define LV_USE_TILEVIEW 1
467 | #if LV_USE_TILEVIEW
468 | /*Time of slide animation [ms] (0: no animation)*/
469 | # define LV_TILEVIEW_DEF_ANIM_TIME 300
470 | #endif
471 |
472 | /*Window (dependencies: lv_cont, lv_btn, lv_label, lv_img, lv_page)*/
473 | #define LV_USE_WIN 1
474 |
475 | /*==================
476 | * Non-user section
477 | *==================*/
478 |
479 | #if defined(_MSC_VER) && !defined(_CRT_SECURE_NO_WARNINGS) /* Disable warnings for Visual Studio*/
480 | # define _CRT_SECURE_NO_WARNINGS
481 | #endif
482 |
483 | /*--END OF LV_CONF_H--*/
484 |
485 | /*Be sure every define has a default value*/
486 | #include "lvgl/src/lv_conf_checker.h"
487 |
488 | #endif /*LV_CONF_H*/
489 |
490 | #endif /*End of "Content enable"*/
491 |
--------------------------------------------------------------------------------
/main.c:
--------------------------------------------------------------------------------
1 | /*-------------------------------------------------------------------------- *
2 | * *
3 | * *
4 | * ____ _____ *
5 | * / ___| ___ __ _ _ __ ___| ___| _ _ __ *
6 | * \___ \ / __/ _` | '__/ __| |_ | | | | '_ \ *
7 | * ___) | (_| (_| | | \__ \ _|| |_| | | | | *
8 | * |____/ \___\__,_|_| |___/_| \__,_|_| |_| *
9 | * *
10 | * *
11 | * 15/07/2019 *
12 | * *
13 | * *
14 | * https://github.com/ScarsFun *
15 | * littleVgl DEMO. *
16 | * *
17 | * LittleVgl (6.0) *
18 | * Custom STM32F103RC Board (72Mhz, 64K ram, 256K Flash) . *
19 | * ILI9341 display over SPI with DMA. rotary encoder. *
20 | * KEIL RTX v5. *
21 | * LVGL event driven refresh. Standby after 10 Secs Encoder inactivity. *
22 | * *
23 | * *
24 | * *
25 | * *
26 | * ILI9341 SPI CONNECTIONS: *
27 | * TFT_RESET PA2 *
28 | * TFT_DC PA3 *
29 | * TFT_CS PA4 *
30 | * TFT_SCK PA5 *
31 | * TFT_MISO PA6 *
32 | * TFT_MOSI PA7 *
33 | * *
34 | * ROTARY ENCODER CONNECTIONS: *
35 | * CLK PB7 *
36 | * DT PB6 *
37 | * SWITCH PB5 *
38 | * *
39 | * PWM LED PB0 *
40 | * Blinky LED PB8 *
41 | * *
42 | * *
43 | *---------------------------------------------------------------------------*/
44 |
45 | #define osObjectsPublic // define objects in main module
46 | #include
47 | #include "cmsis_os2.h"
48 | #include "stm32f10x.h"
49 | #include "lvgl/lvgl.h"
50 | #include "ili9341/core.h"
51 | #include "ili9341/lv_driver.h"
52 | #include "encoder/encoder.h"
53 | #include "pwm/pwm.h"
54 | #include "misc/led.h"
55 |
56 | static lv_group_t* g; //An Object Group
57 | static lv_indev_t* encoder_indev; //The input device
58 | const uint32_t led_intensity[10] = { 1, 14, 68, 207, 490, 990, 1793, 2998, 4718, 70199 };
59 |
60 | lv_obj_t* chart1, *slider, *spinbox;
61 | lv_chart_series_t* dl2_1;
62 |
63 | const osThreadAttr_t lvgl_refresh_Thread_attr = {
64 | .stack_size = 1024 // Create the thread stack with a size of 1024 bytes
65 | };
66 |
67 | const osThreadAttr_t main_app_attr = {
68 | .stack_size = 1280 // Create the thread stack with a size of 1024 bytes
69 | };
70 |
71 | void timer1_callback(void* param);
72 | void lvgl_refresh_Thread(void* argument);
73 |
74 | osThreadId_t T_lvgl_refresh_Thread;
75 | osMutexId_t lvgl_upd_mutex;
76 | osTimerId_t timer0_id, timer1_id;
77 | osEventFlagsId_t LVGL_rfr_evt_id;
78 | osStatus_t status;
79 |
80 | void button_event_cb(lv_obj_t* btn, lv_event_t event)
81 | {
82 | // button is clicked
83 | if (event == LV_EVENT_CLICKED) {
84 | if (lv_btn_get_state(btn) == 0)
85 | {
86 | TIM3->CCR3 = 0;
87 | lv_group_remove_obj(slider);
88 | lv_obj_set_hidden(slider, true);
89 | }
90 | else {
91 |
92 | TIM3->CCR3 = led_intensity[lv_slider_get_value(slider) - 1];
93 | lv_group_add_obj(g, slider);
94 | lv_obj_set_hidden(slider, false);
95 | }
96 | }
97 | }
98 |
99 | static void slider_event_cb(lv_obj_t* slider, lv_event_t event)
100 | {
101 | if (event == LV_EVENT_VALUE_CHANGED)
102 | TIM3->CCR3 = led_intensity[lv_slider_get_value(slider) - 1];
103 | }
104 |
105 | static void checkb_event_cb(lv_obj_t* checkb, lv_event_t event)
106 | {
107 | if (event == LV_EVENT_CLICKED) //A check box is clicked
108 | {
109 | if (lv_cb_is_checked(checkb)) {
110 | status = osTimerStart(timer0_id, 1000);
111 | }
112 | else
113 | osTimerStop(timer0_id);
114 | }
115 | }
116 |
117 | static void spinbox_event_cb(lv_obj_t* spinbox, lv_event_t event)
118 | {
119 | if (event == LV_EVENT_VALUE_CHANGED) {
120 | uint16_t spinbox_value = lv_spinbox_get_value(spinbox);
121 | if (spinbox_value == 0) {
122 | osTimerStop(timer1_id);
123 | GPIO_WriteBit(GPIOB, GPIO_Pin_8, Bit_RESET);
124 | }
125 | else {
126 | osTimerStop(timer1_id);
127 | osTimerStart(timer1_id, spinbox_value * 50);
128 | }
129 | }
130 | }
131 |
132 | static void gui_create(void)
133 | {
134 | lv_theme_t* th = lv_theme_zen_init(240, NULL);
135 | lv_theme_set_current(th);
136 | lv_obj_t* scr = lv_cont_create(NULL, NULL);
137 | lv_scr_load(scr);
138 |
139 | // Create Power toggle button
140 | lv_obj_t* btn = lv_btn_create(lv_scr_act(), NULL);
141 | lv_obj_set_size(btn, 30, 30);
142 | lv_btn_set_toggle(btn, true);
143 | lv_obj_set_event_cb(btn, button_event_cb);
144 | lv_obj_t* btn_label = lv_label_create(btn, NULL);
145 | lv_label_set_text(btn_label, LV_SYMBOL_POWER);
146 | lv_group_add_obj(g, btn);
147 | lv_obj_set_pos(btn, 15, 15);
148 |
149 | //Create a slider
150 | slider = lv_slider_create(lv_scr_act(), NULL);
151 | lv_obj_set_size(slider, 120, 25);
152 | lv_obj_set_event_cb(slider, slider_event_cb);
153 | lv_obj_align(slider, btn, LV_ALIGN_OUT_RIGHT_TOP, 30, 5);
154 | lv_bar_set_range(slider, 1, 10);
155 | lv_obj_set_hidden(slider, true);
156 |
157 | static lv_style_t spinBoxStyle;
158 | lv_style_copy(&spinBoxStyle, th->style.spinbox.bg);
159 | spinBoxStyle.text.font = &lv_font_roboto_28;
160 |
161 | spinbox = lv_spinbox_create(lv_scr_act(), NULL);
162 | lv_spinbox_set_style(spinbox, LV_SPINBOX_STYLE_BG, &spinBoxStyle);
163 |
164 | lv_spinbox_set_digit_format(spinbox, 2, 0);
165 | lv_spinbox_set_range(spinbox, 0, 99);
166 | lv_obj_set_size(spinbox, 110, 55);
167 | lv_obj_align(spinbox, slider, LV_ALIGN_OUT_RIGHT_TOP, 10, -10);
168 | lv_obj_set_event_cb(spinbox, spinbox_event_cb);
169 | lv_group_add_obj(g, spinbox);
170 |
171 | lv_obj_t* checkb = lv_cb_create(lv_scr_act(), NULL); //check box
172 | lv_cb_set_text(checkb, "GRAPH");
173 | lv_group_add_obj(g, checkb); //Add to the group
174 | lv_obj_set_event_cb(checkb, checkb_event_cb);
175 | lv_obj_align(checkb, btn, LV_ALIGN_IN_BOTTOM_LEFT, 0, 40);
176 |
177 | lv_obj_t* label = lv_label_create(lv_scr_act(), NULL);
178 | lv_label_set_text(label, "LittleVgl V6.0");
179 | lv_obj_align(label, checkb, LV_ALIGN_IN_BOTTOM_LEFT, 90, 15);
180 |
181 | chart1 = lv_chart_create(lv_scr_act(), NULL);
182 | lv_obj_set_size(chart1, 310, 130);
183 | lv_obj_set_pos(chart1, 4, 100);
184 | lv_chart_set_series_width(chart1, 2);
185 | lv_chart_set_type(chart1, LV_CHART_TYPE_POINT | LV_CHART_TYPE_LINE);
186 | lv_chart_set_range(chart1, 0, 120);
187 | lv_chart_set_div_line_count(chart1, 4, 0);
188 | dl2_1 = lv_chart_add_series(chart1, LV_COLOR_RED);
189 |
190 | lv_group_set_wrap(g, true);
191 |
192 | }
193 | void timer1_callback(void* param)
194 | {
195 | lv_chart_set_next(chart1, dl2_1, rand() % 120);
196 | lv_chart_refresh(chart1);
197 | osEventFlagsSet(LVGL_rfr_evt_id, 0x0001);
198 | }
199 | void timer2_callback(void* param)
200 | {
201 | GPIOB->ODR ^= (1 << 8); //toggle PB8 LED
202 | }
203 |
204 | // LVGL refresh thread , Standby after 10secs rotary encoder inactivity
205 | void lvgl_refresh_Thread(void* argument)
206 | {
207 | uint32_t index;
208 |
209 | for (;;) {
210 | osEventFlagsWait(LVGL_rfr_evt_id, 0x0001, NULL, osWaitForever);
211 | osMutexAcquire(lvgl_upd_mutex, osWaitForever);
212 | for (index = 0; index < 1000; index++) {
213 | lv_task_handler();
214 | lv_tick_inc(10);
215 | osDelay(10);
216 | }
217 | osMutexRelease(lvgl_upd_mutex);
218 | }
219 | }
220 |
221 | void app_main(void* argument)
222 | {
223 |
224 | lv_init();
225 | ILI9341_init();
226 | PWM_Init();
227 | LED_PB8_init();
228 |
229 | static lv_disp_buf_t disp_buf;
230 | static lv_color_t buf_1[LV_HOR_RES_MAX * 10];
231 | lv_disp_buf_init(&disp_buf, buf_1, NULL, LV_HOR_RES_MAX * 10);
232 |
233 | lv_disp_drv_t disp_drv;
234 | lv_disp_drv_init(&disp_drv);
235 | disp_drv.buffer = &disp_buf;
236 | disp_drv.flush_cb = ILI9341_flush;
237 | lv_disp_drv_register(&disp_drv);
238 |
239 | encoder_init();
240 | lv_indev_drv_t indev_drv;
241 | lv_indev_drv_init(&indev_drv);
242 | indev_drv.type = LV_INDEV_TYPE_ENCODER;
243 | indev_drv.read_cb = encoder_read;
244 | encoder_indev = lv_indev_drv_register(&indev_drv);
245 |
246 | g = lv_group_create();
247 | lv_indev_set_group(encoder_indev, g);
248 |
249 | gui_create();
250 |
251 | lvgl_upd_mutex = osMutexNew(NULL);
252 | LVGL_rfr_evt_id = osEventFlagsNew(NULL);
253 | timer0_id = osTimerNew(timer1_callback, osTimerPeriodic, (void*)0, NULL);
254 | timer1_id = osTimerNew(timer2_callback, osTimerPeriodic, (void*)0, NULL);
255 | T_lvgl_refresh_Thread = osThreadNew(lvgl_refresh_Thread, NULL, &lvgl_refresh_Thread_attr);
256 | osEventFlagsSet(LVGL_rfr_evt_id, 0x0001);
257 | for (;;) {
258 | }
259 | }
260 |
261 | int main(void)
262 | {
263 | // System Initialization
264 | SystemCoreClockUpdate();
265 | osKernelInitialize(); // Initialize CMSIS-RTOS
266 | osThreadNew(app_main, NULL, &main_app_attr); // Create application main thread
267 | osKernelStart(); // Start thread execution
268 | for (;;) {
269 | }
270 | }
271 |
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/misc/delay.c:
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1 | #include "delay.h"
volatile u32 tick = 0;
void SysTick_Handler(void) {
tick++;
}
void delay(uint32_t time, uint32_t load) {
tick = 0;
SysTick_Config(load);
do {
while (!(SysTick->CTRL && SysTick_CTRL_COUNTFLAG_Msk));
} while (tick < time);
SysTick->CTRL = 0;
}
inline void osDelay(uint32_t time) {
delay(time, SystemCoreClock / 1000);
}
inline void delay_us(uint32_t time) {
delay(time, SystemCoreClock / 1000000);
}
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/misc/delay.h:
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1 | #ifndef DELAY_H
2 | #define DELAY_H
3 |
4 | #include "stm32f10x.h"
5 |
6 | void delay_us(uint32_t time);
7 | void osDelay(uint32_t time);
8 |
9 | #endif /* DELAY_H */
10 |
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/misc/led.c:
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1 | #include "stm32f10x.h"
2 |
3 | void LED_PB8_init(void)
4 | {
5 | RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB, ENABLE);
6 | GPIO_InitTypeDef gpioStructure;
7 | gpioStructure.GPIO_Pin = GPIO_Pin_8;
8 | gpioStructure.GPIO_Mode = GPIO_Mode_Out_PP;
9 | gpioStructure.GPIO_Speed = GPIO_Speed_2MHz;
10 | GPIO_Init(GPIOB, &gpioStructure);
11 | GPIO_WriteBit(GPIOB, GPIO_Pin_8, Bit_RESET);
12 | }
13 |
14 |
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/misc/led.h:
--------------------------------------------------------------------------------
1 | void LED_PB8_init(void);
2 |
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/pwm/pwm.c:
--------------------------------------------------------------------------------
1 | #include "stm32f10x.h"
2 | #include "stm32f10x_rcc.h"
3 | #include "stm32f10x_gpio.h"
4 | #include "stm32f10x_tim.h"
5 | #include "pwm.h"
6 |
7 | // GPIOB (PB0) TIM3 PWM
8 |
9 | void PWM_Init(void)
10 | {
11 | // Initialization struct
12 | TIM_TimeBaseInitTypeDef TIM_TimeBaseInitStruct;
13 | TIM_OCInitTypeDef TIM_OCInitStruct;
14 | GPIO_InitTypeDef GPIO_InitStruct;
15 |
16 | // Step 1: Initialize TIM3
17 | RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM3, ENABLE);
18 | // Create 1kHz PWM
19 | // TIM3 is connected to APB1 bus that have default clock 72MHz
20 | // So, the frequency of TIM3 is 72MHz
21 | // We use prescaler 100 here
22 | // So, the frequency of TIM3 now is 720KHz
23 | TIM_TimeBaseInitStruct.TIM_Prescaler = 100;
24 | // TIM_Period determine the PWM frequency by this equation:
25 | // PWM_frequency = timer_clock / (TIM_Period + 1)
26 | // If we want 1Hz PWM we can calculate:
27 | // TIM_Period = (timer_clock / PWM_frequency) - 1
28 | // TIM_Period = (720kHz / 100Hz) - 1 = 7199
29 | TIM_TimeBaseInitStruct.TIM_Period = 7199;
30 | TIM_TimeBaseInitStruct.TIM_ClockDivision = TIM_CKD_DIV1;
31 | TIM_TimeBaseInitStruct.TIM_CounterMode = TIM_CounterMode_Up;
32 | TIM_TimeBaseInit(TIM3, &TIM_TimeBaseInitStruct);
33 | // Start TIM3
34 | TIM_Cmd(TIM3, ENABLE);
35 |
36 | // Step 2: Initialize PWM
37 | // Common PWM settings
38 | TIM_OCInitStruct.TIM_OCMode = TIM_OCMode_PWM1;
39 | TIM_OCInitStruct.TIM_OutputState = TIM_OutputState_Enable;
40 | TIM_OCInitStruct.TIM_OCPolarity = TIM_OCPolarity_High;
41 | // Duty cycle calculation equation:
42 | // TIM_Pulse = (((TIM_Period + 1) * duty_cycle) / 100) - 1
43 | // Ex. 25% duty cycle:
44 | // TIM_Pulse = (((7199 + 1) * 25) / 100) - 1 = 1799
45 | // TIM_Pulse = (((7199 + 1) * 75) / 100) - 1 = 5399
46 | // We initialize PWM value with duty cycle of 0%
47 | TIM_OCInitStruct.TIM_Pulse = 0;
48 | TIM_OC3Init(TIM3, &TIM_OCInitStruct);
49 | TIM_OC3PreloadConfig(TIM3, TIM_OCPreload_Enable);
50 |
51 | // Step 3: Initialize GPIOB (PB0) TIM3
52 | RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB, ENABLE);
53 | // Initialize PB0 as push-pull alternate function (PWM output) for LED
54 | GPIO_InitStruct.GPIO_Pin = GPIO_Pin_0;
55 | GPIO_InitStruct.GPIO_Mode = GPIO_Mode_AF_PP;
56 | GPIO_InitStruct.GPIO_Speed = GPIO_Speed_2MHz;
57 | GPIO_Init(GPIOB, &GPIO_InitStruct);
58 | }
59 |
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/pwm/pwm.h:
--------------------------------------------------------------------------------
1 | void PWM_Init(void);
2 |
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