├── .gitignore ├── CPU ├── CPU.srcs │ ├── sim_1 │ │ └── new │ │ │ ├── test_ALU.v │ │ │ └── test_noflag.v │ └── sources_1 │ │ ├── ip │ │ └── RAM │ │ │ ├── RAM.dcp │ │ │ ├── RAM.veo │ │ │ ├── RAM.vho │ │ │ ├── RAM.xci │ │ │ ├── RAM.xml │ │ │ ├── RAM_ooc.xdc │ │ │ ├── RAM_sim_netlist.v │ │ │ ├── RAM_sim_netlist.vhdl │ │ │ ├── RAM_stub.v │ │ │ ├── RAM_stub.vhdl │ │ │ ├── doc │ │ │ └── blk_mem_gen_v8_4_changelog.txt │ │ │ ├── hdl │ │ │ └── blk_mem_gen_v8_4_vhsyn_rfs.vhd │ │ │ ├── misc │ │ │ └── blk_mem_gen_v8_4.vhd │ │ │ ├── sim │ │ │ └── RAM.v │ │ │ ├── simulation │ │ │ └── blk_mem_gen_v8_4.v │ │ │ └── synth │ │ │ └── RAM.vhd │ │ └── new │ │ ├── ACC.v │ │ ├── ALU.v │ │ ├── BR.v │ │ ├── CU.v │ │ ├── IR.v │ │ ├── MAR.v │ │ ├── MBR.v │ │ ├── MR.v │ │ ├── PC.v │ │ ├── RAM_mod.v │ │ ├── TOP.v │ │ └── params.v ├── CPU.xpr ├── Nexys4DDR_Master.xdc ├── README.md ├── schematic.pdf ├── test_ALU_behav.wcfg ├── test_ALU_flag_behav.wcfg ├── test_CPU_behav.wcfg └── test_nonflag_behav.wcfg ├── Computer Organization and Architecture Course Design.pdf ├── LICENSE ├── POC ├── POC.srcs │ ├── sim_1 │ │ └── new │ │ │ └── test.v │ └── sources_1 │ │ └── new │ │ ├── poc.v │ │ ├── printer.v │ │ ├── processor.v │ │ └── top.v ├── POC.xpr ├── README.md ├── schematic.pdf └── test_behav.wcfg ├── README.md ├── assets ├── CPU.png ├── cpu1.png ├── cpu2.png ├── cpu3.jpg ├── cpu4.png ├── cpu5.png ├── cpu6.png ├── cpu7.png ├── cpu8.png └── poc-1.png ├── coa.code-workspace └── 计算机组织与结构（下）课件（2）-2019-2020-3.pdf /.gitignore: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Sciroccogti/SEU-POC_and_CPU/HEAD/.gitignore -------------------------------------------------------------------------------- /CPU/CPU.srcs/sim_1/new/test_ALU.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Sciroccogti/SEU-POC_and_CPU/HEAD/CPU/CPU.srcs/sim_1/new/test_ALU.v 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