├── fpga_lab2_cnn ├── conv1.cpp ├── conv.h ├── lab2_fpga_lql │ ├── .apc │ │ └── autopilot.apfmapping │ ├── vivado_hls.app │ ├── .settings │ │ ├── lab2_fpga_lql.Debug.launch │ │ ├── lab2_fpga_lql.Release.launch │ │ └── language.settings.xml │ ├── .project │ ├── .vivado_hls_log_all.xml │ └── .cproject ├── cnn_accelerator.h ├── conv_test.cpp ├── conv.cpp └── vivado_hls.log └── README.md /fpga_lab2_cnn/conv1.cpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/SiciliaLeco/hls_cnn_accelerator/HEAD/fpga_lab2_cnn/conv1.cpp -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # hls_cnn_accelerator 2 | 高级硬件设计（HLS）卷积神经网络加速器 3 | 4 | ### 一、完成功能 5 | 1.实现对多通道（16通道）卷积和池化计算进行加速； 6 | 7 | 2.实现卷积与池化的深度融合。 8 | 9 | 3. 使用HLS工具，对其进行优化（如使用pipeline、partition等）。 10 | 11 | ### 二、实验记录 12 | 1.主要的实现在`fpga_lab_2_cnn/conv.cpp`中.测试代码为`fpga_lab2_cnn/conv_test.cpp`. 13 | -------------------------------------------------------------------------------- /fpga_lab2_cnn/conv.h: -------------------------------------------------------------------------------- 1 | #ifndef CONV_H_ 2 | #define CONV_H_ 3 | #include "ap_int.h" 4 | 5 | typedef int din_t; 6 | typedef int dout_t; 7 | 8 | void cnn_accelerator(din_t imgtotal[16*8*8], din_t weitotal[16*3*3], dout_t outtotal[3*3]); 9 | void pool_line_buffer_shift_1_bit(int data); 10 | void conv_line_buffer_shift_1_bit(int data); 11 | int single_pool_calculate(); 12 | int single_conv_calculate(); 13 | #endif 14 | -------------------------------------------------------------------------------- /fpga_lab2_cnn/lab2_fpga_lql/.apc/autopilot.apfmapping: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | -------------------------------------------------------------------------------- /fpga_lab2_cnn/cnn_accelerator.h: -------------------------------------------------------------------------------- 1 | #ifndef CNN_ACCELERATOR_H_ 2 | #define CNN_ACCELERATOR_H_ 3 | 4 | #define WIN_SIZE 3 // must be odd 5 | #define HALF_SIZE ((WIN_SIZE - 1) / 2) 6 | #define HEIGHT 8 7 | #define WIDTH 8 8 | #define PWIN_SIZE 4 9 | #define PHEIGHT HEIGHT - 2 * HALF_SIZE 10 | #define PWIDTH WIDTH - 2 * HALF_SIZE 11 | 12 | int single_conv_calculate(); // 闂佸憡顨嗗ú姗�顢楅悙鍝勭濡炲宸╁┑鍫熷闁挎稑瀚弳锟� 13 | int single_pool_calculate(); // 闂佸憡顨嗗ú姗�顢楅悙娈嬔囨偐閹绘帩鍤欓柣鐘辩筏缁辨洟鎮鹃敓锟� 14 | void conv_accelerate(int img[72], int out[9]); 15 | // void pool_accelerate(hls::stream& in_stream, hls::stream& out_stream); 16 | void conv_line_buffer_shift_1_bit(int data); 17 | void pool_line_buffer_shift_1_bit(int data); 18 | 19 | #endif 20 | -------------------------------------------------------------------------------- /fpga_lab2_cnn/lab2_fpga_lql/vivado_hls.app: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | -------------------------------------------------------------------------------- /fpga_lab2_cnn/conv_test.cpp: -------------------------------------------------------------------------------- 1 | #include "conv.h" 2 | #include 3 | #include "conv.h" 4 | #include 5 | using namespace std; 6 | 7 | int main(void) 8 | { 9 | din_t *img = new din_t[16*8*8]; //input 16 channel images with size 8*8 10 | din_t *wei = new din_t[16*3*3]; //input 16 filters with size of 3*3 11 | dout_t *out = new dout_t[3*3]; //output feature map after convolution and maxpooling 12 | 13 | //initialize img and wei 14 | for(int i=0; i<16*8*8; i++) 15 | img[i] =(din_t)(i%128);//1; 16 | for(int i=0; i<16*3*3; i++) 17 | wei[i] = (din_t)(i%3); 18 | 19 | //get test data from my engine 20 | cnn_accelerator(img, wei, out); 21 | 22 | //calculate golden data 23 | dout_t out1_buf[6][6]; 24 | dout_t out2_buf[3][3]; 25 | memset(out1_buf,0,sizeof(out1_buf)); 26 | memset(out2_buf,0,sizeof(out2_buf)); 27 | 28 | for(int oy=0;oy<6;++oy) //output rows 29 | for(int ox=0;ox<6;++ox) //output columns 30 | for(int kz=0;kz<16;++kz) //input channels 31 | for(int ky=0;ky<3;++ky) //kernel rows 32 | for(int kx=0;kx<3;++kx) //kernel columns 33 | out1_buf[oy][ox] += img[64*kz+8*(oy+ky)+(ox+kx)]*wei[9*kz+3*ky+kx]; 34 | 35 | for(int oy=0; oy<3; oy++) //output rows 36 | for(int ox=0; ox<3; ox++) //output columns 37 | for(int iy=0; iy<2; iy++) //max pooling stride 38 | for(int ix=0; ix<2; ix++) //max pooling stride 39 | if(out1_buf[2*oy+iy][2*ox+ix] > out2_buf[oy][ox]) 40 | out2_buf[oy][ox] = out1_buf[2*oy+iy][2*ox+ix]; 41 | 42 | bool is_valid = true; 43 | cout << "*** output comparison ***" << endl; 44 | for(int i=0; i<3; i++){ 45 | for(int j=0; j<3; j++){ 46 | cout< 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | -------------------------------------------------------------------------------- /fpga_lab2_cnn/lab2_fpga_lql/.settings/lab2_fpga_lql.Release.launch: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | -------------------------------------------------------------------------------- /fpga_lab2_cnn/lab2_fpga_lql/.settings/language.settings.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | 45 | 46 | 47 | 48 | 49 | -------------------------------------------------------------------------------- /fpga_lab2_cnn/lab2_fpga_lql/.project: -------------------------------------------------------------------------------- 1 | 2 | 3 | lab2_fpga_lql 4 | 5 | 6 | 7 | 8 | 9 | org.eclipse.cdt.managedbuilder.core.genmakebuilder 10 | clean,full,incremental, 11 | 12 | 13 | 14 | 15 | org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder 16 | full,incremental, 17 | 18 | 19 | 20 | 21 | 22 | com.autoesl.autopilot.ui.AutopilotNature 23 | org.eclipse.cdt.core.cnature 24 | org.eclipse.cdt.core.ccnature 25 | org.eclipse.cdt.managedbuilder.core.managedBuildNature 26 | org.eclipse.cdt.managedbuilder.core.ScannerConfigNature 27 | 28 | 29 | 30 | source 31 | 2 32 | D:/Desktop/fpga_lab_2/lab2_fpga_lql/.apc/.src 33 | 34 | 35 | testbench 36 | 2 37 | D:/Desktop/fpga_lab_2/lab2_fpga_lql/.apc/.tb 38 | 39 | 40 | solution1/constraints 41 | 2 42 | D:/Desktop/fpga_lab_2/lab2_fpga_lql/solution1/.tcls 43 | 44 | 45 | solution2_pipeline/constraints 46 | 2 47 | D:/Desktop/fpga_lab_2/lab2_fpga_lql/solution2_pipeline/.tcls 48 | 49 | 50 | solution4_partition/constraints 51 | 2 52 | D:/Desktop/fpga_lab_2/lab2_fpga_lql/solution4_partition/.tcls 53 | 54 | 55 | solution5_unroll_11/constraints 56 | 2 57 | D:/Desktop/fpga_lab_2/lab2_fpga_lql/solution5_unroll_11/.tcls 58 | 59 | 60 | source/conv.cpp 61 | 1 62 | D:/Desktop/fpga_lab_2/conv.cpp 63 | 64 | 65 | testbench/conv_test.cpp 66 | 1 67 | D:/Desktop/fpga_lab_2/conv_test.cpp 68 | 69 | 70 | solution1/constraints/.xml.directive 71 | 1 72 | D:/Desktop/fpga_lab_2/lab2_fpga_lql/solution1/solution1.directive 73 | 74 | 75 | solution1/constraints/directives.tcl 76 | 1 77 | D:/Desktop/fpga_lab_2/lab2_fpga_lql/solution1/directives.tcl 78 | 79 | 80 | solution1/constraints/script.tcl 81 | 1 82 | D:/Desktop/fpga_lab_2/lab2_fpga_lql/solution1/script.tcl 83 | 84 | 85 | solution2_pipeline/constraints/.xml.directive 86 | 1 87 | D:/Desktop/fpga_lab_2/lab2_fpga_lql/solution2_pipeline/solution2_pipeline.directive 88 | 89 | 90 | solution2_pipeline/constraints/directives.tcl 91 | 1 92 | D:/Desktop/fpga_lab_2/lab2_fpga_lql/solution2_pipeline/directives.tcl 93 | 94 | 95 | solution2_pipeline/constraints/script.tcl 96 | 1 97 | D:/Desktop/fpga_lab_2/lab2_fpga_lql/solution2_pipeline/script.tcl 98 | 99 | 100 | solution4_partition/constraints/.xml.directive 101 | 1 102 | D:/Desktop/fpga_lab_2/lab2_fpga_lql/solution4_partition/solution4_partition.directive 103 | 104 | 105 | solution4_partition/constraints/directives.tcl 106 | 1 107 | D:/Desktop/fpga_lab_2/lab2_fpga_lql/solution4_partition/directives.tcl 108 | 109 | 110 | solution4_partition/constraints/script.tcl 111 | 1 112 | D:/Desktop/fpga_lab_2/lab2_fpga_lql/solution4_partition/script.tcl 113 | 114 | 115 | solution5_unroll_11/constraints/.xml.directive 116 | 1 117 | D:/Desktop/fpga_lab_2/lab2_fpga_lql/solution5_unroll_11/solution5_unroll_11.directive 118 | 119 | 120 | solution5_unroll_11/constraints/directives.tcl 121 | 1 122 | D:/Desktop/fpga_lab_2/lab2_fpga_lql/solution5_unroll_11/directives.tcl 123 | 124 | 125 | solution5_unroll_11/constraints/script.tcl 126 | 1 127 | D:/Desktop/fpga_lab_2/lab2_fpga_lql/solution5_unroll_11/script.tcl 128 | 129 | 130 | 131 | -------------------------------------------------------------------------------- /fpga_lab2_cnn/conv.cpp: -------------------------------------------------------------------------------- 1 | #include 2 | using namespace std; 3 | #define WIN_SIZE 3 // convolution layer's kernel size 4 | #define HALF_SIZE ((WIN_SIZE - 1) / 2) 5 | #define HEIGHT 8 // input feature map size 6 | #define WIDTH 8 // input feature map size 7 | #define PHEIGHT 6 // convolution result size 8 | #define PWIDTH 6 9 | #define PWIN_SIZE 2 //pooling layer's kernel size 10 | #define CHANNEL 16 11 | 12 | typedef int din_t; 13 | typedef int dout_t; 14 | /* 15 | cal_**** represents the window under calculation in each operation 16 | ****_line_buffer represents the linebuffer 17 | the function is same to that of hls:: 18 | */ 19 | int cal_conv[WIN_SIZE][WIN_SIZE]; 20 | int cal_pool[PWIN_SIZE][PWIN_SIZE]; 21 | int kernel[WIN_SIZE][WIN_SIZE]; 22 | int conv_line_buffer[PWIN_SIZE][8]; 23 | int pool_line_buffer[PWIDTH]; 24 | int conv_result[PHEIGHT][PWIDTH]; 25 | 26 | int single_conv_calculate() 27 | { 28 | // convolution single operation 29 | int ans = 0; 30 | single_conv_calculate_label0:for(int i = 0; i < WIN_SIZE; i++) 31 | { 32 | single_conv_calculate_label1:for(int j = 0; j < WIN_SIZE; j++) 33 | { 34 | ans += cal_conv[i][j] * kernel[i][j]; 35 | } 36 | } 37 | return ans; 38 | } 39 | 40 | int single_pool_calculate() 41 | { 42 | // max pooling single operation 43 | int ans = 0; 44 | single_pool_calculate_label2:for(int i = 0; i <= PWIN_SIZE; i++) 45 | { 46 | single_pool_calculate_label3:for(int j = 0; j <= PWIN_SIZE; j++) 47 | { 48 | ans = ans > cal_pool[i][j]?ans:cal_pool[i][j]; 49 | } 50 | } 51 | return ans; 52 | } 53 | 54 | void conv_line_buffer_shift_1_bit(int data) 55 | { 56 | // convolution shift up function 57 | /* 58 | ----------------- 59 | |1*-|2*-|3*-| 4-| 5-| 6-| 7-| 8-| 60 | 61 | |1*-|2*-|3*-| 4-| 5-| 6-| 7-| 8-| 62 | 63 | |1* |2* |3* | 4 | 5 | 6 | 7 | 8 | 64 | 65 | * : cal_conv 66 | - : conv_linebuffer 67 | 68 | */ 69 | int go_up[2]; // use to update conv_linebuffer 70 | go_up[0] = cal_conv[1][0]; 71 | go_up[1] = cal_conv[2][0]; 72 | 73 | // first update cal_conv 74 | conv_line_buffer_shift_1_bit_label4:for(int i = 0; i < WIN_SIZE; i++) 75 | { 76 | conv_line_buffer_shift_1_bit_label5:for(int j = 0; j < WIN_SIZE; j++) 77 | { 78 | if(j < WIN_SIZE - 1) 79 | cal_conv[i][j] = cal_conv[i][j + 1]; 80 | else if(i < WIN_SIZE - 1) 81 | cal_conv[i][j] = conv_line_buffer[i][WIN_SIZE]; 82 | else 83 | cal_conv[i][j] = data; 84 | } 85 | } 86 | 87 | conv_line_buffer_shift_1_bit_label6:for(int i = 0; i < WIN_SIZE - 1; i++) 88 | { 89 | conv_line_buffer_shift_1_bit_label7:for(int j = 0; j < WIDTH; j++) 90 | { 91 | if(j == WIDTH - 1) 92 | conv_line_buffer[i][j] = go_up[i]; 93 | else 94 | conv_line_buffer[i][j] = conv_line_buffer[i][j + 1]; 95 | 96 | } 97 | } 98 | } 99 | 100 | void pool_line_buffer_shift_1_bit(int data) 101 | { 102 | // pooling layer shift 1 bit up 103 | int go_up=cal_pool[1][0]; 104 | 105 | cal_pool[0][0] = cal_pool[0][1]; 106 | cal_pool[0][1] = pool_line_buffer[WIN_SIZE - 1]; 107 | cal_pool[1][0] = cal_pool[1][1]; 108 | cal_pool[1][1] = data; 109 | 110 | pool_line_buffer_shift_1_bit_label8:for(int i = 0; i < PWIDTH - 1; i++) 111 | pool_line_buffer[i] = pool_line_buffer[i+1]; 112 | 113 | pool_line_buffer[PWIDTH-1] = go_up; 114 | } 115 | 116 | 117 | void cnn_accelerator(din_t imgtotal[16*8*8], din_t weitotal[16*3*3], dout_t outtotal[3*3]){ 118 | /* accelerator of the cnn 119 | 1. do 15 times of convolution calculation (multi-channel) 120 | 2. in the 16 cycle, parallel do pool 121 | 122 | */ 123 | 124 | din_t conv_output[6][6]; 125 | int out_count = 0; 126 | single_conv_test_label9:for(int i =0;i<6;i++) 127 | single_conv_test_label10:for(int j =0;j<6;j++) 128 | conv_output[i][j] = 0; 129 | int conv_count = 0; 130 | single_conv_test_label11:for(int c = 0; c < CHANNEL; c++) 131 | { 132 | #pragma HLS UNROLL 133 | din_t img[8*8]; 134 | // initialize img and kernel 135 | single_conv_test_label12:for(int img_i = 0; img_i < 8 * 8; img_i++) 136 | img[img_i] = imgtotal[c * 64 + img_i]; 137 | 138 | single_conv_test_label13:for(int ker_i = 0; ker_i < 3 * 3; ker_i++) 139 | kernel[ker_i / 3][ker_i % 3] = weitotal[ker_i]; 140 | 141 | int count = 0; 142 | single_conv_test_label14:for(int i = 0; i < WIN_SIZE - 1; i++) 143 | { 144 | single_conv_test_label15:for(int j = 0; j < WIDTH; j++) 145 | { 146 | int data=img[count++]; 147 | if(j < WIN_SIZE) 148 | { 149 | cal_conv[i][j] = data; 150 | conv_line_buffer[i][j] = data; 151 | } 152 | else 153 | { 154 | conv_line_buffer[i][j] = data; 155 | } 156 | } 157 | } 158 | 159 | 160 | single_conv_test_label16:for(int i = 0; i < WIN_SIZE; i++) 161 | cal_conv[WIN_SIZE-1][i] = img[count++]; 162 | 163 | int cal_result_count = 0; 164 | single_conv_test_label17:for(int i = 0; i < PHEIGHT; i++) 165 | { 166 | single_conv_test_label18:for(int j = 0; j < PWIDTH; j++) 167 | { 168 | int out; 169 | if(j < PWIDTH - 1) 170 | { 171 | out = single_conv_calculate(); 172 | int data=img[count++]; 173 | conv_line_buffer_shift_1_bit(data); 174 | } 175 | else 176 | { 177 | single_conv_test_label19:for(int i1 = 0; i1 < WIN_SIZE; i1++) 178 | { 179 | if(i1 == 0){ 180 | out = single_conv_calculate(); 181 | } 182 | int data=img[count++]; 183 | conv_line_buffer_shift_1_bit(data); //shift up and do 184 | } 185 | } 186 | conv_output[i][j] += out; 187 | 188 | if(c == 15){ // pooling start 189 | int pool_output; 190 | if(i == 0) 191 | { 192 | if(j < PWIN_SIZE) 193 | cal_pool[i][j] = conv_output[i][j]; 194 | pool_line_buffer[j] = conv_output[i][j]; 195 | } 196 | 197 | else if((i == 1) && j < PWIN_SIZE){ 198 | cal_pool[i][j] = conv_output[i][j]; 199 | } 200 | else{ 201 | pool_line_buffer_shift_1_bit(conv_output[i][j]); 202 | } 203 | if(i%2==1){ 204 | if(j%2==1) 205 | { 206 | outtotal[out_count++] = single_pool_calculate(); 207 | 208 | } 209 | } 210 | } 211 | 212 | } 213 | } 214 | 215 | } 216 | } 217 | 218 | -------------------------------------------------------------------------------- /fpga_lab2_cnn/lab2_fpga_lql/.vivado_hls_log_all.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | 45 | 46 | 47 | 48 | 49 | 50 | 51 | 52 | -------------------------------------------------------------------------------- /fpga_lab2_cnn/vivado_hls.log: -------------------------------------------------------------------------------- 1 | INFO: [HLS 200-10] Running 'C:/Xilinx/Vivado/2019.1/bin/unwrapped/win64.o/vivado_hls.exe' 2 | INFO: [HLS 200-10] For user 'Cheryl' on host 'desktop-g2qn9mv' (Windows NT_amd64 version 6.2) on Sun Dec 06 13:34:04 +0800 2020 3 | INFO: [HLS 200-10] In directory 'D:/Desktop/fpga_lab_2' 4 | Sourcing Tcl script 'D:/Desktop/fpga_lab_2/lab2_fpga_lql/solution5_unroll_11/csynth.tcl' 5 | INFO: [HLS 200-10] Opening project 'D:/Desktop/fpga_lab_2/lab2_fpga_lql'. 6 | INFO: [HLS 200-10] Adding design file 'conv.cpp' to the project 7 | INFO: [HLS 200-10] Adding test bench file 'conv_test.cpp' to the project 8 | INFO: [HLS 200-10] Opening solution 'D:/Desktop/fpga_lab_2/lab2_fpga_lql/solution5_unroll_11'. 9 | INFO: [SYN 201-201] Setting up clock 'default' with a period of 10ns. 10 | WARNING: [HLS 200-40] Cannot find library 'C:/Xilinx/Vivado/2019.1/common/technology/xilinx/Artix-7/Artix-7.lib'. 11 | WARNING: [HLS 200-40] Cannot find library 'xilinx/Artix-7/Artix-7'. 12 | INFO: [HLS 200-10] Setting target device to 'xc7a12ti-csg325-1L' 13 | INFO: [SCHED 204-61] Option 'relax_ii_for_timing' is enabled, will increase II to preserve clock frequency constraints. 14 | INFO: [HLS 200-10] Analyzing design file 'conv.cpp' ... 15 | INFO: [HLS 200-111] Finished Linking Time (s): cpu = 00:00:01 ; elapsed = 00:00:11 . Memory (MB): peak = 146.199 ; gain = 54.543 16 | INFO: [HLS 200-111] Finished Checking Pragmas Time (s): cpu = 00:00:01 ; elapsed = 00:00:11 . Memory (MB): peak = 146.199 ; gain = 54.543 17 | INFO: [HLS 200-10] Starting code transformations ... 18 | INFO: [HLS 200-111] Finished Standard Transforms Time (s): cpu = 00:00:01 ; elapsed = 00:00:12 . Memory (MB): peak = 146.199 ; gain = 54.543 19 | INFO: [HLS 200-10] Checking synthesizability ... 20 | INFO: [XFORM 203-602] Inlining function 'pool_line_buffer_shift_1_bit' into 'single_conv_test' (conv.cpp:186) automatically. 21 | INFO: [HLS 200-111] Finished Checking Synthesizability Time (s): cpu = 00:00:02 ; elapsed = 00:00:12 . Memory (MB): peak = 146.199 ; gain = 54.543 22 | INFO: [HLS 200-489] Unrolling loop 'single_conv_test_label11' (conv.cpp:113) in function 'single_conv_test' completely with a factor of 16. 23 | INFO: [XFORM 203-102] Automatically partitioning small array 'go_up' (conv.cpp:57) completely based on array size. 24 | INFO: [XFORM 203-101] Partitioning array 'go_up' (conv.cpp:57) in dimension 1 completely. 25 | INFO: [XFORM 203-602] Inlining function 'pool_line_buffer_shift_1_bit' into 'single_conv_test' (conv.cpp:186) automatically. 26 | WARNING: [ANALYSIS 214-31] The program may have out of bound access of array variable 'cal_pool' in function 'single_pool_calculate' (conv.cpp:48:5). 27 | WARNING: [ANALYSIS 214-31] The program may have out of bound access of array variable 'cal_conv' in function 'single_conv_test' (conv.cpp:132:7). 28 | WARNING: [ANALYSIS 214-31] The program may have out of bound access of array variable 'cal_conv' in function 'single_conv_test' (conv.cpp:132:7). 29 | WARNING: [ANALYSIS 214-31] The program may have out of bound access of array variable 'cal_conv' in function 'single_conv_test' (conv.cpp:132:7). 30 | WARNING: [ANALYSIS 214-31] The program may have out of bound access of array variable 'cal_conv' in function 'single_conv_test' (conv.cpp:132:7). 31 | WARNING: [ANALYSIS 214-31] The program may have out of bound access of array variable 'cal_conv' in function 'single_conv_test' (conv.cpp:132:7). 32 | WARNING: [ANALYSIS 214-31] The program may have out of bound access of array variable 'cal_conv' in function 'single_conv_test' (conv.cpp:132:7). 33 | WARNING: [ANALYSIS 214-31] The program may have out of bound access of array variable 'cal_conv' in function 'single_conv_test' (conv.cpp:132:7). 34 | WARNING: [ANALYSIS 214-31] The program may have out of bound access of array variable 'cal_conv' in function 'single_conv_test' (conv.cpp:132:7). 35 | WARNING: [ANALYSIS 214-31] The program may have out of bound access of array variable 'cal_conv' in function 'single_conv_test' (conv.cpp:132:7). 36 | WARNING: [ANALYSIS 214-31] The program may have out of bound access of array variable 'cal_conv' in function 'single_conv_test' (conv.cpp:132:7). 37 | WARNING: [ANALYSIS 214-31] The program may have out of bound access of array variable 'cal_conv' in function 'single_conv_test' (conv.cpp:132:7). 38 | WARNING: [ANALYSIS 214-31] The program may have out of bound access of array variable 'cal_conv' in function 'single_conv_test' (conv.cpp:132:7). 39 | WARNING: [ANALYSIS 214-31] The program may have out of bound access of array variable 'cal_conv' in function 'single_conv_test' (conv.cpp:132:7). 40 | WARNING: [ANALYSIS 214-31] The program may have out of bound access of array variable 'cal_conv' in function 'single_conv_test' (conv.cpp:132:7). 41 | WARNING: [ANALYSIS 214-31] The program may have out of bound access of array variable 'cal_conv' in function 'single_conv_test' (conv.cpp:132:7). 42 | WARNING: [ANALYSIS 214-31] The program may have out of bound access of array variable 'cal_conv' in function 'single_conv_test' (conv.cpp:132:7). 43 | WARNING: [ANALYSIS 214-31] The program may have out of bound access of array variable 'cal_pool' in function 'single_conv_test' (conv.cpp:178:8). 44 | WARNING: [ANALYSIS 214-31] The program may have out of bound access of array variable 'cal_pool' in function 'single_conv_test' (conv.cpp:183:7). 45 | WARNING: [ANALYSIS 214-31] The program may have out of bound access of array variable 'conv_line_buffer' in function 'conv_line_buffer_shift_1_bit' (conv.cpp:69:5). 46 | INFO: [XFORM 203-102] Automatically partitioning small array 'cal_pool' completely based on array size. 47 | INFO: [XFORM 203-101] Partitioning array 'cal_pool' in dimension 1 completely. 48 | INFO: [XFORM 203-101] Partitioning array 'cal_pool' in dimension 2 completely. 49 | INFO: [XFORM 203-401] Performing if-conversion on hyperblock from (conv.cpp:47:4) to (conv.cpp:46:55) in function 'single_pool_calculate'... converting 4 basic blocks. 50 | INFO: [XFORM 203-602] Inlining function 'single_pool_calculate' into 'single_conv_test' (conv.cpp:191) automatically. 51 | INFO: [HLS 200-111] Finished Pre-synthesis Time (s): cpu = 00:00:06 ; elapsed = 00:00:17 . Memory (MB): peak = 160.020 ; gain = 68.363 52 | WARNING: [XFORM 203-631] Renaming function 'single_conv_calculate' to 'single_conv_calculat' (conv.cpp:30:54) 53 | WARNING: [XFORM 203-631] Renaming function 'conv_line_buffer_shift_1_bit' to 'conv_line_buffer_shi' (conv.cpp:58:62) 54 | INFO: [HLS 200-111] Finished Architecture Synthesis Time (s): cpu = 00:00:10 ; elapsed = 00:00:21 . Memory (MB): peak = 190.305 ; gain = 98.648 55 | INFO: [HLS 200-10] Starting hardware synthesis ... 56 | INFO: [HLS 200-10] Synthesizing 'single_conv_test' ... 57 | INFO: [HLS 200-10] ---------------------------------------------------------------- 58 | INFO: [HLS 200-42] -- Implementing module 'single_conv_calculat' 59 | INFO: [HLS 200-10] ---------------------------------------------------------------- 60 | INFO: [SCHED 204-11] Starting scheduling ... 61 | INFO: [SCHED 204-11] Finished scheduling. 62 | INFO: [HLS 200-111] Elapsed time: 21.639 seconds; current allocated memory: 136.146 MB. 63 | INFO: [HLS 200-434] Only 0 loops out of a total 2 loops have been pipelined in this design. 64 | INFO: [BIND 205-100] Starting micro-architecture generation ... 65 | INFO: [BIND 205-101] Performing variable lifetime analysis. 66 | INFO: [BIND 205-101] Exploring resource sharing. 67 | INFO: [BIND 205-101] Binding ... 68 | INFO: [BIND 205-100] Finished micro-architecture generation. 69 | INFO: [HLS 200-111] Elapsed time: 0.264 seconds; current allocated memory: 136.292 MB. 70 | INFO: [HLS 200-10] ---------------------------------------------------------------- 71 | INFO: [HLS 200-42] -- Implementing module 'conv_line_buffer_shi' 72 | INFO: [HLS 200-10] ---------------------------------------------------------------- 73 | INFO: [SCHED 204-11] Starting scheduling ... 74 | INFO: [SCHED 204-11] Finished scheduling. 75 | INFO: [HLS 200-111] Elapsed time: 0.267 seconds; current allocated memory: 136.519 MB. 76 | INFO: [BIND 205-100] Starting micro-architecture generation ... 77 | INFO: [BIND 205-101] Performing variable lifetime analysis. 78 | INFO: [BIND 205-101] Exploring resource sharing. 79 | INFO: [BIND 205-101] Binding ... 80 | INFO: [BIND 205-100] Finished micro-architecture generation. 81 | INFO: [HLS 200-111] Elapsed time: 0.228 seconds; current allocated memory: 136.794 MB. 82 | INFO: [HLS 200-10] ---------------------------------------------------------------- 83 | INFO: [HLS 200-42] -- Implementing module 'single_conv_test' 84 | INFO: [HLS 200-10] ---------------------------------------------------------------- 85 | INFO: [SCHED 204-11] Starting scheduling ... 86 | INFO: [SCHED 204-11] Finished scheduling. 87 | INFO: [HLS 200-111] Elapsed time: 1.91 seconds; current allocated memory: 142.842 MB. 88 | INFO: [BIND 205-100] Starting micro-architecture generation ... 89 | INFO: [BIND 205-101] Performing variable lifetime analysis. 90 | INFO: [BIND 205-101] Exploring resource sharing. 91 | INFO: [BIND 205-101] Binding ... 92 | INFO: [BIND 205-100] Finished micro-architecture generation. 93 | INFO: [HLS 200-111] Elapsed time: 3.127 seconds; current allocated memory: 151.275 MB. 94 | INFO: [HLS 200-10] ---------------------------------------------------------------- 95 | INFO: [HLS 200-10] -- Generating RTL for module 'single_conv_calculat' 96 | INFO: [HLS 200-10] ---------------------------------------------------------------- 97 | INFO: [RTGEN 206-100] Finished creating RTL model for 'single_conv_calculat'. 98 | INFO: [HLS 200-111] Elapsed time: 3.305 seconds; current allocated memory: 152.089 MB. 99 | INFO: [HLS 200-10] ---------------------------------------------------------------- 100 | INFO: [HLS 200-10] -- Generating RTL for module 'conv_line_buffer_shi' 101 | INFO: [HLS 200-10] ---------------------------------------------------------------- 102 | INFO: [RTGEN 206-100] Finished creating RTL model for 'conv_line_buffer_shi'. 103 | INFO: [HLS 200-111] Elapsed time: 0.497 seconds; current allocated memory: 152.656 MB. 104 | INFO: [HLS 200-10] ---------------------------------------------------------------- 105 | INFO: [HLS 200-10] -- Generating RTL for module 'single_conv_test' 106 | INFO: [HLS 200-10] ---------------------------------------------------------------- 107 | INFO: [RTGEN 206-500] Setting interface mode on port 'single_conv_test/imgtotal' to 'ap_memory'. 108 | INFO: [RTGEN 206-500] Setting interface mode on port 'single_conv_test/weitotal' to 'ap_memory'. 109 | INFO: [RTGEN 206-500] Setting interface mode on port 'single_conv_test/outtotal' to 'ap_memory'. 110 | INFO: [RTGEN 206-500] Setting interface mode on function 'single_conv_test' to 'ap_ctrl_hs'. 111 | INFO: [SYN 201-210] Renamed object name 'single_conv_test_cal_conv' to 'single_conv_test_bkb' due to the length limit 20 112 | INFO: [SYN 201-210] Renamed object name 'single_conv_test_conv_line_buffer' to 'single_conv_test_cud' due to the length limit 20 113 | INFO: [SYN 201-210] Renamed object name 'single_conv_test_kernel' to 'single_conv_test_dEe' due to the length limit 20 114 | WARNING: [RTGEN 206-101] Register 'cal_pool_0_0' is power-on initialization. 115 | WARNING: [RTGEN 206-101] Register 'cal_pool_0_1' is power-on initialization. 116 | WARNING: [RTGEN 206-101] Register 'cal_pool_1_0' is power-on initialization. 117 | WARNING: [RTGEN 206-101] Register 'cal_pool_1_1' is power-on initialization. 118 | INFO: [SYN 201-210] Renamed object name 'single_conv_test_pool_line_buffer' to 'single_conv_test_eOg' due to the length limit 20 119 | INFO: [SYN 201-210] Renamed object name 'single_conv_test_conv_output' to 'single_conv_test_fYi' due to the length limit 20 120 | INFO: [SYN 201-210] Renamed object name 'single_conv_test_img' to 'single_conv_test_g8j' due to the length limit 20 121 | INFO: [RTGEN 206-100] Finished creating RTL model for 'single_conv_test'. 122 | INFO: [HLS 200-111] Elapsed time: 2.111 seconds; current allocated memory: 164.422 MB. 123 | INFO: [RTMG 210-278] Implementing memory 'single_conv_test_bkb_ram (RAM)' using block RAMs with power-on initialization. 124 | INFO: [RTMG 210-278] Implementing memory 'single_conv_test_cud_ram (RAM)' using distributed RAMs with power-on initialization. 125 | INFO: [RTMG 210-278] Implementing memory 'single_conv_test_dEe_ram (RAM)' using distributed RAMs with power-on initialization. 126 | INFO: [RTMG 210-278] Implementing memory 'single_conv_test_eOg_ram (RAM)' using distributed RAMs with power-on initialization. 127 | INFO: [RTMG 210-278] Implementing memory 'single_conv_test_fYi_ram (RAM)' using block RAMs. 128 | INFO: [RTMG 210-278] Implementing memory 'single_conv_test_g8j_ram (RAM)' using block RAMs. 129 | INFO: [HLS 200-111] Finished generating all RTL models Time (s): cpu = 00:00:25 ; elapsed = 00:00:46 . Memory (MB): peak = 276.051 ; gain = 184.395 130 | INFO: [VHDL 208-304] Generating VHDL RTL for single_conv_test. 131 | INFO: [VLOG 209-307] Generating Verilog RTL for single_conv_test. 132 | INFO: [HLS 200-112] Total elapsed time: 46.1 seconds; peak allocated memory: 164.422 MB. 133 | -------------------------------------------------------------------------------- /fpga_lab2_cnn/lab2_fpga_lql/.cproject: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | 45 | 46 | 47 | 48 | 65 | 66 | 75 | 76 | 77 | 78 | 79 | 80 | 81 | 82 | 99 | 100 | 109 | 110 | 111 | 112 | 113 | 114 | 115 | 116 | 121 | 122 | 127 | 128 | 129 | 130 | 135 | 136 | 149 | 150 | 151 | 152 | 153 | 154 | 155 | 156 | 157 | 158 | 159 | 160 | 161 | 162 | 163 | 164 | 181 | 182 | 187 | 188 | 189 | 190 | 191 | 192 | 193 | 194 | 195 | 196 | 197 | 198 | 199 | 200 | 201 | 202 | 203 | 204 | 205 | 206 | 207 | 208 | 209 | 210 | 211 | 212 | 213 | 214 | 215 | 216 | 217 | 218 | 219 | 220 | 221 | 222 | 223 | 224 | 225 | 226 | 227 | 228 | 229 | 230 | 231 | 232 | 233 | 234 | 235 | 236 | 237 | 238 | 239 | 240 | 241 | 242 | 243 | 244 | 245 | 246 | 263 | 264 | 265 | 266 | 267 | 268 | 269 | 270 | 287 | 288 | 289 | 290 | 291 | 292 | 293 | 294 | 299 | 300 | 305 | 306 | 307 | 308 | 313 | 314 | 327 | 328 | 329 | 330 | 331 | 332 | 333 | 334 | 335 | 336 | 337 | 338 | 339 | 340 | 341 | 342 | 359 | 360 | 365 | 366 | 367 | 368 | 369 | 370 | 371 | 372 | 373 | 374 | 375 | 376 | 377 | 378 | 379 | 380 | 381 | 382 | 383 | 384 | 385 | 386 | 387 | 388 | 389 | 390 | 391 | 392 | 393 | 394 | 395 | 396 | 397 | 398 | 399 | 400 | 401 | 402 | 403 | 404 | 405 | 406 | 407 | 408 | 409 | 410 | 411 | 412 | 413 | 414 | 415 | 416 | 417 | 418 | 419 | 420 | 421 | 422 | 423 | --------------------------------------------------------------------------------