├── .gitignore ├── CommitHistoryVisualizer ├── Verilog.gif └── Verilog.mp4 ├── Lab1 ├── Lab1_Sheet.pdf ├── NAND_from_AND_n_NOT.v ├── README.md ├── addSub_4bit.v ├── bcd2gray.v ├── fadder_1bit.v ├── fadder_4bit.v ├── filename.vcd ├── magcomp.v ├── module.png ├── mux2to1_beh.v ├── mux2to1_df.v ├── mux2to1_gate.v ├── mux_2to1.v ├── tb_addSub_4bit.v ├── tb_fadder_1bit.v ├── tb_fadder_4bit.v ├── test.out ├── test.v └── testbench_mux2to1_gate.v ├── Lab2 ├── ADDER_8bit.v ├── DECODER.v ├── FADDER.v ├── Lab_Sheet_2_Final.pdf ├── README.md ├── adder_32bit.v ├── comparator_4bit.v ├── decoder_3to1.v ├── fadder_bhvrl.v ├── fadder_dec.v ├── mux16to1_glvl.v ├── mux4to1_gate.v ├── mux4to1_glvl.v ├── tb_comparator_4bit.v ├── tb_fadder_dec.v ├── tb_mux16to1_glvl.v ├── tb_mux4to1_glvl ├── tb_mux4to1_glvl.v ├── test ├── test.v ├── testbench_adder_32bit.v ├── testbench_adder_8bit.v └── testbench_fadder.v ├── Lab3 ├── 4bit_shift_test.PNG ├── Lab_Sheet_3_Final.pdf ├── README.md ├── counter4bit.v ├── counter_4bit.PNG ├── dff_async_clear.v ├── dff_sync_clear.v ├── fullAdder1bit.v ├── mealy.v ├── mealyOutput.PNG ├── mealy_test.v ├── seqDetect.v ├── seqDetect_10110.PNG ├── serialAdder_4bit.PNG ├── serialAdder_4bit.v ├── shift_reg_4bit.png ├── shift_reg_4bit.v ├── shift_reg_4bit_lab.v ├── tb_32bitReg.PNG ├── tb_counter4bit.v ├── tb_serialAdder4bit.v ├── test_dff_sync.v ├── test_seqDetect.v ├── test_shift_reg_4bit.v └── test_shift_reg_4bit_lab.v ├── Lab4 ├── Lab4_sheet_aludesign.pdf ├── MainCU.PNG ├── README.md ├── alu.v ├── aluCU.v ├── fulladder_32bit.v ├── mainCU.v ├── module_32bitAND.v ├── module_32bitOR.v ├── mux_2to1.v ├── mux_2to1_32bit.v ├── mux_2to1_8bit.v ├── mux_3to1_32bit.v ├── tbALU.v ├── tb_aluCU.PNG ├── tb_aluCU.v ├── test_32bitAND.v ├── test_32bitOR.v ├── test_32bitadder.v ├── test_mainCU.v ├── test_mux_2to1_32bit.v ├── test_mux_2to1_8bit.PNG ├── test_mux_2to1_8bit.v └── test_mux_3to1_32bit.v ├── Lab5 ├── Lab5_sheet_registerfile.pdf ├── README.md ├── decoder_2to4.v ├── mux_4to1.v ├── regFile.v ├── reg_32bit.v └── tb_reg32bit.v ├── Lab6 ├── ADDER_8bit.v ├── Lab_Sheet_6_Single_Cycle_Datapath_Final.pdf ├── README.md ├── SCDatapath.v ├── adder_32bit.v ├── alu.v ├── aluCU.v ├── dm.v ├── im.v ├── regFile.v ├── reg_32bit.v ├── shifter.v └── signExt.v ├── Lab7 ├── LabSheet7.pdf ├── README.md ├── mainController.v └── tb_mc.v ├── Lab8 ├── Lab_Sheet_8_Pipeline_DesignF.pdf ├── README.md ├── pipelineAlu.v ├── pipelineCircuit.v ├── pipelineEnc.v ├── pipelineParGen.v ├── tb_pipeline.png └── tb_pipeline.v ├── LabTestPractice ├── 2k11-12 │ ├── LabTest.pdf │ ├── Solution │ │ ├── ALU64bit.v │ │ ├── AlgoTest.v │ │ ├── Decrypt.v │ │ ├── Encrypt.v │ │ ├── Keygen.v │ │ └── Padding.v │ └── file.v ├── 2k13-14 │ ├── LabTest.pdf │ └── file.v ├── 2k15-16 │ ├── Labtest_prev.pdf │ └── file.v ├── 2k16-17 │ ├── file.v │ └── last_year_paper.pdf ├── 2k17-18 │ ├── LabTest_part1.jpg │ ├── Labtest_part2.jpg │ ├── counter_3bit.v │ ├── counter_4bit.v │ ├── dff_async_clear.v │ ├── dff_sync_clear.v │ ├── intg.v │ ├── memory.v │ ├── muxLarge.v │ ├── muxSmall.v │ ├── tb_dff_sync.v │ ├── tb_intg.v │ └── tff.v ├── 2k18-19 │ ├── 2k18-19_1..jpg │ ├── 2k18-19_2.jpg │ └── file.v ├── 2k19-20 │ ├── 2k19_20.pdf │ ├── file.v │ └── markingScheme.jpg ├── 2k20-21 │ ├── Lab Test Sol+Marking Scheme.pdf │ └── Lab Test.jpg ├── mealy.v └── tb_mealy.v ├── PracticeQuestions └── Lab1_2 │ ├── README.md │ ├── README.pdf │ ├── Solutions.md │ └── Solutions.pdf ├── README.md ├── Samir Palnitkar - Verilog HDL-Prentice Hall (1996).pdf ├── Verilog_Notes.pdf └── _config.yml /.gitignore: -------------------------------------------------------------------------------- 1 | *.vvp 2 | *.vcd 3 | -------------------------------------------------------------------------------- /CommitHistoryVisualizer/Verilog.gif: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/SinghCoder/Icarus_Verilog/c326ccb1b1a354daaf6e61368712536428445de5/CommitHistoryVisualizer/Verilog.gif -------------------------------------------------------------------------------- /CommitHistoryVisualizer/Verilog.mp4: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/SinghCoder/Icarus_Verilog/c326ccb1b1a354daaf6e61368712536428445de5/CommitHistoryVisualizer/Verilog.mp4 -------------------------------------------------------------------------------- /Lab1/Lab1_Sheet.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/SinghCoder/Icarus_Verilog/c326ccb1b1a354daaf6e61368712536428445de5/Lab1/Lab1_Sheet.pdf -------------------------------------------------------------------------------- /Lab1/NAND_from_AND_n_NOT.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | module NAND_from_AND_n_NOT (c,a,b); 3 | 4 | //declare port signals 5 | output c; 6 | input a,b; 7 | 8 | //declare internal wire 9 | wire d; 10 | 11 | //instantiate structural logic gates 12 | //d = output, a and b = input 13 | and a1(d,a,b); 14 | // c = output, d = input 15 | not(c,d); 16 | endmodule -------------------------------------------------------------------------------- /Lab1/README.md: -------------------------------------------------------------------------------- 1 | # Lab Sheet 1 2 | 3 | ## LearningObjectives 4 | 5 | - Getting started with HDL program using Icarus Simulator 6 | - Understand basic Verilog language primitives (e.g. module, datatypes, identifiers, vectors, registers, keywords etc. ) 7 | - To understand the various types of modeling 8 | 9 | ## Verilog 10 | 11 | - a Hardware Description Language (HDL) 12 | - Didgital designer uses it to describe designs at a higher level of abstractions - architectural, behavioral and lower levels - gate and switch levels and simulate them b4 commiting to fabrication 13 | - at a point of time, multiple modules could be running, we are simulating hardware 14 | 15 | ## Modules 16 | 17 | - components are designed inside module 18 | - structural and behavioral statements 19 | - module name is optional in syntax for primitives (and/or/not), but for user-defined modules, it is necessary 20 | - timescale is a directive used to define unit and precision of time measurement 21 | - like 15cm scale me 1cm = unit, 1mm = precision 22 | 23 | ![module](module.png) 24 | 25 | ## Level of abstractions 26 | 27 | - Gate level modeling 28 | - close to actual circuit 29 | - define things in terms of gates 30 | - Data Flow 31 | - acc to how data flows between registers and how a design processes data rather than instantiation of gates 32 | - expressions and operators 33 | - Behavioral 34 | - highest level of abstraction 35 | - algo type 36 | 37 | ## Simulation 38 | 39 | - testing the design 40 | - in gen, input becomes reg, and output becomes wire 41 | 42 | ## Exercises 43 | 44 | - [BCD to gray code](bcd2gray.v) 45 | - [magnitude comparator](magcomp.v) 46 | - [1-bit adder](fadder_1bit.v), [testbench](tb_fadder_1bit.v) 47 | - [4-bit adder](fadder_4bit.v), [testbench](tb_fadder_4bit.v) 48 | - [addsub](addSub_4bit.v), [testbench](tb_addSub_4bit.v) 49 | -------------------------------------------------------------------------------- /Lab1/addSub_4bit.v: -------------------------------------------------------------------------------- 1 | `ifndef ADDSUB_4BIT 2 | `define ADDSUB_4BIT 3 | `include "fadder_1bit.v" 4 | module addSub_4bit( 5 | output [3:0] sum, 6 | output cout, 7 | input [3:0] a, 8 | input [3:0] b, 9 | input cin, 10 | input sel 11 | ); 12 | 13 | wire [2:0] tmpCout; 14 | wire [3:0] xorbs; 15 | 16 | assign xorbs[0] = b[0] ^ sel; 17 | assign xorbs[1] = b[1] ^ sel; 18 | assign xorbs[2] = b[2] ^ sel; 19 | assign xorbs[3] = b[3] ^ sel; 20 | 21 | fadder_1bit f1( .cout(tmpCout[0]), .sum(sum[0]), .a(a[0]), .b(xorbs[0]), .cin(cin) ); 22 | fadder_1bit f2( .cout(tmpCout[1]), .sum(sum[1]), .a(a[1]), .b(xorbs[1]), .cin(tmpCout[0]) ); 23 | fadder_1bit f3( .cout(tmpCout[2]), .sum(sum[2]), .a(a[2]), .b(xorbs[2]), .cin(tmpCout[1]) ); 24 | fadder_1bit f4( .cout(cout), .sum(sum[3]), .a(a[3]), .b(xorbs[3]), .cin(tmpCout[2]) ); 25 | 26 | endmodule 27 | `endif -------------------------------------------------------------------------------- /Lab1/bcd2gray.v: -------------------------------------------------------------------------------- 1 | // BCD to gray conversion 2 | 3 | module bcd2gray_gate(a, b); 4 | // gate level 5 | input [3:0]a; 6 | output [3:0]b; 7 | // Assignment statement 8 | xor x0(b[3], 0, a[3]); 9 | xor x1(b[2], a[3], a[2]); 10 | xor x2(b[1], a[2], a[1]); 11 | xor x3(b[0], a[1], a[0]); 12 | endmodule 13 | 14 | module bcd2gray_df(a, b); 15 | // dataflow model 16 | input [3:0]a; 17 | output [3:0]b; 18 | 19 | assign b[3] = a[3]; 20 | assign b[2] = a[3] ^ a[2]; 21 | assign b[1] = a[2] ^ a[1]; 22 | assign b[0] = a[1] ^ a[0]; 23 | 24 | endmodule 25 | 26 | module testbench; 27 | reg [3:0]a; 28 | wire [3:0]b; 29 | 30 | bcd2gray_df bcd2gray(a, b); 31 | initial 32 | begin 33 | $monitor(, $time, " a=%4b, b=%4b", a, b); 34 | #0 a=4'b0000; 35 | 36 | // repeat(n): repeats the statement below n times 37 | repeat(16) 38 | // updates 'a' 16 times at an interval of 10 time units 39 | #10 a=a+4'b0001; 40 | 41 | #180 $finish; 42 | end 43 | 44 | endmodule -------------------------------------------------------------------------------- /Lab1/fadder_1bit.v: -------------------------------------------------------------------------------- 1 | `ifndef FADDER_1BIT 2 | `define FADDER_1BIT 3 | module fadder_1bit( 4 | output sum, 5 | output cout, 6 | input a, 7 | input b, 8 | input cin); 9 | 10 | assign sum = a ^ b ^ cin; 11 | assign cout = a&b | (a|b)&cin; 12 | 13 | endmodule 14 | `endif -------------------------------------------------------------------------------- /Lab1/fadder_4bit.v: -------------------------------------------------------------------------------- 1 | `include "fadder_1bit.v" 2 | module fadder_4bit( 3 | output [3:0] sum, 4 | output cout, 5 | input [3:0] a, 6 | input [3:0] b, 7 | input cin 8 | ); 9 | 10 | wire [2:0] tmpCout; 11 | 12 | fadder_1bit f1( .cout(tmpCout[0]), .sum(sum[0]), .a(a[0]), .b(b[0]), .cin(cin) ); 13 | fadder_1bit f2( .cout(tmpCout[1]), .sum(sum[1]), .a(a[1]), .b(b[1]), .cin(tmpCout[0]) ); 14 | fadder_1bit f3( .cout(tmpCout[2]), .sum(sum[2]), .a(a[2]), .b(b[2]), .cin(tmpCout[1]) ); 15 | fadder_1bit f4( .cout(cout), .sum(sum[3]), .a(a[3]), .b(b[3]), .cin(tmpCout[2]) ); 16 | 17 | endmodule -------------------------------------------------------------------------------- /Lab1/filename.vcd: -------------------------------------------------------------------------------- 1 | $date 2 | Thu Aug 27 14:28:10 2020 3 | $end 4 | $version 5 | Icarus Verilog 6 | $end 7 | $timescale 8 | 1s 9 | $end 10 | $scope module mux2tol_beh $end 11 | $var wire 1 ! a $end 12 | $var wire 1 " b $end 13 | $var wire 1 # s $end 14 | $var reg 1 $ f $end 15 | $upscope $end 16 | $scope module mux2tol_df $end 17 | $var wire 1 % a $end 18 | $var wire 1 & b $end 19 | $var wire 1 ' s $end 20 | $var wire 1 ( f $end 21 | $upscope $end 22 | $scope module testbench $end 23 | $var wire 1 ) f $end 24 | $var reg 1 * a $end 25 | $var reg 1 + b $end 26 | $var reg 1 , s $end 27 | $scope module mux_df $end 28 | $var wire 1 * a $end 29 | $var wire 1 + b $end 30 | $var wire 1 - c $end 31 | $var wire 1 . d $end 32 | $var wire 1 / e $end 33 | $var wire 1 ) f $end 34 | $var wire 1 , s $end 35 | $upscope $end 36 | $upscope $end 37 | $enddefinitions $end 38 | #0 39 | $dumpvars 40 | x/ 41 | 0. 42 | 0- 43 | x, 44 | 0+ 45 | 0* 46 | 0) 47 | z( 48 | z' 49 | z& 50 | z% 51 | z$ 52 | z# 53 | z" 54 | z! 55 | $end 56 | #2 57 | 0/ 58 | 1, 59 | #7 60 | 1/ 61 | 0, 62 | #17 63 | 1* 64 | #32 65 | 1) 66 | 0/ 67 | 1- 68 | 1, 69 | #52 70 | 0) 71 | 1/ 72 | 0- 73 | 0, 74 | #102 75 | -------------------------------------------------------------------------------- /Lab1/magcomp.v: -------------------------------------------------------------------------------- 1 | // Magnitude comparator 2 | 3 | module mag_beh(a, b, c); 4 | 5 | input [3:0] a, b; 6 | output [2:0]c; 7 | reg c; 8 | always@ (a or b) 9 | begin 10 | if(a==b) c=3'b100; 11 | else if(a>b) c=3'b010; 12 | else if(a"; 79 | "test.v"; 80 | -------------------------------------------------------------------------------- /Lab1/test.v: -------------------------------------------------------------------------------- 1 | 2 | 3 | // timescale 1ns/1ps 4 | module mux_2_to_1(a,b,s,f); 5 | input a,b,s; 6 | output f; 7 | reg f; 8 | always@(s or a or b) 9 | if(s==1) f=a; 10 | else f=b; 11 | endmodule 12 | module testbench; 13 | reg a,b,s; 14 | wire f; 15 | mux_2_to_1 mux(a,b,s,f); 16 | initial 17 | begin 18 | $monitor(,$time," a=%b, b=%b, s=%b f=%b",a,b,s,f); 19 | #0 a=1'b0;b=1'b0; 20 | #1 a=1'b0;b=1'b1; 21 | #2 a=1'b1;b=1'b0; 22 | #3 a=1'b1;b=1'b1; 23 | #10 s=1'b1; 24 | #15 s=1'b0; 25 | #100 $finish; 26 | end 27 | endmodule 28 | -------------------------------------------------------------------------------- /Lab1/testbench_mux2to1_gate.v: -------------------------------------------------------------------------------- 1 | 2 | `include "mux2to1_gate.v" 3 | 4 | module testbench_mux2to1_gate; 5 | 6 | reg a; 7 | reg b; 8 | reg s; 9 | 10 | wire f; 11 | 12 | mux2to1_gate mux_gate (a,b,s,f); 13 | initial 14 | begin 15 | $monitor($time," a = %b, b = %b, s = %b, f = %b",a,b,s,f); 16 | #0 a=1'b0; b=1'b1; 17 | #2 s=1'b1; 18 | #5 s=1'b0; 19 | #10 a=1'b1;b=1'b0; 20 | #15 s=1'b1; 21 | #20 s=1'b0; 22 | #100 $finish; 23 | end 24 | 25 | initial 26 | begin 27 | $dumpfile("filename.vcd"); 28 | $dumpvars; 29 | end 30 | endmodule 31 | -------------------------------------------------------------------------------- /Lab2/ADDER_8bit.v: -------------------------------------------------------------------------------- 1 | `include "FADDER.v" 2 | module ADDER_8bit(cfinal,sum,num1,num2,cin); 3 | 4 | input [7:0] num1,num2; 5 | output [7:0] sum; 6 | wire [7:0] cout; 7 | input cin; 8 | output cfinal; 9 | 10 | FADDER add0(sum[0],cout[0],num1[0],num2[0],cin); 11 | FADDER add1(sum[1],cout[1],num1[1],num2[1],cout[0]); 12 | FADDER add2(sum[2],cout[2],num1[2],num2[2],cout[1]); 13 | FADDER add3(sum[3],cout[3],num1[3],num2[3],cout[2]); 14 | FADDER add4(sum[4],cout[4],num1[4],num2[4],cout[3]); 15 | FADDER add5(sum[5],cout[5],num1[5],num2[5],cout[4]); 16 | FADDER add6(sum[6],cout[6],num1[6],num2[6],cout[5]); 17 | FADDER add7(sum[7],cout[7],num1[7],num2[7],cout[6]); 18 | 19 | assign cfinal = cout[7]; 20 | endmodule -------------------------------------------------------------------------------- /Lab2/DECODER.v: -------------------------------------------------------------------------------- 1 | module DECODER(d0,d1,d2,d3,d4,d5,d6,d7,x,y,z); 2 | input x,y,z; 3 | output d0,d1,d2,d3,d4,d5,d6,d7; 4 | wire x0,y0,z0; 5 | not n1(x0,x); 6 | not n2(y0,y); 7 | not n3(z0,z); 8 | and a0(d0,x0,y0,z0); 9 | and a1(d1,x0,y0,z); 10 | and a2(d2,x0,y,z0); 11 | and a3(d3,x0,y,z); 12 | and a4(d4,x,y0,z0); 13 | and a5(d5,x,y0,z); 14 | and a6(d6,x,y,z0); 15 | and a7(d7,x,y,z); 16 | endmodule -------------------------------------------------------------------------------- /Lab2/FADDER.v: -------------------------------------------------------------------------------- 1 | `include "DECODER.v" 2 | module FADDER(s,c,x,y,z); 3 | input x,y,z; 4 | wire d0,d1,d2,d3,d4,d5,d6,d7; 5 | output s,c; 6 | DECODER dec(d0,d1,d2,d3,d4,d5,d6,d7,x,y,z); 7 | assign s = d1 | d2 | d4 | d7, 8 | c = d3 | d5 | d6 | d7; 9 | endmodule -------------------------------------------------------------------------------- /Lab2/Lab_Sheet_2_Final.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/SinghCoder/Icarus_Verilog/c326ccb1b1a354daaf6e61368712536428445de5/Lab2/Lab_Sheet_2_Final.pdf -------------------------------------------------------------------------------- /Lab2/README.md: -------------------------------------------------------------------------------- 1 | # Lab Sheet 2 2 | 3 | ## LearningObjectives 4 | 5 | - Combinational digital circuit modeling 6 | - Constructing a larger module using a smaller module 7 | -------------------------------------------------------------------------------- /Lab2/adder_32bit.v: -------------------------------------------------------------------------------- 1 | `include "ADDER_8bit.v" 2 | 3 | module adder_32bit(cfinal,sum,num1,num2,cin); 4 | input [31:0] num1,num2; 5 | input cin; 6 | output [31:0] sum; 7 | output cfinal; 8 | wire cout[3:0]; 9 | 10 | ADDER_8bit add1(cout[0],sum[7:0],num1[7:0],num2[7:0],cin); 11 | ADDER_8bit add2(cout[1],sum[15:8],num1[15:8],num2[15:8],cout[0]); 12 | ADDER_8bit add3(cout[2],sum[23:16],num1[23:16],num2[23:16],cout[1]); 13 | ADDER_8bit add4(cout[3],sum[31:24],num1[31:24],num2[31:24],cout[2]); 14 | 15 | assign cfinal = cout[2]; 16 | 17 | endmodule -------------------------------------------------------------------------------- /Lab2/comparator_4bit.v: -------------------------------------------------------------------------------- 1 | `ifndef COMPARATOR_4BIT 2 | `define COMPARATOR_4BIT 3 | 4 | module sign( 5 | output sign, 6 | input [3:0] num 7 | ); 8 | reg sign; 9 | 10 | always @* begin 11 | if( num[3] == 1) 12 | sign = 1; 13 | else 14 | sign = 0; 15 | end 16 | 17 | endmodule 18 | 19 | module comparator_4bit( 20 | output agtb, 21 | output altb, 22 | output aeqb, 23 | input [3:0] a, 24 | input [3:0] b 25 | ); 26 | 27 | wire signa, signb; 28 | reg agtb, altb, aeqb; 29 | 30 | sign sa(signa, a); 31 | sign sb(signb, b); 32 | 33 | always @(a or b or signa or signb) begin 34 | 35 | if( (signa == 1) && (signb == 0) ) begin 36 | 37 | agtb = 0; 38 | altb = 1; 39 | aeqb = 0; 40 | 41 | end 42 | 43 | else if( (signa == 0) && (signb == 1) ) begin 44 | 45 | // $display("hi"); 46 | agtb = 1; 47 | altb = 0; 48 | aeqb = 0; 49 | 50 | end 51 | 52 | else begin 53 | 54 | if( a > b ) begin 55 | 56 | agtb = 1; 57 | altb = 0; 58 | aeqb = 0; 59 | 60 | end 61 | 62 | else if( a < b) begin 63 | 64 | agtb = 0; 65 | altb = 1; 66 | aeqb = 0; 67 | 68 | end 69 | 70 | else begin 71 | 72 | agtb = 0; 73 | altb = 0; 74 | aeqb = 1; 75 | 76 | end 77 | 78 | end 79 | end 80 | 81 | endmodule 82 | `endif -------------------------------------------------------------------------------- /Lab2/decoder_3to1.v: -------------------------------------------------------------------------------- 1 | `ifndef DECODER_3TO1 2 | `define DECODE_3TO1 3 | module decoder_3to1( 4 | output [7:0] outp, 5 | input a, 6 | input b, 7 | input c 8 | ); 9 | 10 | wire abar,bbar,cbar; 11 | 12 | not(abar,a); 13 | not(bbar,b); 14 | not(cbar,c); 15 | 16 | and(outp[0], abar,bbar,cbar); 17 | and(outp[1], abar,bbar,c); 18 | and(outp[2], abar,b,cbar); 19 | and(outp[3], abar,b,c); 20 | 21 | and(outp[4], a,bbar,cbar); 22 | and(outp[5], a,bbar,c); 23 | and(outp[6], a,b,cbar); 24 | and(outp[7], a,b,c); 25 | 26 | endmodule 27 | `endif -------------------------------------------------------------------------------- /Lab2/fadder_bhvrl.v: -------------------------------------------------------------------------------- 1 | `ifndef FADDER_BHVRL 2 | `define FADDER_BHVRL 3 | module fadder_bhvrl( 4 | output [3:0] sum, 5 | output cout, 6 | output ovrflow, 7 | input m, 8 | input [3:0] a, 9 | input [3:0] b 10 | ); 11 | 12 | always @( a or b or m) begin 13 | 14 | if(m == 0) begin 15 | 16 | 17 | 18 | end 19 | else begin 20 | end 21 | 22 | end 23 | 24 | endmodule -------------------------------------------------------------------------------- /Lab2/fadder_dec.v: -------------------------------------------------------------------------------- 1 | `include "decoder_3to1.v" 2 | module fadder_dec( 3 | output sum, 4 | output cout, 5 | input a, 6 | input b, 7 | input cin 8 | ); 9 | 10 | wire [7:0] dec_out; 11 | 12 | decoder_3to1 dec(.outp(dec_out), .a(a), .b(b), .c(cin) ); 13 | 14 | assign sum = dec_out[1] | dec_out[2] | dec_out[4] | dec_out[7] ; 15 | assign cout = dec_out[3] | dec_out[5] | dec_out[6] | dec_out[7] ; 16 | 17 | endmodule -------------------------------------------------------------------------------- /Lab2/mux16to1_glvl.v: -------------------------------------------------------------------------------- 1 | `ifndef MUX16TO1 2 | `define MUX16TO1 3 | `include "mux4to1_glvl.v" 4 | 5 | module mux16to1_glvl( 6 | output outp, 7 | input [15:0] inp, 8 | input [3:0] sel 9 | ); 10 | 11 | genvar i; 12 | 13 | wire [3:0] muxOuts; 14 | 15 | generate for(i = 0; i < 4; i = i+1) begin : mux4to1 16 | 17 | mux4to1_glvl mux(.outp(muxOuts[i]), .inp(inp[(4*(i+1)-1)-:4]), .sel(sel[1-:2])); 18 | 19 | end 20 | endgenerate 21 | 22 | mux4to1_glvl endMux(.outp(outp), .inp(muxOuts), .sel(sel[3-:2])); 23 | 24 | endmodule 25 | 26 | `endif -------------------------------------------------------------------------------- /Lab2/mux4to1_gate.v: -------------------------------------------------------------------------------- 1 | module mux4to1_gate(out,in,sel); 2 | input [0:3] in; 3 | input [0:1] sel; 4 | output out; 5 | wire a,b,c,d,n1,n2,a1,a2,a3,a4; 6 | not n(n1,sel[1]); 7 | not nn(n2,sel[0]); 8 | and (a1,in[0],n1,n2); 9 | and (a2,in[1],n2,sel[1]); 10 | and (a3,in[2],sel[0],n1); 11 | and (a4,in[3],sel[0],sel[1]); 12 | or or1(out,a1,a2,a3,a4); 13 | endmodule -------------------------------------------------------------------------------- /Lab2/mux4to1_glvl.v: -------------------------------------------------------------------------------- 1 | `ifndef MUX_4TO1 2 | `define MUX_4TO1 3 | 4 | module mux4to1_glvl( 5 | output outp, 6 | input [3:0] inp, 7 | input [1:0] sel 8 | ); 9 | 10 | wire [1:0] selBar; 11 | not(selBar[0], sel[0]); 12 | not(selBar[1], sel[1]); 13 | 14 | wire case1, case2, case3, case4; 15 | and (case1, selBar[0], selBar[1], inp[0]); 16 | and (case2, sel[0], selBar[1], inp[1]); 17 | and (case3, selBar[0], sel[1], inp[2]); 18 | and (case4, sel[0], sel[1], inp[3]); 19 | 20 | or(outp, case1, case2, case3, case4); 21 | 22 | endmodule 23 | 24 | `endif -------------------------------------------------------------------------------- /Lab2/tb_comparator_4bit.v: -------------------------------------------------------------------------------- 1 | `include "comparator_4bit.v" 2 | module tb_comparator_4bit(); 3 | 4 | reg [3:0] a; 5 | reg [3:0] b; 6 | wire agtb, altb, aeqb; 7 | 8 | comparator_4bit comp(.agtb(agtb), .altb(altb), .aeqb(aeqb), .a(a), .b(b)); 9 | 10 | initial begin 11 | $dumpfile("tb_comparator_4bit.vcd"); 12 | $dumpvars(0,tb_comparator_4bit); 13 | end 14 | 15 | initial begin 16 | a=4'b0000; b=4'b0000; 17 | #5 a=4'b1000; b=4'b1011; 18 | #5 a=4'b0010; b=4'b0111; 19 | #5 a=4'b0101; b=4'b1111; 20 | #5 $finish(); 21 | end 22 | 23 | initial 24 | $monitor("a = %b, b = %b,signa = %b, signb = %b, agtb = %b, altb = %b, aeqb = %b",a, b,comp.signa, comp.signb, agtb, altb, aeqb); 25 | endmodule -------------------------------------------------------------------------------- /Lab2/tb_fadder_dec.v: -------------------------------------------------------------------------------- 1 | `include "fadder_dec.v" 2 | module tb_fadder_dec(); 3 | 4 | reg a, b, cin; 5 | wire sum, cout; 6 | 7 | fadder_dec addr(.cout(cout), .sum(sum), .cin(cin), .a(a), .b(b)); 8 | 9 | initial begin 10 | $dumpfile("tb_fadder_dec.vcd"); 11 | $dumpvars; 12 | end 13 | 14 | initial 15 | $monitor(" a = %b, b = %b, cin = %b, sum = %b, cout = %b",a,b,cin,sum,cout); 16 | 17 | initial begin 18 | 19 | a = 0; b = 0; cin = 0; 20 | #5 a = 0; b = 0; cin = 1; 21 | #5 a = 0; b = 1; cin = 0; 22 | #5 a = 0; b = 1; cin = 1; 23 | #5 a = 1; b = 0; cin = 0; 24 | #5 a = 1; b = 0; cin = 1; 25 | #5 a = 1; b = 1; cin = 0; 26 | #5 a = 1; b = 1; cin = 1; 27 | 28 | end 29 | 30 | endmodule -------------------------------------------------------------------------------- /Lab2/tb_mux16to1_glvl.v: -------------------------------------------------------------------------------- 1 | `include "mux16to1_glvl.v" 2 | module tb_mux16to1_glvl(); 3 | 4 | reg [15:0] inp; 5 | reg [3:0] sel; 6 | wire outp; 7 | 8 | mux16to1_glvl mux(.outp(outp), .sel(sel), .inp(inp)); 9 | 10 | initial begin 11 | $dumpfile("tb_mux16to1_glvl.vcd"); 12 | $dumpvars; 13 | end 14 | 15 | initial begin 16 | 17 | $monitor("inp = %b, sel = %b, outp = %b", inp, sel, outp); 18 | 19 | end 20 | 21 | 22 | initial begin 23 | 24 | inp = 16'b0000_0101_1111_1010; sel = 4'b0000; 25 | #5 sel = 4'b0001; 26 | #5 sel = 4'b0010; 27 | #5 sel = 4'b0011; 28 | #5 sel = 4'b0100; 29 | #5 sel = 4'b0101; 30 | #5 sel = 4'b0110; 31 | #5 sel = 4'b0111; 32 | 33 | #5 sel = 4'b1000; 34 | #5 sel = 4'b1001; 35 | #5 sel = 4'b1010; 36 | #5 sel = 4'b1011; 37 | 38 | #5 sel = 4'b1100; 39 | #5 sel = 4'b1101; 40 | #5 sel = 4'b1110; 41 | #5 sel = 4'b1111; 42 | #5 $finish; 43 | 44 | end 45 | 46 | endmodule -------------------------------------------------------------------------------- /Lab2/tb_mux4to1_glvl: -------------------------------------------------------------------------------- 1 | #! /usr/bin/vvp 2 | :ivl_version "10.3 (stable)"; 3 | :ivl_delay_selection "TYPICAL"; 4 | :vpi_time_precision + 0; 5 | :vpi_module "system"; 6 | :vpi_module "vhdl_sys"; 7 | :vpi_module "v2005_math"; 8 | :vpi_module "va_math"; 9 | S_0x55bce913b2b0 .scope module, "tb_mux4to1_glvl" "tb_mux4to1_glvl" 2 2; 10 | .timescale 0 0; 11 | v0x55bce9151120_0 .var "inp", 3 0; 12 | v0x55bce91511e0_0 .net "outp", 0 0, L_0x55bce9152420; 1 drivers 13 | v0x55bce91512b0_0 .var "sel", 1 0; 14 | S_0x55bce913b430 .scope module, "mux" "mux4to1_glvl" 2 8, 3 4 0, S_0x55bce913b2b0; 15 | .timescale 0 0; 16 | .port_info 0 /OUTPUT 1 "outp" 17 | .port_info 1 /INPUT 4 "inp" 18 | .port_info 2 /INPUT 2 "sel" 19 | L_0x55bce91513b0 .functor NOT 1, L_0x55bce9151480, C4<0>, C4<0>, C4<0>; 20 | L_0x55bce9151660 .functor NOT 1, L_0x55bce9151720, C4<0>, C4<0>, C4<0>; 21 | L_0x55bce9151810 .functor AND 1, L_0x55bce9151910, L_0x55bce9151a80, L_0x55bce9151b70, C4<1>; 22 | L_0x55bce9151cf0 .functor AND 1, L_0x55bce9151d90, L_0x55bce9151e80, L_0x55bce9151f70, C4<1>; 23 | L_0x55bce9152010 .functor AND 1, L_0x55bce91520b0, L_0x55bce9152200, L_0x55bce91522a0, C4<1>; 24 | L_0x55bce9152490 .functor AND 1, L_0x55bce91525a0, L_0x55bce9152640, L_0x55bce91527b0, C4<1>; 25 | L_0x55bce9152420 .functor OR 1, L_0x55bce9151810, L_0x55bce9151cf0, L_0x55bce9152010, L_0x55bce9152490; 26 | v0x55bce91030e0_0 .net *"_s1", 0 0, L_0x55bce91513b0; 1 drivers 27 | v0x55bce914fcf0_0 .net *"_s10", 0 0, L_0x55bce9151720; 1 drivers 28 | v0x55bce914fdd0_0 .net *"_s13", 0 0, L_0x55bce9151910; 1 drivers 29 | v0x55bce914fe90_0 .net *"_s15", 0 0, L_0x55bce9151a80; 1 drivers 30 | v0x55bce914ff70_0 .net *"_s17", 0 0, L_0x55bce9151b70; 1 drivers 31 | v0x55bce91500a0_0 .net *"_s20", 0 0, L_0x55bce9151d90; 1 drivers 32 | v0x55bce9150180_0 .net *"_s22", 0 0, L_0x55bce9151e80; 1 drivers 33 | v0x55bce9150260_0 .net *"_s24", 0 0, L_0x55bce9151f70; 1 drivers 34 | v0x55bce9150340_0 .net *"_s27", 0 0, L_0x55bce91520b0; 1 drivers 35 | v0x55bce9150420_0 .net *"_s29", 0 0, L_0x55bce9152200; 1 drivers 36 | v0x55bce9150500_0 .net *"_s31", 0 0, L_0x55bce91522a0; 1 drivers 37 | v0x55bce91505e0_0 .net *"_s34", 0 0, L_0x55bce91525a0; 1 drivers 38 | v0x55bce91506c0_0 .net *"_s36", 0 0, L_0x55bce9152640; 1 drivers 39 | v0x55bce91507a0_0 .net *"_s38", 0 0, L_0x55bce91527b0; 1 drivers 40 | v0x55bce9150880_0 .net *"_s4", 0 0, L_0x55bce9151480; 1 drivers 41 | v0x55bce9150960_0 .net *"_s6", 0 0, L_0x55bce9151660; 1 drivers 42 | v0x55bce9150a40_0 .net "case1", 0 0, L_0x55bce9151810; 1 drivers 43 | v0x55bce9150b00_0 .net "case2", 0 0, L_0x55bce9151cf0; 1 drivers 44 | v0x55bce9150bc0_0 .net "case3", 0 0, L_0x55bce9152010; 1 drivers 45 | v0x55bce9150c80_0 .net "case4", 0 0, L_0x55bce9152490; 1 drivers 46 | v0x55bce9150d40_0 .net "inp", 3 0, v0x55bce9151120_0; 1 drivers 47 | v0x55bce9150e20_0 .net "outp", 0 0, L_0x55bce9152420; alias, 1 drivers 48 | v0x55bce9150ee0_0 .net "sel", 1 0, v0x55bce91512b0_0; 1 drivers 49 | v0x55bce9150fc0_0 .net "selBar", 1 0, L_0x55bce9151570; 1 drivers 50 | L_0x55bce9151480 .part v0x55bce91512b0_0, 0, 1; 51 | L_0x55bce9151570 .concat8 [ 1 1 0 0], L_0x55bce91513b0, L_0x55bce9151660; 52 | L_0x55bce9151720 .part v0x55bce91512b0_0, 1, 1; 53 | L_0x55bce9151910 .part L_0x55bce9151570, 0, 1; 54 | L_0x55bce9151a80 .part L_0x55bce9151570, 1, 1; 55 | L_0x55bce9151b70 .part v0x55bce9151120_0, 0, 1; 56 | L_0x55bce9151d90 .part v0x55bce91512b0_0, 0, 1; 57 | L_0x55bce9151e80 .part L_0x55bce9151570, 1, 1; 58 | L_0x55bce9151f70 .part v0x55bce9151120_0, 1, 1; 59 | L_0x55bce91520b0 .part L_0x55bce9151570, 0, 1; 60 | L_0x55bce9152200 .part v0x55bce91512b0_0, 1, 1; 61 | L_0x55bce91522a0 .part v0x55bce9151120_0, 2, 1; 62 | L_0x55bce91525a0 .part v0x55bce91512b0_0, 0, 1; 63 | L_0x55bce9152640 .part v0x55bce91512b0_0, 1, 1; 64 | L_0x55bce91527b0 .part v0x55bce9151120_0, 3, 1; 65 | .scope S_0x55bce913b2b0; 66 | T_0 ; 67 | %vpi_call 2 11 "$dumpfile", "tb_mux4to1_glvl.vcd" {0 0 0}; 68 | %vpi_call 2 12 "$dumpvars" {0 0 0}; 69 | %end; 70 | .thread T_0; 71 | .scope S_0x55bce913b2b0; 72 | T_1 ; 73 | %pushi/vec4 5, 0, 4; 74 | %store/vec4 v0x55bce9151120_0, 0, 4; 75 | %pushi/vec4 0, 0, 2; 76 | %store/vec4 v0x55bce91512b0_0, 0, 2; 77 | %delay 5, 0; 78 | %pushi/vec4 1, 0, 2; 79 | %store/vec4 v0x55bce91512b0_0, 0, 2; 80 | %delay 5, 0; 81 | %pushi/vec4 2, 0, 2; 82 | %store/vec4 v0x55bce91512b0_0, 0, 2; 83 | %delay 5, 0; 84 | %pushi/vec4 3, 0, 2; 85 | %store/vec4 v0x55bce91512b0_0, 0, 2; 86 | %end; 87 | .thread T_1; 88 | # The file index is used to find the file name in the following table. 89 | :file_names 4; 90 | "N/A"; 91 | ""; 92 | "tb_mux4to1_glvl.v"; 93 | "./mux4to1_glvl.v"; 94 | -------------------------------------------------------------------------------- /Lab2/tb_mux4to1_glvl.v: -------------------------------------------------------------------------------- 1 | `include "mux4to1_glvl.v" 2 | module tb_mux4to1_glvl(); 3 | 4 | wire outp; 5 | reg [3:0] inp; 6 | reg [1:0] sel; 7 | 8 | mux4to1_glvl mux(.outp(outp), .inp(inp), .sel(sel)); 9 | 10 | initial begin 11 | $dumpfile("tb_mux4to1_glvl.vcd"); 12 | $dumpvars; 13 | end 14 | 15 | initial begin 16 | inp = 4'b0101; sel = 2'b00; 17 | #5 sel = 2'b01; 18 | #5 sel = 2'b10; 19 | #5 sel = 2'b11; 20 | end 21 | 22 | endmodule -------------------------------------------------------------------------------- /Lab2/test: -------------------------------------------------------------------------------- 1 | #! /usr/bin/vvp 2 | :ivl_version "10.3 (stable)"; 3 | :ivl_delay_selection "TYPICAL"; 4 | :vpi_time_precision + 0; 5 | :vpi_module "system"; 6 | :vpi_module "vhdl_sys"; 7 | :vpi_module "v2005_math"; 8 | :vpi_module "va_math"; 9 | S_0x55b37d606190 .scope module, "tb_test" "tb_test" 2 23; 10 | .timescale 0 0; 11 | v0x55b37d618350_0 .var "enable", 0 0; 12 | v0x55b37d6183f0_0 .var "x", 1 0; 13 | v0x55b37d6184c0_0 .net "y", 3 0, v0x55b37d6181a0_0; 1 drivers 14 | S_0x55b37d606310 .scope module, "t1" "binary_encoder" 2 27, 2 1 0, S_0x55b37d606190; 15 | .timescale 0 0; 16 | .port_info 0 /INPUT 2 "x" 17 | .port_info 1 /INPUT 1 "enable" 18 | .port_info 2 /OUTPUT 4 "y" 19 | v0x55b37d5cf0c0_0 .net *"_s3", 0 0, L_0x55b37d6185c0; 1 drivers 20 | v0x55b37d617f40_0 .net *"_s6", 0 0, L_0x55b37d6186e0; 1 drivers 21 | v0x55b37d618020_0 .net "enable", 0 0, v0x55b37d618350_0; 1 drivers 22 | v0x55b37d6180c0_0 .net "x", 1 0, v0x55b37d6183f0_0; 1 drivers 23 | v0x55b37d6181a0_0 .var "y", 3 0; 24 | E_0x55b37d606ba0 .event edge, L_0x55b37d6186e0, L_0x55b37d6185c0, v0x55b37d618020_0; 25 | L_0x55b37d6185c0 .part v0x55b37d6183f0_0, 1, 1; 26 | L_0x55b37d6186e0 .part v0x55b37d6183f0_0, 0, 1; 27 | .scope S_0x55b37d606310; 28 | T_0 ; 29 | %wait E_0x55b37d606ba0; 30 | %load/vec4 v0x55b37d618020_0; 31 | %cmpi/e 0, 0, 1; 32 | %jmp/0xz T_0.0, 4; 33 | %pushi/vec4 0, 0, 4; 34 | %store/vec4 v0x55b37d6181a0_0, 0, 4; 35 | %jmp T_0.1; 36 | T_0.0 ; 37 | %load/vec4 v0x55b37d6180c0_0; 38 | %pad/u 32; 39 | %cmpi/e 0, 0, 32; 40 | %jmp/0xz T_0.2, 4; 41 | %pushi/vec4 1, 0, 4; 42 | %store/vec4 v0x55b37d6181a0_0, 0, 4; 43 | %jmp T_0.3; 44 | T_0.2 ; 45 | %load/vec4 v0x55b37d6180c0_0; 46 | %pad/u 32; 47 | %cmpi/e 1, 0, 32; 48 | %jmp/0xz T_0.4, 4; 49 | %pushi/vec4 2, 0, 4; 50 | %store/vec4 v0x55b37d6181a0_0, 0, 4; 51 | %jmp T_0.5; 52 | T_0.4 ; 53 | %load/vec4 v0x55b37d6180c0_0; 54 | %cmpi/e 2, 0, 2; 55 | %jmp/0xz T_0.6, 4; 56 | %pushi/vec4 4, 0, 4; 57 | %store/vec4 v0x55b37d6181a0_0, 0, 4; 58 | %jmp T_0.7; 59 | T_0.6 ; 60 | %load/vec4 v0x55b37d6180c0_0; 61 | %cmpi/e 3, 0, 2; 62 | %jmp/0xz T_0.8, 4; 63 | %pushi/vec4 8, 0, 4; 64 | %store/vec4 v0x55b37d6181a0_0, 0, 4; 65 | T_0.8 ; 66 | T_0.7 ; 67 | T_0.5 ; 68 | T_0.3 ; 69 | T_0.1 ; 70 | %jmp T_0; 71 | .thread T_0, $push; 72 | .scope S_0x55b37d606190; 73 | T_1 ; 74 | %delay 0, 0; 75 | %pushi/vec4 0, 0, 1; 76 | %store/vec4 v0x55b37d618350_0, 0, 1; 77 | %delay 5, 0; 78 | %pushi/vec4 1, 0, 1; 79 | %store/vec4 v0x55b37d618350_0, 0, 1; 80 | %pushi/vec4 0, 0, 2; 81 | %store/vec4 v0x55b37d6183f0_0, 0, 2; 82 | %delay 10, 0; 83 | %pushi/vec4 1, 0, 2; 84 | %store/vec4 v0x55b37d6183f0_0, 0, 2; 85 | %delay 15, 0; 86 | %pushi/vec4 2, 0, 2; 87 | %store/vec4 v0x55b37d6183f0_0, 0, 2; 88 | %delay 20, 0; 89 | %pushi/vec4 3, 0, 2; 90 | %store/vec4 v0x55b37d6183f0_0, 0, 2; 91 | %delay 25, 0; 92 | %vpi_call 2 35 "$finish" {0 0 0}; 93 | %end; 94 | .thread T_1; 95 | .scope S_0x55b37d606190; 96 | T_2 ; 97 | %vpi_call 2 39 "$monitor", "enable = %b, x = %b, y = %b", v0x55b37d618350_0, v0x55b37d6183f0_0, v0x55b37d6184c0_0 {0 0 0}; 98 | %end; 99 | .thread T_2; 100 | # The file index is used to find the file name in the following table. 101 | :file_names 3; 102 | "N/A"; 103 | ""; 104 | "test.v"; 105 | -------------------------------------------------------------------------------- /Lab2/test.v: -------------------------------------------------------------------------------- 1 | module binary_encoder 2 | ( 3 | input wire [1:0] x, 4 | input wire enable, 5 | output reg [3:0] y 6 | ); 7 | 8 | always @(enable, x[1],x[0]) 9 | begin 10 | if (enable == 1'b0) 11 | y=4'b0000; 12 | else if (x == 0) 13 | y = 4'b0001; 14 | else if (x == 1) 15 | y = 4'b0010; 16 | else if (x == 2'b10) 17 | y = 4'b0100; 18 | else if (x == 2'b11) 19 | y = 4'b1000; 20 | end 21 | endmodule 22 | 23 | module tb_test(); 24 | reg [1:0] x; 25 | reg enable; 26 | wire [3:0] y; 27 | binary_encoder t1(x, enable, y); 28 | initial 29 | begin 30 | #0 enable = 1'b0; 31 | #5 enable = 1'b1; x = 2'b00; 32 | #10 x = 2'b01; 33 | #15 x = 2'b10; 34 | #20 x = 2'b11; 35 | #25 $finish; 36 | end 37 | 38 | initial 39 | $monitor("enable = %b, x = %b, y = %b", enable, x, y); 40 | endmodule -------------------------------------------------------------------------------- /Lab2/testbench_adder_32bit.v: -------------------------------------------------------------------------------- 1 | `include "adder_32bit.v" 2 | 3 | module testbench_adder_32bit; 4 | reg [31:0] num1,num2; 5 | wire [31:0] sum; 6 | wire cfinal; 7 | wire cin; 8 | 9 | assign cin = 0; 10 | 11 | adder_32bit add1(cfinal,sum,num1,num2,cin); 12 | initial 13 | $monitor(,$time,"sum=%b, cfinal = %b, num1=%b, num2=%b, cin = %b",sum,cfinal,num1,num2,cin); 14 | 15 | initial 16 | begin 17 | #0 num1=32'b00000001000000010000000100000001;num2=32'b11111111111111111111111111111111; 18 | #10 num1=32'b00000000000000000000000000000000;num2=32'b11111110111111101111111011111110; 19 | #20 num1=32'b00000000000000000000000000000000;num2=32'b11111101111111011111110111111101; 20 | #30 num1=32'b00000000000000000000000000000000;num2=32'b11111011111110111111101111111011; 21 | #40 num1=32'b00000000000000000000000000000000;num2=32'b11110111111101111111011111110111; 22 | end 23 | endmodule -------------------------------------------------------------------------------- /Lab2/testbench_adder_8bit.v: -------------------------------------------------------------------------------- 1 | `include "ADDER_8bit.v" 2 | module testbench_adder_8bit; 3 | reg [7:0] num1,num2; 4 | wire [7:0] sum; 5 | wire cfinal; 6 | wire cin; 7 | 8 | assign cin = 0; 9 | 10 | ADDER_8bit fl(cfinal,sum,num1,num2,cin); 11 | initial 12 | $monitor(,$time,"sum=%b, cfinal = %b, num1=%b, num2=%b, cin = %b",sum,cfinal,num1,num2,cin); 13 | 14 | initial 15 | begin 16 | #0 num1=8'b00000001;num2=8'b11111111; 17 | #10 num1=8'b00000000;num2=8'b11111110; 18 | #20 num1=8'b00000000;num2=8'b11111101; 19 | #30 num1=8'b00000000;num2=8'b11111011; 20 | #40 num1=8'b00000000;num2=8'b11110111; 21 | end 22 | endmodule -------------------------------------------------------------------------------- /Lab2/testbench_fadder.v: -------------------------------------------------------------------------------- 1 | `include "FADDER.v" 2 | module testbench_fadder; 3 | reg x,y,z; 4 | wire s,c; 5 | FADDER fl(s,c,x,y,z); 6 | initial 7 | $monitor(,$time,"x=%b,y=%b,z=%b,s=%b,c=%b",x,y,z,s,c); 8 | initial 9 | begin 10 | #0 x=1'b0;y=1'b0;z=1'b0; 11 | #4 x=1'b1;y=1'b0;z=1'b0; 12 | #4 x=1'b0;y=1'b1;z=1'b0; 13 | #4 x=1'b1;y=1'b1;z=1'b0; 14 | #4 x=1'b0;y=1'b0;z=1'b1; 15 | #4 x=1'b1;y=1'b0;z=1'b1; 16 | #4 x=1'b0;y=1'b1;z=1'b1; 17 | #4 x=1'b1;y=1'b1;z=1'b1; 18 | end 19 | endmodule -------------------------------------------------------------------------------- /Lab3/4bit_shift_test.PNG: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/SinghCoder/Icarus_Verilog/c326ccb1b1a354daaf6e61368712536428445de5/Lab3/4bit_shift_test.PNG -------------------------------------------------------------------------------- /Lab3/Lab_Sheet_3_Final.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/SinghCoder/Icarus_Verilog/c326ccb1b1a354daaf6e61368712536428445de5/Lab3/Lab_Sheet_3_Final.pdf -------------------------------------------------------------------------------- /Lab3/README.md: -------------------------------------------------------------------------------- 1 | # Lab Sheet 3 2 | 3 | ## LearningObjectives 4 | 5 | - Introduction to Sequential circuits 6 | - Blocking and Non-Blocking Assignments 7 | - Sequential and Parallel blocks 8 | - Finite State Machine Implementation (Mealy Machine) 9 | - 4-bit Shift Register Implementation 10 | 11 | ## Non blocking vs Blocking - Race Conditions 12 | 13 | ```verilog 14 | //Illustration 1: Two concurrent always blocks with blocking 15 | //statements 16 | always @(posedge clock) 17 | a = b; 18 | always @(posedge clock) 19 | b = a; 20 | //Illustration 2: Two concurrent always blocks with nonblocking 21 | //statements 22 | always @(posedge clock) 23 | a <= b; 24 | always @(posedge clock) 25 | b <= a; 26 | ``` 27 | 28 | - treat Non blocking as a sequence of 2 operations 29 | - firstly Read cycle happens 30 | - all the variables on the RHS are read and stored in temporary variables 31 | - At the positive edge of clock, the values of all right-hand-side variables are "read," and the right-hand-side expressions are evaluated and stored in temporary variables. 32 | - During the write operation, the values stored in the temporary variables are assigned to the left-hand-side variables 33 | - For above example, Separating the read and write operations ensures that the values of registers a and b are swapped correctly, regardless of the order in which the write operations are performed. 34 | 35 | ```verilog 36 | //Process nonblocking assignments by using temporary variables 37 | always @(posedge clock) begin 38 | //read operation 39 | //store values of right-hand-side expressions in temporary variable: 40 | temp_a = a ; temp_b = b; 41 | //Write operation 42 | //Assign values of temporary variables to left-hand-side variables 43 | a = temp-b; b = temp-a ; 44 | end 45 | ``` 46 | 47 | - use of nonblocking assignments in place of blocking assignments is highly recommended in places where concurrent data transfers take place after a common event 48 | - In such cases, blocking assignments can potentially cause race conditions because the final result depends on the order in which the assignments are evaluated. 49 | - Nonblocking assignments can be used effectively to model concurrent data transfers because the final result is not dependent on the order in which the assignments are evaluated. 50 | - Typical applications of nonblocking assignments include pipeline modeling and modeling of several mutually exclusive data transfers. 51 | - On the downside, nonblocking assignments can potentially cause a degradation in the simulator performance and increase in memory usage. 52 | 53 | ## Block Types 54 | 55 | - There are two types of blocks: *sequential* blocks and *parallel* blocks 56 | 57 | ### Sequential 58 | 59 | - The keywords **begin** and **end** are used to group statements into sequential blocks. 60 | - The statements in a sequential block are processed in the order they are specified. A statement is executed only after its preceding statement completes execution 61 | - If delay or event control is specified, it is relative to the simulation time when the previous statement in the block completed execution 62 | 63 | ### Parallel 64 | 65 | - specified by keywords **fork** and **join** 66 | - Statements in a parallel block are executed concurrently 67 | - Ordering of statements is controlled by the delay or event control assigned to each statemen 68 | - If delay or event control is specified, it is relative to the time the block was entered 69 | - All statements in a parallel block start at the time when the block was entered. Thus, the order in which the statements are written in the block is not important. 70 | - Parallel blocks provide a mechanism to execute statements in parallel. However, it is important to be careful with parallel blocks because of implicit race conditions that might arise if two statements that affect the same variable complete at the same time 71 | 72 | ```verilog 73 | //Parallel blocks with deliberate race condition 74 | reg x, y; reg [1:0] z, w; 75 | initial 76 | fork 77 | x = 1'bO; y = 1'b1; 78 | z = {x,y}; 79 | w = {y,x}; 80 | join 81 | ``` 82 | 83 | - All statements start at simulation time 0. 84 | - The order in which the statements will execute is not known. 85 | - Variables z and W will get values 1 and 2 if X = l'bO and y = l'bl execute first. 86 | - Variables z and W will get values 2'bxx and 2'bxx if X = l'bO and y = l'bl execute last. Thus, the result of z and W is nondeterministic and dependent on the simulator implementation -------------------------------------------------------------------------------- /Lab3/counter4bit.v: -------------------------------------------------------------------------------- 1 | `ifndef COUNTER_4BIT 2 | `define COUNTER_4BIT 3 | module jkFlipFlop( 4 | output q, 5 | input J, 6 | input K, 7 | input clk, 8 | input reset); 9 | 10 | reg q; 11 | always @(posedge clk) begin 12 | if(reset) 13 | q <= 1'b0; 14 | else begin 15 | case({J,K}) 16 | 2'b0_0: q <= q; 17 | 2'b0_1: q <= 0; 18 | 2'b1_0: q <= 1; 19 | 2'b1_1: q <= ~q; 20 | endcase 21 | end 22 | end 23 | endmodule 24 | 25 | module counter4bit( 26 | output [3:0] q, 27 | input clk, 28 | input reset); 29 | 30 | wire q0q1; 31 | assign q0q1 = q[0] & q[1]; 32 | 33 | wire q0q1q2; 34 | assign q0q1q2 = q0q1 & q[2]; 35 | 36 | jkFlipFlop f0(q[0], 1'b1, 1'b1, clk, reset); 37 | jkFlipFlop f1(q[1], q[0], q[0], clk, reset); 38 | jkFlipFlop f2(q[2], q0q1, q0q1, clk, reset); 39 | jkFlipFlop f3(q[3], q0q1q2, q0q1q2, clk, reset); 40 | 41 | endmodule 42 | `endif -------------------------------------------------------------------------------- /Lab3/counter_4bit.PNG: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/SinghCoder/Icarus_Verilog/c326ccb1b1a354daaf6e61368712536428445de5/Lab3/counter_4bit.PNG -------------------------------------------------------------------------------- /Lab3/dff_async_clear.v: -------------------------------------------------------------------------------- 1 | // module d flip flop with synchronus clear 2 | // clock is negative edge triggered and clear signal is active low 3 | `ifndef DFF_ASYNC_CLEAR 4 | `define DFF_ASYNC_CLEAR 5 | module dff_async_clear(d,clearb, clock, q); 6 | input d, clearb, clock; 7 | output q; 8 | reg q; 9 | 10 | always @(posedge clock or negedge clearb) 11 | begin 12 | if(clearb) 13 | q = d; 14 | else 15 | q = 1'b0; 16 | end 17 | endmodule 18 | `endif -------------------------------------------------------------------------------- /Lab3/dff_sync_clear.v: -------------------------------------------------------------------------------- 1 | `ifndef DFF_SYNC_CLEAR 2 | `define DFF_SYNC_CLEAR 3 | // module d flip flop with synchronus clear 4 | // clock is positive edge triggered 5 | module dff_sync_clear(d,clearb, clock, q); 6 | input d, clearb, clock; 7 | output q; 8 | reg q; 9 | 10 | always @(posedge clock) 11 | begin 12 | if(clearb) 13 | q = d; 14 | else 15 | q = 1'b0; 16 | end 17 | endmodule 18 | `endif -------------------------------------------------------------------------------- /Lab3/fullAdder1bit.v: -------------------------------------------------------------------------------- 1 | `ifndef FULLADDER_1BIT 2 | `define FULLADDER_1BIT 3 | module fullAdder1bit( 4 | input a, 5 | input b, 6 | input cin, 7 | output sum, 8 | output cout); 9 | 10 | // initial 11 | // $display("FA_IP = ") 12 | 13 | // initial 14 | // $monitor("fa i/p: ",cin,b,a," fa o/p: ",cout,sum); 15 | 16 | assign {cout,sum} = a+b+cin; 17 | 18 | 19 | endmodule 20 | `endif -------------------------------------------------------------------------------- /Lab3/mealy.v: -------------------------------------------------------------------------------- 1 | module mealy(inp,rst,clk,outp); 2 | input inp,rst,clk; 3 | output outp; 4 | reg outp; 5 | reg [1:0] state; 6 | 7 | always @(posedge clk , posedge rst) 8 | begin 9 | if(rst) 10 | begin 11 | state <= 2'b00; 12 | outp <= 0; 13 | end 14 | else 15 | begin 16 | case( state ) 17 | 2'b00: 18 | begin 19 | if(inp) 20 | begin 21 | state <= 2'b01; 22 | outp <= 0; 23 | end 24 | else 25 | begin 26 | state <= 2'b10; 27 | outp <= 0; 28 | end 29 | end 30 | 2'b01: 31 | begin 32 | if(inp) 33 | begin 34 | state <= 2'b00; 35 | outp <= 1; 36 | end 37 | else 38 | begin 39 | state <= 2'b10; 40 | outp <= 0; 41 | end 42 | end 43 | 2'b10: 44 | begin 45 | if(inp) 46 | begin 47 | state <= 2'b01; 48 | outp <= 0; 49 | end 50 | else 51 | begin 52 | state <= 2'b00; 53 | outp <= 1; 54 | end 55 | end 56 | default: 57 | begin 58 | state <= 2'b00; 59 | outp <= 0; 60 | end 61 | endcase 62 | end 63 | end 64 | endmodule -------------------------------------------------------------------------------- /Lab3/mealyOutput.PNG: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/SinghCoder/Icarus_Verilog/c326ccb1b1a354daaf6e61368712536428445de5/Lab3/mealyOutput.PNG -------------------------------------------------------------------------------- /Lab3/mealy_test.v: -------------------------------------------------------------------------------- 1 | `include "mealy.v" 2 | module mealy_test; 3 | reg clk,rst,inp; 4 | wire outp; 5 | reg[15:0] sequence; 6 | integer i; 7 | 8 | mealy duty(inp,rst,clk,outp); 9 | 10 | always @(posedge clk or posedge rst) 11 | begin 12 | $display(" State = ",duty.state," Input = ", inp, " Output = " , outp, " Clock = ", clk, " rst = ",rst ," time =",$time); 13 | end 14 | 15 | initial 16 | begin 17 | clk = 0; 18 | rst = 1; 19 | sequence = 16'b0101_0111_0111_0010; 20 | #5 rst <= 0; 21 | 22 | for( i=0; i<=15; i = i+1) 23 | begin 24 | inp = sequence[i]; 25 | #2 clk = 1; 26 | #2 clk = 0; 27 | end 28 | 29 | testing; 30 | end 31 | 32 | task testing; 33 | for( i = 0; i <= 15; i = i + 1) 34 | begin 35 | inp = $random % 2; 36 | #2 clk = 1; 37 | #2 clk = 0; 38 | end 39 | endtask 40 | endmodule 41 | 42 | 43 | -------------------------------------------------------------------------------- /Lab3/seqDetect.v: -------------------------------------------------------------------------------- 1 | `ifndef SEQ_DETECT 2 | `define SEQ_DETECT 3 | module seqDetect( 4 | input inSeq, 5 | input clk, 6 | input reset); 7 | 8 | parameter s0 = 3'b000, 9 | s1 = 3'b001, 10 | s2 = 3'b010, 11 | s3 = 3'b011, 12 | s4 = 3'b100; 13 | 14 | reg [2:0] state; 15 | 16 | always @(posedge clk or posedge reset) begin 17 | if( reset ) 18 | state <= s0; 19 | else begin 20 | // $display("current state = %b ",state); 21 | // $display("input:= ", inSeq); 22 | case (state) 23 | s0 : begin 24 | // $display("State0"); 25 | if (inSeq) 26 | state <= s1; 27 | else 28 | state <= s0; 29 | end 30 | s1 : begin 31 | // $display("State1"); 32 | if (inSeq) 33 | state <= s1; 34 | else 35 | state <= s2; 36 | end 37 | s2 : begin 38 | // $display("State2"); 39 | if (inSeq) 40 | state <= s3; 41 | else 42 | state <= s0; 43 | end 44 | s3 : begin 45 | // $display("State3"); 46 | if (inSeq) 47 | state <= s4; 48 | else 49 | state <= s2; 50 | end 51 | s4 : begin 52 | // $display("State4"); 53 | $display("Sequence detected"); 54 | if (inSeq) 55 | state <= s1; 56 | else 57 | state <= s2; 58 | end 59 | 60 | default: begin 61 | $display("Default state"); 62 | state <= s0; 63 | end 64 | endcase 65 | end 66 | end 67 | endmodule 68 | `endif -------------------------------------------------------------------------------- /Lab3/seqDetect_10110.PNG: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/SinghCoder/Icarus_Verilog/c326ccb1b1a354daaf6e61368712536428445de5/Lab3/seqDetect_10110.PNG -------------------------------------------------------------------------------- /Lab3/serialAdder_4bit.PNG: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/SinghCoder/Icarus_Verilog/c326ccb1b1a354daaf6e61368712536428445de5/Lab3/serialAdder_4bit.PNG -------------------------------------------------------------------------------- /Lab3/serialAdder_4bit.v: -------------------------------------------------------------------------------- 1 | `include "shift_reg_4bit_lab.v" //in, en, q, clk 2 | `include "fullAdder1bit.v" 3 | `include "dff_async_clear.v" //d, clear, clk, q 4 | 5 | module serialAdder_4bit( 6 | output [3:0] serOut1, 7 | output sm, 8 | input serInp, 9 | input shiftCtrl, 10 | input clear, 11 | input clk); 12 | 13 | wire cout, coutLatched, sm; 14 | wire [3:0] serOut1, serOut2; 15 | 16 | shift_reg_4bit_lab sreg1( sm, shiftCtrl, serOut1 , clk ); 17 | shift_reg_4bit_lab sreg2( serInp, shiftCtrl, serOut2 , clk ); 18 | 19 | fullAdder1bit fa( serOut1[0] , serOut2[0] , coutLatched, sm, cout ); 20 | 21 | dff_async_clear dff(cout, clear, shiftCtrl & clk, coutLatched); 22 | 23 | 24 | endmodule -------------------------------------------------------------------------------- /Lab3/shift_reg_4bit.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/SinghCoder/Icarus_Verilog/c326ccb1b1a354daaf6e61368712536428445de5/Lab3/shift_reg_4bit.png -------------------------------------------------------------------------------- /Lab3/shift_reg_4bit.v: -------------------------------------------------------------------------------- 1 | `include "dff_sync_clear.v" //dff_sync_clear(d,clearb, clock, q) 2 | module shift_reg_4bit(d, clk, rst, q); 3 | 4 | input d, clk, rst; 5 | output [3:0] q; 6 | wire rst; 7 | 8 | dff_sync_clear df3( d ,rst ,clk , q[3] ); 9 | dff_sync_clear df2( q[3], rst, clk, q[2] ); 10 | dff_sync_clear df1( q[2], rst, clk, q[1] ); 11 | dff_sync_clear df0( q[1], rst, clk, q[0] ); 12 | 13 | endmodule -------------------------------------------------------------------------------- /Lab3/shift_reg_4bit_lab.v: -------------------------------------------------------------------------------- 1 | `ifndef SHIFT_REG_4BIT_L 2 | `define SHIFT_REG_4BIT_L 3 | module shift_reg_4bit_lab( in, en, Q, clk ); 4 | 5 | parameter n = 4; 6 | input in, en, clk; 7 | output [n-1:0] Q; 8 | reg [n-1:0] Q; 9 | 10 | initial 11 | Q = 4'b0; 12 | 13 | always @(posedge clk) begin 14 | if(en) 15 | begin 16 | Q = {in, Q[n-1:1]}; 17 | end 18 | end 19 | endmodule 20 | `endif -------------------------------------------------------------------------------- /Lab3/tb_32bitReg.PNG: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/SinghCoder/Icarus_Verilog/c326ccb1b1a354daaf6e61368712536428445de5/Lab3/tb_32bitReg.PNG -------------------------------------------------------------------------------- /Lab3/tb_counter4bit.v: -------------------------------------------------------------------------------- 1 | `include "counter4bit.v" //q,clk 2 | 3 | module tb_counter4bit(); 4 | 5 | wire [3:0] q; 6 | reg clk, reset; 7 | 8 | initial 9 | clk = 0; 10 | 11 | always 12 | #2 clk = ~clk; 13 | 14 | initial begin 15 | $monitor("q = %b ", q, " clk = %b ", clk," reset = %b ", reset); 16 | end 17 | 18 | counter4bit ctr(q, clk, reset); 19 | 20 | initial begin 21 | reset = 1'b1; 22 | #4 reset = 1'b0; 23 | // #10 reset = 1'b1; 24 | #64 $finish; 25 | end 26 | 27 | endmodule -------------------------------------------------------------------------------- /Lab3/tb_serialAdder4bit.v: -------------------------------------------------------------------------------- 1 | `include "serialAdder_4bit.v" //Acc, SI, ShftCtrl, clr, clk 2 | module tb_serialAdder4bit(); 3 | 4 | wire [3:0] Acc; 5 | wire SI2; 6 | reg SI; 7 | reg clr, clk, ShftCtrl; 8 | integer i; 9 | 10 | 11 | serialAdder_4bit sa( Acc,SI2, SI, ShftCtrl, clr, clk ); 12 | 13 | always @(posedge clk) begin 14 | $display("ShftCtrl = %b ", ShftCtrl, " SI = %b ", SI," SI2:= ",SI2 ," Acc = %b ", Acc, "Clk: = ",clk," dff_out = %b ", sa.dff.q, "time = ", $time); 15 | end 16 | 17 | reg [19:0] sequence; 18 | 19 | initial begin 20 | 21 | ShftCtrl = 1; 22 | clk = 1'b0; 23 | clr = 1'b0; 24 | #2 clr = 1'b1; 25 | sequence = 20'b0100_0011_0010_0001_0000; 26 | 27 | for(i=0; i<24; i= i+1) begin 28 | if( i<20 ) 29 | SI = sequence[i]; 30 | #2 clk = 1'b1; 31 | #2 clk = 1'b0; 32 | end 33 | 34 | end 35 | 36 | endmodule -------------------------------------------------------------------------------- /Lab3/test_dff_sync.v: -------------------------------------------------------------------------------- 1 | `include "dff_sync_clear.v" 2 | module test_dff_sync; 3 | reg d, clk, rst; 4 | wire q; 5 | 6 | always @(posedge clk) 7 | begin 8 | $monitor("d = %b, clk = %b, rst = %b, q = %b", d,clk,rst,q); 9 | end 10 | 11 | initial begin 12 | forever begin 13 | clk = 0; 14 | #5 clk = 1; 15 | #5 clk = 0; 16 | end 17 | end 18 | initial begin 19 | d = 0; rst = 1; 20 | #4 d = 1; rst = 0; 21 | #50 d = 1; rst = 1; 22 | #20 d = 0; rst = 0; 23 | end 24 | 25 | dff_sync_clear dff(d,rst,clk,q); 26 | endmodule -------------------------------------------------------------------------------- /Lab3/test_seqDetect.v: -------------------------------------------------------------------------------- 1 | `include "seqDetect.v" 2 | 3 | module test_seqDetect(); 4 | 5 | reg inSeq, clk, reset; 6 | wire [2:0] state; 7 | integer i; 8 | 9 | always @(posedge clk) 10 | $display("inSeq = ", inSeq, " reset = ", reset); 11 | 12 | seqDetect sq(inSeq, clk, reset); 13 | 14 | reg [0:15] sequence; 15 | 16 | initial begin 17 | clk = 1'b0; 18 | reset = 1'b0; 19 | reset = 1'b1; 20 | sequence = 16'b1011_0000_1011_0000; 21 | #5 reset = 1'b0; 22 | 23 | for (i = 0; i < 16 ; i = i+1 ) begin 24 | inSeq = sequence[i]; 25 | #2 clk = 1'b1; 26 | #2 clk = 1'b0; 27 | end 28 | end 29 | 30 | endmodule -------------------------------------------------------------------------------- /Lab3/test_shift_reg_4bit.v: -------------------------------------------------------------------------------- 1 | `include "shift_reg_4bit.v" //shift_reg_4bit(d, clk, rst, q); 2 | 3 | module test_shift_reg_4bit(); 4 | 5 | reg clk, d, rst; 6 | reg [0:15] sequence; 7 | wire [3:0] outp; 8 | integer i; 9 | 10 | shift_reg_4bit shr( d, clk, rst, outp ); 11 | 12 | initial 13 | begin 14 | 15 | d = 0; 16 | rst = 0; 17 | sequence = 16'b0101_0001_1111_1011; 18 | 19 | for (i = 0; i <= 15 ; i = i + 1 ) begin 20 | d = sequence[i]; 21 | #2 clk = 1; 22 | #2 clk = 0; 23 | end 24 | end 25 | 26 | always @(posedge clk or negedge rst) begin 27 | $display( "d = ",d," clk = ", clk, " outp = %b ",outp , " time = ", $time); 28 | end 29 | endmodule -------------------------------------------------------------------------------- /Lab3/test_shift_reg_4bit_lab.v: -------------------------------------------------------------------------------- 1 | `include "shift_reg_4bit_lab.v" //shift_reg_4bit_lab( in, en, Q, clk ); 2 | module test_shift_reg_4bit_lab(); 3 | 4 | reg en, in , clk; 5 | wire [3:0] Q; 6 | 7 | shift_reg_4bit_lab shr(in, en, Q, clk); 8 | 9 | initial 10 | clk = 0; 11 | 12 | always 13 | #2 clk = ~clk; 14 | 15 | initial 16 | $monitor(" in = ", in ," en = ", en, " clk = ",clk, " Q = %b", Q); 17 | 18 | initial 19 | begin 20 | in = 0; en = 0; 21 | #4 in = 1; en = 1; 22 | #4 in = 1; en = 0; 23 | #4 in = 0; en = 1; 24 | #5 $finish; 25 | end 26 | 27 | endmodule -------------------------------------------------------------------------------- /Lab4/Lab4_sheet_aludesign.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/SinghCoder/Icarus_Verilog/c326ccb1b1a354daaf6e61368712536428445de5/Lab4/Lab4_sheet_aludesign.pdf -------------------------------------------------------------------------------- /Lab4/MainCU.PNG: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/SinghCoder/Icarus_Verilog/c326ccb1b1a354daaf6e61368712536428445de5/Lab4/MainCU.PNG -------------------------------------------------------------------------------- /Lab4/README.md: -------------------------------------------------------------------------------- 1 | # Lab Sheet 4 2 | 3 | ## LearningObjectives 4 | 5 | - To design a Simple MIPS ALU in a step by step manner 6 | - To design the main Control PLA to generate control signals 7 | - To design the ALU control Logic -------------------------------------------------------------------------------- /Lab4/alu.v: -------------------------------------------------------------------------------- 1 | `ifndef ALU 2 | `define ALU 3 | `include "fulladder_32bit.v" //(sum,cout,num1, num2,cin ); 4 | `include "module_32bitAND.v" //module_32bitAND( outp, in1, in2 ); 5 | `include "module_32bitOR.v" //module_32bitOR( outp, in1, in2 ); 6 | `include "mux_2to1_32bit.v" //mux_2to1_32bit( outp, inp1, inp2, sel ); 7 | `include "mux_3to1_32bit.v" //mux_3to1_32bit( outp, inp1, inp2, inp3, sel ); 8 | 9 | module alu( input [31:0] a, input [31:0] b, input cin, input binv, input [1:0] oper, output [31:0] result, output cout ); 10 | 11 | wire [31:0] bbar, b_sel_bbar, a_and_b, a_or_b, a_addsub_b; 12 | 13 | assign bbar = ~b; 14 | 15 | mux_2to1_32bit mux2to1_op(b_sel_bbar, b, bbar, binv ); 16 | module_32bitAND and_op( a_and_b, a, b_sel_bbar ); 17 | module_32bitOR or_op( a_or_b, a, b_sel_bbar ); 18 | fulladder_32bit fa_outp( a_addsub_b, cout, a, b_sel_bbar, cin ); 19 | mux_3to1_32bit mux3to1_op( result, a_and_b, a_or_b, a_addsub_b, oper ); 20 | 21 | endmodule 22 | `endif -------------------------------------------------------------------------------- /Lab4/aluCU.v: -------------------------------------------------------------------------------- 1 | module aluCU( oper, aluOp, funcfield ); 2 | 3 | input [1:0] aluOp; 4 | input [3:0] funcfield; 5 | output [2:0] oper; 6 | 7 | assign oper[0] = (funcfield[0] | funcfield[3]) & aluOp[1]; 8 | assign oper[1] = ((~aluOp[1]) | (~funcfield[2])); 9 | assign oper[2] = (aluOp[0] | ( aluOp[1] & funcfield[1] )); 10 | 11 | endmodule -------------------------------------------------------------------------------- /Lab4/fulladder_32bit.v: -------------------------------------------------------------------------------- 1 | module fulladder_32bit( output[31:0] sum, output cout, input [31:0] num1, input [31:0] num2, input cin ); 2 | 3 | assign {cout,sum} = num1+num2+cin; 4 | 5 | endmodule -------------------------------------------------------------------------------- /Lab4/mainCU.v: -------------------------------------------------------------------------------- 1 | `ifndef MAIN_CU 2 | `define MAIN_CU 3 | module mainCU ( RegDest, ALUSrc, MemToReg, RegWrite, MemRead, MemWrite, Branch, ALUOp0, ALUOp1, op ); 4 | 5 | input [5:0] op; 6 | output RegDest, ALUSrc, MemToReg, RegWrite, MemRead, MemWrite, Branch, ALUOp0, ALUOp1; 7 | 8 | wire rformat, lw, sw, beq; 9 | 10 | assign rformat = ~(op[0] | op[1] | op[2] | op[3] | op[4] | op[5]); 11 | assign lw = (op[0] & op[1] & (~op[2]) & (~op[3]) & (~op[4]) & op[5]); 12 | assign sw = (op[0] & op[1] & (~op[2]) & op[3] & (~op[4]) & op[5]); 13 | assign beq = ((~op[0]) & (~op[1]) & op[2] & (~op[3]) & (~op[4]) & (~op[5])); 14 | 15 | assign RegDest = rformat; 16 | assign ALUSrc = lw | sw; 17 | assign MemToReg = lw; 18 | assign RegWrite = rformat | lw; 19 | assign MemRead = lw; 20 | assign MemWrite = sw; 21 | assign Branch = beq; 22 | assign ALUOp0 = rformat; 23 | assign ALUOp1 = beq; 24 | 25 | endmodule 26 | `endif -------------------------------------------------------------------------------- /Lab4/module_32bitAND.v: -------------------------------------------------------------------------------- 1 | module module_32bitAND( outp, in1, in2 ); 2 | 3 | input [31:0] in1, in2; 4 | output [31:0] outp; 5 | assign outp = in1 & in2; 6 | 7 | endmodule 8 | -------------------------------------------------------------------------------- /Lab4/module_32bitOR.v: -------------------------------------------------------------------------------- 1 | module module_32bitOR( outp, in1, in2 ); 2 | 3 | input [31:0] in1, in2; 4 | output [31:0] outp; 5 | assign outp = in1 | in2; 6 | 7 | endmodule 8 | 9 | -------------------------------------------------------------------------------- /Lab4/mux_2to1.v: -------------------------------------------------------------------------------- 1 | `ifndef MUX_2to1 2 | `define MUX_2to1 3 | module mux_2to1( out, sel, in1, in2 ); 4 | 5 | output out; 6 | input in1, in2; 7 | input sel; 8 | wire not_sel, and1, and2; 9 | 10 | // out = (~sel & in1) | (sel & in2); 11 | not( not_sel, sel); 12 | and( and1, not_sel, in1); 13 | and( and2, sel, in2); 14 | or( out, and1, and2); 15 | 16 | endmodule 17 | `endif -------------------------------------------------------------------------------- /Lab4/mux_2to1_32bit.v: -------------------------------------------------------------------------------- 1 | `ifndef MUX_32bit 2 | `define MUX_32bit 3 | `include "mux_2to1_8bit.v" //mux_2to1_8bit( outp, inp1, inp2, sel ); 4 | module mux_2to1_32bit( outp, inp1, inp2, sel ); 5 | 6 | input [31:0] inp1, inp2; 7 | output [31:0] outp; 8 | input sel; 9 | 10 | genvar j; 11 | 12 | generate for(j = 0; j < 4; j = j+1) begin: mux_loop 13 | mux_2to1_8bit mx ( outp[ 8*j+7 : 8*j] , inp1[ 8*j+7 : 8*j], inp2[ 8*j+7 : 8*j], sel); 14 | end 15 | endgenerate 16 | 17 | endmodule 18 | `endif -------------------------------------------------------------------------------- /Lab4/mux_2to1_8bit.v: -------------------------------------------------------------------------------- 1 | `ifndef MUX_8bit 2 | `define MUX_8bit 3 | `include "mux_2to1.v" //mux2to1( out, sel, in1, in2 ); 4 | module mux_2to1_8bit( outp, inp1, inp2, sel ); 5 | input [7:0] inp1, inp2; 6 | input sel; 7 | output [7:0] outp; 8 | 9 | genvar j; 10 | 11 | generate for (j = 0; j<=7; j = j+1) begin: mux_loop 12 | mux_2to1 m1(outp[j], sel, inp1[j], inp2[j]); 13 | end 14 | endgenerate 15 | endmodule 16 | `endif -------------------------------------------------------------------------------- /Lab4/mux_3to1_32bit.v: -------------------------------------------------------------------------------- 1 | `include "mux_2to1_32bit.v" //mux_2to1_32bit( outp, inp1, inp2, sel ); 2 | module mux_3to1_32bit( outp, inp1, inp2, inp3, sel ); 3 | 4 | input [31:0] inp1,inp2,inp3; 5 | output [31:0] outp; 6 | wire [31:0] temp1, temp2; 7 | input [1:0] sel; 8 | 9 | mux_2to1_32bit m1( temp1, inp1, inp2, sel[0] ); 10 | mux_2to1_32bit m2( temp2, inp3, 32'b0, sel[0] ); 11 | mux_2to1_32bit m3( outp, temp1, temp2, sel[1] ); 12 | 13 | endmodule -------------------------------------------------------------------------------- /Lab4/tbALU.v: -------------------------------------------------------------------------------- 1 | `include "alu.v" 2 | module tbALU(); 3 | reg Binvert, Carryin; 4 | reg [1:0] Operation; 5 | reg [31:0] a,b; 6 | wire [31:0] Result; 7 | wire CarryOut; 8 | alu al (a,b,Carryin,Binvert,Operation,Result,CarryOut); 9 | 10 | initial 11 | $monitor("a: %b ",a, " b: %b ", b," op: %b ", Operation,"Binvert: %b ",Binvert, "Res: %b ", Result); 12 | 13 | initial begin 14 | a=32'ha5a5a5a5; 15 | b=32'h5a5a5a5a; 16 | Operation=2'b00; 17 | Binvert=1'b0; 18 | Carryin=1'b0; //must perform AND resulting in zero 19 | #100 Operation=2'b01; //OR 20 | #100 Operation=2'b10; //ADD 21 | #100 Binvert=1'b1; //SUB 22 | #200 $finish; 23 | end 24 | endmodule -------------------------------------------------------------------------------- /Lab4/tb_aluCU.PNG: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/SinghCoder/Icarus_Verilog/c326ccb1b1a354daaf6e61368712536428445de5/Lab4/tb_aluCU.PNG -------------------------------------------------------------------------------- /Lab4/tb_aluCU.v: -------------------------------------------------------------------------------- 1 | `include "aluCU.v" //( oper, aluOp, funcfield ); 2 | module tb_aluCU(); 3 | 4 | reg [1:0] aluOp; 5 | reg [3:0] funcField; 6 | wire [2:0] oper; 7 | 8 | initial 9 | $monitor("oper = %b ", oper, "aluOp = %b ",aluOp, "funcField = %b ", funcField); 10 | 11 | aluCU acu(oper, aluOp, funcField); 12 | 13 | initial begin 14 | aluOp = 2'b00; 15 | funcField = 4'b0000; 16 | #100 aluOp = 2'b01; 17 | #200 aluOp = 2'b10; 18 | #300 funcField = 4'b0000; 19 | #400 funcField = 4'b0010; 20 | #500 funcField = 4'b0100; 21 | #600 funcField = 4'b0101; 22 | #700 funcField = 4'b1010; 23 | end 24 | 25 | endmodule -------------------------------------------------------------------------------- /Lab4/test_32bitAND.v: -------------------------------------------------------------------------------- 1 | `include "module_32bitAND.v" 2 | module test_32bitAND(); 3 | 4 | reg [31:0] inp1, inp2; 5 | wire [31:0] out; 6 | module_32bitAND and32bit( out, inp1, inp2 ); 7 | 8 | initial 9 | $monitor("in1 - %b",inp1," in2 - %b ", inp2 ," out - %b ",out); 10 | 11 | initial begin 12 | inp1 = 32'h3FFFFFFF; 13 | inp2 = 32'h5A000000; 14 | 15 | #100 inp1 = 32'hFFFFFFFF; 16 | #1000 $finish; 17 | end 18 | 19 | endmodule -------------------------------------------------------------------------------- /Lab4/test_32bitOR.v: -------------------------------------------------------------------------------- 1 | `include "module_32bitOR.v" 2 | module test_32bitOR(); 3 | 4 | reg [31:0] inp1, inp2; 5 | wire [31:0] out; 6 | module_32bitOR or32bit( out, inp1, inp2 ); 7 | 8 | initial 9 | $monitor("in1 - %b",inp1," in2 - %b ", inp2 ," out - %b ",out); 10 | 11 | initial begin 12 | inp1 = 32'h3FFFFFFF; 13 | inp2 = 32'h5A000000; 14 | 15 | #100 inp1 = 32'hFFFFFFFF; 16 | #1000 $finish; 17 | end 18 | 19 | endmodule -------------------------------------------------------------------------------- /Lab4/test_32bitadder.v: -------------------------------------------------------------------------------- 1 | `include "fulladder_32bit.v" 2 | module test_32bitadder(); 3 | 4 | reg [31:0] in1, in2; 5 | reg cin; 6 | 7 | wire [31:0] sm; 8 | wire cout; 9 | 10 | fulladder_32bit fa1( sm, cout, in1, in2, cin ); 11 | 12 | initial 13 | $monitor(" in1 %b ", in1, "in2: %b ", in2, "sm: %b ", sm, "cout: ", cout); 14 | 15 | initial begin 16 | in1 = 32'hFFFFFF8E; 17 | in2 = 32'hFFFFFF56; 18 | cin = 0; 19 | end 20 | 21 | endmodule -------------------------------------------------------------------------------- /Lab4/test_mainCU.v: -------------------------------------------------------------------------------- 1 | `include "mainCU.v" 2 | module test_mainCU(); 3 | 4 | reg [5:0] opcode; 5 | wire RegDest, ALUSrc, MemToReg, RegWrite, MemRead, MemWrite, Branch, ALUOp0, ALUOp1; 6 | mainCU mcu(RegDest, ALUSrc, MemToReg, RegWrite, MemRead, MemWrite, Branch, ALUOp0, ALUOp1, opcode); 7 | 8 | initial 9 | $monitor("Opcode: %b ",opcode," RegDest = %b ",RegDest," ALUSrc = %b ",ALUSrc," MemToReg = %b ",MemToReg, " RegWrite = %b ",RegWrite," MemRead = %b ",MemRead," MemWrite = %b ",MemWrite," Branch = %b ",Branch," ALUOp0 = %b ",ALUOp0," ALUOp1 = %b", ALUOp1); 10 | 11 | always @(opcode) begin 12 | $display("Active Signals : "); 13 | if(RegDest) 14 | $display("RegDest"); 15 | if(ALUSrc) 16 | $display("ALUSrc"); 17 | if(MemToReg) 18 | $display("MemToReg"); 19 | if(RegWrite) 20 | $display("RegWrite"); 21 | if(MemRead) 22 | $display("MemRead"); 23 | if(MemWrite) 24 | $display("MemWrite"); 25 | if(Branch) 26 | $display("Branch"); 27 | if(ALUOp0) 28 | $display("ALUOp0"); 29 | if(ALUOp1) 30 | $display("ALUOp1"); 31 | end 32 | 33 | 34 | initial begin 35 | opcode = 6'b000000; 36 | #500 opcode = 6'b100011; 37 | #1000 opcode = 6'b101011; 38 | #1500 opcode = 6'b000100; 39 | #2000 $finish; 40 | end 41 | 42 | 43 | endmodule -------------------------------------------------------------------------------- /Lab4/test_mux_2to1_32bit.v: -------------------------------------------------------------------------------- 1 | `include "mux_2to1_32bit.v" //mux_2to1_32bit( outp, inp1, inp2, sel ) 2 | module test_mux_2to1_32bit(); 3 | 4 | reg [31:0] inp1, inp2; 5 | reg sel; 6 | wire [31:0] outp; 7 | 8 | mux_2to1_32bit mx(outp, inp1, inp2, sel); 9 | 10 | initial begin 11 | $monitor(" inp1: %b ", inp1, " inp2: %b ", inp2," sel: ",sel, " outp: %b ",outp); 12 | end 13 | 14 | initial begin 15 | inp1 = 32'b00000000000000000000000000000000; 16 | inp2 = 32'b11111111111111111111111111111111; 17 | 18 | sel = 1'b0; 19 | #100 sel = 1'b1; 20 | #1000 $finish; 21 | end 22 | 23 | endmodule -------------------------------------------------------------------------------- /Lab4/test_mux_2to1_8bit.PNG: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/SinghCoder/Icarus_Verilog/c326ccb1b1a354daaf6e61368712536428445de5/Lab4/test_mux_2to1_8bit.PNG -------------------------------------------------------------------------------- /Lab4/test_mux_2to1_8bit.v: -------------------------------------------------------------------------------- 1 | `include "mux_2to1_8bit.v" //mux_2to1_8bit( outp, inp1, inp2, sel ); 2 | module test_mux_2to1_8bit(); 3 | reg [7:0] inp1, inp2; 4 | reg sel; 5 | wire [7:0] outp; 6 | 7 | mux_2to1_8bit mx(outp, inp1, inp2, sel); 8 | 9 | initial begin 10 | inp1=8'b10101010; 11 | inp2=8'b01010101; 12 | sel=1'b0; 13 | #100 sel=1'b1; 14 | #1000 $finish; 15 | end 16 | 17 | initial 18 | $monitor(" inp1 = %b ", inp1, " inp2 = %b ", inp2, " sel = ", sel, " outp = %b", outp); 19 | 20 | endmodule -------------------------------------------------------------------------------- /Lab4/test_mux_3to1_32bit.v: -------------------------------------------------------------------------------- 1 | `include "mux_3to1_32bit.v" //mux3to1_32bit( outp, inp1, inp2, inp3, sel ) 2 | module test_mux_3to1_32bit(); 3 | 4 | reg [31:0] in1, in2, in3; 5 | reg [1:0] sel; 6 | wire [31:0] outp; 7 | 8 | mux_3to1_32bit mx( outp, in1, in2, in3, sel ); 9 | 10 | initial begin 11 | $monitor(" in1: %b",in1," in2: %b", in2," in3: %b", in3," sel: %b", sel," out: %b", outp); 12 | end 13 | 14 | initial begin 15 | in1 = 32'b0; 16 | in2 = 32'b11111111111111111111111111111111; 17 | in3 = {16'b0, 16'b1111111111111111}; 18 | 19 | sel = 2'b00; 20 | #10 sel = 2'b01; 21 | #100 sel = 2'b10; 22 | #500 sel = 2'b11; 23 | 24 | #1000 $finish; 25 | 26 | end 27 | 28 | endmodule -------------------------------------------------------------------------------- /Lab5/Lab5_sheet_registerfile.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/SinghCoder/Icarus_Verilog/c326ccb1b1a354daaf6e61368712536428445de5/Lab5/Lab5_sheet_registerfile.pdf -------------------------------------------------------------------------------- /Lab5/README.md: -------------------------------------------------------------------------------- 1 | # Lab Sheet 5 2 | 3 | ## LearningObjectives 4 | 5 | - Designing a sample 32-bit register file for a MIPS processor -------------------------------------------------------------------------------- /Lab5/decoder_2to4.v: -------------------------------------------------------------------------------- 1 | `ifndef DECODER_2TO4 2 | `define DECODER_2TO4 3 | module decoder_2to4( 4 | output reg [3:0] register, 5 | input [1:0] regNo); 6 | 7 | always @(regNo) begin 8 | case (regNo) 9 | 2'b00 : 10 | register = 4'b0001; 11 | 2'b01 : 12 | register = 4'b0010; 13 | 2'b10 : 14 | register = 4'b0100; 15 | 2'b11 : 16 | register = 4'b1000; 17 | endcase 18 | end 19 | 20 | endmodule 21 | `endif 22 | -------------------------------------------------------------------------------- /Lab5/mux_4to1.v: -------------------------------------------------------------------------------- 1 | `ifndef MUX_4to1 2 | `define MUX_4to1 3 | module mux_4to1( 4 | output [31:0] regData, 5 | input [31:0] q0, 6 | input [31:0] q1, 7 | input [31:0] q2, 8 | input [31:0] q3, 9 | input [1:0] regNo); 10 | 11 | reg regData; 12 | 13 | always @(regNo) begin 14 | case (regNo) 15 | 2'b00: 16 | regData = q0; 17 | 2'b01: 18 | regData = q1; 19 | 2'b10: 20 | regData = q2; 21 | 2'b11: 22 | regData = q3; 23 | endcase 24 | end 25 | endmodule 26 | `endif 27 | -------------------------------------------------------------------------------- /Lab5/regFile.v: -------------------------------------------------------------------------------- 1 | `ifndef REGFILE 2 | `define REGFILE 3 | `include "reg_32bit.v" //q,d,clk,reset 4 | `include "mux_4to1.v" //regData,q0,q1,q2,q3,regNo 5 | `include "decoder_2to4.v" //register, regNo 6 | 7 | module regFile( 8 | input clk, 9 | input reset, 10 | input [1:0] readReg1, 11 | input [1:0] readReg2, 12 | input [31:0] writeData, 13 | input regWrite, 14 | input [1:0] writeReg, 15 | output [31:0] readData1, 16 | output [31:0] readData2); 17 | genvar j; 18 | 19 | wire [3:0][31:0] regOut; 20 | reg [31:0] regIn; 21 | wire [3:0] decoderOut; 22 | wire [3:0] regClk; 23 | 24 | assign regClk[0] = (clk & regWrite & decoderOut[0]); 25 | assign regClk[1] = (clk & regWrite & decoderOut[1]); 26 | assign regClk[2] = (clk & regWrite & decoderOut[2]); 27 | assign regClk[3] = (clk & regWrite & decoderOut[3]); 28 | 29 | reg_32bit r0( regOut[0], regIn, regClk[0], reset ); 30 | reg_32bit r1( regOut[1], regIn, regClk[1], reset ); 31 | reg_32bit r2( regOut[2], regIn, regClk[2], reset ); 32 | reg_32bit r3( regOut[3], regIn, regClk[3], reset ); 33 | 34 | mux_4to1 m1( readData1, regOut[0] , regOut[1] , regOut[2], regOut[3], readReg1 ); 35 | mux_4to1 m2( readData2, regOut[0] , regOut[1] , regOut[2] , regOut[3], readReg2 ); 36 | decoder_2to4 dec1( decoderOut, writeReg ); 37 | 38 | endmodule 39 | `endif -------------------------------------------------------------------------------- /Lab5/reg_32bit.v: -------------------------------------------------------------------------------- 1 | `ifndef REG_32BIT 2 | `define REG_32BIT 3 | `include "../Lab3/dff_sync_clear.v" // d, clr, clk ,q 4 | module reg_32bit( 5 | output [31:0] q, 6 | input [31:0] d, 7 | input clk, 8 | input reset); 9 | 10 | genvar num; 11 | 12 | generate for (num = 0 ; num < 32 ; num = num + 1) begin: ffs 13 | dff_sync_clear dff( d[num], reset, clk, q[num] ); 14 | end 15 | endgenerate 16 | endmodule 17 | `endif -------------------------------------------------------------------------------- /Lab5/tb_reg32bit.v: -------------------------------------------------------------------------------- 1 | `include "reg_32bit.v" 2 | module tb_reg32bit(); 3 | 4 | wire [31:0] q; 5 | reg [31:0] d; 6 | reg clk, reset; 7 | reg_32bit register( q, d, clk, reset); 8 | 9 | always @(clk) 10 | #5 clk <= ~clk; 11 | 12 | initial 13 | $monitor("clk: ",clk," Reset = ", reset, " D = %b ", d, "Q = %b ",q," time = ", $time); 14 | 15 | initial begin 16 | clk = 1'b1; 17 | reset = 1'b0; 18 | #20 reset = 1'b1; 19 | #20 d = 32'hAFAFAFAF; 20 | #200 $finish; 21 | end 22 | 23 | endmodule -------------------------------------------------------------------------------- /Lab6/ADDER_8bit.v: -------------------------------------------------------------------------------- 1 | `include "FADDER.v" 2 | module ADDER_8bit(cfinal,sum,num1,num2,cin); 3 | 4 | input [7:0] num1,num2; 5 | output [7:0] sum; 6 | wire [7:0] cout; 7 | input cin; 8 | output cfinal; 9 | 10 | FADDER add0(sum[0],cout[0],num1[0],num2[0],cin); 11 | FADDER add1(sum[1],cout[1],num1[1],num2[1],cout[0]); 12 | FADDER add2(sum[2],cout[2],num1[2],num2[2],cout[1]); 13 | FADDER add3(sum[3],cout[3],num1[3],num2[3],cout[2]); 14 | FADDER add4(sum[4],cout[4],num1[4],num2[4],cout[3]); 15 | FADDER add5(sum[5],cout[5],num1[5],num2[5],cout[4]); 16 | FADDER add6(sum[6],cout[6],num1[6],num2[6],cout[5]); 17 | FADDER add7(sum[7],cout[7],num1[7],num2[7],cout[6]); 18 | 19 | assign cfinal = cout[7]; 20 | endmodule -------------------------------------------------------------------------------- /Lab6/Lab_Sheet_6_Single_Cycle_Datapath_Final.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/SinghCoder/Icarus_Verilog/c326ccb1b1a354daaf6e61368712536428445de5/Lab6/Lab_Sheet_6_Single_Cycle_Datapath_Final.pdf -------------------------------------------------------------------------------- /Lab6/README.md: -------------------------------------------------------------------------------- 1 | # Lab Sheet 6 2 | 3 | ## LearningObjectives 4 | 5 | - Modeling MIPS Single Cycle Datapath in Verilog 6 | - Designing modules for each hardware component and some support modules 7 | - Implementation of the modules in Verilog 8 | - Integrating these modules 9 | - Writing test bench 10 | - Testing the circuit with R-format instruction. -------------------------------------------------------------------------------- /Lab6/SCDatapath.v: -------------------------------------------------------------------------------- 1 | `ifndef SC_DATAPATH 2 | `define SC_DATAPATH 3 | `include "im.v" 4 | `include "dm.v" 5 | `include "regFile.v" 6 | `include "alu.v" 7 | `include "aluCU.v" 8 | `include "mainCU.v" 9 | `include "signExt.v" 10 | `include "shifter.v" 11 | `include "fulladder_32bit.v" 12 | `include "mux_2to1_32bit.v" 13 | `include "reg_32bit.v" 14 | 15 | 16 | module SCDatapath( 17 | input reset, 18 | ); 19 | 20 | //PC with address 0 21 | reg clk; 22 | reg [4:0] pcOut; 23 | reg5bit pc( 5'b0, clk, pcOut ); 24 | 25 | //instr memory 26 | im instrMem( pc, reset , instr ); 27 | 28 | 29 | endmodule 30 | 31 | module reg5bit( 32 | input [4:0] inp, 33 | input clk, 34 | output [4:0] outp); 35 | 36 | always @(posedge clk) 37 | outp = inp; 38 | 39 | endmodule 40 | `endif -------------------------------------------------------------------------------- /Lab6/adder_32bit.v: -------------------------------------------------------------------------------- 1 | `include "ADDER_8bit.v" 2 | 3 | module adder_32bit(cfinal,sum,num1,num2,cin); 4 | input [31:0] num1,num2; 5 | input cin; 6 | output [31:0] sum; 7 | output cfinal; 8 | wire cout[3:0]; 9 | 10 | ADDER_8bit add1(cout[0],sum[7:0],num1[7:0],num2[7:0],cin); 11 | ADDER_8bit add2(cout[1],sum[15:8],num1[15:8],num2[15:8],cout[0]); 12 | ADDER_8bit add3(cout[2],sum[23:16],num1[23:16],num2[23:16],cout[1]); 13 | ADDER_8bit add4(cout[3],sum[31:24],num1[31:24],num2[31:24],cout[2]); 14 | 15 | assign cfinal = cout[2]; 16 | 17 | endmodule -------------------------------------------------------------------------------- /Lab6/alu.v: -------------------------------------------------------------------------------- 1 | `ifndef ALU 2 | `define ALU 3 | `include "fulladder_32bit.v" //(sum,cout,num1, num2,cin ); 4 | `include "module_32bitAND.v" //module_32bitAND( outp, in1, in2 ); 5 | `include "module_32bitOR.v" //module_32bitOR( outp, in1, in2 ); 6 | `include "mux_2to1_32bit.v" //mux_2to1_32bit( outp, inp1, inp2, sel ); 7 | `include "mux_3to1_32bit.v" //mux_3to1_32bit( outp, inp1, inp2, inp3, sel ); 8 | 9 | module alu( input [31:0] a, input [31:0] b, input cin, input binv,input reset, input [1:0] oper, output [31:0] result, output cout ); 10 | 11 | wire [31:0] bbar, b_sel_bbar, a_and_b, a_or_b, a_addsub_b; 12 | 13 | assign bbar = ~b; 14 | 15 | mux_2to1_32bit mux2to1_op(b_sel_bbar, b, bbar, binv ); 16 | module_32bitAND and_op( a_and_b, a, b_sel_bbar ); 17 | module_32bitOR or_op( a_or_b, a, b_sel_bbar ); 18 | fulladder_32bit fa_outp( a_addsub_b, cout, a, b_sel_bbar, cin ); 19 | mux_3to1_32bit mux3to1_op( result, a_and_b, a_or_b, a_addsub_b, oper ); 20 | 21 | endmodule 22 | `endif -------------------------------------------------------------------------------- /Lab6/aluCU.v: -------------------------------------------------------------------------------- 1 | module aluCU( oper, aluOp, funcfield ); 2 | 3 | input [1:0] aluOp; 4 | input [3:0] funcfield; 5 | output [2:0] oper; 6 | 7 | assign oper[0] = (funcfield[0] | funcfield[3]) & aluOp[1]; 8 | assign oper[1] = ((~aluOp[1]) | (~funcfield[2])); 9 | assign oper[2] = (aluOp[0] | ( aluOp[1] & funcfield[1] )); 10 | 11 | endmodule -------------------------------------------------------------------------------- /Lab6/dm.v: -------------------------------------------------------------------------------- 1 | `ifndef DM 2 | `define DM 3 | module DM( 4 | input [4:0] addr, 5 | input [31:0] data, 6 | input reset, 7 | input memWrite, 8 | input memRead, 9 | output [31:0] readData); 10 | 11 | reg [31:0] mem [0:31]; 12 | 13 | always @(memWrite) 14 | if(~memRead) 15 | mem[addr] = data; 16 | 17 | always @(memRead) 18 | readData = mem[addr]; 19 | 20 | always @(reset) begin 21 | if(reset) begin 22 | for( j=0; j<32; j = j+1) begin 23 | data[j] = 32'd0; 24 | end 25 | end 26 | end 27 | 28 | endmodule 29 | `endif 30 | -------------------------------------------------------------------------------- /Lab6/im.v: -------------------------------------------------------------------------------- 1 | `ifndef IM 2 | `define IM 3 | module im( 4 | input [4:0] pc, 5 | input reset, 6 | output [31:0] instr); 7 | 8 | reg [31:0] mem[0:31]; //32 mem locns each 32 bit wide 9 | 10 | always @(pc) 11 | instr = mem[pc]; 12 | 13 | always @(reset) begin 14 | if(reset) begin 15 | 16 | //initialization 17 | mem[0] = 32'h00000200; 18 | mem[1] = 32'h00000201; 19 | mem[2] = 32'h00000204; 20 | mem[3] = 32'h00000108; 21 | 22 | end 23 | end 24 | 25 | endmodule 26 | `endif 27 | -------------------------------------------------------------------------------- /Lab6/regFile.v: -------------------------------------------------------------------------------- 1 | `ifndef REGFILE 2 | `define REGFILE 3 | `include "reg_32bit.v" //q,d,clk,reset 4 | `include "mux_4to1.v" //regData,q0,q1,q2,q3,regNo 5 | `include "decoder_2to4.v" //register, regNo 6 | 7 | module regFile( 8 | input clk, 9 | input reset, 10 | input [1:0] readReg1, 11 | input [1:0] readReg2, 12 | input [31:0] writeData, 13 | input regWrite, 14 | input [1:0] writeReg, 15 | output [31:0] readData1, 16 | output [31:0] readData2); 17 | 18 | genvar j; 19 | 20 | wire [3:0][31:0] regOut; 21 | reg [31:0] regIn; 22 | wire [3:0] decoderOut; 23 | wire [3:0] regClk; 24 | 25 | assign regClk[0] = (clk & regWrite & decoderOut[0]); 26 | assign regClk[1] = (clk & regWrite & decoderOut[1]); 27 | assign regClk[2] = (clk & regWrite & decoderOut[2]); 28 | assign regClk[3] = (clk & regWrite & decoderOut[3]); 29 | 30 | reg_32bit r0( regOut[0], regIn, regClk[0], reset ); 31 | reg_32bit r1( regOut[1], regIn, regClk[1], reset ); 32 | reg_32bit r2( regOut[2], regIn, regClk[2], reset ); 33 | reg_32bit r3( regOut[3], regIn, regClk[3], reset ); 34 | 35 | mux_4to1 m1( readData1, regOut[0] , regOut[1] , regOut[2], regOut[3], readReg1 ); 36 | mux_4to1 m2( readData2, regOut[0] , regOut[1] , regOut[2] , regOut[3], readReg2 ); 37 | decoder_2to4 dec1( decoderOut, writeReg ); 38 | 39 | endmodule 40 | `endif -------------------------------------------------------------------------------- /Lab6/reg_32bit.v: -------------------------------------------------------------------------------- 1 | `ifndef REG_32BIT 2 | `define REG_32BIT 3 | `include "dff_sync_clear.v" // d, clr, clk ,q 4 | module reg_32bit( 5 | output [31:0] q, 6 | input [31:0] d, 7 | input clk, 8 | input reset); 9 | 10 | genvar num; 11 | 12 | generate for (num = 0 ; num < 32 ; num = num + 1) begin: ffs 13 | dff_sync_clear dff( d[num], reset, clk, q[num] ); 14 | end 15 | endgenerate 16 | endmodule 17 | `endif -------------------------------------------------------------------------------- /Lab6/shifter.v: -------------------------------------------------------------------------------- 1 | `ifndef SHIFTER 2 | `define SHIFTER 3 | module shifter( 4 | input [31:0] inp, 5 | output [31:0] outp); 6 | 7 | assign outp = {inp[29:0],2'b00}; 8 | 9 | endmodule 10 | `endif -------------------------------------------------------------------------------- /Lab6/signExt.v: -------------------------------------------------------------------------------- 1 | `ifndef SIGN_EXT 2 | `define SIGN_EXT 3 | 4 | module signExt( 5 | input [15:0] inp, 6 | output [31:0] seOutp); 7 | 8 | assign seOutp = {16{inp[15]},inp[15:0]}; 9 | 10 | endmodule 11 | `endif -------------------------------------------------------------------------------- /Lab7/LabSheet7.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/SinghCoder/Icarus_Verilog/c326ccb1b1a354daaf6e61368712536428445de5/Lab7/LabSheet7.pdf -------------------------------------------------------------------------------- /Lab7/README.md: -------------------------------------------------------------------------------- 1 | # Lab Sheet 7 2 | 3 | ## LearningObjectives 4 | 5 | - design the Main controller for MIPS multicycle implementation -------------------------------------------------------------------------------- /Lab7/mainController.v: -------------------------------------------------------------------------------- 1 | `ifndef MC 2 | `define MC 3 | module mainController( 4 | input [5:0] opcode , 5 | input [3:0] state, 6 | output PCWrite , 7 | output PCWriteCond, 8 | output IorD, 9 | output MemRead, 10 | output MemWrite, 11 | output IRWrite, 12 | output MemToReg, 13 | output PCSource1, 14 | output PCSource0, 15 | output ALUOp1, 16 | output ALUOp0, 17 | output ALUSrcB1, 18 | output ALUSrcB0, 19 | output ALUSrcA, 20 | output RegWrite, 21 | output RegDst, 22 | output [3:0] NS); 23 | 24 | wire [16:0] ands; 25 | 26 | assign ands[0] = ((~state[0]) & (~state[1]) & (~state[2]) & (~state[3]) ); 27 | assign ands[1] = ((state[0]) & (~state[1]) & (~state[2]) & (~state[3]) ); 28 | assign ands[2] = ((~state[0]) & (state[1]) & (~state[2]) & (~state[3]) ); 29 | assign ands[3] = ((state[0]) & (state[1]) & (~state[2]) & (~state[3]) ); 30 | assign ands[4] = ((~state[0]) & (~state[1]) & (state[2]) & (~state[3]) ); 31 | assign ands[5] = ((state[0]) & (~state[1]) & (state[2]) & (~state[3]) ); 32 | assign ands[6] = ((~state[0]) & (state[1]) & (state[2]) & (~state[3]) ); 33 | assign ands[7] = ((state[0]) & (state[1]) & (state[2]) & (~state[3]) ); 34 | assign ands[8] = ((~state[0]) & (~state[1]) & (~state[2]) & (state[3]) ); 35 | assign ands[9] = ((state[0]) & (~state[1]) & (~state[2]) & (state[3]) ); 36 | assign ands[10] = ((state[0]) & (~state[1]) & (~state[2]) & (~state[3]) & (~opcode[0]) & (opcode[1]) & (~opcode[2]) & (~opcode[3]) & (~opcode[4]) & (~opcode[5]) ); 37 | assign ands[11] = ((state[0]) & (~state[1]) & (~state[2]) & (~state[3]) & (~opcode[0]) & (~opcode[1]) & (opcode[2]) & (~opcode[3]) & (~opcode[4]) & (~opcode[5]) ); 38 | assign ands[12] = ((state[0]) & (~state[1]) & (~state[2]) & (~state[3]) & (~opcode[0]) & (~opcode[1]) & (~opcode[2]) & (~opcode[3]) & (~opcode[4]) & (~opcode[5]) ); 39 | assign ands[13] = ((~state[0]) & (state[1]) & (~state[2]) & (~state[3]) & (opcode[0]) & (opcode[1]) & (~opcode[2]) & (opcode[3]) & (~opcode[4]) & (opcode[5]) ); 40 | assign ands[14] = ((state[0]) & (~state[1]) & (~state[2]) & (~state[3]) & (opcode[0]) & (opcode[1]) & (~opcode[2]) & (~opcode[3]) & (~opcode[4]) & (opcode[5]) ); 41 | assign ands[15] = ((state[0]) & (~state[1]) & (~state[2]) & (~state[3]) & (opcode[0]) & (opcode[1]) & (~opcode[2]) & (opcode[3]) & (~opcode[4]) & (opcode[5]) ); 42 | assign ands[16] = ((~state[0]) & (state[1]) & (~state[2]) & (~state[3]) & (opcode[0]) & (opcode[1]) & (~opcode[2]) & (~opcode[3]) & (~opcode[4]) & (opcode[5]) ); 43 | 44 | 45 | assign PCWrite = ands[0] | ands[9]; 46 | assign PCWriteCond = ands[8]; 47 | assign IorD = ands[3] | ands[5]; 48 | assign MemRead = ands[0] | ands[3]; 49 | assign MemWrite = ands[5]; 50 | assign IRWrite = ands[0]; 51 | assign MemToReg = ands[4]; 52 | assign PCSource1 = ands[9] ; 53 | assign PCSource0 = ands[8]; 54 | assign ALUOp1 = ands[6]; 55 | assign ALUOp0 = ands[8]; 56 | assign ALUSrcB1 = ands[1] | ands[2]; 57 | assign ALUSrcB0 = ands[0] | ands[1]; 58 | assign ALUSrcA = ands[2] | ands[6] | ands[8] ; 59 | assign RegWrite = ands[4] | ands[7] ; 60 | assign RegDst = ands[7] ; 61 | 62 | assign NS[3] = ands[10] | ands[11] ; 63 | assign NS[2] = ands[12] | ands[13] | ands[3] | ands[6] ; 64 | assign NS[1] = ands[12] | ands[14] | ands[15] | ands[16] | ands[6] ; 65 | assign NS[0] = ands[16] | ands[13] | ands[10] | ands[6] | ands[0] ; 66 | 67 | 68 | endmodule 69 | `endif -------------------------------------------------------------------------------- /Lab7/tb_mc.v: -------------------------------------------------------------------------------- 1 | `include "mainController.v" 2 | module tb_mc(); 3 | 4 | reg [5:0] opcode; 5 | reg [3:0] state; 6 | wire PCWrite ; 7 | wire PCWriteCond; 8 | wire IorD; 9 | wire MemRead; 10 | wire MemWrite; 11 | wire IRWrite; 12 | wire MemToReg; 13 | wire PCSource1; 14 | wire PCSource0; 15 | wire ALUOp1; 16 | wire ALUOp0; 17 | wire ALUSrcB1; 18 | wire ALUSrcB0; 19 | wire ALUSrcA; 20 | wire RegWrite; 21 | wire RegDst; 22 | wire [3:0] NS; 23 | 24 | mainController mc(opcode, state, PCWrite , PCWriteCond, IorD, MemRead, MemWrite, IRWrite, MemToReg, PCSource1, PCSource0, ALUOp1, ALUOp0, ALUSrcB1, ALUSrcB0, ALUSrcA, RegWrite, RegDst, NS ); 25 | 26 | initial 27 | $monitor("opcode: %b ",opcode,"state: %b ",state," PCWrite: %b ", PCWrite ,"PCWriteCond : %b ", PCWriteCond,"IorD: %b ", IorD," MemRead: %b ", MemRead," MemWrite: %b ", MemWrite," IRWrite: %b ", IRWrite," MemToReg: %b ", MemToReg," PCSource1: %b ", PCSource1," PCSource0: %b ", PCSource0," ALUOp1: %b ", ALUOp1," ALUOp0: %b", ALUOp0, " ALUSrcB1: %b ", ALUSrcB1," ALUSrcB0 : %b ", ALUSrcB0," ALUSrcA: %b ", ALUSrcA," RegWrite: %b ", RegWrite," RegDst: %b ", RegDst," NS: %b", NS ); 28 | 29 | initial begin 30 | state = 4'b0000; 31 | #5 state = 4'b0001; 32 | #10 opcode = 6'h23; 33 | #15 state = 4'b0010; 34 | end 35 | endmodule -------------------------------------------------------------------------------- /Lab8/Lab_Sheet_8_Pipeline_DesignF.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/SinghCoder/Icarus_Verilog/c326ccb1b1a354daaf6e61368712536428445de5/Lab8/Lab_Sheet_8_Pipeline_DesignF.pdf -------------------------------------------------------------------------------- /Lab8/README.md: -------------------------------------------------------------------------------- 1 | # Lab Sheet 8 2 | 3 | ## LearningObjectives 4 | 5 | - Modeling 3-stage pipeline design shown below in Verilog 6 | - Designing modules for each hardware component and some support modules 7 | occurring in the pipeline design. 8 | - Implementation of the modules in Verilog 9 | - Integrating these modules 10 | - Writing test bench -------------------------------------------------------------------------------- /Lab8/pipelineAlu.v: -------------------------------------------------------------------------------- 1 | `ifndef PIPELINE_ALU 2 | `define PIPELINE_ALU 3 | `include "pipelineEnc.v" 4 | 5 | module pipelineAlu( 6 | input [2:0] opcode, 7 | input [3:0] srcA, 8 | input [3:0] srcB, 9 | output [3:0] aluOut 10 | ); 11 | 12 | wire [3:0] aluOut; 13 | 14 | assign aluOut = (opcode == `ADD) ? (srcA + srcB) : 15 | (opcode == `SUB) ? (srcA - srcB) : 16 | (opcode == `XOR) ? (srcA ^ srcB) : 17 | (opcode == `OR) ? (srcA | srcB) : 18 | (opcode == `AND) ? (srcA & srcB) : 19 | (opcode == `NOR) ? ~(srcA | srcB) : 20 | (opcode == `NAND) ? ~(srcA & srcB) : 21 | (opcode == `XNOR) ? ~(srcA ^ srcB) : 4'b0; 22 | 23 | 24 | endmodule 25 | 26 | `endif -------------------------------------------------------------------------------- /Lab8/pipelineCircuit.v: -------------------------------------------------------------------------------- 1 | `ifndef PIPELINE_CIRCUIT 2 | `define PIPELINE_CIRCUIT 3 | `include "pipelineParGen.v" 4 | `include "pipelineAlu.v" 5 | `include "pipelineEnc.v" 6 | 7 | module pipelineCircuit( 8 | input [7:0] fncode, 9 | input [3:0] srcA, 10 | input [3:0] srcB, 11 | output parity 12 | ); 13 | /* 14 | ToDo: Use these registers for implementation, Code not correct right now as per labsheet requirements. 15 | */ 16 | reg [10:0] IF_EXReg; 17 | reg [3:0] EX_PARReg; 18 | 19 | wire [2:0] opcode; 20 | wire [3:0] aluOut; 21 | 22 | pipelineEnc enc(fncode, opcode); 23 | pipelineAlu alu(opcode, srcA, srcB, aluOut); 24 | pipelineParGen pargen(aluOut, parity); 25 | 26 | 27 | endmodule 28 | 29 | 30 | 31 | `endif 32 | -------------------------------------------------------------------------------- /Lab8/pipelineEnc.v: -------------------------------------------------------------------------------- 1 | `ifndef PIPELINE_ENC 2 | `define PIPELINE_ENC 3 | 4 | `define ADD 3'b000 5 | `define SUB 3'b001 6 | `define XOR 3'b010 7 | `define OR 3'b011 8 | `define AND 3'b100 9 | `define NOR 3'b101 10 | `define NAND 3'b110 11 | `define XNOR 3'b111 12 | 13 | module pipelineEnc( 14 | input [7:0] fncode, 15 | output [2:0] opcode); 16 | 17 | reg [2:0] opcode; 18 | 19 | always @(fncode) begin 20 | case (fncode) 21 | 8'b00000001 : opcode = `ADD; 22 | 8'b00000010 : opcode = `SUB; 23 | 8'b00000100 : opcode = `XOR; 24 | 8'b00001000 : opcode = `OR; 25 | 8'b00010000 : opcode = `AND; 26 | 8'b00100000 : opcode = `NOR; 27 | 8'b01000000 : opcode = `NAND; 28 | 8'b10000000 : opcode = `XNOR; 29 | endcase 30 | end 31 | 32 | 33 | endmodule 34 | 35 | `endif -------------------------------------------------------------------------------- /Lab8/pipelineParGen.v: -------------------------------------------------------------------------------- 1 | `ifndef PIPELINE_PAR_GEN 2 | `define PIPELINE_PAR_GEN 3 | `include "pipelineAlu.v" 4 | `include "pipelineEnc.v" 5 | 6 | module pipelineParGen( 7 | input [3:0] aluOut, 8 | output parity 9 | ); 10 | 11 | assign parity = aluOut[0] ^ aluOut[1] ^ aluOut[2] ^ aluOut[3]; 12 | 13 | endmodule 14 | 15 | `endif -------------------------------------------------------------------------------- /Lab8/tb_pipeline.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/SinghCoder/Icarus_Verilog/c326ccb1b1a354daaf6e61368712536428445de5/Lab8/tb_pipeline.png -------------------------------------------------------------------------------- /Lab8/tb_pipeline.v: -------------------------------------------------------------------------------- 1 | `include "pipelineCircuit.v" 2 | module tb_pipeline(); 3 | 4 | reg [7:0] fncode; 5 | reg [3:0] srcA, srcB; 6 | 7 | wire parity; 8 | 9 | pipelineCircuit pc(fncode, srcA, srcB, parity); 10 | 11 | initial begin 12 | 13 | fncode = 8'b00000001; 14 | srcA = 4'b0001; 15 | srcB = 4'b0001; 16 | 17 | #100 fncode = 8'b00000010; 18 | #200 fncode = 8'b00000100; 19 | #300 fncode = 8'b00001000; 20 | #400 fncode = 8'b00010000; 21 | #500 fncode = 8'b00100000; 22 | #600 fncode = 8'b01000000; 23 | #700 fncode = 8'b10000000; 24 | 25 | #10 $display(""); 26 | 27 | #100 fncode = 8'b00000001; 28 | srcA = 4'b0101; 29 | srcB = 4'b1010; 30 | 31 | #100 fncode = 8'b00000010; 32 | #200 fncode = 8'b00000100; 33 | #300 fncode = 8'b00001000; 34 | #400 fncode = 8'b00010000; 35 | #500 fncode = 8'b00100000; 36 | #600 fncode = 8'b01000000; 37 | #700 fncode = 8'b10000000; 38 | end 39 | 40 | initial begin 41 | $monitor( "fncode : %b ",fncode, " srcA: %b ", srcA," srcB: %b ", srcB, " aluOut: %b ",pc.aluOut, " parity: %b ", parity ); 42 | end 43 | 44 | endmodule -------------------------------------------------------------------------------- /LabTestPractice/2k11-12/LabTest.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/SinghCoder/Icarus_Verilog/c326ccb1b1a354daaf6e61368712536428445de5/LabTestPractice/2k11-12/LabTest.pdf -------------------------------------------------------------------------------- /LabTestPractice/2k11-12/Solution/ALU64bit.v: -------------------------------------------------------------------------------- 1 | // Design module for ALU64bit 2 | 3 | module ALU64bit(key,left,right,select); 4 | output reg [63:0] key; 5 | input [63:0] left, right; 6 | input select; 7 | 8 | always @(left,right,select) 9 | begin 10 | if(select) // Key 1 : add 11 | key = left + right; 12 | else // Key 2 : subtract 13 | key = left - right; 14 | end 15 | 16 | endmodule -------------------------------------------------------------------------------- /LabTestPractice/2k11-12/Solution/AlgoTest.v: -------------------------------------------------------------------------------- 1 | // Stimulus Module for Algorithm 2 | 3 | module AlgoTest; 4 | wire [255:0] cipherText, decipherText; 5 | reg [247:0] plainText; 6 | reg [63:0] key; 7 | 8 | Encrypt encrypt(cipherText, plainText, key); 9 | Decrypt decrypt (decipherText, cipherText, key); 10 | 11 | initial 12 | begin 13 | 14 | $display("Simulated output of encrption/decrption algorithm"); 15 | $monitor("At time %0d PlainText = %b \n CipherText = %b DecipherText = %b",$time,plainText,cipherText,decipherText); 16 | 17 | #0 plainText = 20; 18 | key = 15; 19 | 20 | #60 $stop; 21 | 22 | end 23 | 24 | endmodule -------------------------------------------------------------------------------- /LabTestPractice/2k11-12/Solution/Decrypt.v: -------------------------------------------------------------------------------- 1 | // Desing Module for Decryption 2 | 3 | module Decrypt(decipherText,cipherText,key); 4 | output reg [255:0] decipherText; 5 | input [255:0] cipherText ; 6 | input [63:0] key; 7 | 8 | wire [63:0] key1,key2; 9 | reg [255:0] temp,cipher; 10 | 11 | Keygen keygen(key1, key2, key); 12 | 13 | always @(cipherText,key) 14 | begin 15 | #55 16 | cipher = cipherText; 17 | 18 | // First Round 19 | cipher[63:0] = cipher[63:0] ^ key2[63:0]; 20 | cipher[127:64] = cipher[127:64] ^ key2[63:0]; 21 | cipher[191:128] = cipher[191:128] ^ key2[63:0]; 22 | cipher[255:192] = cipher[255:192] ^ key2[63:0]; 23 | 24 | // Second Round 25 | temp[255:192] = cipher[63:0] ^ key1[63:0]; 26 | temp[63:0] = cipher[127:64]; 27 | temp[127:64] = cipher[191:128]; 28 | temp[191:128] =cipher[255:192]; 29 | 30 | // Third Round 31 | decipherText[62:0]=temp[63:1]; 32 | decipherText[63]=temp[0]; 33 | 34 | decipherText[126:64]=temp[127:65]; 35 | decipherText[127]=temp[64]; 36 | 37 | decipherText[190:128]=temp[191:129]; 38 | decipherText[191]=temp[128]; 39 | 40 | decipherText[254:192]=temp[255:193]; 41 | decipherText[255]=temp[192]; 42 | 43 | $display("after decryption"); 44 | $display("at time %0d decipher Text = %d\n",$time, decipherText); 45 | $display("plaintext = %0d", decipherText[247:0]); 46 | 47 | end 48 | 49 | 50 | endmodule 51 | 52 | -------------------------------------------------------------------------------- /LabTestPractice/2k11-12/Solution/Encrypt.v: -------------------------------------------------------------------------------- 1 | // Design Module for Encryption 2 | 3 | 4 | module Encrypt(cipherText, plainText , key); 5 | output reg [255:0] cipherText; 6 | input [247:0] plainText ; 7 | input [63:0] key; 8 | 9 | wire [255:0] paddedText; 10 | wire [63:0] key1,key2; 11 | reg [255:0] temp; 12 | 13 | Padd pd(paddedText, plainText); 14 | Keygen keygen(key1, key2, key); 15 | 16 | always @(paddedText , key) 17 | begin 18 | // First Round 19 | #25 20 | temp[63:1] = paddedText [62:0]; 21 | temp[0] = paddedText [63]; 22 | cipherText[63:0] = temp[63:0]; 23 | 24 | temp[63:1] = paddedText [126:64]; 25 | temp[0] = paddedText [127]; 26 | cipherText[127:64] = temp[63:0]; 27 | 28 | temp[63:1] = paddedText [190:128]; 29 | temp[0] = paddedText [191]; 30 | cipherText[191:128] = temp[63:0]; 31 | 32 | temp[63:1] = paddedText [254:192]; 33 | temp[0] = paddedText [255]; 34 | cipherText[255:192] = temp[63:0]; 35 | 36 | // Round Two 37 | temp[127:64] = cipherText[63:0]; 38 | temp[191:128] = cipherText[127:64]; 39 | temp[255:192] = cipherText[191:128]; 40 | temp[63:0] = cipherText[255:192] ^ key1[63:0]; 41 | 42 | 43 | // Round Three 44 | cipherText[63:0] = temp[63:0] ^ key2[63:0]; 45 | cipherText[127:64] = temp[127:64] ^ key2[63:0]; 46 | cipherText[191:128] = temp[191:128] ^ key2[63:0]; 47 | cipherText[255:192] = temp[255:192] ^ key2[63:0]; 48 | 49 | $display("after encryption"); 50 | $display("at time %0d cipher Text = %d\n",$time, cipherText); 51 | end 52 | 53 | endmodule 54 | -------------------------------------------------------------------------------- /LabTestPractice/2k11-12/Solution/Keygen.v: -------------------------------------------------------------------------------- 1 | // Design module for Key Generation 2 | 3 | module Keygen(key1,key2,key); 4 | output reg [63:0] key1,key2; 5 | input [63:0] key; 6 | 7 | wire [63:0] k1,k2; 8 | reg [63:0] left,right; 9 | 10 | ALU64bit alu1(k1,left,right,1'b1); 11 | ALU64bit alu2(k2,left,right,1'b0); 12 | 13 | initial 14 | begin 15 | #10 left = {{32{key[63]}},key[63:32]}; 16 | right = {{32{key[31]}},key[31:0]}; 17 | 18 | //$display("before key generation"); 19 | //$monitor("At time %0d left = %b right = %b",$time,plainText,left,right); 20 | 21 | #5 key1 = k1; 22 | key2 = k2; 23 | $display("after key generation"); 24 | $monitor("At time %0d key1 = %b \n\tkey2 = %b",$time,key1,key2); 25 | end 26 | 27 | endmodule 28 | 29 | -------------------------------------------------------------------------------- /LabTestPractice/2k11-12/Solution/Padding.v: -------------------------------------------------------------------------------- 1 | // Desing Module for Padding 2 | 3 | module Padd(paddedText,plainText); 4 | output reg [255:0] paddedText; 5 | input [247:0] plainText; 6 | 7 | 8 | initial 9 | begin 10 | 11 | // $display("before padding"); 12 | // $display("at time %0d padded text = %d\n",$time,paddedText); 13 | 14 | #5 paddedText[247:0] = plainText; 15 | paddedText[255:248] = 8'd248; 16 | 17 | $display("after padding"); 18 | $display("at time %0d padded text = %d\n",$time, paddedText); 19 | 20 | end 21 | 22 | endmodule 23 | -------------------------------------------------------------------------------- /LabTestPractice/2k11-12/file.v: -------------------------------------------------------------------------------- 1 | module encrypt( 2 | output [255:0] ct, 3 | input [255:0] pt, 4 | input [63:0] key 5 | ); 6 | endmodule 7 | 8 | module decrypt( 9 | output [255:0] ct, 10 | input [255:0] pt, 11 | input [63:0] key 12 | ); 13 | endmodule 14 | 15 | module padd( 16 | output [255:0] ct, 17 | input 18 | ); 19 | endmodule 20 | 21 | module keygen(); 22 | endmodule 23 | 24 | module alu64bit(); 25 | endmodule 26 | 27 | module algotest(); 28 | endmodule -------------------------------------------------------------------------------- /LabTestPractice/2k13-14/LabTest.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/SinghCoder/Icarus_Verilog/c326ccb1b1a354daaf6e61368712536428445de5/LabTestPractice/2k13-14/LabTest.pdf -------------------------------------------------------------------------------- /LabTestPractice/2k13-14/file.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/SinghCoder/Icarus_Verilog/c326ccb1b1a354daaf6e61368712536428445de5/LabTestPractice/2k13-14/file.v -------------------------------------------------------------------------------- /LabTestPractice/2k15-16/Labtest_prev.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/SinghCoder/Icarus_Verilog/c326ccb1b1a354daaf6e61368712536428445de5/LabTestPractice/2k15-16/Labtest_prev.pdf -------------------------------------------------------------------------------- /LabTestPractice/2k15-16/file.v: -------------------------------------------------------------------------------- 1 | module mux16to1( 2 | output [8:0] outp, 3 | input [3:0] x 4 | ); 5 | 6 | assign outp = 25*x; 7 | 8 | endmodule 9 | 10 | module adder_reg( 11 | output [12:0] y, 12 | input acc_rst1, 13 | input acc_rst2, 14 | input clock, 15 | input [8:0] muxVal 16 | ); 17 | 18 | reg [12:0] acc; 19 | initial 20 | acc = 13'b0; 21 | always @(posedge clock) begin 22 | // $display("acc_rst2:= ",acc_rst2); 23 | if(acc_rst1 == 1) 24 | acc = acc + {4'b0,muxVal}; 25 | else 26 | acc = acc; 27 | end 28 | 29 | always @(posedge acc_rst2 or negedge acc_rst2) 30 | acc = 13'b0; 31 | 32 | assign y = acc; 33 | 34 | endmodule 35 | 36 | module dff( 37 | output reg q, 38 | output reg qbar, 39 | input d, 40 | input clock, 41 | input reset 42 | ); 43 | 44 | always @(posedge clock or reset) begin 45 | $display("q:=",q); 46 | if(reset == 1) begin 47 | q = 0; 48 | qbar = 1; 49 | end 50 | else begin 51 | q = d; 52 | qbar = ~q; 53 | end 54 | 55 | end 56 | 57 | endmodule 58 | 59 | module acc_rst( 60 | output acc_rst1, 61 | output acc_rst2, 62 | input clock, 63 | input reset 64 | ); 65 | 66 | wire [3:0] qout; 67 | wire [3:0] qbarout; 68 | 69 | dff ff1(.q(qout[0]),.qbar(qbarout[0]), .d(qbarout[0]), .clock(clock) , .reset(reset)); 70 | dff ff2(.q(qout[1]),.qbar(qbarout[1]), .d(qbarout[1]), .clock(qout[0]), .reset(reset)); 71 | dff ff3(.q(qout[2]),.qbar(qbarout[2]), .d(qbarout[2]), .clock(qout[1]), .reset(reset)); 72 | dff ff4(.q(qout[3]),.qbar(qbarout[3]), .d(qbarout[3]), .clock(qout[2]), .reset(reset)); 73 | 74 | assign acc_rst1 = qout[2]; 75 | assign acc_rst2 = qout[3]; 76 | 77 | always @(posedge clock) begin 78 | $display("q := ",{qout[3],qout[2],qout[1],qout[0]}); 79 | end 80 | 81 | endmodule 82 | 83 | module intg( 84 | output [12:0] y, 85 | input reset, 86 | input [3:0] x, 87 | input clock 88 | ); 89 | 90 | wire accRst1, accRst2; 91 | acc_rst accRst(.clock(clock),.reset(reset),.acc_rst1(accRst1), .acc_rst2(accRst2)); 92 | wire [8:0] muxVal; 93 | mux16to1 mux(.x(x), .outp(muxVal)); 94 | adder_reg adderReg(.clock(clock), .acc_rst1(accRst1), .acc_rst2(accRst2), .muxVal(muxVal), .y(y)); 95 | 96 | endmodule 97 | 98 | module tb_intg(); 99 | 100 | reg reset,clock; 101 | reg [3:0] x; 102 | wire [12:0] y; 103 | 104 | initial begin 105 | clock = 1'b0; 106 | reset = 1'b1; 107 | x = 4'd0; 108 | #16 reset = 1'b0; 109 | #8 x = 4'd10; 110 | #16 x = 4'd5; 111 | #16 x = 4'd12; 112 | #16 x = 4'd1; 113 | 114 | #16 x = 4'd13; 115 | #16 x = 4'd7; 116 | #16 x = 4'd9; 117 | #16 x = 4'd2; 118 | 119 | #16 x = 4'd11; 120 | #16 x = 4'd5; 121 | #16 x = 4'd4; 122 | #16 x = 4'd2; 123 | #200 $finish; 124 | end 125 | always 126 | #8 clock = ~clock; 127 | initial begin 128 | $dumpfile("file.vcd"); 129 | $dumpvars; 130 | end 131 | 132 | intg circuit(.y(y), .reset(reset), .clock(clock), .x(x)); 133 | endmodule -------------------------------------------------------------------------------- /LabTestPractice/2k16-17/file.v: -------------------------------------------------------------------------------- 1 | /*ToDo: Solution is not working right now, correct it */ 2 | `define S0 2'b00 3 | `define S1 2'b01 4 | `define S2 2'b10 5 | `define S3 2'b11 6 | 7 | module bht( 8 | output [1:0] outp, 9 | input [1:0] inp, 10 | input [9:0] address, 11 | input clk, 12 | input write 13 | ); 14 | wire [1:0] outp; 15 | integer i; 16 | reg [1:0] bhtTable [0:1023]; 17 | initial begin 18 | for(i = 0; i < 1024; i = i+1) begin 19 | bhtTable[i] = 2'b0; 20 | end 21 | // outp = 2'b0; 22 | end 23 | 24 | always @(negedge clk) begin 25 | 26 | if(write == 1) 27 | bhtTable[address] = inp; 28 | end 29 | 30 | assign outp = bhtTable[address]; 31 | // $display("address = %b, bhtTable[address] = %b",address, bhtTable[address]); 32 | endmodule 33 | 34 | module mux( 35 | output [1:0] outp, 36 | input [1:0] inp1, 37 | input [1:0] inp2, 38 | input sel 39 | ); 40 | 41 | reg [1:0] outp; 42 | always @* begin 43 | if(sel) 44 | outp = inp2; 45 | else 46 | outp = inp1; 47 | end 48 | 49 | endmodule 50 | 51 | module predictor( 52 | output [1:0] nextState, 53 | input taken, 54 | input clock 55 | ); 56 | 57 | reg [1:0] currState, nextState; 58 | 59 | initial 60 | currState = `S0; 61 | 62 | always @(posedge clock) begin 63 | case({currState,taken}) 64 | 65 | {`S0,1'b0} : nextState <= `S0; 66 | {`S0,1'b1} : nextState <= `S1; 67 | 68 | {`S1,1'b0} : nextState <= `S0; 69 | {`S1,1'b1} : nextState <= `S3; 70 | 71 | {`S2,1'b0} : nextState <= `S0; 72 | {`S2,1'b1} : nextState <= `S3; 73 | 74 | {`S3,1'b0} : nextState <= `S2; 75 | {`S3,1'b1} : nextState <= `S3; 76 | 77 | default : begin 78 | $display("insisde default case.., currState: %d, taken : %b", currState, taken); 79 | nextState <= `S0; 80 | end 81 | endcase 82 | 83 | currState <= nextState; 84 | end 85 | 86 | endmodule 87 | 88 | module intg( 89 | output predn, 90 | input [9:0] address, 91 | input taken, 92 | input clock 93 | ); 94 | reg predn; 95 | initial 96 | predn = 1'b0; 97 | 98 | wire [1:0] bhtOut1, bhtOut2; 99 | wire [1:0] nextState; 100 | wire [1:0] branchPredn; 101 | 102 | reg writeBht1, writeBht2; 103 | 104 | initial begin 105 | writeBht1 = 1'b0; 106 | writeBht2 = 1'b0; 107 | end 108 | // writeBht2 = ~writeBht1; 109 | 110 | // assign writeBht1 = ~taken; 111 | 112 | bht bht1(.outp(bhtOut1), .inp(nextState), .address(address), .write(writeBht1), .clk(clock)); 113 | bht bht2(.outp(bhtOut2), .inp(nextState), .address(address), .write(writeBht2), .clk(clock)); 114 | 115 | mux mux1(.outp(branchPredn), .inp1(bhtOut1), .inp2(bhtOut2), .sel(predn)); 116 | predictor p1(.nextState(nextState), .taken(taken), .clock(clock)); 117 | 118 | always @(branchPredn or nextState) begin 119 | case (branchPredn) 120 | 121 | `S0 : begin 122 | $display("S0: Not taken"); 123 | predn = 1'b0; 124 | writeBht1 = 1'b1; 125 | #10 writeBht1 = 1'b0; 126 | end 127 | 128 | `S1 : begin 129 | $display("S1: Not taken"); 130 | predn = 1'b0; 131 | writeBht1 = 1'b1; 132 | #10 writeBht1 = 1'b0; 133 | end 134 | 135 | `S2 : begin 136 | $display("S2: Taken"); 137 | predn = 1'b1; 138 | writeBht2 = 1'b1; 139 | #10 writeBht2 = 1'b0; 140 | end 141 | 142 | `S3 : begin 143 | $display("S3: Taken"); 144 | predn = 1'b1; 145 | writeBht2 = 1'b1; 146 | #10 writeBht2 = 1'b0; 147 | end 148 | 149 | 150 | default : begin 151 | $display("Not taken"); 152 | predn = 1'b0; 153 | end 154 | endcase 155 | 156 | end 157 | 158 | endmodule 159 | 160 | module tb_intg(); 161 | 162 | initial begin 163 | $dumpfile("file.vcd"); 164 | $dumpvars; 165 | end 166 | 167 | reg [9:0] address; 168 | wire prediction; 169 | reg actualOutcome; 170 | reg clock; 171 | 172 | initial begin 173 | clock = 1'b0; 174 | actualOutcome = 1'b0; 175 | end 176 | 177 | always 178 | #5 clock = ~clock; 179 | 180 | intg mod(prediction, address, actualOutcome, clock); 181 | 182 | initial begin 183 | address = 10'b0011110000; 184 | #10 actualOutcome = 1'b0; 185 | #10 actualOutcome = 1'b1; 186 | #10 actualOutcome = 1'b1; 187 | #10 actualOutcome = 1'b1; 188 | #10 actualOutcome = 1'b0; 189 | #50 $finish; 190 | end 191 | 192 | endmodule 193 | -------------------------------------------------------------------------------- /LabTestPractice/2k16-17/last_year_paper.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/SinghCoder/Icarus_Verilog/c326ccb1b1a354daaf6e61368712536428445de5/LabTestPractice/2k16-17/last_year_paper.pdf -------------------------------------------------------------------------------- /LabTestPractice/2k17-18/LabTest_part1.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/SinghCoder/Icarus_Verilog/c326ccb1b1a354daaf6e61368712536428445de5/LabTestPractice/2k17-18/LabTest_part1.jpg -------------------------------------------------------------------------------- /LabTestPractice/2k17-18/Labtest_part2.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/SinghCoder/Icarus_Verilog/c326ccb1b1a354daaf6e61368712536428445de5/LabTestPractice/2k17-18/Labtest_part2.jpg -------------------------------------------------------------------------------- /LabTestPractice/2k17-18/counter_3bit.v: -------------------------------------------------------------------------------- 1 | `ifndef COUNTER_3BIT 2 | `define COUNTER_3BIT 3 | `include "tff.v" 4 | module counter_3bit( 5 | output [2:0] q, 6 | input clock, 7 | input clear 8 | ); 9 | 10 | reg [2:0] q; 11 | wire inpff1, inpff3; 12 | wire [2:0] outpff; 13 | assign inpff1 = 1'b1; 14 | and( inpff3, outpff[1], outpff[0]); 15 | 16 | tff ff1(.q(outpff[0]), .t(inpff1), .clock(clock), .clear(clear)); 17 | tff ff2(.q(outpff[1]), .t(outpff[0]), .clock(clock), .clear(clear)); 18 | tff ff3(.q(outpff[2]), .t(inpff3), .clock(clock), .clear(clear)); 19 | 20 | always @(posedge clock or clear) begin 21 | 22 | if(clear) 23 | q = 4'b0; 24 | else 25 | q = outpff; 26 | 27 | end 28 | 29 | endmodule 30 | `endif 31 | -------------------------------------------------------------------------------- /LabTestPractice/2k17-18/counter_4bit.v: -------------------------------------------------------------------------------- 1 | `ifndef COUTNER_4BIT 2 | `define COUNTER_4BIT 3 | `include "tff.v" 4 | module counter_4bit( 5 | output [3:0] q, 6 | input clock, 7 | input clear 8 | ); 9 | 10 | reg [3:0]q; 11 | initial 12 | q = 4'b0; 13 | 14 | wire inpff1, inpff3, inpff4; 15 | wire [3:0] outpff; 16 | assign inpff1 = 1'b1; 17 | and( inpff3, outpff[1], outpff[0]); 18 | and( inpff4, outpff[2], inpff3); 19 | 20 | tff ff1(.q(outpff[0]), .t(inpff1), .clock(clock), .clear(clear)); 21 | tff ff2(.q(outpff[1]), .t(outpff[0]), .clock(clock), .clear(clear)); 22 | tff ff3(.q(outpff[2]), .t(inpff3), .clock(clock), .clear(clear)); 23 | tff ff4(.q(outpff[3]), .t(inpff4), .clock(clock), .clear(clear)); 24 | 25 | always @(posedge clock or clear) begin 26 | 27 | if(clear) 28 | q = 4'b0; 29 | else 30 | q = outpff; 31 | 32 | end 33 | 34 | endmodule 35 | `endif 36 | -------------------------------------------------------------------------------- /LabTestPractice/2k17-18/dff_async_clear.v: -------------------------------------------------------------------------------- 1 | `ifndef DFF_ASYNC_CLEAR 2 | `define DFF_ASYNC_CLEAR 3 | module dff_async_clear( 4 | output q, 5 | input d, 6 | input clock, 7 | input clear 8 | ); 9 | 10 | reg q; 11 | 12 | always @(posedge clock or clear) begin 13 | 14 | if(clear) 15 | q = 0; 16 | else 17 | q = d; 18 | 19 | end 20 | 21 | endmodule 22 | `endif -------------------------------------------------------------------------------- /LabTestPractice/2k17-18/dff_sync_clear.v: -------------------------------------------------------------------------------- 1 | `ifndef DFF_SYNC_CLEAR 2 | `define DFF_SYNC_CLEAR 3 | module dff_sync_clear( 4 | output q, 5 | input d, 6 | input clear, 7 | input clock 8 | ); 9 | 10 | reg q; 11 | always @(clock) begin 12 | 13 | if(clear) 14 | q = 0; 15 | else 16 | q = d; 17 | 18 | end 19 | 20 | endmodule 21 | `endif -------------------------------------------------------------------------------- /LabTestPractice/2k17-18/intg.v: -------------------------------------------------------------------------------- 1 | `ifndef INTG 2 | `define INTG 3 | `include "muxLarge.v" 4 | `include "tff.v" 5 | `include "counter_4bit.v" 6 | `include "counter_3bit.v" 7 | `include "memory.v" 8 | 9 | module intg( 10 | output wf, 11 | input clear, 12 | input clock 13 | ); 14 | 15 | wire [2:0] outp_cnt3bit; 16 | wire [3:0] outp_cnt4bit; 17 | wire clk_cnt4bit; 18 | // wire [3:0] value; 19 | 20 | // assign value = outp_cnt4bit; 21 | 22 | and(clk_cnt4bit, outp_cnt3bit[0], outp_cnt3bit[1], outp_cnt3bit[2]); 23 | memory mem(); 24 | muxLarge mux(.outp(wf), .inp(mem.membyte[outp_cnt4bit]), .sel(outp_cnt3bit)); 25 | counter_4bit cnt4bit(.clock(clk_cnt4bit), .clear(clear), .q(outp_cnt4bit)); 26 | counter_3bit cnt3bit(.clock(clock), .clear(clear), .q(outp_cnt3bit)); 27 | endmodule 28 | 29 | `endif -------------------------------------------------------------------------------- /LabTestPractice/2k17-18/memory.v: -------------------------------------------------------------------------------- 1 | `ifndef MEMORY 2 | `define MEMORY 3 | module memory(); 4 | reg [7:0] membyte [0:15]; 5 | integer i; 6 | initial begin 7 | for (i = 0; i < 16; i = i+1) begin 8 | 9 | if( i%2 == 0) 10 | membyte[i] = 8'b1100_1100; 11 | else 12 | membyte[i] = 8'b1010_1010; 13 | 14 | end 15 | end 16 | endmodule 17 | `endif -------------------------------------------------------------------------------- /LabTestPractice/2k17-18/muxLarge.v: -------------------------------------------------------------------------------- 1 | `ifndef MUX_LARGE 2 | `define MUX_LARGE 3 | `include "muxSmall.v" 4 | 5 | module muxLarge( 6 | output outp, 7 | input [7:0] inp, 8 | input [2:0] sel 9 | ); 10 | 11 | wire [3:0] layer1Outs; 12 | wire [1:0] layer2Outs; 13 | genvar i; 14 | 15 | generate for (i = 0; i<4; i = i+1) begin : layer1 16 | muxSmall mux(.outp(layer1Outs[i]), .inp({inp[2*i+1],inp[2*i]}) , .sel(sel[0])); 17 | end 18 | endgenerate 19 | 20 | generate for (i = 0; i<2; i = i+1) begin : layer2 21 | muxSmall mux(.outp(layer2Outs[i]), .inp({layer1Outs[2*i+1], layer1Outs[2*i]}) , .sel(sel[1])); 22 | end 23 | endgenerate 24 | 25 | generate for (i = 0; i<1; i= i+1) begin : layer3 26 | muxSmall mux(.outp(outp), .inp({layer2Outs[2*i+1], layer2Outs[2*i]}) , .sel(sel[2])); 27 | end 28 | endgenerate 29 | 30 | endmodule 31 | 32 | `endif -------------------------------------------------------------------------------- /LabTestPractice/2k17-18/muxSmall.v: -------------------------------------------------------------------------------- 1 | `ifndef MUX_SMALL 2 | `define MUX_SMALL 3 | 4 | module muxSmall( 5 | output outp, 6 | input [1:0] inp, 7 | input sel 8 | ); 9 | 10 | wire selBar; 11 | not(selBar, sel); 12 | 13 | wire tmp1, tmp2; 14 | and(tmp1, selBar, inp[0]); 15 | and(tmp2, sel, inp[1]); 16 | or(outp, tmp1, tmp2); 17 | 18 | endmodule 19 | `endif -------------------------------------------------------------------------------- /LabTestPractice/2k17-18/tb_dff_sync.v: -------------------------------------------------------------------------------- 1 | `include "dff_async_clear.v" 2 | module tb_dff_sync(); 3 | 4 | reg clock, d, clear; 5 | wire q; 6 | 7 | dff_async_clear dff(.q(q), .d(d), .clear(clear), .clock(clock)); 8 | 9 | initial begin 10 | $dumpfile("tb_dff.vcd"); 11 | $dumpvars; 12 | end 13 | 14 | initial 15 | clock = 1'b0; 16 | 17 | always 18 | #5 clock = ~clock; 19 | 20 | initial begin 21 | 22 | d = 1'b0; 23 | clear = 1'b1; 24 | #10 d = 1'b1; 25 | #10 d = 1'b0; 26 | #10 clear = 1'b0; 27 | #10 d = 1'b1; 28 | #10 d = 1'b0; 29 | #10 $finish; 30 | end 31 | 32 | endmodule 33 | -------------------------------------------------------------------------------- /LabTestPractice/2k17-18/tb_intg.v: -------------------------------------------------------------------------------- 1 | `include "intg.v" 2 | `timescale 1ms/1ns 3 | module tb_intg(); 4 | 5 | initial begin 6 | $dumpfile("tb_intg.vcd"); 7 | $dumpvars; 8 | end 9 | 10 | reg clear, clock; 11 | wire wf; 12 | 13 | intg mod(.wf(wf), .clear(clear), .clock(clock)); 14 | 15 | initial 16 | clock = 1'b0; 17 | always 18 | #0.5 clock = ~clock; 19 | 20 | initial begin 21 | clear = 1'b1; 22 | #1 clear = 1'b0; 23 | #1000 $finish; 24 | end 25 | 26 | // initial 27 | // $monitor("Main := clock = %b, clear = %b, wf = %b \n Cntr3bit := clock = %b, q = %d \n Cntr4bit := clock = %b, q = %d \n MuxLarge := input = %b, sel = %d, output = %b\n\n",clock, clear, wf, mod.cnt3bit.clock, mod.cnt3bit.q,mod.cnt4bit.clock, mod.cnt4bit.q,mod.mux.inp,mod.mux.sel, mod.mux.outp); 28 | 29 | endmodule -------------------------------------------------------------------------------- /LabTestPractice/2k17-18/tff.v: -------------------------------------------------------------------------------- 1 | `ifndef TFF 2 | `define TFF 3 | module tff( 4 | output q, 5 | input t, 6 | input clock, 7 | input clear 8 | ); 9 | 10 | reg q; 11 | 12 | always @(posedge clock , clear) begin 13 | 14 | if(clear) 15 | q = 1'b0; 16 | else 17 | if( t==1 ) 18 | q = ~q; 19 | else 20 | q = q; 21 | 22 | end 23 | 24 | endmodule 25 | `endif -------------------------------------------------------------------------------- /LabTestPractice/2k18-19/2k18-19_1..jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/SinghCoder/Icarus_Verilog/c326ccb1b1a354daaf6e61368712536428445de5/LabTestPractice/2k18-19/2k18-19_1..jpg -------------------------------------------------------------------------------- /LabTestPractice/2k18-19/2k18-19_2.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/SinghCoder/Icarus_Verilog/c326ccb1b1a354daaf6e61368712536428445de5/LabTestPractice/2k18-19/2k18-19_2.jpg -------------------------------------------------------------------------------- /LabTestPractice/2k18-19/file.v: -------------------------------------------------------------------------------- 1 | `timescale 1ms/1ns 2 | /*Behavioral*/ 3 | module dff( 4 | output q, 5 | input d, 6 | input clk, 7 | input reset, 8 | input set 9 | ); 10 | 11 | reg q; 12 | 13 | initial 14 | q = 1'b0; 15 | 16 | always @(posedge clk or set) begin 17 | case ({reset, set}) 18 | 2'b00 : q <= d; 19 | 2'b01 : q <= 1'b1; 20 | 2'b10 : q <= 1'b0; 21 | 2'b11 : q <= 1'bz; 22 | endcase 23 | end 24 | 25 | endmodule 26 | 27 | module tff( 28 | output q, 29 | input t, 30 | input clk, 31 | input reset 32 | ); 33 | reg q; 34 | initial 35 | q <= 1'b0; 36 | always @(posedge clk) begin 37 | if(reset) 38 | q <= 1'b0; 39 | else 40 | if( t == 0) 41 | q <= q; 42 | else 43 | q <= ~q; 44 | end 45 | 46 | endmodule 47 | 48 | module counter4bit( 49 | output [3:0] q, 50 | input clock, 51 | input rst, 52 | input en 53 | ); 54 | wire clk; 55 | wire [3:0] t; 56 | assign t[0] = 1'b1; 57 | assign t[1] = q[0]; 58 | and(t[2], q[1], q[0]); 59 | and(t[3], q[2], t[2]); 60 | 61 | assign clk = clock & en; 62 | 63 | tff ff1(q[0], t[0], clk, rst); 64 | tff ff2(q[1], t[1], clk, rst); 65 | tff ff3(q[2], t[2], clk, rst); 66 | tff ff4(q[3], t[3], clk, rst); 67 | 68 | endmodule 69 | 70 | /*Gate Lvl*/ 71 | module ctrlLogic( 72 | output t0, 73 | output t1, 74 | output t2, 75 | input clk, 76 | input s, 77 | input z, 78 | input x, 79 | input set 80 | ); 81 | // reg t0; 82 | // initial 83 | // t0 = 1'b1; 84 | wire dt0, dt1, dt2, t0, t1, t2; 85 | wire sbar, zbar, xbar; 86 | wire t0and1, t0and2, t0or1; 87 | wire t1and1, t1and2, t1and3, t1or1, t1or2; 88 | wire t2and1, t2and2, t2or1; 89 | 90 | not(sbar,s); 91 | not(zbar,z); 92 | not(xbar,x); 93 | 94 | and(t0and1, t0, sbar); 95 | and(t0and2, t2, z); 96 | or(t0or1, t0and1, t0and2); 97 | 98 | and(t1and1, t0, s); 99 | and(t1and2, t2, xbar, zbar); 100 | and(t1and3, t1, xbar); 101 | or(t1or1, t1and1, t1and2); 102 | or(t1or2, t1or1, t1and3); 103 | 104 | and(t2and1, t1, x); 105 | and(t2and2, t2, x, zbar); 106 | or(t2or1, t2and1, t2and2); 107 | 108 | dff ff1(t0,t0or1,clk, 1'b0, set); 109 | dff ff2(t1,t1or2,clk, 1'b0, 1'b0); 110 | dff ff3(t2,t2or1,clk, 1'b0, 1'b0); 111 | 112 | endmodule 113 | 114 | module intg( 115 | output [3:0] q, 116 | output g, 117 | input s, 118 | input xx, 119 | input clk, 120 | input set 121 | ); 122 | 123 | wire rst; 124 | wire en; 125 | wire [2:0] t; 126 | wire zz; 127 | 128 | assign rst = t[0] & s; 129 | assign en = (t[1] & xx) | (t[2] & (~zz) & xx); 130 | 131 | wire [3:0] q; 132 | counter4bit ctr(q, clk, rst, en); 133 | 134 | assign zz = q[0] & q[1] & q[2] & q[3]; 135 | ctrlLogic ctrl(t[0], t[1], t[2], clk, s, zz, xx, set); 136 | 137 | wire d; 138 | assign d = zz & t[2]; 139 | dff ff(g, d, clk, rst, 1'b0); 140 | 141 | endmodule 142 | 143 | module tb_intg(); 144 | 145 | reg clk; 146 | initial 147 | clk = 1'b0; 148 | always 149 | #0.5 clk = ~clk; 150 | 151 | reg s; 152 | reg xx; 153 | reg set; 154 | wire [3:0] q; 155 | wire g; 156 | 157 | intg mod(q, g, s, xx, clk, set); 158 | 159 | initial begin 160 | set = 1'b1; 161 | s = 1'b0; 162 | xx = 1'b0; 163 | #5 s = 1'b1; 164 | set = 1'b0; 165 | xx = 1'b1; 166 | #30 xx = 1'b0; 167 | #100 $finish; 168 | 169 | end 170 | initial begin 171 | $dumpfile("file.vcd"); 172 | $dumpvars; 173 | end 174 | 175 | initial begin 176 | $monitor($time,"s = %b, x = %b, q = %d, g = %b", s, xx, q, g); 177 | end 178 | 179 | endmodule 180 | -------------------------------------------------------------------------------- /LabTestPractice/2k19-20/2k19_20.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/SinghCoder/Icarus_Verilog/c326ccb1b1a354daaf6e61368712536428445de5/LabTestPractice/2k19-20/2k19_20.pdf -------------------------------------------------------------------------------- /LabTestPractice/2k19-20/file.v: -------------------------------------------------------------------------------- 1 | /* 2 | Name : Harpinder Jot Singh 3 | ID : 2017A7PS0057P 4 | */ 5 | `timescale 1ms/1ns 6 | module MUX_2x1( 7 | output E, 8 | input C, 9 | input D, 10 | input F 11 | ); 12 | 13 | assign E = F ? D : C; 14 | 15 | endmodule 16 | 17 | module MUX_8x1( 18 | output O, 19 | input [7:0] E, 20 | input [2:0] Q 21 | ); 22 | 23 | assign O = Q[2] ? 24 | (Q[1] ? 25 | ( (Q[0] ? (E[7]) : (E[6]) ) ) 26 | : ( (Q[0] ? (E[5]) : (E[4]) )) ) 27 | : (Q[1] ? 28 | ( (Q[0] ? (E[3]) : (E[2]) )) 29 | : ( (Q[0] ? (E[1]) : (E[0]) ))); 30 | 31 | endmodule 32 | 33 | module MUX_ARRAY( 34 | output [7:0] E, 35 | input [7:0] C, 36 | input [7:0] D, 37 | input [7:0] F 38 | ); 39 | 40 | //wire ground = 1'b0; 41 | 42 | genvar i; 43 | 44 | generate for(i = 0; i < 8; i = i+1) begin :muxarr 45 | 46 | MUX_2x1 mux( E[i], D[i], C[i], F[i] ); 47 | 48 | end 49 | endgenerate 50 | 51 | endmodule 52 | 53 | module COUNTER_3BIT( 54 | output [2:0] Q, 55 | input CLEAR, 56 | input CLK 57 | ); 58 | 59 | reg [2:0] Q; 60 | 61 | initial 62 | Q = 3'b0; 63 | 64 | always @(posedge CLK) begin 65 | Q <= Q + 1; 66 | end 67 | 68 | always @(CLEAR) 69 | if(CLEAR) 70 | Q <= 3'b0; 71 | 72 | 73 | 74 | endmodule 75 | 76 | 77 | 78 | module DECODER( 79 | 80 | output [7:0] B, 81 | input EN, 82 | input [2:0] A 83 | 84 | ); 85 | reg [7:0] B; 86 | always @(A) begin 87 | if(EN) begin 88 | case(A) 89 | 90 | 3'd0 : B = 8'b0000_0001; 91 | 3'd1 : B = 8'b0000_0010; 92 | 3'd2 : B = 8'b0000_0100; 93 | 3'd3 : B = 8'b0000_1000; 94 | 95 | 3'd4 : B = 8'b0001_0000; 96 | 3'd5 : B = 8'b0010_0000; 97 | 3'd6 : B = 8'b0100_0000; 98 | 3'd7 : B = 8'b1000_0000; 99 | 100 | endcase 101 | end 102 | end 103 | 104 | 105 | endmodule 106 | 107 | 108 | 109 | 110 | module MEMORY( 111 | 112 | output [7:0] G, 113 | input [2:0] A 114 | 115 | ); 116 | 117 | reg [7:0] memory[0:7]; 118 | reg [7:0] G; 119 | 120 | always @(A) begin 121 | 122 | case(A) 123 | 124 | 3'd0 : G = memory[0]; 125 | 3'd1 : G = memory[1]; 126 | 3'd2 : G = memory[2]; 127 | 3'd3 : G = memory[3]; 128 | 129 | 3'd4 : G = memory[4]; 130 | 3'd5 : G = memory[5]; 131 | 3'd6 : G = memory[6]; 132 | 3'd7 : G = memory[7]; 133 | 134 | endcase 135 | end 136 | 137 | 138 | integer i; 139 | 140 | initial begin 141 | 142 | memory[0] = 8'h01; 143 | memory[1] = 8'h03; 144 | memory[2] = 8'h07; 145 | memory[3] = 8'h0F; 146 | 147 | memory[4] = 8'h1F; 148 | memory[5] = 8'h3F; 149 | memory[6] = 8'h7F; 150 | memory[7] = 8'hFF; 151 | 152 | end 153 | 154 | endmodule 155 | 156 | 157 | 158 | module TOP_MODULE( 159 | 160 | output O, 161 | input CLK, 162 | input CLEAR, 163 | input [2:0] S 164 | ); 165 | wire [2:0] Q; 166 | 167 | COUNTER_3BIT cnt(Q, CLEAR, CLK); 168 | 169 | wire [7:0] B; 170 | 171 | DECODER dec(B, 1'b1, Q); 172 | 173 | wire [7:0] G; 174 | MEMORY mem(G, S); 175 | 176 | wire [7:0] E; 177 | wire [7:0] GROUND = 8'b0; 178 | MUX_ARRAY arr(E, B,GROUND, G); 179 | 180 | MUX_8x1 mux(O, E, Q); 181 | 182 | 183 | 184 | endmodule 185 | 186 | 187 | module TB_TOPMODULE(); 188 | 189 | initial begin 190 | $dumpfile("file.vcd"); 191 | $dumpvars; 192 | end 193 | 194 | 195 | wire O; 196 | reg CLK; 197 | reg CLEAR; 198 | reg [2:0] S; 199 | 200 | TOP_MODULE mod(O, CLK, CLEAR, S); 201 | 202 | always 203 | #0.5 CLK = ~CLK; 204 | 205 | initial begin 206 | CLK = 1'b0; 207 | S = 3'b0; 208 | CLEAR = 1'b1; 209 | #1 CLEAR = 1'b0; 210 | #100 $finish; 211 | end 212 | 213 | always 214 | #8 S = S+1; 215 | 216 | initial 217 | $monitor($time," , CLK = %b, S = %b, CLEAR = %b, O = %b", CLK, S, CLEAR, O); 218 | endmodule -------------------------------------------------------------------------------- /LabTestPractice/2k19-20/markingScheme.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/SinghCoder/Icarus_Verilog/c326ccb1b1a354daaf6e61368712536428445de5/LabTestPractice/2k19-20/markingScheme.jpg -------------------------------------------------------------------------------- /LabTestPractice/2k20-21/Lab Test Sol+Marking Scheme.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/SinghCoder/Icarus_Verilog/c326ccb1b1a354daaf6e61368712536428445de5/LabTestPractice/2k20-21/Lab Test Sol+Marking Scheme.pdf -------------------------------------------------------------------------------- /LabTestPractice/2k20-21/Lab Test.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/SinghCoder/Icarus_Verilog/c326ccb1b1a354daaf6e61368712536428445de5/LabTestPractice/2k20-21/Lab Test.jpg -------------------------------------------------------------------------------- /LabTestPractice/mealy.v: -------------------------------------------------------------------------------- 1 | `define S0 2'b00 2 | `define S1 2'b01 3 | `define S2 2'b10 4 | 5 | module mealy( 6 | output outp, 7 | input inp, 8 | input reset, 9 | input clock 10 | ); 11 | 12 | reg [1:0] state; 13 | reg outp; 14 | 15 | always @(posedge clock or reset) begin 16 | 17 | if( reset ) begin 18 | state <= `S0; 19 | outp <= 1'b0; 20 | end 21 | 22 | else begin 23 | case (state) 24 | 25 | `S0 : begin 26 | state <= (inp == 1) ? `S1 : `S2; 27 | outp <= (inp == 1) ? 1'b0 : 1'b0; 28 | end 29 | 30 | `S1 : begin 31 | state <= (inp == 1) ? `S0 : `S2; 32 | outp <= (inp == 1) ? 1'b1 : 1'b0; 33 | end 34 | 35 | `S2 : begin 36 | state <= (inp == 1) ? `S1 : `S0; 37 | outp <= (inp == 1) ? 1'b0 : 1'b1; 38 | end 39 | 40 | default : begin 41 | state <= `S0; 42 | outp<= 1'b0; 43 | end 44 | endcase 45 | end 46 | 47 | end 48 | 49 | endmodule -------------------------------------------------------------------------------- /LabTestPractice/tb_mealy.v: -------------------------------------------------------------------------------- 1 | `include "mealy.v" 2 | module tb_mealy(); 3 | 4 | initial begin 5 | $dumpfile("tb_mealy.vcd"); 6 | $dumpvars; 7 | end 8 | 9 | reg clock; 10 | wire outp; 11 | reg inp, reset; 12 | 13 | initial 14 | clock = 1'b1; 15 | 16 | always 17 | #5 clock = ~clock; 18 | 19 | mealy m1(.reset(reset), .clock(clock), .inp(inp), .outp(outp)); 20 | 21 | initial begin 22 | 23 | reset <= 1'b1; 24 | inp <= 1'b0; 25 | #10 reset <= 1'b0; 26 | #10 inp <= 1'b1; 27 | #10 inp <= 1'b1; 28 | #10 inp <= 1'b0; 29 | #10 inp <= 1'b0; 30 | #10 $finish; 31 | end 32 | 33 | endmodule -------------------------------------------------------------------------------- /PracticeQuestions/Lab1_2/README.md: -------------------------------------------------------------------------------- 1 | # Practice Questions 2 | 3 | For the following questions, write the errors/warnings in the code. 4 | 5 | 1. Question 1 6 | 7 | ```verilog 8 | module bitwise_or(a, b, c); 9 | input[3:0] a,b; 10 | output[3:0] c; 11 | reg [3:0] c; 12 | assign c = a | b; 13 | endmodule 14 | ``` 15 | 16 | 2. Question 2 17 | 18 | ```verilog 19 | module and_gate(ina, inb, out); 20 | input ina; 21 | input inb; 22 | output out; 23 | always @(ina or inb) 24 | begin 25 | if(ina == 1) 26 | out = inb; 27 | else 28 | out = ina; 29 | end 30 | endmodule 31 | ``` 32 | 33 | 3. Question 3 34 | 35 | ```verilog 36 | module or_gate(ina, inb, out); 37 | input ina; 38 | input inb; 39 | output out; 40 | if(ina == 1) 41 | out = 1; 42 | else 43 | out = inb; 44 | endmodule 45 | ``` 46 | 47 | 4. Question 4 48 | 49 | ```verilog 50 | module adder(ina, inb, out); 51 | input [3:0] ina; 52 | input [3:0] inb; 53 | output [3:0] out; 54 | out = ina + inb; 55 | endmodule 56 | 57 | module tb_test(); 58 | reg a, b, c; 59 | adder (a, b, c); 60 | initial 61 | begin 62 | #0 a = 4'b0000; b = 4'b0001; 63 | #5 a = 4'b0010; b = 4'b0001; 64 | #10 a = 4'b1111; b = 4'b0001; 65 | #15 $finish; 66 | end 67 | 68 | $monitor("a = %b, b = %b, c = %b", a, b, c); 69 | endmodule 70 | ``` -------------------------------------------------------------------------------- /PracticeQuestions/Lab1_2/README.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/SinghCoder/Icarus_Verilog/c326ccb1b1a354daaf6e61368712536428445de5/PracticeQuestions/Lab1_2/README.pdf -------------------------------------------------------------------------------- /PracticeQuestions/Lab1_2/Solutions.md: -------------------------------------------------------------------------------- 1 | # Solutions 2 | 3 | 1. Solution 1 4 | 5 | ```verilog 6 | module bitwise_or(a, b, c); 7 | input[3:0] a,b; 8 | output[3:0] c; 9 | reg [3:0] c; // output is declared as reg and then assigned using assign 10 | assign c = a | b; 11 | // to correct it, either remove line reg [3:0] c; or remove assign keyword, and make this assignment inside an always block 12 | /* 13 | input[3:0] a,b; 14 | output[3:0] c; 15 | assign c = a | b; 16 | */ 17 | /* 18 | input[3:0] a,b; 19 | output[3:0] c; 20 | reg [3:0] c; 21 | always @(a or b) 22 | c = a | b; 23 | */ 24 | endmodule 25 | ``` 26 | 27 | 2. Solution 2 28 | 29 | ```verilog 30 | module and_gate(ina, inb, out); 31 | input ina; 32 | input inb; 33 | output out; // the out signal is assigned inside an assign block without being declared as reg, declare it as a reg 34 | always @(ina or inb) 35 | begin 36 | if(ina == 1) 37 | out = inb; 38 | else 39 | out = ina; 40 | end 41 | endmodule 42 | ``` 43 | 44 | 3. Solution 3 45 | 46 | ```verilog 47 | module or_gate(ina, inb, out); 48 | input ina; 49 | input inb; 50 | output out; // declare it as reg 51 | if(ina == 1) // put the if-else block inside an always block 52 | out = 1; 53 | else 54 | out = inb; 55 | endmodule 56 | ``` 57 | 58 | 4. Solution 4 59 | 60 | ```verilog 61 | module adder(ina, inb, out); 62 | input [3:0] ina; 63 | input [3:0] inb; 64 | output [3:0] out; 65 | out = ina + inb; 66 | endmodule 67 | 68 | module tb_test(); 69 | reg a, b, c; // inputs and output are of 4 bit, passing 1 bit here 70 | // declare c as a wire instead of reg 71 | adder (a, b, c); // missing a name for module instance 72 | initial 73 | begin 74 | #0 a = 4'b0000; b = 4'b0001; 75 | #5 a = 4'b0010; b = 4'b0001; 76 | #10 a = 4'b1111; b = 4'b0001; 77 | #15 $finish; 78 | end 79 | 80 | $monitor("a = %b, b = %b, c = %b", a, b, c); // put monitor statement inside an initial block 81 | endmodule 82 | ``` 83 | -------------------------------------------------------------------------------- /PracticeQuestions/Lab1_2/Solutions.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/SinghCoder/Icarus_Verilog/c326ccb1b1a354daaf6e61368712536428445de5/PracticeQuestions/Lab1_2/Solutions.pdf -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # Verilog Snippets and Notes 2 | 3 | A host for some Verilog-snippets written during Lab Sessions of **Computer Architecture** Course at **BITS Pilani**. 4 | 5 | ***Consider giving it a ☆ if the repo helps you in any way*** 6 | 7 | ## Running a file 8 | 9 | - Compile the verilog file (one with.v extension) using following command 10 | 11 | ```verilog 12 | iverilog -o filename.vvp filename.v 13 | ``` 14 | 15 | - To see output using $monitor statements run following command 16 | 17 | ```verilog 18 | vvp filename.vvp 19 | ``` 20 | 21 | - To get graphical waveform output, make sure to add following lines in every test branch 22 | 23 | ```verilog 24 | initial 25 | begin 26 | $dumpfile("filename.vcd"); 27 | $dumpvars; 28 | end 29 | ``` 30 | 31 | - To see graphical waveform output 32 | 33 | ```verilog 34 | gtkwave filename.vcd 35 | ``` 36 | 37 | - To include a header file in your program 38 | 39 | ```verilog 40 | `include "modulename.v" 41 | ``` 42 | 43 | ## Most Common Mistakes in Verilog 44 | 45 | 1. All keywords should be in lower case. 46 | 2. Upper case and lower case are distinct in verilog, it is case sensitive 47 | 3. Make sure that the wires are properly declared before usage. 48 | 4. Unwanted spaces will put you in trouble ex. endmodule doesn’t have any space in between. 49 | 5. Module declaration is a statement terminate it with a semicolon. 50 | 6. Module name can’t start with a number and can’t have a special charcters in it. 51 | 7. The output ‘x’ indicates that the signal is still unkown and being evaluated. 52 | 8. In combinational circuits ‘z’ in the output means the signals are not connected properly. 53 | 54 | ## Labs Breakdown 55 | 56 | | Lab# | Labsheet | notes | topic | 57 | | ---- | -------------------------------------------------------- | ---------------------- | ------------------------------ | 58 | | 1 | [link](Lab1/Lab1_Sheet.pdf) | [link](Lab1/README.md) | Intro to verilog | 59 | | 2 | [link](Lab2/Lab_Sheet_2_Final.pdf) | [link](Lab2/README.md) | Combinational Circuit Modeling | 60 | | 3 | [link](Lab3/Lab_Sheet_3_Final.pdf) | [link](Lab3/README.md) | Sequential Circuit Modeling | 61 | | 4 | [link](Lab4/Lab4_sheet_aludesign.pdf) | [link](Lab4/README.md) | ALU Design | 62 | | 5 | [link](Lab5/Lab5_sheet_registerfile.pdf) | [link](Lab5/README.md) | Register File Implementation | 63 | | 6 | [link](Lab6/Lab_Sheet_6_Single_Cycle_Datapath_Final.pdf) | [link](Lab6/README.md) | Single Cycle Datapath Design | 64 | | 7 | [link](Lab7/LabSheet7.pdf) | [link](Lab7/README.md) | Multi-Cycle controller Design | 65 | | 8 | [link](Lab8/Lab_Sheet_8_Pipeline_DesignF.pdf) | [link](Lab8/README.md) | Pipeline Design | 66 | 67 | ## References 68 | 69 | 1. *Verilog HDL by Samir Palnitkar* 70 | 71 | ## Disclaimer 72 | 73 | - *The codes are not guaranteed to be correct and have not been verified thouroughly, if you find a mistake please feel free to send a PR or contact me via mail.* 74 | - *All files on this repository are for educational purpose with no intentions of promoting unfair means in any evaluative component* 75 | 76 | ## Commit History Visualizer 77 | 78 | ![GIF](CommitHistoryVisualizer/Verilog.gif) 79 | 80 | [video](CommitHistoryVisualizer/Verilog.mp4) 81 | 82 | - Above video is made using ![Visual Source](https://img.shields.io/badge/visual-source-orange) 83 | -------------------------------------------------------------------------------- /Samir Palnitkar - Verilog HDL-Prentice Hall (1996).pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/SinghCoder/Icarus_Verilog/c326ccb1b1a354daaf6e61368712536428445de5/Samir Palnitkar - Verilog HDL-Prentice Hall (1996).pdf -------------------------------------------------------------------------------- /Verilog_Notes.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/SinghCoder/Icarus_Verilog/c326ccb1b1a354daaf6e61368712536428445de5/Verilog_Notes.pdf -------------------------------------------------------------------------------- /_config.yml: -------------------------------------------------------------------------------- 1 | theme: jekyll-theme-hacker --------------------------------------------------------------------------------