├── README.md └── v1.0 Encode-Decoder no Fsm ├── Polar_1024bits ├── D_FF.lso ├── D_FF.vhd ├── D_FF_1bit.vhd ├── D_FF_N.lso ├── D_FF_N.prj ├── D_FF_N.stx ├── D_FF_N.vhd ├── D_FF_N.xst ├── D_FF_N_envsettings.html ├── Decoder1024.lso ├── Decoder1024.prj ├── Decoder1024.stx ├── Decoder1024.vhd ├── Decoder1024.xst ├── Encoder1024.bld ├── Encoder1024.cmd_log ├── Encoder1024.lso ├── Encoder1024.ngc ├── Encoder1024.ngd ├── Encoder1024.prj ├── Encoder1024.stx ├── Encoder1024.syr ├── Encoder1024.vhd ├── Encoder1024.xst ├── Encoder1024_envsettings.html ├── Encoder1024_map.map ├── Encoder1024_map.mrp ├── Encoder1024_map.ngm ├── Encoder1024_map.xrpt ├── Encoder1024_ngdbuild.xrpt ├── Encoder1024_summary.html ├── Encoder1024_xst.xrpt ├── F.vhd ├── G.vhd ├── MyPackage.vhd ├── PartialSumGenerator.lso ├── PartialSumGenerator.vhd ├── Polar_1024bits.gise ├── Polar_1024bits.xise ├── _ngo │ └── netlist.lst ├── _xmsgs │ ├── map.xmsgs │ └── ngdbuild.xmsgs ├── counter.vhd ├── fuse.xmsgs ├── fuseRelaunch.cmd ├── iseconfig │ ├── D_FF_N.xreport │ ├── Decoder1024.xreport │ ├── Encoder1024.xreport │ ├── Polar1024.projectmgr │ └── Polar_1024bits.projectmgr ├── llr_test.lso ├── llr_test.prj ├── llr_test.stx ├── llr_test.vhd ├── llr_test.xst ├── math_real.vhdl.txt ├── pepExtractor.prj ├── system.bmm ├── system.vhd ├── system_isim_beh.exe ├── system_isim_beh.wdb ├── test.vhd ├── test_encoder.vhd └── xlnx_auto_0_xdb │ └── cst.xbcd ├── Polar_32bits ├── 1.txt ├── BoxMuller.vhd ├── D_FF.vhd ├── D_FF_1bit.vhd ├── D_FF_N.vhd ├── D_FF_beh.prj ├── D_FF_en.vhd ├── D_FF_llr.vhd ├── Decoder.vhd ├── Decoder_envsettings.html ├── Decoder_guide.ncd ├── Decoder_isim_beh1.wdb ├── Decoder_summary.html ├── Encoder.vhd ├── Encoder32_beh.prj ├── Encoder32_summary.html ├── Encoder_summary.html ├── F.vhd ├── FSM_Encoder.vhd ├── F_envsettings.html ├── F_summary.html ├── G.vhd ├── IO_Input.vhd ├── IO_Outputs.vhd ├── MyPackage.vhd ├── PartialSumGenerator.vhd ├── Polar_32bits.gise ├── Polar_32bits.xise ├── _ngo │ └── netlist.lst ├── _xmsgs │ ├── map.xmsgs │ ├── ngdbuild.xmsgs │ ├── par.xmsgs │ ├── pn_parser.xmsgs │ ├── trce.xmsgs │ └── xst.xmsgs ├── ananeosi.vhd ├── channel_testbench.vhd ├── cntr_fifo.vhd ├── counter.lso ├── counter.vhd ├── counterNdivKbits.vhd ├── encoder_channel_vhd.vhd ├── fast.vhd ├── fuse.log ├── fuse.xmsgs ├── fuseRelaunch.cmd ├── iseconfig │ ├── Decoder.xreport │ ├── Encoder16.xreport │ ├── F.xreport │ ├── FSM_Encoder.xreport │ ├── Polar_32bits.projectmgr │ ├── mysystem.xreport │ └── system.xreport ├── isim.cmd ├── isim.log ├── isim │ ├── isim_usage_statistics.html │ ├── pn_info │ ├── precompiled.exe.sim │ │ └── ieee │ │ │ ├── p_1242562249.c │ │ │ ├── p_1242562249.didat │ │ │ ├── p_1242562249.nt64.obj │ │ │ ├── p_2592010699.c │ │ │ ├── p_2592010699.didat │ │ │ ├── p_2592010699.nt64.obj │ │ │ ├── p_3499444699.c │ │ │ ├── p_3499444699.didat │ │ │ ├── p_3499444699.nt64.obj │ │ │ ├── p_3620187407.c │ │ │ ├── p_3620187407.didat │ │ │ ├── p_3620187407.nt64.obj │ │ │ ├── p_3972351953.c │ │ │ ├── p_3972351953.didat │ │ │ └── p_3972351953.nt64.obj │ ├── system_isim_beh.exe.sim │ │ ├── ISimEngine-DesignHierarchy.dbg │ │ ├── isimcrash.log │ │ ├── isimkernel.log │ │ ├── libPortability.dll │ │ ├── netId.dat │ │ ├── system_isim_beh.exe │ │ ├── tmp_save │ │ │ └── _1 │ │ └── work │ │ │ ├── a_0422964305_3212880686.c │ │ │ ├── a_0422964305_3212880686.didat │ │ │ ├── a_0422964305_3212880686.nt64.obj │ │ │ ├── a_0515771138_3212880686.c │ │ │ ├── a_0515771138_3212880686.didat │ │ │ ├── a_0515771138_3212880686.nt64.obj │ │ │ ├── a_1721066749_3212880686.c │ │ │ ├── a_1721066749_3212880686.didat │ │ │ ├── a_1721066749_3212880686.nt64.obj │ │ │ ├── a_1881823395_3212880686.c │ │ │ ├── a_1881823395_3212880686.didat │ │ │ ├── a_1881823395_3212880686.nt64.obj │ │ │ ├── a_1911451838_3212880686.c │ │ │ ├── a_1911451838_3212880686.didat │ │ │ ├── a_1911451838_3212880686.nt64.obj │ │ │ ├── a_2064211777_3212880686.c │ │ │ ├── a_2064211777_3212880686.didat │ │ │ ├── a_2064211777_3212880686.nt64.obj │ │ │ ├── a_2263464102_3212880686.c │ │ │ ├── a_2263464102_3212880686.didat │ │ │ ├── a_2263464102_3212880686.nt64.obj │ │ │ ├── a_2933281589_3212880686.c │ │ │ ├── a_2933281589_3212880686.didat │ │ │ ├── a_2933281589_3212880686.nt64.obj │ │ │ ├── a_3289945837_1142133938.c │ │ │ ├── a_3289945837_1142133938.didat │ │ │ ├── a_3289945837_1142133938.nt64.obj │ │ │ ├── a_3959846087_3212880686.c │ │ │ ├── a_3959846087_3212880686.didat │ │ │ ├── a_3959846087_3212880686.nt64.obj │ │ │ ├── a_4250923597_3212880686.c │ │ │ ├── a_4250923597_3212880686.didat │ │ │ ├── a_4250923597_3212880686.nt64.obj │ │ │ ├── p_4053066488.c │ │ │ ├── p_4053066488.didat │ │ │ ├── p_4053066488.nt64.obj │ │ │ ├── system_isim_beh.exe_main.c │ │ │ └── system_isim_beh.exe_main.nt64.obj │ └── work │ │ ├── counter.vdb │ │ ├── d_ff_1bit.vdb │ │ ├── d_ff_gen.vdb │ │ ├── decoder.vdb │ │ ├── encoder.vdb │ │ ├── f.vdb │ │ ├── g.vdb │ │ ├── llr_test.vdb │ │ ├── mypackage.vdb │ │ ├── partialsumgenerator.vdb │ │ └── system.vdb ├── ldzcount.vhd ├── llr2_to_channel.vhd ├── llr_test.vhd ├── llr_test_beh.prj ├── mac.vhd ├── mt2.vhd ├── mux.vhd ├── myawgn.vhd ├── mybpsk.vhd ├── mycos.vhd ├── mycount.vhd ├── mycount2.vhd ├── mydff.vhd ├── mydff2.vhd ├── myfsm.vhd ├── myfsm3.vhd ├── myfsm4.vhd ├── mylfsr2.vhd ├── myllr.vhd ├── mylog2.vhd ├── myram.vhd ├── myram2.vhd ├── myreg.vhd ├── myreg2.vhd ├── myrom2.vhd ├── mysystem.vhd ├── mysystem_summary.html ├── mytel.vhd ├── par_usage_statistics.html ├── paragogi.vhd ├── pepExtractor.prj ├── pinakes2.vhd ├── sat.vhd ├── sat51.vhd ├── sel.vhd ├── sel2.vhd ├── shift.vhd ├── shifting.vhd ├── snrlut.vhd ├── synt1.vhd ├── synt2.vhd ├── synt3.vhd ├── synt4.vhd ├── synt5.vhd ├── system.bld ├── system.cmd_log ├── system.lso ├── system.ncd ├── system.ngc ├── system.ngd ├── system.ngr ├── system.pad ├── system.par ├── system.pcf ├── system.prj ├── system.ptwx ├── system.stx ├── system.syr ├── system.twr ├── system.twx ├── system.unroutes ├── system.vhd ├── system.xpi ├── system.xst ├── system_beh.prj ├── system_guide.ncd ├── system_isim_beh.exe ├── system_isim_beh.wdb ├── system_isim_beh1.wdb ├── system_map.map ├── system_map.mrp ├── system_map.ncd ├── system_map.ngm ├── system_map.xrpt ├── system_ngdbuild.xrpt ├── system_pad.csv ├── system_pad.txt ├── system_par.xrpt ├── system_summary.xml ├── system_usage.xml ├── system_vhdl.prj ├── system_xst.xrpt ├── test.vhd ├── test_encoder32.vhd ├── testold.vhd ├── txt_util.vhd ├── uutfsm.vhd ├── vsim.wlf ├── webtalk_pn.xml ├── work │ ├── _info │ ├── _lib.qdb │ ├── _lib1_1.qdb │ ├── _lib1_1.qpg │ ├── _lib1_1.qtl │ └── _vmake ├── xilinxsim.ini ├── xlnx_auto_0_xdb │ └── cst.xbcd └── xst │ └── work │ ├── hdllib.ref │ ├── hdpdeps.ref │ └── sub00 │ ├── vhpl00.vho │ ├── vhpl01.vho │ ├── vhpl02.vho │ ├── vhpl03.vho │ ├── vhpl04.vho │ ├── vhpl05.vho │ ├── vhpl06.vho │ ├── vhpl07.vho │ ├── vhpl08.vho │ ├── vhpl09.vho │ ├── vhpl10.vho │ ├── vhpl11.vho │ ├── vhpl12.vho │ ├── vhpl13.vho │ ├── vhpl14.vho │ ├── vhpl15.vho │ ├── vhpl16.vho │ ├── vhpl17.vho │ ├── vhpl18.vho │ ├── vhpl19.vho │ ├── vhpl20.vho │ └── vhpl21.vho └── Polar_512bits ├── .lso ├── D_FF.vhd ├── D_FF_1bit.vhd ├── D_FF_N.vhd ├── D_FF_en.vhd ├── Decoder512.bmm ├── Decoder512.vhd ├── Decoder512_beh.prj ├── Encoder1024.ngc ├── Encoder1024.vhd ├── Encoder512.vhd ├── F.vhd ├── FSM_Encoder.vhd ├── G.vhd ├── IO_Outputs.vhd ├── IO_Outputs_summary.html ├── MyPackage.vhd ├── PartialSumGenerator.vhd ├── Polar_512bits.gise ├── Polar_512bits.xise ├── _ngo ├── system_cs_signalbrowser.ngo └── system_cs_signalbrowser.ver ├── _xmsgs ├── ngcbuild.xmsgs └── pn_parser.xmsgs ├── chipscope512.cdc ├── counter.vhd ├── encoder_testbench.vhd ├── fuse.xmsgs ├── fuseRelaunch.cmd ├── iseconfig ├── IO_Outputs.xreport ├── Polar_512bits.projectmgr └── system.xreport ├── llr_test.vhd ├── math_real.vhdl ├── mux.vhd ├── pepExtractor.prj ├── system.prj ├── system.stx ├── system.vhd ├── system.xst ├── system_summary.html ├── system_testbench.vhd ├── system_vhdl.prj ├── test.vhd ├── test_decoder.vhd ├── test_decoder_beh.prj ├── test_encoder.vhd ├── test_encoder512.vhd ├── test_encoder512_isim_beh1.wdb └── xst └── work ├── hdllib.ref ├── hdpdeps.ref └── sub00 ├── vhpl00.vho ├── vhpl01.vho ├── vhpl02.vho ├── vhpl03.vho ├── vhpl04.vho ├── vhpl05.vho ├── vhpl06.vho ├── vhpl07.vho ├── vhpl08.vho ├── vhpl09.vho ├── vhpl10.vho ├── vhpl11.vho ├── vhpl12.vho ├── vhpl13.vho ├── vhpl14.vho ├── vhpl15.vho ├── vhpl16.vho ├── vhpl17.vho ├── vhpl18.vho ├── vhpl19.vho ├── vhpl20.vho └── vhpl21.vho /README.md: -------------------------------------------------------------------------------- 1 | #Polar-Codes-Hardware-VHDL-N-16 2 | -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_1024bits/D_FF.lso: -------------------------------------------------------------------------------- 1 | work 2 | -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_1024bits/D_FF.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Company: 3 | -- Engineer: 4 | -- 5 | -- Create Date: 14:03:21 02/23/2016 6 | -- Design Name: 7 | -- Module Name: D_FF - Behavioral 8 | -- Project Name: 9 | -- Target Devices: 10 | -- Tool versions: 11 | -- Description: 12 | -- 13 | -- Dependencies: 14 | -- 15 | -- Revision: 16 | -- Revision 0.01 - File Created 17 | -- Additional Comments: 18 | -- 19 | ---------------------------------------------------------------------------------- 20 | library IEEE; 21 | use IEEE.STD_LOGIC_1164.ALL; 22 | use work.all; 23 | use work.MyPackage.all; 24 | 25 | -- Uncomment the following library declaration if using 26 | -- arithmetic functions with Signed or Unsigned values 27 | --use IEEE.NUMERIC_STD.ALL; 28 | 29 | -- Uncomment the following library declaration if instantiating 30 | -- any Xilinx primitives in this code. 31 | --library UNISIM; 32 | --use UNISIM.VComponents.all; 33 | 34 | entity D_FF_gen is 35 | generic(width: integer := K); 36 | port( 37 | clk : in std_logic; 38 | rst : in std_logic; 39 | ce : in std_logic; 40 | d : in std_logic_vector(width-1 downto 0); 41 | q : out std_logic_vector(width-1 downto 0)); 42 | end entity D_FF_gen; 43 | 44 | architecture Behavioral of D_FF_gen is 45 | begin 46 | process (clk) 47 | begin 48 | if rising_edge(clk) then 49 | if(rst = '1') then 50 | q <= (others => '0'); 51 | else 52 | if( ce = '1') then 53 | q <= d; 54 | end if; 55 | end if; 56 | end if; 57 | end process; 58 | end architecture Behavioral; 59 | 60 | -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_1024bits/D_FF_1bit.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Company: 3 | -- Engineer: 4 | -- 5 | -- Create Date: 14:03:21 02/23/2016 6 | -- Design Name: 7 | -- Module Name: D_FF - Behavioral 8 | -- Project Name: 9 | -- Target Devices: 10 | -- Tool versions: 11 | -- Description: 12 | -- 13 | -- Dependencies: 14 | -- 15 | -- Revision: 16 | -- Revision 0.01 - File Created 17 | -- Additional Comments: 18 | -- 19 | ---------------------------------------------------------------------------------- 20 | library IEEE; 21 | use IEEE.STD_LOGIC_1164.ALL; 22 | use work.all; 23 | use work.MyPackage.all; 24 | 25 | -- Uncomment the following library declaration if using 26 | -- arithmetic functions with Signed or Unsigned values 27 | --use IEEE.NUMERIC_STD.ALL; 28 | 29 | -- Uncomment the following library declaration if instantiating 30 | -- any Xilinx primitives in this code. 31 | --library UNISIM; 32 | --use UNISIM.VComponents.all; 33 | 34 | entity D_FF_1bit is 35 | port( 36 | clk : in std_logic; 37 | rst : in std_logic; 38 | ce : in std_logic; 39 | d : in std_logic; 40 | q : out std_logic); 41 | end entity D_FF_1bit; 42 | 43 | architecture Behavioral of D_FF_1bit is 44 | begin 45 | process (clk) 46 | begin 47 | if rising_edge(clk) then 48 | if(rst = '1') then 49 | q <= '0'; 50 | else 51 | if( ce = '1') then 52 | q <= d; 53 | end if; 54 | end if; 55 | end if; 56 | end process; 57 | end architecture Behavioral; 58 | 59 | -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_1024bits/D_FF_N.lso: -------------------------------------------------------------------------------- 1 | work 2 | -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_1024bits/D_FF_N.prj: -------------------------------------------------------------------------------- 1 | vhdl work "MyPackage.vhd" 2 | vhdl work "D_FF_N.vhd" 3 | -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_1024bits/D_FF_N.stx: -------------------------------------------------------------------------------- 1 | Release 14.2 - xst P.28xd (nt64) 2 | Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. 3 | --> Parameter TMPDIR set to D:/Dropbox/Thesis Project/Hardware/Polar1024/xst/projnav.tmp 4 | 5 | 6 | Total REAL time to Xst completion: 0.00 secs 7 | Total CPU time to Xst completion: 0.44 secs 8 | 9 | --> Parameter xsthdpdir set to D:/Dropbox/Thesis Project/Hardware/Polar1024/xst 10 | 11 | 12 | Total REAL time to Xst completion: 0.00 secs 13 | Total CPU time to Xst completion: 0.44 secs 14 | 15 | --> Reading design: D_FF_N.prj 16 | 17 | TABLE OF CONTENTS 18 | 1) Synthesis Options Summary 19 | 2) HDL Parsing 20 | 3) HDL Elaboration 21 | 4) HDL Synthesis 22 | 4.1) HDL Synthesis Report 23 | 5) Advanced HDL Synthesis 24 | 5.1) Advanced HDL Synthesis Report 25 | 6) Low Level Synthesis 26 | 7) Partition Report 27 | 8) Design Summary 28 | 8.1) Primitive and Black Box Usage 29 | 8.2) Device utilization summary 30 | 8.3) Partition Resource Summary 31 | 8.4) Timing Report 32 | 8.4.1) Clock Information 33 | 8.4.2) Asynchronous Control Signals Information 34 | 8.4.3) Timing Summary 35 | 8.4.4) Timing Details 36 | 8.4.5) Cross Clock Domains Report 37 | 38 | 39 | ========================================================================= 40 | * HDL Parsing * 41 | ========================================================================= 42 | Parsing VHDL file "D:\Dropbox\Thesis Project\Hardware\Polar1024\MyPackage.vhd" into library work 43 | Parsing package . 44 | Parsing package body . 45 | Parsing VHDL file "D:\Dropbox\Thesis Project\Hardware\Polar1024\D_FF_N.vhd" into library work 46 | Parsing entity . 47 | Parsing architecture of entity . 48 | 49 | 50 | Total REAL time to Xst completion: 11.00 secs 51 | Total CPU time to Xst completion: 11.09 secs 52 | 53 | --> 54 | 55 | Total memory usage is 214420 kilobytes 56 | 57 | Number of errors : 0 ( 0 filtered) 58 | Number of warnings : 0 ( 0 filtered) 59 | Number of infos : 0 ( 0 filtered) 60 | 61 | -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_1024bits/D_FF_N.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Company: 3 | -- Engineer: 4 | -- 5 | -- Create Date: 14:03:21 02/23/2016 6 | -- Design Name: 7 | -- Module Name: D_FF - Behavioral 8 | -- Project Name: 9 | -- Target Devices: 10 | -- Tool versions: 11 | -- Description: 12 | -- 13 | -- Dependencies: 14 | -- 15 | -- Revision: 16 | -- Revision 0.01 - File Created 17 | -- Additional Comments: 18 | -- 19 | ---------------------------------------------------------------------------------- 20 | library IEEE; 21 | use IEEE.STD_LOGIC_1164.ALL; 22 | use work.all; 23 | use work.MyPackage.all; 24 | 25 | -- Uncomment the following library declaration if using 26 | -- arithmetic functions with Signed or Unsigned values 27 | --use IEEE.NUMERIC_STD.ALL; 28 | 29 | -- Uncomment the following library declaration if instantiating 30 | -- any Xilinx primitives in this code. 31 | --library UNISIM; 32 | --use UNISIM.VComponents.all; 33 | 34 | entity D_FF_N is 35 | port( 36 | clk : in std_logic; 37 | rst : in std_logic; 38 | ce : in std_logic; 39 | d : in llr; 40 | q : out llr); 41 | end entity D_FF_N; 42 | 43 | architecture Behavioral of D_FF_N is 44 | begin 45 | process (clk) 46 | begin 47 | if rising_edge(clk) then 48 | if(rst = '1') then 49 | q <= (others =>'0'); 50 | else 51 | if( ce = '1') then 52 | q <= d; 53 | end if; 54 | end if; 55 | end if; 56 | end process; 57 | end architecture Behavioral; 58 | 59 | -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_1024bits/D_FF_N.xst: -------------------------------------------------------------------------------- 1 | set -tmpdir "D:/Dropbox/Thesis Project/Hardware/Polar1024/xst/projnav.tmp" 2 | set -xsthdpdir "D:/Dropbox/Thesis Project/Hardware/Polar1024/xst" 3 | run -compileonly yes 4 | -p xc7vx330t-2-ffg1157 5 | -top D_FF_N 6 | -opt_mode Speed 7 | -opt_level 1 8 | -power NO 9 | -iuc NO 10 | -keep_hierarchy No 11 | -netlist_hierarchy As_Optimized 12 | -rtlview Yes 13 | -glob_opt AllClockNets 14 | -read_cores YES 15 | -write_timing_constraints NO 16 | -cross_clock_analysis NO 17 | -hierarchy_separator / 18 | -bus_delimiter <> 19 | -case Maintain 20 | -slice_utilization_ratio 100 21 | -bram_utilization_ratio 100 22 | -dsp_utilization_ratio 100 23 | -lc Auto 24 | -reduce_control_sets Auto 25 | -fsm_extract YES -fsm_encoding Auto 26 | -safe_implementation No 27 | -fsm_style LUT 28 | -ram_extract Yes 29 | -ram_style Auto 30 | -rom_extract Yes 31 | -shreg_extract YES 32 | -rom_style Auto 33 | -auto_bram_packing NO 34 | -resource_sharing YES 35 | -async_to_sync NO 36 | -shreg_min_size 2 37 | -use_dsp48 Auto 38 | -iobuf YES 39 | -max_fanout 100000 40 | -bufg 32 41 | -register_duplication YES 42 | -register_balancing No 43 | -optimize_primitives NO 44 | -use_clock_enable Auto 45 | -use_sync_set Auto 46 | -use_sync_reset Auto 47 | -iob Auto 48 | -equivalent_register_removal YES 49 | -slice_utilization_ratio_maxmargin 5 50 | -ifn D_FF_N.prj 51 | -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_1024bits/Decoder1024.lso: -------------------------------------------------------------------------------- 1 | work 2 | -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_1024bits/Decoder1024.prj: -------------------------------------------------------------------------------- 1 | vhdl work "MyPackage.vhd" 2 | vhdl work "PartialSumGenerator.vhd" 3 | vhdl work "G.vhd" 4 | vhdl work "F.vhd" 5 | vhdl work "D_FF_1bit.vhd" 6 | vhdl work "D_FF.vhd" 7 | vhdl work "Decoder1024.vhd" 8 | -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_1024bits/Decoder1024.xst: -------------------------------------------------------------------------------- 1 | set -tmpdir "D:/Dropbox/Thesis Project/Hardware/Polar1024/xst/projnav.tmp" 2 | set -xsthdpdir "D:/Dropbox/Thesis Project/Hardware/Polar1024/xst" 3 | run -compileonly yes 4 | -p xc7vx330t-2-ffg1157 5 | -top Decoder1024 6 | -opt_mode Speed 7 | -opt_level 1 8 | -power NO 9 | -iuc NO 10 | -keep_hierarchy No 11 | -netlist_hierarchy As_Optimized 12 | -rtlview Yes 13 | -glob_opt AllClockNets 14 | -read_cores YES 15 | -write_timing_constraints NO 16 | -cross_clock_analysis NO 17 | -hierarchy_separator / 18 | -bus_delimiter <> 19 | -case Maintain 20 | -slice_utilization_ratio 100 21 | -bram_utilization_ratio 100 22 | -dsp_utilization_ratio 100 23 | -lc Auto 24 | -reduce_control_sets Auto 25 | -fsm_extract YES -fsm_encoding Auto 26 | -safe_implementation No 27 | -fsm_style LUT 28 | -ram_extract Yes 29 | -ram_style Auto 30 | -rom_extract Yes 31 | -shreg_extract YES 32 | -rom_style Auto 33 | -auto_bram_packing NO 34 | -resource_sharing YES 35 | -async_to_sync NO 36 | -shreg_min_size 2 37 | -use_dsp48 Auto 38 | -iobuf YES 39 | -max_fanout 100000 40 | -bufg 32 41 | -register_duplication YES 42 | -register_balancing No 43 | -optimize_primitives NO 44 | -use_clock_enable Auto 45 | -use_sync_set Auto 46 | -use_sync_reset Auto 47 | -iob Auto 48 | -equivalent_register_removal YES 49 | -slice_utilization_ratio_maxmargin 5 50 | -ifn Decoder1024.prj 51 | -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_1024bits/Encoder1024.bld: -------------------------------------------------------------------------------- 1 | Release 14.2 ngdbuild P.28xd (nt64) 2 | Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. 3 | 4 | Command Line: C:\Xilinx\14.2\ISE_DS\ISE\bin\nt64\unwrapped\ngdbuild.exe 5 | -intstyle ise -dd _ngo -nt timestamp -i -p xc7vx330t-ffg1157-2 Encoder1024.ngc 6 | Encoder1024.ngd 7 | 8 | Reading NGO file "D:/Dropbox/Thesis Project/Hardware/Polar1024/Encoder1024.ngc" 9 | ... 10 | Gathering constraint information from source properties... 11 | Done. 12 | 13 | Resolving constraint associations... 14 | Checking Constraint Associations... 15 | Done... 16 | 17 | Checking expanded design ... 18 | 19 | Partition Implementation Status 20 | ------------------------------- 21 | 22 | No Partitions were found in this design. 23 | 24 | ------------------------------- 25 | 26 | NGDBUILD Design Results Summary: 27 | Number of errors: 0 28 | Number of warnings: 0 29 | 30 | Total memory usage is 218960 kilobytes 31 | 32 | Writing NGD file "Encoder1024.ngd" ... 33 | Total REAL time to NGDBUILD completion: 13 sec 34 | Total CPU time to NGDBUILD completion: 13 sec 35 | 36 | Writing NGDBUILD log file "Encoder1024.bld"... 37 | -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_1024bits/Encoder1024.cmd_log: -------------------------------------------------------------------------------- 1 | xst -intstyle ise -ifn "D:/Dropbox/Thesis Project/Hardware/Polar1024/Encoder1024.xst" -ofn "D:/Dropbox/Thesis Project/Hardware/Polar1024/Encoder1024.syr" 2 | ngdbuild -intstyle ise -dd _ngo -nt timestamp -i -p xc7v2000t-flg1925-2 "Encoder1024.ngc" Encoder1024.ngd 3 | map -intstyle ise -p xc7v2000t-flg1925-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -mt off -ir off -pr off -lc off -power off -o Encoder1024_map.ncd Encoder1024.ngd Encoder1024.pcf 4 | xst -intstyle ise -ifn "D:/Dropbox/Thesis Project/Hardware/Polar1024/Encoder1024.xst" -ofn "D:/Dropbox/Thesis Project/Hardware/Polar1024/Encoder1024.syr" 5 | ngdbuild -intstyle ise -dd _ngo -nt timestamp -i -p xc7vx330t-ffg1157-2 "Encoder1024.ngc" Encoder1024.ngd 6 | map -intstyle ise -p xc7vx330t-ffg1157-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -mt off -ir off -pr off -lc off -power off -o Encoder1024_map.ncd Encoder1024.ngd Encoder1024.pcf 7 | map -intstyle ise -p xc7vx330t-ffg1157-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -mt off -ir off -pr off -lc off -power off -o Encoder1024_map.ncd Encoder1024.ngd Encoder1024.pcf 8 | -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_1024bits/Encoder1024.lso: -------------------------------------------------------------------------------- 1 | work 2 | -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_1024bits/Encoder1024.prj: -------------------------------------------------------------------------------- 1 | vhdl work "MyPackage.vhd" 2 | vhdl work "Encoder1024.vhd" 3 | -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_1024bits/Encoder1024.stx: -------------------------------------------------------------------------------- 1 | Release 14.2 - xst P.28xd (nt64) 2 | Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. 3 | --> Parameter TMPDIR set to D:/Dropbox/Thesis Project/Hardware/Polar1024/xst/projnav.tmp 4 | 5 | 6 | Total REAL time to Xst completion: 1.00 secs 7 | Total CPU time to Xst completion: 0.35 secs 8 | 9 | --> Parameter xsthdpdir set to D:/Dropbox/Thesis Project/Hardware/Polar1024/xst 10 | 11 | 12 | Total REAL time to Xst completion: 1.00 secs 13 | Total CPU time to Xst completion: 0.35 secs 14 | 15 | --> Reading design: Encoder1024.prj 16 | 17 | TABLE OF CONTENTS 18 | 1) Synthesis Options Summary 19 | 2) HDL Parsing 20 | 3) HDL Elaboration 21 | 4) HDL Synthesis 22 | 4.1) HDL Synthesis Report 23 | 5) Advanced HDL Synthesis 24 | 5.1) Advanced HDL Synthesis Report 25 | 6) Low Level Synthesis 26 | 7) Partition Report 27 | 8) Design Summary 28 | 8.1) Primitive and Black Box Usage 29 | 8.2) Device utilization summary 30 | 8.3) Partition Resource Summary 31 | 8.4) Timing Report 32 | 8.4.1) Clock Information 33 | 8.4.2) Asynchronous Control Signals Information 34 | 8.4.3) Timing Summary 35 | 8.4.4) Timing Details 36 | 8.4.5) Cross Clock Domains Report 37 | 38 | 39 | ========================================================================= 40 | * HDL Parsing * 41 | ========================================================================= 42 | Parsing VHDL file "D:\Dropbox\Thesis Project\Hardware\Polar1024\MyPackage.vhd" into library work 43 | Parsing package . 44 | Parsing package body . 45 | Parsing VHDL file "D:\Dropbox\Thesis Project\Hardware\Polar1024\Encoder1024.vhd" into library work 46 | Parsing entity . 47 | Parsing architecture of entity . 48 | 49 | 50 | Total REAL time to Xst completion: 12.00 secs 51 | Total CPU time to Xst completion: 11.17 secs 52 | 53 | --> 54 | 55 | Total memory usage is 226068 kilobytes 56 | 57 | Number of errors : 0 ( 0 filtered) 58 | Number of warnings : 0 ( 0 filtered) 59 | Number of infos : 0 ( 0 filtered) 60 | 61 | -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_1024bits/Encoder1024.xst: -------------------------------------------------------------------------------- 1 | set -tmpdir "D:/Dropbox/Thesis Project/Hardware/Polar1024/xst/projnav.tmp" 2 | set -xsthdpdir "D:/Dropbox/Thesis Project/Hardware/Polar1024/xst" 3 | run -compileonly yes 4 | -p xc7vx330t-2-ffg1157 5 | -top Encoder1024 6 | -opt_mode Speed 7 | -opt_level 1 8 | -power NO 9 | -iuc NO 10 | -keep_hierarchy No 11 | -netlist_hierarchy As_Optimized 12 | -rtlview Yes 13 | -glob_opt AllClockNets 14 | -read_cores YES 15 | -write_timing_constraints NO 16 | -cross_clock_analysis NO 17 | -hierarchy_separator / 18 | -bus_delimiter <> 19 | -case Maintain 20 | -slice_utilization_ratio 100 21 | -bram_utilization_ratio 100 22 | -dsp_utilization_ratio 100 23 | -lc Auto 24 | -reduce_control_sets Auto 25 | -fsm_extract YES -fsm_encoding Auto 26 | -safe_implementation No 27 | -fsm_style LUT 28 | -ram_extract Yes 29 | -ram_style Auto 30 | -rom_extract Yes 31 | -shreg_extract YES 32 | -rom_style Auto 33 | -auto_bram_packing NO 34 | -resource_sharing YES 35 | -async_to_sync NO 36 | -shreg_min_size 2 37 | -use_dsp48 Auto 38 | -iobuf YES 39 | -max_fanout 100000 40 | -bufg 32 41 | -register_duplication YES 42 | -register_balancing No 43 | -optimize_primitives NO 44 | -use_clock_enable Auto 45 | -use_sync_set Auto 46 | -use_sync_reset Auto 47 | -iob Auto 48 | -equivalent_register_removal YES 49 | -slice_utilization_ratio_maxmargin 5 50 | -ifn Encoder1024.prj 51 | -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_1024bits/F.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Company: 3 | -- Engineer: 4 | -- 5 | -- Create Date: 17:34:30 02/06/2016 6 | -- Design Name: 7 | -- Module Name: F - Behavioral 8 | -- Project Name: 9 | -- Target Devices: 10 | -- Tool versions: 11 | -- Description: 12 | -- 13 | -- Dependencies: 14 | -- 15 | -- Revision: 16 | -- Revision 0.01 - File Created 17 | -- Additional Comments: 18 | -- 19 | ---------------------------------------------------------------------------------- 20 | library IEEE; 21 | use IEEE.STD_LOGIC_1164.ALL; 22 | use IEEE.NUMERIC_STD.ALL; 23 | use work.MyPackage.all; 24 | 25 | -- Uncomment the following library declaration if using 26 | -- arithmetic functions with Signed or Unsigned values 27 | 28 | 29 | -- Uncomment the following library declaration if instantiating 30 | -- any Xilinx primitives in this code. 31 | --library UNISIM; 32 | --use UNISIM.VComponents.all; 33 | 34 | entity F is 35 | Port ( lamdaA : in llr; 36 | lamdaB : in llr; 37 | lamdaOut : out llr); 38 | end F; 39 | 40 | architecture Behavioral of F is 41 | signal positive_lamdaA, positive_lamdaB: signed(integer_part+fractional_part-1 downto 0); 42 | signal min: llr; 43 | signal sign: STD_LOGIC; 44 | begin 45 | sign <= lamdaA(sign_bit) xor lamdaB(sign_bit); 46 | positive_lamdaA <= signed(not(lamdaA)) + one when lamdaA(sign_bit) = '1' 47 | else signed(lamdaA); 48 | positive_lamdaB <= signed(not(lamdaB)) + one when lamdaB(sign_bit) = '1' 49 | else signed(lamdaB); 50 | min <= std_logic_vector(positive_lamdaA(integer_part+fractional_part-1 downto 0)) when positive_lamdaA < positive_lamdaB 51 | else std_logic_vector(positive_lamdaB(integer_part+fractional_part-1 downto 0)); 52 | lamdaOut <= min when sign = '0' 53 | else std_logic_vector(signed(not(min)) + one); 54 | 55 | end Behavioral; 56 | 57 | -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_1024bits/G.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Company: 3 | -- Engineer: 4 | -- 5 | -- Create Date: 18:18:52 02/06/2016 6 | -- Design Name: 7 | -- Module Name: G - Behavioral 8 | -- Project Name: 9 | -- Target Devices: 10 | -- Tool versions: 11 | -- Description: 12 | -- 13 | -- Dependencies: 14 | -- 15 | -- Revision: 16 | -- Revision 0.01 - File Created 17 | -- Additional Comments: 18 | -- 19 | ---------------------------------------------------------------------------------- 20 | library IEEE; 21 | use IEEE.STD_LOGIC_1164.ALL; 22 | use IEEE.NUMERIC_STD.ALL; 23 | use work.MyPackage.all; 24 | 25 | -- Uncomment the following library declaration if using 26 | -- arithmetic functions with Signed or Unsigned values 27 | --use IEEE.NUMERIC_STD.ALL; 28 | 29 | -- Uncomment the following library declaration if instantiating 30 | -- any Xilinx primitives in this code. 31 | --library UNISIM; 32 | --use UNISIM.VComponents.all; 33 | 34 | entity G is 35 | Port ( lamdaA : in llr; 36 | lamdaB : in llr; 37 | s : in STD_LOGIC; 38 | lamdaOut : out llr); 39 | end G; 40 | 41 | architecture Behavioral of G is 42 | begin 43 | lamdaOut <= std_logic_vector(signed(lamdaA) + signed(lamdaB)) when s = '0' 44 | else std_logic_vector((signed(not(lamdaA)) + one) + signed(lamdaB)); 45 | 46 | end Behavioral; 47 | 48 | -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_1024bits/MyPackage.vhd: -------------------------------------------------------------------------------- 1 | -- 2 | -- Package File Template 3 | -- 4 | -- Purpose: This package defines supplemental types, subtypes, 5 | -- constants, and functions 6 | -- 7 | -- To use any of the example code shown below, uncomment the lines and modify as necessary 8 | -- 9 | 10 | library IEEE; 11 | use IEEE.STD_LOGIC_1164.all; 12 | use IEEE.NUMERIC_STD.ALL; 13 | 14 | package MyPackage is 15 | -- Declare functions and procedure 16 | -- 17 | -- function (signal : in ) return ; 18 | -- procedure ( : in ); 19 | -- 20 | 21 | -- Declare constants 22 | -- 23 | constant N : integer := 1024; 24 | constant K : integer := 512; 25 | constant stages : integer := 10; 26 | constant num_of_partials : integer := stages * N; 27 | constant integer_part : integer := 12; 28 | constant fractional_part : integer := 2; 29 | constant sign_bit : integer := integer_part + fractional_part -1; 30 | constant one : signed(integer_part+fractional_part-1 downto 0) := (0=>'1',others=>'0'); 31 | -- 32 | subtype s_1d is std_logic_vector(0 to N/2-1); 33 | type s_2d is array (1 to stages) of s_1d; 34 | subtype llr is std_logic_vector(integer_part+fractional_part-1 downto 0); 35 | type data is array (0 to N-1) of llr; 36 | type llr_2d is array (0 to stages) of data; 37 | -- record 38 | -- : std_logic_vector( 7 downto 0); 39 | -- : std_logic; 40 | -- end record; 41 | -- 42 | 43 | 44 | end MyPackage; 45 | 46 | package body MyPackage is 47 | 48 | ---- Example 1 49 | -- function (signal : in ) return is 50 | -- variable : ; 51 | -- begin 52 | -- := xor ; 53 | -- return ; 54 | -- end ; 55 | 56 | ---- Example 2 57 | -- function (signal : in ; 58 | -- signal : in ) return is 59 | -- begin 60 | -- if ( = '1') then 61 | -- return ; 62 | -- else 63 | -- return 'Z'; 64 | -- end if; 65 | -- end ; 66 | 67 | ---- Procedure Example 68 | -- procedure ( : in ) is 69 | -- 70 | -- begin 71 | -- 72 | -- end ; 73 | 74 | end MyPackage; 75 | -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_1024bits/PartialSumGenerator.lso: -------------------------------------------------------------------------------- 1 | work 2 | -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_1024bits/Polar_1024bits.gise: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 11.1 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_1024bits/_ngo/netlist.lst: -------------------------------------------------------------------------------- 1 | D:\Dropbox\Thesis Project\Hardware\Polar1024\Encoder1024.ngc 1459691713 2 | OK 3 | -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_1024bits/_xmsgs/map.xmsgs: -------------------------------------------------------------------------------- 1 | 2 | 7 | 8 | PAD symbol "inputs<511>" has an undefined IOSTANDARD. 9 | 10 | 11 | PAD symbol "inputs<511>" is not constrained (LOC) to a specific location. 12 | 13 | 14 | All of the single ended outputs in this design are using slew rate limited output drivers. The delay on speed critical single ended outputs can be dramatically reduced by designating them as fast outputs. 15 | 16 | 17 | Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius) 18 | 19 | 20 | Initializing voltage to 0.970 Volts. (default - Range: 0.970 to 1.030 Volts) 21 | 22 | 23 | Too many bonded comps of type "IOB" found to fit this device. 24 | 25 | 26 | The design is too large to fit the device. Please check the Design Summary section to see which resource requirement for your design exceeds the resources available in the device. Note that the number of slices reported may not be reflected accurately as their packing might not have been completed. 27 | 28 | 29 | 30 | 31 | -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_1024bits/_xmsgs/ngdbuild.xmsgs: -------------------------------------------------------------------------------- 1 | 2 | 7 | 8 | 9 | 10 | -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_1024bits/counter.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Company: 3 | -- Engineer: 4 | -- 5 | -- Create Date: 15:06:44 04/06/2016 6 | -- Design Name: 7 | -- Module Name: counter - Behavioral 8 | -- Project Name: 9 | -- Target Devices: 10 | -- Tool versions: 11 | -- Description: 12 | -- 13 | -- Dependencies: 14 | -- 15 | -- Revision: 16 | -- Revision 0.01 - File Created 17 | -- Additional Comments: 18 | -- 19 | ---------------------------------------------------------------------------------- 20 | library IEEE; 21 | use IEEE.STD_LOGIC_1164.ALL; 22 | use work.MyPackage.all; 23 | use ieee.std_logic_unsigned.all; 24 | -- Uncomment the following library declaration if using 25 | -- arithmetic functions with Signed or Unsigned values 26 | --use IEEE.NUMERIC_STD.ALL; 27 | 28 | -- Uncomment the following library declaration if instantiating 29 | -- any Xilinx primitives in this code. 30 | --library UNISIM; 31 | --use UNISIM.VComponents.all; 32 | 33 | entity counter is 34 | generic (width : integer := 8); 35 | Port ( clk : in STD_LOGIC; 36 | rst : in STD_LOGIC; 37 | count : in STD_LOGIC; 38 | Q : out STD_LOGIC_VECTOR(width-1 downto 0)); 39 | end counter; 40 | 41 | architecture behv of counter is 42 | signal Pre_Q: std_logic_vector(width-1 downto 0):= (others=>'0'); 43 | begin 44 | 45 | -- behavior describe the counter 46 | 47 | process(clk) 48 | begin 49 | if(rising_edge(clk)) then 50 | if rst = '1' then 51 | Pre_Q <= (others =>'0'); 52 | else 53 | if count = '1' then 54 | Pre_Q <= Pre_Q + 1; 55 | end if; 56 | end if; 57 | end if; 58 | end process; 59 | 60 | -- concurrent assignment statement 61 | Q <= Pre_Q; 62 | 63 | end behv; 64 | 65 | -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_1024bits/fuse.xmsgs: -------------------------------------------------------------------------------- 1 | 2 | 7 | 8 | 9 | 10 | -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_1024bits/fuseRelaunch.cmd: -------------------------------------------------------------------------------- 1 | -intstyle "ise" -incremental -lib "secureip" -o "D:/Dropbox/Thesis Project/Hardware/Polar1024/system_isim_beh.exe" -prj "D:/Dropbox/Thesis Project/Hardware/Polar1024/system_beh.prj" "work.system" 2 | -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_1024bits/llr_test.lso: -------------------------------------------------------------------------------- 1 | work 2 | -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_1024bits/llr_test.prj: -------------------------------------------------------------------------------- 1 | vhdl work "MyPackage.vhd" 2 | vhdl work "llr_test.vhd" 3 | -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_1024bits/llr_test.stx: -------------------------------------------------------------------------------- 1 | Release 14.2 - xst P.28xd (nt64) 2 | Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. 3 | --> Parameter TMPDIR set to D:/Dropbox/Thesis Project/Hardware/Polar1024/xst/projnav.tmp 4 | 5 | 6 | Total REAL time to Xst completion: 0.00 secs 7 | Total CPU time to Xst completion: 0.33 secs 8 | 9 | --> Parameter xsthdpdir set to D:/Dropbox/Thesis Project/Hardware/Polar1024/xst 10 | 11 | 12 | Total REAL time to Xst completion: 0.00 secs 13 | Total CPU time to Xst completion: 0.33 secs 14 | 15 | --> Reading design: llr_test.prj 16 | 17 | TABLE OF CONTENTS 18 | 1) Synthesis Options Summary 19 | 2) HDL Parsing 20 | 3) HDL Elaboration 21 | 4) HDL Synthesis 22 | 4.1) HDL Synthesis Report 23 | 5) Advanced HDL Synthesis 24 | 5.1) Advanced HDL Synthesis Report 25 | 6) Low Level Synthesis 26 | 7) Partition Report 27 | 8) Design Summary 28 | 8.1) Primitive and Black Box Usage 29 | 8.2) Device utilization summary 30 | 8.3) Partition Resource Summary 31 | 8.4) Timing Report 32 | 8.4.1) Clock Information 33 | 8.4.2) Asynchronous Control Signals Information 34 | 8.4.3) Timing Summary 35 | 8.4.4) Timing Details 36 | 8.4.5) Cross Clock Domains Report 37 | 38 | 39 | ========================================================================= 40 | * HDL Parsing * 41 | ========================================================================= 42 | Parsing VHDL file "D:\Dropbox\Thesis Project\Hardware\Polar1024\MyPackage.vhd" into library work 43 | Parsing package . 44 | Parsing package body . 45 | Parsing VHDL file "D:\Dropbox\Thesis Project\Hardware\Polar1024\llr_test.vhd" into library work 46 | Parsing entity . 47 | Parsing architecture of entity . 48 | 49 | 50 | Total REAL time to Xst completion: 10.00 secs 51 | Total CPU time to Xst completion: 10.78 secs 52 | 53 | --> 54 | 55 | Total memory usage is 214100 kilobytes 56 | 57 | Number of errors : 0 ( 0 filtered) 58 | Number of warnings : 0 ( 0 filtered) 59 | Number of infos : 0 ( 0 filtered) 60 | 61 | -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_1024bits/llr_test.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Company: 3 | -- Engineer: 4 | -- 5 | -- Create Date: 14:27:04 04/22/2016 6 | -- Design Name: 7 | -- Module Name: llr_test - Behavioral 8 | -- Project Name: 9 | -- Target Devices: 10 | -- Tool versions: 11 | -- Description: 12 | -- 13 | -- Dependencies: 14 | -- 15 | -- Revision: 16 | -- Revision 0.01 - File Created 17 | -- Additional Comments: 18 | -- 19 | ---------------------------------------------------------------------------------- 20 | library IEEE; 21 | use IEEE.STD_LOGIC_1164.ALL; 22 | use work.all; 23 | use work.MyPackage.all; 24 | 25 | -- Uncomment the following library declaration if using 26 | -- arithmetic functions with Signed or Unsigned values 27 | --use IEEE.NUMERIC_STD.ALL; 28 | 29 | -- Uncomment the following library declaration if instantiating 30 | -- any Xilinx primitives in this code. 31 | --library UNISIM; 32 | --use UNISIM.VComponents.all; 33 | 34 | entity llr_test is 35 | Port (inputs: in std_logic_vector(N-1 downto 0); 36 | outputs: out data); 37 | end llr_test; 38 | 39 | architecture Behavioral of llr_test is 40 | constant pos_llr : std_logic_vector(integer_part + fractional_part -1 downto 0):= (0 => '1', others=>'0'); -- +1 41 | constant neg_llr : std_logic_vector(integer_part + fractional_part -1 downto 0):= (others=> '1'); -- -1 42 | begin 43 | Decision: 44 | for i in 0 to N-1 generate 45 | Decision1: 46 | outputs(i) <= pos_llr when inputs(i)='0' 47 | else neg_llr; 48 | end generate Decision; 49 | end Behavioral; 50 | 51 | -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_1024bits/llr_test.xst: -------------------------------------------------------------------------------- 1 | set -tmpdir "D:/Dropbox/Thesis Project/Hardware/Polar1024/xst/projnav.tmp" 2 | set -xsthdpdir "D:/Dropbox/Thesis Project/Hardware/Polar1024/xst" 3 | run -compileonly yes 4 | -p xc7vx330t-2-ffg1157 5 | -top llr_test 6 | -opt_mode Speed 7 | -opt_level 1 8 | -power NO 9 | -iuc NO 10 | -keep_hierarchy No 11 | -netlist_hierarchy As_Optimized 12 | -rtlview Yes 13 | -glob_opt AllClockNets 14 | -read_cores YES 15 | -write_timing_constraints NO 16 | -cross_clock_analysis NO 17 | -hierarchy_separator / 18 | -bus_delimiter <> 19 | -case Maintain 20 | -slice_utilization_ratio 100 21 | -bram_utilization_ratio 100 22 | -dsp_utilization_ratio 100 23 | -lc Auto 24 | -reduce_control_sets Auto 25 | -fsm_extract YES -fsm_encoding Auto 26 | -safe_implementation No 27 | -fsm_style LUT 28 | -ram_extract Yes 29 | -ram_style Auto 30 | -rom_extract Yes 31 | -shreg_extract YES 32 | -rom_style Auto 33 | -auto_bram_packing NO 34 | -resource_sharing YES 35 | -async_to_sync NO 36 | -shreg_min_size 2 37 | -use_dsp48 Auto 38 | -iobuf YES 39 | -max_fanout 100000 40 | -bufg 32 41 | -register_duplication YES 42 | -register_balancing No 43 | -optimize_primitives NO 44 | -use_clock_enable Auto 45 | -use_sync_set Auto 46 | -use_sync_reset Auto 47 | -iob Auto 48 | -equivalent_register_removal YES 49 | -slice_utilization_ratio_maxmargin 5 50 | -ifn llr_test.prj 51 | -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_1024bits/pepExtractor.prj: -------------------------------------------------------------------------------- 1 | work "Encoder1024.vhd" 2 | work "MyPackage.vhd" 3 | -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_1024bits/system.bmm: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Spartak0s/Polar-Codes-Hardware-VHDL/41139d92e8d3e5550fba42f7f550bb1c36afce17/v1.0 Encode-Decoder no Fsm/Polar_1024bits/system.bmm -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_1024bits/system.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Company: 3 | -- Engineer: 4 | -- 5 | -- Create Date: 13:44:39 05/15/2016 6 | -- Design Name: 7 | -- Module Name: system - Behavioral 8 | -- Project Name: 9 | -- Target Devices: 10 | -- Tool versions: 11 | -- Description: 12 | -- 13 | -- Dependencies: 14 | -- 15 | -- Revision: 16 | -- Revision 0.01 - File Created 17 | -- Additional Comments: 18 | -- 19 | ---------------------------------------------------------------------------------- 20 | library IEEE; 21 | use IEEE.STD_LOGIC_1164.ALL; 22 | use work.all; 23 | use work.MyPackage.all; 24 | 25 | -- Uncomment the following library declaration if using 26 | -- arithmetic functions with Signed or Unsigned values 27 | --use IEEE.NUMERIC_STD.ALL; 28 | 29 | -- Uncomment the following library declaration if instantiating 30 | -- any Xilinx primitives in this code. 31 | --library UNISIM; 32 | --use UNISIM.VComponents.all; 33 | 34 | entity system is 35 | Port ( clk : in STD_LOGIC; 36 | boot : in STD_LOGIC; 37 | correct : out STD_LOGIC); 38 | end system; 39 | 40 | architecture Behavioral of system is 41 | constant correct_check: std_logic_vector(N/2-1 downto 0) := (others =>'0'); 42 | signal ce_decoder,ce_delay,input_enable: std_logic; 43 | signal in_generator,delay1,delay2,dec_out,check: std_logic_vector(N/2-1 downto 0); 44 | signal encoder_out: std_logic_vector(N-1 downto 0); 45 | signal llr_out: data; 46 | begin 47 | --FSM 48 | input_enable <= '1'; 49 | ce_decoder <= '1'; 50 | ce_delay <= '1'; 51 | check <= (delay2 xor dec_out); 52 | correct <= '1' when (check = correct_check) 53 | else '0'; 54 | --Generate Input 55 | U_Input_Generator: entity counter generic map(width => N/2) 56 | port map(clk => clk, 57 | rst => boot, 58 | count => input_enable, 59 | q => in_generator); 60 | --Delay Input 61 | U_Delay1: entity D_FF_gen generic map(width => N/2) port map(clk =>clk,rst =>boot,ce =>ce_delay,d => in_generator,q =>delay1); 62 | U_Delay2: entity D_FF_gen generic map(width => N/2) port map(clk =>clk,rst =>boot,ce =>ce_delay,d => delay1,q =>delay2); 63 | 64 | --Encoder 65 | U_Encoder: entity Encoder1024 port map(inputs =>in_generator, 66 | outputs =>encoder_out); 67 | --llr transform 68 | U_Channel: entity llr_test port map(inputs => encoder_out, 69 | outputs => llr_out); 70 | --Decoder 71 | U_Decoder: entity Decoder1024 port map(clk => clk, 72 | rst => boot, 73 | ce_inputs => ce_decoder, 74 | inputs => llr_out, 75 | outputs => dec_out); 76 | 77 | 78 | end Behavioral; 79 | 80 | -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_1024bits/system_isim_beh.exe: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Spartak0s/Polar-Codes-Hardware-VHDL/41139d92e8d3e5550fba42f7f550bb1c36afce17/v1.0 Encode-Decoder no Fsm/Polar_1024bits/system_isim_beh.exe -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_1024bits/system_isim_beh.wdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Spartak0s/Polar-Codes-Hardware-VHDL/41139d92e8d3e5550fba42f7f550bb1c36afce17/v1.0 Encode-Decoder no Fsm/Polar_1024bits/system_isim_beh.wdb -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_1024bits/test_encoder.vhd: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- 2 | -- Company: 3 | -- Engineer: 4 | -- 5 | -- Create Date: 14:33:19 04/02/2016 6 | -- Design Name: 7 | -- Module Name: D:/Dropbox/Thesis Project/Hardware/Polar1024/test_encoder.vhd 8 | -- Project Name: Polar1024 9 | -- Target Device: 10 | -- Tool versions: 11 | -- Description: 12 | -- 13 | -- VHDL Test Bench Created by ISE for module: Decoder1024 14 | -- 15 | -- Dependencies: 16 | -- 17 | -- Revision: 18 | -- Revision 0.01 - File Created 19 | -- Additional Comments: 20 | -- 21 | -- Notes: 22 | -- This testbench has been automatically generated using types std_logic and 23 | -- std_logic_vector for the ports of the unit under test. Xilinx recommends 24 | -- that these types always be used for the top-level I/O of a design in order 25 | -- to guarantee that the testbench will bind correctly to the post-implementation 26 | -- simulation model. 27 | -------------------------------------------------------------------------------- 28 | LIBRARY ieee; 29 | USE ieee.std_logic_1164.ALL; 30 | 31 | -- Uncomment the following library declaration if using 32 | -- arithmetic functions with Signed or Unsigned values 33 | --USE ieee.numeric_std.ALL; 34 | 35 | ENTITY test_encoder IS 36 | END test_encoder; 37 | 38 | ARCHITECTURE behavior OF test_encoder IS 39 | 40 | -- Component Declaration for the Unit Under Test (UUT) 41 | 42 | COMPONENT Decoder1024 43 | PORT( 44 | inputs : IN std_logic_vector(0 to 1023); 45 | clk : IN std_logic; 46 | outputs : OUT std_logic_vector(511 downto 0) 47 | ); 48 | END COMPONENT; 49 | 50 | 51 | --Inputs 52 | signal inputs : std_logic_vector(0 to 1023) := (others => '0'); 53 | signal clk : std_logic := '0'; 54 | 55 | --Outputs 56 | signal outputs : std_logic_vector(511 downto 0); 57 | 58 | -- Clock period definitions 59 | constant clk_period : time := 10 ns; 60 | 61 | BEGIN 62 | 63 | -- Instantiate the Unit Under Test (UUT) 64 | uut: Decoder1024 PORT MAP ( 65 | inputs => inputs, 66 | clk => clk, 67 | outputs => outputs 68 | ); 69 | 70 | -- Clock process definitions 71 | clk_process :process 72 | begin 73 | clk <= '0'; 74 | wait for clk_period/2; 75 | clk <= '1'; 76 | wait for clk_period/2; 77 | end process; 78 | 79 | 80 | -- Stimulus process 81 | stim_proc: process 82 | begin 83 | -- hold reset state for 100 ns. 84 | wait for 100 ns; 85 | 86 | wait for clk_period*10; 87 | 88 | -- insert stimulus here 89 | 90 | wait; 91 | end process; 92 | 93 | END; 94 | -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_1024bits/xlnx_auto_0_xdb/cst.xbcd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Spartak0s/Polar-Codes-Hardware-VHDL/41139d92e8d3e5550fba42f7f550bb1c36afce17/v1.0 Encode-Decoder no Fsm/Polar_1024bits/xlnx_auto_0_xdb/cst.xbcd -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_32bits/D_FF.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Company: 3 | -- Engineer: 4 | -- 5 | -- Create Date: 14:03:21 02/23/2016 6 | -- Design Name: 7 | -- Module Name: D_FF - Behavioral 8 | -- Project Name: 9 | -- Target Devices: 10 | -- Tool versions: 11 | -- Description: 12 | -- 13 | -- Dependencies: 14 | -- 15 | -- Revision: 16 | -- Revision 0.01 - File Created 17 | -- Additional Comments: 18 | -- 19 | ---------------------------------------------------------------------------------- 20 | library IEEE; 21 | use IEEE.STD_LOGIC_1164.ALL; 22 | use work.all; 23 | use work.MyPackage.all; 24 | 25 | -- Uncomment the following library declaration if using 26 | -- arithmetic functions with Signed or Unsigned values 27 | --use IEEE.NUMERIC_STD.ALL; 28 | 29 | -- Uncomment the following library declaration if instantiating 30 | -- any Xilinx primitives in this code. 31 | --library UNISIM; 32 | --use UNISIM.VComponents.all; 33 | 34 | entity D_FF_gen is 35 | generic(width: integer := K); 36 | port( 37 | clk : in std_logic; 38 | rst : in std_logic; 39 | ce : in std_logic; 40 | d : in std_logic_vector(width-1 downto 0); 41 | q : out std_logic_vector(width-1 downto 0)); 42 | end entity D_FF_gen; 43 | 44 | architecture Behavioral of D_FF_gen is 45 | begin 46 | process (clk) 47 | begin 48 | if rising_edge(clk) then 49 | if(rst = '1') then 50 | q <= (others => '0'); 51 | else 52 | if( ce = '1') then 53 | q <= d; 54 | end if; 55 | end if; 56 | end if; 57 | end process; 58 | end architecture Behavioral; 59 | 60 | -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_32bits/D_FF_1bit.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Company: 3 | -- Engineer: 4 | -- 5 | -- Create Date: 14:03:21 02/23/2016 6 | -- Design Name: 7 | -- Module Name: D_FF - Behavioral 8 | -- Project Name: 9 | -- Target Devices: 10 | -- Tool versions: 11 | -- Description: 12 | -- 13 | -- Dependencies: 14 | -- 15 | -- Revision: 16 | -- Revision 0.01 - File Created 17 | -- Additional Comments: 18 | -- 19 | ---------------------------------------------------------------------------------- 20 | library IEEE; 21 | use IEEE.STD_LOGIC_1164.ALL; 22 | use work.all; 23 | use work.MyPackage.all; 24 | 25 | -- Uncomment the following library declaration if using 26 | -- arithmetic functions with Signed or Unsigned values 27 | --use IEEE.NUMERIC_STD.ALL; 28 | 29 | -- Uncomment the following library declaration if instantiating 30 | -- any Xilinx primitives in this code. 31 | --library UNISIM; 32 | --use UNISIM.VComponents.all; 33 | 34 | entity D_FF_1bit is 35 | port( 36 | clk : in std_logic; 37 | rst : in std_logic; 38 | ce : in std_logic; 39 | d : in std_logic; 40 | q : out std_logic); 41 | end entity D_FF_1bit; 42 | 43 | architecture Behavioral of D_FF_1bit is 44 | begin 45 | process (clk) 46 | begin 47 | if rising_edge(clk) then 48 | if(rst = '1') then 49 | q <= '0'; 50 | else 51 | if( ce = '1') then 52 | q <= d; 53 | end if; 54 | end if; 55 | end if; 56 | end process; 57 | end architecture Behavioral; 58 | 59 | -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_32bits/D_FF_N.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Company: 3 | -- Engineer: 4 | -- 5 | -- Create Date: 14:03:21 02/23/2016 6 | -- Design Name: 7 | -- Module Name: D_FF - Behavioral 8 | -- Project Name: 9 | -- Target Devices: 10 | -- Tool versions: 11 | -- Description: 12 | -- 13 | -- Dependencies: 14 | -- 15 | -- Revision: 16 | -- Revision 0.01 - File Created 17 | -- Additional Comments: 18 | -- 19 | ---------------------------------------------------------------------------------- 20 | library IEEE; 21 | use IEEE.STD_LOGIC_1164.ALL; 22 | use work.all; 23 | use work.MyPackage.all; 24 | 25 | -- Uncomment the following library declaration if using 26 | -- arithmetic functions with Signed or Unsigned values 27 | --use IEEE.NUMERIC_STD.ALL; 28 | 29 | -- Uncomment the following library declaration if instantiating 30 | -- any Xilinx primitives in this code. 31 | --library UNISIM; 32 | --use UNISIM.VComponents.all; 33 | 34 | entity D_FF_N is 35 | port( 36 | clk : in std_logic; 37 | d : in llr; 38 | q : out llr); 39 | end entity D_FF_N; 40 | 41 | architecture Behavioral of D_FF_N is 42 | begin 43 | process (clk) 44 | begin 45 | if rising_edge(clk) then 46 | q <= d; 47 | end if; 48 | end process; 49 | end architecture Behavioral; 50 | 51 | -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_32bits/D_FF_beh.prj: -------------------------------------------------------------------------------- 1 | vhdl work "MyPackage.vhd" 2 | vhdl work "D_FF.vhd" 3 | -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_32bits/D_FF_en.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Company: 3 | -- Engineer: 4 | -- 5 | -- Create Date: 18:35:08 04/04/2016 6 | -- Design Name: 7 | -- Module Name: D_FF_en - Behavioral 8 | -- Project Name: 9 | -- Target Devices: 10 | -- Tool versions: 11 | -- Description: 12 | -- 13 | -- Dependencies: 14 | -- 15 | -- Revision: 16 | -- Revision 0.01 - File Created 17 | -- Additional Comments: 18 | -- 19 | ---------------------------------------------------------------------------------- 20 | library IEEE; 21 | use IEEE.STD_LOGIC_1164.ALL; 22 | use work.all; 23 | use work.MyPackage.all; 24 | -- Uncomment the following library declaration if using 25 | -- arithmetic functions with Signed or Unsigned values 26 | --use IEEE.NUMERIC_STD.ALL; 27 | 28 | -- Uncomment the following library declaration if instantiating 29 | -- any Xilinx primitives in this code. 30 | --library UNISIM; 31 | --use UNISIM.VComponents.all; 32 | 33 | entity D_FF_en is 34 | generic( width: integer := K); 35 | Port ( d : in STD_LOGIC_VECTOR (width-1 downto 0); 36 | q : out STD_LOGIC_VECTOR (width-1 downto 0); 37 | clk : in STD_LOGIC; 38 | en : in STD_LOGIC); 39 | end D_FF_en; 40 | 41 | architecture Behavioral of D_FF_en is 42 | 43 | begin 44 | process (clk) 45 | begin 46 | if (rising_edge(clk) and en='1') then 47 | q <= d; 48 | end if; 49 | end process; 50 | end architecture Behavioral; 51 | -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_32bits/D_FF_llr.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Company: 3 | -- Engineer: 4 | -- 5 | -- Create Date: 14:03:21 02/23/2016 6 | -- Design Name: 7 | -- Module Name: D_FF - Behavioral 8 | -- Project Name: 9 | -- Target Devices: 10 | -- Tool versions: 11 | -- Description: 12 | -- 13 | -- Dependencies: 14 | -- 15 | -- Revision: 16 | -- Revision 0.01 - File Created 17 | -- Additional Comments: 18 | -- 19 | ---------------------------------------------------------------------------------- 20 | library IEEE; 21 | use IEEE.STD_LOGIC_1164.ALL; 22 | use work.all; 23 | use work.MyPackage.all; 24 | 25 | -- Uncomment the following library declaration if using 26 | -- arithmetic functions with Signed or Unsigned values 27 | --use IEEE.NUMERIC_STD.ALL; 28 | 29 | -- Uncomment the following library declaration if instantiating 30 | -- any Xilinx primitives in this code. 31 | --library UNISIM; 32 | --use UNISIM.VComponents.all; 33 | 34 | entity D_FF_llr is 35 | port( 36 | clk : in std_logic; 37 | rst : in std_logic; 38 | d : in llr; 39 | q : out llr); 40 | end entity D_FF_llr; 41 | 42 | architecture Behavioral of D_FF_llr is 43 | begin 44 | process (clk,rst) 45 | begin 46 | if (rst='1') then 47 | q <= (others => '0'); 48 | elsif rising_edge(clk) then 49 | q <= d; 50 | end if; 51 | end process; 52 | end architecture Behavioral; 53 | 54 | -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_32bits/Decoder_isim_beh1.wdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Spartak0s/Polar-Codes-Hardware-VHDL/41139d92e8d3e5550fba42f7f550bb1c36afce17/v1.0 Encode-Decoder no Fsm/Polar_32bits/Decoder_isim_beh1.wdb -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_32bits/Encoder32_beh.prj: -------------------------------------------------------------------------------- 1 | vhdl work "MyPackage.vhd" 2 | vhdl work "Encoder.vhd" 3 | -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_32bits/F.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Company: 3 | -- Engineer: 4 | -- 5 | -- Create Date: 17:34:30 02/06/2016 6 | -- Design Name: 7 | -- Module Name: F - Behavioral 8 | -- Project Name: 9 | -- Target Devices: 10 | -- Tool versions: 11 | -- Description: 12 | -- 13 | -- Dependencies: 14 | -- 15 | -- Revision: 16 | -- Revision 0.01 - File Created 17 | -- Additional Comments: 18 | -- 19 | ---------------------------------------------------------------------------------- 20 | library IEEE; 21 | use IEEE.STD_LOGIC_1164.ALL; 22 | use IEEE.NUMERIC_STD.ALL; 23 | use work.MyPackage.all; 24 | 25 | -- Uncomment the following library declaration if using 26 | -- arithmetic functions with Signed or Unsigned values 27 | 28 | 29 | -- Uncomment the following library declaration if instantiating 30 | -- any Xilinx primitives in this code. 31 | --library UNISIM; 32 | --use UNISIM.VComponents.all; 33 | 34 | entity F is 35 | Port ( lamdaA : in llr; 36 | lamdaB : in llr; 37 | lamdaOut : out llr); 38 | end F; 39 | 40 | architecture Behavioral of F is 41 | signal positive_lamdaA, positive_lamdaB: signed(integer_part+fractional_part-1 downto 0); 42 | signal min: llr; 43 | signal sign: STD_LOGIC; 44 | begin 45 | sign <= lamdaA(sign_bit) xor lamdaB(sign_bit); 46 | positive_lamdaA <= signed(not(lamdaA)) + one when lamdaA(sign_bit) = '1' 47 | else signed(lamdaA); 48 | positive_lamdaB <= signed(not(lamdaB)) + one when lamdaB(sign_bit) = '1' 49 | else signed(lamdaB); 50 | min <= std_logic_vector(positive_lamdaA(integer_part+fractional_part-1 downto 0)) when positive_lamdaA < positive_lamdaB 51 | else std_logic_vector(positive_lamdaB(integer_part+fractional_part-1 downto 0)); 52 | lamdaOut <= min when sign = '0' 53 | else std_logic_vector(signed(not(min)) + one); 54 | 55 | end Behavioral; 56 | 57 | -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_32bits/G.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Company: 3 | -- Engineer: 4 | -- 5 | -- Create Date: 18:18:52 02/06/2016 6 | -- Design Name: 7 | -- Module Name: G - Behavioral 8 | -- Project Name: 9 | -- Target Devices: 10 | -- Tool versions: 11 | -- Description: 12 | -- 13 | -- Dependencies: 14 | -- 15 | -- Revision: 16 | -- Revision 0.01 - File Created 17 | -- Additional Comments: 18 | -- 19 | ---------------------------------------------------------------------------------- 20 | library IEEE; 21 | use IEEE.STD_LOGIC_1164.ALL; 22 | use IEEE.NUMERIC_STD.ALL; 23 | use work.MyPackage.all; 24 | 25 | -- Uncomment the following library declaration if using 26 | -- arithmetic functions with Signed or Unsigned values 27 | --use IEEE.NUMERIC_STD.ALL; 28 | 29 | -- Uncomment the following library declaration if instantiating 30 | -- any Xilinx primitives in this code. 31 | --library UNISIM; 32 | --use UNISIM.VComponents.all; 33 | 34 | entity G is 35 | Port ( lamdaA : in llr; 36 | lamdaB : in llr; 37 | s : in STD_LOGIC; 38 | lamdaOut : out llr); 39 | end G; 40 | 41 | architecture Behavioral of G is 42 | begin 43 | lamdaOut <= std_logic_vector(signed(lamdaA) + signed(lamdaB)) when s = '0' 44 | else std_logic_vector((signed(not(lamdaA)) + one) + signed(lamdaB)); 45 | 46 | end Behavioral; 47 | 48 | -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_32bits/IO_Input.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Company: 3 | -- Engineer: 4 | -- 5 | -- Create Date: 18:23:05 04/04/2016 6 | -- Design Name: 7 | -- Module Name: IO_Input - Behavioral 8 | -- Project Name: 9 | -- Target Devices: 10 | -- Tool versions: 11 | -- Description: 12 | -- 13 | -- Dependencies: 14 | -- 15 | -- Revision: 16 | -- Revision 0.01 - File Created 17 | -- Additional Comments: 18 | -- 19 | ---------------------------------------------------------------------------------- 20 | library IEEE; 21 | use IEEE.STD_LOGIC_1164.ALL; 22 | use work.all; 23 | use work.MyPackage.all; 24 | 25 | -- Uncomment the following library declaration if using 26 | -- arithmetic functions with Signed or Unsigned values 27 | --use IEEE.NUMERIC_STD.ALL; 28 | 29 | -- Uncomment the following library declaration if instantiating 30 | -- any Xilinx primitives in this code. 31 | --library UNISIM; 32 | --use UNISIM.VComponents.all; 33 | 34 | entity IO_Input is 35 | Port ( inputs : in STD_LOGIC_VECTOR (K-1 downto 0); 36 | clk : in std_logic; 37 | outputs : out STD_LOGIC_VECTOR (N/2-1 downto 0)); 38 | end IO_Input; 39 | 40 | architecture Behavioral of IO_Input is 41 | signal enable: std_logic_vector(NdivK-1 downto 0); 42 | begin 43 | 44 | 45 | Shift:if(NdivK-1)/=0 generate 46 | Shift_register: entity work.shift port map(clk,'0',enable); 47 | FF:for i in 0 to NdivK-1 generate 48 | FF_ins: entity work.D_FF_en port map(inputs,outputs((i*K)+K-1 downto i*K),clk,enable(i)); 49 | end generate FF; 50 | end generate Shift; 51 | 52 | 53 | No_Shift:if (NdivK-1)=0 generate 54 | FF_ins: entity work.D_FF_en port map(inputs,outputs(K-1 downto 0),clk,'1'); 55 | end generate No_Shift; 56 | 57 | 58 | 59 | 60 | end Behavioral; 61 | 62 | -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_32bits/IO_Outputs.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Company: 3 | -- Engineer: 4 | -- 5 | -- Create Date: 16:15:25 04/05/2016 6 | -- Design Name: 7 | -- Module Name: IO_Outputs - Behavioral 8 | -- Project Name: 9 | -- Target Devices: 10 | -- Tool versions: 11 | -- Description: 12 | -- 13 | -- Dependencies: 14 | -- 15 | -- Revision: 16 | -- Revision 0.01 - File Created 17 | -- Additional Comments: 18 | -- 19 | ---------------------------------------------------------------------------------- 20 | library IEEE; 21 | use IEEE.STD_LOGIC_1164.ALL; 22 | use work.all; 23 | use work.MyPackage.all; 24 | 25 | -- Uncomment the following library declaration if using 26 | -- arithmetic functions with Signed or Unsigned values 27 | --use IEEE.NUMERIC_STD.ALL; 28 | 29 | -- Uncomment the following library declaration if instantiating 30 | -- any Xilinx primitives in this code. 31 | --library UNISIM; 32 | --use UNISIM.VComponents.all; 33 | 34 | entity IO_Outputs is 35 | Port ( clk : in std_logic; 36 | inputs : in STD_LOGIC_VECTOR (N/2-1 downto 0); 37 | outputs : out STD_LOGIC_VECTOR (K-1 downto 0)); 38 | end IO_Outputs; 39 | 40 | architecture Behavioral of IO_Outputs is 41 | signal counter_out: std_logic_vector(NdivKbits-1 downto 0); 42 | begin 43 | 44 | Mux_counter: entity work.counter generic map(width => NdivKbits) port map(clk,'0','1',counter_out); 45 | MUX: entity work.mux port map(counter_out,inputs,outputs); 46 | 47 | 48 | 49 | end Behavioral; 50 | 51 | -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_32bits/MyPackage.vhd: -------------------------------------------------------------------------------- 1 | -- 2 | -- Package File Template 3 | -- 4 | -- Purpose: This package defines supplemental types, subtypes, 5 | -- constants, and functions 6 | -- 7 | -- To use any of the example code shown below, uncomment the lines and modify as necessary 8 | -- 9 | 10 | library IEEE; 11 | use IEEE.STD_LOGIC_1164.all; 12 | use IEEE.NUMERIC_STD.ALL; 13 | use ieee.MATH_REAL.all; 14 | 15 | package MyPackage is 16 | -- Declare functions and procedure 17 | -- 18 | -- function (signal : in ) return ; 19 | -- procedure ( : in ); 20 | -- 21 | 22 | -- Declare constants 23 | -- 24 | constant K : integer := 16; 25 | constant N : integer := 32; 26 | constant stages : integer := 5; 27 | constant num_of_partials : integer := stages * N; 28 | constant integer_part : integer := 5; 29 | constant fractional_part : integer := 2; 30 | constant sign_bit : integer := integer_part + fractional_part -1; 31 | constant one : signed(integer_part + fractional_part-1 downto 0) := (0=>'1',others=>'0'); 32 | -- 33 | subtype s_1d is std_logic_vector(0 to N/2-1); 34 | type s_2d is array (1 to stages) of s_1d; 35 | subtype llr is std_logic_vector(integer_part+fractional_part-1 downto 0); 36 | type data is array (0 to N-1) of llr; 37 | type llr_2d is array (0 to stages) of data; 38 | type llr2bit is array (1 downto 0) of llr; 39 | type llr2bit_int is array (1 downto 0) of signed(integer_part+fractional_part -1 downto 0); 40 | -- record 41 | -- : std_logic_vector( 7 downto 0); 42 | -- : std_logic; 43 | -- end record; 44 | -- 45 | 46 | 47 | end MyPackage; 48 | 49 | package body MyPackage is 50 | 51 | ---- Example 1 52 | -- function (signal : in ) return is 53 | -- variable : ; 54 | -- begin 55 | -- := xor ; 56 | -- return ; 57 | -- end ; 58 | 59 | ---- Example 2 60 | -- function (signal : in ; 61 | -- signal : in ) return is 62 | -- begin 63 | -- if ( = '1') then 64 | -- return ; 65 | -- else 66 | -- return 'Z'; 67 | -- end if; 68 | -- end ; 69 | 70 | ---- Procedure Example 71 | -- procedure ( : in ) is 72 | -- 73 | -- begin 74 | -- 75 | -- end ; 76 | 77 | end MyPackage; 78 | -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_32bits/_ngo/netlist.lst: -------------------------------------------------------------------------------- 1 | D:\Dropbox\Thesis Project\Hardware\v1.0 Encode-Decode no Fsm\Polar_32bits\system.ngc 1463320291 2 | OK 3 | -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_32bits/_xmsgs/map.xmsgs: -------------------------------------------------------------------------------- 1 | 2 | 7 | 8 | No environment variables are currently set. 9 | 10 | 11 | All of the single ended outputs in this design are using slew rate limited output drivers. The delay on speed critical single ended outputs can be dramatically reduced by designating them as fast outputs. 12 | 13 | 14 | 15 | 16 | -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_32bits/_xmsgs/ngdbuild.xmsgs: -------------------------------------------------------------------------------- 1 | 2 | 7 | 8 | 9 | 10 | -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_32bits/_xmsgs/par.xmsgs: -------------------------------------------------------------------------------- 1 | 2 | 7 | 8 | No user timing constraints were detected or you have set the option to ignore timing constraints ("par -x"). Place and Route will run in "Performance Evaluation Mode" to automatically improve the performance of all internal clocks in this design. Because there are not defined timing requirements, a timing score will not be reported in the PAR report in this mode. The PAR timing summary will list the performance achieved for each clock. Note: For the fastest runtime, set the effort level to "std". For best performance, set the effort level to "high". 9 | 10 | 11 | N/A entries in the Constraints List may indicate that the constraint is not analyzed due to the following: No paths covered by this constraint; Other constraints intersect with this constraint; or This constraint was disabled by a Path Tracing Control. Please run the Timespec Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI. 12 | 13 | 14 | 15 | -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_32bits/_xmsgs/trce.xmsgs: -------------------------------------------------------------------------------- 1 | 2 | 7 | 8 | No timing constraints found, doing default enumeration. 9 | 10 | To improve timing, see the Timing Closure User Guide (UG612). 11 | 12 | To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report. 13 | 14 | The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet. 15 | 16 | This architecture does not support a default System Jitter value, please add SYSTEM_JITTER constraint to the UCF to modify the Clock Uncertainty calculation. 17 | 18 | This architecture does not support 'Discrete Jitter' and 'Phase Error' calculations, these terms will be zero in the Clock Uncertainty calculation. Please make appropriate modification to SYSTEM_JITTER to account for the unsupported Discrete Jitter and Phase Error. 19 | 20 | 21 | 22 | -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_32bits/ananeosi.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use ieee.std_logic_signed.all; 4 | use ieee.numeric_std.all; 5 | 6 | entity ananeosi is 7 | port( eisodos1: in signed (31 downto 0); 8 | eisodos2: in signed (31 downto 0); 9 | eisodos3: in signed (31 downto 0); 10 | eksodos : out signed (31 downto 0) 11 | ); 12 | end entity; 13 | 14 | architecture struct of ananeosi is 15 | 16 | signal x,x1,x2,x3,temp,temp2 : signed (31 downto 0); 17 | constant c1 : signed (31 downto 0):= "10000000000000000000000000000000"; 18 | constant c2 : signed (31 downto 0):= "01111111111111111111111111111111"; 19 | constant c3 : signed (31 downto 0):= "10011001000010001011000011011111"; 20 | 21 | begin 22 | x1<=eisodos1 and c1; 23 | x2<=eisodos2 and c2; 24 | 25 | x <= x1 or x2; 26 | x3<=x srl 1; 27 | temp <= eisodos3 xor x3; 28 | temp2<=temp xor c3; 29 | eksodos<=temp2 when temp(0)='1' else temp; 30 | end struct; 31 | -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_32bits/cntr_fifo.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use ieee.std_logic_unsigned.all; 4 | 5 | 6 | entity cntr_fifo is 7 | 8 | generic(n: natural :=3); 9 | port( clock: in std_logic; 10 | reset: in std_logic; 11 | hold : in std_logic; 12 | q: out std_logic_vector(n-1 downto 0); 13 | cc: in std_logic 14 | ); 15 | end cntr_fifo; 16 | 17 | 18 | architecture behv of cntr_fifo is 19 | 20 | signal count: std_logic_vector(n-1 downto 0); 21 | 22 | begin 23 | 24 | 25 | process(clock) 26 | begin 27 | 28 | 29 | if (clock='1' and clock'event) then 30 | if reset = '0' then 31 | count<= "000"; 32 | else 33 | if (hold = '1')then 34 | if count = "100" then 35 | count<="010"; 36 | else 37 | count <= count + 1; 38 | end if; 39 | end if; 40 | end if; 41 | end if; 42 | end process; 43 | q <=count; 44 | end behv; -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_32bits/counter.lso: -------------------------------------------------------------------------------- 1 | work 2 | -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_32bits/counter.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Company: 3 | -- Engineer: 4 | -- 5 | -- Create Date: 15:06:44 04/06/2016 6 | -- Design Name: 7 | -- Module Name: counter - Behavioral 8 | -- Project Name: 9 | -- Target Devices: 10 | -- Tool versions: 11 | -- Description: 12 | -- 13 | -- Dependencies: 14 | -- 15 | -- Revision: 16 | -- Revision 0.01 - File Created 17 | -- Additional Comments: 18 | -- 19 | ---------------------------------------------------------------------------------- 20 | library IEEE; 21 | use IEEE.STD_LOGIC_1164.ALL; 22 | use work.MyPackage.all; 23 | use ieee.std_logic_unsigned.all; 24 | -- Uncomment the following library declaration if using 25 | -- arithmetic functions with Signed or Unsigned values 26 | --use IEEE.NUMERIC_STD.ALL; 27 | 28 | -- Uncomment the following library declaration if instantiating 29 | -- any Xilinx primitives in this code. 30 | --library UNISIM; 31 | --use UNISIM.VComponents.all; 32 | 33 | entity counter is 34 | generic (width : integer := 8); 35 | Port ( clk : in STD_LOGIC; 36 | rst : in STD_LOGIC; 37 | count : in STD_LOGIC; 38 | Q : out STD_LOGIC_VECTOR(width-1 downto 0)); 39 | end counter; 40 | 41 | architecture behv of counter is 42 | signal Pre_Q: std_logic_vector(width-1 downto 0):= (others=>'0'); 43 | begin 44 | 45 | -- behavior describe the counter 46 | 47 | process(clk) 48 | begin 49 | if(rising_edge(clk)) then 50 | if rst = '1' then 51 | Pre_Q <= (others =>'0'); 52 | else 53 | if count = '1' then 54 | Pre_Q <= Pre_Q + 1; 55 | end if; 56 | end if; 57 | end if; 58 | end process; 59 | 60 | -- concurrent assignment statement 61 | Q <= Pre_Q; 62 | 63 | end behv; 64 | 65 | -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_32bits/counterNdivKbits.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Company: 3 | -- Engineer: 4 | -- 5 | -- Create Date: 15:06:44 04/06/2016 6 | -- Design Name: 7 | -- Module Name: counter - Behavioral 8 | -- Project Name: 9 | -- Target Devices: 10 | -- Tool versions: 11 | -- Description: 12 | -- 13 | -- Dependencies: 14 | -- 15 | -- Revision: 16 | -- Revision 0.01 - File Created 17 | -- Additional Comments: 18 | -- 19 | ---------------------------------------------------------------------------------- 20 | library IEEE; 21 | use IEEE.STD_LOGIC_1164.ALL; 22 | use work.MyPackage.all; 23 | use ieee.std_logic_unsigned.all; 24 | -- Uncomment the following library declaration if using 25 | -- arithmetic functions with Signed or Unsigned values 26 | --use IEEE.NUMERIC_STD.ALL; 27 | 28 | -- Uncomment the following library declaration if instantiating 29 | -- any Xilinx primitives in this code. 30 | --library UNISIM; 31 | --use UNISIM.VComponents.all; 32 | 33 | entity counter is 34 | 35 | Port ( clk : in STD_LOGIC; 36 | clear : in STD_LOGIC; 37 | count : in STD_LOGIC; 38 | Q : out STD_LOGIC_VECTOR(N/2-1 downto 0)); 39 | end counter; 40 | 41 | architecture behv of counter is 42 | signal Pre_Q: std_logic_vector(N/2-1 downto 0):= (others=>'0'); 43 | begin 44 | 45 | -- behavior describe the counter 46 | 47 | process(clk, count, clear) 48 | begin 49 | if clear = '1' then 50 | Pre_Q <= (others =>'0'); 51 | elsif (clk='1' and clk'event) then 52 | if count = '1' then 53 | Pre_Q <= Pre_Q + 1; 54 | end if; 55 | end if; 56 | end process; 57 | 58 | -- concurrent assignment statement 59 | Q <= Pre_Q; 60 | 61 | end behv; 62 | 63 | -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_32bits/encoder_channel_vhd.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | library Encoder_2K_mqam; 3 | use Encoder_2K_mqam.all; 4 | use ieee.std_logic_1164.all; 5 | use ieee.std_logic_signed.all; 6 | use ieee.std_logic_unsigned.all; 7 | use ieee.numeric_std.all; 8 | 9 | 10 | entity encoder_top_entity is 11 | port (clk:in std_logic; 12 | rst:in std_logic; 13 | snr:in std_logic_vector(5 downto 0); 14 | feedbk:in std_logic; 15 | lfsr_out1:out std_logic_vector(7 downto 0); 16 | fram_pass:out std_logic_vector(31 downto 0); 17 | data_for_dec:out std_logic_vector(31 downto 0); 18 | lfsr_init_state:out std_logic_vector(31 downto 0)); 19 | end encoder_top_entity; 20 | 21 | 22 | 23 | architecture struct of encoder_top_entity is 24 | 25 | 26 | component encoder is 27 | port (clk:in std_logic; 28 | rst:in std_logic; 29 | snr:in std_logic_vector(5 downto 0); 30 | dec_fin1:in std_logic; 31 | start:in std_logic; 32 | lfsr_out1:out std_logic_vector(7 downto 0); 33 | fram_pass:out std_logic_vector(35 downto 0); 34 | doutready:out std_logic; 35 | dfordec1:out std_logic_vector(5 downto 0); 36 | dfordec2:out std_logic_vector(5 downto 0)); 37 | --lfsr_init_state:out std_logic_vector(7 downto 0)); 38 | end component; 39 | 40 | component uutfsm is 41 | port ( clk : in std_logic; 42 | rst : in std_logic; 43 | feedbk:in std_logic; 44 | dec_fin:out std_logic; 45 | conti : out std_logic 46 | ); 47 | end component; 48 | 49 | component mydff is 50 | port( clk : in std_logic; 51 | rst : in std_logic; 52 | eisod : in std_logic; 53 | deigma : out std_logic 54 | ); 55 | end component; 56 | 57 | component myreg3 is 58 | generic(n: integer:=40); 59 | port( clk : in std_logic; 60 | rst : in std_logic; 61 | eisod : in std_logic_vector (n-1 downto 0); 62 | deigma : out std_logic_vector (n-1 downto 0) 63 | ); 64 | end component; 65 | 66 | signal rst1, start,decoder_fin,doutready1:std_logic; 67 | signal dllr0,dllr1:std_logic_vector(5 downto 0); 68 | signal fram_pass_temp:std_logic_vector(35 downto 0); 69 | --signal lfsr_out1_temp:std_logic_vector(7 downto 0); 70 | --signal lfsr_init_state_temp: std_logic_vector(31 downto 0); 71 | 72 | 73 | begin 74 | 75 | 76 | rst1<= not rst; 77 | 78 | 79 | U_fm1 : uutfsm port map (clk=>clk, 80 | rst=>rst1, 81 | feedbk=>feedbk, 82 | dec_fin=>decoder_fin, 83 | conti=>start 84 | ); 85 | 86 | 87 | U_enc: encoder port map(clk=>clk, 88 | rst=>rst1, 89 | snr=>snr, 90 | dec_fin1=>decoder_fin, 91 | start=>start, 92 | lfsr_out1=>lfsr_out1, 93 | fram_pass=>fram_pass_temp, 94 | doutready=>doutready1, 95 | dfordec1=>dllr0, 96 | dfordec2=>dllr1); 97 | --lfsr_init_state=>lfsr_init_state_temp); 98 | 99 | fram_pass<=fram_pass_temp(31 downto 0); 100 | data_for_dec<="0000000000000000000"&dllr0&dllr1&doutready1; 101 | --lfsr_init_state<="000000000000000000000000"&lfsr_init_state_temp; 102 | --doutready<=doutready1; 103 | 104 | end struct; 105 | -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_32bits/fast.vhd: -------------------------------------------------------------------------------- 1 | library IEEE; 2 | use IEEE.std_logic_1164.all; 3 | use IEEE.numeric_std.all; 4 | 5 | 6 | entity fast is 7 | generic ( 8 | n: integer := 8; 9 | k: integer := 4 10 | ); 11 | port ( clk : in std_logic; 12 | rst : in std_logic; 13 | wen : in std_logic; 14 | a: in signed (n-1 downto 0); 15 | b: in signed (n-1 downto 0); 16 | p: out signed (2*n-1 downto 0) 17 | ); 18 | end fast; 19 | 20 | architecture struct of fast is 21 | 22 | 23 | component myreg is 24 | generic(n: integer:=40); 25 | port( clk : in std_logic; 26 | rst : in std_logic; 27 | wen : in std_logic; 28 | eisod : in signed (n-1 downto 0); 29 | deigma : out signed (n-1 downto 0) 30 | ); 31 | end component; 32 | 33 | signal signextpLL: signed (k-1 downto 0); 34 | signal signextpHL:signed (k-1 downto 0); 35 | signal signextrlow:signed (k-1 downto 0); 36 | 37 | signal klow: signed (k-1 downto 0); 38 | -- 39 | signal pLL,pLL2: signed (2*k+1 downto 0); 40 | signal pHL,pHL2: signed (n downto 0); 41 | signal pLH,pLH2: signed (n downto 0); 42 | signal pHH,pHH2: signed (2*(n -k) - 1 downto 0); 43 | -- 44 | 45 | signal rlow: signed (k + n + 1 downto 0); 46 | signal rhigh: signed ( n + k downto 0); 47 | --- 48 | signal alow, blow : signed (k downto 0); 49 | signal ahigh, bhigh: signed (n- k-1 downto 0); 50 | -- 51 | signal result: signed(2*n+1 downto 0); 52 | begin 53 | 54 | alow <= '0' & a( k -1 downto 0); -- k+1 bits 55 | ahigh <= a(n - 1 downto k); -- n-k bits 56 | 57 | blow <= '0' & b(k -1 downto 0); -- k+1 bits 58 | bhigh <= b(n - 1 downto k); -- n-k bits 59 | 60 | pLL <= alow * blow ; -- 2(k+1) bits 61 | pLH <= alow * bhigh; -- n-k+k+1=n+1 bits 62 | pHL <= ahigh * blow; -- n-k+k+1=n+1 bits 63 | pHH <= ahigh * bhigh; -- 2(n-k) bits 64 | 65 | U_rg1: myreg generic map ( 2*(k+1)) port map (clk=>clk,rst=>rst,wen=>wen,eisod=>pLL,deigma=>pLL2); 66 | U_rg2: myreg generic map ( n+1) port map (clk=>clk,rst=>rst,wen=>wen,eisod=>pLH,deigma=>pLH2); 67 | U_rg3: myreg generic map ( n+1) port map (clk=>clk,rst=>rst,wen=>wen,eisod=>pHL,deigma=>pHL2); 68 | U_rg4: myreg generic map ( 2*(n-k)) port map (clk=>clk,rst=>rst,wen=>wen,eisod=>pHH,deigma=>pHH2); 69 | --------------pipelinestage 1: delay partial products 70 | 71 | klow <= (others => '0'); -- k bits 72 | signextpLL <= (others => '0'); 73 | signextpHL <= (others => pHL2(n)); 74 | 75 | 76 | 77 | rlow <= (pLH2(n) & pLH2 & klow) + (signextpLL & pLL2) ; -- 62 bits 78 | 79 | rhigh <= (pHH2(2*(n -k) - 1) & pHH2 & klow )+ ( signextpHL & pHL2) ; -- 61 bits 80 | 81 | --------------pipelinestage 2: delay partial sums 82 | 83 | signextrlow<= ( others =>rlow(n+k+1)); 84 | 85 | result <= ( rhigh(n+k) & rhigh & klow) + ( signextrlow & rlow); 86 | 87 | p <= result( 2*n-1 downto 0); 88 | 89 | --------------pipelinestage 3:?????? 90 | 91 | end architecture struct; 92 | -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_32bits/fuse.xmsgs: -------------------------------------------------------------------------------- 1 | 2 | 7 | 8 | 9 | 10 | -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_32bits/fuseRelaunch.cmd: -------------------------------------------------------------------------------- 1 | -intstyle "ise" -incremental -o "D:/Dropbox/Thesis Project/Hardware/v1.0 Encode-Decoder no Fsm/Polar_32bits/system_isim_beh.exe" -prj "D:/Dropbox/Thesis Project/Hardware/v1.0 Encode-Decoder no Fsm/Polar_32bits/system_beh.prj" "work.system" 2 | -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_32bits/isim.cmd: -------------------------------------------------------------------------------- 1 | onerror {resume} 2 | wave add / 3 | run 1000 ns; 4 | -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_32bits/isim/isim_usage_statistics.html: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 |
ISim Statistics
Xilinx HDL Libraries Used=ieee
Fuse Resource Usage=1045 ms, 38368 KB
Total Signals=1163
Total Nets=3559
Total Blocks=286
Total Processes=683
Total Simulation Time=1613900 ps
Simulation Resource Usage=9.36006 sec, 493752 KB
Simulation Mode=gui
Hardware CoSim=0
17 | -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_32bits/isim/pn_info: -------------------------------------------------------------------------------- 1 | 14.2 2 | -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_32bits/isim/precompiled.exe.sim/ieee/p_1242562249.didat: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Spartak0s/Polar-Codes-Hardware-VHDL/41139d92e8d3e5550fba42f7f550bb1c36afce17/v1.0 Encode-Decoder no Fsm/Polar_32bits/isim/precompiled.exe.sim/ieee/p_1242562249.didat -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_32bits/isim/precompiled.exe.sim/ieee/p_1242562249.nt64.obj: -------------------------------------------------------------------------------- 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Fsm/Polar_32bits/isim/system_isim_beh.exe.sim/work/a_3959846087_3212880686.didat: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Spartak0s/Polar-Codes-Hardware-VHDL/41139d92e8d3e5550fba42f7f550bb1c36afce17/v1.0 Encode-Decoder no Fsm/Polar_32bits/isim/system_isim_beh.exe.sim/work/a_3959846087_3212880686.didat -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_32bits/isim/system_isim_beh.exe.sim/work/a_3959846087_3212880686.nt64.obj: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Spartak0s/Polar-Codes-Hardware-VHDL/41139d92e8d3e5550fba42f7f550bb1c36afce17/v1.0 Encode-Decoder no Fsm/Polar_32bits/isim/system_isim_beh.exe.sim/work/a_3959846087_3212880686.nt64.obj -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no 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Fsm/Polar_32bits/isim/system_isim_beh.exe.sim/work/p_4053066488.c: -------------------------------------------------------------------------------- 1 | /**********************************************************************/ 2 | /* ____ ____ */ 3 | /* / /\/ / */ 4 | /* /___/ \ / */ 5 | /* \ \ \/ */ 6 | /* \ \ Copyright (c) 2003-2009 Xilinx, Inc. */ 7 | /* / / All Right Reserved. */ 8 | /* /---/ /\ */ 9 | /* \ \ / \ */ 10 | /* \___\/\___\ */ 11 | /***********************************************************************/ 12 | 13 | /* This file is designed for use with ISim build 0xa0883be4 */ 14 | 15 | #define XSI_HIDE_SYMBOL_SPEC true 16 | #include "xsi.h" 17 | #include 18 | #ifdef __GNUC__ 19 | #include 20 | #else 21 | #include 22 | #define alloca _alloca 23 | #endif 24 | 25 | 26 | 27 | 28 | void ieee_p_2592010699_sub_3130575329_503743352(); 29 | 30 | void ieee_p_2592010699_sub_3130575329_503743352(); 31 | 32 | extern void work_p_4053066488_init() 33 | { 34 | xsi_register_didat("work_p_4053066488", "isim/system_isim_beh.exe.sim/work/p_4053066488.didat"); 35 | xsi_register_resolution_function(1, 2, (void *)ieee_p_2592010699_sub_3130575329_503743352, 5); 36 | xsi_register_resolution_function(4, 2, (void *)ieee_p_2592010699_sub_3130575329_503743352, 5); 37 | } 38 | -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_32bits/isim/system_isim_beh.exe.sim/work/p_4053066488.didat: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Spartak0s/Polar-Codes-Hardware-VHDL/41139d92e8d3e5550fba42f7f550bb1c36afce17/v1.0 Encode-Decoder no Fsm/Polar_32bits/isim/system_isim_beh.exe.sim/work/p_4053066488.didat -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_32bits/isim/system_isim_beh.exe.sim/work/p_4053066488.nt64.obj: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Spartak0s/Polar-Codes-Hardware-VHDL/41139d92e8d3e5550fba42f7f550bb1c36afce17/v1.0 Encode-Decoder no Fsm/Polar_32bits/isim/system_isim_beh.exe.sim/work/p_4053066488.nt64.obj -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_32bits/isim/system_isim_beh.exe.sim/work/system_isim_beh.exe_main.c: -------------------------------------------------------------------------------- 1 | /**********************************************************************/ 2 | /* ____ ____ */ 3 | /* / /\/ / */ 4 | /* /___/ \ / */ 5 | /* \ \ \/ */ 6 | /* \ \ Copyright (c) 2003-2009 Xilinx, Inc. */ 7 | /* / / All Right Reserved. */ 8 | /* /---/ /\ */ 9 | /* \ \ / \ */ 10 | /* \___\/\___\ */ 11 | /***********************************************************************/ 12 | 13 | #include "xsi.h" 14 | 15 | struct XSI_INFO xsi_info; 16 | 17 | char *IEEE_P_2592010699; 18 | char *STD_STANDARD; 19 | char *IEEE_P_1242562249; 20 | char *IEEE_P_3972351953; 21 | char *WORK_P_4053066488; 22 | char *IEEE_P_3620187407; 23 | char *IEEE_P_3499444699; 24 | 25 | 26 | int main(int argc, char **argv) 27 | { 28 | xsi_init_design(argc, argv); 29 | xsi_register_info(&xsi_info); 30 | 31 | xsi_register_min_prec_unit(-12); 32 | ieee_p_2592010699_init(); 33 | ieee_p_1242562249_init(); 34 | ieee_p_3972351953_init(); 35 | work_p_4053066488_init(); 36 | ieee_p_3499444699_init(); 37 | ieee_p_3620187407_init(); 38 | work_a_3289945837_1142133938_init(); 39 | work_a_2064211777_3212880686_init(); 40 | work_a_1881823395_3212880686_init(); 41 | work_a_0515771138_3212880686_init(); 42 | work_a_3959846087_3212880686_init(); 43 | work_a_1911451838_3212880686_init(); 44 | work_a_1721066749_3212880686_init(); 45 | work_a_0422964305_3212880686_init(); 46 | work_a_4250923597_3212880686_init(); 47 | work_a_2263464102_3212880686_init(); 48 | work_a_2933281589_3212880686_init(); 49 | 50 | 51 | xsi_register_tops("work_a_2933281589_3212880686"); 52 | 53 | IEEE_P_2592010699 = xsi_get_engine_memory("ieee_p_2592010699"); 54 | xsi_register_ieee_std_logic_1164(IEEE_P_2592010699); 55 | STD_STANDARD = xsi_get_engine_memory("std_standard"); 56 | IEEE_P_1242562249 = xsi_get_engine_memory("ieee_p_1242562249"); 57 | IEEE_P_3972351953 = xsi_get_engine_memory("ieee_p_3972351953"); 58 | WORK_P_4053066488 = xsi_get_engine_memory("work_p_4053066488"); 59 | IEEE_P_3620187407 = xsi_get_engine_memory("ieee_p_3620187407"); 60 | IEEE_P_3499444699 = xsi_get_engine_memory("ieee_p_3499444699"); 61 | 62 | return xsi_run_simulation(argc, argv); 63 | 64 | } 65 | -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_32bits/isim/system_isim_beh.exe.sim/work/system_isim_beh.exe_main.nt64.obj: -------------------------------------------------------------------------------- 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Fsm/Polar_32bits/isim/work/g.vdb -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_32bits/isim/work/llr_test.vdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Spartak0s/Polar-Codes-Hardware-VHDL/41139d92e8d3e5550fba42f7f550bb1c36afce17/v1.0 Encode-Decoder no Fsm/Polar_32bits/isim/work/llr_test.vdb -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_32bits/isim/work/mypackage.vdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Spartak0s/Polar-Codes-Hardware-VHDL/41139d92e8d3e5550fba42f7f550bb1c36afce17/v1.0 Encode-Decoder no Fsm/Polar_32bits/isim/work/mypackage.vdb -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_32bits/isim/work/partialsumgenerator.vdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Spartak0s/Polar-Codes-Hardware-VHDL/41139d92e8d3e5550fba42f7f550bb1c36afce17/v1.0 Encode-Decoder no Fsm/Polar_32bits/isim/work/partialsumgenerator.vdb -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_32bits/isim/work/system.vdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Spartak0s/Polar-Codes-Hardware-VHDL/41139d92e8d3e5550fba42f7f550bb1c36afce17/v1.0 Encode-Decoder no Fsm/Polar_32bits/isim/work/system.vdb -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_32bits/llr2_to_channel.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Company: 3 | -- Engineer: 4 | -- 5 | -- Create Date: 14:27:04 04/22/2016 6 | -- Design Name: 7 | -- Module Name: llr_test - Behavioral 8 | -- Project Name: 9 | -- Target Devices: 10 | -- Tool versions: 11 | -- Description: 12 | -- 13 | -- Dependencies: 14 | -- 15 | -- Revision: 16 | -- Revision 0.01 - File Created 17 | -- Additional Comments: 18 | -- 19 | ---------------------------------------------------------------------------------- 20 | library IEEE; 21 | use IEEE.STD_LOGIC_1164.ALL; 22 | use work.all; 23 | use work.MyPackage.all; 24 | 25 | -- Uncomment the following library declaration if using 26 | -- arithmetic functions with Signed or Unsigned values 27 | --use IEEE.NUMERIC_STD.ALL; 28 | 29 | -- Uncomment the following library declaration if instantiating 30 | -- any Xilinx primitives in this code. 31 | --library UNISIM; 32 | --use UNISIM.VComponents.all; 33 | 34 | entity llr2_to_channel is 35 | Port (inputs: in std_logic_vector(1 downto 0); 36 | outputs: out data); 37 | end llr2_to_channel; 38 | 39 | architecture Behavioral of llr2_to_channel is 40 | constant pos_llr : std_logic_vector(integer_part + fractional_part -1 downto 0):= "00010100"; -- +7 41 | constant neg_llr : std_logic_vector(integer_part + fractional_part -1 downto 0):= "11101100"; -- -7 42 | begin 43 | Decision: 44 | for i in 0 to N-1 generate 45 | Decision1: 46 | outputs(i) <= pos_llr when inputs(i)='0' 47 | else neg_llr; 48 | end generate Decision; 49 | end Behavioral; 50 | 51 | -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_32bits/llr_test.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Company: 3 | -- Engineer: 4 | -- 5 | -- Create Date: 14:27:04 04/22/2016 6 | -- Design Name: 7 | -- Module Name: llr_test - Behavioral 8 | -- Project Name: 9 | -- Target Devices: 10 | -- Tool versions: 11 | -- Description: 12 | -- 13 | -- Dependencies: 14 | -- 15 | -- Revision: 16 | -- Revision 0.01 - File Created 17 | -- Additional Comments: 18 | -- 19 | ---------------------------------------------------------------------------------- 20 | library IEEE; 21 | use IEEE.STD_LOGIC_1164.ALL; 22 | use work.all; 23 | use work.MyPackage.all; 24 | 25 | -- Uncomment the following library declaration if using 26 | -- arithmetic functions with Signed or Unsigned values 27 | --use IEEE.NUMERIC_STD.ALL; 28 | 29 | -- Uncomment the following library declaration if instantiating 30 | -- any Xilinx primitives in this code. 31 | --library UNISIM; 32 | --use UNISIM.VComponents.all; 33 | 34 | entity llr_test is 35 | Port (inputs: in std_logic_vector(N-1 downto 0); 36 | outputs: out data); 37 | end llr_test; 38 | 39 | architecture Behavioral of llr_test is 40 | constant pos_llr : std_logic_vector(integer_part + fractional_part -1 downto 0):= (0 => '1', others=>'0'); -- +1 41 | constant neg_llr : std_logic_vector(integer_part + fractional_part -1 downto 0):= (others=> '1'); -- -1 42 | begin 43 | Decision: 44 | for i in 0 to N-1 generate 45 | Decision1: 46 | outputs(i) <= pos_llr when inputs(i)='0' 47 | else neg_llr; 48 | end generate Decision; 49 | end Behavioral; 50 | 51 | -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_32bits/llr_test_beh.prj: -------------------------------------------------------------------------------- 1 | vhdl work "MyPackage.vhd" 2 | vhdl work "llr_test.vhd" 3 | -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_32bits/mac.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use ieee.std_logic_signed.all; 4 | use ieee.numeric_std.all; 5 | 6 | entity mac is 7 | generic(n: integer:=40); 8 | port ( 9 | clk : in std_logic; 10 | rst : in std_logic; 11 | wen1 : in std_logic; 12 | wen2 : in std_logic; 13 | a : in signed (n-1 downto 0); 14 | x : in signed (n-1 downto 0); 15 | c : in signed (2*n-1 downto 0); 16 | s : out signed (2*n-1 downto 0) 17 | ); 18 | end mac; 19 | 20 | architecture struct of mac is 21 | 22 | signal p,p1: signed (2*n-1 downto 0); 23 | 24 | component fast is 25 | generic ( 26 | n: integer := 8; 27 | k: integer := 4 28 | ); 29 | port ( clk : in std_logic; 30 | rst : in std_logic; 31 | wen : in std_logic; 32 | a: in signed (n-1 downto 0); 33 | b: in signed (n-1 downto 0); 34 | p: out signed (2*n-1 downto 0) 35 | ); 36 | end component; 37 | 38 | begin 39 | 40 | 41 | U_ml1: fast generic map (n=>n,k=>(n/2)) port map (clk=>clk,rst=>rst,wen=>wen2,a=>a,b=>x,p=>p); 42 | 43 | pr1:process (clk) 44 | begin 45 | if clk='1' and clk'event then 46 | if rst='0' then 47 | p1 <=(others => '0'); 48 | elsif (wen1='1') then 49 | p1 <= p; 50 | end if; 51 | end if; 52 | end process; 53 | 54 | s<=p1+c; 55 | 56 | end struct; 57 | -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_32bits/mux.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Company: 3 | -- Engineer: 4 | -- 5 | -- Create Date: 16:19:54 04/05/2016 6 | -- Design Name: 7 | -- Module Name: mux - Behavioral 8 | -- Project Name: 9 | -- Target Devices: 10 | -- Tool versions: 11 | -- Description: 12 | -- 13 | -- Dependencies: 14 | -- 15 | -- Revision: 16 | -- Revision 0.01 - File Created 17 | -- Additional Comments: 18 | -- 19 | ---------------------------------------------------------------------------------- 20 | library IEEE; 21 | use IEEE.STD_LOGIC_1164.ALL; 22 | use work.all; 23 | use work.MyPackage.all; 24 | 25 | -- Uncomment the following library declaration if using 26 | -- arithmetic functions with Signed or Unsigned values 27 | use IEEE.NUMERIC_STD.ALL; 28 | 29 | -- Uncomment the following library declaration if instantiating 30 | -- any Xilinx primitives in this code. 31 | --library UNISIM; 32 | --use UNISIM.VComponents.all; 33 | 34 | entity mux is 35 | generic (in_width : integer := (N/2)*(integer_part+fractional_part); 36 | out_width : integer :=(integer_part+fractional_part); 37 | sel_width : integer := Ndiv2bits); 38 | Port ( sel : in std_logic_vector(sel_width-1 downto 0); 39 | inputs : in STD_LOGIC_VECTOR (in_width-1 downto 0); 40 | outputs : out STD_LOGIC_VECTOR (out_width-1 downto 0)); 41 | end mux; 42 | 43 | architecture Behavioral of mux is 44 | begin 45 | 46 | process(sel,inputs) is 47 | constant in_div_out : integer := in_width /out_width; 48 | variable tmp : std_logic_vector(out_width-1 downto 0); 49 | begin 50 | for i in 0 to in_div_out-1 loop 51 | if i = unsigned(sel) then 52 | tmp := inputs(((out_width-1)+i*out_width) downto (i*out_width)); 53 | end if; 54 | end loop; 55 | outputs <= tmp; 56 | end process; 57 | 58 | 59 | 60 | 61 | end Behavioral; 62 | 63 | -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_32bits/myawgn.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use ieee.std_logic_signed.all; 4 | use ieee.numeric_std.all; 5 | 6 | 7 | entity myawgn is 8 | port( clk : in std_logic; 9 | rst : in std_logic; 10 | fre : in std_logic; 11 | ready : out std_logic; 12 | deigma1 : out signed (39 downto 0); 13 | deigma2 : out signed (39 downto 0) 14 | ); 15 | end entity; 16 | 17 | 18 | architecture struct of myawgn is 19 | 20 | component BoxMuller is 21 | port( clk : in std_logic; 22 | rst : in std_logic; 23 | wen : in std_logic; 24 | eisodos1: in signed (31 downto 0); 25 | eisodos2: in signed (31 downto 0); 26 | eksodos : out signed (39 downto 0) 27 | ); 28 | end component; 29 | 30 | component mt2 is 31 | port( clk : in std_logic; 32 | rst : in std_logic; 33 | freeze : in std_logic; 34 | running : out std_logic; 35 | frozen : out std_logic; 36 | tixaios1 : out signed (31 downto 0); 37 | tixaios2 : out signed (31 downto 0); 38 | tixaios3 : out signed (31 downto 0); 39 | tixaios4 : out signed (31 downto 0) 40 | ); 41 | end component; 42 | 43 | component myreg is 44 | generic(n: integer:=40); 45 | port( clk : in std_logic; 46 | rst : in std_logic; 47 | wen : in std_logic; 48 | eisod : in signed (n-1 downto 0); 49 | deigma : out signed (n-1 downto 0) 50 | ); 51 | 52 | end component; 53 | 54 | component mydff2 is 55 | port( clk : in std_logic; 56 | rst : in std_logic; 57 | wen : in std_logic; 58 | eisod : in std_logic; 59 | deigma : out std_logic 60 | ); 61 | end component; 62 | 63 | signal arithmos1,arithmos2,arithmos3,arithmos4: signed (31 downto 0); 64 | signal trexo,sinex: std_logic; 65 | 66 | begin 67 | 68 | U_mt1: mt2 port map (clk=>clk, 69 | rst=>rst, 70 | freeze=>fre, 71 | running=>trexo, 72 | frozen=>sinex, 73 | tixaios1=>arithmos1, 74 | tixaios2=>arithmos2, 75 | tixaios3=>arithmos3, 76 | tixaios4=>arithmos4 77 | ); 78 | 79 | U_bm1: BoxMuller port map (clk=>clk, 80 | rst=>trexo, 81 | wen=>sinex, 82 | eisodos1=>arithmos1, 83 | eisodos2=>arithmos2, 84 | eksodos=>deigma1 85 | ); 86 | 87 | U_bm2: BoxMuller port map (clk=>clk, 88 | rst=>trexo, 89 | wen=>sinex, 90 | eisodos1=>arithmos3, 91 | eisodos2=>arithmos4, 92 | eksodos=>deigma2 93 | ); 94 | 95 | -- U_rg1: myreg generic map (n=>40) port map ( clk => clk, 96 | -- rst=>rst, 97 | -- wen=>sinex, 98 | -- eisod=> deigma1, 99 | -- deigma=>deigma 100 | -- ); 101 | 102 | -- U_df1: mydff2 port map (clk=>clk, 103 | -- rst=>rst, 104 | -- wen=>sinex, 105 | -- eisod=>trexo, 106 | -- deigma=>ready 107 | -- ); 108 | ready<=trexo; 109 | 110 | end struct; 111 | -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_32bits/mybpsk.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use ieee.std_logic_signed.all; 4 | use ieee.numeric_std.all; 5 | 6 | 7 | entity mybpsk is 8 | port( simeio : in std_logic; 9 | symbol : out signed (79 downto 0) 10 | ); 11 | end entity; 12 | 13 | 14 | architecture struct of mybpsk is 15 | 16 | constant ena : signed (79 downto 0):= "00000000000000010000000000000000000000000000000000000000000000000000000000000000"; 17 | constant plinena : signed (79 downto 0):= "11111111111111110000000000000000000000000000000000000000000000000000000000000000"; 18 | begin 19 | 20 | symbol<=plinena when simeio='0' else ena; 21 | 22 | end struct; 23 | -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_32bits/mycount.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use ieee.std_logic_signed.all; 4 | use ieee.numeric_std.all; 5 | 6 | entity mycount is 7 | generic(n: integer:=40); 8 | port( clk : in std_logic; 9 | rst : in std_logic; 10 | en : in std_logic; 11 | cnt : out std_logic_vector (n-1 downto 0) 12 | ); 13 | end mycount; 14 | 15 | architecture struct of mycount is 16 | 17 | signal count : std_logic_vector (n-1 downto 0); 18 | 19 | begin 20 | 21 | pr1:process (clk) 22 | begin 23 | if clk='1' and clk'event then 24 | if rst='0' then 25 | count <=(others => '0'); 26 | elsif en='1' then 27 | count <= count+1; 28 | end if; 29 | end if; 30 | end process; 31 | 32 | cnt<=count; 33 | 34 | end struct; 35 | -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_32bits/mycount2.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use ieee.std_logic_signed.all; 4 | use ieee.numeric_std.all; 5 | 6 | entity mycount2 is 7 | generic(n: integer:=40); 8 | port( clk : in std_logic; 9 | rst : in std_logic; 10 | en : in std_logic; 11 | cnt : out std_logic_vector (n-1 downto 0) 12 | ); 13 | end mycount2; 14 | 15 | architecture struct of mycount2 is 16 | 17 | signal count : std_logic_vector (n-1 downto 0); 18 | 19 | begin 20 | 21 | pr1:process (clk) 22 | begin 23 | if clk='1' and clk'event then 24 | if rst='0' then 25 | count <="000000000000000000000000000000000001";--(others => '0'); 26 | elsif en='1' then 27 | count <= count+1; 28 | end if; 29 | end if; 30 | end process; 31 | 32 | cnt<=count; 33 | 34 | end struct; 35 | -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_32bits/mydff.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use ieee.std_logic_signed.all; 4 | use ieee.numeric_std.all; 5 | 6 | 7 | entity mydff is 8 | port( clk : in std_logic; 9 | rst : in std_logic; 10 | eisod : in std_logic; 11 | deigma : out std_logic 12 | ); 13 | end entity; 14 | 15 | 16 | architecture struct of mydff is 17 | 18 | 19 | begin 20 | 21 | pr1:process (clk) 22 | begin 23 | if clk='1' and clk'event then 24 | if rst='0' then 25 | deigma <='0'; 26 | else 27 | deigma <= eisod; 28 | end if; 29 | end if; 30 | end process; 31 | 32 | 33 | 34 | end struct; 35 | -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_32bits/mydff2.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use ieee.std_logic_signed.all; 4 | use ieee.numeric_std.all; 5 | 6 | 7 | entity mydff2 is 8 | port( clk : in std_logic; 9 | rst : in std_logic; 10 | wen : in std_logic; 11 | eisod : in std_logic; 12 | deigma : out std_logic 13 | ); 14 | end entity; 15 | 16 | 17 | architecture struct of mydff2 is 18 | 19 | 20 | begin 21 | 22 | pr1:process (clk) 23 | begin 24 | if clk='1' and clk'event then 25 | if rst='0' then 26 | deigma <='0'; 27 | elsif (wen='1') then 28 | deigma <= eisod; 29 | end if; 30 | end if; 31 | end process; 32 | 33 | 34 | 35 | end struct; 36 | -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_32bits/myfsm.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use ieee.std_logic_signed.all; 4 | use ieee.numeric_std.all; 5 | 6 | 7 | entity myfsm is 8 | port ( clk : in std_logic; 9 | rst : in std_logic; 10 | freezing : in std_logic; 11 | running : out std_logic; 12 | conti : out std_logic; 13 | address : out signed (9 downto 0) 14 | ); 15 | end entity; 16 | 17 | architecture struct of myfsm is 18 | 19 | type state_type is (r0,t0,t1); 20 | signal state: state_type; 21 | signal addr : signed (9 downto 0); 22 | -- signal var1 : std_logic; 23 | 24 | begin 25 | 26 | pr1:process(clk) 27 | begin 28 | if clk'event and clk='1' then 29 | if rst='0' then 30 | state<=r0; 31 | addr<="0000000000"; 32 | else 33 | case state is 34 | when r0=> 35 | if (addr="1001101100" and freezing='0') then 36 | state<=t0; 37 | addr<="0000000000"; 38 | elsif (addr="1001101100" and freezing='1') then 39 | state<=t1; 40 | addr<="0000000000"; 41 | else 42 | state<=r0; 43 | addr<=addr+4; 44 | end if; 45 | when t0=> 46 | if (freezing='1') then 47 | state<=t1; 48 | if (addr="1001101100") then 49 | addr<="0000000000"; 50 | else 51 | addr<=addr+4; 52 | end if; 53 | else 54 | if (addr="1001101100") then 55 | addr<="0000000000"; 56 | else 57 | addr<=addr+4; 58 | end if; 59 | state<=t0; 60 | end if; 61 | when t1 => 62 | if (freezing='0') then 63 | state<=t0; 64 | else 65 | state<=t1; 66 | end if; 67 | when others=> 68 | state<=r0; 69 | addr<="0000000000"; 70 | end case; 71 | end if; 72 | end if; 73 | end process; 74 | 75 | pr2:process(state) 76 | begin 77 | case state is 78 | when r0=> running<='0'; 79 | conti<='1'; 80 | when t0=> running<='1'; 81 | conti<='1'; 82 | when t1=> running<='1'; 83 | conti<='0'; 84 | when others=> running<='0'; 85 | conti<='0'; 86 | end case; 87 | end process; 88 | 89 | -- running<=var1; 90 | address<=addr; 91 | 92 | end struct; 93 | -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_32bits/mylfsr2.vhd: -------------------------------------------------------------------------------- 1 | ------------------------------------------------------------- 2 | -- This file is generated through a matalab script. For -- 3 | -- any problems please contact to paraskeu@ceid.upatras.gr -- 4 | -- with subject: lfsr2 script. Thank you! -- 5 | ------------------------------------------------------------- 6 | 7 | library ieee; 8 | use ieee.std_logic_1164.all; 9 | 10 | entity mylfsr2 is 11 | port ( starting: in std_logic_vector (7 downto 0); 12 | lfsr2_out: out std_logic_vector(7 downto 0); 13 | clk: in std_logic; 14 | rst: in std_logic; 15 | en: in std_logic); 16 | end mylfsr2; 17 | 18 | architecture struct of mylfsr2 is 19 | 20 | signal count: std_logic_vector (7 downto 0); 21 | 22 | begin 23 | 24 | pr1:process(clk) 25 | begin 26 | if (clk'event and clk='1')then 27 | if (rst='0') then 28 | count<=starting; 29 | elsif (en='1') then 30 | count(0)<=count(7); 31 | count(1)<=count(0); 32 | count(2)<=count(7) xor count(1); 33 | count(3)<=count(7) xor count(2); 34 | count(4)<=count(7) xor count(3); 35 | count(5)<=count(4); 36 | count(6)<=count(5); 37 | count(7)<=count(6); 38 | end if; 39 | end if; 40 | end process; 41 | 42 | lfsr2_out<=count; 43 | 44 | end struct; 45 | -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_32bits/myllr.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use ieee.std_logic_signed.all; 4 | use ieee.numeric_std.all; 5 | 6 | entity myllr is 7 | port ( simeio : in signed (39 downto 0); 8 | llr : out signed (5 downto 0) 9 | ); 10 | end entity; 11 | 12 | architecture struct of myllr is 13 | 14 | constant ena : signed (39 downto 0):= "0000000100000000000000000000000000000000"; 15 | constant plinena : signed (39 downto 0):= "1111111100000000000000000000000000000000"; 16 | constant ena2 : signed (44 downto 0):="000000000000010000000000000000000000000000000"; 17 | constant miden : signed (39 downto 0):="0000000000000000000000000000000000000000"; 18 | constant enaround : signed (39 downto 0):= "0000000100000000000000000000000000000000"; 19 | constant plinenaround : signed (39 downto 0):= "1111111100000000000000000000000000000000"; 20 | constant trianta1 : signed (5 downto 0):="011111"; 21 | constant pltrianta1 : signed (5 downto 0):="100001"; 22 | 23 | signal simeio1,simeio2,sfalma1,sfalma2,sfalma: signed (39 downto 0); 24 | signal temp1,temp2,temp3,temp4,temp5,temp6 : signed (44 downto 0); 25 | 26 | begin 27 | 28 | simeio1<=simeio + ena; 29 | simeio2<=simeio - ena; 30 | sfalma<= simeio2 when simeio(39)='0' else simeio1; 31 | sfalma1<= sfalma + enaround; 32 | sfalma2<= sfalma - enaround; 33 | temp1<=sfalma1(39)&sfalma1(39)&sfalma1(39)&sfalma1(39)&sfalma1(39)&sfalma1; 34 | temp2<=sfalma2(39)&sfalma2(39)&sfalma2(39)&sfalma2(39)&sfalma2(39)&sfalma2; 35 | temp3<=sfalma1&"00000"; 36 | temp4<=sfalma2&"00000"; 37 | temp5<=temp3-temp1+ena2; 38 | temp6<=temp4-temp2+ena2; 39 | llr <= trianta1 when (simeio(39)='0' and sfalma(39)='0') else temp5(37 downto 32) when(simeio(39)='0' and sfalma(39)='1') else temp6(37 downto 32) when (simeio(39)='1' and sfalma(39)='0' and sfalma/=miden) else pltrianta1; 40 | 41 | end struct; 42 | -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_32bits/myram.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use ieee.std_logic_signed.all; 4 | use ieee.numeric_std.all; 5 | 6 | entity myram is 7 | generic( width : natural := 32; 8 | adr_length : natural := 8 9 | ); 10 | port( clk : in std_logic; 11 | wen : in std_logic; 12 | neostoix : in signed (width-1 downto 0); 13 | address1 : in signed (adr_length-1 downto 0); 14 | address2 : in signed (adr_length-1 downto 0); 15 | stoixeio1 : out signed (width-1 downto 0); 16 | stoixeio2 : out signed (width-1 downto 0) 17 | ); 18 | end myram; 19 | 20 | 21 | architecture struct of myram is 22 | 23 | type mem_type is array ((2**adr_length-1) downto 0) of signed (width-1 downto 0); 24 | signal stoixeia: mem_type; 25 | 26 | begin 27 | 28 | pr1:process (clk) 29 | begin 30 | if (clk'event and clk = '1') then 31 | if (wen = '1') then 32 | stoixeia(to_integer(unsigned(address1))) <= neostoix; 33 | end if; 34 | end if; 35 | end process; 36 | 37 | stoixeio1 <= stoixeia(to_integer(unsigned(address1))); 38 | stoixeio2 <= stoixeia(to_integer(unsigned(address2))); 39 | 40 | end struct; 41 | -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_32bits/myram2.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use ieee.std_logic_signed.all; 4 | use ieee.numeric_std.all; 5 | 6 | entity myram2 is 7 | generic( width : natural := 32; 8 | adr_length : natural := 8 9 | ); 10 | port( clk : in std_logic; 11 | wen : in std_logic; 12 | neostoix : in signed (width-1 downto 0); 13 | address1 : in signed (adr_length-1 downto 0); 14 | stoixeio1 : out signed (width-1 downto 0) 15 | ); 16 | end myram2; 17 | 18 | 19 | architecture struct of myram2 is 20 | 21 | type mem_type is array ((2**adr_length-1) downto 0) of signed (width-1 downto 0); 22 | signal stoixeia: mem_type; 23 | 24 | begin 25 | 26 | pr1:process (clk) 27 | begin 28 | if (clk'event and clk = '1') then 29 | if (wen = '1') then 30 | stoixeia(to_integer(unsigned(address1))) <= neostoix; 31 | end if; 32 | end if; 33 | end process; 34 | 35 | stoixeio1 <= stoixeia(to_integer(unsigned(address1))); 36 | 37 | end struct; 38 | -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_32bits/myreg.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use ieee.std_logic_signed.all; 4 | use ieee.numeric_std.all; 5 | 6 | 7 | entity myreg is 8 | generic(n: integer:=40); 9 | port( clk : in std_logic; 10 | rst : in std_logic; 11 | wen : in std_logic; 12 | eisod : in signed (n-1 downto 0); 13 | deigma : out signed (n-1 downto 0) 14 | ); 15 | end entity; 16 | 17 | 18 | architecture struct of myreg is 19 | 20 | 21 | begin 22 | 23 | pr1:process (clk) 24 | begin 25 | if clk='1' and clk'event then 26 | if rst='0' then 27 | deigma <=(others => '0'); 28 | elsif (wen='1') then 29 | deigma <= eisod; 30 | end if; 31 | end if; 32 | end process; 33 | 34 | 35 | 36 | end struct; 37 | -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_32bits/myreg2.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use ieee.std_logic_signed.all; 4 | use ieee.numeric_std.all; 5 | 6 | 7 | entity myreg2 is 8 | generic(n: integer:=40); 9 | port( clk : in std_logic; 10 | rst : in std_logic; 11 | eisod : in signed (n-1 downto 0); 12 | deigma : out signed (n-1 downto 0) 13 | ); 14 | end entity; 15 | 16 | 17 | architecture struct of myreg2 is 18 | 19 | 20 | begin 21 | 22 | pr1:process (clk) 23 | begin 24 | if clk='1' and clk'event then 25 | if rst='0' then 26 | deigma <=(others => '0'); 27 | else 28 | deigma <= eisod; 29 | end if; 30 | end if; 31 | end process; 32 | 33 | 34 | 35 | end struct; 36 | -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_32bits/paragogi.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use ieee.std_logic_signed.all; 4 | use ieee.numeric_std.all; 5 | 6 | entity paragogi is 7 | port( eisodos : in signed (31 downto 0); 8 | eksodos : out signed (31 downto 0) 9 | ); 10 | end entity; 11 | 12 | architecture struct of paragogi is 13 | 14 | signal y,y1,y2,y3,y4,y5,y6,y7,y8,y9 : signed (31 downto 0); 15 | constant c1 : signed (31 downto 0):= "10011101001011000101011010000000"; 16 | constant c2 : signed (31 downto 0):= "11101111110001100000000000000000"; 17 | 18 | begin 19 | 20 | y <= eisodos; 21 | y1<=y srl 11; 22 | y2 <= y xor y1; 23 | y3<=y2 sll 7; 24 | y4<=y3 and c1; 25 | y5 <= y2 xor y4; 26 | y6<=y5 sll 15; 27 | y7<=y6 and c2; 28 | y8 <= y5 xor y7; 29 | y9<=y8 srl 18; 30 | eksodos <= y8 xor y9; 31 | 32 | end struct; 33 | -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_32bits/pepExtractor.prj: -------------------------------------------------------------------------------- 1 | work "Encoder.vhd" 2 | work "MyPackage.vhd" 3 | -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_32bits/sat.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use ieee.std_logic_signed.all; 4 | use ieee.numeric_std.all; 5 | 6 | entity sat is 7 | port( eisodos : in signed (79 downto 0); 8 | eksodos : out signed (39 downto 0) 9 | ); 10 | end entity; 11 | 12 | architecture struct of sat is 13 | 14 | signal endiameso: signed (39 downto 0); 15 | signal a,b1,b: signed (7 downto 0); 16 | signal c,c1: signed (31 downto 0); 17 | constant miden : signed ( 7 downto 0):="00000000"; 18 | constant assoi : signed (7 downto 0) :="11111111"; 19 | 20 | 21 | begin 22 | a<=eisodos(79 downto 72); 23 | b1<=eisodos(71 downto 64); 24 | c1<=eisodos(63 downto 32); 25 | endiameso<=b&c; 26 | eksodos<=endiameso; 27 | 28 | 29 | 30 | pr1:process(a,b1,c1) 31 | begin 32 | if ((a=miden and b1(7)='0') or (a=assoi and b1(7)='1')) then 33 | b<=b1; 34 | c<=c1; 35 | elsif (a(7)='0') then 36 | b<="01111111"; 37 | c<=(others=>'1'); 38 | else 39 | b<="10000000"; 40 | c<=(others=>'0'); 41 | end if; 42 | end process; 43 | 44 | 45 | 46 | end struct; 47 | -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_32bits/sat51.vhd: -------------------------------------------------------------------------------- 1 | -------------- 2 | -- LLRs=5.1 -- 3 | -------------- 4 | 5 | library ieee; 6 | use ieee.std_logic_1164.all; 7 | use ieee.std_logic_signed.all; 8 | use ieee.numeric_std.all; 9 | 10 | entity sat51 is 11 | port( eisodos : in signed (79 downto 0); 12 | eksodos : out signed (5 downto 0) 13 | ); 14 | end entity; 15 | 16 | architecture struct of sat51 is 17 | 18 | signal endiameso: signed (5 downto 0); 19 | signal a: signed (10 downto 0); 20 | signal b1,b: signed (4 downto 0); 21 | signal c,c1: signed (0 downto 0); 22 | constant miden : signed ( 10 downto 0):="00000000000"; 23 | constant assoi : signed (10 downto 0) :="11111111111"; 24 | 25 | 26 | begin 27 | a<=eisodos(79 downto 69); 28 | b1<=eisodos(68 downto 64); 29 | c1<=eisodos(63 downto 63); 30 | endiameso<=b&c; 31 | eksodos<=endiameso; 32 | 33 | 34 | 35 | pr1:process(a,b1,c1) 36 | begin 37 | if ((a=miden and b1(4)='0') or (a=assoi and b1(4)='1')) then 38 | b<=b1; 39 | c<=c1; 40 | elsif (a(10)='0') then 41 | b<="01111"; 42 | c<=(others=>'1'); 43 | else 44 | b<="10000"; 45 | c<=(others=>'0'); 46 | end if; 47 | end process; 48 | 49 | 50 | 51 | end struct; 52 | -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_32bits/sel.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use ieee.std_logic_signed.all; 4 | use ieee.numeric_std.all; 5 | 6 | entity sel is 7 | port( eisodos1 : in signed (39 downto 0); 8 | eksodos1 : out signed (39 downto 0) 9 | ); 10 | end entity; 11 | 12 | architecture struct of sel is 13 | 14 | constant pi: signed(39 downto 0):="0000001100100100001111110110101010001000"; 15 | constant pi2: signed(39 downto 0):="0000011001001000011111101101010100010000"; 16 | constant pimiso: signed(39 downto 0):="0000000110010010000111111011010101000100"; 17 | constant pi32: signed (39 downto 0):= "0000010010110110010111110001111111001100"; 18 | constant miden: signed (39 downto 0):=(others=>'0'); 19 | signal eks1 : signed (39 downto 0); 20 | signal eks2 : signed (39 downto 0); 21 | signal eks3 : signed (39 downto 0); 22 | signal eks4 : signed (39 downto 0); 23 | 24 | begin 25 | 26 | pr1:process(eisodos1) 27 | begin 28 | if (miden<=eisodos1 and eisodos1'0'); 20 | 21 | begin 22 | 23 | 24 | pr1:process(eisodos1,eisodos2) 25 | begin 26 | if (miden<=eisodos1 and eisodos1'1', others=>'0'); 41 | begin 42 | process (clk) 43 | begin 44 | if rising_edge(clk) then 45 | if(rst = '1') then 46 | tmp <= (0 => '1', others => '0'); 47 | else 48 | tmp <= tmp(width-2 downto 0)& tmp(width-1); 49 | end if; 50 | end if; 51 | end process; 52 | outputs <= tmp; 53 | end Behavioral; 54 | 55 | -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_32bits/shifting.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use ieee.std_logic_signed.all; 4 | use ieee.numeric_std.all; 5 | 6 | 7 | 8 | entity shifting is 9 | generic (n: integer:=8); 10 | port ( arithmos: in signed (N-1 downto 0); 11 | theseis:in signed (N-2 downto 0); 12 | eksodos: out signed (N-1 downto 0) ); 13 | end shifting; 14 | 15 | architecture Behavioral of shifting is 16 | 17 | signal num1,num2: unsigned (N-1 downto 0); 18 | signal num3: integer; 19 | 20 | begin 21 | 22 | num1<=unsigned(arithmos); 23 | num3<=to_integer(theseis); 24 | num2<=num1 sll num3; 25 | eksodos<=signed(num2); 26 | 27 | end Behavioral; 28 | 29 | -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_32bits/synt5.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use ieee.std_logic_signed.all; 4 | use ieee.numeric_std.all; 5 | 6 | entity synt5 is 7 | port( 8 | address1 : in signed (5 downto 0); 9 | stoixeio1 : out signed (40-1 downto 0) 10 | ); 11 | end synt5; 12 | 13 | 14 | architecture struct of synt5 is 15 | 16 | type rom_type is array (35 downto 0) of signed (39 downto 0); 17 | constant stoixeia : rom_type :=("0000000000000001011111001010011101110000", 18 | "0000000000000001100000100101010001011001", 19 | "0000000000000001100010000100010000000111", 20 | "0000000000000001100011100111101111011001", 21 | "0000000000000001100101010000000101011001", 22 | "0000000000000001100110111101101101101000", 23 | "0000000000000001101000110001000100111101", 24 | "0000000000000001101010101010101100001111", 25 | "0000000000000001101100101011001000011001", 26 | "0000000000000001101110110011000100011001", 27 | "0000000000000001110001000011001111110111", 28 | "0000000000000001110011011100100001110101", 29 | "0000000000000001110101111111111010101111", 30 | "0000000000000001111000101110100011000011", 31 | "0000000000000001111011101001110001010101", 32 | "0000000000000001111110110011001010010001", 33 | "0000000000000010000010001100100011010001", 34 | "0000000000000010000101111000001011010100", 35 | "0000000000000010001001111000101010110011", 36 | "0000000000000010001110010001001111001000", 37 | "0000000000000010010011000101110011111011", 38 | "0000000000000010011000011011001110100100", 39 | "0000000000000010011110010111100010010010", 40 | "0000000000000010100101000010011010010011", 41 | "0000000000000010101100100101100110000100", 42 | "0000000000000010110101001101100100001011", 43 | "0000000000000010111111001010111000111100", 44 | "0000000000000011001010110010100010100011", 45 | "0000000000000011011000011111010110111110", 46 | "0000000000000011101000100010010101011001", 47 | "0000000000000011101111110111010111001100", 48 | "1111111111110000011111111100010010111011", 49 | "1111111111111111101000111110101000101101", 50 | "1111010101100000000000000000000000000000", 51 | "0000000000000000000000000000000000000000", 52 | "0000000000000000000000000000000000000000"); 53 | 54 | begin 55 | 56 | stoixeio1<=stoixeia(to_integer((unsigned(address1)))); 57 | end struct; 58 | -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_32bits/system.bld: -------------------------------------------------------------------------------- 1 | Release 14.2 ngdbuild P.28xd (nt64) 2 | Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. 3 | 4 | Command Line: C:\Xilinx\14.2\ISE_DS\ISE\bin\nt64\unwrapped\ngdbuild.exe 5 | -intstyle ise -dd _ngo -nt timestamp -i -p xc3s700a-fg484-4 system.ngc 6 | system.ngd 7 | 8 | Reading NGO file "D:/Dropbox/Thesis Project/Hardware/v1.0 Encode-Decode no 9 | Fsm/Polar_32bits/system.ngc" ... 10 | Gathering constraint information from source properties... 11 | Done. 12 | 13 | Resolving constraint associations... 14 | Checking Constraint Associations... 15 | Done... 16 | 17 | Checking expanded design ... 18 | 19 | Partition Implementation Status 20 | ------------------------------- 21 | 22 | No Partitions were found in this design. 23 | 24 | ------------------------------- 25 | 26 | NGDBUILD Design Results Summary: 27 | Number of errors: 0 28 | Number of warnings: 0 29 | 30 | Total memory usage is 163532 kilobytes 31 | 32 | Writing NGD file "system.ngd" ... 33 | Total REAL time to NGDBUILD completion: 6 sec 34 | Total CPU time to NGDBUILD completion: 6 sec 35 | 36 | Writing NGDBUILD log file "system.bld"... 37 | -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_32bits/system.cmd_log: -------------------------------------------------------------------------------- 1 | xst -intstyle ise -ifn "D:/Dropbox/Thesis Project/Hardware/v1.0 Encode-Decode no Fsm/Polar_32bits/system.xst" -ofn "D:/Dropbox/Thesis Project/Hardware/v1.0 Encode-Decode no Fsm/Polar_32bits/system.syr" 2 | ngdbuild -intstyle ise -dd _ngo -nt timestamp -i -p xc3s700a-fg484-4 "system.ngc" system.ngd 3 | map -intstyle ise -p xc3s700a-fg484-4 -cm area -ir off -pr off -c 100 -o system_map.ncd system.ngd system.pcf 4 | par -w -intstyle ise -ol high -t 1 system_map.ncd system.ncd system.pcf 5 | trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml system.twx system.ncd -o system.twr system.pcf 6 | -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_32bits/system.lso: -------------------------------------------------------------------------------- 1 | work 2 | -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_32bits/system.pcf: -------------------------------------------------------------------------------- 1 | //! ************************************************************************** 2 | // Written by: Map P.28xd on Sun May 15 16:51:47 2016 3 | //! ************************************************************************** 4 | 5 | -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_32bits/system.prj: -------------------------------------------------------------------------------- 1 | vhdl work "MyPackage.vhd" 2 | vhdl work "PartialSumGenerator.vhd" 3 | vhdl work "G.vhd" 4 | vhdl work "F.vhd" 5 | vhdl work "D_FF_1bit.vhd" 6 | vhdl work "D_FF.vhd" 7 | vhdl work "llr_test.vhd" 8 | vhdl work "Encoder.vhd" 9 | vhdl work "Decoder.vhd" 10 | vhdl work "counter.vhd" 11 | vhdl work "system.vhd" 12 | -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_32bits/system.stx: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Spartak0s/Polar-Codes-Hardware-VHDL/41139d92e8d3e5550fba42f7f550bb1c36afce17/v1.0 Encode-Decoder no Fsm/Polar_32bits/system.stx -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_32bits/system.unroutes: -------------------------------------------------------------------------------- 1 | Release 14.2 - par P.28xd (nt64) 2 | Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. 3 | 4 | Sun May 15 16:52:37 2016 5 | 6 | All signals are completely routed. 7 | 8 | 9 | 10 | -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_32bits/system.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Company: 3 | -- Engineer: 4 | -- 5 | -- Create Date: 13:44:39 05/15/2016 6 | -- Design Name: 7 | -- Module Name: system - Behavioral 8 | -- Project Name: 9 | -- Target Devices: 10 | -- Tool versions: 11 | -- Description: 12 | -- 13 | -- Dependencies: 14 | -- 15 | -- Revision: 16 | -- Revision 0.01 - File Created 17 | -- Additional Comments: 18 | -- 19 | ---------------------------------------------------------------------------------- 20 | library IEEE; 21 | use IEEE.STD_LOGIC_1164.ALL; 22 | use work.all; 23 | use work.MyPackage.all; 24 | 25 | -- Uncomment the following library declaration if using 26 | -- arithmetic functions with Signed or Unsigned values 27 | --use IEEE.NUMERIC_STD.ALL; 28 | 29 | -- Uncomment the following library declaration if instantiating 30 | -- any Xilinx primitives in this code. 31 | --library UNISIM; 32 | --use UNISIM.VComponents.all; 33 | 34 | entity system is 35 | Port ( clk : in STD_LOGIC; 36 | boot : in STD_LOGIC; 37 | correct : out STD_LOGIC); 38 | end system; 39 | 40 | architecture Behavioral of system is 41 | constant correct_check: std_logic_vector(N/2-1 downto 0) := (others =>'0'); 42 | signal ce_decoder,ce_delay,input_enable: std_logic; 43 | signal in_generator,delay1,delay2,dec_out,check: std_logic_vector(N/2-1 downto 0); 44 | signal encoder_out: std_logic_vector(N-1 downto 0); 45 | signal llr_out: data; 46 | begin 47 | --FSM 48 | input_enable <= '1'; 49 | ce_decoder <= '1'; 50 | ce_delay <= '1'; 51 | check <= (delay2 xor dec_out); 52 | correct <= '1' when (check = correct_check) 53 | else '0'; 54 | --Generate Input 55 | U_Input_Generator: entity counter generic map(width => N/2) 56 | port map(clk => clk, 57 | rst => boot, 58 | count => input_enable, 59 | q => in_generator); 60 | --Delay Input 61 | U_Delay1: entity D_FF_gen generic map(width => N/2) port map(clk =>clk,rst =>boot,ce =>ce_delay,d => in_generator,q =>delay1); 62 | U_Delay2: entity D_FF_gen generic map(width => N/2) port map(clk =>clk,rst =>boot,ce =>ce_delay,d => delay1,q =>delay2); 63 | 64 | --Encoder 65 | U_Encoder: entity Encoder port map(inputs =>in_generator, 66 | outputs =>encoder_out); 67 | --llr transform 68 | U_Channel: entity llr_test port map(inputs => encoder_out, 69 | outputs => llr_out); 70 | --Decoder 71 | U_Decoder: entity Decoder port map(clk => clk, 72 | rst => boot, 73 | ce_inputs => ce_decoder, 74 | inputs => llr_out, 75 | outputs => dec_out); 76 | end Behavioral; 77 | 78 | -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_32bits/system.xpi: -------------------------------------------------------------------------------- 1 | PROGRAM=PAR 2 | STATE=ROUTED 3 | TIMESPECS_MET=OFF 4 | -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_32bits/system.xst: -------------------------------------------------------------------------------- 1 | set -tmpdir "xst/projnav.tmp" 2 | set -xsthdpdir "xst" 3 | run 4 | -ifn system.prj 5 | -ifmt mixed 6 | -ofn system 7 | -ofmt NGC 8 | -p xc3s700a-4-fg484 9 | -top system 10 | -opt_mode Speed 11 | -opt_level 1 12 | -iuc NO 13 | -keep_hierarchy No 14 | -netlist_hierarchy As_Optimized 15 | -rtlview Yes 16 | -glob_opt AllClockNets 17 | -read_cores YES 18 | -write_timing_constraints NO 19 | -cross_clock_analysis NO 20 | -hierarchy_separator / 21 | -bus_delimiter <> 22 | -case Maintain 23 | -slice_utilization_ratio 100 24 | -bram_utilization_ratio 100 25 | -verilog2001 YES 26 | -fsm_extract YES -fsm_encoding Auto 27 | -safe_implementation No 28 | -fsm_style LUT 29 | -ram_extract Yes 30 | -ram_style Auto 31 | -rom_extract Yes 32 | -mux_style Auto 33 | -decoder_extract YES 34 | -priority_extract Yes 35 | -shreg_extract YES 36 | -shift_extract YES 37 | -xor_collapse YES 38 | -rom_style Auto 39 | -auto_bram_packing NO 40 | -mux_extract Yes 41 | -resource_sharing YES 42 | -async_to_sync NO 43 | -mult_style Auto 44 | -iobuf YES 45 | -max_fanout 100000 46 | -bufg 24 47 | -register_duplication YES 48 | -register_balancing No 49 | -slice_packing YES 50 | -optimize_primitives NO 51 | -use_clock_enable Yes 52 | -use_sync_set Yes 53 | -use_sync_reset Yes 54 | -iob Auto 55 | -equivalent_register_removal YES 56 | -slice_utilization_ratio_maxmargin 5 57 | -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_32bits/system_beh.prj: -------------------------------------------------------------------------------- 1 | vhdl work "MyPackage.vhd" 2 | vhdl work "PartialSumGenerator.vhd" 3 | vhdl work "G.vhd" 4 | vhdl work "F.vhd" 5 | vhdl work "D_FF_1bit.vhd" 6 | vhdl work "D_FF.vhd" 7 | vhdl work "llr_test.vhd" 8 | vhdl work "Encoder.vhd" 9 | vhdl work "Decoder.vhd" 10 | vhdl work "counter.vhd" 11 | vhdl work "system.vhd" 12 | -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_32bits/system_isim_beh.exe: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Spartak0s/Polar-Codes-Hardware-VHDL/41139d92e8d3e5550fba42f7f550bb1c36afce17/v1.0 Encode-Decoder no Fsm/Polar_32bits/system_isim_beh.exe -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_32bits/system_isim_beh.wdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Spartak0s/Polar-Codes-Hardware-VHDL/41139d92e8d3e5550fba42f7f550bb1c36afce17/v1.0 Encode-Decoder no Fsm/Polar_32bits/system_isim_beh.wdb -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_32bits/system_isim_beh1.wdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Spartak0s/Polar-Codes-Hardware-VHDL/41139d92e8d3e5550fba42f7f550bb1c36afce17/v1.0 Encode-Decoder no Fsm/Polar_32bits/system_isim_beh1.wdb -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_32bits/system_map.map: -------------------------------------------------------------------------------- 1 | Release 14.2 Map P.28xd (nt64) 2 | Xilinx Map Application Log File for Design 'system' 3 | 4 | Design Information 5 | ------------------ 6 | Command Line : map -intstyle ise -p xc3s700a-fg484-4 -cm area -ir off -pr off 7 | -c 100 -o system_map.ncd system.ngd system.pcf 8 | Target Device : xc3s700a 9 | Target Package : fg484 10 | Target Speed : -4 11 | Mapper Version : spartan3a -- $Revision: 1.55 $ 12 | Mapped Date : Sun May 15 16:51:43 2016 13 | 14 | Mapping design into LUTs... 15 | Running directed packing... 16 | Running delay-based LUT packing... 17 | Running related packing... 18 | Updating timing models... 19 | 20 | Design Summary 21 | -------------- 22 | 23 | Design Summary: 24 | Number of errors: 0 25 | Number of warnings: 0 26 | Logic Utilization: 27 | Number of Slice Flip Flops: 103 out of 11,776 1% 28 | Number of 4 input LUTs: 2,525 out of 11,776 21% 29 | Logic Distribution: 30 | Number of occupied Slices: 1,353 out of 5,888 22% 31 | Number of Slices containing only related logic: 1,353 out of 1,353 100% 32 | Number of Slices containing unrelated logic: 0 out of 1,353 0% 33 | *See NOTES below for an explanation of the effects of unrelated logic. 34 | Total Number of 4 input LUTs: 2,553 out of 11,776 21% 35 | Number used as logic: 2,525 36 | Number used as a route-thru: 28 37 | 38 | The Slice Logic Distribution report is not meaningful if the design is 39 | over-mapped for a non-slice resource or if Placement fails. 40 | 41 | Number of bonded IOBs: 3 out of 372 1% 42 | Number of BUFGMUXs: 1 out of 24 4% 43 | 44 | Average Fanout of Non-Clock Nets: 3.68 45 | 46 | Peak Memory Usage: 292 MB 47 | Total REAL time to MAP completion: 5 secs 48 | Total CPU time to MAP completion: 4 secs 49 | 50 | NOTES: 51 | 52 | Related logic is defined as being logic that shares connectivity - e.g. two 53 | LUTs are "related" if they share common inputs. When assembling slices, 54 | Map gives priority to combine logic that is related. Doing so results in 55 | the best timing performance. 56 | 57 | Unrelated logic shares no connectivity. Map will only begin packing 58 | unrelated logic into a slice once 99% of the slices are occupied through 59 | related logic packing. 60 | 61 | Note that once logic distribution reaches the 99% level through related 62 | logic packing, this does not mean the device is completely utilized. 63 | Unrelated logic packing will then begin, continuing until all usable LUTs 64 | and FFs are occupied. Depending on your timing budget, increased levels of 65 | unrelated logic packing may adversely affect the overall timing performance 66 | of your design. 67 | 68 | Mapping completed. 69 | See MAP report file "system_map.mrp" for details. 70 | -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_32bits/system_summary.xml: -------------------------------------------------------------------------------- 1 | 2 | 7 | 8 | 9 | 10 | 11 | -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_32bits/system_usage.xml: -------------------------------------------------------------------------------- 1 | 2 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_32bits/system_vhdl.prj: -------------------------------------------------------------------------------- 1 | vhdl work "D:\Dropbox\Thesis Project\Hardware\v1.0 Encode-Decode no Fsm\Polar_32bits\MyPackage.vhd" 2 | vhdl work "D:\Dropbox\Thesis Project\Hardware\v1.0 Encode-Decode no Fsm\Polar_32bits\PartialSumGenerator.vhd" 3 | vhdl work "D:\Dropbox\Thesis Project\Hardware\v1.0 Encode-Decode no Fsm\Polar_32bits\G.vhd" 4 | vhdl work "D:\Dropbox\Thesis Project\Hardware\v1.0 Encode-Decode no Fsm\Polar_32bits\F.vhd" 5 | vhdl work "D:\Dropbox\Thesis Project\Hardware\v1.0 Encode-Decode no Fsm\Polar_32bits\D_FF_1bit.vhd" 6 | vhdl work "D:\Dropbox\Thesis Project\Hardware\v1.0 Encode-Decode no Fsm\Polar_32bits\D_FF.vhd" 7 | vhdl work "D:\Dropbox\Thesis Project\Hardware\v1.0 Encode-Decode no Fsm\Polar_32bits\llr_test.vhd" 8 | vhdl work "D:\Dropbox\Thesis Project\Hardware\v1.0 Encode-Decode no Fsm\Polar_32bits\Encoder.vhd" 9 | vhdl work "D:\Dropbox\Thesis Project\Hardware\v1.0 Encode-Decode no Fsm\Polar_32bits\Decoder.vhd" 10 | vhdl work "D:\Dropbox\Thesis Project\Hardware\v1.0 Encode-Decode no Fsm\Polar_32bits\counter.vhd" 11 | vhdl work "D:\Dropbox\Thesis Project\Hardware\v1.0 Encode-Decode no Fsm\Polar_32bits\system.vhd" 12 | -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_32bits/test_encoder32.vhd: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- 2 | -- Company: 3 | -- Engineer: 4 | -- 5 | -- Create Date: 14:07:49 05/09/2016 6 | -- Design Name: 7 | -- Module Name: D:/Dropbox/Thesis Project/Hardware/Backup/Polar_32bits/test_encoder32.vhd 8 | -- Project Name: Polar_32bits 9 | -- Target Device: 10 | -- Tool versions: 11 | -- Description: 12 | -- 13 | -- VHDL Test Bench Created by ISE for module: Encoder 14 | -- 15 | -- Dependencies: 16 | -- 17 | -- Revision: 18 | -- Revision 0.01 - File Created 19 | -- Additional Comments: 20 | -- 21 | -- Notes: 22 | -- This testbench has been automatically generated using types std_logic and 23 | -- std_logic_vector for the ports of the unit under test. Xilinx recommends 24 | -- that these types always be used for the top-level I/O of a design in order 25 | -- to guarantee that the testbench will bind correctly to the post-implementation 26 | -- simulation model. 27 | -------------------------------------------------------------------------------- 28 | LIBRARY ieee; 29 | USE ieee.std_logic_1164.ALL; 30 | USE ieee.numeric_std.all; 31 | 32 | -- Uncomment the following library declaration if using 33 | -- arithmetic functions with Signed or Unsigned values 34 | --USE ieee.numeric_std.ALL; 35 | 36 | ENTITY test_encoder32 IS 37 | END test_encoder32; 38 | 39 | ARCHITECTURE behavior OF test_encoder32 IS 40 | 41 | -- Component Declaration for the Unit Under Test (UUT) 42 | 43 | COMPONENT Encoder 44 | PORT( 45 | inputs : IN std_logic_vector(15 downto 0); 46 | outputs : OUT std_logic_vector(31 downto 0) 47 | ); 48 | END COMPONENT; 49 | 50 | 51 | --Inputs 52 | signal inputs : std_logic_vector(15 downto 0) := (others => '0'); 53 | 54 | --Outputs 55 | signal outputs : std_logic_vector(31 downto 0); 56 | -- No clocks detected in port list. Replace below with 57 | -- appropriate port name 58 | 59 | BEGIN 60 | -- Instantiate the Unit Under Test (UUT) 61 | uut: Encoder PORT MAP ( 62 | inputs => inputs, 63 | outputs => outputs 64 | ); 65 | 66 | -- Stimulus process 67 | stim_proc: process 68 | variable I : integer range 0 to (2**16)+1 := 0; 69 | begin 70 | -- hold reset state for 100 ns. 71 | wait for 5 ns; 72 | while( I /= (2**16)) loop 73 | inputs <= std_logic_vector(to_unsigned(I,inputs'length)); 74 | I := I + 1; 75 | wait for 1ns; 76 | end loop; 77 | -- insert stimulus here 78 | wait; 79 | end process; 80 | 81 | END; 82 | -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_32bits/uutfsm.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use ieee.std_logic_signed.all; 4 | use ieee.numeric_std.all; 5 | 6 | 7 | entity uutfsm is 8 | port ( clk : in std_logic; 9 | rst : in std_logic; 10 | feedbk:in std_logic; 11 | dec_fin:out std_logic; 12 | conti : out std_logic 13 | ); 14 | end entity; 15 | 16 | architecture struct of uutfsm is 17 | 18 | type state_type is (r0,t0,t1,t2,t3); 19 | signal state: state_type; 20 | signal count1 : std_logic_vector (7 downto 0); 21 | signal count2 : std_logic_vector (9 downto 0); 22 | signal control1,control2: std_logic; 23 | 24 | begin 25 | 26 | control2<=control1 xor feedbk; 27 | 28 | pr1:process(clk) 29 | begin 30 | if clk'event and clk='1' then 31 | if rst='0' then 32 | state<=r0; 33 | count1<=(others=>'0'); 34 | count2<=(others=>'0'); 35 | else 36 | case state is 37 | when r0=> 38 | state<=t0; 39 | when t0=> 40 | control1<='0'; 41 | if (count1="11001000") then 42 | state<=t1; 43 | else 44 | state<=t0; 45 | count1<=count1 + '1'; 46 | end if; 47 | when t1 => 48 | if (count2="1011110011") then 49 | state<=t2; 50 | else 51 | state<=t1; 52 | count2<=count2 + '1'; 53 | end if; 54 | when t2 => 55 | if (control2='1') then 56 | state<=t3; 57 | else 58 | state<=t2; 59 | end if; 60 | when t3 => 61 | control1<=feedbk; 62 | state<=t2; 63 | when others=> 64 | state<=r0; 65 | end case; 66 | end if; 67 | end if; 68 | end process; 69 | 70 | pr2:process(state) 71 | begin 72 | case state is 73 | when r0=> conti<='0'; 74 | dec_fin<='0'; 75 | when t0=> conti<='0'; 76 | dec_fin<='0'; 77 | when t1=> conti<='1'; 78 | dec_fin<='0'; 79 | when t2=> conti<='0'; 80 | dec_fin<='0'; 81 | when t3=> conti<='0'; 82 | dec_fin<='1'; 83 | when others=> conti<='0'; 84 | dec_fin<='0'; 85 | end case; 86 | end process; 87 | 88 | end struct; 89 | -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_32bits/vsim.wlf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Spartak0s/Polar-Codes-Hardware-VHDL/41139d92e8d3e5550fba42f7f550bb1c36afce17/v1.0 Encode-Decoder no Fsm/Polar_32bits/vsim.wlf -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_32bits/work/_lib.qdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Spartak0s/Polar-Codes-Hardware-VHDL/41139d92e8d3e5550fba42f7f550bb1c36afce17/v1.0 Encode-Decoder no Fsm/Polar_32bits/work/_lib.qdb -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_32bits/work/_lib1_1.qdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Spartak0s/Polar-Codes-Hardware-VHDL/41139d92e8d3e5550fba42f7f550bb1c36afce17/v1.0 Encode-Decoder no Fsm/Polar_32bits/work/_lib1_1.qdb -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_32bits/work/_lib1_1.qpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Spartak0s/Polar-Codes-Hardware-VHDL/41139d92e8d3e5550fba42f7f550bb1c36afce17/v1.0 Encode-Decoder no Fsm/Polar_32bits/work/_lib1_1.qpg -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_32bits/work/_lib1_1.qtl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Spartak0s/Polar-Codes-Hardware-VHDL/41139d92e8d3e5550fba42f7f550bb1c36afce17/v1.0 Encode-Decoder no Fsm/Polar_32bits/work/_lib1_1.qtl -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_32bits/work/_vmake: -------------------------------------------------------------------------------- 1 | m255 2 | K4 3 | z0 4 | cModel Technology 5 | -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_32bits/xilinxsim.ini: -------------------------------------------------------------------------------- 1 | work=isim/work 2 | -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_32bits/xlnx_auto_0_xdb/cst.xbcd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Spartak0s/Polar-Codes-Hardware-VHDL/41139d92e8d3e5550fba42f7f550bb1c36afce17/v1.0 Encode-Decoder no Fsm/Polar_32bits/xlnx_auto_0_xdb/cst.xbcd -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_32bits/xst/work/hdllib.ref: -------------------------------------------------------------------------------- 1 | AR encoder behavioral "D:/Dropbox/Thesis Project/Hardware/v1.0 Encode-Decode no Fsm/Polar_32bits/Encoder.vhd" sub00/vhpl15 1463320267 2 | AR f behavioral "D:/Dropbox/Thesis Project/Hardware/v1.0 Encode-Decode no Fsm/Polar_32bits/F.vhd" sub00/vhpl05 1463320257 3 | EN d_ff_gen NULL "D:/Dropbox/Thesis Project/Hardware/v1.0 Encode-Decode no Fsm/Polar_32bits/D_FF.vhd" sub00/vhpl02 1463320254 4 | AR llr_test behavioral "D:/Dropbox/Thesis Project/Hardware/v1.0 Encode-Decode no Fsm/Polar_32bits/llr_test.vhd" sub00/vhpl17 1463320269 5 | AR system behavioral "D:/Dropbox/Thesis Project/Hardware/v1.0 Encode-Decode no Fsm/Polar_32bits/system.vhd" sub00/vhpl21 1463320273 6 | EN d_ff_1bit NULL "D:/Dropbox/Thesis Project/Hardware/v1.0 Encode-Decode no Fsm/Polar_32bits/D_FF_1bit.vhd" sub00/vhpl08 1463320260 7 | EN llr_test NULL "D:/Dropbox/Thesis Project/Hardware/v1.0 Encode-Decode no Fsm/Polar_32bits/llr_test.vhd" sub00/vhpl16 1463320268 8 | AR decoder behavioral "D:/Dropbox/Thesis Project/Hardware/v1.0 Encode-Decode no Fsm/Polar_32bits/Decoder.vhd" sub00/vhpl19 1463320271 9 | EN f NULL "D:/Dropbox/Thesis Project/Hardware/v1.0 Encode-Decode no Fsm/Polar_32bits/F.vhd" sub00/vhpl04 1463320256 10 | EN g NULL "D:/Dropbox/Thesis Project/Hardware/v1.0 Encode-Decode no Fsm/Polar_32bits/G.vhd" sub00/vhpl06 1463320258 11 | EN counter NULL "D:/Dropbox/Thesis Project/Hardware/v1.0 Encode-Decode no Fsm/Polar_32bits/counter.vhd" sub00/vhpl12 1463320264 12 | EN encoder NULL "D:/Dropbox/Thesis Project/Hardware/v1.0 Encode-Decode no Fsm/Polar_32bits/Encoder.vhd" sub00/vhpl14 1463320266 13 | PH mypackage NULL "D:/Dropbox/Thesis Project/Hardware/v1.0 Encode-Decode no Fsm/Polar_32bits/MyPackage.vhd" sub00/vhpl00 1463320252 14 | EN system NULL "D:/Dropbox/Thesis Project/Hardware/v1.0 Encode-Decode no Fsm/Polar_32bits/system.vhd" sub00/vhpl20 1463320272 15 | AR g behavioral "D:/Dropbox/Thesis Project/Hardware/v1.0 Encode-Decode no Fsm/Polar_32bits/G.vhd" sub00/vhpl07 1463320259 16 | EN partialsumgenerator NULL "D:/Dropbox/Thesis Project/Hardware/v1.0 Encode-Decode no Fsm/Polar_32bits/PartialSumGenerator.vhd" sub00/vhpl10 1463320262 17 | AR counter behv "D:/Dropbox/Thesis Project/Hardware/v1.0 Encode-Decode no Fsm/Polar_32bits/counter.vhd" sub00/vhpl13 1463320265 18 | AR partialsumgenerator behavioral "D:/Dropbox/Thesis Project/Hardware/v1.0 Encode-Decode no Fsm/Polar_32bits/PartialSumGenerator.vhd" sub00/vhpl11 1463320263 19 | EN decoder NULL "D:/Dropbox/Thesis Project/Hardware/v1.0 Encode-Decode no Fsm/Polar_32bits/Decoder.vhd" sub00/vhpl18 1463320270 20 | AR d_ff_gen behavioral "D:/Dropbox/Thesis Project/Hardware/v1.0 Encode-Decode no Fsm/Polar_32bits/D_FF.vhd" sub00/vhpl03 1463320255 21 | AR d_ff_1bit behavioral "D:/Dropbox/Thesis Project/Hardware/v1.0 Encode-Decode no Fsm/Polar_32bits/D_FF_1bit.vhd" sub00/vhpl09 1463320261 22 | PB mypackage mypackage "D:/Dropbox/Thesis Project/Hardware/v1.0 Encode-Decode no Fsm/Polar_32bits/MyPackage.vhd" sub00/vhpl01 1463320253 23 | -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_32bits/xst/work/sub00/vhpl00.vho: -------------------------------------------------------------------------------- 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0.01 - File Created 17 | -- Additional Comments: 18 | -- 19 | ---------------------------------------------------------------------------------- 20 | library IEEE; 21 | use IEEE.STD_LOGIC_1164.ALL; 22 | use work.all; 23 | use work.MyPackage.all; 24 | 25 | -- Uncomment the following library declaration if using 26 | -- arithmetic functions with Signed or Unsigned values 27 | --use IEEE.NUMERIC_STD.ALL; 28 | 29 | -- Uncomment the following library declaration if instantiating 30 | -- any Xilinx primitives in this code. 31 | --library UNISIM; 32 | --use UNISIM.VComponents.all; 33 | 34 | entity D_FF_gen is 35 | generic(width: integer := K); 36 | port( 37 | clk : in std_logic; 38 | rst : in std_logic; 39 | ce : in std_logic; 40 | d : in std_logic_vector(width-1 downto 0); 41 | q : out std_logic_vector(width-1 downto 0)); 42 | end entity D_FF_gen; 43 | 44 | architecture Behavioral of D_FF_gen is 45 | begin 46 | process (clk) 47 | begin 48 | if rising_edge(clk) then 49 | if(rst = '1') then 50 | q <= (others => '0'); 51 | else 52 | if( ce = '1') then 53 | q <= d; 54 | end if; 55 | end if; 56 | end if; 57 | end process; 58 | end architecture Behavioral; 59 | 60 | -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_512bits/D_FF_1bit.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Company: 3 | -- Engineer: 4 | -- 5 | -- Create Date: 14:03:21 02/23/2016 6 | -- Design Name: 7 | -- Module Name: D_FF - Behavioral 8 | -- Project Name: 9 | -- Target Devices: 10 | -- Tool versions: 11 | -- Description: 12 | -- 13 | -- Dependencies: 14 | -- 15 | -- Revision: 16 | -- Revision 0.01 - File Created 17 | -- Additional Comments: 18 | -- 19 | ---------------------------------------------------------------------------------- 20 | library IEEE; 21 | use IEEE.STD_LOGIC_1164.ALL; 22 | use work.all; 23 | use work.MyPackage.all; 24 | 25 | -- Uncomment the following library declaration if using 26 | -- arithmetic functions with Signed or Unsigned values 27 | --use IEEE.NUMERIC_STD.ALL; 28 | 29 | -- Uncomment the following library declaration if instantiating 30 | -- any Xilinx primitives in this code. 31 | --library UNISIM; 32 | --use UNISIM.VComponents.all; 33 | 34 | entity D_FF_1bit is 35 | port( 36 | clk : in std_logic; 37 | rst : in std_logic; 38 | ce : in std_logic; 39 | d : in std_logic; 40 | q : out std_logic); 41 | end entity D_FF_1bit; 42 | 43 | architecture Behavioral of D_FF_1bit is 44 | begin 45 | process (clk) 46 | begin 47 | if rising_edge(clk) then 48 | if(rst = '1') then 49 | q <= '0'; 50 | else 51 | if( ce = '1') then 52 | q <= d; 53 | end if; 54 | end if; 55 | end if; 56 | end process; 57 | end architecture Behavioral; 58 | 59 | -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_512bits/D_FF_N.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Company: 3 | -- Engineer: 4 | -- 5 | -- Create Date: 14:03:21 02/23/2016 6 | -- Design Name: 7 | -- Module Name: D_FF - Behavioral 8 | -- Project Name: 9 | -- Target Devices: 10 | -- Tool versions: 11 | -- Description: 12 | -- 13 | -- Dependencies: 14 | -- 15 | -- Revision: 16 | -- Revision 0.01 - File Created 17 | -- Additional Comments: 18 | -- 19 | ---------------------------------------------------------------------------------- 20 | library IEEE; 21 | use IEEE.STD_LOGIC_1164.ALL; 22 | use work.all; 23 | use work.MyPackage.all; 24 | 25 | -- Uncomment the following library declaration if using 26 | -- arithmetic functions with Signed or Unsigned values 27 | --use IEEE.NUMERIC_STD.ALL; 28 | 29 | -- Uncomment the following library declaration if instantiating 30 | -- any Xilinx primitives in this code. 31 | --library UNISIM; 32 | --use UNISIM.VComponents.all; 33 | 34 | entity D_FF_N is 35 | generic(width: integer := integer_part + fractional_part); 36 | port( 37 | clk : in std_logic; 38 | rst : in std_logic; 39 | d : in std_logic_vector(width-1 downto 0); 40 | q : out std_logic_vector(width-1 downto 0)); 41 | end entity D_FF_N; 42 | 43 | architecture Behavioral of D_FF_N is 44 | begin 45 | process (clk) 46 | begin 47 | if rising_edge(clk) then 48 | if(rst = '1') then 49 | q <= (others => '0'); 50 | else 51 | q <= d; 52 | end if; 53 | end if; 54 | end process; 55 | end architecture Behavioral; 56 | 57 | -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_512bits/D_FF_en.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Company: 3 | -- Engineer: 4 | -- 5 | -- Create Date: 18:35:08 04/04/2016 6 | -- Design Name: 7 | -- Module Name: D_FF_en - Behavioral 8 | -- Project Name: 9 | -- Target Devices: 10 | -- Tool versions: 11 | -- Description: 12 | -- 13 | -- Dependencies: 14 | -- 15 | -- Revision: 16 | -- Revision 0.01 - File Created 17 | -- Additional Comments: 18 | -- 19 | ---------------------------------------------------------------------------------- 20 | library IEEE; 21 | use IEEE.STD_LOGIC_1164.ALL; 22 | use work.all; 23 | use work.MyPackage.all; 24 | -- Uncomment the following library declaration if using 25 | -- arithmetic functions with Signed or Unsigned values 26 | --use IEEE.NUMERIC_STD.ALL; 27 | 28 | -- Uncomment the following library declaration if instantiating 29 | -- any Xilinx primitives in this code. 30 | --library UNISIM; 31 | --use UNISIM.VComponents.all; 32 | 33 | entity D_FF_en is 34 | generic( width: integer := K); 35 | Port ( d : in STD_LOGIC_VECTOR (width-1 downto 0); 36 | q : out STD_LOGIC_VECTOR (width-1 downto 0); 37 | clk : in STD_LOGIC; 38 | rst : in std_logic; 39 | en : in STD_LOGIC); 40 | end D_FF_en; 41 | 42 | architecture Behavioral of D_FF_en is 43 | 44 | begin 45 | D_FF_proc:process (clk) 46 | begin 47 | if(rising_edge(clk)) then 48 | if (rst = '1') then 49 | q <= (others => '0'); 50 | else 51 | if (en='1') then 52 | q <= d; 53 | end if; 54 | end if; 55 | end if; 56 | end process; 57 | end architecture Behavioral; -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_512bits/Decoder512.bmm: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Spartak0s/Polar-Codes-Hardware-VHDL/41139d92e8d3e5550fba42f7f550bb1c36afce17/v1.0 Encode-Decoder no Fsm/Polar_512bits/Decoder512.bmm -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_512bits/Decoder512_beh.prj: -------------------------------------------------------------------------------- 1 | vhdl work "MyPackage.vhd" 2 | vhdl work "PartialSumGenerator.vhd" 3 | vhdl work "G.vhd" 4 | vhdl work "F.vhd" 5 | vhdl work "D_FF_N.vhd" 6 | vhdl work "D_FF.vhd" 7 | vhdl work "Decoder512.vhd" 8 | -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_512bits/F.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Company: 3 | -- Engineer: 4 | -- 5 | -- Create Date: 17:34:30 02/06/2016 6 | -- Design Name: 7 | -- Module Name: F - Behavioral 8 | -- Project Name: 9 | -- Target Devices: 10 | -- Tool versions: 11 | -- Description: 12 | -- 13 | -- Dependencies: 14 | -- 15 | -- Revision: 16 | -- Revision 0.01 - File Created 17 | -- Additional Comments: 18 | -- 19 | ---------------------------------------------------------------------------------- 20 | library IEEE; 21 | use IEEE.STD_LOGIC_1164.ALL; 22 | use IEEE.NUMERIC_STD.ALL; 23 | use work.MyPackage.all; 24 | 25 | -- Uncomment the following library declaration if using 26 | -- arithmetic functions with Signed or Unsigned values 27 | 28 | 29 | -- Uncomment the following library declaration if instantiating 30 | -- any Xilinx primitives in this code. 31 | --library UNISIM; 32 | --use UNISIM.VComponents.all; 33 | 34 | entity F is 35 | Port ( lamdaA : in llr; 36 | lamdaB : in llr; 37 | lamdaOut : out llr); 38 | end F; 39 | 40 | architecture Behavioral of F is 41 | signal positive_lamdaA, positive_lamdaB: signed(integer_part+fractional_part-1 downto 0); 42 | signal min: llr; 43 | signal sign: STD_LOGIC; 44 | begin 45 | sign <= lamdaA(sign_bit) xor lamdaB(sign_bit); 46 | positive_lamdaA <= signed(not(lamdaA)) + one when lamdaA(sign_bit) = '1' 47 | else signed(lamdaA); 48 | positive_lamdaB <= signed(not(lamdaB)) + one when lamdaB(sign_bit) = '1' 49 | else signed(lamdaB); 50 | min <= std_logic_vector(positive_lamdaA(integer_part+fractional_part-1 downto 0)) when positive_lamdaA < positive_lamdaB 51 | else std_logic_vector(positive_lamdaB(integer_part+fractional_part-1 downto 0)); 52 | lamdaOut <= min when sign = '0' 53 | else std_logic_vector(signed(not(min)) + one); 54 | 55 | end Behavioral; -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_512bits/G.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Company: 3 | -- Engineer: 4 | -- 5 | -- Create Date: 18:18:52 02/06/2016 6 | -- Design Name: 7 | -- Module Name: G - Behavioral 8 | -- Project Name: 9 | -- Target Devices: 10 | -- Tool versions: 11 | -- Description: 12 | -- 13 | -- Dependencies: 14 | -- 15 | -- Revision: 16 | -- Revision 0.01 - File Created 17 | -- Additional Comments: 18 | -- 19 | ---------------------------------------------------------------------------------- 20 | library IEEE; 21 | use IEEE.STD_LOGIC_1164.ALL; 22 | use IEEE.NUMERIC_STD.ALL; 23 | use work.MyPackage.all; 24 | 25 | -- Uncomment the following library declaration if using 26 | -- arithmetic functions with Signed or Unsigned values 27 | --use IEEE.NUMERIC_STD.ALL; 28 | 29 | -- Uncomment the following library declaration if instantiating 30 | -- any Xilinx primitives in this code. 31 | --library UNISIM; 32 | --use UNISIM.VComponents.all; 33 | 34 | entity G is 35 | Port ( lamdaA : in llr; 36 | lamdaB : in llr; 37 | s : in STD_LOGIC; 38 | lamdaOut : out llr); 39 | end G; 40 | 41 | architecture Behavioral of G is 42 | begin 43 | lamdaOut <= std_logic_vector(signed(lamdaA) + signed(lamdaB)) when s = '0' 44 | else std_logic_vector((signed(not(lamdaA)) + one) + signed(lamdaB)); 45 | 46 | end Behavioral; -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_512bits/IO_Outputs.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Company: 3 | -- Engineer: 4 | -- 5 | -- Create Date: 16:15:25 04/05/2016 6 | -- Design Name: 7 | -- Module Name: IO_Outputs - Behavioral 8 | -- Project Name: 9 | -- Target Devices: 10 | -- Tool versions: 11 | -- Description: 12 | -- 13 | -- Dependencies: 14 | -- 15 | -- Revision: 16 | -- Revision 0.01 - File Created 17 | -- Additional Comments: 18 | -- 19 | ---------------------------------------------------------------------------------- 20 | library IEEE; 21 | use IEEE.STD_LOGIC_1164.ALL; 22 | use work.all; 23 | use work.MyPackage.all; 24 | 25 | -- Uncomment the following library declaration if using 26 | -- arithmetic functions with Signed or Unsigned values 27 | --use IEEE.NUMERIC_STD.ALL; 28 | 29 | -- Uncomment the following library declaration if instantiating 30 | -- any Xilinx primitives in this code. 31 | --library UNISIM; 32 | --use UNISIM.VComponents.all; 33 | 34 | entity IO_Outputs is 35 | Port ( clk : in std_logic; 36 | inputs : in STD_LOGIC_VECTOR (N/2-1 downto 0); 37 | outputs : out STD_LOGIC_VECTOR (K-1 downto 0)); 38 | end IO_Outputs; 39 | 40 | architecture Behavioral of IO_Outputs is 41 | signal counter_out: std_logic_vector(NdivKbits-1 downto 0); 42 | begin 43 | 44 | Mux_counter: entity work.counter generic map(width => NdivKbits) port map( 45 | clk => clk, 46 | clear => '0', 47 | count => '1', 48 | Q => counter_out); 49 | 50 | MUX: entity work.mux generic map(in_width => N/2, 51 | out_width => K, 52 | sel_width => NdivKbits) 53 | port map(sel => counter_out, 54 | inputs => inputs, 55 | outputs => outputs); 56 | 57 | end Behavioral; -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_512bits/MyPackage.vhd: -------------------------------------------------------------------------------- 1 | -- 2 | -- Package File Template 3 | -- 4 | -- Purpose: This package defines supplemental types, subtypes, 5 | -- constants, and functions 6 | -- 7 | -- To use any of the example code shown below, uncomment the lines and modify as necessary 8 | -- 9 | 10 | library IEEE; 11 | use IEEE.STD_LOGIC_1164.all; 12 | use IEEE.NUMERIC_STD.ALL; 13 | 14 | package MyPackage is 15 | -- Declare functions and procedure 16 | -- 17 | -- function (signal : in ) return ; 18 | -- procedure ( : in ); 19 | -- 20 | 21 | -- Declare constants 22 | -- 23 | constant K : integer := 256; 24 | constant N : integer := 512; 25 | constant stages : integer := 9; 26 | constant num_of_partials : integer := stages * N; 27 | constant integer_part : integer := 10; 28 | constant fractional_part : integer := 2; 29 | constant sign_bit : integer := integer_part + fractional_part -1; 30 | constant one : signed(integer_part+fractional_part-1 downto 0) := (0=>'1',others=>'0'); 31 | -- 32 | subtype s_1d is std_logic_vector(0 to N/2-1); 33 | type s_2d is array (1 to stages) of s_1d; 34 | subtype llr is std_logic_vector(integer_part+fractional_part-1 downto 0); 35 | type data is array (0 to N-1) of llr; 36 | type llr_2d is array (0 to stages) of data; 37 | -- record 38 | -- : std_logic_vector( 7 downto 0); 39 | -- : std_logic; 40 | -- end record; 41 | -- 42 | 43 | 44 | end MyPackage; 45 | 46 | package body MyPackage is 47 | 48 | ---- Example 1 49 | -- function (signal : in ) return is 50 | -- variable : ; 51 | -- begin 52 | -- := xor ; 53 | -- return ; 54 | -- end ; 55 | 56 | ---- Example 2 57 | -- function (signal : in ; 58 | -- signal : in ) return is 59 | -- begin 60 | -- if ( = '1') then 61 | -- return ; 62 | -- else 63 | -- return 'Z'; 64 | -- end if; 65 | -- end ; 66 | 67 | ---- Procedure Example 68 | -- procedure ( : in ) is 69 | -- 70 | -- begin 71 | -- 72 | -- end ; 73 | 74 | end MyPackage; 75 | -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_512bits/Polar_512bits.gise: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 11.1 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_512bits/_ngo/system_cs_signalbrowser.ver: -------------------------------------------------------------------------------- 1 | ISE Version 14.2.0 2 | -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_512bits/_xmsgs/ngcbuild.xmsgs: -------------------------------------------------------------------------------- 1 | 2 | 7 | 8 | 9 | 10 | -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_512bits/_xmsgs/pn_parser.xmsgs: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | Parsing VHDL file "D:/Dropbox/Thesis Project/Hardware/v1.0 Encode-Decode no Fsm/Polar_512bits/counter.vhd" into library work 12 | 13 | 14 | 15 | 16 | -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_512bits/chipscope512.cdc: -------------------------------------------------------------------------------- 1 | #ChipScope Core Inserter Project File Version 3.0 2 | #Sun May 08 19:31:02 EEST 2016 3 | Project.device.designInputFile=D\:\\Dropbox\\Thesis Project\\Hardware\\Simple after Athens\\Polar_512bits 4 | Project.device.designOutputFile=D\:\\Dropbox\\Thesis Project\\Hardware\\Simple after Athens\\Polar_512bits\\Polar_512bits.ngo 5 | Project.device.deviceFamily=15 6 | Project.device.enableRPMs=true 7 | Project.device.outputDirectory=D\:\\Dropbox\\Thesis Project\\Hardware\\Simple after Athens\\Polar_512bits 8 | Project.device.useSRL16=true 9 | Project.filter.dimension=0 10 | Project.icon.boundaryScanChain=1 11 | Project.icon.enableExtTriggerIn=false 12 | Project.icon.enableExtTriggerOut=false 13 | Project.icon.triggerInPinName= 14 | Project.icon.triggerOutPinName= 15 | Project.unit.dimension=0 16 | -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_512bits/counter.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Company: 3 | -- Engineer: 4 | -- 5 | -- Create Date: 15:06:44 04/06/2016 6 | -- Design Name: 7 | -- Module Name: counter - Behavioral 8 | -- Project Name: 9 | -- Target Devices: 10 | -- Tool versions: 11 | -- Description: 12 | -- 13 | -- Dependencies: 14 | -- 15 | -- Revision: 16 | -- Revision 0.01 - File Created 17 | -- Additional Comments: 18 | -- 19 | ---------------------------------------------------------------------------------- 20 | library IEEE; 21 | use IEEE.STD_LOGIC_1164.ALL; 22 | use work.MyPackage.all; 23 | use ieee.std_logic_unsigned.all; 24 | -- Uncomment the following library declaration if using 25 | -- arithmetic functions with Signed or Unsigned values 26 | --use IEEE.NUMERIC_STD.ALL; 27 | 28 | -- Uncomment the following library declaration if instantiating 29 | -- any Xilinx primitives in this code. 30 | --library UNISIM; 31 | --use UNISIM.VComponents.all; 32 | 33 | entity counter is 34 | generic (width : integer := 8); 35 | Port ( clk : in STD_LOGIC; 36 | rst : in STD_LOGIC; 37 | count : in STD_LOGIC; 38 | Q : out STD_LOGIC_VECTOR(width-1 downto 0)); 39 | end counter; 40 | 41 | architecture behv of counter is 42 | signal Pre_Q: std_logic_vector(width-1 downto 0):= (others=>'0'); 43 | begin 44 | 45 | -- behavior describe the counter 46 | 47 | process(clk) 48 | begin 49 | if(rising_edge(clk)) then 50 | if rst = '1' then 51 | Pre_Q <= (others =>'0'); 52 | else 53 | if count = '1' then 54 | Pre_Q <= Pre_Q + 1; 55 | end if; 56 | end if; 57 | end if; 58 | end process; 59 | 60 | -- concurrent assignment statement 61 | Q <= Pre_Q; 62 | 63 | end behv; 64 | 65 | -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_512bits/encoder_testbench.vhd: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- 2 | -- Company: 3 | -- Engineer: 4 | -- 5 | -- Create Date: 12:09:57 05/09/2016 6 | -- Design Name: 7 | -- Module Name: D:/Dropbox/Thesis Project/Hardware/Simple after Athens/Polar_512bits/encoder_testbench.vhd 8 | -- Project Name: Polar_512bits 9 | -- Target Device: 10 | -- Tool versions: 11 | -- Description: 12 | -- 13 | -- VHDL Test Bench Created by ISE for module: Encoder512 14 | -- 15 | -- Dependencies: 16 | -- 17 | -- Revision: 18 | -- Revision 0.01 - File Created 19 | -- Additional Comments: 20 | -- 21 | -- Notes: 22 | -- This testbench has been automatically generated using types std_logic and 23 | -- std_logic_vector for the ports of the unit under test. Xilinx recommends 24 | -- that these types always be used for the top-level I/O of a design in order 25 | -- to guarantee that the testbench will bind correctly to the post-implementation 26 | -- simulation model. 27 | -------------------------------------------------------------------------------- 28 | LIBRARY ieee; 29 | USE ieee.std_logic_1164.ALL; 30 | use ieee.numeric_std.all; 31 | -- Uncomment the following library declaration if using 32 | -- arithmetic functions with Signed or Unsigned values 33 | --USE ieee.numeric_std.ALL; 34 | 35 | ENTITY encoder_testbench IS 36 | END encoder_testbench; 37 | 38 | ARCHITECTURE behavior OF encoder_testbench IS 39 | 40 | -- Component Declaration for the Unit Under Test (UUT) 41 | 42 | COMPONENT Encoder512 43 | PORT( 44 | inputs : IN std_logic_vector(255 downto 0); 45 | outputs : OUT std_logic_vector(511 downto 0) 46 | ); 47 | END COMPONENT; 48 | 49 | 50 | --Inputs 51 | signal inputs : std_logic_vector(255 downto 0) := (others => '0'); 52 | 53 | --Outputs 54 | signal outputs : std_logic_vector(511 downto 0); 55 | -- No clocks detected in port list. Replace below with 56 | -- appropriate port name 57 | 58 | 59 | BEGIN 60 | 61 | -- Instantiate the Unit Under Test (UUT) 62 | uut: Encoder512 PORT MAP ( 63 | inputs => inputs, 64 | outputs => outputs 65 | ); 66 | 67 | -- Stimulus process 68 | stim_proc: process 69 | begin 70 | -- hold reset state for 100 ns. 71 | wait for 100 ns; 72 | inputs <= (others =>'0'); 73 | wait for 50ns; 74 | inputs <= std_logic_vector(to_unsigned(inputs)+1); 75 | wait for 50ns; 76 | inputs <= std_logic_vector(integer(inputs)+1); 77 | wait for 50ns; 78 | inputs <= std_logic_vector(integer(inputs)+1); 79 | wait for 50ns; 80 | inputs <= std_logic_vector(integer(inputs)+1); 81 | wait for 50ns; 82 | inputs <= std_logic_vector(integer(inputs)+1); 83 | wait for 50ns; 84 | inputs <= std_logic_vector(integer(inputs)+1); 85 | -- insert stimulus here 86 | 87 | wait; 88 | end process; 89 | 90 | END; 91 | -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_512bits/fuse.xmsgs: -------------------------------------------------------------------------------- 1 | 2 | 7 | 8 | 9 | 10 | -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_512bits/fuseRelaunch.cmd: -------------------------------------------------------------------------------- 1 | -intstyle "ise" -incremental -o "D:/Dropbox/Thesis Project/Hardware/v1.0 Encode-Decode no Fsm/Polar_512bits/system_isim_beh.exe" -prj "D:/Dropbox/Thesis Project/Hardware/v1.0 Encode-Decode no Fsm/Polar_512bits/system_beh.prj" "work.system" 2 | -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_512bits/llr_test.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Company: 3 | -- Engineer: 4 | -- 5 | -- Create Date: 14:27:04 04/22/2016 6 | -- Design Name: 7 | -- Module Name: llr_test - Behavioral 8 | -- Project Name: 9 | -- Target Devices: 10 | -- Tool versions: 11 | -- Description: 12 | -- 13 | -- Dependencies: 14 | -- 15 | -- Revision: 16 | -- Revision 0.01 - File Created 17 | -- Additional Comments: 18 | -- 19 | ---------------------------------------------------------------------------------- 20 | library IEEE; 21 | use IEEE.STD_LOGIC_1164.ALL; 22 | use work.all; 23 | use work.MyPackage.all; 24 | 25 | -- Uncomment the following library declaration if using 26 | -- arithmetic functions with Signed or Unsigned values 27 | --use IEEE.NUMERIC_STD.ALL; 28 | 29 | -- Uncomment the following library declaration if instantiating 30 | -- any Xilinx primitives in this code. 31 | --library UNISIM; 32 | --use UNISIM.VComponents.all; 33 | 34 | entity llr_test is 35 | Port (inputs: in std_logic_vector(N-1 downto 0); 36 | outputs: out data); 37 | end llr_test; 38 | 39 | architecture Behavioral of llr_test is 40 | constant pos_llr : std_logic_vector(integer_part + fractional_part -1 downto 0):= "000000000001"; -- +1 41 | constant neg_llr : std_logic_vector(integer_part + fractional_part -1 downto 0):= "111111111111"; -- -1 42 | begin 43 | Decision: 44 | for i in 0 to N-1 generate 45 | Decision1: 46 | outputs(i) <= pos_llr when inputs(i)='0' 47 | else neg_llr; 48 | end generate Decision; 49 | end Behavioral; 50 | 51 | -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_512bits/mux.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Company: 3 | -- Engineer: 4 | -- 5 | -- Create Date: 16:19:54 04/05/2016 6 | -- Design Name: 7 | -- Module Name: mux - Behavioral 8 | -- Project Name: 9 | -- Target Devices: 10 | -- Tool versions: 11 | -- Description: 12 | -- 13 | -- Dependencies: 14 | -- 15 | -- Revision: 16 | -- Revision 0.01 - File Created 17 | -- Additional Comments: 18 | -- 19 | ---------------------------------------------------------------------------------- 20 | library IEEE; 21 | use IEEE.STD_LOGIC_1164.ALL; 22 | use work.all; 23 | use work.MyPackage.all; 24 | 25 | -- Uncomment the following library declaration if using 26 | -- arithmetic functions with Signed or Unsigned values 27 | use IEEE.NUMERIC_STD.ALL; 28 | 29 | -- Uncomment the following library declaration if instantiating 30 | -- any Xilinx primitives in this code. 31 | --library UNISIM; 32 | --use UNISIM.VComponents.all; 33 | 34 | entity mux is 35 | generic (in_width : integer := 4;--N; 36 | out_width : integer := 2; 37 | sel_width : integer := 2;--Ndiv2bits; 38 | ff_number : integer := 2);--N/2); 39 | Port ( sel : in std_logic_vector(sel_width-1 downto 0); 40 | inputs : in STD_LOGIC_VECTOR (in_width-1 downto 0); 41 | outputs : out STD_LOGIC_VECTOR (out_width-1 downto 0)); 42 | end mux; 43 | 44 | architecture Behavioral of mux is 45 | begin 46 | 47 | outputs<= inputs(to_integer(unsigned(sel))*out_width+out_width-1 downto to_integer(unsigned(sel))*out_width); 48 | --Mux_process:process(sel,inputs) is 49 | --variable tmp : std_logic_vector(out_width-1 downto 0); 50 | --begin 51 | -- for i in 0 to ff_number-1 loop 52 | -- if i = unsigned(sel) then 53 | -- tmp := inputs(((out_width-1)+i*out_width) downto (i*out_width)); 54 | -- end if; 55 | -- end loop; 56 | --outputs <= tmp; 57 | --end process; 58 | 59 | end Behavioral; 60 | 61 | -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_512bits/pepExtractor.prj: -------------------------------------------------------------------------------- 1 | work "D_FF.vhd" 2 | work "D_FF_N.vhd" 3 | work "Decoder512.vhd" 4 | work "F.vhd" 5 | work "G.vhd" 6 | work "MyPackage.vhd" 7 | work "PartialSumGenerator.vhd" 8 | -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_512bits/system.prj: -------------------------------------------------------------------------------- 1 | vhdl work "MyPackage.vhd" 2 | vhdl work "PartialSumGenerator.vhd" 3 | vhdl work "G.vhd" 4 | vhdl work "F.vhd" 5 | vhdl work "D_FF_1bit.vhd" 6 | vhdl work "D_FF.vhd" 7 | vhdl work "llr_test.vhd" 8 | vhdl work "Encoder512.vhd" 9 | vhdl work "Decoder512.vhd" 10 | vhdl work "counter.vhd" 11 | vhdl work "system.vhd" 12 | -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_512bits/system.xst: -------------------------------------------------------------------------------- 1 | set -tmpdir "D:/Dropbox/Thesis Project/Hardware/v1.0 Encode-Decode no Fsm/Polar_512bits/xst/projnav.tmp" 2 | set -xsthdpdir "D:/Dropbox/Thesis Project/Hardware/v1.0 Encode-Decode no Fsm/Polar_512bits/xst" 3 | elaborate 4 | -ifn system.prj 5 | -ifmt mixed 6 | -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_512bits/system_vhdl.prj: -------------------------------------------------------------------------------- 1 | vhdl work "D:\Dropbox\Thesis Project\Hardware\v1.0 Encode-Decode no Fsm\Polar_512bits\MyPackage.vhd" 2 | vhdl work "D:\Dropbox\Thesis Project\Hardware\v1.0 Encode-Decode no Fsm\Polar_512bits\PartialSumGenerator.vhd" 3 | vhdl work "D:\Dropbox\Thesis Project\Hardware\v1.0 Encode-Decode no Fsm\Polar_512bits\G.vhd" 4 | vhdl work "D:\Dropbox\Thesis Project\Hardware\v1.0 Encode-Decode no Fsm\Polar_512bits\F.vhd" 5 | vhdl work "D:\Dropbox\Thesis Project\Hardware\v1.0 Encode-Decode no Fsm\Polar_512bits\D_FF_1bit.vhd" 6 | vhdl work "D:\Dropbox\Thesis Project\Hardware\v1.0 Encode-Decode no Fsm\Polar_512bits\D_FF.vhd" 7 | vhdl work "D:\Dropbox\Thesis Project\Hardware\v1.0 Encode-Decode no Fsm\Polar_512bits\llr_test.vhd" 8 | vhdl work "D:\Dropbox\Thesis Project\Hardware\v1.0 Encode-Decode no Fsm\Polar_512bits\Encoder512.vhd" 9 | vhdl work "D:\Dropbox\Thesis Project\Hardware\v1.0 Encode-Decode no Fsm\Polar_512bits\Decoder512.vhd" 10 | vhdl work "D:\Dropbox\Thesis Project\Hardware\v1.0 Encode-Decode no Fsm\Polar_512bits\counter.vhd" 11 | vhdl work "D:\Dropbox\Thesis Project\Hardware\v1.0 Encode-Decode no Fsm\Polar_512bits\system.vhd" 12 | -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_512bits/test_decoder_beh.prj: -------------------------------------------------------------------------------- 1 | vhdl work "MyPackage.vhd" 2 | vhdl work "PartialSumGenerator.vhd" 3 | vhdl work "G.vhd" 4 | vhdl work "F.vhd" 5 | vhdl work "D_FF_N.vhd" 6 | vhdl work "D_FF.vhd" 7 | vhdl work "Decoder512.vhd" 8 | vhdl work "test_decoder.vhd" 9 | -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_512bits/test_encoder512.vhd: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- 2 | -- Company: 3 | -- Engineer: 4 | -- 5 | -- Create Date: 12:33:32 05/09/2016 6 | -- Design Name: 7 | -- Module Name: D:/Dropbox/Thesis Project/Hardware/Simple after Athens/Polar_512bits/test_encoder512.vhd 8 | -- Project Name: Polar_512bits 9 | -- Target Device: 10 | -- Tool versions: 11 | -- Description: 12 | -- 13 | -- VHDL Test Bench Created by ISE for module: Encoder512 14 | -- 15 | -- Dependencies: 16 | -- 17 | -- Revision: 18 | -- Revision 0.01 - File Created 19 | -- Additional Comments: 20 | -- 21 | -- Notes: 22 | -- This testbench has been automatically generated using types std_logic and 23 | -- std_logic_vector for the ports of the unit under test. Xilinx recommends 24 | -- that these types always be used for the top-level I/O of a design in order 25 | -- to guarantee that the testbench will bind correctly to the post-implementation 26 | -- simulation model. 27 | -------------------------------------------------------------------------------- 28 | LIBRARY ieee; 29 | USE ieee.std_logic_1164.ALL; 30 | use ieee.math_real.all; 31 | use ieee.numeric_std.all; 32 | 33 | -- Uncomment the following library declaration if using 34 | -- arithmetic functions with Signed or Unsigned values 35 | --USE ieee.numeric_std.ALL; 36 | 37 | ENTITY test_encoder512 IS 38 | END test_encoder512; 39 | 40 | ARCHITECTURE behavior OF test_encoder512 IS 41 | 42 | -- Component Declaration for the Unit Under Test (UUT) 43 | 44 | COMPONENT Encoder512 45 | PORT( 46 | inputs : IN std_logic_vector(255 downto 0); 47 | outputs : OUT std_logic_vector(511 downto 0) 48 | ); 49 | END COMPONENT; 50 | 51 | 52 | --Inputs 53 | signal inputs : std_logic_vector(255 downto 0) := (others => '0'); 54 | 55 | --Outputs 56 | signal outputs : std_logic_vector(511 downto 0); 57 | -- No clocks detected in port list. Replace below with 58 | -- appropriate port name 59 | 60 | BEGIN 61 | 62 | -- Instantiate the Unit Under Test (UUT) 63 | uut: Encoder512 PORT MAP ( 64 | inputs => inputs, 65 | outputs => outputs 66 | ); 67 | 68 | 69 | 70 | -- Stimulus process 71 | stim_proc: process 72 | variable I : integer range 0 to (2**256)+1 := 0; 73 | begin 74 | -- hold reset state for 100 ns. 75 | wait for 10 ns; 76 | while( I /= (2**20)) loop 77 | inputs <= std_logic_vector(to_unsigned(I,inputs'length)); 78 | I := I + 1; 79 | wait for 1ns; 80 | end loop; 81 | -- insert stimulus here 82 | wait; 83 | end process; 84 | 85 | END; 86 | -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_512bits/test_encoder512_isim_beh1.wdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Spartak0s/Polar-Codes-Hardware-VHDL/41139d92e8d3e5550fba42f7f550bb1c36afce17/v1.0 Encode-Decoder no Fsm/Polar_512bits/test_encoder512_isim_beh1.wdb -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_512bits/xst/work/hdllib.ref: -------------------------------------------------------------------------------- 1 | EN encoder512 NULL "D:/Dropbox/Thesis Project/Hardware/v1.0 Encode-Decode no Fsm/Polar_512bits/Encoder512.vhd" sub00/vhpl14 1463319208 2 | AR f behavioral "D:/Dropbox/Thesis Project/Hardware/v1.0 Encode-Decode no Fsm/Polar_512bits/F.vhd" sub00/vhpl05 1463319199 3 | EN d_ff_gen NULL "D:/Dropbox/Thesis Project/Hardware/v1.0 Encode-Decode no Fsm/Polar_512bits/D_FF.vhd" sub00/vhpl02 1463319196 4 | AR llr_test behavioral "D:/Dropbox/Thesis Project/Hardware/v1.0 Encode-Decode no Fsm/Polar_512bits/llr_test.vhd" sub00/vhpl17 1463319211 5 | AR system behavioral "D:/Dropbox/Thesis Project/Hardware/v1.0 Encode-Decode no Fsm/Polar_512bits/system.vhd" sub00/vhpl21 1463319215 6 | EN d_ff_1bit NULL "D:/Dropbox/Thesis Project/Hardware/v1.0 Encode-Decode no Fsm/Polar_512bits/D_FF_1bit.vhd" sub00/vhpl08 1463319202 7 | EN llr_test NULL "D:/Dropbox/Thesis Project/Hardware/v1.0 Encode-Decode no Fsm/Polar_512bits/llr_test.vhd" sub00/vhpl16 1463319210 8 | AR decoder512 behavioral "D:/Dropbox/Thesis Project/Hardware/v1.0 Encode-Decode no Fsm/Polar_512bits/Decoder512.vhd" sub00/vhpl19 1463319213 9 | EN f NULL "D:/Dropbox/Thesis Project/Hardware/v1.0 Encode-Decode no Fsm/Polar_512bits/F.vhd" sub00/vhpl04 1463319198 10 | EN g NULL "D:/Dropbox/Thesis Project/Hardware/v1.0 Encode-Decode no Fsm/Polar_512bits/G.vhd" sub00/vhpl06 1463319200 11 | EN counter NULL "D:/Dropbox/Thesis Project/Hardware/v1.0 Encode-Decode no Fsm/Polar_512bits/counter.vhd" sub00/vhpl12 1463319206 12 | EN decoder512 NULL "D:/Dropbox/Thesis Project/Hardware/v1.0 Encode-Decode no Fsm/Polar_512bits/Decoder512.vhd" sub00/vhpl18 1463319212 13 | PH mypackage NULL "D:/Dropbox/Thesis Project/Hardware/v1.0 Encode-Decode no Fsm/Polar_512bits/MyPackage.vhd" sub00/vhpl00 1463319194 14 | EN system NULL "D:/Dropbox/Thesis Project/Hardware/v1.0 Encode-Decode no Fsm/Polar_512bits/system.vhd" sub00/vhpl20 1463319214 15 | AR g behavioral "D:/Dropbox/Thesis Project/Hardware/v1.0 Encode-Decode no Fsm/Polar_512bits/G.vhd" sub00/vhpl07 1463319201 16 | EN partialsumgenerator NULL "D:/Dropbox/Thesis Project/Hardware/v1.0 Encode-Decode no Fsm/Polar_512bits/PartialSumGenerator.vhd" sub00/vhpl10 1463319204 17 | AR counter behv "D:/Dropbox/Thesis Project/Hardware/v1.0 Encode-Decode no Fsm/Polar_512bits/counter.vhd" sub00/vhpl13 1463319207 18 | AR encoder512 behavioral "D:/Dropbox/Thesis Project/Hardware/v1.0 Encode-Decode no Fsm/Polar_512bits/Encoder512.vhd" sub00/vhpl15 1463319209 19 | AR partialsumgenerator behavioral "D:/Dropbox/Thesis Project/Hardware/v1.0 Encode-Decode no Fsm/Polar_512bits/PartialSumGenerator.vhd" sub00/vhpl11 1463319205 20 | AR d_ff_gen behavioral "D:/Dropbox/Thesis Project/Hardware/v1.0 Encode-Decode no Fsm/Polar_512bits/D_FF.vhd" sub00/vhpl03 1463319197 21 | AR d_ff_1bit behavioral "D:/Dropbox/Thesis Project/Hardware/v1.0 Encode-Decode no Fsm/Polar_512bits/D_FF_1bit.vhd" sub00/vhpl09 1463319203 22 | PB mypackage mypackage "D:/Dropbox/Thesis Project/Hardware/v1.0 Encode-Decode no Fsm/Polar_512bits/MyPackage.vhd" sub00/vhpl01 1463319195 23 | -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_512bits/xst/work/sub00/vhpl00.vho: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Spartak0s/Polar-Codes-Hardware-VHDL/41139d92e8d3e5550fba42f7f550bb1c36afce17/v1.0 Encode-Decoder no Fsm/Polar_512bits/xst/work/sub00/vhpl00.vho -------------------------------------------------------------------------------- /v1.0 Encode-Decoder no Fsm/Polar_512bits/xst/work/sub00/vhpl01.vho: -------------------------------------------------------------------------------- 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