├── hw ├── vhdl │ └── .gitignore ├── gen │ └── .gitignore ├── verilog │ └── .gitignore └── spinal │ └── projectname │ ├── Config.scala │ ├── MyTopLevel.scala │ ├── MyTopLevelFormal.scala │ └── MyTopLevelSim.scala ├── .mill-version ├── project ├── build.properties └── plugins.sbt ├── .scalafmt.conf ├── .gitignore └── README.md /hw/vhdl/.gitignore: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /hw/gen/.gitignore: -------------------------------------------------------------------------------- 1 | * 2 | -------------------------------------------------------------------------------- /hw/verilog/.gitignore: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /.mill-version: -------------------------------------------------------------------------------- 1 | 0.11.11 2 | -------------------------------------------------------------------------------- /project/build.properties: -------------------------------------------------------------------------------- 1 | sbt.version=1.10.2 2 | -------------------------------------------------------------------------------- /project/plugins.sbt: -------------------------------------------------------------------------------- 1 | addSbtPlugin("org.scalameta" % "sbt-scalafmt" % "2.4.6") 2 | -------------------------------------------------------------------------------- /.scalafmt.conf: -------------------------------------------------------------------------------- 1 | version = 3.6.0 2 | runner.dialect = scala212 3 | align.preset = some 4 | maxColumn = 120 5 | docstrings.wrap = no 6 | -------------------------------------------------------------------------------- /hw/spinal/projectname/Config.scala: -------------------------------------------------------------------------------- 1 | package projectname 2 | 3 | import spinal.core._ 4 | import spinal.core.sim._ 5 | 6 | object Config { 7 | def spinal = SpinalConfig( 8 | targetDirectory = "hw/gen", 9 | defaultConfigForClockDomains = ClockDomainConfig( 10 | resetActiveLevel = HIGH 11 | ), 12 | onlyStdLogicVectorAtTopLevelIo = false 13 | ) 14 | 15 | def sim = SimConfig.withConfig(spinal).withFstWave 16 | } 17 | -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | *.class 2 | *.log 3 | *.bak 4 | 5 | # sbt specific 6 | .cache/ 7 | .history/ 8 | .lib/ 9 | dist/* 10 | target 11 | lib_managed/ 12 | src_managed/ 13 | project/boot/ 14 | project/project 15 | project/plugins/project/ 16 | 17 | # Scala-IDE specific 18 | .scala_dependencies 19 | .worksheet 20 | .bloop 21 | 22 | .idea 23 | out 24 | 25 | # Metals 26 | .metals 27 | project/metals.sbt 28 | 29 | # Eclipse 30 | bin/ 31 | .classpath 32 | .project 33 | .settings 34 | .cache-main 35 | 36 | #User 37 | /*.vhd 38 | /*.v 39 | *.cf 40 | *.json 41 | *.vcd 42 | !tester/src/test/resources/*.vhd 43 | 44 | 45 | simWorkspace/ 46 | tmp/ 47 | null 48 | -------------------------------------------------------------------------------- /hw/spinal/projectname/MyTopLevel.scala: -------------------------------------------------------------------------------- 1 | package projectname 2 | 3 | import spinal.core._ 4 | 5 | // Hardware definition 6 | case class MyTopLevel() extends Component { 7 | val io = new Bundle { 8 | val cond0 = in Bool() 9 | val cond1 = in Bool() 10 | val flag = out Bool() 11 | val state = out UInt(8 bits) 12 | } 13 | 14 | val counter = Reg(UInt(8 bits)) init 0 15 | 16 | when(io.cond0) { 17 | counter := counter + 1 18 | } 19 | 20 | io.state := counter 21 | io.flag := (counter === 0) | io.cond1 22 | } 23 | 24 | object MyTopLevelVerilog extends App { 25 | Config.spinal.generateVerilog(MyTopLevel()) 26 | } 27 | 28 | object MyTopLevelVhdl extends App { 29 | Config.spinal.generateVhdl(MyTopLevel()) 30 | } 31 | -------------------------------------------------------------------------------- /hw/spinal/projectname/MyTopLevelFormal.scala: -------------------------------------------------------------------------------- 1 | package projectname 2 | 3 | import spinal.core._ 4 | import spinal.core.formal._ 5 | 6 | // You need SymbiYosys to be installed. 7 | // See https://spinalhdl.github.io/SpinalDoc-RTD/master/SpinalHDL/Formal%20verification/index.html#installing-requirements 8 | object MyTopLevelFormal extends App { 9 | FormalConfig 10 | .withBMC(10) 11 | .doVerify(new Component { 12 | val dut = FormalDut(MyTopLevel()) 13 | 14 | // Ensure the formal test start with a reset 15 | assumeInitial(clockDomain.isResetActive) 16 | 17 | // Provide some stimulus 18 | anyseq(dut.io.cond0) 19 | anyseq(dut.io.cond1) 20 | 21 | // Check the state initial value and increment 22 | assert(dut.io.state === past(dut.io.state + U(dut.io.cond0)).init(0)) 23 | }) 24 | } 25 | -------------------------------------------------------------------------------- /hw/spinal/projectname/MyTopLevelSim.scala: -------------------------------------------------------------------------------- 1 | package projectname 2 | 3 | import spinal.core._ 4 | import spinal.core.sim._ 5 | 6 | object MyTopLevelSim extends App { 7 | Config.sim.compile(MyTopLevel()).doSim { dut => 8 | // Fork a process to generate the reset and the clock on the dut 9 | dut.clockDomain.forkStimulus(period = 10) 10 | 11 | var modelState = 0 12 | for (idx <- 0 to 99) { 13 | // Drive the dut inputs with random values 14 | dut.io.cond0.randomize() 15 | dut.io.cond1.randomize() 16 | 17 | // Wait a rising edge on the clock 18 | dut.clockDomain.waitRisingEdge() 19 | 20 | // Check that the dut values match with the reference model ones 21 | val modelFlag = modelState == 0 || dut.io.cond1.toBoolean 22 | assert(dut.io.state.toInt == modelState) 23 | assert(dut.io.flag.toBoolean == modelFlag) 24 | 25 | // Update the reference model value 26 | if (dut.io.cond0.toBoolean) { 27 | modelState = (modelState + 1) & 0xff 28 | } 29 | } 30 | } 31 | } 32 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # SpinalHDL Base Project 2 | 3 | This repository is a base project to help Spinal users set-up project without knowledge about Scala and SBT. 4 | 5 | 6 | ## If it is your are learning SpinalHDL 7 | 8 | You can follow the tutorial on the [Getting Started](https://spinalhdl.github.io/SpinalDoc-RTD/master/SpinalHDL/Getting%20Started/index.html) page. 9 | 10 | More specifically: 11 | 12 | * instructions to install tools can be found on the [Install and setup](https://spinalhdl.github.io/SpinalDoc-RTD/master/SpinalHDL/Getting%20Started/Install%20and%20setup.html#install-and-setup) page 13 | * instructions to get this repository locally are available in the [Create a SpinalHDL project](https://spinalhdl.github.io/SpinalDoc-RTD/master/SpinalHDL/Getting%20Started/Install%20and%20setup.html#create-a-spinalhdl-project) section. 14 | 15 | 16 | ### TL;DR Things have already been set up in my environment, how do I run things to try SpinalHDL? 17 | 18 | Once in the `SpinalTemplateSbt` directory, when tools are installed, the commands below can be run to use `sbt`. 19 | 20 | ```sh 21 | // To generate the Verilog from the example 22 | sbt "runMain projectname.MyTopLevelVerilog" 23 | 24 | // To generate the VHDL from the example 25 | sbt "runMain projectname.MyTopLevelVhdl" 26 | 27 | // To run the testbench 28 | sbt "runMain projectname.MyTopLevelSim" 29 | ``` 30 | 31 | * The example hardware description is into `hw/spinal/projectname/MyTopLevel.scala` 32 | * The testbench is into `hw/spinal/projectname/MyTopLevelSim.scala` 33 | 34 | When you really start working with SpinalHDL, it is recommended (both for comfort and efficiency) to use an IDE, see the [Getting started](https://spinalhdl.github.io/SpinalDoc-RTD/master/SpinalHDL/Getting%20Started/index.html). 35 | 36 | 37 | ## If you want to create a new project from this template 38 | 39 | ### Change project name 40 | 41 | You might want to change the project name, which is currently `projectname`. To do so (let's say your actual project name is `myproject`; it must be all lowercase with no separators): 42 | 43 | * Update `build.sbt` and/or `build.sc` by replacing `projectname` by the name of your project `myproject` (1 occurrence in each file). The better is to replace in both (it will always work), but in some contexts you can keep only one of these two files: 44 | * If you are sure all people only use `sbt`, you can replace only in `build.sbt` and remove `build.sc` 45 | * If you are sure all people only use `mill`, you can replace only in `build.sc` and remove `build.sbt` 46 | * Replace in both files for open-source project. 47 | * Put all your scala files into `hw/spinal/myproject/` (remove the unused `hw/spinal/projectname/` folder) 48 | * Start all your scala files with `package myproject` 49 | 50 | 51 | ### Change project structure 52 | 53 | You can change the project structure as you want. The only restrictions (from Scala environment) are (let's say your actual project name is `myproject`): 54 | 55 | * you must have a `myproject` folder and files in it must start with `package myproject` 56 | * if you have a file in a subfolder `myproject/somepackage/MyElement.scala` it must start with `package myproject.somepackage`. 57 | * `sbt` and `mill` must be run right in the folder containing their configurations (recommended to not move these files) 58 | 59 | Once the project structure is modified, update configurations: 60 | 61 | * In `build.sbt` and/or `build.sc` (see above) replace `/ "hw" / "spinal"` by the new path to the folder containing the `myproject` folder. 62 | * In the spinal configuration file (if you kept it, by default it is in `projectname/Config.scala`) change the path in `targetDirectory = "hw/gen"` to the directory where you want generated files to be written. If you don't use a config or if it doesn't contain this element, generated files will be written in the root directory. 63 | 64 | 65 | ### Update this README 66 | 67 | Of course you can replace/modify this file to help people with your own project! 68 | 69 | 70 | ## Mill Support (Experimental) 71 | 72 | The [Mill build tool](https://com-lihaoyi.github.io/mill) can be installed and used instead of `sbt`. 73 | 74 | ```sh 75 | // To generate the Verilog from the example 76 | mill projectname.runMain projectname.MyTopLevelVerilog 77 | 78 | // To generate the VHDL from the example 79 | mill projectname.runMain projectname.MyTopLevelVhdl 80 | 81 | // To run the testbench 82 | mill projectname.runMain projectname.MyTopLevelSim 83 | ``` 84 | --------------------------------------------------------------------------------