├── .github └── workflows │ └── scala.yml ├── .gitignore ├── .gitmodules ├── .travis.yml ├── LICENSE ├── README.md ├── assets ├── brieySoc.png └── fpuDesign.png ├── build.sbt ├── build.sc ├── doc ├── diagram.drawio ├── gcdPeripheral │ ├── README.md │ ├── img │ │ ├── murax-gcd-diagrams-gcd-controlpath.png │ │ ├── murax-gcd-diagrams-gcd-datapath.png │ │ ├── murax-gcd-diagrams-gcd-dp+cp.png │ │ ├── murax-gcd-diagrams-gcd.png │ │ ├── murax-gcd-diagrams.drawio │ │ └── simulationWave.PNG │ └── src │ │ └── main │ │ ├── c │ │ └── murax │ │ │ └── gcd_world │ │ │ ├── makefile │ │ │ ├── project │ │ │ └── build.properties │ │ │ └── src │ │ │ ├── crt.S │ │ │ ├── gcd.h │ │ │ ├── gpio.h │ │ │ ├── interrupt.h │ │ │ ├── linker.ld │ │ │ ├── main.c │ │ │ ├── main.h │ │ │ ├── murax.h │ │ │ ├── prescaler.h │ │ │ ├── timer.h │ │ │ └── uart.h │ │ └── scala │ │ └── vexriscv │ │ ├── demo │ │ └── Murax.scala │ │ └── periph │ │ └── gcd │ │ ├── Apb3GCDCtrl.scala │ │ ├── GCDCtrl.scala │ │ ├── GCDData.scala │ │ ├── GCDTop.scala │ │ └── GCDTopSim.scala ├── nativeJtag │ ├── README.md │ ├── soc_init.cfg │ └── usb_connect.cfg ├── smp │ └── smp.md └── vjtag │ └── README.md ├── project ├── build.properties └── plugins.sbt ├── scripts ├── Murax │ ├── arty_a7 │ │ ├── README.md │ │ ├── arty_a7.xdc │ │ ├── arty_a7_org.xdc │ │ ├── make_bit_file.tcl │ │ ├── make_mcs_file │ │ ├── make_mcs_file.tcl │ │ ├── make_mmi_files │ │ ├── make_mmi_files.tcl │ │ ├── make_vivado_project │ │ ├── make_vivado_project.tcl │ │ ├── makefile │ │ ├── open_vivado_project │ │ ├── open_vivado_project.tcl │ │ ├── picocom_arty │ │ ├── soc_mmi.tcl │ │ ├── toplevel.v │ │ ├── vivado_params.tcl │ │ ├── write_flash │ │ ├── write_flash.tcl │ │ ├── write_fpga │ │ └── write_fpga.tcl │ ├── iCE40-hx8k_breakout_board │ │ ├── Makefile │ │ ├── README.md │ │ ├── img │ │ │ ├── cram-programming-config.png │ │ │ └── iCE40HX8K-breakout-revA.png │ │ ├── toplevel.pcf │ │ └── toplevel.v │ ├── iCE40-hx8k_breakout_board_xip │ │ ├── Makefile │ │ ├── Murax_iCE40_hx8k_breakout_board_xip.pcf │ │ ├── README.md │ │ └── img │ │ │ ├── cram-programming-config.png │ │ │ └── iCE40HX8K-breakout-revA.png │ └── iCE40HX8K-EVB │ │ ├── Makefile │ │ ├── toplevel.pcf │ │ ├── toplevel.v │ │ └── toplevel_pll.v └── regression │ ├── .gitignore │ ├── makefile │ ├── regression.mk │ └── verilator.mk ├── src ├── main │ ├── c │ │ ├── common │ │ │ ├── ram.ld │ │ │ ├── riscv64-unknown-elf.mk │ │ │ └── standalone.mk │ │ ├── emulator │ │ │ ├── .gitignore │ │ │ ├── build │ │ │ │ ├── emulator.asm │ │ │ │ ├── emulator.bin │ │ │ │ └── emulator.hex │ │ │ ├── makefile │ │ │ └── src │ │ │ │ ├── config.h │ │ │ │ ├── hal.c │ │ │ │ ├── hal.h │ │ │ │ ├── main.c │ │ │ │ ├── riscv.h │ │ │ │ ├── start.S │ │ │ │ ├── trap.S │ │ │ │ └── utils.S │ │ └── murax │ │ │ ├── hello_world │ │ │ ├── makefile │ │ │ └── src │ │ │ │ ├── crt.S │ │ │ │ ├── gpio.h │ │ │ │ ├── interrupt.h │ │ │ │ ├── linker.ld │ │ │ │ ├── main.c │ │ │ │ ├── murax.h │ │ │ │ ├── prescaler.h │ │ │ │ ├── timer.h │ │ │ │ └── uart.h │ │ │ └── xipBootloader │ │ │ ├── .gitignore │ │ │ ├── crt.S │ │ │ ├── crt.bin │ │ │ ├── demo.S │ │ │ ├── makefile │ │ │ ├── mapping.ld │ │ │ ├── mapping_rom.ld │ │ │ └── mapping_xip.ld │ ├── ressource │ │ └── hex │ │ │ ├── muraxDemo.elf │ │ │ └── muraxDemo.hex │ └── scala │ │ ├── spinal │ │ └── lib │ │ │ └── eda │ │ │ └── icestorm │ │ │ └── IcestormFlow.scala │ │ └── vexriscv │ │ ├── Pipeline.scala │ │ ├── Riscv.scala │ │ ├── Services.scala │ │ ├── Stage.scala │ │ ├── TestsWorkspace.scala │ │ ├── VexRiscv.scala │ │ ├── VexRiscvBmbGenerator.scala │ │ ├── demo │ │ ├── Briey.scala │ │ ├── CustomCsrDemoPlugin.scala │ │ ├── CustomInstruction.scala │ │ ├── FormalSimple.scala │ │ ├── GenCustomCsr.scala │ │ ├── GenCustomInterrupt.scala │ │ ├── GenCustomSimdAdd.scala │ │ ├── GenDeterministicVex.scala │ │ ├── GenFull.scala │ │ ├── GenFullNoMmu.scala │ │ ├── GenFullNoMmuMaxPerf.scala │ │ ├── GenFullNoMmuNoCache.scala │ │ ├── GenFullNoMmuNoCacheSimpleMul.scala │ │ ├── GenFullWithOfficialRiscvDebug.scala │ │ ├── GenFullWithTcm.scala │ │ ├── GenFullWithTcmIntegrated.scala │ │ ├── GenMicroNoCsr.scala │ │ ├── GenNoCacheNoMmuMaxPerf.scala │ │ ├── GenSecure.scala │ │ ├── GenSmallAndProductive.scala │ │ ├── GenSmallAndProductiveCfu.scala │ │ ├── GenSmallAndProductiveICache.scala │ │ ├── GenSmallAndProductiveVfu.scala │ │ ├── GenSmallest.scala │ │ ├── GenSmallestNoCsr.scala │ │ ├── GenTwoThreeStage.scala │ │ ├── Linux.scala │ │ ├── Murax.scala │ │ ├── MuraxUtiles.scala │ │ ├── OpenRoad.scala │ │ ├── SynthesisBench.scala │ │ ├── VexRiscvAhbLite3.scala │ │ ├── VexRiscvAvalonForSim.scala │ │ ├── VexRiscvAvalonWithIntegratedJtag.scala │ │ ├── VexRiscvAxi4LinuxPlicClint.scala │ │ ├── VexRiscvAxi4WithIntegratedJtag.scala │ │ ├── VexRiscvCachedWishboneForSim.scala │ │ ├── WhiteboxPlugin.scala │ │ └── smp │ │ │ ├── Misc.scala │ │ │ ├── VexRiscvSmpCluster.scala │ │ │ ├── VexRiscvSmpLitexCluster.scala │ │ │ └── VexRiscvSmpLitexMpCluster.scala │ │ ├── ip │ │ ├── DataCache.scala │ │ ├── InstructionCache.scala │ │ └── fpu │ │ │ ├── FpuCore.scala │ │ │ ├── FpuDiv.scala │ │ │ ├── FpuSqrt.scala │ │ │ └── Interface.scala │ │ ├── plugin │ │ ├── AesPlugin.scala │ │ ├── BranchPlugin.scala │ │ ├── CfuPlugin.scala │ │ ├── CsrPlugin.scala │ │ ├── DBusCachedPlugin.scala │ │ ├── DBusSimplePlugin.scala │ │ ├── DebugPlugin.scala │ │ ├── DecoderSimplePlugin.scala │ │ ├── DivPlugin.scala │ │ ├── DummyFencePlugin.scala │ │ ├── EmbeddedRiscvJtag.scala │ │ ├── ExternalInterruptArrayPlugin.scala │ │ ├── Fetcher.scala │ │ ├── FormalPlugin.scala │ │ ├── FpuPlugin.scala │ │ ├── HaltOnExceptionPlugin.scala │ │ ├── HazardPessimisticPlugin.scala │ │ ├── HazardSimplePlugin.scala │ │ ├── IBusCachedPlugin.scala │ │ ├── IBusSimplePlugin.scala │ │ ├── IntAluPlugin.scala │ │ ├── MemoryTranslatorPlugin.scala │ │ ├── Misc.scala │ │ ├── MmuPlugin.scala │ │ ├── Mul16Plugin.scala │ │ ├── MulDivIterativePlugin.scala │ │ ├── MulPlugin.scala │ │ ├── MulSimplePlugin.scala │ │ ├── NoPipeliningPlugin.scala │ │ ├── PcManagerSimplePlugin.scala │ │ ├── Plugin.scala │ │ ├── PmpPlugin.scala │ │ ├── PmpPluginNapot.scala │ │ ├── RegFilePlugin.scala │ │ ├── ShiftPlugins.scala │ │ ├── SingleInstructionLimiterPlugin.scala │ │ ├── SrcPlugin.scala │ │ ├── StaticMemoryTranslatorPlugin.scala │ │ ├── VfuPlugin.scala │ │ └── YamlPlugin.scala │ │ └── test │ │ └── Swing.scala └── test │ ├── cpp │ ├── briey │ │ ├── .cproject │ │ ├── installs.txt │ │ ├── jtag.gtkw │ │ ├── main.cpp │ │ ├── makefile │ │ ├── sdram.gtkw │ │ └── wip.gtkw │ ├── common │ │ ├── framework.h │ │ ├── jtag.h │ │ └── uart.h │ ├── custom │ │ ├── atomic │ │ │ ├── build │ │ │ │ ├── atomic.asm │ │ │ │ ├── atomic.elf │ │ │ │ ├── atomic.hex │ │ │ │ ├── atomic.map │ │ │ │ └── atomic.v │ │ │ ├── makefile │ │ │ └── src │ │ │ │ ├── crt.S │ │ │ │ └── ld │ │ ├── custom_csr │ │ │ ├── build │ │ │ │ ├── custom_csr.asm │ │ │ │ ├── custom_csr.elf │ │ │ │ ├── custom_csr.hex │ │ │ │ ├── custom_csr.map │ │ │ │ └── custom_csr.v │ │ │ ├── makefile │ │ │ └── src │ │ │ │ ├── crt.S │ │ │ │ └── ld │ │ └── simd_add │ │ │ ├── build │ │ │ ├── custom_simd_add.asm │ │ │ ├── custom_simd_add.elf │ │ │ ├── custom_simd_add.hex │ │ │ ├── custom_simd_add.map │ │ │ └── custom_simd_add.v │ │ │ ├── makefile │ │ │ └── src │ │ │ ├── crt.S │ │ │ └── ld │ ├── fpu │ │ └── math │ │ │ ├── .gitignore │ │ │ ├── fpu_math.c │ │ │ └── libcode.version │ ├── murax │ │ ├── main.cpp │ │ ├── makefile │ │ └── murax.gtkw │ ├── raw │ │ ├── amo │ │ │ ├── .gitignore │ │ │ ├── build │ │ │ │ ├── amo.asm │ │ │ │ └── amo.hex │ │ │ ├── makefile │ │ │ └── src │ │ │ │ ├── crt.S │ │ │ │ └── ld │ │ ├── common │ │ │ └── asm.mk │ │ ├── dcache │ │ │ ├── .gitignore │ │ │ ├── build │ │ │ │ ├── dcache.asm │ │ │ │ └── dcache.hex │ │ │ ├── makefile │ │ │ └── src │ │ │ │ ├── crt.S │ │ │ │ └── ld │ │ ├── deleg │ │ │ ├── .gitignore │ │ │ ├── build │ │ │ │ ├── deleg.asm │ │ │ │ └── deleg.hex │ │ │ ├── makefile │ │ │ └── src │ │ │ │ ├── crt.S │ │ │ │ ├── encoding.h │ │ │ │ └── ld │ │ ├── fpu │ │ │ ├── .gitignore │ │ │ ├── build │ │ │ │ ├── amo.asm │ │ │ │ ├── amo.hex │ │ │ │ ├── fpu.asm │ │ │ │ └── fpu.hex │ │ │ ├── makefile │ │ │ └── src │ │ │ │ ├── crt.S │ │ │ │ └── ld │ │ ├── icache │ │ │ ├── .gitignore │ │ │ ├── build │ │ │ │ ├── icache.asm │ │ │ │ └── icache.hex │ │ │ ├── makefile │ │ │ └── src │ │ │ │ ├── crt.S │ │ │ │ └── ld │ │ ├── lrsc │ │ │ ├── .gitignore │ │ │ ├── build │ │ │ │ ├── lrsc.asm │ │ │ │ └── lrsc.hex │ │ │ ├── makefile │ │ │ └── src │ │ │ │ ├── crt.S │ │ │ │ └── ld │ │ ├── machineCsr │ │ │ ├── .gitignore │ │ │ ├── build │ │ │ │ ├── machineCsr.asm │ │ │ │ ├── machineCsr.hex │ │ │ │ ├── machineCsrCompressed.asm │ │ │ │ └── machineCsrCompressed.hex │ │ │ ├── makefile │ │ │ └── src │ │ │ │ ├── crt.S │ │ │ │ └── ld │ │ ├── mmu │ │ │ ├── .gitignore │ │ │ ├── build │ │ │ │ ├── mmu.asm │ │ │ │ └── mmu.hex │ │ │ ├── makefile │ │ │ └── src │ │ │ │ ├── crt.S │ │ │ │ └── ld │ │ ├── pmp │ │ │ ├── build │ │ │ │ ├── pmp.asm │ │ │ │ ├── pmp.elf │ │ │ │ ├── pmp.hex │ │ │ │ └── pmp.map │ │ │ ├── makefile │ │ │ └── src │ │ │ │ ├── crt.S │ │ │ │ └── ld │ │ ├── privSpec │ │ │ ├── .gitignore │ │ │ ├── build │ │ │ │ └── privSpec.hex │ │ │ ├── makefile │ │ │ └── src │ │ │ │ ├── crt.S │ │ │ │ ├── ld │ │ │ │ ├── privileged.h │ │ │ │ └── riscv_asm.h │ │ └── smp │ │ │ ├── .gitignore │ │ │ ├── build │ │ │ ├── smp.asm │ │ │ └── smp.bin │ │ │ ├── makefile │ │ │ └── src │ │ │ ├── crt.S │ │ │ └── ld │ └── regression │ │ ├── .gitignore │ │ ├── atomic.gtkw │ │ ├── branch.gtkw │ │ ├── dcache.gtkw │ │ ├── debug.gtkw │ │ ├── default.gtkw │ │ ├── dhrystoneO3.logRef │ │ ├── dhrystoneO3C.logRef │ │ ├── dhrystoneO3M.logRef │ │ ├── dhrystoneO3MC.logRef │ │ ├── encoding.h │ │ ├── fail.gtkw │ │ ├── icache.gtkw │ │ ├── jtag.h │ │ ├── main.cpp │ │ ├── makefile │ │ ├── prediction.gtkw │ │ ├── refDiff.gtkw │ │ ├── wrongDiff.gtkw │ │ └── yolo.gtkw │ ├── java │ └── vexriscv │ │ └── ip │ │ └── fpu │ │ └── FpuMath.java │ ├── python │ ├── gcloud │ │ ├── .gitignore │ │ ├── gcloud.py │ │ ├── makefile │ │ ├── remotePull.py │ │ ├── remoteTest.py │ │ ├── run.sh │ │ ├── stopScript.sh │ │ └── try.py │ └── tool │ │ ├── .gitignore │ │ └── hexToAsm.py │ ├── resources │ ├── .gitignore │ ├── asm │ │ ├── C.ADD.elf.objdump │ │ ├── C.ADDI.elf.objdump │ │ ├── C.ADDI16SP.elf.objdump │ │ ├── C.ADDI4SPN.elf.objdump │ │ ├── C.AND.elf.objdump │ │ ├── C.ANDI.elf.objdump │ │ ├── C.BEQZ.elf.objdump │ │ ├── C.BNEZ.elf.objdump │ │ ├── C.J.elf.objdump │ │ ├── C.JAL.elf.objdump │ │ ├── C.JALR.elf.objdump │ │ ├── C.JR.elf.objdump │ │ ├── C.LI.elf.objdump │ │ ├── C.LUI.elf.objdump │ │ ├── C.LW.elf.objdump │ │ ├── C.LWSP.elf.objdump │ │ ├── C.MV.elf.objdump │ │ ├── C.OR.elf.objdump │ │ ├── C.SLLI.elf.objdump │ │ ├── C.SRAI.elf.objdump │ │ ├── C.SRLI.elf.objdump │ │ ├── C.SUB.elf.objdump │ │ ├── C.SW.elf.objdump │ │ ├── C.SWSP.elf.objdump │ │ ├── C.XOR.elf.objdump │ │ ├── DIV.elf.objdump │ │ ├── DIVU.elf.objdump │ │ ├── DIVW.elf.objdump │ │ ├── I-ADD-01.elf.objdump │ │ ├── I-ADDI-01.elf.objdump │ │ ├── I-AND-01.elf.objdump │ │ ├── I-ANDI-01.elf.objdump │ │ ├── I-AUIPC-01.elf.objdump │ │ ├── I-BEQ-01.elf.objdump │ │ ├── I-BGE-01.elf.objdump │ │ ├── I-BGEU-01.elf.objdump │ │ ├── I-BLT-01.elf.objdump │ │ ├── I-BLTU-01.elf.objdump │ │ ├── I-BNE-01.elf.objdump │ │ ├── I-CSRRC-01.elf.objdump │ │ ├── I-CSRRCI-01.elf.objdump │ │ ├── I-CSRRS-01.elf.objdump │ │ ├── I-CSRRSI-01.elf.objdump │ │ ├── I-CSRRW-01.elf.objdump │ │ ├── I-CSRRWI-01.elf.objdump │ │ ├── I-DELAY_SLOTS-01.elf.objdump │ │ ├── I-EBREAK-01.elf.objdump │ │ ├── I-ECALL-01.elf.objdump │ │ ├── I-ENDIANESS-01.elf.objdump │ │ ├── I-FENCE.I-01.elf.objdump │ │ ├── I-IO.elf.objdump │ │ ├── I-JAL-01.elf.objdump │ │ ├── I-JALR-01.elf.objdump │ │ ├── I-LB-01.elf.objdump │ │ ├── I-LBU-01.elf.objdump │ │ ├── I-LH-01.elf.objdump │ │ ├── I-LHU-01.elf.objdump │ │ ├── I-LUI-01.elf.objdump │ │ ├── I-LW-01.elf.objdump │ │ ├── I-MISALIGN_JMP-01.elf.objdump │ │ ├── I-MISALIGN_LDST-01.elf.objdump │ │ ├── I-NOP-01.elf.objdump │ │ ├── I-OR-01.elf.objdump │ │ ├── I-ORI-01.elf.objdump │ │ ├── I-RF_size-01.elf.objdump │ │ ├── I-RF_width-01.elf.objdump │ │ ├── I-RF_x0-01.elf.objdump │ │ ├── I-SB-01.elf.objdump │ │ ├── I-SH-01.elf.objdump │ │ ├── I-SLL-01.elf.objdump │ │ ├── I-SLLI-01.elf.objdump │ │ ├── I-SLT-01.elf.objdump │ │ ├── I-SLTI-01.elf.objdump │ │ ├── I-SLTIU-01.elf.objdump │ │ ├── I-SLTU-01.elf.objdump │ │ ├── I-SRA-01.elf.objdump │ │ ├── I-SRAI-01.elf.objdump │ │ ├── I-SRL-01.elf.objdump │ │ ├── I-SRLI-01.elf.objdump │ │ ├── I-SUB-01.elf.objdump │ │ ├── I-SW-01.elf.objdump │ │ ├── I-XOR-01.elf.objdump │ │ ├── I-XORI-01.elf.objdump │ │ ├── MUL.elf.objdump │ │ ├── MULH.elf.objdump │ │ ├── MULHSU.elf.objdump │ │ ├── MULHU.elf.objdump │ │ ├── MULW.elf.objdump │ │ ├── REM.elf.objdump │ │ ├── REMU.elf.objdump │ │ ├── REMUW.elf.objdump │ │ ├── REMW.elf.objdump │ │ ├── dhrystoneO3.asm │ │ ├── dhrystoneO3C.asm │ │ ├── dhrystoneO3MC.asm │ │ ├── machineCsr.asm │ │ ├── machineCsrCompressed.asm │ │ ├── mmu.asm │ │ ├── rv32uc-p-rvc.dump │ │ ├── rv32ud-p-fadd.dump │ │ ├── rv32ud-p-fclass.dump │ │ ├── rv32ud-p-fcmp.dump │ │ ├── rv32ud-p-fcvt.dump │ │ ├── rv32ud-p-fcvt_w.dump │ │ ├── rv32ud-p-fdiv.dump │ │ ├── rv32ud-p-fmadd.dump │ │ ├── rv32ud-p-fmin.dump │ │ ├── rv32ud-p-ldst.dump │ │ ├── rv32ud-p-recoding.dump │ │ ├── rv32uf-p-fadd.dump │ │ ├── rv32uf-p-fclass.dump │ │ ├── rv32uf-p-fcmp.dump │ │ ├── rv32uf-p-fcvt.dump │ │ ├── rv32uf-p-fcvt_w.dump │ │ ├── rv32uf-p-fdiv.dump │ │ ├── rv32uf-p-fmadd.dump │ │ ├── rv32uf-p-fmin.dump │ │ ├── rv32uf-p-ldst.dump │ │ ├── rv32uf-p-move.dump │ │ ├── rv32uf-p-recoding.dump │ │ ├── rv32ui-p-add.dump │ │ ├── rv32ui-p-addi.dump │ │ ├── rv32ui-p-and.dump │ │ ├── rv32ui-p-andi.dump │ │ ├── rv32ui-p-auipc.dump │ │ ├── rv32ui-p-beq.dump │ │ ├── rv32ui-p-bge.dump │ │ ├── rv32ui-p-bgeu.dump │ │ ├── rv32ui-p-blt.dump │ │ ├── rv32ui-p-bltu.dump │ │ ├── rv32ui-p-bne.dump │ │ ├── rv32ui-p-fence_i.dump │ │ ├── rv32ui-p-jal.dump │ │ ├── rv32ui-p-jalr.dump │ │ ├── rv32ui-p-lb.dump │ │ ├── rv32ui-p-lbu.dump │ │ ├── rv32ui-p-lh.dump │ │ ├── rv32ui-p-lhu.dump │ │ ├── rv32ui-p-lui.dump │ │ ├── rv32ui-p-lw.dump │ │ ├── rv32ui-p-or.dump │ │ ├── rv32ui-p-ori.dump │ │ ├── rv32ui-p-sb.dump │ │ ├── rv32ui-p-sh.dump │ │ ├── rv32ui-p-simple.dump │ │ ├── rv32ui-p-sll.dump │ │ ├── rv32ui-p-slli.dump │ │ ├── rv32ui-p-slt.dump │ │ ├── rv32ui-p-slti.dump │ │ ├── rv32ui-p-sltiu.dump │ │ ├── rv32ui-p-sltu.dump │ │ ├── rv32ui-p-sra.dump │ │ ├── rv32ui-p-srai.dump │ │ ├── rv32ui-p-srl.dump │ │ ├── rv32ui-p-srli.dump │ │ ├── rv32ui-p-sub.dump │ │ ├── rv32ui-p-sw.dump │ │ ├── rv32ui-p-xor.dump │ │ ├── rv32ui-p-xori.dump │ │ ├── rv32um-p-div.dump │ │ ├── rv32um-p-divu.dump │ │ ├── rv32um-p-mul.dump │ │ ├── rv32um-p-mulh.dump │ │ ├── rv32um-p-mulhsu.dump │ │ ├── rv32um-p-mulhu.dump │ │ ├── rv32um-p-rem.dump │ │ ├── rv32um-p-remu.dump │ │ └── testA.asm │ ├── bin │ │ ├── .gitignore │ │ ├── coremark_rv32i.bin │ │ ├── coremark_rv32ic.bin │ │ ├── coremark_rv32im.bin │ │ └── coremark_rv32imc.bin │ ├── elf │ │ └── uart.elf │ ├── freertos │ │ ├── AltBlckQ_rv32i_O0.hex │ │ ├── AltBlckQ_rv32i_O3.hex │ │ ├── AltBlckQ_rv32ic_O0.hex │ │ ├── AltBlckQ_rv32ic_O3.hex │ │ ├── AltBlckQ_rv32im_O3.hex │ │ ├── AltBlckQ_rv32imac_O3.hex │ │ ├── AltBlock_rv32i_O0.hex │ │ ├── AltBlock_rv32i_O3.hex │ │ ├── AltBlock_rv32ic_O0.hex │ │ ├── AltBlock_rv32ic_O3.hex │ │ ├── AltBlock_rv32im_O3.hex │ │ ├── AltBlock_rv32imac_O3.hex │ │ ├── AltPollQ_rv32i_O0.hex │ │ ├── AltPollQ_rv32i_O3.hex │ │ ├── AltPollQ_rv32ic_O0.hex │ │ ├── AltPollQ_rv32ic_O3.hex │ │ ├── AltPollQ_rv32im_O3.hex │ │ ├── AltPollQ_rv32imac_O3.hex │ │ ├── AltQTest_rv32i_O0.hex │ │ ├── AltQTest_rv32i_O3.hex │ │ ├── AltQTest_rv32ic_O0.hex │ │ ├── AltQTest_rv32ic_O3.hex │ │ ├── AltQTest_rv32im_O3.hex │ │ ├── AltQTest_rv32imac_O3.hex │ │ ├── BlockQ_rv32i_O0.hex │ │ ├── BlockQ_rv32i_O3.hex │ │ ├── BlockQ_rv32ic_O0.hex │ │ ├── BlockQ_rv32ic_O3.hex │ │ ├── BlockQ_rv32im_O3.hex │ │ ├── BlockQ_rv32imac_O3.hex │ │ ├── EventGroupsDemo_rv32i_O0.hex │ │ ├── EventGroupsDemo_rv32i_O3.hex │ │ ├── EventGroupsDemo_rv32ic_O0.hex │ │ ├── EventGroupsDemo_rv32ic_O3.hex │ │ ├── EventGroupsDemo_rv32im_O3.hex │ │ ├── EventGroupsDemo_rv32imac_O3.hex │ │ ├── GenQTest_rv32i_O0.hex │ │ ├── GenQTest_rv32i_O3.hex │ │ ├── GenQTest_rv32ic_O0.hex │ │ ├── GenQTest_rv32ic_O3.hex │ │ ├── GenQTest_rv32im_O3.hex │ │ ├── GenQTest_rv32imac_O3.hex │ │ ├── PollQ_rv32i_O0.hex │ │ ├── PollQ_rv32i_O3.hex │ │ ├── PollQ_rv32ic_O0.hex │ │ ├── PollQ_rv32ic_O3.hex │ │ ├── PollQ_rv32im_O3.hex │ │ ├── PollQ_rv32imac_O3.hex │ │ ├── QPeek_rv32i_O0.hex │ │ ├── QPeek_rv32i_O3.hex │ │ ├── QPeek_rv32ic_O0.hex │ │ ├── QPeek_rv32ic_O3.hex │ │ ├── QPeek_rv32im_O3.hex │ │ ├── QPeek_rv32imac_O3.hex │ │ ├── QueueOverwrite_rv32i_O0.hex │ │ ├── QueueOverwrite_rv32i_O3.hex │ │ ├── QueueOverwrite_rv32ic_O0.hex │ │ ├── QueueOverwrite_rv32ic_O3.hex │ │ ├── QueueOverwrite_rv32im_O3.hex │ │ ├── QueueOverwrite_rv32imac_O3.hex │ │ ├── QueueSetPolling_rv32i_O0.hex │ │ ├── QueueSetPolling_rv32i_O3.hex │ │ ├── QueueSetPolling_rv32ic_O0.hex │ │ ├── QueueSetPolling_rv32ic_O3.hex │ │ ├── QueueSetPolling_rv32im_O3.hex │ │ ├── QueueSetPolling_rv32imac_O3.hex │ │ ├── QueueSet_rv32i_O0.hex │ │ ├── QueueSet_rv32i_O3.hex │ │ ├── QueueSet_rv32ic_O0.hex │ │ ├── QueueSet_rv32ic_O3.hex │ │ ├── QueueSet_rv32im_O3.hex │ │ ├── QueueSet_rv32imac_O3.hex │ │ ├── TaskNotify_rv32i_O0.hex │ │ ├── TaskNotify_rv32i_O3.hex │ │ ├── TaskNotify_rv32ic_O0.hex │ │ ├── TaskNotify_rv32ic_O3.hex │ │ ├── TaskNotify_rv32im_O3.hex │ │ ├── TaskNotify_rv32imac_O3.hex │ │ ├── blocktim_rv32i_O0.hex │ │ ├── blocktim_rv32i_O3.hex │ │ ├── blocktim_rv32ic_O0.hex │ │ ├── blocktim_rv32ic_O3.hex │ │ ├── blocktim_rv32im_O3.hex │ │ ├── blocktim_rv32imac_O3.hex │ │ ├── countsem_rv32i_O0.hex │ │ ├── countsem_rv32i_O3.hex │ │ ├── countsem_rv32ic_O0.hex │ │ ├── countsem_rv32ic_O3.hex │ │ ├── countsem_rv32im_O3.hex │ │ ├── countsem_rv32imac_O3.hex │ │ ├── crhook_rv32i_O0.hex │ │ ├── crhook_rv32i_O3.hex │ │ ├── crhook_rv32ic_O0.hex │ │ ├── crhook_rv32ic_O3.hex │ │ ├── crhook_rv32im_O3.hex │ │ ├── crhook_rv32imac_O3.hex │ │ ├── dead_rv32i_O0.hex │ │ ├── dead_rv32i_O3.hex │ │ ├── dead_rv32ic_O0.hex │ │ ├── dead_rv32ic_O3.hex │ │ ├── dead_rv32im_O3.hex │ │ ├── dead_rv32imac_O3.hex │ │ ├── dynamic_rv32i_O0.hex │ │ ├── dynamic_rv32i_O3.hex │ │ ├── dynamic_rv32ic_O0.hex │ │ ├── dynamic_rv32ic_O3.hex │ │ ├── dynamic_rv32im_O3.hex │ │ ├── dynamic_rv32imac_O3.hex │ │ ├── flop_rv32i_O0.hex │ │ ├── flop_rv32i_O3.hex │ │ ├── flop_rv32ic_O0.hex │ │ ├── flop_rv32ic_O3.hex │ │ ├── flop_rv32im_O3.hex │ │ ├── flop_rv32imac_O3.hex │ │ ├── integer_rv32i_O0.hex │ │ ├── integer_rv32i_O3.hex │ │ ├── integer_rv32ic_O0.hex │ │ ├── integer_rv32ic_O3.hex │ │ ├── integer_rv32im_O3.hex │ │ ├── integer_rv32imac_O3.hex │ │ ├── recmutex_rv32i_O0.hex │ │ ├── recmutex_rv32i_O3.hex │ │ ├── recmutex_rv32ic_O0.hex │ │ ├── recmutex_rv32ic_O3.hex │ │ ├── recmutex_rv32im_O3.hex │ │ ├── recmutex_rv32imac_O3.hex │ │ ├── semtest_rv32i_O0.hex │ │ ├── semtest_rv32i_O3.hex │ │ ├── semtest_rv32ic_O0.hex │ │ ├── semtest_rv32ic_O3.hex │ │ ├── semtest_rv32im_O3.hex │ │ ├── semtest_rv32imac_O3.hex │ │ ├── sp_flop_rv32i_O0.hex │ │ ├── sp_flop_rv32i_O3.hex │ │ ├── sp_flop_rv32ic_O0.hex │ │ ├── sp_flop_rv32ic_O3.hex │ │ ├── sp_flop_rv32im_O3.hex │ │ ├── sp_flop_rv32imac_O3.hex │ │ ├── test1_rv32i_O0.hex │ │ ├── test1_rv32i_O3.hex │ │ ├── test1_rv32ic_O0.hex │ │ ├── test1_rv32ic_O3.hex │ │ ├── test1_rv32im_O3.hex │ │ └── test1_rv32imac_O3.hex │ ├── hex │ │ ├── C.ADD.elf.hex │ │ ├── C.ADDI.elf.hex │ │ ├── C.ADDI16SP.elf.hex │ │ ├── C.ADDI4SPN.elf.hex │ │ ├── C.AND.elf.hex │ │ ├── C.ANDI.elf.hex │ │ ├── C.BEQZ.elf.hex │ │ ├── C.BNEZ.elf.hex │ │ ├── C.J.elf.hex │ │ ├── C.JAL.elf.hex │ │ ├── C.JALR.elf.hex │ │ ├── C.JR.elf.hex │ │ ├── C.LI.elf.hex │ │ ├── C.LUI.elf.hex │ │ ├── C.LW.elf.hex │ │ ├── C.LWSP.elf.hex │ │ ├── C.MV.elf.hex │ │ ├── C.OR.elf.hex │ │ ├── C.SLLI.elf.hex │ │ ├── C.SRAI.elf.hex │ │ ├── C.SRLI.elf.hex │ │ ├── C.SUB.elf.hex │ │ ├── C.SW.elf.hex │ │ ├── C.SWSP.elf.hex │ │ ├── C.XOR.elf.hex │ │ ├── DIV.elf.hex │ │ ├── DIVU.elf.hex │ │ ├── I-ADD-01.elf.hex │ │ ├── I-ADDI-01.elf.hex │ │ ├── I-AND-01.elf.hex │ │ ├── I-ANDI-01.elf.hex │ │ ├── I-AUIPC-01.elf.hex │ │ ├── I-BEQ-01.elf.hex │ │ ├── I-BGE-01.elf.hex │ │ ├── I-BGEU-01.elf.hex │ │ ├── I-BLT-01.elf.hex │ │ ├── I-BLTU-01.elf.hex │ │ ├── I-BNE-01.elf.hex │ │ ├── I-CSRRC-01.elf.hex │ │ ├── I-CSRRCI-01.elf.hex │ │ ├── I-CSRRS-01.elf.hex │ │ ├── I-CSRRSI-01.elf.hex │ │ ├── I-CSRRW-01.elf.hex │ │ ├── I-CSRRWI-01.elf.hex │ │ ├── I-DELAY_SLOTS-01.elf.hex │ │ ├── I-EBREAK-01.elf.hex │ │ ├── I-ECALL-01.elf.hex │ │ ├── I-ENDIANESS-01.elf.hex │ │ ├── I-FENCE.I-01.elf.hex │ │ ├── I-IO.elf.hex │ │ ├── I-JAL-01.elf.hex │ │ ├── I-JALR-01.elf.hex │ │ ├── I-LB-01.elf.hex │ │ ├── I-LBU-01.elf.hex │ │ ├── I-LH-01.elf.hex │ │ ├── I-LHU-01.elf.hex │ │ ├── I-LUI-01.elf.hex │ │ ├── I-LW-01.elf.hex │ │ ├── I-MISALIGN_JMP-01.elf.hex │ │ ├── I-MISALIGN_LDST-01.elf.hex │ │ ├── I-NOP-01.elf.hex │ │ ├── I-OR-01.elf.hex │ │ ├── I-ORI-01.elf.hex │ │ ├── I-RF_size-01.elf.hex │ │ ├── I-RF_width-01.elf.hex │ │ ├── I-RF_x0-01.elf.hex │ │ ├── I-SB-01.elf.hex │ │ ├── I-SH-01.elf.hex │ │ ├── I-SLL-01.elf.hex │ │ ├── I-SLLI-01.elf.hex │ │ ├── I-SLT-01.elf.hex │ │ ├── I-SLTI-01.elf.hex │ │ ├── I-SLTIU-01.elf.hex │ │ ├── I-SLTU-01.elf.hex │ │ ├── I-SRA-01.elf.hex │ │ ├── I-SRAI-01.elf.hex │ │ ├── I-SRL-01.elf.hex │ │ ├── I-SRLI-01.elf.hex │ │ ├── I-SUB-01.elf.hex │ │ ├── I-SW-01.elf.hex │ │ ├── I-XOR-01.elf.hex │ │ ├── I-XORI-01.elf.hex │ │ ├── MUL.elf.hex │ │ ├── MULH.elf.hex │ │ ├── MULHSU.elf.hex │ │ ├── MULHU.elf.hex │ │ ├── REM.elf.hex │ │ ├── REMU.elf.hex │ │ ├── debugPlugin.hex │ │ ├── debugPluginExternal.hex │ │ ├── dhrystoneO3.hex │ │ ├── dhrystoneO3C.hex │ │ ├── dhrystoneO3M.hex │ │ ├── dhrystoneO3MC.hex │ │ ├── freeRTOS_demo.hex │ │ ├── machineCsr.hex │ │ ├── machineCsrCompressed.hex │ │ ├── mmu.hex │ │ ├── rv32uc-p-rvc.hex │ │ ├── rv32ud-p-fadd.hex │ │ ├── rv32ud-p-fclass.hex │ │ ├── rv32ud-p-fcmp.hex │ │ ├── rv32ud-p-fcvt.hex │ │ ├── rv32ud-p-fcvt_w.hex │ │ ├── rv32ud-p-fdiv.hex │ │ ├── rv32ud-p-fmadd.hex │ │ ├── rv32ud-p-fmin.hex │ │ ├── rv32ud-p-ldst.hex │ │ ├── rv32ud-p-recoding.hex │ │ ├── rv32uf-p-fadd.hex │ │ ├── rv32uf-p-fclass.hex │ │ ├── rv32uf-p-fcmp.hex │ │ ├── rv32uf-p-fcvt.hex │ │ ├── rv32uf-p-fcvt_w.hex │ │ ├── rv32uf-p-fdiv.hex │ │ ├── rv32uf-p-fmadd.hex │ │ ├── rv32uf-p-fmin.hex │ │ ├── rv32uf-p-ldst.hex │ │ ├── rv32uf-p-move.hex │ │ ├── rv32uf-p-recoding.hex │ │ ├── rv32ui-p-add.hex │ │ ├── rv32ui-p-addi.hex │ │ ├── rv32ui-p-and.hex │ │ ├── rv32ui-p-andi.hex │ │ ├── rv32ui-p-auipc.hex │ │ ├── rv32ui-p-beq.hex │ │ ├── rv32ui-p-bge.hex │ │ ├── rv32ui-p-bgeu.hex │ │ ├── rv32ui-p-blt.hex │ │ ├── rv32ui-p-bltu.hex │ │ ├── rv32ui-p-bne.hex │ │ ├── rv32ui-p-fence_i.hex │ │ ├── rv32ui-p-jal.hex │ │ ├── rv32ui-p-jalr.hex │ │ ├── rv32ui-p-lb.hex │ │ ├── rv32ui-p-lbu.hex │ │ ├── rv32ui-p-lh.hex │ │ ├── rv32ui-p-lhu.hex │ │ ├── rv32ui-p-lui.hex │ │ ├── rv32ui-p-lui.hex.hex │ │ ├── rv32ui-p-lw.hex │ │ ├── rv32ui-p-or.hex │ │ ├── rv32ui-p-ori.hex │ │ ├── rv32ui-p-sb.hex │ │ ├── rv32ui-p-sh.hex │ │ ├── rv32ui-p-simple.hex │ │ ├── rv32ui-p-sll.hex │ │ ├── rv32ui-p-slli.hex │ │ ├── rv32ui-p-slt.hex │ │ ├── rv32ui-p-slti.hex │ │ ├── rv32ui-p-sltiu.hex │ │ ├── rv32ui-p-sltu.hex │ │ ├── rv32ui-p-sra.hex │ │ ├── rv32ui-p-srai.hex │ │ ├── rv32ui-p-srl.hex │ │ ├── rv32ui-p-srli.hex │ │ ├── rv32ui-p-sub.hex │ │ ├── rv32ui-p-sw.hex │ │ ├── rv32ui-p-xor.hex │ │ ├── rv32ui-p-xori.hex │ │ ├── rv32um-p-div.hex │ │ ├── rv32um-p-divu.hex │ │ ├── rv32um-p-mul.hex │ │ ├── rv32um-p-mulh.hex │ │ ├── rv32um-p-mulhsu.hex │ │ ├── rv32um-p-mulhu.hex │ │ ├── rv32um-p-rem.hex │ │ ├── rv32um-p-remu.hex │ │ └── testA.hex │ └── ref │ │ ├── C.ADD.reference_output │ │ ├── C.ADDI.reference_output │ │ ├── C.ADDI16SP.reference_output │ │ ├── C.ADDI4SPN.reference_output │ │ ├── C.AND.reference_output │ │ ├── C.ANDI.reference_output │ │ ├── C.BEQZ.reference_output │ │ ├── C.BNEZ.reference_output │ │ ├── C.J.reference_output │ │ ├── C.JAL.reference_output │ │ ├── C.JALR.reference_output │ │ ├── C.JR.reference_output │ │ ├── C.LI.reference_output │ │ ├── C.LUI.reference_output │ │ ├── C.LW.reference_output │ │ ├── C.LWSP.reference_output │ │ ├── C.MV.reference_output │ │ ├── C.OR.reference_output │ │ ├── C.SLLI.reference_output │ │ ├── C.SRAI.reference_output │ │ ├── C.SRLI.reference_output │ │ ├── C.SUB.reference_output │ │ ├── C.SW.reference_output │ │ ├── C.SWSP.reference_output │ │ ├── C.XOR.reference_output │ │ ├── DIV.reference_output │ │ ├── DIVU.reference_output │ │ ├── I-ADD-01.reference_output │ │ ├── I-ADDI-01.reference_output │ │ ├── I-AND-01.reference_output │ │ ├── I-ANDI-01.reference_output │ │ ├── I-AUIPC-01.reference_output │ │ ├── I-BEQ-01.reference_output │ │ ├── I-BGE-01.reference_output │ │ ├── I-BGEU-01.reference_output │ │ ├── I-BLT-01.reference_output │ │ ├── I-BLTU-01.reference_output │ │ ├── I-BNE-01.reference_output │ │ ├── I-CSRRC-01.reference_output │ │ ├── I-CSRRCI-01.reference_output │ │ ├── I-CSRRS-01.reference_output │ │ ├── I-CSRRSI-01.reference_output │ │ ├── I-CSRRW-01.reference_output │ │ ├── I-CSRRWI-01.reference_output │ │ ├── I-DELAY_SLOTS-01.reference_output │ │ ├── I-EBREAK-01.reference_output │ │ ├── I-ECALL-01.reference_output │ │ ├── I-ENDIANESS-01.reference_output │ │ ├── I-FENCE.I-01.reference_output │ │ ├── I-IO.reference_output │ │ ├── I-JAL-01.reference_output │ │ ├── I-JALR-01.reference_output │ │ ├── I-LB-01.reference_output │ │ ├── I-LBU-01.reference_output │ │ ├── I-LH-01.reference_output │ │ ├── I-LHU-01.reference_output │ │ ├── I-LUI-01.reference_output │ │ ├── I-LW-01.reference_output │ │ ├── I-MISALIGN_JMP-01.reference_output │ │ ├── I-MISALIGN_LDST-01.reference_output │ │ ├── I-NOP-01.reference_output │ │ ├── I-OR-01.reference_output │ │ ├── I-ORI-01.reference_output │ │ ├── I-RF_size-01.reference_output │ │ ├── I-RF_width-01.reference_output │ │ ├── I-RF_x0-01.reference_output │ │ ├── I-SB-01.reference_output │ │ ├── I-SH-01.reference_output │ │ ├── I-SLL-01.reference_output │ │ ├── I-SLLI-01.reference_output │ │ ├── I-SLT-01.reference_output │ │ ├── I-SLTI-01.reference_output │ │ ├── I-SLTIU-01.reference_output │ │ ├── I-SLTU-01.reference_output │ │ ├── I-SRA-01.reference_output │ │ ├── I-SRAI-01.reference_output │ │ ├── I-SRL-01.reference_output │ │ ├── I-SRLI-01.reference_output │ │ ├── I-SUB-01.reference_output │ │ ├── I-SW-01.reference_output │ │ ├── I-XOR-01.reference_output │ │ ├── I-XORI-01.reference_output │ │ ├── MUL.reference_output │ │ ├── MULH.reference_output │ │ ├── MULHSU.reference_output │ │ ├── MULHU.reference_output │ │ ├── REM.reference_output │ │ └── REMU.reference_output │ └── scala │ └── vexriscv │ ├── DhrystoneBench.scala │ ├── MuraxSim.scala │ ├── TestIndividualFeatures.scala │ ├── experimental │ ├── Experiments.scala │ ├── GenMicro.scala │ ├── PlicCost.scala │ └── config.scala │ └── ip │ └── fpu │ ├── FpuTest.scala │ └── Playground.scala └── tools.sh /.gitignore: -------------------------------------------------------------------------------- 1 | *.class 2 | *.log 3 | *.bak 4 | .*.swp 5 | 6 | # sbt specific 7 | .cache/ 8 | .history/ 9 | .lib/ 10 | dist/* 11 | target 12 | lib_managed/ 13 | src_managed/ 14 | project/boot/ 15 | project/plugins/project/ 16 | 17 | # Scala-IDE specific 18 | .scala_dependencies 19 | .worksheet 20 | 21 | .idea 22 | out 23 | 24 | # Eclipse 25 | bin/ 26 | .classpath 27 | .project 28 | .cproject 29 | .settings 30 | .cache-main 31 | 32 | #User 33 | /*.vhd 34 | /*.v 35 | *.cf 36 | *.json 37 | *.vcd 38 | *.fst* 39 | !tester/src/test/resources/*.vhd 40 | obj_dir 41 | *.logTrace 42 | *.yaml 43 | *.memTrace 44 | *.regTrace 45 | *.debugTrace 46 | *.tcl 47 | *.o 48 | *.bin 49 | explor 50 | 51 | mill 52 | 53 | simWorkspace/ 54 | tmp/ 55 | /archive.tar.gz 56 | *.out32 57 | -------------------------------------------------------------------------------- /.gitmodules: -------------------------------------------------------------------------------- 1 | [submodule "src/test/resources/VexRiscvRegressionData"] 2 | path = src/test/resources/VexRiscvRegressionData 3 | url = https://github.com/SpinalHDL/VexRiscvRegressionData.git 4 | -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | MIT License 2 | 3 | Copyright (c) 2016 Spinal HDL contributors 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in all 13 | copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 | SOFTWARE. -------------------------------------------------------------------------------- /assets/brieySoc.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/SpinalHDL/VexRiscv/79e6a600bd7fdae275bc893fda317bd6a27df762/assets/brieySoc.png -------------------------------------------------------------------------------- /assets/fpuDesign.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/SpinalHDL/VexRiscv/79e6a600bd7fdae275bc893fda317bd6a27df762/assets/fpuDesign.png -------------------------------------------------------------------------------- /build.sbt: -------------------------------------------------------------------------------- 1 | val spinalVersion = "1.12.0" 2 | 3 | lazy val root = (project in file(".")). 4 | settings( 5 | inThisBuild(List( 6 | organization := "com.github.spinalhdl", 7 | scalaVersion := "2.12.18", 8 | version := "2.0.0" 9 | )), 10 | libraryDependencies ++= Seq( 11 | "com.github.spinalhdl" %% "spinalhdl-core" % spinalVersion, 12 | "com.github.spinalhdl" %% "spinalhdl-lib" % spinalVersion, 13 | compilerPlugin("com.github.spinalhdl" %% "spinalhdl-idsl-plugin" % spinalVersion), 14 | "org.scalatest" %% "scalatest" % "3.2.17", 15 | "org.yaml" % "snakeyaml" % "1.8" 16 | ), 17 | name := "VexRiscv" 18 | ) 19 | 20 | fork := true 21 | -------------------------------------------------------------------------------- /build.sc: -------------------------------------------------------------------------------- 1 | import mill._, scalalib._ 2 | 3 | val spinalVersion = "1.12.0" 4 | 5 | object ivys { 6 | val sv = "2.11.12" 7 | val spinalCore = ivy"com.github.spinalhdl::spinalhdl-core:$spinalVersion" 8 | val spinalLib = ivy"com.github.spinalhdl::spinalhdl-lib:$spinalVersion" 9 | val spinalPlugin = ivy"com.github.spinalhdl::spinalhdl-idsl-plugin:$spinalVersion" 10 | val scalatest = ivy"org.scalatest::scalatest:3.2.5" 11 | val macroParadise = ivy"org.scalamacros:::paradise:2.1.1" 12 | val yaml = ivy"org.yaml:snakeyaml:1.8" 13 | } 14 | 15 | trait Common extends ScalaModule { 16 | override def scalaVersion = ivys.sv 17 | override def scalacPluginIvyDeps = Agg(ivys.macroParadise, ivys.spinalPlugin) 18 | override def ivyDeps = Agg(ivys.spinalCore, ivys.spinalLib, ivys.yaml, ivys.scalatest) 19 | override def scalacOptions = Seq("-Xsource:2.11") 20 | } 21 | 22 | object VexRiscv extends Common with SbtModule{ 23 | override def millSourcePath = os.pwd 24 | override def moduleDeps: Seq[JavaModule] = super.moduleDeps 25 | 26 | object test extends SbtModuleTests with TestModule.ScalaTest 27 | } 28 | 29 | -------------------------------------------------------------------------------- /doc/gcdPeripheral/img/murax-gcd-diagrams-gcd-controlpath.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/SpinalHDL/VexRiscv/79e6a600bd7fdae275bc893fda317bd6a27df762/doc/gcdPeripheral/img/murax-gcd-diagrams-gcd-controlpath.png -------------------------------------------------------------------------------- /doc/gcdPeripheral/img/murax-gcd-diagrams-gcd-datapath.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/SpinalHDL/VexRiscv/79e6a600bd7fdae275bc893fda317bd6a27df762/doc/gcdPeripheral/img/murax-gcd-diagrams-gcd-datapath.png -------------------------------------------------------------------------------- /doc/gcdPeripheral/img/murax-gcd-diagrams-gcd-dp+cp.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/SpinalHDL/VexRiscv/79e6a600bd7fdae275bc893fda317bd6a27df762/doc/gcdPeripheral/img/murax-gcd-diagrams-gcd-dp+cp.png -------------------------------------------------------------------------------- /doc/gcdPeripheral/img/murax-gcd-diagrams-gcd.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/SpinalHDL/VexRiscv/79e6a600bd7fdae275bc893fda317bd6a27df762/doc/gcdPeripheral/img/murax-gcd-diagrams-gcd.png -------------------------------------------------------------------------------- /doc/gcdPeripheral/img/simulationWave.PNG: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/SpinalHDL/VexRiscv/79e6a600bd7fdae275bc893fda317bd6a27df762/doc/gcdPeripheral/img/simulationWave.PNG -------------------------------------------------------------------------------- /doc/gcdPeripheral/src/main/c/murax/gcd_world/project/build.properties: -------------------------------------------------------------------------------- 1 | sbt.version=1.4.9 2 | -------------------------------------------------------------------------------- /doc/gcdPeripheral/src/main/c/murax/gcd_world/src/gcd.h: -------------------------------------------------------------------------------- 1 | #ifndef GCD_H_ 2 | #define GCD_H_ 3 | 4 | typedef struct 5 | { 6 | volatile uint32_t A; 7 | volatile uint32_t B; 8 | volatile uint32_t RES; 9 | volatile uint32_t READY; 10 | volatile uint32_t VALID; 11 | } Gcd_Reg; 12 | 13 | #endif /* GCD_H_ */ 14 | -------------------------------------------------------------------------------- /doc/gcdPeripheral/src/main/c/murax/gcd_world/src/gpio.h: -------------------------------------------------------------------------------- 1 | #ifndef GPIO_H_ 2 | #define GPIO_H_ 3 | 4 | 5 | typedef struct 6 | { 7 | volatile uint32_t INPUT; 8 | volatile uint32_t OUTPUT; 9 | volatile uint32_t OUTPUT_ENABLE; 10 | } Gpio_Reg; 11 | 12 | 13 | #endif /* GPIO_H_ */ 14 | 15 | 16 | -------------------------------------------------------------------------------- /doc/gcdPeripheral/src/main/c/murax/gcd_world/src/interrupt.h: -------------------------------------------------------------------------------- 1 | #ifndef INTERRUPTCTRL_H_ 2 | #define INTERRUPTCTRL_H_ 3 | 4 | #include 5 | 6 | typedef struct 7 | { 8 | volatile uint32_t PENDINGS; 9 | volatile uint32_t MASKS; 10 | } InterruptCtrl_Reg; 11 | 12 | static void interruptCtrl_init(InterruptCtrl_Reg* reg){ 13 | reg->MASKS = 0; 14 | reg->PENDINGS = 0xFFFFFFFF; 15 | } 16 | 17 | #endif /* INTERRUPTCTRL_H_ */ 18 | -------------------------------------------------------------------------------- /doc/gcdPeripheral/src/main/c/murax/gcd_world/src/main.c: -------------------------------------------------------------------------------- 1 | //#include "stddefs.h" 2 | #include 3 | 4 | #include "murax.h" 5 | 6 | #include "main.h" 7 | 8 | #define DEBUG 0 9 | 10 | uint32_t gcd(uint32_t a, uint32_t b){ 11 | GCD->A = a; 12 | GCD->B = b; 13 | GCD->VALID = 0x00000001; 14 | uint32_t rdyFlag = 0; 15 | do{ 16 | rdyFlag = GCD->READY; 17 | }while(!rdyFlag); 18 | return GCD->RES; 19 | } 20 | 21 | void calcPrintGCD(uint32_t a, uint32_t b){ 22 | uint32_t myGCD = 0; 23 | char buf[5] = { 0x00 }; 24 | char aBuf[11] = { 0x00 }; 25 | char bBuf[11] = { 0x00 }; 26 | itoa(a, aBuf, 10); 27 | itoa(b, bBuf, 10); 28 | print("gcd(");print(aBuf);print(",");print(bBuf);println("):"); 29 | myGCD = gcd(a,b); 30 | itoa(myGCD, buf, 10); 31 | println(buf); 32 | } 33 | 34 | void main() { 35 | GPIO_A->OUTPUT_ENABLE = 0x0000000F; 36 | GPIO_A->OUTPUT = 0x00000001; 37 | println("hello gcd world"); 38 | const int nleds = 4; 39 | const int nloops = 2000000; 40 | 41 | GCD->VALID = 0x00000000; 42 | while(GCD->READY); 43 | 44 | calcPrintGCD(1, 123913); 45 | calcPrintGCD(461952, 116298); 46 | calcPrintGCD(461952, 116298); 47 | calcPrintGCD(461952, 116298); 48 | 49 | while(1){ 50 | for(unsigned int i=0;iOUTPUT = 1<OUTPUT = (1<<(nleds-1))>>i; 56 | delay(nloops); 57 | } 58 | } 59 | } 60 | 61 | void irqCallback(){ 62 | } 63 | -------------------------------------------------------------------------------- /doc/gcdPeripheral/src/main/c/murax/gcd_world/src/murax.h: -------------------------------------------------------------------------------- 1 | #ifndef __MURAX_H__ 2 | #define __MURAX_H__ 3 | 4 | #include "timer.h" 5 | #include "prescaler.h" 6 | #include "interrupt.h" 7 | #include "gpio.h" 8 | #include "uart.h" 9 | #include "gcd.h" 10 | 11 | #define GPIO_A ((Gpio_Reg*)(0xF0000000)) 12 | #define TIMER_PRESCALER ((Prescaler_Reg*)0xF0020000) 13 | #define TIMER_INTERRUPT ((InterruptCtrl_Reg*)0xF0020010) 14 | #define TIMER_A ((Timer_Reg*)0xF0020040) 15 | #define TIMER_B ((Timer_Reg*)0xF0020050) 16 | #define UART ((Uart_Reg*)(0xF0010000)) 17 | #define GCD ((Gcd_Reg*)(0xF0030000)) 18 | 19 | 20 | #endif /* __MURAX_H__ */ 21 | -------------------------------------------------------------------------------- /doc/gcdPeripheral/src/main/c/murax/gcd_world/src/prescaler.h: -------------------------------------------------------------------------------- 1 | #ifndef PRESCALERCTRL_H_ 2 | #define PRESCALERCTRL_H_ 3 | 4 | #include 5 | 6 | 7 | typedef struct 8 | { 9 | volatile uint32_t LIMIT; 10 | } Prescaler_Reg; 11 | 12 | static void prescaler_init(Prescaler_Reg* reg){ 13 | 14 | } 15 | 16 | #endif /* PRESCALERCTRL_H_ */ 17 | -------------------------------------------------------------------------------- /doc/gcdPeripheral/src/main/c/murax/gcd_world/src/timer.h: -------------------------------------------------------------------------------- 1 | #ifndef TIMERCTRL_H_ 2 | #define TIMERCTRL_H_ 3 | 4 | #include 5 | 6 | 7 | typedef struct 8 | { 9 | volatile uint32_t CLEARS_TICKS; 10 | volatile uint32_t LIMIT; 11 | volatile uint32_t VALUE; 12 | } Timer_Reg; 13 | 14 | static void timer_init(Timer_Reg *reg){ 15 | reg->CLEARS_TICKS = 0; 16 | reg->VALUE = 0; 17 | } 18 | 19 | 20 | #endif /* TIMERCTRL_H_ */ 21 | -------------------------------------------------------------------------------- /doc/gcdPeripheral/src/main/c/murax/gcd_world/src/uart.h: -------------------------------------------------------------------------------- 1 | #ifndef UART_H_ 2 | #define UART_H_ 3 | 4 | 5 | typedef struct 6 | { 7 | volatile uint32_t DATA; 8 | volatile uint32_t STATUS; 9 | volatile uint32_t CLOCK_DIVIDER; 10 | volatile uint32_t FRAME_CONFIG; 11 | } Uart_Reg; 12 | 13 | enum UartParity {NONE = 0,EVEN = 1,ODD = 2}; 14 | enum UartStop {ONE = 0,TWO = 1}; 15 | 16 | typedef struct { 17 | uint32_t dataLength; 18 | enum UartParity parity; 19 | enum UartStop stop; 20 | uint32_t clockDivider; 21 | } Uart_Config; 22 | 23 | static uint32_t uart_writeAvailability(Uart_Reg *reg){ 24 | return (reg->STATUS >> 16) & 0xFF; 25 | } 26 | static uint32_t uart_readOccupancy(Uart_Reg *reg){ 27 | return reg->STATUS >> 24; 28 | } 29 | 30 | static void uart_write(Uart_Reg *reg, uint32_t data){ 31 | while(uart_writeAvailability(reg) == 0); 32 | reg->DATA = data; 33 | } 34 | 35 | static void uart_applyConfig(Uart_Reg *reg, Uart_Config *config){ 36 | reg->CLOCK_DIVIDER = config->clockDivider; 37 | reg->FRAME_CONFIG = ((config->dataLength-1) << 0) | (config->parity << 8) | (config->stop << 16); 38 | } 39 | 40 | #endif /* UART_H_ */ 41 | 42 | 43 | -------------------------------------------------------------------------------- /doc/gcdPeripheral/src/main/scala/vexriscv/periph/gcd/Apb3GCDCtrl.scala: -------------------------------------------------------------------------------- 1 | package vexriscv.periph.gcd 2 | 3 | import spinal.core._ 4 | import spinal.lib._ 5 | import spinal.lib.bus.amba3.apb.{Apb3, Apb3Config, Apb3SlaveFactory} 6 | import spinal.lib.eda.altera.QSysify 7 | import spinal.lib.slave 8 | 9 | object Apb3GCDCtrl { 10 | def getApb3Config = Apb3Config( 11 | addressWidth = 5, 12 | dataWidth = 32, 13 | selWidth = 1, 14 | useSlaveError = false 15 | ) 16 | } 17 | 18 | class Apb3GCDCtrl(apb3Config : Apb3Config) extends Component { 19 | val io = new Bundle { 20 | val apb = slave(Apb3(Apb3GCDCtrl.getApb3Config)) 21 | // maybe later 22 | // val interrupt = out Bool 23 | } 24 | val gcdCtrl = new GCDTop() 25 | val apbCtrl = Apb3SlaveFactory(io.apb) 26 | apbCtrl.driveAndRead(gcdCtrl.io.a, address=0) 27 | apbCtrl.driveAndRead(gcdCtrl.io.b, address=4) 28 | // when result of calculation ready, synchronize it into memory mapped register 29 | val resSyncBuf = RegNextWhen(gcdCtrl.io.res, gcdCtrl.io.ready) 30 | apbCtrl.read(resSyncBuf, address=8) 31 | // if result is read, it will be consumed, set ready to 0 32 | apbCtrl.onRead(8)(resSyncBuf := 0) 33 | apbCtrl.onRead(8)(rdySyncBuf := False) 34 | // synchronize ready signal into memory mapped register 35 | val rdySyncBuf = RegNextWhen(gcdCtrl.io.ready, gcdCtrl.io.ready) 36 | apbCtrl.read(rdySyncBuf, address=12) 37 | // set valid based on memory mapped register but clear/consume it after 1 cycle b): 23 | * a := a - b 24 | * else if(b > a): 25 | * b := b - a 26 | * else: 27 | * done := True 28 | */ 29 | //registers 30 | val regA = Reg(UInt(32 bits)) init(0) 31 | val regB = Reg(UInt(32 bits)) init(0) 32 | // compare 33 | val xGTy = regA > regB 34 | val xLTy = regA < regB 35 | // mux 36 | val chX = io.dataCtrl.selL ? regB | regA 37 | val chY = io.dataCtrl.selR ? regB | regA 38 | // subtract 39 | val subXY = chX - chY 40 | // load logic 41 | when(io.dataCtrl.init){ 42 | regA := io.a 43 | regB := io.b 44 | } 45 | when(io.dataCtrl.loadA){ 46 | regA := subXY 47 | } 48 | when(io.dataCtrl.loadB){ 49 | regB := subXY 50 | } 51 | io.dataCtrl.cmpAgtB := xGTy 52 | io.dataCtrl.cmpAltB := xLTy 53 | io.res := regA 54 | } -------------------------------------------------------------------------------- /doc/gcdPeripheral/src/main/scala/vexriscv/periph/gcd/GCDTop.scala: -------------------------------------------------------------------------------- 1 | package vexriscv.periph.gcd 2 | 3 | import spinal.core._ 4 | import spinal.lib._ 5 | import spinal.lib.IMasterSlave 6 | 7 | case class GCDDataControl() extends Bundle with IMasterSlave{ 8 | val cmpAgtB = Bool 9 | val cmpAltB = Bool 10 | val loadA = Bool 11 | val loadB = Bool 12 | val init = Bool 13 | val selL = Bool 14 | val selR = Bool 15 | // define <> semantic 16 | override def asMaster(): Unit = { 17 | // as controller: output, input 18 | out(loadA, loadB, selL, selR, init) 19 | in(cmpAgtB, cmpAltB) 20 | } 21 | } 22 | 23 | //Hardware definition 24 | class GCDTop() extends Component { 25 | val io = new Bundle { 26 | val valid = in Bool() 27 | val ready = out Bool() 28 | val a = in(UInt(32 bits)) 29 | val b = in(UInt(32 bits)) 30 | val res = out(UInt(32 bits)) 31 | } 32 | val gcdCtr = new GCDCtrl() 33 | gcdCtr.io.valid := io.valid 34 | io.ready := gcdCtr.io.ready 35 | val gcdDat = new GCDData() 36 | gcdDat.io.a := io.a 37 | gcdDat.io.b := io.b 38 | io.res := gcdDat.io.res 39 | gcdCtr.io.dataCtrl <> gcdDat.io.dataCtrl 40 | } 41 | 42 | object GCDTopVerilog { 43 | def main(args: Array[String]) { 44 | SpinalVerilog(new GCDTop) 45 | } 46 | } -------------------------------------------------------------------------------- /doc/gcdPeripheral/src/main/scala/vexriscv/periph/gcd/GCDTopSim.scala: -------------------------------------------------------------------------------- 1 | package vexriscv.periph.gcd 2 | 3 | import spinal.core._ 4 | import spinal.sim._ 5 | import spinal.core.sim._ 6 | 7 | //import scala.util.Random 8 | import java.util.concurrent.ThreadLocalRandom 9 | object GCDTopSim { 10 | def main(args: Array[String]) { 11 | 12 | SimConfig.withWave.doSim(new GCDTop()){dut => 13 | // SimConfig.doSim(new GCDTop()){dut => 14 | def gcd(a: Long,b: Long): Long = { 15 | if(b==0) a else gcd(b, a%b) 16 | } 17 | def RndNextUInt32(): Long = { 18 | ThreadLocalRandom.current().nextLong(Math.pow(2, 32).toLong - 1) 19 | } 20 | var a = 0L 21 | var b = 0L 22 | var model = 0L 23 | dut.io.a #= 0 24 | dut.io.b #= 0 25 | dut.io.valid #= false 26 | 27 | dut.clockDomain.forkStimulus(period = 10) 28 | dut.clockDomain.waitRisingEdge() 29 | 30 | for(idx <- 0 to 500){ 31 | // generate 2 random ints 32 | a = RndNextUInt32() 33 | b = RndNextUInt32() 34 | // calculate the model value (software) 35 | model = gcd(a,b) 36 | // apply stimulus with random ints 37 | dut.io.a #= a 38 | dut.io.b #= b 39 | dut.io.valid #= true 40 | dut.clockDomain.waitRisingEdge() 41 | dut.io.valid #= false 42 | // wait until calculation of hardware is done 43 | waitUntil(dut.io.ready.toBoolean) 44 | assert( 45 | assertion = (dut.io.res.toBigInt == model), 46 | message = "test " + idx + " failed. Expected " + model + ", retrieved: " + dut.io.res.toBigInt 47 | ) 48 | waitUntil(!dut.io.ready.toBoolean) 49 | } 50 | } 51 | } 52 | } 53 | -------------------------------------------------------------------------------- /doc/nativeJtag/soc_init.cfg: -------------------------------------------------------------------------------- 1 | if [info exists env(SPINAL_SIM)] { 2 | set SPINAL_SIM $::env(SPINAL_SIM) 3 | } else { 4 | set SPINAL_SIM no 5 | } 6 | 7 | set cpu_count 1 8 | 9 | 10 | for {set i 0} {$i < $cpu_count} {incr i} { 11 | target create saxon.cpu$i vexriscv -endian little -chain-position $TAP_NAME -coreid $i -dbgbase [expr $i*0x1000+0x10B80000] 12 | vexriscv readWaitCycles 40 13 | vexriscv cpuConfigFile $CPU0_YAML 14 | if {$SPINAL_SIM != "yes"} { 15 | vexriscv jtagMapping 3 3 0 1 2 2 16 | } 17 | } 18 | 19 | for {set i 0} {$i < $cpu_count} {incr i} { 20 | targets saxon.cpu$i 21 | poll_period 50 22 | init 23 | soft_reset_halt 24 | } 25 | 26 | puts " done" 27 | -------------------------------------------------------------------------------- /doc/nativeJtag/usb_connect.cfg: -------------------------------------------------------------------------------- 1 | adapter driver ftdi 2 | ftdi_device_desc "Digilent USB Device" 3 | ftdi_vid_pid 0x0403 0x6010 4 | ftdi_channel 0 5 | ftdi_layout_init 0x00e8 0x60eb 6 | ftdi_tdo_sample_edge falling 7 | 8 | reset_config none 9 | adapter speed 5000 10 | 11 | source [find cpld/xilinx-xc7.cfg] 12 | source [find cpld/jtagspi.cfg] 13 | 14 | set TAP_NAME xc7.tap 15 | -------------------------------------------------------------------------------- /project/build.properties: -------------------------------------------------------------------------------- 1 | sbt.version=1.6.0 2 | -------------------------------------------------------------------------------- /project/plugins.sbt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/SpinalHDL/VexRiscv/79e6a600bd7fdae275bc893fda317bd6a27df762/project/plugins.sbt -------------------------------------------------------------------------------- /scripts/Murax/arty_a7/make_mcs_file: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | #Create mcs file for QSPI flash 3 | 4 | cd ./build 5 | 6 | vivado -mode batch -source ../make_mcs_file.tcl -notrace 7 | -------------------------------------------------------------------------------- /scripts/Murax/arty_a7/make_mcs_file.tcl: -------------------------------------------------------------------------------- 1 | 2 | # Input file 3 | set source_bit_file "./latest.bit" 4 | 5 | # Output file 6 | set output_mcs_file "./latest.mcs" 7 | 8 | # Delete target file 9 | file delete -force $output_mcs_file 10 | 11 | # Determine if the user has built the project and has the target source file 12 | # If not, then use the reference bit file shipped with the project 13 | if { ![file exists $source_bit_file] } { 14 | puts "\n********************************************" 15 | puts "INFO - File $source_bit_file doesn't exist as project has not been built\n" 16 | puts "********************************************/n" 17 | error 18 | } 19 | 20 | # Create MCS file for base board QSPI flash memory 21 | write_cfgmem -force -format MCS -size 16 -interface SPIx4 -loadbit " up 0 $source_bit_file" $output_mcs_file 22 | 23 | # Check MCS was correctly made 24 | if { ![file exists $output_mcs_file] } { 25 | puts "ERROR - $output_bit_file not made" 26 | return -1 27 | } else { 28 | puts "\n********************************************" 29 | puts " $output_mcs_file correctly generated" 30 | puts "********************************************\n" 31 | } 32 | -------------------------------------------------------------------------------- /scripts/Murax/arty_a7/make_mmi_files: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | cd ./build 4 | vivado -mode batch -source ../make_mmi_files.tcl -notrace 5 | -------------------------------------------------------------------------------- /scripts/Murax/arty_a7/make_mmi_files.tcl: -------------------------------------------------------------------------------- 1 | source [file join [file dirname [file normalize [info script]]] vivado_params.tcl] 2 | 3 | open_project -read_only $outputdir/$projectName 4 | open_run impl_1 5 | source $base/soc_mmi.tcl 6 | puts "mmi files generated" 7 | -------------------------------------------------------------------------------- /scripts/Murax/arty_a7/make_vivado_project: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | #cannot rm build because it erase software images that the make file copy there 4 | #rm -rf ./build 5 | 6 | mkdir -p ./build 7 | 8 | cd ./build 9 | vivado -mode batch -source ../make_vivado_project.tcl -notrace 10 | -------------------------------------------------------------------------------- /scripts/Murax/arty_a7/makefile: -------------------------------------------------------------------------------- 1 | ROOT=../../.. 2 | SWBASE=$(ROOT)/src/main/c/murax 3 | SOCSW=hello_world 4 | SOCMEMSRC=$(SWBASE)/$(SOCSW)/build/$(SOCSW).v 5 | SOCMEM=build/soc.mem 6 | 7 | TOP=Murax 8 | 9 | all : build/latest.bit 10 | 11 | ../../../$(TOP).v : toplevel.v 12 | (cd ../../..; sbt "runMain vexriscv.demo.Murax_arty") 13 | 14 | .PHONY: $(SOCMEMSRC) 15 | $(SOCMEMSRC): 16 | mkdir -p build 17 | make -C $(SWBASE)/$(SOCSW) 18 | 19 | $(SOCMEM) : $(SOCMEMSRC) 20 | cp -u $(SOCMEMSRC) $(SOCMEM) 21 | 22 | build/vivado_project/fpga.runs/impl_1/toplevel.bit : toplevel.v arty_a7.xdc ../../../$(TOP).v 23 | mkdir -p build 24 | ./make_vivado_project 25 | cp build/vivado_project/fpga.runs/impl_1/toplevel.bit build/latest.bit 26 | 27 | build/soc.mmi: build/vivado_project/fpga.runs/impl_1/toplevel.bit 28 | ./make_mmi_files 29 | 30 | build/latest_soc_sw.bit : $(SOCMEM) build/soc.mmi 31 | rm -f updatemem.jou updatemem.log 32 | updatemem -force --meminfo build/soc.mmi --data $(SOCMEM) --bit build/latest.bit --proc dummy --out build/latest_soc_sw.bit 33 | cp build/latest_soc_sw.bit build/latest.bit 34 | 35 | build/latest.bit : build/latest_soc_sw.bit 36 | 37 | build/latest.mcs : build/latest.bit 38 | ./make_mcs_file 39 | 40 | prog : build/latest.bit 41 | ./write_fpga 42 | 43 | flash : build/latest.mcs 44 | ./write_flash 45 | 46 | clean-soc-sw: 47 | make -C $(SWBASE)/$(SOCSW) clean-all 48 | 49 | soc-sw: clean-soc-sw $(SOCMEM) 50 | 51 | .PHONY: clean 52 | clean : 53 | rm -rf build 54 | mkdir build 55 | rm -f updatemem.jou 56 | rm -f updatemem.log 57 | 58 | clean-sw: clean-soc-sw 59 | 60 | clean-all : clean clean-sw 61 | rm -f ../../../$(TOP).v 62 | rm -f ../../../$(TOP).v_* 63 | -------------------------------------------------------------------------------- /scripts/Murax/arty_a7/open_vivado_project: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | cd ./build 4 | vivado -mode batch -source ../open_vivado_project.tcl -notrace 5 | -------------------------------------------------------------------------------- /scripts/Murax/arty_a7/open_vivado_project.tcl: -------------------------------------------------------------------------------- 1 | source [file join [file dirname [file normalize [info script]]] vivado_params.tcl] 2 | 3 | open_project -read_only $outputdir/$projectName 4 | start_gui 5 | -------------------------------------------------------------------------------- /scripts/Murax/arty_a7/picocom_arty: -------------------------------------------------------------------------------- 1 | picocom --baud 115200 --imap lfcrlf /dev/ttyUSB1 2 | -------------------------------------------------------------------------------- /scripts/Murax/arty_a7/vivado_params.tcl: -------------------------------------------------------------------------------- 1 | set outputdir ./vivado_project 2 | set part "xc7a35ticsg324-1L" 3 | set base ".." 4 | set projectName "fpga" 5 | set topv "$base/../../../Murax.v" 6 | -------------------------------------------------------------------------------- /scripts/Murax/arty_a7/write_flash: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | cd ./build 3 | vivado -mode batch -source ../write_flash.tcl -notrace 4 | -------------------------------------------------------------------------------- /scripts/Murax/arty_a7/write_fpga: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | cd ./build 3 | vivado -mode batch -source ../write_fpga.tcl -notrace 4 | -------------------------------------------------------------------------------- /scripts/Murax/arty_a7/write_fpga.tcl: -------------------------------------------------------------------------------- 1 | open_hw 2 | connect_hw_server 3 | open_hw_target 4 | current_hw_device [get_hw_devices xc7a35t_0] 5 | refresh_hw_device -update_hw_probes false [lindex [get_hw_devices xc7a35t_0] 0] 6 | set_property PROBES.FILE {} [get_hw_devices xc7a35t_0] 7 | set_property FULL_PROBES.FILE {} [get_hw_devices xc7a35t_0] 8 | set_property PROGRAM.FILE {latest.bit} [get_hw_devices xc7a35t_0] 9 | program_hw_devices [get_hw_devices xc7a35t_0] 10 | disconnect_hw_server 11 | -------------------------------------------------------------------------------- /scripts/Murax/iCE40-hx8k_breakout_board/Makefile: -------------------------------------------------------------------------------- 1 | 2 | 3 | VERILOG = ../../../Murax.v toplevel.v 4 | 5 | generate : 6 | (cd ../../..; sbt "runMain vexriscv.demo.MuraxWithRamInit") 7 | 8 | ../../../Murax.v : 9 | (cd ../../..; sbt "runMain vexriscv.demo.MuraxWithRamInit") 10 | 11 | ../../../Murax.v*.bin: 12 | 13 | bin/toplevel.blif : ${VERILOG} ../../../Murax.v*.bin 14 | mkdir -p bin 15 | rm -f Murax.v*.bin 16 | cp ../../../Murax.v*.bin . | true 17 | yosys -v3 -p "synth_ice40 -top toplevel -blif bin/toplevel.blif" ${VERILOG} 18 | 19 | bin/toplevel.asc : toplevel.pcf bin/toplevel.blif 20 | arachne-pnr -p toplevel.pcf -d 8k --max-passes 600 -P ct256 bin/toplevel.blif -o bin/toplevel.asc 21 | 22 | bin/toplevel.bin : bin/toplevel.asc 23 | icepack bin/toplevel.asc bin/toplevel.bin 24 | 25 | compile : bin/toplevel.bin 26 | 27 | time: bin/toplevel.bin 28 | icetime -tmd hx8k bin/toplevel.asc 29 | 30 | prog : bin/toplevel.bin 31 | iceprog -S bin/toplevel.bin 32 | 33 | sudo-prog : bin/toplevel.bin 34 | sudo iceprog -S bin/toplevel.bin 35 | 36 | clean : 37 | rm -rf bin 38 | rm -f Murax.v*.bin 39 | -------------------------------------------------------------------------------- /scripts/Murax/iCE40-hx8k_breakout_board/img/cram-programming-config.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/SpinalHDL/VexRiscv/79e6a600bd7fdae275bc893fda317bd6a27df762/scripts/Murax/iCE40-hx8k_breakout_board/img/cram-programming-config.png -------------------------------------------------------------------------------- /scripts/Murax/iCE40-hx8k_breakout_board/img/iCE40HX8K-breakout-revA.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/SpinalHDL/VexRiscv/79e6a600bd7fdae275bc893fda317bd6a27df762/scripts/Murax/iCE40-hx8k_breakout_board/img/iCE40HX8K-breakout-revA.png -------------------------------------------------------------------------------- /scripts/Murax/iCE40-hx8k_breakout_board/toplevel.pcf: -------------------------------------------------------------------------------- 1 | ## iCE40-hx8k breakout board 2 | 3 | set_io io_J3 J3 4 | set_io io_H16 H16 5 | set_io io_G15 G15 6 | set_io io_G16 G16 7 | set_io io_F15 F15 8 | set_io io_B12 B12 9 | set_io io_B10 B10 10 | set_io io_led[0] B5 11 | set_io io_led[1] B4 12 | set_io io_led[2] A2 13 | set_io io_led[3] A1 14 | set_io io_led[4] C5 15 | set_io io_led[5] C4 16 | set_io io_led[6] B3 17 | set_io io_led[7] C3 18 | 19 | 20 | -------------------------------------------------------------------------------- /scripts/Murax/iCE40-hx8k_breakout_board/toplevel.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module toplevel( 4 | input io_J3, 5 | input io_H16, 6 | input io_G15, 7 | output io_G16, 8 | input io_F15, 9 | output io_B12, 10 | input io_B10, 11 | output [7:0] io_led 12 | ); 13 | 14 | wire [31:0] io_gpioA_read; 15 | wire [31:0] io_gpioA_write; 16 | wire [31:0] io_gpioA_writeEnable; 17 | wire io_mainClk; 18 | wire io_jtag_tck; 19 | 20 | SB_GB mainClkBuffer ( 21 | .USER_SIGNAL_TO_GLOBAL_BUFFER (io_J3), 22 | .GLOBAL_BUFFER_OUTPUT ( io_mainClk) 23 | ); 24 | 25 | SB_GB jtagClkBuffer ( 26 | .USER_SIGNAL_TO_GLOBAL_BUFFER (io_H16), 27 | .GLOBAL_BUFFER_OUTPUT ( io_jtag_tck) 28 | ); 29 | 30 | assign io_led = io_gpioA_write[7 : 0]; 31 | 32 | Murax murax ( 33 | .io_asyncReset(0), 34 | .io_mainClk (io_mainClk ), 35 | .io_jtag_tck(io_jtag_tck), 36 | .io_jtag_tdi(io_G15), 37 | .io_jtag_tdo(io_G16), 38 | .io_jtag_tms(io_F15), 39 | .io_gpioA_read (io_gpioA_read), 40 | .io_gpioA_write (io_gpioA_write), 41 | .io_gpioA_writeEnable(io_gpioA_writeEnable), 42 | .io_uart_txd(io_B12), 43 | .io_uart_rxd(io_B10) 44 | ); 45 | endmodule -------------------------------------------------------------------------------- /scripts/Murax/iCE40-hx8k_breakout_board_xip/Makefile: -------------------------------------------------------------------------------- 1 | 2 | VBASE = ../../.. 3 | VNAME = Murax_iCE40_hx8k_breakout_board_xip 4 | VERILOG = ${VBASE}/${VNAME}.v 5 | 6 | all: prog 7 | 8 | ${VERILOG} : 9 | (cd ${VBASE}; sbt "runMain vexriscv.demo.${VNAME}") 10 | 11 | generate : ${VERILOG} 12 | 13 | ${VERILOG}*.bin: 14 | 15 | bin/Murax_iCE40_hx8k_breakout_board_xip.blif : ${VERILOG} ${VERILOG}*.bin 16 | mkdir -p bin 17 | rm -f Murax_iCE40_hx8k_breakout_board_xip.v*.bin 18 | cp ${VERILOG}*.bin . | true 19 | yosys -v3 -p "synth_ice40 -top Murax_iCE40_hx8k_breakout_board_xip -blif bin/Murax_iCE40_hx8k_breakout_board_xip.blif" ${VERILOG} 20 | 21 | bin/Murax_iCE40_hx8k_breakout_board_xip.asc : Murax_iCE40_hx8k_breakout_board_xip.pcf bin/Murax_iCE40_hx8k_breakout_board_xip.blif 22 | arachne-pnr -p Murax_iCE40_hx8k_breakout_board_xip.pcf -d 8k --max-passes 600 -P ct256 bin/Murax_iCE40_hx8k_breakout_board_xip.blif -o bin/Murax_iCE40_hx8k_breakout_board_xip.asc 23 | 24 | bin/Murax_iCE40_hx8k_breakout_board_xip.bin : bin/Murax_iCE40_hx8k_breakout_board_xip.asc 25 | icepack bin/Murax_iCE40_hx8k_breakout_board_xip.asc bin/Murax_iCE40_hx8k_breakout_board_xip.bin 26 | 27 | compile : bin/Murax_iCE40_hx8k_breakout_board_xip.bin 28 | 29 | time: bin/Murax_iCE40_hx8k_breakout_board_xip.bin 30 | icetime -tmd hx8k bin/Murax_iCE40_hx8k_breakout_board_xip.asc 31 | 32 | prog : bin/Murax_iCE40_hx8k_breakout_board_xip.bin 33 | lsusb -d 0403:6010 34 | iceprog -S bin/Murax_iCE40_hx8k_breakout_board_xip.bin 35 | 36 | sudo-prog : bin/Murax_iCE40_hx8k_breakout_board_xip.bin 37 | sudo lsusb -d 0403:6010 38 | sudo iceprog -S bin/Murax_iCE40_hx8k_breakout_board_xip.bin 39 | 40 | clean : 41 | rm -rf bin 42 | rm -f Murax_iCE40_hx8k_breakout_board_xip.v*.bin 43 | rm -f ${VERILOG}*.bin 44 | rm -f ${VERILOG} 45 | -------------------------------------------------------------------------------- /scripts/Murax/iCE40-hx8k_breakout_board_xip/Murax_iCE40_hx8k_breakout_board_xip.pcf: -------------------------------------------------------------------------------- 1 | ## iCE40-hx8k breakout board 2 | 3 | set_io io_mainClk J3 4 | set_io io_jtag_tck H16 5 | set_io io_jtag_tdi G15 6 | set_io io_jtag_tdo G16 7 | set_io io_jtag_tms F15 8 | set_io io_uart_txd B12 9 | set_io io_uart_rxd B10 10 | set_io io_led[0] B5 11 | set_io io_led[1] B4 12 | set_io io_led[2] A2 13 | set_io io_led[3] A1 14 | set_io io_led[4] C5 15 | set_io io_led[5] C4 16 | set_io io_led[6] B3 17 | set_io io_led[7] C3 18 | 19 | #XIP 20 | set_io io_miso P12 21 | set_io io_mosi P11 22 | set_io io_sclk R11 23 | set_io io_spis R12 24 | -------------------------------------------------------------------------------- /scripts/Murax/iCE40-hx8k_breakout_board_xip/img/cram-programming-config.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/SpinalHDL/VexRiscv/79e6a600bd7fdae275bc893fda317bd6a27df762/scripts/Murax/iCE40-hx8k_breakout_board_xip/img/cram-programming-config.png -------------------------------------------------------------------------------- /scripts/Murax/iCE40-hx8k_breakout_board_xip/img/iCE40HX8K-breakout-revA.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/SpinalHDL/VexRiscv/79e6a600bd7fdae275bc893fda317bd6a27df762/scripts/Murax/iCE40-hx8k_breakout_board_xip/img/iCE40HX8K-breakout-revA.png -------------------------------------------------------------------------------- /scripts/Murax/iCE40HX8K-EVB/Makefile: -------------------------------------------------------------------------------- 1 | 2 | 3 | VERILOG = ../../../Murax.v toplevel.v toplevel_pll.v 4 | 5 | generate : 6 | (cd ../../..; sbt "runMain vexriscv.demo.MuraxWithRamInit") 7 | 8 | ../../../Murax.v : 9 | (cd ../../..; sbt "runMain vexriscv.demo.MuraxWithRamInit") 10 | 11 | ../../../Murax.v*.bin: 12 | 13 | bin/toplevel.blif : ${VERILOG} ../../../Murax.v*.bin 14 | mkdir -p bin 15 | rm -f Murax.v*.bin 16 | cp ../../../Murax.v*.bin . | true 17 | yosys -v3 -p "synth_ice40 -top toplevel -blif bin/toplevel.blif" ${VERILOG} 18 | 19 | bin/toplevel.asc : toplevel.pcf bin/toplevel.blif 20 | arachne-pnr -p toplevel.pcf -d 8k --max-passes 600 -P ct256 bin/toplevel.blif -o bin/toplevel.asc 21 | 22 | bin/toplevel.bin : bin/toplevel.asc 23 | icepack bin/toplevel.asc bin/toplevel.bin 24 | 25 | compile : bin/toplevel.bin 26 | 27 | time: bin/toplevel.bin 28 | icetime -tmd hx8k bin/toplevel.asc 29 | 30 | prog : bin/toplevel.bin 31 | iceprogduino bin/toplevel.bin 32 | 33 | sudo-prog : bin/toplevel.bin 34 | sudo iceprogduino bin/toplevel.bin 35 | 36 | clean : 37 | rm -rf bin 38 | rm -f Murax.v*.bin 39 | -------------------------------------------------------------------------------- /scripts/Murax/iCE40HX8K-EVB/toplevel.pcf: -------------------------------------------------------------------------------- 1 | set_io CLK J3 2 | set_io BUT1 K11 3 | set_io BUT2 P13 4 | set_io LED1 M12 5 | set_io LED2 R16 6 | -------------------------------------------------------------------------------- /scripts/Murax/iCE40HX8K-EVB/toplevel.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module toplevel( 4 | input CLK, 5 | input BUT1, 6 | input BUT2, 7 | output LED1, 8 | output LED2 9 | ); 10 | 11 | assign LED1 = io_gpioA_write[0]; 12 | assign LED2 = io_gpioA_write[7]; 13 | 14 | wire [31:0] io_gpioA_read; 15 | wire [31:0] io_gpioA_write; 16 | wire [31:0] io_gpioA_writeEnable; 17 | wire io_mainClk; 18 | 19 | // Use PLL to downclock external clock. 20 | toplevel_pll toplevel_pll_inst(.REFERENCECLK(CLK), 21 | .PLLOUTCORE(io_mainClk), 22 | .PLLOUTGLOBAL(), 23 | .RESET(1'b1)); 24 | 25 | Murax murax ( 26 | .io_asyncReset(1'b0), 27 | .io_mainClk (io_mainClk), 28 | .io_jtag_tck(1'b0), 29 | .io_jtag_tdi(1'b0), 30 | .io_jtag_tdo(), 31 | .io_jtag_tms(1'b0), 32 | .io_gpioA_read (io_gpioA_read), 33 | .io_gpioA_write (io_gpioA_write), 34 | .io_gpioA_writeEnable(io_gpioA_writeEnable), 35 | .io_uart_txd(), 36 | .io_uart_rxd(0'b0) 37 | ); 38 | 39 | endmodule 40 | -------------------------------------------------------------------------------- /scripts/Murax/iCE40HX8K-EVB/toplevel_pll.v: -------------------------------------------------------------------------------- 1 | module toplevel_pll(REFERENCECLK, 2 | PLLOUTCORE, 3 | PLLOUTGLOBAL, 4 | RESET); 5 | 6 | input REFERENCECLK; 7 | input RESET; /* To initialize the simulation properly, the RESET signal (Active Low) must be asserted at the beginning of the simulation */ 8 | output PLLOUTCORE; 9 | output PLLOUTGLOBAL; 10 | 11 | SB_PLL40_CORE toplevel_pll_inst(.REFERENCECLK(REFERENCECLK), 12 | .PLLOUTCORE(PLLOUTCORE), 13 | .PLLOUTGLOBAL(PLLOUTGLOBAL), 14 | .EXTFEEDBACK(), 15 | .DYNAMICDELAY(), 16 | .RESETB(RESET), 17 | .BYPASS(1'b0), 18 | .LATCHINPUTVALUE(), 19 | .LOCK(), 20 | .SDI(), 21 | .SDO(), 22 | .SCLK()); 23 | 24 | //\\ Fin=100, Fout=12; 25 | defparam toplevel_pll_inst.DIVR = 4'b0010; 26 | defparam toplevel_pll_inst.DIVF = 7'b0010110; 27 | defparam toplevel_pll_inst.DIVQ = 3'b110; 28 | defparam toplevel_pll_inst.FILTER_RANGE = 3'b011; 29 | defparam toplevel_pll_inst.FEEDBACK_PATH = "SIMPLE"; 30 | defparam toplevel_pll_inst.DELAY_ADJUSTMENT_MODE_FEEDBACK = "FIXED"; 31 | defparam toplevel_pll_inst.FDA_FEEDBACK = 4'b0000; 32 | defparam toplevel_pll_inst.DELAY_ADJUSTMENT_MODE_RELATIVE = "FIXED"; 33 | defparam toplevel_pll_inst.FDA_RELATIVE = 4'b0000; 34 | defparam toplevel_pll_inst.SHIFTREG_DIV_MODE = 2'b00; 35 | defparam toplevel_pll_inst.PLLOUT_SELECT = "GENCLK"; 36 | defparam toplevel_pll_inst.ENABLE_ICEGATE = 1'b0; 37 | 38 | endmodule 39 | -------------------------------------------------------------------------------- /scripts/regression/.gitignore: -------------------------------------------------------------------------------- 1 | verilator* 2 | verilator 3 | !verilator.mk 4 | -------------------------------------------------------------------------------- /scripts/regression/makefile: -------------------------------------------------------------------------------- 1 | .ONESHELL: 2 | 3 | include verilator.mk 4 | include regression.mk 5 | 6 | 7 | 8 | -------------------------------------------------------------------------------- /scripts/regression/regression.mk: -------------------------------------------------------------------------------- 1 | .ONESHELL: 2 | 3 | 4 | regression_random: 5 | cd ../.. 6 | export VEXRISCV_REGRESSION_CONFIG_COUNT=4 7 | export VEXRISCV_REGRESSION_FREERTOS_COUNT=1 8 | export VEXRISCV_REGRESSION_ZEPHYR_COUNT=4 9 | export VEXRISCV_REGRESSION_THREAD_COUNT=1 10 | sbt "testOnly vexriscv.TestIndividualFeatures" 11 | 12 | regression_random_linux: 13 | cd ../.. 14 | export VEXRISCV_REGRESSION_CONFIG_COUNT=2 15 | export VEXRISCV_REGRESSION_CONFIG_LINUX_RATE=1.0 16 | export VEXRISCV_REGRESSION_CONFIG_SECURE_RATE=0.0 17 | export VEXRISCV_REGRESSION_FREERTOS_COUNT=1 18 | export VEXRISCV_REGRESSION_ZEPHYR_COUNT=2 19 | export VEXRISCV_REGRESSION_THREAD_COUNT=1 20 | sbt "testOnly vexriscv.TestIndividualFeatures" 21 | 22 | 23 | regression_random_machine_os: 24 | cd ../.. 25 | export VEXRISCV_REGRESSION_CONFIG_COUNT=10 26 | export VEXRISCV_REGRESSION_CONFIG_LINUX_RATE=0.0 27 | export VEXRISCV_REGRESSION_CONFIG_MACHINE_OS_RATE=1.0 28 | export VEXRISCV_REGRESSION_CONFIG_SECURE_RATE=0.0 29 | export VEXRISCV_REGRESSION_FREERTOS_COUNT=1 30 | export VEXRISCV_REGRESSION_ZEPHYR_COUNT=2 31 | export VEXRISCV_REGRESSION_THREAD_COUNT=1 32 | sbt "testOnly vexriscv.TestIndividualFeatures" 33 | 34 | regression_random_baremetal: 35 | cd ../.. 36 | export VEXRISCV_REGRESSION_CONFIG_COUNT=30 37 | export VEXRISCV_REGRESSION_CONFIG_LINUX_RATE=0.0 38 | export VEXRISCV_REGRESSION_CONFIG_MACHINE_OS_RATE=0.0 39 | export VEXRISCV_REGRESSION_CONFIG_SECURE_RATE=0.0 40 | export VEXRISCV_REGRESSION_FREERTOS_COUNT=1 41 | export VEXRISCV_REGRESSION_ZEPHYR_COUNT=no 42 | export VEXRISCV_REGRESSION_THREAD_COUNT=1 43 | sbt "testOnly vexriscv.TestIndividualFeatures" 44 | 45 | 46 | regression_dhrystone: 47 | cd ../.. 48 | sbt "testOnly vexriscv.DhrystoneBench" 49 | -------------------------------------------------------------------------------- /scripts/regression/verilator.mk: -------------------------------------------------------------------------------- 1 | 2 | .ONESHELL: 3 | 4 | verilator/configure: 5 | rm -rf verilator* 6 | wget https://www.veripool.org/ftp/verilator-4.034.tgz 7 | tar xvzf verilator*.t*gz 8 | mv verilator-4.034 verilator 9 | 10 | verilator/Makefile: verilator/configure 11 | cd verilator 12 | ./configure 13 | 14 | verilator/bin/verilator_bin: verilator/Makefile 15 | cd verilator 16 | make -j$(shell nproc) 17 | rm -rf src/obj_dbg 18 | rm -rf src/obj_opt 19 | 20 | verilator_binary: verilator/bin/verilator_bin 21 | -------------------------------------------------------------------------------- /src/main/c/common/riscv64-unknown-elf.mk: -------------------------------------------------------------------------------- 1 | RISCV_BIN ?= riscv64-unknown-elf- 2 | RISCV_CC=${RISCV_BIN}gcc 3 | RISCV_OBJCOPY=${RISCV_BIN}objcopy 4 | RISCV_OBJDUMP=${RISCV_BIN}objdump 5 | 6 | MARCH := rv32i 7 | ifeq ($(MULDIV),yes) 8 | MARCH := $(MARCH)M 9 | endif 10 | ifeq ($(COMPRESSED),yes) 11 | MARCH := $(MARCH)AC 12 | endif 13 | 14 | CFLAGS += -march=$(MARCH) -mabi=ilp32 -DUSE_GP 15 | LDFLAGS += -march=$(MARCH) -mabi=ilp32 16 | 17 | -------------------------------------------------------------------------------- /src/main/c/common/standalone.mk: -------------------------------------------------------------------------------- 1 | 2 | 3 | LDFLAGS += -lc 4 | 5 | CFLAGS += -I${STANDALONE}/include 6 | 7 | 8 | 9 | 10 | ifeq ($(DEBUG),yes) 11 | CFLAGS += -g3 -Og 12 | endif 13 | 14 | ifeq ($(DEBUG),no) 15 | CFLAGS += -O3 16 | endif 17 | 18 | 19 | LDFLAGS += -nostdlib -lgcc -nostartfiles -ffreestanding -Wl,-Bstatic,-T,$(LDSCRIPT),-Map,$(OBJDIR)/$(PROJ_NAME).map,--print-memory-usage 20 | 21 | 22 | 23 | OBJDIR ?= build 24 | OBJS := $(SRCS) 25 | OBJS := $(OBJS:.c=.o) 26 | OBJS := $(OBJS:.cpp=.o) 27 | OBJS := $(OBJS:.S=.o) 28 | OBJS := $(OBJS:..=miaou) 29 | OBJS := $(addprefix $(OBJDIR)/,$(OBJS)) 30 | 31 | 32 | 33 | all: $(OBJDIR)/$(PROJ_NAME).elf $(OBJDIR)/$(PROJ_NAME).hex $(OBJDIR)/$(PROJ_NAME).asm $(OBJDIR)/$(PROJ_NAME).bin 34 | 35 | $(OBJDIR)/%.elf: $(OBJS) | $(OBJDIR) 36 | $(RISCV_CC) $(CFLAGS) -o $@ $^ $(LDFLAGS) $(LIBS) 37 | 38 | %.hex: %.elf 39 | $(RISCV_OBJCOPY) -O ihex $^ $@ 40 | 41 | %.bin: %.elf 42 | $(RISCV_OBJCOPY) -O binary $^ $@ 43 | 44 | %.v: %.elf 45 | $(RISCV_OBJCOPY) -O verilog $^ $@ 46 | 47 | %.asm: %.elf 48 | $(RISCV_OBJDUMP) -S -d $^ > $@ 49 | 50 | $(OBJDIR)/%.o: %.c 51 | mkdir -p $(dir $@) 52 | $(RISCV_CC) -c $(CFLAGS) $(INC) -o $@ $^ 53 | 54 | $(OBJDIR)/%.o: %.cpp 55 | mkdir -p $(dir $@) 56 | $(RISCV_CC) -c $(CFLAGS) $(INC) -o $@ $^ 57 | 58 | $(OBJDIR)/%.o: %.S 59 | mkdir -p $(dir $@) 60 | $(RISCV_CC) -c $(CFLAGS) -o $@ $^ -D__ASSEMBLY__=1 61 | 62 | $(OBJDIR): 63 | mkdir -p $@ 64 | 65 | clean: 66 | rm -f $(OBJDIR)/$(PROJ_NAME).elf 67 | rm -f $(OBJDIR)/$(PROJ_NAME).hex 68 | rm -f $(OBJDIR)/$(PROJ_NAME).map 69 | rm -f $(OBJDIR)/$(PROJ_NAME).v 70 | rm -f $(OBJDIR)/$(PROJ_NAME).bin 71 | rm -f $(OBJDIR)/$(PROJ_NAME).asm 72 | find $(OBJDIR) -type f -name '*.o' -print0 | xargs -0 -r rm 73 | 74 | .SECONDARY: $(OBJS) -------------------------------------------------------------------------------- /src/main/c/emulator/.gitignore: -------------------------------------------------------------------------------- 1 | *.map 2 | *.v 3 | *.elf 4 | *.o 5 | *.hex 6 | !*.bin -------------------------------------------------------------------------------- /src/main/c/emulator/build/emulator.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/SpinalHDL/VexRiscv/79e6a600bd7fdae275bc893fda317bd6a27df762/src/main/c/emulator/build/emulator.bin -------------------------------------------------------------------------------- /src/main/c/emulator/makefile: -------------------------------------------------------------------------------- 1 | PROJ_NAME=emulator 2 | DEBUG=no 3 | MULDIV=no 4 | COMPRESSED=no 5 | STANDALONE = .. 6 | 7 | 8 | SRCS = $(wildcard src/*.c) \ 9 | $(wildcard src/*.cpp) \ 10 | $(wildcard src/*.S) 11 | 12 | 13 | LDSCRIPT = ${STANDALONE}/common/ram.ld 14 | 15 | sim: CFLAGS += -DSIM 16 | sim: all 17 | 18 | qemu: CFLAGS += -DQEMU 19 | qemu: all 20 | 21 | litex: CFLAGS += -DLITEX -I${LITEX_GENERATED} -I${LITEX_BASE}/litex/soc/software/include 22 | litex: | check_litex all 23 | check_litex: 24 | @[ "${LITEX_BASE}" ] || ( echo ">> LITEX_BASE is not set"; exit 1 ) 25 | @[ "${LITEX_GENERATED}" ] || ( echo ">> LITEX_GENERATED is not set"; exit 1 ) 26 | 27 | include ${STANDALONE}/common/riscv64-unknown-elf.mk 28 | include ${STANDALONE}/common/standalone.mk 29 | 30 | -------------------------------------------------------------------------------- /src/main/c/emulator/src/config.h: -------------------------------------------------------------------------------- 1 | #ifndef CONFIG_H 2 | #define CONFIG_H 3 | 4 | #ifndef OS_CALL 5 | #define OS_CALL 0xC0000000 6 | #endif 7 | 8 | #ifndef DTB 9 | #define DTB 0xC3000000 10 | #endif 11 | 12 | #endif 13 | -------------------------------------------------------------------------------- /src/main/c/emulator/src/hal.h: -------------------------------------------------------------------------------- 1 | 2 | #ifndef HAL_H 3 | #define HAL_H 4 | 5 | #include 6 | 7 | #define SBI_SET_TIMER 0 8 | #define SBI_CONSOLE_PUTCHAR 1 9 | #define SBI_CONSOLE_GETCHAR 2 10 | #define SBI_CLEAR_IPI 3 11 | #define SBI_SEND_IPI 4 12 | #define SBI_REMOTE_FENCE_I 5 13 | #define SBI_REMOTE_SFENCE_VMA 6 14 | #define SBI_REMOTE_SFENCE_VMA_ASID 7 15 | #define SBI_SHUTDOWN 8 16 | 17 | void halInit(); 18 | void stopSim(); 19 | void putC(char c); 20 | int32_t getC(); 21 | uint32_t rdtime(); 22 | uint32_t rdtimeh(); 23 | void setMachineTimerCmp(uint32_t low, uint32_t high); 24 | 25 | #endif 26 | -------------------------------------------------------------------------------- /src/main/c/emulator/src/start.S: -------------------------------------------------------------------------------- 1 | .section .init 2 | .globl _start 3 | .type _start,@function 4 | 5 | #include "config.h" 6 | _start: 7 | /*#ifdef USE_GP 8 | .option push 9 | .option norelax 10 | la gp, __global_pointer$ 11 | .option pop 12 | #endif*/ 13 | la sp, _sp 14 | 15 | 16 | /* Load data section */ 17 | la a0, _data_lma 18 | la a1, _data 19 | la a2, _edata 20 | bgeu a1, a2, 2f 21 | 1: 22 | lw t0, (a0) 23 | sw t0, (a1) 24 | addi a0, a0, 4 25 | addi a1, a1, 4 26 | bltu a1, a2, 1b 27 | 2: 28 | 29 | /* Clear bss section */ 30 | la a0, __bss_start 31 | la a1, _end 32 | bgeu a0, a1, 2f 33 | 1: 34 | sw zero, (a0) 35 | addi a0, a0, 4 36 | bltu a0, a1, 1b 37 | 2: 38 | 39 | call __libc_init_array 40 | call init 41 | la ra, done 42 | li a0, 0 43 | li a1, DTB 44 | mret 45 | done: 46 | j done 47 | 48 | 49 | .globl _init 50 | _init: 51 | ret 52 | -------------------------------------------------------------------------------- /src/main/c/emulator/src/trap.S: -------------------------------------------------------------------------------- 1 | .section .init 2 | .globl trapEntry 3 | .type trapEntry,@function 4 | 5 | trapEntry: 6 | csrrw sp, mscratch, sp 7 | sw x1, 1*4(sp) 8 | sw x3, 3*4(sp) 9 | sw x4, 4*4(sp) 10 | sw x5, 5*4(sp) 11 | sw x6, 6*4(sp) 12 | sw x7, 7*4(sp) 13 | sw x8, 8*4(sp) 14 | sw x9, 9*4(sp) 15 | sw x10, 10*4(sp) 16 | sw x11, 11*4(sp) 17 | sw x12, 12*4(sp) 18 | sw x13, 13*4(sp) 19 | sw x14, 14*4(sp) 20 | sw x15, 15*4(sp) 21 | sw x16, 16*4(sp) 22 | sw x17, 17*4(sp) 23 | sw x18, 18*4(sp) 24 | sw x19, 19*4(sp) 25 | sw x20, 20*4(sp) 26 | sw x21, 21*4(sp) 27 | sw x22, 22*4(sp) 28 | sw x23, 23*4(sp) 29 | sw x24, 24*4(sp) 30 | sw x25, 25*4(sp) 31 | sw x26, 26*4(sp) 32 | sw x27, 27*4(sp) 33 | sw x28, 28*4(sp) 34 | sw x29, 29*4(sp) 35 | sw x30, 30*4(sp) 36 | sw x31, 31*4(sp) 37 | call trap 38 | lw x1, 1*4(sp) 39 | lw x3, 3*4(sp) 40 | lw x4, 4*4(sp) 41 | lw x5, 5*4(sp) 42 | lw x6, 6*4(sp) 43 | lw x7, 7*4(sp) 44 | lw x8, 8*4(sp) 45 | lw x9, 9*4(sp) 46 | lw x10, 10*4(sp) 47 | lw x11, 11*4(sp) 48 | lw x12, 12*4(sp) 49 | lw x13, 13*4(sp) 50 | lw x14, 14*4(sp) 51 | lw x15, 15*4(sp) 52 | lw x16, 16*4(sp) 53 | lw x17, 17*4(sp) 54 | lw x18, 18*4(sp) 55 | lw x19, 19*4(sp) 56 | lw x20, 20*4(sp) 57 | lw x21, 21*4(sp) 58 | lw x22, 22*4(sp) 59 | lw x23, 23*4(sp) 60 | lw x24, 24*4(sp) 61 | lw x25, 25*4(sp) 62 | lw x26, 26*4(sp) 63 | lw x27, 27*4(sp) 64 | lw x28, 28*4(sp) 65 | lw x29, 29*4(sp) 66 | lw x30, 30*4(sp) 67 | lw x31, 31*4(sp) 68 | csrrw sp, mscratch, sp 69 | mret 70 | 71 | 72 | -------------------------------------------------------------------------------- /src/main/c/emulator/src/utils.S: -------------------------------------------------------------------------------- 1 | #include "riscv.h" 2 | /* 3 | 4 | .section .init 5 | .globl readMemory 6 | .type readMemory,@function 7 | readWord: 8 | csrr a4, mepc 9 | li a2, MSTATUS_MPRV 10 | csrs mstatus, a2 11 | li a3, emulationTrap 12 | csrw mepc, a3 13 | lw a0, 0(a0) 14 | li a3, trapEntry 15 | csrw mepc, a3 16 | csrc mstatus, a2 17 | 18 | writeWord: 19 | csrr a4, mepc 20 | li a2, MSTATUS_MPRV 21 | csrs mstatus, a2 22 | li a3, emulationTrap 23 | csrw mepc, a3 24 | sw a1, 0(a0) 25 | li a3, trapEntry 26 | csrw mepc, a3 27 | csrc mstatus, a2 28 | */ 29 | //Redirect trap to supervisor 30 | /* 31 | .section .init 32 | .globl emulationTrap 33 | .type emulationTrap,@function 34 | emulationTrap: 35 | li a0, MSTATUS_MPRV 36 | csrc mstatus, a0 37 | 38 | la sp, _sp 39 | csrw sepc, a4 40 | csrr a0, mcause 41 | csrw scause, a0 42 | csrr a0, mbadaddr 43 | csrw sbadaddr, a0 44 | 45 | call init 46 | mret 47 | */ 48 | -------------------------------------------------------------------------------- /src/main/c/murax/hello_world/src/gpio.h: -------------------------------------------------------------------------------- 1 | #ifndef GPIO_H_ 2 | #define GPIO_H_ 3 | 4 | 5 | typedef struct 6 | { 7 | volatile uint32_t INPUT; 8 | volatile uint32_t OUTPUT; 9 | volatile uint32_t OUTPUT_ENABLE; 10 | } Gpio_Reg; 11 | 12 | 13 | #endif /* GPIO_H_ */ 14 | 15 | 16 | -------------------------------------------------------------------------------- /src/main/c/murax/hello_world/src/interrupt.h: -------------------------------------------------------------------------------- 1 | #ifndef INTERRUPTCTRL_H_ 2 | #define INTERRUPTCTRL_H_ 3 | 4 | #include 5 | 6 | typedef struct 7 | { 8 | volatile uint32_t PENDINGS; 9 | volatile uint32_t MASKS; 10 | } InterruptCtrl_Reg; 11 | 12 | static void interruptCtrl_init(InterruptCtrl_Reg* reg){ 13 | reg->MASKS = 0; 14 | reg->PENDINGS = 0xFFFFFFFF; 15 | } 16 | 17 | #endif /* INTERRUPTCTRL_H_ */ 18 | -------------------------------------------------------------------------------- /src/main/c/murax/hello_world/src/main.c: -------------------------------------------------------------------------------- 1 | //#include "stddefs.h" 2 | #include 3 | 4 | #include "murax.h" 5 | 6 | void print(const char*str){ 7 | while(*str){ 8 | uart_write(UART,*str); 9 | str++; 10 | } 11 | } 12 | void println(const char*str){ 13 | print(str); 14 | uart_write(UART,'\n'); 15 | } 16 | 17 | void delay(uint32_t loops){ 18 | for(int i=0;iOUTPUT; 20 | } 21 | } 22 | 23 | void main() { 24 | GPIO_A->OUTPUT_ENABLE = 0x0000000F; 25 | GPIO_A->OUTPUT = 0x00000001; 26 | println("hello world arty a7 v1"); 27 | const int nleds = 4; 28 | const int nloops = 2000000; 29 | while(1){ 30 | for(unsigned int i=0;iOUTPUT = 1<OUTPUT = (1<<(nleds-1))>>i; 36 | delay(nloops); 37 | } 38 | } 39 | } 40 | 41 | void irqCallback(){ 42 | } 43 | -------------------------------------------------------------------------------- /src/main/c/murax/hello_world/src/murax.h: -------------------------------------------------------------------------------- 1 | #ifndef __MURAX_H__ 2 | #define __MURAX_H__ 3 | 4 | #include "timer.h" 5 | #include "prescaler.h" 6 | #include "interrupt.h" 7 | #include "gpio.h" 8 | #include "uart.h" 9 | 10 | #define GPIO_A ((Gpio_Reg*)(0xF0000000)) 11 | #define TIMER_PRESCALER ((Prescaler_Reg*)0xF0020000) 12 | #define TIMER_INTERRUPT ((InterruptCtrl_Reg*)0xF0020010) 13 | #define TIMER_A ((Timer_Reg*)0xF0020040) 14 | #define TIMER_B ((Timer_Reg*)0xF0020050) 15 | #define UART ((Uart_Reg*)(0xF0010000)) 16 | 17 | #endif /* __MURAX_H__ */ 18 | -------------------------------------------------------------------------------- /src/main/c/murax/hello_world/src/prescaler.h: -------------------------------------------------------------------------------- 1 | #ifndef PRESCALERCTRL_H_ 2 | #define PRESCALERCTRL_H_ 3 | 4 | #include 5 | 6 | 7 | typedef struct 8 | { 9 | volatile uint32_t LIMIT; 10 | } Prescaler_Reg; 11 | 12 | static void prescaler_init(Prescaler_Reg* reg){ 13 | 14 | } 15 | 16 | #endif /* PRESCALERCTRL_H_ */ 17 | -------------------------------------------------------------------------------- /src/main/c/murax/hello_world/src/timer.h: -------------------------------------------------------------------------------- 1 | #ifndef TIMERCTRL_H_ 2 | #define TIMERCTRL_H_ 3 | 4 | #include 5 | 6 | 7 | typedef struct 8 | { 9 | volatile uint32_t CLEARS_TICKS; 10 | volatile uint32_t LIMIT; 11 | volatile uint32_t VALUE; 12 | } Timer_Reg; 13 | 14 | static void timer_init(Timer_Reg *reg){ 15 | reg->CLEARS_TICKS = 0; 16 | reg->VALUE = 0; 17 | } 18 | 19 | 20 | #endif /* TIMERCTRL_H_ */ 21 | -------------------------------------------------------------------------------- /src/main/c/murax/hello_world/src/uart.h: -------------------------------------------------------------------------------- 1 | #ifndef UART_H_ 2 | #define UART_H_ 3 | 4 | 5 | typedef struct 6 | { 7 | volatile uint32_t DATA; 8 | volatile uint32_t STATUS; 9 | volatile uint32_t CLOCK_DIVIDER; 10 | volatile uint32_t FRAME_CONFIG; 11 | } Uart_Reg; 12 | 13 | enum UartParity {NONE = 0,EVEN = 1,ODD = 2}; 14 | enum UartStop {ONE = 0,TWO = 1}; 15 | 16 | typedef struct { 17 | uint32_t dataLength; 18 | enum UartParity parity; 19 | enum UartStop stop; 20 | uint32_t clockDivider; 21 | } Uart_Config; 22 | 23 | static uint32_t uart_writeAvailability(Uart_Reg *reg){ 24 | return (reg->STATUS >> 16) & 0xFF; 25 | } 26 | static uint32_t uart_readOccupancy(Uart_Reg *reg){ 27 | return reg->STATUS >> 24; 28 | } 29 | 30 | static void uart_write(Uart_Reg *reg, uint32_t data){ 31 | while(uart_writeAvailability(reg) == 0); 32 | reg->DATA = data; 33 | } 34 | 35 | static void uart_applyConfig(Uart_Reg *reg, Uart_Config *config){ 36 | reg->CLOCK_DIVIDER = config->clockDivider; 37 | reg->FRAME_CONFIG = ((config->dataLength-1) << 0) | (config->parity << 8) | (config->stop << 16); 38 | } 39 | 40 | #endif /* UART_H_ */ 41 | 42 | 43 | -------------------------------------------------------------------------------- /src/main/c/murax/xipBootloader/.gitignore: -------------------------------------------------------------------------------- 1 | *.elf 2 | *.map 3 | *.d 4 | *.asm 5 | *.o -------------------------------------------------------------------------------- /src/main/c/murax/xipBootloader/crt.S: -------------------------------------------------------------------------------- 1 | #define CTRL_BASE 0xF001F000 2 | #define XIP_BASE 0xE0040000 3 | #define CTRL_DATA 0x00 4 | #define CTRL_STATUS 0x04 5 | #define CTRL_MODE 0x08 6 | #define CTRL_RATE 0x20 7 | #define CTRL_SS_SETUP 0x24 8 | #define CTRL_SS_HOLD 0x28 9 | #define CTRL_SS_DISABLE 0x2C 10 | 11 | #define CTRL_XIP_CONFIG 0x40 12 | #define CTRL_XIP_MODE 0x44 13 | 14 | .global crtStart 15 | .global main 16 | 17 | #define CTRL x31 18 | 19 | crtStart: 20 | li x31, CTRL_BASE 21 | sw x0, CTRL_MODE(CTRL) 22 | li t0, 2 23 | sw t0, CTRL_RATE(CTRL) 24 | li t0, 4 25 | sw t0, CTRL_SS_SETUP(CTRL) 26 | sw t0, CTRL_SS_HOLD(CTRL) 27 | sw t0, CTRL_SS_DISABLE(CTRL) 28 | 29 | 30 | li a0, 0x880 31 | call spiWrite 32 | li a0, 0x181 33 | call spiWrite 34 | li a0, 0x183 35 | call spiWrite 36 | li a0, 0x800 37 | call spiWrite 38 | 39 | 40 | li t0, 0x00FF010B 41 | sw t0, CTRL_XIP_MODE(CTRL) 42 | li t0, 0x1 43 | sw t0, CTRL_XIP_CONFIG(CTRL) 44 | li t0, XIP_BASE 45 | lw t1, (t0) 46 | li t2, 0xFFFFFFFF 47 | xor t3,t1,t2 48 | beqz t3,retry 49 | //if we are here we have read a value from flash which is not all ones 50 | lw t2, (t0) 51 | xor t3,t1,t2 52 | bnez t3,retry 53 | lw t2, (t0) 54 | xor t3,t1,t2 55 | bnez t3,retry 56 | //if we are here we have read the same value 3 times, so flash seems good, lets's jump 57 | jr t0 58 | 59 | retry: 60 | li a0, 0x800 61 | call spiWrite 62 | li t1,100000 63 | loop: 64 | addi t1,t1,-1 65 | bnez t1, loop 66 | j crtStart 67 | 68 | spiWrite: 69 | sw a0,CTRL_DATA(CTRL) 70 | spiWrite_wait: 71 | lw t0,CTRL_STATUS(CTRL) 72 | slli t0,t0,0x10 73 | beqz t0,spiWrite_wait 74 | ret 75 | -------------------------------------------------------------------------------- /src/main/c/murax/xipBootloader/crt.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/SpinalHDL/VexRiscv/79e6a600bd7fdae275bc893fda317bd6a27df762/src/main/c/murax/xipBootloader/crt.bin -------------------------------------------------------------------------------- /src/main/c/murax/xipBootloader/demo.S: -------------------------------------------------------------------------------- 1 | #define GPIO_BASE 0xF0000000 2 | #define GPIO_OUTPUT 4 3 | #define GPIO_OUTPUT_ENABLE 8 4 | 5 | 6 | .global crtStart 7 | 8 | crtStart: 9 | 10 | li x31, 0x12340000 // magic word expected by bootloader 11 | 12 | li x31, GPIO_BASE 13 | li t0, 0x000000FF 14 | sw t0, GPIO_OUTPUT_ENABLE(x31) 15 | 16 | li t0,1 17 | redo: 18 | sw t0, GPIO_OUTPUT(x31) 19 | li t1,10000 20 | slli t0,t0,1 21 | andi t0,t0,0xFF 22 | bnez t0, loop 23 | li t0,1 24 | loop: 25 | addi t1,t1,-1 26 | bnez t1, loop 27 | j redo 28 | -------------------------------------------------------------------------------- /src/main/ressource/hex/muraxDemo.elf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/SpinalHDL/VexRiscv/79e6a600bd7fdae275bc893fda317bd6a27df762/src/main/ressource/hex/muraxDemo.elf -------------------------------------------------------------------------------- /src/main/scala/vexriscv/demo/WhiteboxPlugin.scala: -------------------------------------------------------------------------------- 1 | package vexriscv.demo 2 | 3 | import spinal.core._ 4 | import vexriscv.plugin.Plugin 5 | import vexriscv.{DecoderService, Stageable, VexRiscv} 6 | 7 | class WhiteboxPlugin extends Plugin[VexRiscv]{ 8 | override def build(pipeline: VexRiscv): Unit = { 9 | Component.current.afterElaboration { 10 | def export(name : String): Unit = out(Component.current.reflectBaseType(name)) 11 | export("IBusCachedPlugin_fetchPc_pc") 12 | } 13 | } 14 | } 15 | -------------------------------------------------------------------------------- /src/main/scala/vexriscv/plugin/DummyFencePlugin.scala: -------------------------------------------------------------------------------- 1 | package vexriscv.plugin 2 | 3 | import spinal.core._ 4 | import vexriscv.{VexRiscv, _} 5 | 6 | class DummyFencePlugin extends Plugin[VexRiscv]{ 7 | 8 | override def setup(pipeline: VexRiscv): Unit = { 9 | import Riscv._ 10 | import pipeline.config._ 11 | 12 | val decoderService = pipeline.service(classOf[DecoderService]) 13 | decoderService.add(FENCE_I, Nil) 14 | decoderService.add(FENCE, Nil) 15 | } 16 | 17 | override def build(pipeline: VexRiscv): Unit = { 18 | import pipeline._ 19 | import pipeline.config._ 20 | //Dummy 21 | } 22 | } 23 | -------------------------------------------------------------------------------- /src/main/scala/vexriscv/plugin/ExternalInterruptArrayPlugin.scala: -------------------------------------------------------------------------------- 1 | package vexriscv.plugin 2 | 3 | import spinal.core._ 4 | import vexriscv.VexRiscv 5 | 6 | class ExternalInterruptArrayPlugin(arrayWidth : Int = 32, 7 | machineMaskCsrId : Int = 0xBC0, 8 | machinePendingsCsrId : Int = 0xFC0, 9 | supervisorMaskCsrId : Int = 0x9C0, 10 | supervisorPendingsCsrId : Int = 0xDC0) extends Plugin[VexRiscv]{ 11 | var externalInterruptArray : Bits = null 12 | 13 | override def setup(pipeline: VexRiscv): Unit = { 14 | externalInterruptArray = in(Bits(arrayWidth bits)).setName("externalInterruptArray") 15 | } 16 | 17 | override def build(pipeline: VexRiscv): Unit = { 18 | val csr = pipeline.service(classOf[CsrPlugin]) 19 | val externalInterruptArrayBuffer = RegNext(externalInterruptArray) 20 | def gen(maskCsrId : Int, pendingsCsrId : Int, interruptPin : Bool) = new Area { 21 | val mask = Reg(Bits(arrayWidth bits)) init(0) 22 | val pendings = mask & externalInterruptArrayBuffer 23 | interruptPin.setAsDirectionLess() := pendings.orR 24 | csr.rw(maskCsrId, mask) 25 | csr.r(pendingsCsrId, pendings) 26 | } 27 | gen(machineMaskCsrId, machinePendingsCsrId, csr.externalInterrupt) 28 | if(csr.config.supervisorGen) gen(supervisorMaskCsrId, supervisorPendingsCsrId, csr.externalInterruptS) 29 | } 30 | } 31 | -------------------------------------------------------------------------------- /src/main/scala/vexriscv/plugin/HaltOnExceptionPlugin.scala: -------------------------------------------------------------------------------- 1 | 2 | package vexriscv.plugin 3 | 4 | import spinal.core._ 5 | import spinal.lib._ 6 | import vexriscv._ 7 | import vexriscv.Riscv._ 8 | 9 | import scala.collection.mutable.ArrayBuffer 10 | import scala.collection.mutable 11 | 12 | 13 | class HaltOnExceptionPlugin() extends Plugin[VexRiscv] with ExceptionService { 14 | def xlen = 32 15 | 16 | //Mannage ExceptionService calls 17 | val exceptionPortsInfos = ArrayBuffer[ExceptionPortInfo]() 18 | def exceptionCodeWidth = 4 19 | override def newExceptionPort(stage : Stage, priority : Int = 0, codeWidth : Int = 4) = { 20 | val interface = Flow(ExceptionCause(4)) 21 | exceptionPortsInfos += ExceptionPortInfo(interface,stage,priority, codeWidth) 22 | interface 23 | } 24 | override def isExceptionPending(stage : Stage): Bool = False 25 | 26 | 27 | override def build(pipeline: VexRiscv): Unit = { 28 | import pipeline._ 29 | import pipeline.config._ 30 | stages.head.insert(FORMAL_HALT) := False 31 | stages.foreach(stage => { 32 | val stagePorts = exceptionPortsInfos.filter(_.stage == stage) 33 | if(stagePorts.nonEmpty) { 34 | when(stagePorts.map(info => info.port.valid).orR) { 35 | stage.output(FORMAL_HALT) := True 36 | stage.arbitration.haltItself := True 37 | } 38 | for(stage <- stages){ 39 | stage.output(FORMAL_HALT) clearWhen(stage.arbitration.isFlushed) 40 | } 41 | } 42 | }) 43 | } 44 | } 45 | -------------------------------------------------------------------------------- /src/main/scala/vexriscv/plugin/HazardPessimisticPlugin.scala: -------------------------------------------------------------------------------- 1 | package vexriscv.plugin 2 | 3 | import vexriscv._ 4 | import spinal.core._ 5 | import spinal.lib._ 6 | 7 | 8 | class HazardPessimisticPlugin() extends Plugin[VexRiscv] { 9 | import Riscv._ 10 | 11 | override def setup(pipeline: VexRiscv): Unit = { 12 | import pipeline.config._ 13 | val decoderService = pipeline.service(classOf[DecoderService]) 14 | decoderService.addDefault(HAS_SIDE_EFFECT, False) 15 | } 16 | 17 | override def build(pipeline: VexRiscv): Unit = { 18 | import pipeline._ 19 | import pipeline.config._ 20 | 21 | val writesInPipeline = stages.dropWhile(_ != execute).map(s => s.arbitration.isValid && s.input(REGFILE_WRITE_VALID)) :+ RegNext(stages.last.arbitration.isValid && stages.last.input(REGFILE_WRITE_VALID)) 22 | decode.arbitration.haltByOther.setWhen(decode.arbitration.isValid && writesInPipeline.orR) 23 | } 24 | } 25 | -------------------------------------------------------------------------------- /src/main/scala/vexriscv/plugin/NoPipeliningPlugin.scala: -------------------------------------------------------------------------------- 1 | package vexriscv.plugin 2 | 3 | import spinal.core._ 4 | import spinal.lib._ 5 | import vexriscv._ 6 | 7 | 8 | class NoPipeliningPlugin() extends Plugin[VexRiscv] { 9 | 10 | override def setup(pipeline: VexRiscv): Unit = { 11 | import pipeline.config._ 12 | val decoderService = pipeline.service(classOf[DecoderService]) 13 | decoderService.addDefault(HAS_SIDE_EFFECT, False) 14 | } 15 | 16 | override def build(pipeline: VexRiscv): Unit = { 17 | import pipeline._ 18 | import pipeline.config._ 19 | 20 | val writesInPipeline = stages.dropWhile(_ != execute).map(s => s.arbitration.isValid && s.input(REGFILE_WRITE_VALID)) :+ RegNext(stages.last.arbitration.isValid && stages.last.input(REGFILE_WRITE_VALID)) 21 | decode.arbitration.haltByOther.setWhen(stagesFromExecute.map(_.arbitration.isValid).orR) 22 | } 23 | } 24 | -------------------------------------------------------------------------------- /src/main/scala/vexriscv/plugin/Plugin.scala: -------------------------------------------------------------------------------- 1 | package vexriscv.plugin 2 | 3 | import vexriscv.{Pipeline, Stage} 4 | import spinal.core.{Area, Nameable} 5 | 6 | /** 7 | * Created by PIC32F_USER on 03/03/2017. 8 | */ 9 | trait Plugin[T <: Pipeline] extends Nameable{ 10 | var pipeline : T = null.asInstanceOf[T] 11 | setName(this.getClass.getSimpleName.replace("$","")) 12 | 13 | // Used to setup things with other plugins 14 | def setup(pipeline: T) : Unit = {} 15 | 16 | //Used to flush out the required hardware (called after setup) 17 | def build(pipeline: T) : Unit 18 | 19 | implicit class implicitsStage(stage: Stage){ 20 | def plug[T <: Area](area : T) : T = {area.setCompositeName(stage,getName()).reflectNames();area} 21 | } 22 | implicit class implicitsPipeline(stage: Pipeline){ 23 | def plug[T <: Area](area : T) = {area.setName(getName()).reflectNames();area} 24 | } 25 | } 26 | -------------------------------------------------------------------------------- /src/main/scala/vexriscv/plugin/SingleInstructionLimiterPlugin.scala: -------------------------------------------------------------------------------- 1 | package vexriscv.plugin 2 | 3 | import vexriscv._ 4 | import spinal.core._ 5 | import spinal.lib._ 6 | 7 | 8 | class SingleInstructionLimiterPlugin() extends Plugin[VexRiscv] { 9 | override def build(pipeline: VexRiscv): Unit = { 10 | import pipeline._ 11 | import pipeline.config._ 12 | val fetcher = pipeline.service(classOf[IBusFetcher]) 13 | when(fetcher.incoming() || List(decode,execute,memory,writeBack).map(_.arbitration.isValid).orR) { 14 | fetcher.haltIt() 15 | } 16 | } 17 | } 18 | -------------------------------------------------------------------------------- /src/main/scala/vexriscv/plugin/StaticMemoryTranslatorPlugin.scala: -------------------------------------------------------------------------------- 1 | package vexriscv.plugin 2 | 3 | import vexriscv.{VexRiscv, _} 4 | import spinal.core._ 5 | import spinal.lib._ 6 | 7 | import scala.collection.mutable.ArrayBuffer 8 | case class StaticMemoryTranslatorPort(bus : MemoryTranslatorBus, priority : Int) 9 | 10 | class StaticMemoryTranslatorPlugin(ioRange : UInt => Bool) extends Plugin[VexRiscv] with MemoryTranslator { 11 | val portsInfo = ArrayBuffer[StaticMemoryTranslatorPort]() 12 | 13 | override def newTranslationPort(priority : Int,args : Any): MemoryTranslatorBus = { 14 | val port = StaticMemoryTranslatorPort(MemoryTranslatorBus(MemoryTranslatorBusParameter(wayCount = 0)),priority) 15 | portsInfo += port 16 | port.bus 17 | } 18 | 19 | override def setup(pipeline: VexRiscv): Unit = { 20 | } 21 | 22 | override def build(pipeline: VexRiscv): Unit = { 23 | import pipeline._ 24 | import pipeline.config._ 25 | import Riscv._ 26 | 27 | val core = pipeline plug new Area { 28 | val ports = for ((port, portId) <- portsInfo.zipWithIndex) yield new Area { 29 | port.bus.rsp.physicalAddress := port.bus.cmd.last.virtualAddress 30 | port.bus.rsp.allowRead := True 31 | port.bus.rsp.allowWrite := True 32 | port.bus.rsp.allowExecute := True 33 | port.bus.rsp.isIoAccess := ioRange(port.bus.rsp.physicalAddress) 34 | port.bus.rsp.isPaging := False 35 | port.bus.rsp.exception := False 36 | port.bus.rsp.refilling := False 37 | port.bus.busy := False 38 | } 39 | } 40 | } 41 | } 42 | -------------------------------------------------------------------------------- /src/main/scala/vexriscv/plugin/YamlPlugin.scala: -------------------------------------------------------------------------------- 1 | package vexriscv.plugin 2 | 3 | import java.util 4 | 5 | import vexriscv.{ReportService, VexRiscv} 6 | import org.yaml.snakeyaml.{DumperOptions, Yaml} 7 | 8 | 9 | /** 10 | * Created by spinalvm on 09.06.17. 11 | */ 12 | class YamlPlugin(path : String) extends Plugin[VexRiscv] with ReportService{ 13 | 14 | val content = new util.HashMap[String, Object]() 15 | 16 | def add(that : (String,Object)) : Unit = content.put(that._1,that._2) 17 | 18 | override def setup(pipeline: VexRiscv): Unit = { 19 | 20 | } 21 | 22 | override def build(pipeline: VexRiscv): Unit = { 23 | val options = new DumperOptions() 24 | options.setWidth(50) 25 | options.setIndent(4) 26 | options.setCanonical(true) 27 | options.setDefaultFlowStyle(DumperOptions.FlowStyle.BLOCK) 28 | 29 | val yaml = new Yaml() 30 | yaml.dump(content, new java.io.FileWriter(path)) 31 | } 32 | } 33 | -------------------------------------------------------------------------------- /src/test/cpp/briey/installs.txt: -------------------------------------------------------------------------------- 1 | sudo apt-get install libYAML-dev 2 | 3 | 4 | sudo apt-get update 5 | sudo apt-get install build-essential software-properties-common -y 6 | sudo add-apt-repository ppa:ubuntu-toolchain-r/test -y 7 | sudo apt-get update 8 | sudo apt-get install gcc-6 g++-6 -y 9 | sudo update-alternatives --install /usr/bin/gcc gcc /usr/bin/gcc-6 60 --slave /usr/bin/g++ g++ /usr/bin/g++-6 10 | 11 | 12 | wget -O boost_1_64_0.tar.gz http://sourceforge.net/projects/boost/files/boost/1.64.0/boost_1_64_0.tar.gz/download 13 | tar xzvf boost_1_64_0.tar.gz 14 | cd boost_1_64_0/ 15 | ./bootstrap.sh --prefix=/usr/local 16 | ./b2 17 | sudo ./b2 install 18 | 19 | 20 | 21 | echo "using gcc : 6.3 : /usr/bin/g++-6 ; " >> tools/build/src/user-config.jam 22 | bjam --toolset=gcc-6 23 | -------------------------------------------------------------------------------- /src/test/cpp/briey/jtag.gtkw: -------------------------------------------------------------------------------- 1 | [*] 2 | [*] GTKWave Analyzer v3.3.58 (w)1999-2014 BSI 3 | [*] Fri Jun 9 08:05:42 2017 4 | [*] 5 | [dumpfile] "/home/spinalvm/Spinal/VexRiscv/src/test/cpp/briey/Briey.vcd" 6 | [dumpfile_mtime] "Fri Jun 9 08:05:37 2017" 7 | [dumpfile_size] 2070466159 8 | [savefile] "/home/spinalvm/Spinal/VexRiscv/src/test/cpp/briey/jtag.gtkw" 9 | [timestart] 51980000000 10 | [size] 1776 953 11 | [pos] -1 -353 12 | *-33.000000 62611680000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 13 | [treeopen] TOP. 14 | [treeopen] TOP.Briey. 15 | [treeopen] TOP.Briey.axi_jtagCtrl. 16 | [sst_width] 288 17 | [signals_width] 302 18 | [sst_expanded] 1 19 | [sst_vpaned_height] 503 20 | @28 21 | TOP.io_jtag_tck 22 | TOP.io_jtag_tdi 23 | TOP.io_jtag_tdo 24 | TOP.io_jtag_tms 25 | @22 26 | TOP.Briey.axi_jtagCtrl.jtagBridge_1.jtag_tap_fsm_state[3:0] 27 | TOP.Briey.axi_core_cpu.debug_bus_cmd_payload_address[7:0] 28 | TOP.Briey.axi_core_cpu.debug_bus_cmd_payload_data[31:0] 29 | @29 30 | TOP.Briey.axi_core_cpu.debug_bus_cmd_payload_wr 31 | @28 32 | TOP.Briey.axi_core_cpu.debug_bus_cmd_ready 33 | TOP.Briey.axi_core_cpu.debug_bus_cmd_valid 34 | @22 35 | TOP.Briey.axi_core_cpu.debug_bus_rsp_data[31:0] 36 | @28 37 | TOP.Briey.axi_core_cpu.DebugPlugin_haltIt 38 | TOP.Briey.axi_core_cpu.DebugPlugin_haltedByBreak 39 | [pattern_trace] 1 40 | [pattern_trace] 0 41 | -------------------------------------------------------------------------------- /src/test/cpp/briey/makefile: -------------------------------------------------------------------------------- 1 | DEBUG?=no 2 | TRACE?=no 3 | TRACE_INSTRUCTION?=no 4 | TRACE_REG?=no 5 | PRINT_PERF?=no 6 | VGA?=yes 7 | TRACE_START=0 8 | ADDCFLAGS += -CFLAGS -pthread 9 | ADDCFLAGS += -CFLAGS -lSDL2 10 | ADDCFLAGS += -LDFLAGS -lSDL2 11 | 12 | 13 | 14 | ifeq ($(TRACE),yes) 15 | VERILATOR_ARGS += --trace 16 | ADDCFLAGS += -CFLAGS -DTRACE --trace-fst 17 | endif 18 | ifeq ($(DEBUG),yes) 19 | ADDCFLAGS += -CFLAGS "-g3 -O0" 20 | endif 21 | ifneq ($(DEBUG),yes) 22 | ADDCFLAGS += -CFLAGS "-O3" 23 | endif 24 | ifeq ($(PRINT_PERF),yes) 25 | ADDCFLAGS += -CFLAGS -DPRINT_PERF 26 | endif 27 | 28 | ifeq ($(VGA),yes) 29 | ADDCFLAGS += -CFLAGS -DVGA 30 | endif 31 | ifeq ($(TRACE_INSTRUCTION),yes) 32 | ADDCFLAGS += -CFLAGS -DTRACE_INSTRUCTION 33 | endif 34 | 35 | ifeq ($(TRACE_REG),yes) 36 | ADDCFLAGS += -CFLAGS -DTRACE_REG 37 | endif 38 | 39 | ADDCFLAGS += -CFLAGS -DTRACE_START=${TRACE_START} 40 | 41 | 42 | 43 | all: clean compile 44 | 45 | run: compile 46 | ./obj_dir/VBriey 47 | 48 | verilate: ../../../../Briey.v 49 | rm -f Briey.v*.bin 50 | cp ../../../../Briey.v*.bin . | true 51 | verilator -cc ../../../../Briey.v ${ADDCFLAGS} --gdbbt ${VERILATOR_ARGS} -Wno-WIDTH -Wno-UNOPTFLAT --x-assign unique --exe main.cpp 52 | 53 | compile: verilate 54 | make -j -C obj_dir/ -f VBriey.mk VBriey 55 | 56 | clean: 57 | rm -f Briey.v*.bin 58 | rm -rf obj_dir 59 | 60 | -------------------------------------------------------------------------------- /src/test/cpp/briey/wip.gtkw: -------------------------------------------------------------------------------- 1 | [*] 2 | [*] GTKWave Analyzer v3.3.58 (w)1999-2014 BSI 3 | [*] Sun Jul 9 22:38:21 2017 4 | [*] 5 | [dumpfile] "/home/spinalvm/Spinal/VexRiscv/src/test/cpp/briey/Briey.vcd" 6 | [dumpfile_mtime] "Sun Jul 9 22:38:03 2017" 7 | [dumpfile_size] 1880556694 8 | [savefile] "/home/spinalvm/Spinal/VexRiscv/src/test/cpp/briey/wip.gtkw" 9 | [timestart] 225385490000 10 | [size] 1776 953 11 | [pos] -775 -1 12 | *-24.000000 225374620001 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 13 | [treeopen] TOP. 14 | [treeopen] TOP.Briey. 15 | [treeopen] TOP.Briey.axi_vgaCtrl. 16 | [sst_width] 358 17 | [signals_width] 150 18 | [sst_expanded] 1 19 | [sst_vpaned_height] 279 20 | @28 21 | TOP.Briey.axi_vgaCtrl.vga_ctrl.io_frameStart 22 | TOP.Briey.axi_vgaCtrl.vga_ctrl.io_pixels_ready 23 | TOP.Briey.axi_vgaCtrl.vga_ctrl.io_pixels_valid 24 | TOP.Briey.axi_vgaCtrl.vga_ctrl.io_softReset 25 | TOP.Briey.axi_vgaCtrl.vga_ctrl.io_vgaClk 26 | TOP.Briey.axi_vgaCtrl.vga_ctrl.io_vga_colorEn 27 | @29 28 | TOP.Briey.axi_vgaCtrl.vga_run 29 | [pattern_trace] 1 30 | [pattern_trace] 0 31 | -------------------------------------------------------------------------------- /src/test/cpp/custom/atomic/build/atomic.elf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/SpinalHDL/VexRiscv/79e6a600bd7fdae275bc893fda317bd6a27df762/src/test/cpp/custom/atomic/build/atomic.elf -------------------------------------------------------------------------------- /src/test/cpp/custom/atomic/build/atomic.map: -------------------------------------------------------------------------------- 1 | 2 | Memory Configuration 3 | 4 | Name Origin Length Attributes 5 | onChipRam 0x0000000000000000 0x0000000000002000 w !xr 6 | *default* 0x0000000000000000 0xffffffffffffffff 7 | 8 | Linker script and memory map 9 | 10 | LOAD build/src/crt.o 11 | LOAD /opt/riscv/bin/../lib/gcc/riscv64-unknown-elf/7.1.1/libgcc.a 12 | START GROUP 13 | LOAD /opt/riscv/bin/../lib/gcc/riscv64-unknown-elf/7.1.1/../../../../riscv64-unknown-elf/lib/libc.a 14 | LOAD /opt/riscv/bin/../lib/gcc/riscv64-unknown-elf/7.1.1/../../../../riscv64-unknown-elf/lib/libgloss.a 15 | END GROUP 16 | LOAD /opt/riscv/bin/../lib/gcc/riscv64-unknown-elf/7.1.1/libgcc.a 17 | 0x0000000000000000 . = 0x0 18 | 19 | .crt_section 0x0000000000000000 0x38c 20 | 0x0000000000000000 . = ALIGN (0x4) 21 | *crt.o(.text) 22 | .text 0x0000000000000000 0x38c build/src/crt.o 23 | 0x0000000000000020 trap_entry 24 | 0x000000000000004c _start 25 | OUTPUT(build/atomic.elf elf32-littleriscv) 26 | 27 | .data 0x000000000000038c 0x0 28 | .data 0x000000000000038c 0x0 build/src/crt.o 29 | 30 | .bss 0x000000000000038c 0x0 31 | .bss 0x000000000000038c 0x0 build/src/crt.o 32 | -------------------------------------------------------------------------------- /src/test/cpp/custom/atomic/src/ld: -------------------------------------------------------------------------------- 1 | OUTPUT_ARCH( "riscv" ) 2 | 3 | MEMORY { 4 | onChipRam (W!RX)/*(RX)*/ : ORIGIN = 0x00000000, LENGTH = 8K 5 | } 6 | 7 | SECTIONS 8 | { 9 | . = 0x000; 10 | 11 | .crt_section : 12 | { 13 | . = ALIGN(4); 14 | *crt.o(.text) 15 | } > onChipRam 16 | 17 | } 18 | -------------------------------------------------------------------------------- /src/test/cpp/custom/custom_csr/build/custom_csr.elf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/SpinalHDL/VexRiscv/79e6a600bd7fdae275bc893fda317bd6a27df762/src/test/cpp/custom/custom_csr/build/custom_csr.elf -------------------------------------------------------------------------------- /src/test/cpp/custom/custom_csr/build/custom_csr.hex: -------------------------------------------------------------------------------- 1 | :10000000130E1000F32040B0732140B0F32140B034 2 | :100010006348110663C62106130E2000B7C05D00B9 3 | :100020009380A098739040B0732140B0634A11044C 4 | :10003000130E3000F32050B0732150B0F32150B0B4 5 | :1000400063D02004635E3102130E4000739060B0F1 6 | :10005000F32040B01301001063F42002130E50008F 7 | :10006000F32070B0F32040B03701004013010110BD 8 | :10007000B701004063F6200063E430006F00000128 9 | :10008000370110F0130141F22320C101370110F0B4 10 | :10009000130101F2232001001300000013000000EF 11 | :1000A0001300000013000000130000001300000004 12 | :00000001FF 13 | -------------------------------------------------------------------------------- /src/test/cpp/custom/custom_csr/build/custom_csr.map: -------------------------------------------------------------------------------- 1 | 2 | Memory Configuration 3 | 4 | Name Origin Length Attributes 5 | onChipRam 0x0000000000000000 0x0000000000002000 w !xr 6 | *default* 0x0000000000000000 0xffffffffffffffff 7 | 8 | Linker script and memory map 9 | 10 | LOAD build/src/crt.o 11 | LOAD /opt/riscv/bin/../lib/gcc/riscv64-unknown-elf/7.2.0/rv32i/ilp32/libgcc.a 12 | START GROUP 13 | LOAD /opt/riscv/bin/../lib/gcc/riscv64-unknown-elf/7.2.0/../../../../riscv64-unknown-elf/lib/rv32i/ilp32/libc.a 14 | LOAD /opt/riscv/bin/../lib/gcc/riscv64-unknown-elf/7.2.0/../../../../riscv64-unknown-elf/lib/rv32i/ilp32/libgloss.a 15 | END GROUP 16 | LOAD /opt/riscv/bin/../lib/gcc/riscv64-unknown-elf/7.2.0/rv32i/ilp32/libgcc.a 17 | 0x0000000000000000 . = 0x0 18 | 19 | .crt_section 0x0000000000000000 0xb0 20 | 0x0000000000000000 . = ALIGN (0x4) 21 | *crt.o(.text) 22 | .text 0x0000000000000000 0xb0 build/src/crt.o 23 | 0x0000000000000000 _start 24 | OUTPUT(build/custom_csr.elf elf32-littleriscv) 25 | 26 | .data 0x00000000000000b0 0x0 27 | .data 0x00000000000000b0 0x0 build/src/crt.o 28 | 29 | .bss 0x00000000000000b0 0x0 30 | .bss 0x00000000000000b0 0x0 build/src/crt.o 31 | -------------------------------------------------------------------------------- /src/test/cpp/custom/custom_csr/build/custom_csr.v: -------------------------------------------------------------------------------- 1 | @00000000 2 | 13 0E 10 00 F3 20 40 B0 73 21 40 B0 F3 21 40 B0 3 | 63 48 11 06 63 C6 21 06 13 0E 20 00 B7 C0 5D 00 4 | 93 80 A0 98 73 90 40 B0 73 21 40 B0 63 4A 11 04 5 | 13 0E 30 00 F3 20 50 B0 73 21 50 B0 F3 21 50 B0 6 | 63 D0 20 04 63 5E 31 02 13 0E 40 00 73 90 60 B0 7 | F3 20 40 B0 13 01 00 10 63 F4 20 02 13 0E 50 00 8 | F3 20 70 B0 F3 20 40 B0 37 01 00 40 13 01 01 10 9 | B7 01 00 40 63 F6 20 00 63 E4 30 00 6F 00 00 01 10 | 37 01 10 F0 13 01 41 F2 23 20 C1 01 37 01 10 F0 11 | 13 01 01 F2 23 20 01 00 13 00 00 00 13 00 00 00 12 | 13 00 00 00 13 00 00 00 13 00 00 00 13 00 00 00 13 | -------------------------------------------------------------------------------- /src/test/cpp/custom/custom_csr/src/crt.S: -------------------------------------------------------------------------------- 1 | .globl _start 2 | _start: 3 | 4 | //Test 1 5 | li x28, 1 6 | csrr x1, 0xB04 7 | csrr x2, 0xB04 8 | csrr x3, 0xB04 9 | blt x2, x1, fail 10 | blt x3, x2, fail 11 | 12 | 13 | //Test 2 14 | li x28, 2 15 | li x1, 6142346 16 | csrw 0xB04, x1 17 | csrr x2, 0xB04 18 | blt x2, x1, fail 19 | 20 | 21 | //Test 3 22 | li x28, 3 23 | csrr x1, 0xB05 24 | csrr x2, 0xB05 25 | csrr x3, 0xB05 26 | bge x1, x2, fail 27 | bge x2, x3, fail 28 | 29 | 30 | 31 | //Test 4 32 | li x28, 4 33 | csrw 0xB06, x1 34 | csrr x1, 0xB04 35 | li x2, 0x100 36 | bgeu x1, x2, fail 37 | 38 | //Test 5 39 | li x28, 5 40 | csrr x1, 0xB07 41 | csrr x1, 0xB04 42 | li x2, 0x40000100 43 | li x3, 0x40000000 44 | bgeu x1, x2, fail 45 | bltu x1, x3, fail 46 | 47 | j pass 48 | 49 | fail: //x28 => error code 50 | li x2, 0xF00FFF24 51 | sw x28, 0(x2) 52 | 53 | pass: 54 | li x2, 0xF00FFF20 55 | sw x0, 0(x2) 56 | 57 | 58 | 59 | nop 60 | nop 61 | nop 62 | nop 63 | nop 64 | nop 65 | -------------------------------------------------------------------------------- /src/test/cpp/custom/custom_csr/src/ld: -------------------------------------------------------------------------------- 1 | OUTPUT_ARCH( "riscv" ) 2 | 3 | MEMORY { 4 | onChipRam (W!RX)/*(RX)*/ : ORIGIN = 0x00000000, LENGTH = 8K 5 | } 6 | 7 | SECTIONS 8 | { 9 | . = 0x000; 10 | 11 | .crt_section : 12 | { 13 | . = ALIGN(4); 14 | *crt.o(.text) 15 | } > onChipRam 16 | 17 | } 18 | -------------------------------------------------------------------------------- /src/test/cpp/custom/simd_add/build/custom_simd_add.elf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/SpinalHDL/VexRiscv/79e6a600bd7fdae275bc893fda317bd6a27df762/src/test/cpp/custom/simd_add/build/custom_simd_add.elf -------------------------------------------------------------------------------- /src/test/cpp/custom/simd_add/build/custom_simd_add.hex: -------------------------------------------------------------------------------- 1 | :10000000130E1000B3000006639C0008130E2000BE 2 | :100010009300000013010000B380200663920008E3 3 | :10002000130E3000B700020193804030130100002E 4 | :10003000B381200663961106130E400037120603A3 5 | :100040001302C290B70002019380403037010402CE 6 | :1000500013018160B381200663944104130E5000A4 7 | :10006000370200FF130222109300F0FF3701010056 8 | :1000700013013120B381200663944102130E600006 9 | :1000800093026000930010001301200093013000E0 10 | :10009000B3802006B3803006639450006F000001E7 11 | :1000A000370110F0130141F22320C101370110F094 12 | :1000B000130101F2232001001300000013000000CF 13 | :1000C00013000000130000001300000013000000E4 14 | :00000001FF 15 | -------------------------------------------------------------------------------- /src/test/cpp/custom/simd_add/build/custom_simd_add.map: -------------------------------------------------------------------------------- 1 | 2 | Memory Configuration 3 | 4 | Name Origin Length Attributes 5 | onChipRam 0x0000000000000000 0x0000000000002000 w !xr 6 | *default* 0x0000000000000000 0xffffffffffffffff 7 | 8 | Linker script and memory map 9 | 10 | LOAD build/src/crt.o 11 | LOAD /opt/riscv/bin/../lib/gcc/riscv64-unknown-elf/7.2.0/rv32i/ilp32/libgcc.a 12 | START GROUP 13 | LOAD /opt/riscv/bin/../lib/gcc/riscv64-unknown-elf/7.2.0/../../../../riscv64-unknown-elf/lib/rv32i/ilp32/libc.a 14 | LOAD /opt/riscv/bin/../lib/gcc/riscv64-unknown-elf/7.2.0/../../../../riscv64-unknown-elf/lib/rv32i/ilp32/libgloss.a 15 | END GROUP 16 | LOAD /opt/riscv/bin/../lib/gcc/riscv64-unknown-elf/7.2.0/rv32i/ilp32/libgcc.a 17 | 0x0000000000000000 . = 0x0 18 | 19 | .crt_section 0x0000000000000000 0xd0 20 | 0x0000000000000000 . = ALIGN (0x4) 21 | *crt.o(.text) 22 | .text 0x0000000000000000 0xd0 build/src/crt.o 23 | 0x0000000000000000 _start 24 | OUTPUT(build/custom_simd_add.elf elf32-littleriscv) 25 | 26 | .data 0x00000000000000d0 0x0 27 | .data 0x00000000000000d0 0x0 build/src/crt.o 28 | 29 | .bss 0x00000000000000d0 0x0 30 | .bss 0x00000000000000d0 0x0 build/src/crt.o 31 | -------------------------------------------------------------------------------- /src/test/cpp/custom/simd_add/build/custom_simd_add.v: -------------------------------------------------------------------------------- 1 | @00000000 2 | 13 0E 10 00 B3 00 00 06 63 9C 00 08 13 0E 20 00 3 | 93 00 00 00 13 01 00 00 B3 80 20 06 63 92 00 08 4 | 13 0E 30 00 B7 00 02 01 93 80 40 30 13 01 00 00 5 | B3 81 20 06 63 96 11 06 13 0E 40 00 37 12 06 03 6 | 13 02 C2 90 B7 00 02 01 93 80 40 30 37 01 04 02 7 | 13 01 81 60 B3 81 20 06 63 94 41 04 13 0E 50 00 8 | 37 02 00 FF 13 02 22 10 93 00 F0 FF 37 01 01 00 9 | 13 01 31 20 B3 81 20 06 63 94 41 02 13 0E 60 00 10 | 93 02 60 00 93 00 10 00 13 01 20 00 93 01 30 00 11 | B3 80 20 06 B3 80 30 06 63 94 50 00 6F 00 00 01 12 | 37 01 10 F0 13 01 41 F2 23 20 C1 01 37 01 10 F0 13 | 13 01 01 F2 23 20 01 00 13 00 00 00 13 00 00 00 14 | 13 00 00 00 13 00 00 00 13 00 00 00 13 00 00 00 15 | -------------------------------------------------------------------------------- /src/test/cpp/custom/simd_add/src/crt.S: -------------------------------------------------------------------------------- 1 | .globl _start 2 | _start: 3 | 4 | #define r_type_insn(_f7, _rs2, _rs1, _f3, _rd, _opc) \ 5 | .word (((_f7) << 25) | ((_rs2) << 20) | ((_rs1) << 15) | ((_f3) << 12) | ((_rd) << 7) | ((_opc) << 0)) 6 | 7 | #define SIMD_ADD(_rd, _rs1, _rs2 ) \ 8 | r_type_insn(0b0000011, _rs2, _rs1, 0b000, _rd, 0b0110011) 9 | 10 | //Test 1 11 | li x28, 1 12 | SIMD_ADD(1, 0, 0) 13 | bne x1, x0, fail 14 | 15 | //Test 2 16 | li x28, 2 17 | li x1, 0x00000000 18 | li x2, 0x00000000 19 | SIMD_ADD(1, 1, 2) 20 | bne x1, x0, fail 21 | 22 | //Test 3 23 | li x28, 3 24 | li x1, 0x01020304 25 | li x2, 0x00000000 26 | SIMD_ADD(3, 1, 2) 27 | bne x3, x1, fail 28 | 29 | //Test 4 30 | li x28, 4 31 | li x4, 0x0306090C 32 | li x1, 0x01020304 33 | li x2, 0x02040608 34 | SIMD_ADD(3, 1, 2) 35 | bne x3, x4, fail 36 | 37 | //Test 5 38 | li x28, 5 39 | li x4, 0xFF000102 40 | li x1, 0xFFFFFFFF 41 | li x2, 0x00010203 42 | SIMD_ADD(3, 1, 2) 43 | bne x3, x4, fail 44 | 45 | //Test 5 46 | li x28, 6 47 | li x5, 0x00000006 48 | li x1, 0x00000001 49 | li x2, 0x00000002 50 | li x3, 0x00000003 51 | SIMD_ADD(1, 1, 2) 52 | SIMD_ADD(1, 1, 3) 53 | bne x1, x5, fail 54 | 55 | j pass 56 | 57 | fail: //x28 => error code 58 | li x2, 0xF00FFF24 59 | sw x28, 0(x2) 60 | 61 | pass: 62 | li x2, 0xF00FFF20 63 | sw x0, 0(x2) 64 | 65 | 66 | 67 | nop 68 | nop 69 | nop 70 | nop 71 | nop 72 | nop 73 | -------------------------------------------------------------------------------- /src/test/cpp/custom/simd_add/src/ld: -------------------------------------------------------------------------------- 1 | OUTPUT_ARCH( "riscv" ) 2 | 3 | MEMORY { 4 | onChipRam (W!RX)/*(RX)*/ : ORIGIN = 0x80000000, LENGTH = 8K 5 | } 6 | 7 | SECTIONS 8 | { 9 | .crt_section : 10 | { 11 | . = ALIGN(4); 12 | *crt.o(.text) 13 | } > onChipRam 14 | 15 | } 16 | -------------------------------------------------------------------------------- /src/test/cpp/fpu/math/.gitignore: -------------------------------------------------------------------------------- 1 | *.so 2 | *.a 3 | -------------------------------------------------------------------------------- /src/test/cpp/fpu/math/libcode.version: -------------------------------------------------------------------------------- 1 | CODEABI_1.0 { 2 | global: FpuMath_*; 3 | local: *; 4 | } -------------------------------------------------------------------------------- /src/test/cpp/murax/makefile: -------------------------------------------------------------------------------- 1 | DEBUG?=no 2 | TRACE?=no 3 | PRINT_PERF?=no 4 | TRACE_START=0 5 | ADDCFLAGS += -CFLAGS -pthread -LDFLAGS -pthread 6 | 7 | 8 | ifeq ($(TRACE),yes) 9 | VERILATOR_ARGS += --trace 10 | ADDCFLAGS += -CFLAGS -DTRACE --trace-fst 11 | endif 12 | ifeq ($(DEBUG),yes) 13 | ADDCFLAGS += -CFLAGS "-g3 -O0" 14 | endif 15 | ifneq ($(DEBUG),yes) 16 | ADDCFLAGS += -CFLAGS "-O3" 17 | endif 18 | ifeq ($(PRINT_PERF),yes) 19 | ADDCFLAGS += -CFLAGS -DPRINT_PERF 20 | endif 21 | 22 | ADDCFLAGS += -CFLAGS -DTRACE_START=${TRACE_START} 23 | 24 | 25 | 26 | all: clean compile 27 | 28 | run: compile 29 | ./obj_dir/VMurax 30 | 31 | verilate: ../../../../Murax.v 32 | rm -f Murax.v*.bin 33 | cp ../../../../Murax.v*.bin . | true 34 | verilator -I../../../.. -cc ../../../../Murax.v ${ADDCFLAGS} --gdbbt ${VERILATOR_ARGS} -Wno-WIDTH -Wno-UNOPTFLAT --x-assign unique --exe main.cpp 35 | 36 | compile: verilate 37 | make -j -C obj_dir/ -f VMurax.mk VMurax 38 | 39 | clean: 40 | rm -rf obj_dir 41 | rm -f Murax.v*.bin 42 | 43 | -------------------------------------------------------------------------------- /src/test/cpp/raw/amo/.gitignore: -------------------------------------------------------------------------------- 1 | *.map 2 | *.v 3 | *.elf 4 | *.o -------------------------------------------------------------------------------- /src/test/cpp/raw/amo/makefile: -------------------------------------------------------------------------------- 1 | PROJ_NAME=amo 2 | 3 | ATOMIC=yes 4 | 5 | include ../common/asm.mk -------------------------------------------------------------------------------- /src/test/cpp/raw/amo/src/ld: -------------------------------------------------------------------------------- 1 | OUTPUT_ARCH( "riscv" ) 2 | 3 | MEMORY { 4 | onChipRam (W!RX)/*(RX)*/ : ORIGIN = 0x80000000, LENGTH = 128K 5 | } 6 | 7 | SECTIONS 8 | { 9 | 10 | .crt_section : 11 | { 12 | . = ALIGN(4); 13 | *crt.o(.text) 14 | } > onChipRam 15 | 16 | } 17 | -------------------------------------------------------------------------------- /src/test/cpp/raw/dcache/.gitignore: -------------------------------------------------------------------------------- 1 | *.map 2 | *.v 3 | *.elf 4 | *.o -------------------------------------------------------------------------------- /src/test/cpp/raw/dcache/build/dcache.hex: -------------------------------------------------------------------------------- 1 | :0200000480007A 2 | :10000000970000009380400B130E10009300100027 3 | :100010001301300093802000639E2008130E2000FF 4 | :10002000B70067F537F10F901303004093011000FC 5 | :1000300093022000B3036300B3817100B3827200A6 6 | :100040002320310023A00000032201006394420614 7 | :100050001303C3FF93800001130101010F5000003F 8 | :10006000E31603FC130E3000B70067F537F10F906D 9 | :10007000130300409301200093023000B303630098 10 | :10008000B3817100B382720003220100232031008A 11 | :1000900023A000000F50000003220100639C4200D7 12 | :1000A0001303C3FF9380000113010101E31403FC58 13 | :1000B0006F000001370110F0130141F22320C1014C 14 | :1000C000370110F0130101F223200100130000009A 15 | :1000D00013000000130000001300000013000000D4 16 | :0400E0001300000009 17 | :00000001FF 18 | -------------------------------------------------------------------------------- /src/test/cpp/raw/dcache/makefile: -------------------------------------------------------------------------------- 1 | PROJ_NAME=dcache 2 | 3 | include ../common/asm.mk -------------------------------------------------------------------------------- /src/test/cpp/raw/dcache/src/crt.S: -------------------------------------------------------------------------------- 1 | .globl _star 2 | #define TEST_ID x28 3 | 4 | _start: 5 | la x1, fail 6 | //csrw mtvec, x1 7 | 8 | test1: //Dummy test 9 | li TEST_ID, 1 10 | li x1, 1 11 | li x2, 3 12 | addi x1, x1, 2 13 | bne x1, x2, fail 14 | 15 | test2: //No invalidate, without load => new one 16 | li TEST_ID, 2 17 | li x1, 0xF5670000 18 | li x2, 0x900FF000 19 | li x6, 4096/4 20 | test2_repeat: 21 | la x3, 1 22 | la x5, 2 23 | add x7, x6, x6 24 | add x3, x3, x7 25 | add x5, x5, x7 26 | sw x3, 0(x2) 27 | sw x0, 0(x1) 28 | lw x4, 0(x2) 29 | bne x5,x4, fail 30 | addi x6, x6, -4 31 | addi x1, x1, 16 32 | addi x2, x2, 16 33 | .word 0x000500F // dcache flush 34 | bnez x6, test2_repeat 35 | 36 | test3: //with invalidate, with preload 37 | li TEST_ID, 3 38 | li x1, 0xF5670000 39 | li x2, 0x900FF000 40 | li x6, 4096/4 41 | test3_repeat: 42 | la x3, 2 43 | la x5, 3 44 | add x7, x6, x6 45 | add x3, x3, x7 46 | add x5, x5, x7 47 | lw x4, 0(x2) 48 | sw x3, 0(x2) 49 | sw x0, 0(x1) 50 | .word 0x000500F // dcache flush 51 | lw x4, 0(x2) 52 | bne x5,x4, fail 53 | addi x6, x6, -4 54 | addi x1, x1, 16 55 | addi x2, x2, 16 56 | bnez x6, test3_repeat 57 | 58 | 59 | 60 | j pass 61 | 62 | fail: 63 | li x2, 0xF00FFF24 64 | sw TEST_ID, 0(x2) 65 | 66 | pass: 67 | li x2, 0xF00FFF20 68 | sw x0, 0(x2) 69 | 70 | nop 71 | nop 72 | nop 73 | nop 74 | nop 75 | nop 76 | -------------------------------------------------------------------------------- /src/test/cpp/raw/dcache/src/ld: -------------------------------------------------------------------------------- 1 | OUTPUT_ARCH( "riscv" ) 2 | 3 | MEMORY { 4 | onChipRam (W!RX)/*(RX)*/ : ORIGIN = 0x80000000, LENGTH = 128K 5 | } 6 | 7 | SECTIONS 8 | { 9 | 10 | .crt_section : 11 | { 12 | . = ALIGN(4); 13 | *crt.o(.text) 14 | } > onChipRam 15 | 16 | } 17 | -------------------------------------------------------------------------------- /src/test/cpp/raw/deleg/.gitignore: -------------------------------------------------------------------------------- 1 | *.map 2 | *.v 3 | *.elf 4 | *.o -------------------------------------------------------------------------------- /src/test/cpp/raw/deleg/makefile: -------------------------------------------------------------------------------- 1 | PROJ_NAME=deleg 2 | 3 | include ../common/asm.mk -------------------------------------------------------------------------------- /src/test/cpp/raw/deleg/src/ld: -------------------------------------------------------------------------------- 1 | OUTPUT_ARCH( "riscv" ) 2 | 3 | MEMORY { 4 | onChipRam (W!RX)/*(RX)*/ : ORIGIN = 0x80000000, LENGTH = 128K 5 | } 6 | 7 | SECTIONS 8 | { 9 | 10 | .crt_section : 11 | { 12 | . = ALIGN(4); 13 | *crt.o(.text) 14 | } > onChipRam 15 | 16 | } 17 | -------------------------------------------------------------------------------- /src/test/cpp/raw/fpu/.gitignore: -------------------------------------------------------------------------------- 1 | *.map 2 | *.v 3 | *.elf 4 | *.o -------------------------------------------------------------------------------- /src/test/cpp/raw/fpu/makefile: -------------------------------------------------------------------------------- 1 | PROJ_NAME=fpu 2 | 3 | FLOATING=yes 4 | 5 | include ../common/asm.mk -------------------------------------------------------------------------------- /src/test/cpp/raw/fpu/src/ld: -------------------------------------------------------------------------------- 1 | OUTPUT_ARCH( "riscv" ) 2 | 3 | MEMORY { 4 | onChipRam (W!RX)/*(RX)*/ : ORIGIN = 0x80000000, LENGTH = 128K 5 | } 6 | 7 | SECTIONS 8 | { 9 | 10 | .crt_section : 11 | { 12 | . = ALIGN(4); 13 | *crt.o(.text) 14 | } > onChipRam 15 | 16 | } 17 | -------------------------------------------------------------------------------- /src/test/cpp/raw/icache/.gitignore: -------------------------------------------------------------------------------- 1 | *.map 2 | *.v 3 | *.elf 4 | *.o -------------------------------------------------------------------------------- /src/test/cpp/raw/icache/build/icache.hex: -------------------------------------------------------------------------------- 1 | :0200000480007A 2 | :10000000970000009380C004130E100093001000AE 3 | :100010001301300093802000639A2002130E200009 4 | :100020009300300117010000130101026F0040002E 5 | :10003000232011000F100000130A8000130AFAFF9A 6 | :10004000E31E0AFE6F0080006F000001370110F010 7 | :10005000130141F22320C101370110F0130101F215 8 | :100060002320010013000000130000001300000013 9 | :100070001300000013000000130000000000000047 10 | :04008000000000007C 11 | :00000001FF 12 | -------------------------------------------------------------------------------- /src/test/cpp/raw/icache/makefile: -------------------------------------------------------------------------------- 1 | PROJ_NAME=icache 2 | 3 | include ../common/asm.mk -------------------------------------------------------------------------------- /src/test/cpp/raw/icache/src/crt.S: -------------------------------------------------------------------------------- 1 | .globl _star 2 | #define TEST_ID x28 3 | 4 | #define delay \ 5 | li x20, 8; \ 6 | 1: addi x20, x20, -1; \ 7 | bne x20, x0, 1b; 8 | 9 | _start: 10 | la x1, fail 11 | // csrw mtvec, x1 12 | 13 | test1: //Dummy test 14 | li TEST_ID, 1 15 | li x1, 1 16 | li x2, 3 17 | addi x1, x1, 2 18 | bne x1, x2, fail 19 | 20 | test2: 21 | li TEST_ID, 2 22 | li x1, 0x13 //nop 23 | la x2, test2_trigger 24 | j test2_aligned 25 | .align(4) 26 | test2_aligned: 27 | sw x1, 0(x2) 28 | fence.i 29 | delay 30 | test2_trigger: 31 | j fail 32 | 33 | 34 | j pass 35 | 36 | fail: 37 | li x2, 0xF00FFF24 38 | sw TEST_ID, 0(x2) 39 | 40 | pass: 41 | li x2, 0xF00FFF20 42 | sw x0, 0(x2) 43 | 44 | nop 45 | nop 46 | nop 47 | nop 48 | nop 49 | nop 50 | -------------------------------------------------------------------------------- /src/test/cpp/raw/icache/src/ld: -------------------------------------------------------------------------------- 1 | OUTPUT_ARCH( "riscv" ) 2 | 3 | MEMORY { 4 | onChipRam (W!RX)/*(RX)*/ : ORIGIN = 0x80000000, LENGTH = 128K 5 | } 6 | 7 | SECTIONS 8 | { 9 | 10 | .crt_section : 11 | { 12 | . = ALIGN(4); 13 | *crt.o(.text) 14 | } > onChipRam 15 | 16 | } 17 | -------------------------------------------------------------------------------- /src/test/cpp/raw/lrsc/.gitignore: -------------------------------------------------------------------------------- 1 | *.map 2 | *.v 3 | *.elf 4 | *.o -------------------------------------------------------------------------------- /src/test/cpp/raw/lrsc/makefile: -------------------------------------------------------------------------------- 1 | PROJ_NAME=lrsc 2 | 3 | ATOMIC=yes 4 | 5 | include ../common/asm.mk -------------------------------------------------------------------------------- /src/test/cpp/raw/lrsc/src/ld: -------------------------------------------------------------------------------- 1 | OUTPUT_ARCH( "riscv" ) 2 | 3 | MEMORY { 4 | onChipRam (W!RX)/*(RX)*/ : ORIGIN = 0x80000000, LENGTH = 128K 5 | } 6 | 7 | SECTIONS 8 | { 9 | 10 | .crt_section : 11 | { 12 | . = ALIGN(4); 13 | *crt.o(.text) 14 | } > onChipRam 15 | 16 | } 17 | -------------------------------------------------------------------------------- /src/test/cpp/raw/machineCsr/.gitignore: -------------------------------------------------------------------------------- 1 | *.map 2 | *.v 3 | *.elf 4 | *.o -------------------------------------------------------------------------------- /src/test/cpp/raw/machineCsr/build/machineCsr.hex: -------------------------------------------------------------------------------- 1 | :0200000480007A 2 | :100000006F004009130000001300000013000000FF 3 | :100010001300000013000000130000001300000094 4 | :10002000732E2034631E0E00130FC0FFF32E103406 5 | :10003000B3FEEE01938E4E0073901E346F00C0012C 6 | :10004000B70E0080337FDE0163180F00F32E1034EB 7 | :10005000938E4E0073901E34B70E0080938E3E0038 8 | :100060006398CE01373C01F0930C000023209C01E3 9 | :10007000B70E0080938E7E006394CE0173504030A3 10 | :10008000B70E0080938EBE006394CE017350403053 11 | :1000900073002030130E100073000000130E2000B8 12 | :1000A0009302800073A0023093028000739042306C 13 | :1000B000373C01F0930C100023209C01130000003A 14 | :1000C00013000000130000001300000013000000E4 15 | :1000D00013000000130000001300000013000000D4 16 | :1000E000130000001300000013000000130E300086 17 | :1000F00093020008739042301300000013000000C8 18 | :1001000013000000130000001300000013000000A3 19 | :1001100013000000130E4000B7120000938202800B 20 | :100120007390423013000000130000001300000021 21 | :100130001300000013000000130000001300000073 22 | :10014000130E5000B70110F0938101F403A20100D7 23 | :1001500083A241001302F23F23A4410023A65100D1 24 | :100160001300000013000000130000001300000043 25 | :100170001300000013000000130000001300000033 26 | :100180001300000013000000130000001300000023 27 | :100190001300000013000000130E6000130200089B 28 | :1001A00073104230130E700073005010130E800055 29 | :1001B0009301100023A04100130E900023904100F2 30 | :1001C000130EA00003A20100130EB0000392010061 31 | :1001D000130EC000130ED000832000006F0020001B 32 | :1001E00083200000130EE00073002020130EF000A7 33 | :1001F000B70010F0938000F603A10000130E000179 34 | :1002000023A02000130E10016780000000000000F2 35 | :1002100000000000000000000000000000000000DE 36 | :0400000580000094E3 37 | :00000001FF 38 | -------------------------------------------------------------------------------- /src/test/cpp/raw/machineCsr/build/machineCsrCompressed.hex: -------------------------------------------------------------------------------- 1 | :0200000480007A 2 | :100000006F004009130000001300000013000000FF 3 | :100010001300000013000000130000001300000094 4 | :10002000732E2034631E0E00130FC0FFF32E103406 5 | :10003000B3FEEE01938E4E0073901E346F00C0012C 6 | :10004000B70E0080337FDE0163180F00F32E1034EB 7 | :10005000938E4E0073901E34B70E0080938E3E0038 8 | :100060006398CE01373C01F0930C000023209C01E3 9 | :10007000B70E0080938E7E006394CE0173504030A3 10 | :10008000B70E0080938EBE006394CE017350403053 11 | :1000900073002030130E100073000000130E2000B8 12 | :1000A0009302800073A0023093028000739042306C 13 | :1000B000373C01F0930C100023209C01130000003A 14 | :1000C00013000000130000001300000013000000E4 15 | :1000D00013000000130000001300000013000000D4 16 | :1000E000130000001300000013000000130E300086 17 | :1000F00093020008739042301300000013000000C8 18 | :1001000013000000130000001300000013000000A3 19 | :1001100013000000130E4000B7120000938202800B 20 | :100120007390423013000000130000001300000021 21 | :100130001300000013000000130000001300000073 22 | :10014000130E5000B70110F0938101F403A20100D7 23 | :1001500083A241001302F23F23A4410023A65100D1 24 | :100160001300000013000000130000001300000043 25 | :100170001300000013000000130000001300000033 26 | :100180001300000013000000130000001300000023 27 | :100190001300000013000000130E6000130200089B 28 | :1001A00073104230130E700073005010130E800055 29 | :1001B0009301100023A04100130E900023904100F2 30 | :1001C000130EA00003A20100130EB0000392010061 31 | :1001D000130EC000130ED000832000006F0020001B 32 | :1001E00083200000130EE00073002020130EF000A7 33 | :1001F000B70010F0938000F603A10000130E000179 34 | :1002000023A02000130E10016780000000000000F2 35 | :1002100000000000000000000000000000000000DE 36 | :0400000580000094E3 37 | :00000001FF 38 | -------------------------------------------------------------------------------- /src/test/cpp/raw/machineCsr/makefile: -------------------------------------------------------------------------------- 1 | ifeq ($(COMPRESSED),yes) 2 | PROJ_NAME=machineCsrCompressed 3 | CFLAGS=-DCOMPRESSED 4 | else 5 | PROJ_NAME=machineCsr 6 | endif 7 | 8 | 9 | 10 | 11 | include ../common/asm.mk -------------------------------------------------------------------------------- /src/test/cpp/raw/machineCsr/src/ld: -------------------------------------------------------------------------------- 1 | OUTPUT_ARCH( "riscv" ) 2 | 3 | MEMORY { 4 | onChipRam (W!RX)/*(RX)*/ : ORIGIN = 0x80000000, LENGTH = 128K 5 | } 6 | 7 | SECTIONS 8 | { 9 | 10 | .crt_section : 11 | { 12 | . = ALIGN(4); 13 | *crt.o(.text) 14 | } > onChipRam 15 | 16 | } 17 | -------------------------------------------------------------------------------- /src/test/cpp/raw/mmu/.gitignore: -------------------------------------------------------------------------------- 1 | *.map 2 | *.v 3 | *.elf 4 | *.o -------------------------------------------------------------------------------- /src/test/cpp/raw/mmu/makefile: -------------------------------------------------------------------------------- 1 | PROJ_NAME=mmu 2 | 3 | include ../common/asm.mk -------------------------------------------------------------------------------- /src/test/cpp/raw/mmu/src/ld: -------------------------------------------------------------------------------- 1 | OUTPUT_ARCH( "riscv" ) 2 | 3 | MEMORY { 4 | onChipRam (W!RX)/*(RX)*/ : ORIGIN = 0x80000000, LENGTH = 128K 5 | } 6 | 7 | SECTIONS 8 | { 9 | 10 | .crt_section : 11 | { 12 | . = ALIGN(4); 13 | *crt.o(.text) 14 | } > onChipRam 15 | 16 | } 17 | -------------------------------------------------------------------------------- /src/test/cpp/raw/pmp/build/pmp.elf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/SpinalHDL/VexRiscv/79e6a600bd7fdae275bc893fda317bd6a27df762/src/test/cpp/raw/pmp/build/pmp.elf -------------------------------------------------------------------------------- /src/test/cpp/raw/pmp/build/pmp.map: -------------------------------------------------------------------------------- 1 | 2 | Memory Configuration 3 | 4 | Name Origin Length Attributes 5 | onChipRam 0x0000000080000000 0x0000000000020000 w !xr 6 | *default* 0x0000000000000000 0xffffffffffffffff 7 | 8 | Linker script and memory map 9 | 10 | LOAD build/src/crt.o 11 | LOAD /opt/riscv_10092021/bin/../lib/gcc/riscv64-unknown-elf/8.3.0/rv32i/ilp32/libgcc.a 12 | START GROUP 13 | LOAD /opt/riscv_10092021/bin/../lib/gcc/riscv64-unknown-elf/8.3.0/../../../../riscv64-unknown-elf/lib/rv32i/ilp32/libc.a 14 | LOAD /opt/riscv_10092021/bin/../lib/gcc/riscv64-unknown-elf/8.3.0/../../../../riscv64-unknown-elf/lib/rv32i/ilp32/libgloss.a 15 | END GROUP 16 | LOAD /opt/riscv_10092021/bin/../lib/gcc/riscv64-unknown-elf/8.3.0/rv32i/ilp32/libgcc.a 17 | 18 | .crt_section 0x0000000080000000 0x364 19 | 0x0000000080000000 . = ALIGN (0x4) 20 | *crt.o(.text) 21 | .text 0x0000000080000000 0x364 build/src/crt.o 22 | 0x0000000080000000 _start 23 | 0x0000000080000014 trap 24 | OUTPUT(build/pmp.elf elf32-littleriscv) 25 | 26 | .data 0x0000000080000364 0x0 27 | .data 0x0000000080000364 0x0 build/src/crt.o 28 | 29 | .bss 0x0000000080000364 0x0 30 | .bss 0x0000000080000364 0x0 build/src/crt.o 31 | 32 | .riscv.attributes 33 | 0x0000000000000000 0x1a 34 | .riscv.attributes 35 | 0x0000000000000000 0x1a build/src/crt.o 36 | -------------------------------------------------------------------------------- /src/test/cpp/raw/pmp/makefile: -------------------------------------------------------------------------------- 1 | PROJ_NAME=pmp 2 | 3 | include ../common/asm.mk 4 | -------------------------------------------------------------------------------- /src/test/cpp/raw/pmp/src/ld: -------------------------------------------------------------------------------- 1 | OUTPUT_ARCH( "riscv" ) 2 | 3 | MEMORY { 4 | onChipRam (W!RX)/*(RX)*/ : ORIGIN = 0x80000000, LENGTH = 128K 5 | } 6 | 7 | SECTIONS 8 | { 9 | 10 | .crt_section : 11 | { 12 | . = ALIGN(4); 13 | *crt.o(.text) 14 | } > onChipRam 15 | 16 | } 17 | -------------------------------------------------------------------------------- /src/test/cpp/raw/privSpec/.gitignore: -------------------------------------------------------------------------------- 1 | *.map 2 | *.v 3 | *.elf 4 | *.o -------------------------------------------------------------------------------- /src/test/cpp/raw/privSpec/makefile: -------------------------------------------------------------------------------- 1 | PROJ_NAME=privSpec 2 | 3 | FLOATING=yes 4 | 5 | include ../common/asm.mk -------------------------------------------------------------------------------- /src/test/cpp/raw/privSpec/src/ld: -------------------------------------------------------------------------------- 1 | OUTPUT_ARCH( "riscv" ) 2 | 3 | MEMORY { 4 | onChipRam (W!RX)/*(RX)*/ : ORIGIN = 0x80000000, LENGTH = 128K 5 | } 6 | 7 | SECTIONS 8 | { 9 | 10 | .crt_section : 11 | { 12 | . = ALIGN(4); 13 | *crt.o(.text) 14 | } > onChipRam 15 | 16 | } 17 | -------------------------------------------------------------------------------- /src/test/cpp/raw/smp/.gitignore: -------------------------------------------------------------------------------- 1 | *.map 2 | *.v 3 | *.elf 4 | *.o 5 | *.hex 6 | !*.bin -------------------------------------------------------------------------------- /src/test/cpp/raw/smp/build/smp.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/SpinalHDL/VexRiscv/79e6a600bd7fdae275bc893fda317bd6a27df762/src/test/cpp/raw/smp/build/smp.bin -------------------------------------------------------------------------------- /src/test/cpp/raw/smp/makefile: -------------------------------------------------------------------------------- 1 | PROJ_NAME=smp 2 | 3 | ATOMIC=yes 4 | 5 | include ../common/asm.mk -------------------------------------------------------------------------------- /src/test/cpp/raw/smp/src/ld: -------------------------------------------------------------------------------- 1 | OUTPUT_ARCH( "riscv" ) 2 | 3 | MEMORY { 4 | onChipRam (W!RX)/*(RX)*/ : ORIGIN = 0x80000000, LENGTH = 128K 5 | } 6 | 7 | SECTIONS 8 | { 9 | 10 | .crt_section : 11 | { 12 | . = ALIGN(4); 13 | *crt.o(.text) 14 | } > onChipRam 15 | 16 | } 17 | -------------------------------------------------------------------------------- /src/test/cpp/regression/.gitignore: -------------------------------------------------------------------------------- 1 | *.regTraceRef 2 | /freertos.gtkw 3 | *.cproject 4 | -------------------------------------------------------------------------------- /src/test/cpp/regression/atomic.gtkw: -------------------------------------------------------------------------------- 1 | [*] 2 | [*] GTKWave Analyzer v3.3.58 (w)1999-2014 BSI 3 | [*] Thu Jan 4 16:18:18 2018 4 | [*] 5 | [dumpfile] "/home/spinalvm/hdl/VexRiscv/src/test/cpp/regression/atomic.vcd" 6 | [dumpfile_mtime] "Thu Jan 4 16:18:11 2018" 7 | [dumpfile_size] 19545269 8 | [savefile] "/home/spinalvm/hdl/VexRiscv/src/test/cpp/regression/atomic.gtkw" 9 | [timestart] 1478 10 | [size] 1784 950 11 | [pos] -1 -1 12 | *-7.000000 1726 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 13 | [treeopen] TOP. 14 | [treeopen] TOP.VexRiscv. 15 | [sst_width] 289 16 | [signals_width] 559 17 | [sst_expanded] 1 18 | [sst_vpaned_height] 191 19 | @22 20 | TOP.VexRiscv.writeBack_RegFilePlugin_regFileWrite_payload_address[4:0] 21 | TOP.VexRiscv.writeBack_RegFilePlugin_regFileWrite_payload_data[31:0] 22 | @28 23 | TOP.VexRiscv.writeBack_RegFilePlugin_regFileWrite_valid 24 | TOP.VexRiscv.dataCache_1.stageB_atomic_entriesHit 25 | @22 26 | TOP.VexRiscv.dataCache_1.stageB_atomic_entries_0_address[31:0] 27 | @28 28 | TOP.VexRiscv.dataCache_1.stageB_atomic_entries_0_size[1:0] 29 | TOP.VexRiscv.dataCache_1.stageB_atomic_entries_0_valid 30 | @22 31 | TOP.VexRiscv.dataCache_1.stageB_atomic_entries_1_address[31:0] 32 | @28 33 | TOP.VexRiscv.dataCache_1.stageB_atomic_entries_1_size[1:0] 34 | TOP.VexRiscv.dataCache_1.stageB_atomic_entries_1_valid 35 | @29 36 | [color] 1 37 | TOP.VexRiscv.writeBack_arbitration_isFiring 38 | [color] 1 39 | TOP.VexRiscv.writeBack_arbitration_isValid 40 | @23 41 | [color] 1 42 | TOP.VexRiscv.writeBack_PC[31:0] 43 | @28 44 | TOP.VexRiscv.CsrPlugin_mstatus_MIE 45 | TOP.VexRiscv.CsrPlugin_mstatus_MPIE 46 | TOP.VexRiscv.CsrPlugin_mstatus_MPP[1:0] 47 | @24 48 | TOP.VexRiscv.RegFilePlugin_regFile(28)[31:0] 49 | @22 50 | TOP.VexRiscv.CsrPlugin_mepc[31:0] 51 | [pattern_trace] 1 52 | [pattern_trace] 0 53 | -------------------------------------------------------------------------------- /src/test/cpp/regression/branch.gtkw: -------------------------------------------------------------------------------- 1 | [*] 2 | [*] GTKWave Analyzer v3.3.58 (w)1999-2014 BSI 3 | [*] Mon Mar 20 10:40:36 2017 4 | [*] 5 | [dumpfile] "/home/spinalvm/Spinal/VexRiscv/src/test/cpp/testA/dhrystoneO3M.vcd" 6 | [dumpfile_mtime] "Mon Mar 20 10:40:36 2017" 7 | [dumpfile_size] 1149914709 8 | [savefile] "/home/spinalvm/Spinal/VexRiscv/src/test/cpp/testA/branch.gtkw" 9 | [timestart] 68 10 | [size] 1776 953 11 | [pos] -775 -1 12 | *-4.000000 87 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 13 | [treeopen] TOP. 14 | [sst_width] 432 15 | [signals_width] 520 16 | [sst_expanded] 1 17 | [sst_vpaned_height] 279 18 | @28 19 | TOP.VexRiscv.execute_input_HISTORY_LINE_history[1:0] 20 | TOP.VexRiscv.fetch_HISTORY_LINE_history[1:0] 21 | TOP.VexRiscv.memory_input_HISTORY_LINE_history[1:0] 22 | TOP.VexRiscv.decode_arbitration_isValid 23 | TOP.VexRiscv.decode_arbitration_isFiring 24 | @22 25 | TOP.VexRiscv.decode_input_PC[31:0] 26 | @28 27 | TOP.VexRiscv.decode_input_HISTORY_LINE_history[1:0] 28 | @29 29 | TOP.VexRiscv.prefetch_PcManagerSimplePlugin_jump_pcLoad_valid 30 | [pattern_trace] 1 31 | [pattern_trace] 0 32 | -------------------------------------------------------------------------------- /src/test/cpp/regression/fail.gtkw: -------------------------------------------------------------------------------- 1 | [*] 2 | [*] GTKWave Analyzer v3.3.100 (w)1999-2019 BSI 3 | [*] Thu Apr 25 14:41:35 2019 4 | [*] 5 | [dumpfile] "/home/miaou/pro/VexRiscv/src/test/cpp/regression/C.SLLI.vcd" 6 | [dumpfile_mtime] "Thu Apr 25 14:39:03 2019" 7 | [dumpfile_size] 295925 8 | [savefile] "/home/miaou/pro/VexRiscv/src/test/cpp/regression/fail.gtkw" 9 | [timestart] 0 10 | [size] 1920 1030 11 | [pos] -458 -215 12 | *-2.000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 13 | [treeopen] TOP. 14 | [sst_width] 196 15 | [signals_width] 366 16 | [sst_expanded] 1 17 | [sst_vpaned_height] 299 18 | @28 19 | TOP.VexRiscv.lastStageIsValid 20 | TOP.VexRiscv.lastStageIsFiring 21 | @22 22 | TOP.VexRiscv.lastStageInstruction[31:0] 23 | TOP.VexRiscv.lastStagePc[31:0] 24 | TOP.VexRiscv.lastStageRegFileWrite_payload_address[4:0] 25 | TOP.VexRiscv.lastStageRegFileWrite_payload_data[31:0] 26 | @28 27 | TOP.VexRiscv.lastStageRegFileWrite_valid 28 | [pattern_trace] 1 29 | [pattern_trace] 0 30 | -------------------------------------------------------------------------------- /src/test/cpp/regression/prediction.gtkw: -------------------------------------------------------------------------------- 1 | [*] 2 | [*] GTKWave Analyzer v3.3.58 (w)1999-2014 BSI 3 | [*] Mon Jan 29 13:38:19 2018 4 | [*] 5 | [dumpfile] "/home/spinalvm/hdl/VexRiscv/src/test/cpp/regression/dhrystoneO3M.vcd" 6 | [dumpfile_mtime] "Mon Jan 29 13:37:19 2018" 7 | [dumpfile_size] 1215443558 8 | [savefile] "/home/spinalvm/hdl/VexRiscv/src/test/cpp/regression/prediction.gtkw" 9 | [timestart] 127017 10 | [size] 1784 950 11 | [pos] -383 -155 12 | *-3.000000 127032 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 13 | [treeopen] TOP. 14 | [sst_width] 400 15 | [signals_width] 583 16 | [sst_expanded] 1 17 | [sst_vpaned_height] 492 18 | @28 19 | TOP.VexRiscv.iBus_cmd_valid 20 | TOP.VexRiscv.decode_arbitration_flushAll 21 | TOP.VexRiscv.execute_arbitration_flushAll 22 | TOP.VexRiscv.fetch_arbitration_flushAll 23 | TOP.VexRiscv.memory_arbitration_flushAll 24 | TOP.VexRiscv.prefetch_arbitration_flushAll 25 | TOP.VexRiscv.writeBack_arbitration_flushAll 26 | TOP.VexRiscv.execute_BranchPlugin_predictionMissmatch 27 | TOP.VexRiscv.execute_PREDICTION2_confidence[1:0] 28 | @22 29 | TOP.VexRiscv.execute_PREDICTION2_source[18:0] 30 | TOP.VexRiscv.execute_PREDICTION2_target[31:0] 31 | @28 32 | TOP.VexRiscv.execute_PREDICTION_HIT2 33 | TOP.VexRiscv.execute_PREDICTION_WRITE_HAZARD2 34 | @23 35 | TOP.VexRiscv.execute_PC[31:0] 36 | @28 37 | TOP.VexRiscv.prefetch_PcManagerSimplePlugin_jump_pcLoad_valid 38 | @22 39 | TOP.VexRiscv.prefetch_PcManagerSimplePlugin_jump_pcLoad_payload[31:0] 40 | @29 41 | TOP.VexRiscv.execute_arbitration_isFiring 42 | [pattern_trace] 1 43 | [pattern_trace] 0 44 | -------------------------------------------------------------------------------- /src/test/cpp/regression/refDiff.gtkw: -------------------------------------------------------------------------------- 1 | [*] 2 | [*] GTKWave Analyzer v3.3.58 (w)1999-2014 BSI 3 | [*] Fri Mar 17 18:05:14 2017 4 | [*] 5 | [dumpfile] "/home/spinalvm/Spinal/VexRiscv/src/test/cpp/testA/DhrystoneRef.vcd" 6 | [dumpfile_mtime] "Fri Mar 17 18:03:52 2017" 7 | [dumpfile_size] 1483111421 8 | [savefile] "/home/spinalvm/Spinal/VexRiscv/src/test/cpp/testA/refDiff.gtkw" 9 | [timestart] 36700 10 | [size] 1774 451 11 | [pos] -775 -353 12 | *-2.000000 36713 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 13 | [treeopen] TOP. 14 | [treeopen] TOP.VexRiscv. 15 | [sst_width] 201 16 | [signals_width] 583 17 | [sst_expanded] 1 18 | [sst_vpaned_height] 68 19 | @22 20 | TOP.VexRiscv.writeBack_RegFilePlugin_regFileWrite_payload_address[4:0] 21 | @24 22 | TOP.VexRiscv.writeBack_RegFilePlugin_regFileWrite_payload_data[31:0] 23 | @28 24 | TOP.VexRiscv.writeBack_RegFilePlugin_regFileWrite_valid 25 | TOP.VexRiscv.writeBack_arbitration_isValid 26 | TOP.VexRiscv.clk 27 | @22 28 | TOP.VexRiscv.core.writeBack_inInst_payload_instruction[31:0] 29 | TOP.VexRiscv.core.writeBack_inInst_payload_pcPlus4[31:0] 30 | TOP.dCmd_payload_address[31:0] 31 | TOP.dCmd_payload_data[31:0] 32 | @28 33 | TOP.dCmd_payload_size[1:0] 34 | TOP.dCmd_payload_wr 35 | TOP.dCmd_ready 36 | TOP.dCmd_valid 37 | @25 38 | TOP.dRsp_data[31:0] 39 | [pattern_trace] 1 40 | [pattern_trace] 0 41 | -------------------------------------------------------------------------------- /src/test/java/vexriscv/ip/fpu/FpuMath.java: -------------------------------------------------------------------------------- 1 | package vexriscv.ip.fpu; 2 | 3 | import java.io.File; 4 | 5 | public class FpuMath { 6 | public native float addF32(float a, float b, int rounding); 7 | public native float mulF32(float a, float b, int rounding); 8 | public native int mulFlagF32(float a, float b, int rounding); 9 | public native float d2f(double a, int rounding); 10 | public native int d2fFlag(double a, int rounding); 11 | 12 | static{ 13 | System.load(new File("src/test/cpp/fpu/math/fpu_math.so").getAbsolutePath()); 14 | } 15 | } -------------------------------------------------------------------------------- /src/test/python/gcloud/.gitignore: -------------------------------------------------------------------------------- 1 | /gcloud.pyc 2 | *.tar.gz 3 | -------------------------------------------------------------------------------- /src/test/python/gcloud/makefile: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/SpinalHDL/VexRiscv/79e6a600bd7fdae275bc893fda317bd6a27df762/src/test/python/gcloud/makefile -------------------------------------------------------------------------------- /src/test/python/gcloud/remotePull.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python 2 | 3 | from gcloud import GCInstance 4 | 5 | gci = GCInstance("vexriscv") 6 | gci.create() 7 | gci.start() 8 | gci.remoteToLocal("run.txt","run.txt") 9 | gci.stop() 10 | gci.delete() 11 | -------------------------------------------------------------------------------- /src/test/python/gcloud/remoteTest.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python 2 | 3 | from os import system 4 | from sys import argv 5 | 6 | from gcloud import GCInstance 7 | 8 | gci = GCInstance("vexriscv") 9 | #gci.create("n1-standard-1") 10 | gci.create("n1-highcpu-8") 11 | gci.start() 12 | gci.stopHours(20) 13 | gci.stopScript("src/test/python/gcloud/stopScript.sh") 14 | 15 | gci.local("rm -rf archive.tar.gz; git ls-files -z | xargs -0 tar -czf archive.tar.gz") 16 | gci.localToRemote("archive.tar.gz", "") 17 | gci.local("cd ../SpinalHDL; rm -rf spinal.tar.gz; git ls-files -z | xargs -0 tar -czf spinal.tar.gz") 18 | gci.localToRemote("../SpinalHDL/spinal.tar.gz", "") 19 | gci.localToRemote("src/test/python/gcloud/run.sh", "") 20 | gci.remote("rm -rf run.txt; setsid nohup sh run.sh &> run.txt") 21 | 22 | #setsid nohup (sbt test;sudo poweroff) &> sbtTest.txt 23 | -------------------------------------------------------------------------------- /src/test/python/gcloud/run.sh: -------------------------------------------------------------------------------- 1 | rm -rf sbtTest.txt 2 | rm -rf VexRiscv 3 | rm -rf SpinalHDL 4 | #git clone https://github.com/SpinalHDL/SpinalHDL.git -b dev 5 | mkdir SpinalHDL 6 | tar -xzf spinal.tar.gz -C SpinalHDL 7 | mkdir VexRiscv 8 | tar -xzf archive.tar.gz -C VexRiscv 9 | cd VexRiscv 10 | sudo git init 11 | sudo git add * 12 | sudo git commit -m miaou 13 | export VEXRISCV_REGRESSION_CONFIG_COUNT=128 14 | export VEXRISCV_REGRESSION_FREERTOS_COUNT=30 15 | sbt test 16 | cd .. 17 | 18 | #sudo apt-get install mailutils + https://cloud.google.com/compute/docs/tutorials/sending-mail/using-mailgun 19 | echo "Miaou" | mail -s "VexRiscv cloud" charles.papon.90@gmail.com -A run.txt 20 | sleep 15 21 | 22 | sudo shutdown -P now 23 | 24 | 25 | -------------------------------------------------------------------------------- /src/test/python/gcloud/stopScript.sh: -------------------------------------------------------------------------------- 1 | #! /bin/bash 2 | 3 | echo "preempted :(" | mail -s "VexRiscv cloud" charles.papon.90@gmail.com -A /home/spinalvm/run.txt 4 | sleep 10 5 | -------------------------------------------------------------------------------- /src/test/python/gcloud/try.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python 2 | 3 | from os import system 4 | from sys import argv 5 | 6 | project = "ivory-infusion-209508" 7 | zone = "europe-west1-b" 8 | instance = "miaou" 9 | 10 | def local(cmd): 11 | print(cmd) 12 | system(cmd) 13 | 14 | def remote(cmd): 15 | cmd = 'gcloud compute --project "{}" ssh --zone "{}" "{}" -- "{}"'.format(project, zone, instance, cmd) 16 | print(cmd) 17 | system(cmd) 18 | 19 | def localToRemote(source, target): 20 | remote("rm -rf target") 21 | cmd = 'gcloud compute --project "{}" scp --zone "{}" {} {}:{}'.format(project, zone, source, instance, target) 22 | print(cmd) 23 | system(cmd) 24 | 25 | #local("sbt test &") 26 | local("python -c 'from os import system; system(\"(sbt test >> sbtTest.txt) &\")'") 27 | #python -c 'from os import system; system("sbt test")' & 28 | -------------------------------------------------------------------------------- /src/test/python/tool/.gitignore: -------------------------------------------------------------------------------- 1 | /disasm.s 2 | -------------------------------------------------------------------------------- /src/test/python/tool/hexToAsm.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python3 2 | 3 | from os import system 4 | from sys import argv 5 | 6 | with open("disasm.s", "w") as f: 7 | instr = int(argv[1], 16) 8 | print(".word 0x%04x" % (instr), file=f) 9 | 10 | system("riscv64-unknown-elf-gcc -c disasm.s") 11 | system("riscv64-unknown-elf-objdump -d -M numeric,no-aliases disasm.o") 12 | -------------------------------------------------------------------------------- /src/test/resources/.gitignore: -------------------------------------------------------------------------------- 1 | !bin 2 | -------------------------------------------------------------------------------- /src/test/resources/bin/.gitignore: -------------------------------------------------------------------------------- 1 | !*.bin 2 | -------------------------------------------------------------------------------- /src/test/resources/bin/coremark_rv32i.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/SpinalHDL/VexRiscv/79e6a600bd7fdae275bc893fda317bd6a27df762/src/test/resources/bin/coremark_rv32i.bin -------------------------------------------------------------------------------- /src/test/resources/bin/coremark_rv32ic.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/SpinalHDL/VexRiscv/79e6a600bd7fdae275bc893fda317bd6a27df762/src/test/resources/bin/coremark_rv32ic.bin -------------------------------------------------------------------------------- /src/test/resources/bin/coremark_rv32im.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/SpinalHDL/VexRiscv/79e6a600bd7fdae275bc893fda317bd6a27df762/src/test/resources/bin/coremark_rv32im.bin -------------------------------------------------------------------------------- /src/test/resources/bin/coremark_rv32imc.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/SpinalHDL/VexRiscv/79e6a600bd7fdae275bc893fda317bd6a27df762/src/test/resources/bin/coremark_rv32imc.bin -------------------------------------------------------------------------------- /src/test/resources/elf/uart.elf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/SpinalHDL/VexRiscv/79e6a600bd7fdae275bc893fda317bd6a27df762/src/test/resources/elf/uart.elf -------------------------------------------------------------------------------- /src/test/resources/hex/C.ADDI16SP.elf.hex: -------------------------------------------------------------------------------- 1 | :0200000480007A 2 | :1000000001000100010001000100010001000100E8 3 | :1000100001000100010001000100010001000100D8 4 | :1000200001000100010001000100010001000100C8 5 | :1000300001000100010001000100010001000100B8 6 | :1000400001000100010001000100010001000100A8 7 | :100050000100010001000100010001000100010098 8 | :100060000100010001000100010001000100010088 9 | :100070000100010001000100010001000100010078 10 | :100080000100010001000100010001000100010068 11 | :100090000100010001000100010001000100010058 12 | :1000A0000100010001000100010001000100010048 13 | :1000B0000100010001000100010001000100010038 14 | :1000C0000100010001000100010001000100010028 15 | :1000D0000100010001000100010001000100010018 16 | :1000E0000100010001000100010001000100971062 17 | :1000F0000000938020F1410123A020009710000010 18 | :10010000938080F0056123A0200097100000938069 19 | :10011000E0EF216123A0200097100000938040EFC2 20 | :100120007D6123A02000971000009380A0EE017154 21 | :1001300023A02000171500001305C5EC971500003B 22 | :10014000938545EE370610F01306C6F2630CB50032 23 | :10015000544514C2144514C2544114C2144114C26B 24 | :100160004105EDB7370510F0130505F22320050012 25 | :0201700000008D 26 | :10100000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF0 27 | :10101000FFFFFFFF000000000000000000000000D4 28 | :040000058000000077 29 | :00000001FF 30 | -------------------------------------------------------------------------------- /src/test/resources/hex/C.ADDI4SPN.elf.hex: -------------------------------------------------------------------------------- 1 | :0200000480007A 2 | :1000000001000100010001000100010001000100E8 3 | :1000100001000100010001000100010001000100D8 4 | :1000200001000100010001000100010001000100C8 5 | :1000300001000100010001000100010001000100B8 6 | :1000400001000100010001000100010001000100A8 7 | :100050000100010001000100010001000100010098 8 | :100060000100010001000100010001000100010088 9 | :100070000100010001000100010001000100010078 10 | :100080000100010001000100010001000100010068 11 | :100090000100010001000100010001000100010058 12 | :1000A0000100010001000100010001000100010048 13 | :1000B0000100010001000100010001000100010038 14 | :1000C0000100010001000100010001000100010028 15 | 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:1000200001000100010001000100010001000100C8 5 | :1000300001000100010001000100010001000100B8 6 | :1000400001000100010001000100010001000100A8 7 | :100050000100010001000100010001000100010098 8 | :100060000100010001000100010001000100010088 9 | :100070000100010001000100010001000100010078 10 | :100080000100010001000100010001000100010068 11 | :100090000100010001000100010001000100010058 12 | :1000A0000100010001000100010001000100010048 13 | :1000B0000100010001000100010001000100010038 14 | :1000C0000100010001000100010001000100010028 15 | :1000D0000100010001000100010001000100010018 16 | :1000E00001000100010001000100010001001711E1 17 | :1000F0000000130121F181479D8F89C7B7270100B7 18 | :100100009387B73A3EC0171100001301E1EF054491 19 | :10011000018C09C4372401001304B43A22C017111A 20 | :1001200000001301A1EEFD54858C89C4B7240100A1 21 | :100130009384B43A26C017110000130161EDB7850E 22 | :1001400000009385F5FF8D8D89C5B7250100938546 23 | :10015000B53A2EC0171100001301C1EB2166118EB4 24 | :1001600009C6372601001306B63A32C0171500003B 25 | :10017000130545E9971500009385C5EA370610F089 26 | :100180001306C6F2630CB500544514C2144514C2DC 27 | :10019000544114C2144114C24105EDB7370510F0A3 28 | :1001A000130505F2232005000000000000000000F8 29 | :0201B00000004D 30 | :10100000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF0 31 | :10101000FFFFFFFF000000000000000000000000D4 32 | :040000058000000077 33 | :00000001FF 34 | -------------------------------------------------------------------------------- /src/test/resources/hex/C.BNEZ.elf.hex: -------------------------------------------------------------------------------- 1 | :0200000480007A 2 | :1000000001000100010001000100010001000100E8 3 | :1000100001000100010001000100010001000100D8 4 | :1000200001000100010001000100010001000100C8 5 | :1000300001000100010001000100010001000100B8 6 | :1000400001000100010001000100010001000100A8 7 | :100050000100010001000100010001000100010098 8 | :100060000100010001000100010001000100010088 9 | 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-------------------------------------------------------------------------------- /src/test/resources/hex/C.J.elf.hex: -------------------------------------------------------------------------------- 1 | :0200000480007A 2 | :1000000001000100010001000100010001000100E8 3 | :1000100001000100010001000100010001000100D8 4 | :1000200001000100010001000100010001000100C8 5 | :1000300001000100010001000100010001000100B8 6 | :1000400001000100010001000100010001000100A8 7 | :100050000100010001000100010001000100010098 8 | :100060000100010001000100010001000100010088 9 | :100070000100010001000100010001000100010078 10 | :100080000100010001000100010001000100010068 11 | :100090000100010001000100010001000100010058 12 | :1000A0000100010001000100010001000100010048 13 | :1000B0000100010001000100010001000100010038 14 | :1000C0000100010001000100010001000100010028 15 | :1000D0000100010001000100010001000100010018 16 | :1000E00001000100010001000100010001001711E1 17 | :1000F0000000130121F1814529A0B7250100938556 18 | :10010000B53A2EC017110000130101F0054629A0D1 19 | :10011000372601001306B63A32C01711000013014A 20 | :10012000E1EEFD5629A0B72601009386B63A36C007 21 | :10013000171100001301C1ED378700001307F7FF07 22 | :1001400029A0372701001307B73A3AC0171100005A 23 | :10015000130141ECA16729A0B72701009387B73AA3 24 | :100160003EC0171500001305E5E9971500009385BB 25 | :1001700065EB370610F01306C6F2630CB500544564 26 | :1001800014C2144514C2544114C2144114C241058E 27 | :10019000EDB7370510F0130505F223200500000028 28 | :0201A00000005D 29 | :10100000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF0 30 | :10101000FFFFFFFF000000000000000000000000D4 31 | :040000058000000077 32 | :00000001FF 33 | -------------------------------------------------------------------------------- /src/test/resources/hex/C.JAL.elf.hex: -------------------------------------------------------------------------------- 1 | :0200000480007A 2 | :1000000001000100010001000100010001000100E8 3 | :1000100001000100010001000100010001000100D8 4 | :1000200001000100010001000100010001000100C8 5 | :1000300001000100010001000100010001000100B8 6 | :1000400001000100010001000100010001000100A8 7 | :100050000100010001000100010001000100010098 8 | :100060000100010001000100010001000100010088 9 | :100070000100010001000100010001000100010078 10 | :100080000100010001000100010001000100010068 11 | :100090000100010001000100010001000100010058 12 | :1000A0000100010001000100010001000100010048 13 | :1000B0000100010001000100010001000100010038 14 | :1000C0000100010001000100010001000100010028 15 | :1000D0000100010001000100010001000100010018 16 | :1000E00001000100010001000100010001001711E1 17 | :1000F0000000130121F101442920372401001304D9 18 | :10010000B43A22C017110000130101F085442920E0 19 | :10011000B72401009384B43A26C0171100001301DC 20 | :10012000E1EEFD552920B72501009385B53A2EC093 21 | :10013000171100001301C1ED378600001306F6FF0A 22 | :100140002920372601001306B63A32C017110000E5 23 | :10015000130141ECA1662920B72601009386B63A27 24 | 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/src/test/resources/ref/I-DELAY_SLOTS-01.reference_output: -------------------------------------------------------------------------------- 1 | 44444444333333332222222211111111 2 | 88888888777777776666666655555555 3 | -------------------------------------------------------------------------------- /src/test/resources/ref/I-EBREAK-01.reference_output: -------------------------------------------------------------------------------- 1 | 00000000000000001111111100000003 2 | -------------------------------------------------------------------------------- /src/test/resources/ref/I-ECALL-01.reference_output: -------------------------------------------------------------------------------- 1 | 0000000000000000111111110000000b 2 | -------------------------------------------------------------------------------- /src/test/resources/ref/I-ENDIANESS-01.reference_output: -------------------------------------------------------------------------------- 1 | 00000089000001230000456701234567 2 | 00000001000000230000004500000067 3 | -------------------------------------------------------------------------------- /src/test/resources/ref/I-FENCE.I-01.reference_output: -------------------------------------------------------------------------------- 1 | 001101b3000000420000001200000030 2 | -------------------------------------------------------------------------------- /src/test/resources/ref/I-IO.reference_output: -------------------------------------------------------------------------------- 1 | ffffffff000000010000000000000000 2 | 0000000100000001800000007fffffff 3 | 80000001800000000000000000000002 4 | fffffffe00000000ffffffffffffffff 5 | 7fffffff7fffffff7fffffff7ffffffe 6 | fffffffffffffffe7ffffffe80000000 7 | 7fffffff800000018000000080000000 8 | 0000abcd0000000100000000ffffffff 9 | 0000abd10000abd00000abcf0000abce 10 | 00000000000000000000abd30000abd2 11 | 36925814369258143692581400000000 12 | -------------------------------------------------------------------------------- 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00000001000000010000000180000000 8 | 00000000ffffffff0000000100000001 9 | 00000000000000010000000100000000 10 | 00000001000000000000000000000000 11 | 00000001000000000000000100000000 12 | -------------------------------------------------------------------------------- /src/test/resources/ref/I-SLTIU-01.reference_output: -------------------------------------------------------------------------------- 1 | 00000001000000010000000100000000 2 | 00000000000000010000000100000000 3 | 00000001000000000000000100000001 4 | 000000000000000000000000ffffffff 5 | 000000007fffffff0000000000000000 6 | 00000001000000000000000100000000 7 | 00000001000000000000000080000000 8 | 00000000000000010000000100000000 9 | 00000001000000010000000100000000 10 | 00000001000000000000000100000000 11 | 00000001000000000000000100000000 12 | -------------------------------------------------------------------------------- /src/test/resources/ref/I-SLTU-01.reference_output: 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-------------------------------------------------------------------------------- /src/test/resources/ref/I-SUB-01.reference_output: -------------------------------------------------------------------------------- 1 | 00000001ffffffff0000000000000000 2 | 00000001000000018000000080000001 3 | 80000001800000020000000200000000 4 | 00000000fffffffeffffffffffffffff 5 | 7fffffff7fffffff7fffffff80000000 6 | ffffffff00000000800000007ffffffe 7 | 800000017fffffff8000000080000000 8 | 0000abcd000000010000000000000001 9 | 0000abc90000abca0000abcb0000abcc 10 | 00000000000000000000abc70000abc8 11 | c96da7ecc96da7ec3692581400000000 12 | -------------------------------------------------------------------------------- /src/test/resources/ref/I-SW-01.reference_output: -------------------------------------------------------------------------------- 1 | f77788f855f5f666f33344f411f1f222 2 | 0fff00f0dd0d0eee0bbbcc0c99090aaa 3 | 765432109abcdef01122334400000000 4 | 25814963147258361472583689abcdef 5 | -------------------------------------------------------------------------------- /src/test/resources/ref/I-XOR-01.reference_output: -------------------------------------------------------------------------------- 1 | ffffffff000000010000000000000000 2 | 0000000100000001800000007fffffff 3 | 800000017ffffffefffffffe00000000 4 | 00000000fffffffeffffffffffffffff 5 | 7fffffff7fffffff7fffffff80000000 6 | ffffffff00000000800000007ffffffe 7 | 7fffffff800000018000000080000000 8 | abcdffff0000007f00000000ffffffff 9 | abcdffafabcdffa0abcdffbfabcdff80 10 | 0000000000000000abcdffababcdffa8 11 | 36925814369258143692581400000000 12 | -------------------------------------------------------------------------------- /src/test/resources/ref/I-XORI-01.reference_output: -------------------------------------------------------------------------------- 1 | ffffffff000007ff0000000100000000 2 | 0000000000000001fffff80000000000 3 | fffff80100000001fffffffe000007fe 4 | 00000000fffff800fffffffeffffffff 5 | 7ffffffe7fffffff000007ffffffffff 6 | 800007ff7fffffff800000007ffff800 7 | 7fffffff800007ff8000000180000000 8 | abcdff80abcdffff7ffff80080000000 9 | abcdffa8abcdffafabcdffa0abcdffbf 10 | 000000010000000000000000abcdffab 11 | 36925814369258143692581436925814 12 | -------------------------------------------------------------------------------- /src/test/resources/ref/MUL.reference_output: -------------------------------------------------------------------------------- 1 | 00000000000000000000000000000000 2 | ffffffff000000010000000000000000 3 | ffffffff00000000800000007fffffff 4 | 00000000800000008000000100000001 5 | 8000000000000001800000017fffffff 6 | 80000000800000008000000000000000 7 | ffffffffffffffffffffffff00000000 8 | ffffffffffffffffffffffffffffffff 9 | ffffffffffffffffffffffffffffffff 10 | ffffffffffffffffffffffffffffffff 11 | ffffffffffffffffffffffffffffffff 12 | ffffffffffffffffffffffffffffffff 13 | 0000000000000000ffffffffffffffff 14 | -------------------------------------------------------------------------------- /src/test/resources/ref/MULH.reference_output: -------------------------------------------------------------------------------- 1 | 00000000000000000000000000000000 2 | ffffffff000000000000000000000000 3 | ffffffff00000000ffffffff00000000 4 | 0000000000000000ffffffff00000000 5 | c00000003fffffffffffffff00000000 6 | c000000000000000ffffffff00000000 7 | ffffffffffffffffffffffff40000000 8 | ffffffffffffffffffffffffffffffff 9 | ffffffffffffffffffffffffffffffff 10 | ffffffffffffffffffffffffffffffff 11 | ffffffffffffffffffffffffffffffff 12 | ffffffffffffffffffffffffffffffff 13 | 0000000000000000ffffffffffffffff 14 | -------------------------------------------------------------------------------- /src/test/resources/ref/MULHSU.reference_output: -------------------------------------------------------------------------------- 1 | 00000000000000000000000000000000 2 | 00000000000000000000000000000000 3 | ffffffff000000000000000000000000 4 | 00000000ffffffffffffffffffffffff 5 | 3fffffff3fffffff7ffffffe00000000 6 | c000000080000000ffffffff00000000 7 | ffffffffffffffffffffffffc0000000 8 | ffffffffffffffffffffffffffffffff 9 | ffffffffffffffffffffffffffffffff 10 | ffffffffffffffffffffffffffffffff 11 | ffffffffffffffffffffffffffffffff 12 | ffffffffffffffffffffffffffffffff 13 | 0000000000000000ffffffffffffffff 14 | -------------------------------------------------------------------------------- /src/test/resources/ref/MULHU.reference_output: -------------------------------------------------------------------------------- 1 | 00000000000000000000000000000000 2 | 00000000000000000000000000000000 3 | 00000000000000000000000000000000 4 | 000000007fffffff7ffffffefffffffe 5 | 3fffffff3fffffff7ffffffe00000000 6 | 3fffffff7fffffff0000000000000000 7 | ffffffffffffffffffffffff40000000 8 | ffffffffffffffffffffffffffffffff 9 | ffffffffffffffffffffffffffffffff 10 | ffffffffffffffffffffffffffffffff 11 | ffffffffffffffffffffffffffffffff 12 | ffffffffffffffffffffffffffffffff 13 | 0000000000000000ffffffffffffffff 14 | -------------------------------------------------------------------------------- /src/test/resources/ref/REM.reference_output: -------------------------------------------------------------------------------- 1 | 00000000000000000000000000000000 2 | 00000000000000000000000100000000 3 | 00000000ffffffff0000000100000001 4 | 7fffffffffffffffffffffff00000000 5 | 7fffffff000000000000000000000000 6 | ffffffff000000000000000080000000 7 | ffffffffffffffffffffffff00000000 8 | ffffffffffffffffffffffffffffffff 9 | ffffffffffffffffffffffffffffffff 10 | ffffffffffffffffffffffffffffffff 11 | ffffffffffffffffffffffffffffffff 12 | ffffffffffffffffffffffffffffffff 13 | 0000000000000000ffffffffffffffff 14 | -------------------------------------------------------------------------------- /src/test/resources/ref/REMU.reference_output: -------------------------------------------------------------------------------- 1 | 00000000000000000000000000000000 2 | 00000001000000000000000100000000 3 | 00000000ffffffff0000000100000001 4 | 7fffffff7fffffff0000000100000000 5 | 7fffffff000000007fffffff00000000 6 | 00000001800000000000000080000000 7 | ffffffffffffffffffffffff00000000 8 | ffffffffffffffffffffffffffffffff 9 | ffffffffffffffffffffffffffffffff 10 | ffffffffffffffffffffffffffffffff 11 | ffffffffffffffffffffffffffffffff 12 | ffffffffffffffffffffffffffffffff 13 | 0000000000000000ffffffffffffffff 14 | -------------------------------------------------------------------------------- /src/test/scala/vexriscv/experimental/config.scala: -------------------------------------------------------------------------------- 1 | package vexriscv.experimental 2 | 3 | import spinal.core.SpinalVerilog 4 | import vexriscv.ip.InstructionCacheConfig 5 | import vexriscv.{VexRiscv, VexRiscvConfig, plugin} 6 | import vexriscv.plugin._ 7 | 8 | import scala.collection.mutable.ArrayBuffer 9 | 10 | object Presentation extends App{ 11 | 12 | val config = VexRiscvConfig() 13 | 14 | config.plugins ++= List( 15 | // new IBusSimplePlugin(resetVector = 0x80000000l), 16 | new DBusSimplePlugin, 17 | new CsrPlugin(CsrPluginConfig.smallest), 18 | new DecoderSimplePlugin, 19 | new RegFilePlugin(regFileReadyKind = plugin.SYNC), 20 | new IntAluPlugin, 21 | new SrcPlugin, 22 | new MulDivIterativePlugin( 23 | mulUnrollFactor = 4, 24 | divUnrollFactor = 1 25 | ), 26 | new FullBarrelShifterPlugin, 27 | new HazardSimplePlugin, 28 | new BranchPlugin( 29 | earlyBranch = false 30 | ), 31 | new YamlPlugin("cpu0.yaml") 32 | ) 33 | 34 | new VexRiscv(config) 35 | } 36 | 37 | -------------------------------------------------------------------------------- /src/test/scala/vexriscv/ip/fpu/Playground.scala: -------------------------------------------------------------------------------- 1 | package vexriscv.ip.fpu 2 | 3 | object MiaouDiv extends App{ 4 | val input = 2.5 5 | var output = 1/(input*0.95) 6 | 7 | def y = output 8 | def x = input 9 | 10 | for(i <- 0 until 10) { 11 | output = 2 * y - x * y * y 12 | println(output) 13 | } 14 | 15 | 16 | //output = x*output 17 | println(1/input) 18 | } 19 | 20 | object MiaouSqrt extends App{ 21 | val input = 2.0 22 | var output = 1/Math.sqrt(input*0.95) 23 | // def x = output 24 | // def y = input 25 | 26 | def y = output 27 | def x = input 28 | 29 | for(i <- 0 until 10) { 30 | output = y * (1.5 - x * y * y / 2) 31 | println(output) 32 | } 33 | 34 | output = x*output 35 | println(output) 36 | println(s"ref ${Math.sqrt(input)}") 37 | } 38 | 39 | 40 | object MiaouNan extends App{ 41 | println(Float.NaN + 3.0f) 42 | println(3.0f + Float.NaN ) 43 | println(0.0f*Float.PositiveInfinity ) 44 | println(1.0f/0.0f ) 45 | println(Float.MaxValue -1 ) 46 | println(Float.PositiveInfinity - Float.PositiveInfinity) 47 | } -------------------------------------------------------------------------------- /tools.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | install_verilator(){ 4 | sudo apt install -y git make autoconf g++ flex libfl-dev bison # First time prerequisites 5 | git clone https://github.com/verilator/verilator.git # Only first time 6 | unset VERILATOR_ROOT # For bash 7 | cd verilator 8 | git pull # Make sure we're up-to-date 9 | git checkout v4.216 10 | autoconf # Create ./configure script 11 | ./configure --prefix ~/tools 12 | make -j$(nproc) 13 | make install 14 | cd .. 15 | } 16 | 17 | install_ghdl(){ 18 | sudo apt install -y gnat-9 libgnat-9 zlib1g-dev libboost-dev 19 | git clone https://github.com/ghdl/ghdl ghdl-build && cd ghdl-build 20 | git reset --hard "0316f95368837dc163173e7ca52f37ecd8d3591d" 21 | mkdir build 22 | cd build 23 | ../configure --prefix=~/tools 24 | make -j$(nproc) 25 | make install 26 | cd .. 27 | } 28 | 29 | install_iverilog(){ 30 | sudo apt install -y gperf readline-common bison flex libfl-dev 31 | curl -fsSL https://github.com/steveicarus/iverilog/archive/v10_3.tar.gz | tar -xvz 32 | cd iverilog-10_3 33 | autoconf 34 | ./configure --prefix ~/tools 35 | make -j$(nproc) 36 | make install 37 | cd .. 38 | } 39 | 40 | install_cocotb(){ 41 | pip3 install --user cocotb 42 | sudo apt install -y git make gcc g++ swig python3-dev 43 | } 44 | 45 | purge_cocotb(){ 46 | # Force cocotb to compile VPI to avoid race condition when tests are start in parallel 47 | cd tester/src/test/python/spinal/Dummy 48 | make TOPLEVEL_LANG=verilog 49 | make TOPLEVEL_LANG=vhdl 50 | cd ../../../../../.. 51 | } 52 | 53 | install_packages(){ 54 | sudo apt install -y gnat-9 libgnat-9 zlib1g-dev libboost-dev 55 | } 56 | 57 | install_tools(){ 58 | install_verilator 59 | install_ghdl 60 | install_iverilog 61 | install_cocotb 62 | } 63 | --------------------------------------------------------------------------------