├── .github └── workflows │ └── scala.yml ├── .gitignore ├── .gitmodules ├── .travis.yml ├── LICENSE ├── README.md ├── assets ├── brieySoc.png └── fpuDesign.png ├── doc ├── diagram.drawio ├── gcdPeripheral │ ├── README.md │ ├── img │ │ ├── murax-gcd-diagrams-gcd-controlpath.png │ │ ├── murax-gcd-diagrams-gcd-datapath.png │ │ ├── murax-gcd-diagrams-gcd-dp+cp.png │ │ ├── murax-gcd-diagrams-gcd.png │ │ ├── murax-gcd-diagrams.drawio │ │ └── simulationWave.PNG │ └── src │ │ └── main │ │ ├── c │ │ └── murax │ │ │ └── gcd_world │ │ │ ├── makefile │ │ │ ├── project │ │ │ └── build.properties │ │ │ └── src │ │ │ ├── crt.S │ │ │ ├── gcd.h │ │ │ ├── gpio.h │ │ │ ├── interrupt.h │ │ │ ├── linker.ld │ │ │ ├── main.c │ │ │ ├── main.h │ │ │ ├── murax.h │ │ │ ├── prescaler.h │ │ │ ├── timer.h │ │ │ └── uart.h │ │ └── scala │ │ └── vexriscv │ │ ├── demo │ │ └── Murax.scala │ │ └── periph │ │ └── gcd │ │ ├── Apb3GCDCtrl.scala │ │ ├── GCDCtrl.scala │ │ ├── GCDData.scala │ │ ├── GCDTop.scala │ │ └── GCDTopSim.scala ├── nativeJtag │ ├── README.md │ ├── soc_init.cfg │ └── usb_connect.cfg ├── smp │ └── smp.md └── vjtag │ └── README.md ├── project ├── build.properties └── plugins.sbt ├── scripts ├── Murax │ ├── arty_a7 │ │ ├── README.md │ │ ├── arty_a7.xdc │ │ ├── arty_a7_org.xdc │ │ ├── make_bit_file.tcl │ │ ├── make_mcs_file │ │ ├── make_mcs_file.tcl │ │ ├── make_mmi_files │ │ ├── make_mmi_files.tcl │ │ ├── make_vivado_project │ │ ├── make_vivado_project.tcl │ │ ├── makefile │ │ ├── open_vivado_project │ │ ├── open_vivado_project.tcl │ │ ├── picocom_arty │ │ ├── soc_mmi.tcl │ │ ├── toplevel.v │ │ ├── vivado_params.tcl │ │ ├── write_flash │ │ ├── write_flash.tcl │ │ ├── write_fpga │ │ └── write_fpga.tcl │ ├── iCE40-hx8k_breakout_board │ │ ├── Makefile │ │ ├── README.md │ │ ├── img │ │ │ ├── cram-programming-config.png │ │ │ └── iCE40HX8K-breakout-revA.png │ │ ├── toplevel.pcf │ │ └── toplevel.v │ ├── iCE40-hx8k_breakout_board_xip │ │ ├── Makefile │ │ ├── Murax_iCE40_hx8k_breakout_board_xip.pcf │ │ ├── README.md │ │ └── img │ │ │ ├── cram-programming-config.png │ │ │ └── iCE40HX8K-breakout-revA.png │ ├── iCE40HX8K-EVB │ │ ├── Makefile │ │ ├── toplevel.pcf │ │ ├── toplevel.v │ │ └── toplevel_pll.v │ └── iCESugar │ │ ├── Makefile │ │ ├── io.pcf │ │ └── toplevel.v └── regression │ ├── .gitignore │ ├── makefile │ ├── regression.mk │ └── verilator.mk ├── src ├── main │ ├── c │ │ ├── common │ │ │ ├── ram.ld │ │ │ ├── riscv64-unknown-elf.mk │ │ │ └── standalone.mk │ │ ├── emulator │ │ │ ├── .gitignore │ │ │ ├── build │ │ │ │ ├── emulator.asm │ │ │ │ ├── emulator.bin │ │ │ │ └── emulator.hex │ │ │ ├── makefile │ │ │ └── src │ │ │ │ ├── config.h │ │ │ │ ├── hal.c │ │ │ │ ├── hal.h │ │ │ │ ├── main.c │ │ │ │ ├── riscv.h │ │ │ │ ├── start.S │ │ │ │ ├── trap.S │ │ │ │ └── utils.S │ │ └── murax │ │ │ ├── hello_world │ │ │ ├── makefile │ │ │ └── src │ │ │ │ ├── crt.S │ │ │ │ ├── gpio.h │ │ │ │ ├── interrupt.h │ │ │ │ ├── linker.ld │ │ │ │ ├── main.c │ │ │ │ ├── murax.h │ │ │ │ ├── prescaler.h │ │ │ │ ├── timer.h │ │ │ │ └── uart.h │ │ │ └── xipBootloader │ │ │ ├── .gitignore │ │ │ ├── crt.S │ │ │ ├── crt.bin │ │ │ ├── demo.S │ │ │ ├── makefile │ │ │ ├── mapping.ld │ │ │ ├── mapping_rom.ld │ │ │ └── mapping_xip.ld │ ├── ressource │ │ └── hex │ │ │ ├── muraxDemo.elf │ │ │ └── muraxDemo.hex │ └── scala │ │ ├── spinal │ │ └── lib │ │ │ └── eda │ │ │ └── icestorm │ │ │ └── IcestormFlow.scala │ │ └── vexriscv │ │ ├── Pipeline.scala │ │ ├── Riscv.scala │ │ ├── Services.scala │ │ ├── Stage.scala │ │ ├── TestsWorkspace.scala │ │ ├── VexRiscv.scala │ │ ├── VexRiscvBmbGenerator.scala │ │ ├── demo │ │ ├── Briey.scala │ │ ├── CustomCsrDemoPlugin.scala │ │ ├── CustomInstruction.scala │ │ ├── FormalSimple.scala │ │ ├── GenCustomCsr.scala │ │ ├── GenCustomInterrupt.scala │ │ ├── GenCustomSimdAdd.scala │ │ ├── GenDeterministicVex.scala │ │ ├── GenFull.scala │ │ ├── GenFullNoMmu.scala │ │ ├── GenFullNoMmuMaxPerf.scala │ │ ├── GenFullNoMmuNoCache.scala │ │ ├── GenFullNoMmuNoCacheSimpleMul.scala │ │ ├── GenFullWithOfficialRiscvDebug.scala │ │ ├── GenFullWithTcm.scala │ │ ├── GenFullWithTcmIntegrated.scala │ │ ├── GenMicroNoCsr.scala │ │ ├── GenNoCacheNoMmuMaxPerf.scala │ │ ├── GenSecure.scala │ │ ├── GenSmallAndProductive.scala │ │ ├── GenSmallAndProductiveCfu.scala │ │ ├── GenSmallAndProductiveICache.scala │ │ ├── GenSmallAndProductiveVfu.scala │ │ ├── GenSmallest.scala │ │ ├── GenSmallestNoCsr.scala │ │ ├── GenTwoThreeStage.scala │ │ ├── Linux.scala │ │ ├── Murax.scala │ │ ├── MuraxUtiles.scala │ │ ├── OpenRoad.scala │ │ ├── SynthesisBench.scala │ │ ├── VexRiscvAhbLite3.scala │ │ ├── VexRiscvAvalonForSim.scala │ │ ├── VexRiscvAvalonWithIntegratedJtag.scala │ │ ├── VexRiscvAxi4LinuxPlicClint.scala │ │ ├── VexRiscvAxi4WithIntegratedJtag.scala │ │ ├── VexRiscvCachedWishboneForSim.scala │ │ ├── WhiteboxPlugin.scala │ │ └── smp │ │ │ ├── Misc.scala │ │ │ ├── VexRiscvSmpCluster.scala │ │ │ ├── VexRiscvSmpLitexCluster.scala │ │ │ └── VexRiscvSmpLitexMpCluster.scala │ │ ├── ip │ │ ├── DataCache.scala │ │ ├── InstructionCache.scala │ │ └── fpu │ │ │ ├── FpuCore.scala │ │ │ ├── FpuDiv.scala │ │ │ ├── FpuSqrt.scala │ │ │ └── Interface.scala │ │ ├── plugin │ │ ├── AesPlugin.scala │ │ ├── BranchPlugin.scala │ │ ├── CfuPlugin.scala │ │ ├── CsrPlugin.scala │ │ ├── DBusCachedPlugin.scala │ │ ├── DBusSimplePlugin.scala │ │ ├── DebugPlugin.scala │ │ ├── DecoderSimplePlugin.scala │ │ ├── DivPlugin.scala │ │ ├── DummyFencePlugin.scala │ │ ├── EmbeddedRiscvJtag.scala │ │ ├── ExternalInterruptArrayPlugin.scala │ │ ├── Fetcher.scala │ │ ├── FormalPlugin.scala │ │ ├── FpuPlugin.scala │ │ ├── HaltOnExceptionPlugin.scala │ │ ├── HazardPessimisticPlugin.scala │ │ ├── HazardSimplePlugin.scala │ │ ├── IBusCachedPlugin.scala │ │ ├── IBusSimplePlugin.scala │ │ ├── IntAluPlugin.scala │ │ ├── MemoryTranslatorPlugin.scala │ │ ├── Misc.scala │ │ ├── MmuPlugin.scala │ │ ├── Mul16Plugin.scala │ │ ├── MulDivIterativePlugin.scala │ │ ├── MulPlugin.scala │ │ ├── MulSimplePlugin.scala │ │ ├── NoPipeliningPlugin.scala │ │ ├── PcManagerSimplePlugin.scala │ │ ├── Plugin.scala │ │ ├── PmpPlugin.scala │ │ ├── PmpPluginNapot.scala │ │ ├── RegFilePlugin.scala │ │ ├── ShiftPlugins.scala │ │ ├── SingleInstructionLimiterPlugin.scala │ │ ├── SrcPlugin.scala │ │ ├── StaticMemoryTranslatorPlugin.scala │ │ ├── VfuPlugin.scala │ │ └── YamlPlugin.scala │ │ └── test │ │ └── Swing.scala └── test │ ├── cpp │ ├── briey │ │ ├── .cproject │ │ ├── installs.txt │ │ ├── jtag.gtkw │ │ ├── main.cpp │ │ ├── makefile │ │ ├── sdram.gtkw │ │ └── wip.gtkw │ ├── common │ │ ├── framework.h │ │ ├── jtag.h │ │ └── uart.h │ ├── custom │ │ ├── atomic │ │ │ ├── build │ │ │ │ ├── atomic.asm │ │ │ │ ├── atomic.elf │ │ │ │ ├── atomic.hex │ │ │ │ ├── atomic.map │ │ │ │ └── atomic.v │ │ │ ├── makefile │ │ │ └── src │ │ │ │ ├── crt.S │ │ │ │ └── ld │ │ ├── custom_csr │ │ │ ├── build │ │ │ │ ├── custom_csr.asm │ │ │ │ ├── custom_csr.elf │ │ │ │ ├── custom_csr.hex │ │ │ │ ├── custom_csr.map │ │ │ │ └── custom_csr.v │ │ │ ├── makefile │ │ │ └── src │ │ │ │ ├── crt.S │ │ │ │ └── ld │ │ └── simd_add │ │ │ ├── build │ │ │ ├── custom_simd_add.asm │ │ │ ├── custom_simd_add.elf │ │ │ ├── custom_simd_add.hex │ │ │ ├── custom_simd_add.map │ │ │ └── custom_simd_add.v │ │ │ ├── makefile │ │ │ └── src │ │ │ ├── crt.S │ │ │ └── ld │ ├── fpu │ │ └── math │ │ │ ├── .gitignore │ │ │ ├── fpu_math.c │ │ │ └── libcode.version │ ├── murax │ │ ├── main.cpp │ │ ├── makefile │ │ └── murax.gtkw │ ├── raw │ │ ├── amo │ │ │ ├── .gitignore │ │ │ ├── build │ │ │ │ ├── amo.asm │ │ │ │ └── amo.hex │ │ │ ├── makefile │ │ │ └── src │ │ │ │ ├── crt.S │ │ │ │ └── ld │ │ ├── common │ │ │ └── asm.mk │ │ ├── dcache │ │ │ ├── .gitignore │ │ │ ├── build │ │ │ │ ├── dcache.asm │ │ │ │ └── dcache.hex │ │ │ ├── makefile │ │ │ └── src │ │ │ │ ├── crt.S │ │ │ │ └── ld │ │ ├── deleg │ │ │ ├── .gitignore │ │ │ ├── build │ │ │ │ ├── deleg.asm │ │ │ │ └── deleg.hex │ │ │ ├── makefile │ │ │ └── src │ │ │ │ ├── crt.S │ │ │ │ ├── encoding.h │ │ │ │ └── ld │ │ ├── fpu │ │ │ ├── .gitignore │ │ │ ├── build │ │ │ │ ├── amo.asm │ │ │ │ ├── amo.hex │ │ │ │ ├── fpu.asm │ │ │ │ └── fpu.hex │ │ │ ├── makefile │ │ │ └── src │ │ │ │ ├── crt.S │ │ │ │ └── ld │ │ ├── icache │ │ │ ├── .gitignore │ │ │ ├── build │ │ │ │ ├── icache.asm │ │ │ │ └── icache.hex │ │ │ ├── makefile │ │ │ └── src │ │ │ │ ├── crt.S │ │ │ │ └── ld │ │ ├── lrsc │ │ │ ├── .gitignore │ │ │ ├── build │ │ │ │ ├── lrsc.asm │ │ │ │ └── lrsc.hex │ │ │ ├── makefile │ │ │ └── src │ │ │ │ ├── crt.S │ │ │ │ └── ld │ │ ├── machineCsr │ │ │ ├── .gitignore │ │ │ ├── build │ │ │ │ ├── machineCsr.asm │ │ │ │ ├── machineCsr.hex │ │ │ │ ├── machineCsrCompressed.asm │ │ │ │ └── machineCsrCompressed.hex │ │ │ ├── makefile │ │ │ └── src │ │ │ │ ├── crt.S │ │ │ │ └── ld │ │ ├── mmu │ │ │ ├── .gitignore │ │ │ ├── build │ │ │ │ ├── mmu.asm │ │ │ │ └── mmu.hex │ │ │ ├── makefile │ │ │ └── src │ │ │ │ ├── crt.S │ │ │ │ └── ld │ │ ├── pmp │ │ │ ├── build │ │ │ │ ├── pmp.asm │ │ │ │ ├── pmp.elf │ │ │ │ ├── pmp.hex │ │ │ │ └── pmp.map │ │ │ ├── makefile │ │ │ └── src │ │ │ │ ├── crt.S │ │ │ │ └── ld │ │ ├── privSpec │ │ │ ├── .gitignore │ │ │ ├── build │ │ │ │ └── privSpec.hex │ │ │ ├── makefile │ │ │ └── src │ │ │ │ ├── crt.S │ │ │ │ ├── ld │ │ │ │ ├── privileged.h │ │ │ │ └── riscv_asm.h │ │ └── smp │ │ │ ├── .gitignore │ │ │ ├── build │ │ │ ├── smp.asm │ │ │ └── smp.bin │ │ │ ├── makefile │ │ │ └── src │ │ │ ├── crt.S │ │ │ └── ld │ └── regression │ │ ├── .gitignore │ │ ├── atomic.gtkw │ │ ├── branch.gtkw │ │ ├── dcache.gtkw │ │ ├── debug.gtkw │ │ ├── default.gtkw │ │ ├── dhrystoneO3.logRef │ │ ├── dhrystoneO3C.logRef │ │ ├── dhrystoneO3M.logRef │ │ ├── dhrystoneO3MC.logRef │ │ ├── encoding.h │ │ ├── fail.gtkw │ │ ├── icache.gtkw │ │ ├── jtag.h │ │ ├── main.cpp │ │ ├── makefile │ │ ├── prediction.gtkw │ │ ├── refDiff.gtkw │ │ ├── wrongDiff.gtkw │ │ └── yolo.gtkw │ ├── java │ └── vexriscv │ │ └── ip │ │ └── fpu │ │ └── FpuMath.java │ ├── python │ ├── gcloud │ │ ├── .gitignore │ │ ├── gcloud.py │ │ ├── makefile │ │ ├── remotePull.py │ │ ├── remoteTest.py │ │ ├── run.sh │ │ ├── stopScript.sh │ │ └── try.py │ └── tool │ │ ├── .gitignore │ │ └── hexToAsm.py │ ├── resources │ ├── .gitignore │ ├── asm │ │ ├── C.ADD.elf.objdump │ │ ├── C.ADDI.elf.objdump │ │ ├── C.ADDI16SP.elf.objdump │ │ ├── C.ADDI4SPN.elf.objdump │ │ ├── C.AND.elf.objdump │ │ ├── C.ANDI.elf.objdump │ │ ├── C.BEQZ.elf.objdump │ │ ├── C.BNEZ.elf.objdump │ │ ├── C.J.elf.objdump │ │ ├── C.JAL.elf.objdump │ │ ├── C.JALR.elf.objdump │ │ ├── C.JR.elf.objdump │ │ ├── C.LI.elf.objdump │ │ ├── C.LUI.elf.objdump │ │ ├── C.LW.elf.objdump │ │ ├── C.LWSP.elf.objdump │ │ ├── C.MV.elf.objdump │ │ ├── C.OR.elf.objdump │ │ ├── C.SLLI.elf.objdump │ │ ├── C.SRAI.elf.objdump │ │ ├── C.SRLI.elf.objdump │ │ ├── C.SUB.elf.objdump │ │ ├── C.SW.elf.objdump │ │ ├── C.SWSP.elf.objdump │ │ ├── C.XOR.elf.objdump │ │ ├── DIV.elf.objdump │ │ ├── DIVU.elf.objdump │ │ ├── DIVW.elf.objdump │ │ ├── I-ADD-01.elf.objdump │ │ ├── I-ADDI-01.elf.objdump │ │ ├── I-AND-01.elf.objdump │ │ ├── I-ANDI-01.elf.objdump │ │ ├── I-AUIPC-01.elf.objdump │ │ ├── I-BEQ-01.elf.objdump │ │ ├── I-BGE-01.elf.objdump │ │ ├── I-BGEU-01.elf.objdump │ │ ├── I-BLT-01.elf.objdump │ │ ├── I-BLTU-01.elf.objdump │ │ ├── I-BNE-01.elf.objdump │ │ ├── I-CSRRC-01.elf.objdump │ │ ├── I-CSRRCI-01.elf.objdump │ │ ├── I-CSRRS-01.elf.objdump │ │ ├── I-CSRRSI-01.elf.objdump │ │ ├── I-CSRRW-01.elf.objdump │ │ ├── I-CSRRWI-01.elf.objdump │ │ ├── I-DELAY_SLOTS-01.elf.objdump │ │ ├── I-EBREAK-01.elf.objdump │ │ ├── I-ECALL-01.elf.objdump │ │ ├── I-ENDIANESS-01.elf.objdump │ │ ├── I-FENCE.I-01.elf.objdump │ │ ├── I-IO.elf.objdump │ │ ├── I-JAL-01.elf.objdump │ │ ├── I-JALR-01.elf.objdump │ │ ├── I-LB-01.elf.objdump │ │ ├── I-LBU-01.elf.objdump │ │ ├── I-LH-01.elf.objdump │ │ ├── I-LHU-01.elf.objdump │ │ ├── I-LUI-01.elf.objdump │ │ ├── I-LW-01.elf.objdump │ │ ├── I-MISALIGN_JMP-01.elf.objdump │ │ ├── I-MISALIGN_LDST-01.elf.objdump │ │ ├── I-NOP-01.elf.objdump │ │ ├── I-OR-01.elf.objdump │ │ ├── I-ORI-01.elf.objdump │ │ ├── I-RF_size-01.elf.objdump │ │ ├── I-RF_width-01.elf.objdump │ │ ├── I-RF_x0-01.elf.objdump │ │ ├── I-SB-01.elf.objdump │ │ ├── I-SH-01.elf.objdump │ │ ├── I-SLL-01.elf.objdump │ │ ├── I-SLLI-01.elf.objdump │ │ ├── I-SLT-01.elf.objdump │ │ ├── I-SLTI-01.elf.objdump │ │ ├── I-SLTIU-01.elf.objdump │ │ ├── I-SLTU-01.elf.objdump │ │ ├── I-SRA-01.elf.objdump │ │ ├── I-SRAI-01.elf.objdump │ │ ├── I-SRL-01.elf.objdump │ │ ├── I-SRLI-01.elf.objdump │ │ ├── I-SUB-01.elf.objdump │ │ ├── I-SW-01.elf.objdump │ │ ├── I-XOR-01.elf.objdump │ │ ├── I-XORI-01.elf.objdump │ │ ├── MUL.elf.objdump │ │ ├── MULH.elf.objdump │ │ ├── MULHSU.elf.objdump │ │ ├── MULHU.elf.objdump │ │ ├── MULW.elf.objdump │ │ ├── REM.elf.objdump │ │ ├── REMU.elf.objdump │ │ ├── REMUW.elf.objdump │ │ ├── REMW.elf.objdump │ │ ├── dhrystoneO3.asm │ │ ├── dhrystoneO3C.asm │ │ ├── dhrystoneO3MC.asm │ │ ├── machineCsr.asm │ │ ├── machineCsrCompressed.asm │ │ ├── mmu.asm │ │ ├── rv32uc-p-rvc.dump │ │ ├── rv32ud-p-fadd.dump │ │ ├── rv32ud-p-fclass.dump │ │ ├── rv32ud-p-fcmp.dump │ │ ├── rv32ud-p-fcvt.dump │ │ ├── rv32ud-p-fcvt_w.dump │ │ ├── rv32ud-p-fdiv.dump │ │ ├── rv32ud-p-fmadd.dump │ │ ├── rv32ud-p-fmin.dump │ │ ├── rv32ud-p-ldst.dump │ │ ├── rv32ud-p-recoding.dump │ │ ├── rv32uf-p-fadd.dump │ │ ├── rv32uf-p-fclass.dump │ │ ├── rv32uf-p-fcmp.dump │ │ ├── rv32uf-p-fcvt.dump │ │ ├── rv32uf-p-fcvt_w.dump │ │ ├── rv32uf-p-fdiv.dump │ │ ├── rv32uf-p-fmadd.dump │ │ ├── rv32uf-p-fmin.dump │ │ ├── rv32uf-p-ldst.dump │ │ ├── rv32uf-p-move.dump │ │ ├── rv32uf-p-recoding.dump │ │ ├── rv32ui-p-add.dump │ │ ├── rv32ui-p-addi.dump │ │ ├── rv32ui-p-and.dump │ │ ├── rv32ui-p-andi.dump │ │ ├── rv32ui-p-auipc.dump │ │ ├── rv32ui-p-beq.dump │ │ ├── rv32ui-p-bge.dump │ │ ├── rv32ui-p-bgeu.dump │ │ ├── rv32ui-p-blt.dump │ │ ├── rv32ui-p-bltu.dump │ │ ├── rv32ui-p-bne.dump │ │ ├── rv32ui-p-fence_i.dump │ │ ├── rv32ui-p-jal.dump │ │ ├── rv32ui-p-jalr.dump │ │ ├── rv32ui-p-lb.dump │ │ ├── rv32ui-p-lbu.dump │ │ ├── rv32ui-p-lh.dump │ │ ├── rv32ui-p-lhu.dump │ │ ├── rv32ui-p-lui.dump │ │ ├── rv32ui-p-lw.dump │ │ ├── rv32ui-p-or.dump │ │ ├── rv32ui-p-ori.dump │ │ ├── rv32ui-p-sb.dump │ │ ├── rv32ui-p-sh.dump │ │ ├── rv32ui-p-simple.dump │ │ ├── rv32ui-p-sll.dump │ │ ├── rv32ui-p-slli.dump │ │ ├── rv32ui-p-slt.dump │ │ ├── rv32ui-p-slti.dump │ │ ├── rv32ui-p-sltiu.dump │ │ ├── rv32ui-p-sltu.dump │ │ ├── rv32ui-p-sra.dump │ │ ├── rv32ui-p-srai.dump │ │ ├── rv32ui-p-srl.dump │ │ ├── rv32ui-p-srli.dump │ │ ├── rv32ui-p-sub.dump │ │ ├── rv32ui-p-sw.dump │ │ ├── rv32ui-p-xor.dump │ │ ├── rv32ui-p-xori.dump │ │ ├── rv32um-p-div.dump │ │ ├── rv32um-p-divu.dump │ │ ├── rv32um-p-mul.dump │ │ ├── rv32um-p-mulh.dump │ │ ├── rv32um-p-mulhsu.dump │ │ ├── rv32um-p-mulhu.dump │ │ ├── rv32um-p-rem.dump │ │ ├── rv32um-p-remu.dump │ │ └── testA.asm │ ├── bin │ │ ├── .gitignore │ │ ├── coremark_rv32i.bin │ │ ├── coremark_rv32ic.bin │ │ ├── coremark_rv32im.bin │ │ └── coremark_rv32imc.bin │ ├── elf │ │ └── uart.elf │ ├── freertos │ │ ├── AltBlckQ_rv32i_O0.hex │ │ ├── AltBlckQ_rv32i_O3.hex │ │ ├── AltBlckQ_rv32ic_O0.hex │ │ ├── AltBlckQ_rv32ic_O3.hex │ │ ├── AltBlckQ_rv32im_O3.hex │ │ ├── AltBlckQ_rv32imac_O3.hex │ │ ├── AltBlock_rv32i_O0.hex │ │ ├── AltBlock_rv32i_O3.hex │ │ ├── AltBlock_rv32ic_O0.hex │ │ ├── AltBlock_rv32ic_O3.hex │ │ ├── AltBlock_rv32im_O3.hex │ │ ├── AltBlock_rv32imac_O3.hex │ │ ├── AltPollQ_rv32i_O0.hex │ │ ├── AltPollQ_rv32i_O3.hex │ │ ├── AltPollQ_rv32ic_O0.hex │ │ ├── AltPollQ_rv32ic_O3.hex │ │ ├── AltPollQ_rv32im_O3.hex │ │ ├── AltPollQ_rv32imac_O3.hex │ │ ├── AltQTest_rv32i_O0.hex │ │ ├── AltQTest_rv32i_O3.hex │ │ ├── AltQTest_rv32ic_O0.hex │ │ ├── AltQTest_rv32ic_O3.hex │ │ ├── AltQTest_rv32im_O3.hex │ │ ├── AltQTest_rv32imac_O3.hex │ │ ├── BlockQ_rv32i_O0.hex │ │ ├── BlockQ_rv32i_O3.hex │ │ ├── BlockQ_rv32ic_O0.hex │ │ ├── BlockQ_rv32ic_O3.hex │ │ ├── BlockQ_rv32im_O3.hex │ │ ├── BlockQ_rv32imac_O3.hex │ │ ├── EventGroupsDemo_rv32i_O0.hex │ │ ├── EventGroupsDemo_rv32i_O3.hex │ │ ├── EventGroupsDemo_rv32ic_O0.hex │ │ ├── EventGroupsDemo_rv32ic_O3.hex │ │ ├── EventGroupsDemo_rv32im_O3.hex │ │ ├── EventGroupsDemo_rv32imac_O3.hex │ │ ├── GenQTest_rv32i_O0.hex │ │ ├── GenQTest_rv32i_O3.hex │ │ ├── GenQTest_rv32ic_O0.hex │ │ ├── GenQTest_rv32ic_O3.hex │ │ ├── GenQTest_rv32im_O3.hex │ │ ├── GenQTest_rv32imac_O3.hex │ │ ├── PollQ_rv32i_O0.hex │ │ ├── PollQ_rv32i_O3.hex │ │ ├── PollQ_rv32ic_O0.hex │ │ ├── PollQ_rv32ic_O3.hex │ │ ├── PollQ_rv32im_O3.hex │ │ ├── PollQ_rv32imac_O3.hex │ │ ├── QPeek_rv32i_O0.hex │ │ ├── QPeek_rv32i_O3.hex │ │ ├── QPeek_rv32ic_O0.hex │ │ ├── QPeek_rv32ic_O3.hex │ │ ├── QPeek_rv32im_O3.hex │ │ ├── QPeek_rv32imac_O3.hex │ │ ├── QueueOverwrite_rv32i_O0.hex │ │ ├── QueueOverwrite_rv32i_O3.hex │ │ ├── QueueOverwrite_rv32ic_O0.hex │ │ ├── QueueOverwrite_rv32ic_O3.hex │ │ ├── QueueOverwrite_rv32im_O3.hex │ │ ├── QueueOverwrite_rv32imac_O3.hex │ │ ├── QueueSetPolling_rv32i_O0.hex │ │ ├── QueueSetPolling_rv32i_O3.hex │ │ ├── QueueSetPolling_rv32ic_O0.hex │ │ ├── QueueSetPolling_rv32ic_O3.hex │ │ ├── QueueSetPolling_rv32im_O3.hex │ │ ├── QueueSetPolling_rv32imac_O3.hex │ │ ├── QueueSet_rv32i_O0.hex │ │ ├── QueueSet_rv32i_O3.hex │ │ ├── QueueSet_rv32ic_O0.hex │ │ ├── QueueSet_rv32ic_O3.hex │ │ ├── QueueSet_rv32im_O3.hex │ │ ├── QueueSet_rv32imac_O3.hex │ │ ├── TaskNotify_rv32i_O0.hex │ │ ├── TaskNotify_rv32i_O3.hex │ │ ├── TaskNotify_rv32ic_O0.hex │ │ ├── TaskNotify_rv32ic_O3.hex │ │ ├── TaskNotify_rv32im_O3.hex │ │ ├── TaskNotify_rv32imac_O3.hex │ │ ├── blocktim_rv32i_O0.hex │ │ ├── blocktim_rv32i_O3.hex │ │ ├── blocktim_rv32ic_O0.hex │ │ ├── blocktim_rv32ic_O3.hex │ │ ├── blocktim_rv32im_O3.hex │ │ ├── blocktim_rv32imac_O3.hex │ │ ├── countsem_rv32i_O0.hex │ │ ├── countsem_rv32i_O3.hex │ │ ├── countsem_rv32ic_O0.hex │ │ ├── countsem_rv32ic_O3.hex │ │ ├── countsem_rv32im_O3.hex │ │ ├── countsem_rv32imac_O3.hex │ │ ├── crhook_rv32i_O0.hex │ │ ├── crhook_rv32i_O3.hex │ │ ├── crhook_rv32ic_O0.hex │ │ ├── crhook_rv32ic_O3.hex │ │ ├── crhook_rv32im_O3.hex │ │ ├── crhook_rv32imac_O3.hex │ │ ├── dead_rv32i_O0.hex │ │ ├── dead_rv32i_O3.hex │ │ ├── dead_rv32ic_O0.hex │ │ ├── dead_rv32ic_O3.hex │ │ ├── dead_rv32im_O3.hex │ │ ├── dead_rv32imac_O3.hex │ │ ├── dynamic_rv32i_O0.hex │ │ ├── dynamic_rv32i_O3.hex │ │ ├── dynamic_rv32ic_O0.hex │ │ ├── dynamic_rv32ic_O3.hex │ │ ├── dynamic_rv32im_O3.hex │ │ ├── dynamic_rv32imac_O3.hex │ │ ├── flop_rv32i_O0.hex │ │ ├── flop_rv32i_O3.hex │ │ ├── flop_rv32ic_O0.hex │ │ ├── flop_rv32ic_O3.hex │ │ ├── flop_rv32im_O3.hex │ │ ├── flop_rv32imac_O3.hex │ │ ├── integer_rv32i_O0.hex │ │ ├── integer_rv32i_O3.hex │ │ ├── integer_rv32ic_O0.hex │ │ ├── integer_rv32ic_O3.hex │ │ ├── integer_rv32im_O3.hex │ │ ├── integer_rv32imac_O3.hex │ │ ├── recmutex_rv32i_O0.hex │ │ ├── recmutex_rv32i_O3.hex │ │ ├── recmutex_rv32ic_O0.hex │ │ ├── recmutex_rv32ic_O3.hex │ │ ├── recmutex_rv32im_O3.hex │ │ ├── recmutex_rv32imac_O3.hex │ │ ├── semtest_rv32i_O0.hex │ │ ├── semtest_rv32i_O3.hex │ │ ├── semtest_rv32ic_O0.hex │ │ ├── semtest_rv32ic_O3.hex │ │ ├── semtest_rv32im_O3.hex │ │ ├── semtest_rv32imac_O3.hex │ │ ├── sp_flop_rv32i_O0.hex │ │ ├── sp_flop_rv32i_O3.hex │ │ ├── sp_flop_rv32ic_O0.hex │ │ ├── sp_flop_rv32ic_O3.hex │ │ ├── sp_flop_rv32im_O3.hex │ │ ├── sp_flop_rv32imac_O3.hex │ │ ├── test1_rv32i_O0.hex │ │ ├── test1_rv32i_O3.hex │ │ ├── test1_rv32ic_O0.hex │ │ ├── test1_rv32ic_O3.hex │ │ ├── test1_rv32im_O3.hex │ │ └── test1_rv32imac_O3.hex │ ├── hex │ │ ├── C.ADD.elf.hex │ │ ├── C.ADDI.elf.hex │ │ ├── C.ADDI16SP.elf.hex │ │ ├── C.ADDI4SPN.elf.hex │ │ ├── C.AND.elf.hex │ │ ├── C.ANDI.elf.hex │ │ ├── C.BEQZ.elf.hex │ │ ├── C.BNEZ.elf.hex │ │ ├── C.J.elf.hex │ │ ├── C.JAL.elf.hex │ │ ├── C.JALR.elf.hex │ │ ├── C.JR.elf.hex │ │ ├── C.LI.elf.hex │ │ ├── C.LUI.elf.hex │ │ ├── C.LW.elf.hex │ │ ├── C.LWSP.elf.hex │ │ ├── C.MV.elf.hex │ │ ├── C.OR.elf.hex │ │ ├── C.SLLI.elf.hex │ │ ├── C.SRAI.elf.hex │ │ ├── C.SRLI.elf.hex │ │ ├── C.SUB.elf.hex │ │ ├── C.SW.elf.hex │ │ ├── C.SWSP.elf.hex │ │ ├── C.XOR.elf.hex │ │ ├── DIV.elf.hex │ │ ├── DIVU.elf.hex │ │ ├── I-ADD-01.elf.hex │ │ ├── I-ADDI-01.elf.hex │ │ ├── I-AND-01.elf.hex │ │ ├── I-ANDI-01.elf.hex │ │ ├── I-AUIPC-01.elf.hex │ │ ├── I-BEQ-01.elf.hex │ │ ├── I-BGE-01.elf.hex │ │ ├── I-BGEU-01.elf.hex │ │ ├── I-BLT-01.elf.hex │ │ ├── I-BLTU-01.elf.hex │ │ ├── I-BNE-01.elf.hex │ │ ├── I-CSRRC-01.elf.hex │ │ ├── I-CSRRCI-01.elf.hex │ │ ├── I-CSRRS-01.elf.hex │ │ ├── I-CSRRSI-01.elf.hex │ │ ├── I-CSRRW-01.elf.hex │ │ ├── I-CSRRWI-01.elf.hex │ │ ├── I-DELAY_SLOTS-01.elf.hex │ │ ├── I-EBREAK-01.elf.hex │ │ ├── I-ECALL-01.elf.hex │ │ ├── I-ENDIANESS-01.elf.hex │ │ ├── I-FENCE.I-01.elf.hex │ │ ├── I-IO.elf.hex │ │ ├── I-JAL-01.elf.hex │ │ ├── I-JALR-01.elf.hex │ │ ├── I-LB-01.elf.hex │ │ ├── I-LBU-01.elf.hex │ │ ├── I-LH-01.elf.hex │ │ ├── I-LHU-01.elf.hex │ │ ├── I-LUI-01.elf.hex │ │ ├── I-LW-01.elf.hex │ │ ├── I-MISALIGN_JMP-01.elf.hex │ │ ├── I-MISALIGN_LDST-01.elf.hex │ │ ├── I-NOP-01.elf.hex │ │ ├── I-OR-01.elf.hex │ │ ├── I-ORI-01.elf.hex │ │ ├── I-RF_size-01.elf.hex │ │ ├── I-RF_width-01.elf.hex │ │ ├── I-RF_x0-01.elf.hex │ │ ├── I-SB-01.elf.hex │ │ ├── I-SH-01.elf.hex │ │ ├── I-SLL-01.elf.hex │ │ ├── I-SLLI-01.elf.hex │ │ ├── I-SLT-01.elf.hex │ │ ├── I-SLTI-01.elf.hex │ │ ├── I-SLTIU-01.elf.hex │ │ ├── I-SLTU-01.elf.hex │ │ ├── I-SRA-01.elf.hex │ │ ├── I-SRAI-01.elf.hex │ │ ├── I-SRL-01.elf.hex │ │ ├── I-SRLI-01.elf.hex │ │ ├── I-SUB-01.elf.hex │ │ ├── I-SW-01.elf.hex │ │ ├── I-XOR-01.elf.hex │ │ ├── I-XORI-01.elf.hex │ │ ├── MUL.elf.hex │ │ ├── MULH.elf.hex │ │ ├── MULHSU.elf.hex │ │ ├── MULHU.elf.hex │ │ ├── REM.elf.hex │ │ ├── REMU.elf.hex │ │ ├── debugPlugin.hex │ │ ├── debugPluginExternal.hex │ │ ├── dhrystoneO3.hex │ │ ├── dhrystoneO3C.hex │ │ ├── dhrystoneO3M.hex │ │ ├── dhrystoneO3MC.hex │ │ ├── freeRTOS_demo.hex │ │ ├── machineCsr.hex │ │ ├── machineCsrCompressed.hex │ │ ├── mmu.hex │ │ ├── rv32uc-p-rvc.hex │ │ ├── rv32ud-p-fadd.hex │ │ ├── rv32ud-p-fclass.hex │ │ ├── rv32ud-p-fcmp.hex │ │ ├── rv32ud-p-fcvt.hex │ │ ├── rv32ud-p-fcvt_w.hex │ │ ├── rv32ud-p-fdiv.hex │ │ ├── rv32ud-p-fmadd.hex │ │ ├── rv32ud-p-fmin.hex │ │ ├── rv32ud-p-ldst.hex │ │ ├── rv32ud-p-recoding.hex │ │ ├── rv32uf-p-fadd.hex │ │ ├── rv32uf-p-fclass.hex │ │ ├── rv32uf-p-fcmp.hex │ │ ├── rv32uf-p-fcvt.hex │ │ ├── rv32uf-p-fcvt_w.hex │ │ ├── rv32uf-p-fdiv.hex │ │ ├── rv32uf-p-fmadd.hex │ │ ├── rv32uf-p-fmin.hex │ │ ├── rv32uf-p-ldst.hex │ │ ├── rv32uf-p-move.hex │ │ ├── rv32uf-p-recoding.hex │ │ ├── rv32ui-p-add.hex │ │ ├── rv32ui-p-addi.hex │ │ ├── rv32ui-p-and.hex │ │ ├── rv32ui-p-andi.hex │ │ ├── rv32ui-p-auipc.hex │ │ ├── rv32ui-p-beq.hex │ │ ├── rv32ui-p-bge.hex │ │ ├── rv32ui-p-bgeu.hex │ │ ├── rv32ui-p-blt.hex │ │ ├── rv32ui-p-bltu.hex │ │ ├── rv32ui-p-bne.hex │ │ ├── rv32ui-p-fence_i.hex │ │ ├── rv32ui-p-jal.hex │ │ ├── rv32ui-p-jalr.hex │ │ ├── rv32ui-p-lb.hex │ │ ├── rv32ui-p-lbu.hex │ │ ├── rv32ui-p-lh.hex │ │ ├── rv32ui-p-lhu.hex │ │ ├── rv32ui-p-lui.hex │ │ ├── rv32ui-p-lui.hex.hex │ │ ├── rv32ui-p-lw.hex │ │ ├── rv32ui-p-or.hex │ │ ├── rv32ui-p-ori.hex │ │ ├── rv32ui-p-sb.hex │ │ ├── rv32ui-p-sh.hex │ │ ├── rv32ui-p-simple.hex │ │ ├── rv32ui-p-sll.hex │ │ ├── rv32ui-p-slli.hex │ │ ├── rv32ui-p-slt.hex │ │ ├── rv32ui-p-slti.hex │ │ ├── rv32ui-p-sltiu.hex │ │ ├── rv32ui-p-sltu.hex │ │ ├── rv32ui-p-sra.hex │ │ ├── rv32ui-p-srai.hex │ │ ├── rv32ui-p-srl.hex │ │ ├── rv32ui-p-srli.hex │ │ ├── rv32ui-p-sub.hex │ │ ├── rv32ui-p-sw.hex │ │ ├── rv32ui-p-xor.hex │ │ ├── rv32ui-p-xori.hex │ │ ├── rv32um-p-div.hex │ │ ├── rv32um-p-divu.hex │ │ ├── rv32um-p-mul.hex │ │ ├── rv32um-p-mulh.hex │ │ ├── rv32um-p-mulhsu.hex │ │ ├── rv32um-p-mulhu.hex │ │ ├── rv32um-p-rem.hex │ │ ├── rv32um-p-remu.hex │ │ └── testA.hex │ └── ref │ │ ├── C.ADD.reference_output │ │ ├── C.ADDI.reference_output │ │ ├── C.ADDI16SP.reference_output │ │ ├── C.ADDI4SPN.reference_output │ │ ├── C.AND.reference_output │ │ ├── C.ANDI.reference_output │ │ ├── C.BEQZ.reference_output │ │ ├── C.BNEZ.reference_output │ │ ├── C.J.reference_output │ │ ├── C.JAL.reference_output │ │ ├── C.JALR.reference_output │ │ ├── C.JR.reference_output │ │ ├── C.LI.reference_output │ │ ├── C.LUI.reference_output │ │ ├── C.LW.reference_output │ │ ├── C.LWSP.reference_output │ │ ├── C.MV.reference_output │ │ ├── C.OR.reference_output │ │ ├── C.SLLI.reference_output │ │ ├── C.SRAI.reference_output │ │ ├── C.SRLI.reference_output │ │ ├── C.SUB.reference_output │ │ ├── C.SW.reference_output │ │ ├── C.SWSP.reference_output │ │ ├── C.XOR.reference_output │ │ ├── DIV.reference_output │ │ ├── DIVU.reference_output │ │ ├── I-ADD-01.reference_output │ │ ├── I-ADDI-01.reference_output │ │ ├── I-AND-01.reference_output │ │ ├── I-ANDI-01.reference_output │ │ ├── I-AUIPC-01.reference_output │ │ ├── I-BEQ-01.reference_output │ │ ├── I-BGE-01.reference_output │ │ ├── I-BGEU-01.reference_output │ │ ├── I-BLT-01.reference_output │ │ ├── I-BLTU-01.reference_output │ │ ├── I-BNE-01.reference_output │ │ ├── I-CSRRC-01.reference_output │ │ ├── I-CSRRCI-01.reference_output │ │ ├── I-CSRRS-01.reference_output │ │ ├── I-CSRRSI-01.reference_output │ │ ├── I-CSRRW-01.reference_output │ │ ├── I-CSRRWI-01.reference_output │ │ ├── I-DELAY_SLOTS-01.reference_output │ │ ├── I-EBREAK-01.reference_output │ │ ├── I-ECALL-01.reference_output │ │ ├── I-ENDIANESS-01.reference_output │ │ ├── I-FENCE.I-01.reference_output │ │ ├── I-IO.reference_output │ │ ├── I-JAL-01.reference_output │ │ ├── I-JALR-01.reference_output │ │ ├── I-LB-01.reference_output │ │ ├── I-LBU-01.reference_output │ │ ├── I-LH-01.reference_output │ │ ├── I-LHU-01.reference_output │ │ ├── I-LUI-01.reference_output │ │ ├── I-LW-01.reference_output │ │ ├── I-MISALIGN_JMP-01.reference_output │ │ ├── I-MISALIGN_LDST-01.reference_output │ │ ├── I-NOP-01.reference_output │ │ ├── I-OR-01.reference_output │ │ ├── I-ORI-01.reference_output │ │ ├── I-RF_size-01.reference_output │ │ ├── I-RF_width-01.reference_output │ │ ├── I-RF_x0-01.reference_output │ │ ├── I-SB-01.reference_output │ │ ├── I-SH-01.reference_output │ │ ├── I-SLL-01.reference_output │ │ ├── I-SLLI-01.reference_output │ │ ├── I-SLT-01.reference_output │ │ ├── I-SLTI-01.reference_output │ │ ├── I-SLTIU-01.reference_output │ │ ├── I-SLTU-01.reference_output │ │ ├── I-SRA-01.reference_output │ │ ├── I-SRAI-01.reference_output │ │ ├── I-SRL-01.reference_output │ │ ├── I-SRLI-01.reference_output │ │ ├── I-SUB-01.reference_output │ │ ├── I-SW-01.reference_output │ │ ├── I-XOR-01.reference_output │ │ ├── I-XORI-01.reference_output │ │ ├── MUL.reference_output │ │ ├── MULH.reference_output │ │ ├── MULHSU.reference_output │ │ ├── MULHU.reference_output │ │ ├── REM.reference_output │ │ └── REMU.reference_output │ └── scala │ └── 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