22 | Back to my home page. 23 | 24 | 25 | -------------------------------------------------------------------------------- /people.inf.ethz.ch/wirth/FPGA-relatedWork/ComputerSystemDesign.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Spirit-of-Oberon/wirth-personal/874a6024c1b6b1eff0208225e1004bc1aa62fb79/people.inf.ethz.ch/wirth/FPGA-relatedWork/ComputerSystemDesign.pdf -------------------------------------------------------------------------------- /people.inf.ethz.ch/wirth/FPGA-relatedWork/DRAM.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | module DRAM(input [10:0] adr, 3 | input [31:0] din, 4 | output reg [31:0] dout, 5 | input we, 6 | input clk); 7 | reg [31:0] mem [2047: 0]; 8 | always @(posedge clk) begin 9 | if (we) mem[adr] <= din; 10 | dout <= mem[adr]; 11 | end 12 | endmodule 13 | 14 | -------------------------------------------------------------------------------- /people.inf.ethz.ch/wirth/FPGA-relatedWork/DRAM.v.html: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | module DRAM(input [10:0] adr, 3 | input [31:0] din, 4 | output reg [31:0] dout, 5 | input we, 6 | input clk); 7 | reg [31:0] mem [2047: 0]; 8 | always @(posedge clk) begin 9 | if (we) mem[adr] <= din; 10 | dout <= mem[adr]; 11 | end 12 | endmodule 13 | 14 | -------------------------------------------------------------------------------- /people.inf.ethz.ch/wirth/FPGA-relatedWork/Divider.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps // NW 31.10.10 2 | 3 | module Divider( 4 | input clk, run, 5 | output stall, 6 | input [31:0] x, y, 7 | output [31:0] quot, rem); 8 | 9 | reg [4:0] S; // state 10 | reg [31:0] r3, q2; 11 | wire [31:0] r0, r1, r2, q0, q1, d; 12 | 13 | assign stall = run & ~(S == 31); 14 | assign r0 = (S == 0) ? 0 : r3; 15 | assign d = r1 - y; 16 | assign r1 = {r0[30:0], q0[31]}; 17 | assign r2 = d[31] ? r1 : d; 18 | assign q0 = (S == 0) ? x : q2; 19 | assign q1 = {q0[30:0], ~d[31]}; 20 | assign rem = r2; 21 | assign quot = q1; 22 | 23 | always @ (posedge(clk)) begin 24 | r3 <= r2; q2 <= q1; 25 | S <= run ? S+1 : 0; 26 | end 27 | 28 | endmodule 29 | -------------------------------------------------------------------------------- /people.inf.ethz.ch/wirth/FPGA-relatedWork/Divider.v.html: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps // NW 31.10.10 2 | 3 | module Divider( 4 | input clk, run, 5 | output stall, 6 | input [31:0] x, y, 7 | output [31:0] quot, rem); 8 | 9 | reg [4:0] S; // state 10 | reg [31:0] r3, q2; 11 | wire [31:0] r0, r1, r2, q0, q1, d; 12 | 13 | assign stall = run & ~(S == 31); 14 | assign r0 = (S == 0) ? 0 : r3; 15 | assign d = r1 - y; 16 | assign r1 = {r0[30:0], q0[31]}; 17 | assign r2 = d[31] ? r1 : d; 18 | assign q0 = (S == 0) ? x : q2; 19 | assign q1 = {q0[30:0], ~d[31]}; 20 | assign rem = r2; 21 | assign quot = q1; 22 | 23 | always @ (posedge(clk)) begin 24 | r3 <= r2; q2 <= q1; 25 | S <= run ? S+1 : 0; 26 | end 27 | 28 | endmodule 29 | -------------------------------------------------------------------------------- /people.inf.ethz.ch/wirth/FPGA-relatedWork/Multiplier.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps // NW 3.12.2010 2 | 3 | module Multiplier( 4 | input clk, run, u, 5 | output stall, 6 | input [31:0] x, y, 7 | output [63:0] z); 8 | 9 | reg [4:0] S; // state 10 | reg [31:0] B2, A2; // high and low parts of partial product 11 | wire [32:0] B0, B00, B01; 12 | wire [31:0] B1, A0, A1; 13 | 14 | assign stall = run & ~(S == 31); 15 | assign B00 = (S == 0) ? 0 : {B2[31] & u, B2}; 16 | assign B01 = A0[0] ? {y[31] & u, y} : 0; 17 | assign B0 = ((S == 31) & u) ? B00 - B01 : B00 + B01; 18 | assign B1 = B0[32:1]; 19 | assign A0 = (S == 0) ? x : A2; 20 | assign A1 = {B0[0], A0[31:1]}; 21 | assign z = {B1, A1}; 22 | 23 | always @ (posedge(clk)) begin 24 | B2 <= B1; A2 <= A1; 25 | S <= run ? S+1 : 0; 26 | end 27 | 28 | endmodule 29 | -------------------------------------------------------------------------------- /people.inf.ethz.ch/wirth/FPGA-relatedWork/Multiplier.v.html: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps // NW 3.12.2010 2 | 3 | module Multiplier( 4 | input clk, run, u, 5 | output stall, 6 | input [31:0] x, y, 7 | output [63:0] z); 8 | 9 | reg [4:0] S; // state 10 | reg [31:0] B2, A2; // high and low parts of partial product 11 | wire [32:0] B0, B00, B01; 12 | wire [31:0] B1, A0, A1; 13 | 14 | assign stall = run & ~(S == 31); 15 | assign B00 = (S == 0) ? 0 : {B2[31] & u, B2}; 16 | assign B01 = A0[0] ? {y[31] & u, y} : 0; 17 | assign B0 = ((S == 31) & u) ? B00 - B01 : B00 + B01; 18 | assign B1 = B0[32:1]; 19 | assign A0 = (S == 0) ? x : A2; 20 | assign A1 = {B0[0], A0[31:1]}; 21 | assign z = {B1, A1}; 22 | 23 | always @ (posedge(clk)) begin 24 | B2 <= B1; A2 <= A1; 25 | S <= run ? S+1 : 0; 26 | end 27 | 28 | endmodule 29 | -------------------------------------------------------------------------------- /people.inf.ethz.ch/wirth/FPGA-relatedWork/Multiplier1.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps // NW 29.4.2011 2 | module Multiplier1( 3 | input clk, run, u, 4 | output stall, 5 | input [31:0] x, y, 6 | output [63:0] z); 7 | 8 | reg S; // state 9 | reg [15:0] z0; 10 | reg [47:0] z1, z2; 11 | wire [35:0] p0, p1, p2, p3; 12 | 13 | assign stall = run & ~S; 14 | assign z[15:0] = z0; 15 | assign z[63:16] = z1 + z2; 16 | 17 | MULT18X18 mult0(.P(p0), .A({2'b0, x[15:0]}), .B({2'b0, y[15:0]})); 18 | MULT18X18 mult1(.P(p1), .A({{2{u&x[31]}}, x[31:16]}), .B({2'b0, y[15:0]})); 19 | MULT18X18 mult2(.P(p2), .A({2'b0, x[15:0]}), .B({{2{u&y[31]}}, y[31:16]})); 20 | MULT18X18 mult3(.P(p3), .A({{2{u&x[31]}}, x[31:16]}), .B({{2{u&y[31]}}, y[31:16]})); 21 | 22 | always @(posedge clk) begin 23 | S <= stall; 24 | z0 <= p0[15:0]; 25 | z1 <= {{32'b0}, p0[31:16]} + {{16{u&p1[31]}}, p1[31:0]}; 26 | z2 <= {{16{u&p2[31]}}, p2[31:0]} + {p3[31:0], 16'b0}; 27 | end 28 | endmodule 29 | -------------------------------------------------------------------------------- /people.inf.ethz.ch/wirth/FPGA-relatedWork/Multiplier1.v.html: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps // NW 29.4.2011 2 | module Multiplier1( 3 | input clk, run, u, 4 | output stall, 5 | input [31:0] x, y, 6 | output [63:0] z); 7 | 8 | reg S; // state 9 | reg [15:0] z0; 10 | reg [47:0] z1, z2; 11 | wire [35:0] p0, p1, p2, p3; 12 | 13 | assign stall = run & ~S; 14 | assign z[15:0] = z0; 15 | assign z[63:16] = z1 + z2; 16 | 17 | MULT18X18 mult0(.P(p0), .A({2'b0, x[15:0]}), .B({2'b0, y[15:0]})); 18 | MULT18X18 mult1(.P(p1), .A({{2{u&x[31]}}, x[31:16]}), .B({2'b0, y[15:0]})); 19 | MULT18X18 mult2(.P(p2), .A({2'b0, x[15:0]}), .B({{2{u&y[31]}}, y[31:16]})); 20 | MULT18X18 mult3(.P(p3), .A({{2{u&x[31]}}, x[31:16]}), .B({{2{u&y[31]}}, y[31:16]})); 21 | 22 | always @(posedge clk) begin 23 | S <= stall; 24 | z0 <= p0[15:0]; 25 | z1 <= {{32'b0}, p0[31:16]} + {{16{u&p1[31]}}, p1[31:0]}; 26 | z2 <= {{16{u&p2[31]}}, p2[31:0]} + {p3[31:0], 16'b0}; 27 | end 28 | endmodule 29 | -------------------------------------------------------------------------------- /people.inf.ethz.ch/wirth/FPGA-relatedWork/PROM.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | module PROM( 3 | input [10:0] adr, 4 | output reg [31:0] data, 5 | input clk); 6 | reg [31:0] mem [2047: 0]; 7 | initial $readmemh("../prom.mem", mem); 8 | always @(posedge clk) data <= mem[adr]; 9 | endmodule 10 | 11 | -------------------------------------------------------------------------------- /people.inf.ethz.ch/wirth/FPGA-relatedWork/PROM.v.html: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | module PROM( 3 | input [10:0] adr, 4 | output reg [31:0] data, 5 | input clk); 6 | reg [31:0] mem [2047: 0]; 7 | initial $readmemh("../prom.mem", mem); 8 | always @(posedge clk) data <= mem[adr]; 9 | endmodule 10 | 11 | -------------------------------------------------------------------------------- /people.inf.ethz.ch/wirth/FPGA-relatedWork/RISC-Arch.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Spirit-of-Oberon/wirth-personal/874a6024c1b6b1eff0208225e1004bc1aa62fb79/people.inf.ethz.ch/wirth/FPGA-relatedWork/RISC-Arch.pdf -------------------------------------------------------------------------------- /people.inf.ethz.ch/wirth/FPGA-relatedWork/RISC.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Spirit-of-Oberon/wirth-personal/874a6024c1b6b1eff0208225e1004bc1aa62fb79/people.inf.ethz.ch/wirth/FPGA-relatedWork/RISC.pdf -------------------------------------------------------------------------------- /people.inf.ethz.ch/wirth/FPGA-relatedWork/RISC0.ucf: -------------------------------------------------------------------------------- 1 | NET "CLK50M" LOC = "T9" ; 2 | NET "CLK50M" PERIOD = 20.0ns HIGH 50%; 3 | NET "rstIN" LOC = "L14"; 4 | 5 | NET "TxD" LOC = "R13"; 6 | NET "RxD" LOC = "T13" ; 7 | 8 | NET "swi[0]" LOC = "F12"; 9 | NET "swi[1]" LOC = "G12"; 10 | NET "swi[2]" LOC = "H14"; 11 | NET "swi[3]" LOC = "H13"; 12 | NET "swi[4]" LOC = "J14"; 13 | NET "swi[5]" LOC = "J13"; 14 | NET "swi[6]" LOC = "K14"; 15 | NET "swi[7]" LOC = "K13"; 16 | 17 | NET "leds[0]" LOC = "K12"; 18 | NET "leds[1]" LOC = "P14"; 19 | NET "leds[2]" LOC = "L12"; 20 | NET "leds[3]" LOC = "N14"; 21 | NET "leds[4]" LOC = "P13"; 22 | NET "leds[5]" LOC = "N12"; 23 | NET "leds[6]" LOC = "P12"; 24 | NET "leds[7]" LOC = "P11"; 25 | -------------------------------------------------------------------------------- /people.inf.ethz.ch/wirth/FPGA-relatedWork/RISC0.ucf.html: -------------------------------------------------------------------------------- 1 | NET "CLK50M" LOC = "T9" ; 2 | NET "CLK50M" PERIOD = 20.0ns HIGH 50%; 3 | NET "rstIN" LOC = "L14"; 4 | 5 | NET "TxD" LOC = "R13"; 6 | NET "RxD" LOC = "T13" ; 7 | 8 | NET "swi[0]" LOC = "F12"; 9 | NET "swi[1]" LOC = "G12"; 10 | NET "swi[2]" LOC = "H14"; 11 | NET "swi[3]" LOC = "H13"; 12 | NET "swi[4]" LOC = "J14"; 13 | NET "swi[5]" LOC = "J13"; 14 | NET "swi[6]" LOC = "K14"; 15 | NET "swi[7]" LOC = "K13"; 16 | 17 | NET "leds[0]" LOC = "K12"; 18 | NET "leds[1]" LOC = "P14"; 19 | NET "leds[2]" LOC = "L12"; 20 | NET "leds[3]" LOC = "N14"; 21 | NET "leds[4]" LOC = "P13"; 22 | NET "leds[5]" LOC = "N12"; 23 | NET "leds[6]" LOC = "P12"; 24 | NET "leds[7]" LOC = "P11"; 25 | -------------------------------------------------------------------------------- /people.inf.ethz.ch/wirth/FPGA-relatedWork/RISC0.v.html: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps // NW 8.10.12 rev. 26.12.2013 2 | 3 | module RISC0( 4 | input clk, rst, 5 | input [31:0] inbus, 6 | output [5:0] ioadr, 7 | output iord, iowr, 8 | output [31:0] outbus); 9 | 10 | reg [11:0] PC; 11 | reg N, Z, C, OV; // condition flags 12 | reg [31:0] R [0:15]; // array of 16 registers 13 | reg [31:0] H; // aux register 14 | reg stall1; 15 | 16 | wire [31:0] IR; 17 | wire [31:0] pmout; 18 | wire [11:0] pcmux, nxpc; 19 | wire cond, S; 20 | wire sa, sb, sc; 21 | 22 | wire p, q, u, v, w; // instruction fields 23 | wire [3:0] op, ira, ira0, irb, irc; 24 | wire [2:0] cc; 25 | wire [15:0] imm; 26 | wire [19:0] off; 27 | 28 | wire regwr; 29 | wire [13:0] dmadr; 30 | wire dmwr, ioenb; 31 | wire [31:0] dmin, dmout; 32 | wire [1:0] sc1, sc0; // shift counts 33 | 34 | wire [31:0] A, B, C0, C1, regmux; 35 | wire [31:0] s1, s2, s3, t1, t2, t3; 36 | wire [32:0] aluRes; 37 | wire [31:0] quotient, remainder; 38 | wire [63:0] product; 39 | wire stall, stallL, stallM, stallD; 40 | 41 | wire MOV, LSL, ASR, ROR, AND, ANN, IOR, XOR; // operation signals 42 | wire ADD, SUB, MUL, DIV; 43 | wire LDR, STR, BR; 44 | 45 | PROM PM (.adr(pcmux[10:0]), .data(pmout), .clk(clk)); 46 | DRAM DM (.adr(dmadr[12:2]), .din(dmin), .dout(dmout), .we(dmwr), .clk(clk)); 47 | 48 | Multiplier1 mulUnit (.clk(clk), .run(MUL), .stall(stallM), 49 | .u(~u), .x(B), .y(C1), .z(product)); 50 | 51 | Divider divUnit (.clk(clk), .run(DIV), .stall(stallD), 52 | .x(B), .y(C1), .quot(quotient), .rem(remainder)); 53 | 54 | assign IR = pmout; // decoding 55 | assign p = IR[31]; 56 | assign q = IR[30]; 57 | assign u = IR[29]; 58 | assign v = IR[28]; 59 | assign w = IR[16]; 60 | assign cc = IR[26:24]; 61 | assign ira = IR[27:24]; 62 | assign irb = IR[23:20]; 63 | assign op = IR[19:16]; 64 | assign irc = IR[3:0]; 65 | assign imm = IR[15:0]; 66 | assign off = IR[19:0]; 67 | 68 | assign MOV = ~p & (op == 0); 69 | assign LSL = ~p & (op == 1); 70 | assign ASR = ~p & (op == 2); 71 | assign ROR = ~p & (op == 3); 72 | assign AND = ~p & (op == 4); 73 | assign ANN = ~p & (op == 5); 74 | assign IOR = ~p & (op == 6); 75 | assign XOR = ~p & (op == 7); 76 | assign ADD = ~p & (op == 8); 77 | assign SUB = ~p & (op == 9); 78 | assign MUL = ~p & (op == 10); 79 | assign DIV = ~p & (op == 11); 80 | 81 | assign LDR = p & ~q & ~u; 82 | assign STR = p & ~q & u; 83 | assign BR = p & q; 84 | 85 | assign A = R[ira0]; // register data signals 86 | assign B = R[irb]; 87 | assign C0 = R[irc]; 88 | 89 | // Arithmetic-logical unit (ALU) 90 | assign ira0 = BR ? 15 : ira; 91 | assign C1 = ~q ? C0 : {{16{v}}, imm}; 92 | assign dmadr = B[13:0] + off[13:0]; 93 | assign dmwr = STR & ~stall; 94 | assign dmin = A; 95 | 96 | assign ioenb = (dmadr[13:6] == 8'b11111111); 97 | assign iowr = STR & ioenb; 98 | assign iord = LDR & ioenb; 99 | assign ioadr = dmadr[5:0]; 100 | assign outbus = A; 101 | 102 | assign sc0 = C1[1:0]; 103 | assign sc1 = C1[3:2]; 104 | 105 | // shifter for ASR and ROR 106 | assign s1 = (sc0 == 3) ? {(w ? B[2:0] : {3{B[31]}}), B[31:3]} : 107 | (sc0 == 2) ? {(w ? B[1:0] : {2{B[31]}}), B[31:2]} : 108 | (sc0 == 1) ? {(w ? B[0] : B[31]), B[31:1]} : B; 109 | assign s2 = (sc1 == 3) ? {(w ? s1[11:0] : {12{s1[31]}}), s1[31:12]} : 110 | (sc1 == 2) ? {(w ? s1[7:0] : {8{s1[31]}}), s1[31:8]} : 111 | (sc1 == 1) ? {(w ? s1[3:0] : {4{s1[31]}}), s1[31:4]} : s1; 112 | assign s3 = C1[4] ? {(w ? s2[15:0] : {16{s2[31]}}), s2[31:16]} : s2; 113 | 114 | // shifter for LSL 115 | assign t1 = (sc0 == 3) ? {B[28:0], 3'b0} : 116 | (sc0 == 2) ? {B[29:0], 2'b0} : 117 | (sc0 == 1) ? {B[30:0], 1'b0} : B; 118 | assign t2 = (sc1 == 3) ? {t1[19:0], 12'b0} : 119 | (sc1 == 2) ? {t1[23:0], 8'b0} : 120 | (sc1 == 1) ? {t1[27:0], 4'b0} : t1; 121 | assign t3 = C1[4] ? {t2[15:0], 16'b0} : t2; 122 | 123 | assign aluRes = 124 | MOV ? (q ? 125 | (~u ? {{16{v}}, imm} : {imm, 16'b0}) : 126 | (~u ? C0 : (~v ? H : {N, Z, C, OV, 20'b0, 8'b10100000}))) : 127 | LSL ? t3 : 128 | (ASR|ROR) ? s3 : 129 | AND ? B & C1 : 130 | ANN ? B & ~C1 : 131 | IOR ? B | C1 : 132 | XOR ? B ^ C1 : 133 | ADD ? B + C1 + (u & C) : 134 | SUB ? B - C1 - (u & C) : 135 | MUL ? product[31:0] : 136 | DIV ? quotient : 0; 137 | 138 | assign regwr = ~p & ~stall | (LDR & stall1)| (BR & cond & v) ; 139 | assign regmux = 140 | (LDR & ~ioenb) ? dmout : 141 | (LDR & ioenb) ? inbus : 142 | (BR & v) ? {18'b0, nxpc, 2'b0} : aluRes; 143 | 144 | // Control unit CU 145 | assign S = N ^ OV; 146 | assign nxpc = PC + 1; 147 | assign cond = IR[27] ^ 148 | ((cc == 0) & N | // MI, PL 149 | (cc == 1) & Z | // EQ, NE 150 | (cc == 2) & C | // CS, CC 151 | (cc == 3) & OV | // VS, VC 152 | (cc == 4) & (C|Z) | // LS, HI 153 | (cc == 5) & S | // LT, GE 154 | (cc == 6) & (S|Z) | // LE, GT 155 | (cc == 7)); // T, F 156 | 157 | assign pcmux = 158 | (~rst) ? 0 : 159 | (stall) ? PC : 160 | (BR & cond & u) ? off[11:0] + nxpc : 161 | (BR & cond & ~u) ? C0[13:2] : nxpc; 162 | 163 | assign sa = aluRes[31]; 164 | assign sb = B[31]; 165 | assign sc = C1[31] ^ SUB; 166 | 167 | assign stall = stallL | stallM | stallD; 168 | assign stallL = LDR & ~stall1; 169 | 170 | always @ (posedge clk) begin 171 | PC <= pcmux; 172 | stall1 <= stallL; 173 | R[ira0] <= regwr ? regmux : A; 174 | N <= regwr ? regmux[31] : N; 175 | Z <= regwr ? (regmux[31:0] == 0) : Z; 176 | C <= (ADD|SUB) ? aluRes[32] : C; 177 | OV <= (ADD|SUB) ? (sa & ~sb & ~sc | ~sa & sb & sc) : OV; 178 | H <= MUL ? product[63:32] : DIV ? remainder : H; 179 | end 180 | endmodule 181 | -------------------------------------------------------------------------------- /people.inf.ethz.ch/wirth/FPGA-relatedWork/RISC0Top.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps // NW 27.5.09 LL 10.12.09 NW 28.7.2011 2 | 3 | module RISC0Top( 4 | input CLK50M, 5 | input rstIn, 6 | input RxD, 7 | input [7:0] swi, 8 | output TxD, 9 | output [7:0] leds); 10 | 11 | wire clk, clk50; 12 | reg rst, clk25; 13 | 14 | wire[5:0] ioadr; 15 | wire [3:0] iowadr; 16 | wire iowr; 17 | wire[31:0] inbus, outbus; 18 | 19 | wire [7:0] dataTx, dataRx; 20 | wire rdyRx, doneRx, startTx, rdyTx; 21 | wire limit; // of cnt0 22 | 23 | reg [7:0] Lreg; 24 | reg [15:0] cnt0; 25 | reg [31:0] cnt1; // milliseconds 26 | 27 | RISC0 riscx(.clk(clk), .rst(rst), .iord(iord), .iowr(iowr), 28 | .ioadr(ioadr), .inbus(inbus), .outbus(outbus)); 29 | 30 | RS232R receiver(.clk(clk), .rst(rst), .RxD(RxD), .done(doneRx), .data(dataRx), .rdy(rdyRx)); 31 | RS232T transmitter(.clk(clk), .rst(rst), .start(startTx), .data(dataTx), .TxD(TxD), .rdy(rdyTx)); 32 | 33 | assign iowadr = ioadr[5:2]; 34 | assign inbus = (iowadr == 0) ? cnt1 : 35 | (iowadr == 1) ? swi : 36 | (iowadr == 2) ? {24'b0, dataRx} : 37 | (iowadr == 3) ? {30'b0, rdyTx, rdyRx} : 0; 38 | 39 | assign dataTx = outbus[7:0]; 40 | assign startTx = iowr & (iowadr == 2); 41 | assign doneRx = iord & (iowadr == 2); 42 | assign limit = (cnt0 == 25000); 43 | assign leds = Lreg; 44 | 45 | always @(posedge clk) 46 | begin 47 | rst <= ~rstIn; 48 | Lreg <= ~rst ? 0 : (iowr & (iowadr == 1)) ? outbus[7:0] : Lreg; 49 | cnt0 <= limit ? 0 : cnt0 + 1; 50 | cnt1 <= limit ? cnt1 + 1 : cnt1; 51 | end 52 | 53 | //The Clocks 54 | IBUFG clkInBuf(.I(CLK50M), .O(clk50)); 55 | always @ (posedge clk50) clk25 <= ~clk25; 56 | BUFG clk150buf(.I(clk25), .O(clk)); 57 | endmodule 58 | -------------------------------------------------------------------------------- /people.inf.ethz.ch/wirth/FPGA-relatedWork/RISC0Top.v.html: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps // NW 27.5.09 LL 10.12.09 NW 28.7.2011 2 | 3 | module RISC0Top( 4 | input CLK50M, 5 | input rstIn, 6 | input RxD, 7 | input [7:0] swi, 8 | output TxD, 9 | output [7:0] leds); 10 | 11 | wire clk, clk50; 12 | reg rst, clk25; 13 | 14 | wire[5:0] ioadr; 15 | wire [3:0] iowadr; 16 | wire iowr; 17 | wire[31:0] inbus, outbus; 18 | 19 | wire [7:0] dataTx, dataRx; 20 | wire rdyRx, doneRx, startTx, rdyTx; 21 | wire limit; // of cnt0 22 | 23 | reg [7:0] Lreg; 24 | reg [15:0] cnt0; 25 | reg [31:0] cnt1; // milliseconds 26 | 27 | RISC0 riscx(.clk(clk), .rst(rst), .iord(iord), .iowr(iowr), 28 | .ioadr(ioadr), .inbus(inbus), .outbus(outbus)); 29 | 30 | RS232R receiver(.clk(clk), .rst(rst), .RxD(RxD), .done(doneRx), .data(dataRx), .rdy(rdyRx)); 31 | RS232T transmitter(.clk(clk), .rst(rst), .start(startTx), .data(dataTx), .TxD(TxD), .rdy(rdyTx)); 32 | 33 | assign iowadr = ioadr[5:2]; 34 | assign inbus = (iowadr == 0) ? cnt1 : 35 | (iowadr == 1) ? swi : 36 | (iowadr == 2) ? {24'b0, dataRx} : 37 | (iowadr == 3) ? {30'b0, rdyTx, rdyRx} : 0; 38 | 39 | assign dataTx = outbus[7:0]; 40 | assign startTx = iowr & (iowadr == 2); 41 | assign doneRx = iord & (iowadr == 2); 42 | assign limit = (cnt0 == 25000); 43 | assign leds = Lreg; 44 | 45 | always @(posedge clk) 46 | begin 47 | rst <= ~rstIn; 48 | Lreg <= ~rst ? 0 : (iowr & (iowadr == 1)) ? outbus[7:0] : Lreg; 49 | cnt0 <= limit ? 0 : cnt0 + 1; 50 | cnt1 <= limit ? cnt1 + 1 : cnt1; 51 | end 52 | 53 | //The Clocks 54 | IBUFG clkInBuf(.I(CLK50M), .O(clk50)); 55 | always @ (posedge clk50) clk25 <= ~clk25; 56 | BUFG clk150buf(.I(clk25), .O(clk)); 57 | endmodule 58 | -------------------------------------------------------------------------------- /people.inf.ethz.ch/wirth/FPGA-relatedWork/RS232R.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps // NW 4.5.09 / 15.8.10 / 15.11.10 2 | 3 | // RS232 receiver for 19200 bps, 8 bit data 4 | // clock is 25 MHz; 25000 / 1302 = 19.2 KHz 5 | // clock is 35 MHz; 35000 / 1823 = 19.2 KHz 6 | 7 | module RS232R( 8 | input clk, rst, 9 | input done, // "byte has been read" 10 | input RxD, 11 | output rdy, 12 | output [7:0] data); 13 | 14 | wire endtick, midtick; 15 | reg run, stat; 16 | reg [11:0] tick; 17 | reg [3:0] bitcnt; 18 | reg [7:0] shreg; 19 | 20 | assign endtick = tick == 1302; 21 | assign midtick = tick == 651; 22 | assign endbit = bitcnt == 8; 23 | assign data = shreg; 24 | assign rdy = stat; 25 | 26 | always @ (posedge clk) begin 27 | run <= (~RxD) ? 1 : (~rst | endtick & endbit) ? 0 : run; 28 | tick <= (run & ~endtick) ? tick + 1 : 0; 29 | bitcnt <= (endtick & ~endbit) ? bitcnt + 1 : 30 | (endtick & endbit) ? 0 : bitcnt; 31 | shreg <= midtick ? {RxD, shreg[7:1]} : shreg; 32 | stat <= (endtick & endbit) ? 1 : (~rst | done) ? 0 : stat; 33 | end 34 | endmodule 35 | -------------------------------------------------------------------------------- /people.inf.ethz.ch/wirth/FPGA-relatedWork/RS232R.v.html: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps // NW 4.5.09 / 15.8.10 / 15.11.10 2 | 3 | // RS232 receiver for 19200 bps, 8 bit data 4 | // clock is 25 MHz; 25000 / 1302 = 19.2 KHz 5 | // clock is 35 MHz; 35000 / 1823 = 19.2 KHz 6 | 7 | module RS232R( 8 | input clk, rst, 9 | input done, // "byte has been read" 10 | input RxD, 11 | output rdy, 12 | output [7:0] data); 13 | 14 | wire endtick, midtick; 15 | reg run, stat; 16 | reg [11:0] tick; 17 | reg [3:0] bitcnt; 18 | reg [7:0] shreg; 19 | 20 | assign endtick = tick == 1302; 21 | assign midtick = tick == 651; 22 | assign endbit = bitcnt == 8; 23 | assign data = shreg; 24 | assign rdy = stat; 25 | 26 | always @ (posedge clk) begin 27 | run <= (~RxD) ? 1 : (~rst | endtick & endbit) ? 0 : run; 28 | tick <= (run & ~endtick) ? tick + 1 : 0; 29 | bitcnt <= (endtick & ~endbit) ? bitcnt + 1 : 30 | (endtick & endbit) ? 0 : bitcnt; 31 | shreg <= midtick ? {RxD, shreg[7:1]} : shreg; 32 | stat <= (endtick & endbit) ? 1 : (~rst | done) ? 0 : stat; 33 | end 34 | endmodule 35 | -------------------------------------------------------------------------------- /people.inf.ethz.ch/wirth/FPGA-relatedWork/RS232T.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps // NW 4.5.09 / 15.8.10 / 15.11.10 2 | 3 | // RS232 receiver for 19200 bps, 8 bit data 4 | // clock is 25 MHz; 25000 / 1302 = 19.2 KHz 5 | // clock is 35 MHz; 35000 / 1823 = 19.2 KHz 6 | 7 | module RS232T( 8 | input clk, rst, 9 | input start, // request to accept and send a byte 10 | input [7:0] data, 11 | output rdy, 12 | output TxD); 13 | 14 | wire endtick, endbit; 15 | reg run; 16 | reg [11:0] tick; 17 | reg [3:0] bitcnt; 18 | reg [8:0] shreg; 19 | 20 | assign endtick = tick == 1302; 21 | assign endbit = bitcnt == 9; 22 | assign rdy = ~run; 23 | assign TxD = shreg[0]; 24 | 25 | always @ (posedge clk) begin 26 | run <= (~rst | endtick & endbit) ? 0 : start ? 1 : run; 27 | tick <= (run & ~endtick) ? tick + 1 : 0; 28 | bitcnt <= (endtick & ~endbit) ? bitcnt + 1 : 29 | (endtick & endbit) ? 0 : bitcnt; 30 | shreg <= (~rst) ? 1 : start ? {data, 1'b0} : 31 | endtick ? {1'b1, shreg[8:1]} : shreg; 32 | end 33 | endmodule 34 | -------------------------------------------------------------------------------- /people.inf.ethz.ch/wirth/FPGA-relatedWork/RS232T.v.html: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps // NW 4.5.09 / 15.8.10 / 15.11.10 2 | 3 | // RS232 receiver for 19200 bps, 8 bit data 4 | // clock is 25 MHz; 25000 / 1302 = 19.2 KHz 5 | // clock is 35 MHz; 35000 / 1823 = 19.2 KHz 6 | 7 | module RS232T( 8 | input clk, rst, 9 | input start, // request to accept and send a byte 10 | input [7:0] data, 11 | output rdy, 12 | output TxD); 13 | 14 | wire endtick, endbit; 15 | reg run; 16 | reg [11:0] tick; 17 | reg [3:0] bitcnt; 18 | reg [8:0] shreg; 19 | 20 | assign endtick = tick == 1302; 21 | assign endbit = bitcnt == 9; 22 | assign rdy = ~run; 23 | assign TxD = shreg[0]; 24 | 25 | always @ (posedge clk) begin 26 | run <= (~rst | endtick & endbit) ? 0 : start ? 1 : run; 27 | tick <= (run & ~endtick) ? tick + 1 : 0; 28 | bitcnt <= (endtick & ~endbit) ? bitcnt + 1 : 29 | (endtick & endbit) ? 0 : bitcnt; 30 | shreg <= (~rst) ? 1 : start ? {data, 1'b0} : 31 | endtick ? {1'b1, shreg[8:1]} : shreg; 32 | end 33 | endmodule 34 | -------------------------------------------------------------------------------- /people.inf.ethz.ch/wirth/FPGA-relatedWork/StandalonePrograms.Mod.txt: -------------------------------------------------------------------------------- 1 | (* ORP.Compile @ ORTool.DecObj Counter.rsc 2 | ORX.WriteFile Counter.rsc 2048 "D:/Verilog/RISC/prom.mem"~ 3 | ORX.WriteFile Shifter.rsc 2048 "D:/Verilog/RISC/prom.mem"~ *) 4 | 5 | MODULE* Counter; 6 | VAR x, y, z: INTEGER; 7 | BEGIN LED(1); z := 0; 8 | REPEAT LED(z); x := 1000; 9 | REPEAT y := 1000; 10 | REPEAT y := y-1 UNTIL y = 0; 11 | x := x-1 12 | UNTIL x = 0; 13 | z := z+1 14 | UNTIL FALSE 15 | END Counter. 16 | 17 | MODULE* Shifter; 18 | VAR x, y, z, d: INTEGER; 19 | BEGIN z := 1; d := 1; 20 | REPEAT LED(z); x := 1000; 21 | REPEAT y := 1000; 22 | REPEAT y := y-1 UNTIL y = 0; 23 | x := x-1 24 | UNTIL x = 0; 25 | IF z = 128 THEN d := -1 ELSIF z = 1 THEN d := 1 END ; 26 | IF d = 1 THEN z := LSL(z, 1) ELSE z := ASR(z, 1) END 27 | UNTIL FALSE 28 | END Shifter. 29 | 30 | -------------------------------------------------------------------------------- /people.inf.ethz.ch/wirth/FPGA-relatedWork/ThreeCounters.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Spirit-of-Oberon/wirth-personal/874a6024c1b6b1eff0208225e1004bc1aa62fb79/people.inf.ethz.ch/wirth/FPGA-relatedWork/ThreeCounters.pdf -------------------------------------------------------------------------------- /people.inf.ethz.ch/wirth/FPGA-relatedWork/index.html: -------------------------------------------------------------------------------- 1 | 2 |
3 | 4 | 5 |31 | Back to my home page. 32 | 33 | 34 | -------------------------------------------------------------------------------- /people.inf.ethz.ch/wirth/Lola/Lola2.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Spirit-of-Oberon/wirth-personal/874a6024c1b6b1eff0208225e1004bc1aa62fb79/people.inf.ethz.ch/wirth/Lola/Lola2.pdf -------------------------------------------------------------------------------- /people.inf.ethz.ch/wirth/Lola/LolaCompiler.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Spirit-of-Oberon/wirth-personal/874a6024c1b6b1eff0208225e1004bc1aa62fb79/people.inf.ethz.ch/wirth/Lola/LolaCompiler.pdf -------------------------------------------------------------------------------- /people.inf.ethz.ch/wirth/Lola/Sources/DCMX3.v: -------------------------------------------------------------------------------- 1 | module DCMX3 (input CLKIN, output CLKFX); 2 | (* LOC = "DCM_X1Y1" *) DCM #(.CLKFX_MULTIPLY(3), .CLK_FEEDBACK("NONE")) 3 | dcm(.CLKIN(CLKIN), .CLKFX(CLKFX)); 4 | endmodule 5 | -------------------------------------------------------------------------------- /people.inf.ethz.ch/wirth/Lola/Sources/DCMX3.v.html: -------------------------------------------------------------------------------- 1 | module DCMX3 (input CLKIN, output CLKFX); 2 | (* LOC = "DCM_X1Y1" *) DCM #(.CLKFX_MULTIPLY(3), .CLK_FEEDBACK("NONE")) 3 | dcm(.CLKIN(CLKIN), .CLKFX(CLKFX)); 4 | endmodule 5 | -------------------------------------------------------------------------------- /people.inf.ethz.ch/wirth/Lola/Sources/Divider.Lola.txt: -------------------------------------------------------------------------------- 1 | MODULE Divider( (*NW 14.9.2015*) 2 | IN clk, run, u: BIT; 3 | OUT stall: BIT; 4 | IN x, y: WORD; (*y > 0*) 5 | OUT quot, rem: WORD); 6 | 7 | REG (clk) S: [6] BIT; 8 | RQ: [64] BIT; 9 | VAR sign: BIT; 10 | x0, w0, w1: WORD; 11 | BEGIN stall := run & (S # 33); 12 | sign := x.31 & u; 13 | x0 := sign -> -x : x; 14 | w0 := RQ[62:31]; 15 | w1 := w0 - y; 16 | S := run -> S+1 : 0; 17 | quot := ~sign -> RQ[31:0] : (RQ[63:32] = 0) -> -RQ[31:0] : -RQ[31:0] - 1; 18 | rem := ~sign -> RQ[63:32] : (RQ[63:32] = 0) -> 0 : y - RQ[63:32]; 19 | RQ := (S = 0) -> {0'32, x0} : {w1.31 -> w0 : w1, RQ[30:0], ~w1[31]} 20 | END Divider. 21 | -------------------------------------------------------------------------------- /people.inf.ethz.ch/wirth/Lola/Sources/FPAdder.Lola.txt: -------------------------------------------------------------------------------- 1 | MODULE FPAdder( (*NW 4.10.2016*) 2 | IN clk, run, u, v: BIT; x, y: WORD; 3 | OUT stall: BIT; z: WORD); 4 | 5 | REG (clk) State: [2] BIT; 6 | x3, y3, t3: [25] BIT; 7 | Sum: [27] BIT; 8 | 9 | VAR xs, ys, xn, yn: BIT; (*signs, null*) 10 | xe, ye: [9] BIT; (*exponents*) 11 | xm, ym: [25] BIT; (*mantissas*) 12 | 13 | dx, dy, e0, e1: [9] BIT; 14 | sx, sy: [9] BIT; (*shift counts*) 15 | sx0, sx1, sy0, sy1: [2] BIT; 16 | sxh, syh: BIT; 17 | x0, x1,x2, y0, y1, y2: [25] BIT; 18 | s: [27] BIT; 19 | 20 | z24, z22, z20, z18, z16, z14, z12, z10, z8, z6, z4, z2: BIT; 21 | sc: [5] BIT; (*shift count*) 22 | sc0, sc1: [2] BIT; 23 | t1, t2: [25] BIT; 24 | 25 | BEGIN (*unpack*) 26 | xs := x.31; 27 | xe := u -> 150'9 : {0'1, x[30:23]}; 28 | xm := {(~u | x.23), x[22:0], 0'1}; 29 | xn := x[30:0] = 0; 30 | ys := y.31; 31 | ye := {0'1, y[30:23]}; 32 | ym := {(~u & ~v), y[22:0], 0'1}; 33 | yn := y[30:0] = 0; 34 | dx := xe - ye; dy := ye - xe; 35 | e0 := dx.8 -> ye : xe; 36 | sx := dy.8 -> 0 : dy; sy := dx.8 -> 0 : dx; 37 | sx0 := sx[1:0]; sx1 := sx[3:2]; 38 | sy0 := sy[1:0]; sy1 := sy[3:2]; 39 | sxh := sx.7 | sx.6 | sx.5; syh := sy.7 | sy.6 | sy.5; 40 | 41 | (*denormalize; right shift*) 42 | x0 := (xs & ~u) -> -xm : xm; 43 | x1 := (sx0 = 3) -> {xs!3, x0[24:3]} : 44 | (sx0 = 2) -> {xs!2, x0[24:2]} : 45 | (sx0 = 1) -> {xs, x0[24:1]} : x0; 46 | x2 := (sx1 = 3) -> {xs!12, x1[24:12]} : 47 | (sx1 = 2) -> {xs!8, x1[24:8]} : 48 | (sx1 = 1) -> {xs!4, x1[24:4]} : x1; 49 | x3 := sxh -> {xs!25} : sx.4 -> {xs!16, x2[24:16]} : x2; 50 | 51 | y0 := (ys & ~u) -> -ym : ym; 52 | y1 := (sy0 = 3) -> {ys!3, y0[24:3]} : 53 | (sy0 = 2) -> {ys!2, y0[24:2]} : 54 | (sy0 = 1) -> {ys, y0[24:1]} : y0; 55 | y2 := (sy1 = 3) -> {ys!12, y1[24:12]} : 56 | (sy1 = 2) -> {ys!8, y1[24:8]} : 57 | (sy1 = 1) -> {ys!4, y1[24:4]} : y1; 58 | y3 := syh -> {ys!25} : (sy.4 -> {ys!16, y2[24:16]} : y2); 59 | 60 | (*addition*) 61 | Sum := {xs, xs, x3} + {ys, ys, y3}; s := (Sum.26 -> -Sum : Sum) + 1; (*round*) 62 | 63 | (*post-normalize, shift left; sc = shift count*) 64 | z24 := ~s.25 & ~s.24; 65 | z22 := z24 & ~s.23 & ~s.22; 66 | z20 := z22 & ~s.21 & ~s.20; 67 | z18 := z20 & ~s.19 & ~s.18; 68 | z16 := z18 & ~s.17 & ~s.16; 69 | z14 := z16 & ~s.15 & ~s.14; 70 | z12 := z14 & ~s.13 & ~s.12; 71 | z10 := z12 & ~s.11 & ~s.10; 72 | z8 := z10 & ~s.9 & ~s.8; 73 | z6 := z8 & ~s.7 & ~s.6; 74 | z4 := z6 & ~s.5 & ~s.4; 75 | z2 := z4 & ~s.3 & ~s.2; 76 | 77 | sc := {z10, 78 | z18 & (s.17 | s.16 | s.15 | s.14 | s.13 | s.12 | s.11 | s.10) | z2, 79 | z22 & (s.21 | s.20 | s.19 | s.18) | z14 & (s.13 | s.12 | s.11 | s.10) | z6 & (s.5 | s.4 | s.3 | s.2), 80 | z24 & (s.23 | s.22) | z20 & (s.19 | s.18) | z16 & (s.15 | s.14) | z12 & (s.11 | s.10) | z8 & (s.7 | s.6) | z4 & (s.3 | s.2), 81 | ~s.25 & s.24 | z24 & ~s.23 & s.22 | z24 & ~s.23 & s.22 | z22 & ~s.21 & s.20 | z20 & ~s.19 & s.18 | z18 & ~s.17 & s.16 | 82 | z16 & ~s.15 & s.14 | z14 & ~s.13 & s.12 | z12 & ~s.11 & s.10 | z10 & ~s.9 & s.8 | z8 & ~s.7 & s.6 | z6 & ~s.5 & s.4 | z4 & ~s.3 & s.2}; 83 | 84 | e1 := e0 - {0'4, sc} + 1; 85 | sc0 := sc[1:0]; sc1 := sc[3:2]; 86 | t1 := (sc0 = 3) -> {s[22:1], 0'3} : 87 | (sc0 = 2) -> {s[23:1], 0'2} : 88 | (sc0 = 1) -> {s[24:1], 0'1} : s[25:1]; 89 | t2 := (sc1 = 3) -> {t1[12:0], 0'12} : 90 | (sc1 = 2) -> {t1[16:0], 0'8} : 91 | (sc1 = 1) -> {t1[20:0], 0'4} : t1; 92 | t3 := sc.4 -> {t2[8:0], 0'16} : t2; 93 | 94 | stall := run & (State # 3); 95 | State := run -> State+1 : 0; 96 | 97 | z := v -> {Sum.26 ! 7, Sum[25:1]} : (*FLOOR*) 98 | xn -> (u|yn -> 0 : y) : 99 | yn -> x : 100 | (t3 = 0) | e1.8 -> 0 : {Sum.26, e1[7:0], t3[23:1]} 101 | END FPAdder. 102 | -------------------------------------------------------------------------------- /people.inf.ethz.ch/wirth/Lola/Sources/FPDivider.Lola.txt: -------------------------------------------------------------------------------- 1 | MODULE FPDivider( (*NW 28.10.2016*) 2 | IN clk, run: BIT; x, y: WORD; 3 | OUT stall: BIT; z: WORD); 4 | 5 | REG (clk) S: [5] BIT; (*state*) 6 | R: [24] BIT; (*remainder*) 7 | Q: [26] BIT; (*quotient*) 8 | 9 | VAR sign: BIT; 10 | xe, ye: [8] BIT; 11 | e0, e1: [9] BIT; 12 | r0, r1, d: [25] BIT; 13 | q0: [26] BIT; 14 | z0, z1: [25] BIT; 15 | 16 | BEGIN 17 | sign := x.31 ^ y.31; (*xor*) 18 | xe := x[30:23]; ye := y[30:23]; 19 | e0 := {0'1, xe} - {0'1, ye}; 20 | e1 := e0 + 126 + {0'8, Q.25}; 21 | stall := run & (S # 26); 22 | 23 | r0 := (S = 0) -> {1'2, x[22:0]} : {R, 0'1}; 24 | r1 := d.24 -> 0 : d; 25 | d := r0 - {1'2, y[22:0]}; 26 | q0 := (S = 0) -> 0 : Q; 27 | 28 | z0 := Q.25 -> Q[25:1] : Q[24:0]; (* normalize*) 29 | z1 := z0 + 1; (*round*) 30 | z := (xe = 0) -> 0 : 31 | (ye = 0) -> {sign, 0FFH'8, 0'23} : (*divide by 0*) 32 | ~e1.8 -> {sign, e1[7:0], z1[23:1]} : 33 | ~e1.7 -> {sign, 0FFH'8, z0[23:1]} : 0; (*overflow*) 34 | 35 | R := r1[23:0]; 36 | Q := {q0[24:0], ~d.24}; 37 | S := run -> S+1 : 0 38 | END FPDivider. 39 | -------------------------------------------------------------------------------- /people.inf.ethz.ch/wirth/Lola/Sources/FPMultiplier.Lola.txt: -------------------------------------------------------------------------------- 1 | MODULE FPMultiplier( (*NW 28.10.2016*) 2 | IN clk, run: BIT; x, y: WORD; 3 | OUT stall: BIT; z: WORD); 4 | 5 | REG (clk) S: [5] BIT; (*state*) 6 | P: [48] BIT; (*product*) 7 | 8 | VAR sign: BIT; 9 | xe, ye: [8] BIT; 10 | e0, e1: [9] BIT; 11 | w0: [24] BIT; 12 | w1, z0: [25] BIT; 13 | 14 | BEGIN sign := x.31 ^ y.31; (*xor*) 15 | xe := x[30:23]; ye := y[30:23]; 16 | e0 := {0'1, xe} + {0'1, ye}; 17 | e1 := e0 - 127 + {0'8, P.47}; 18 | stall := run & (S # 25); 19 | w0 := P.0 -> {1'1, y[22:0]} : 0; 20 | w1 := {0'1, P[47:24]} + {0'1, w0}; 21 | 22 | P := (S = 0) -> {0'24, 1'1, x[22:0]} : {w1, P[23:1]}; 23 | S := run -> S+1 : 0; 24 | 25 | z0 := P.47 -> P[47:23]+1 : P[46:22]+1; (*round & normalize*) 26 | z := (xe = 0) | (ye = 0) -> 0 : 27 | ~e1.8 -> {sign, e1[7:0], z0[23:1]} : 28 | ~e1.7 -> {sign, 0FFH'8, z0[23:1]} : 0; (*overflow*) 29 | END FPMultiplier. 30 | 31 | MODULE FPMultiplier( 32 | IN clk, run: BIT; x, y: WORD; 33 | OUT stall: BIT; z: WORD); 34 | 35 | REG (clk) S: [5] BIT; (*state*) 36 | B2, A2: [24] BIT; 37 | 38 | VAR sign: BIT; 39 | xe, ye: [8] BIT; 40 | e0, e1: [9] BIT; 41 | B0: [25] BIT; 42 | B00, B01, B1, A1, A0, z0: [24] BIT; 43 | 44 | BEGIN sign := x.31 ^ y.31; (*xor*) 45 | xe := x[30:23]; ye := y[30:23]; e0 := {0'1, xe} + {0'1, ye}; 46 | B00 := (S = 0) -> 0 : B2; 47 | B01 := A0.0 -> {1'1, y[22:0]} : 0; 48 | B0 := {0'1, B00} + {0'1, B01}; 49 | B1 := B0[24:1]; 50 | A0 := (S = 0) -> {1'1, x[22:0]} : A2; 51 | A1 := {B0.0, A0[23:1]}; 52 | 53 | e1 := e0 - 127 + B1.23; 54 | z0 := B1.23 -> B1 : {B1[22:0], A1.23}; 55 | z := (xe = 0) | (ye = 0) -> 0 : 56 | ~e1.8 -> {sign, e1[7:0], z0[22:0]} : 57 | ~e1.7 -> {sign, 0FFH'8, z0[22:0]} : 0; (*overflow*) 58 | stall := run & (S # 23); 59 | 60 | B2 := B1; A2 := A1; 61 | S := run -> S+1 : 0; 62 | END FPMultiplier. 63 | -------------------------------------------------------------------------------- /people.inf.ethz.ch/wirth/Lola/Sources/LSB.Mod.txt: -------------------------------------------------------------------------------- 1 | MODULE LSB; (*Lola System Compiler Base LSBX, 26.9.2015*) 2 | IMPORT Texts, Oberon; 3 | 4 | CONST 5 | bit* = 0; array* = 1; unit* = 2; (*type forms*) 6 | 7 | (*tags in output*) const* = 1; typ* = 2; var* = 3; lit* = 4; sel* = 7; range* = 8; cons* = 9; 8 | repl* = 10; not* = 11; and* = 12; mul* = 13; div* = 14; or* = 15; xor* = 16; add* = 17; sub* = 18; 9 | eql* = 20; neq* = 21; lss* = 22; geq* = 23; leq* = 24; gtr* = 25; 10 | then* = 30; else* = 31; ts* = 32; next* = 33; 11 | 12 | TYPE 13 | Item* = POINTER TO ItemDesc; 14 | Object* = POINTER TO ObjDesc; 15 | Type* = POINTER TO TypeDesc; 16 | ArrayType* = POINTER TO ArrayTypeDesc; 17 | UnitType* = POINTER TO UnitTypeDesc; 18 | 19 | ItemDesc* = RECORD 20 | tag*: INTEGER; 21 | type*: Type; 22 | val*, size*: LONGINT; 23 | a*, b*: Item 24 | END ; 25 | 26 | ObjDesc* = RECORD (ItemDesc) 27 | next*: Object; 28 | name*: ARRAY 32 OF CHAR; 29 | marked*: BOOLEAN 30 | END ; 31 | 32 | TypeDesc* = RECORD len*, size*: LONGINT; typobj*: Object END ; 33 | ArrayTypeDesc* = RECORD (TypeDesc) eltyp*: Type END ; 34 | UnitTypeDesc* = RECORD (TypeDesc) firstobj*: Object END ; 35 | 36 | VAR root*, top*: Object; 37 | bitType*, integer*, string*: Type; 38 | byteType*, wordType*: ArrayType; 39 | modname*: ARRAY 32 OF CHAR; 40 | 41 | PROCEDURE Register*(name: ARRAY OF CHAR; list: Object); 42 | BEGIN modname := name; top := list 43 | END Register; 44 | 45 | BEGIN NEW(bitType); bitType.len := 0; bitType.size := 1; NEW(integer); NEW(string); 46 | NEW(byteType); byteType.len := 8; byteType.size := 8; byteType.eltyp := bitType; 47 | NEW(wordType); wordType.len := 32; wordType.size := 32; wordType.eltyp := bitType; 48 | NEW(root); root.tag := typ; root.name := "WORD"; root.type := wordType; root.next := NIL; 49 | NEW(top); top.tag := typ; top.name := "BYTE"; top.type := byteType; top.next := root; root := top; 50 | NEW(top); top.tag := typ; top.name := "BIT"; top.type := bitType; top.next := root; root := top 51 | END LSB. 52 | 53 | -------------------------------------------------------------------------------- /people.inf.ethz.ch/wirth/Lola/Sources/LSP.Mod.txt: -------------------------------------------------------------------------------- 1 | MODULE LSP; (*display data structure; NW 28.8.2015*) 2 | IMPORT Texts, Oberon, LSB; 3 | 4 | VAR W: Texts.Writer; 5 | C: ARRAY 64, 6 OF CHAR; 6 | 7 | PROCEDURE PrintType(typ: LSB.Type); 8 | VAR obj: LSB.Object; 9 | BEGIN 10 | IF typ IS LSB.ArrayType THEN 11 | Texts.Write(W, "["); Texts.WriteInt(W, typ.len, 1); Texts.Write(W, "]"); PrintType(typ(LSB.ArrayType).eltyp) 12 | ELSIF typ IS LSB.UnitType THEN 13 | Texts.WriteString(W, "UnitType "); obj := typ(LSB.UnitType).firstobj; 14 | ELSE Texts.WriteString(W, "BIT") 15 | END ; 16 | Texts.Append(Oberon.Log, W.buf) 17 | END PrintType; 18 | 19 | PROCEDURE PrintTree(x: LSB.Item; n: INTEGER); 20 | VAR i: INTEGER; 21 | BEGIN 22 | IF x # NIL THEN i := n; 23 | IF x IS LSB.Object THEN 24 | WHILE i > 0 DO Texts.Write(W, 9X); DEC(i) END ; 25 | Texts.WriteString(W, x(LSB.Object).name); Texts.WriteLn(W) 26 | ELSE 27 | PrintTree(x.a, n+1); 28 | WHILE i > 0 DO Texts.Write(W, 9X); DEC(i) END ; 29 | IF x.tag = LSB.lit THEN Texts. WriteInt(W, x.val, 1) ELSE Texts.WriteString(W, C[x.tag]); END ; 30 | Texts.WriteLn(W); 31 | PrintTree(x.b, n+1) 32 | END 33 | END 34 | END PrintTree; 35 | 36 | PROCEDURE PrintObj(obj: LSB.Object; n: INTEGER); 37 | VAR apar: LSB.Item; obj1: LSB.Object; 38 | BEGIN 39 | IF n > 0 THEN Texts.Write(W, 9X) END ; 40 | Texts.WriteString(W, C[obj.tag]); Texts.Write(W, " "); Texts.WriteString(W, obj.name); Texts.Append(Oberon.Log, W.buf); 41 | IF obj.tag = LSB.const THEN Texts.WriteString(W, " = "); PrintTree(obj.b, 1); Texts.WriteLn(W) 42 | ELSIF obj.tag = LSB.typ THEN 43 | IF obj.type IS LSB.UnitType THEN (*formal param list*) 44 | obj1 := obj.type(LSB.UnitType).firstobj; 45 | Texts.WriteString(W, " BEGIN "); Texts.WriteLn(W); 46 | WHILE (obj1 # NIL) & (obj1 # LSB.root) DO PrintObj(obj1, 0); obj1 := obj1.next END ; 47 | Texts.WriteString(W, "END"); Texts.WriteLn(W) 48 | ELSE PrintType(obj.type) 49 | END 50 | ELSE (*var*) Texts.WriteString(W, ": "); 51 | IF obj.type IS LSB.UnitType THEN 52 | Texts.WriteString(W, obj.type.typobj.name); 53 | apar := obj.b; Texts.WriteString(W, " ["); (*actual param list*) 54 | WHILE apar # NIL DO PrintTree(apar.b, 1); apar := apar.a END ; 55 | Texts.Write(W, "]"); Texts.WriteLn(W) 56 | ELSE PrintType(obj.type); 57 | Texts.WriteString(W, " #"); Texts.WriteInt(W, obj.val, 1); 58 | IF obj.a # NIL THEN 59 | IF obj.val = 0 THEN Texts.WriteString(W, " CLK") ELSIF obj.val = 1 THEN (*indexed*) Texts.WriteString(W, " DEMUX") END ; 60 | PrintTree(obj.a, 1) 61 | END ; 62 | IF obj.b # NIL THEN Texts.WriteString(W, " := "); Texts.WriteLn(W); PrintTree(obj.b, 1) 63 | ELSE Texts.WriteLn(W) 64 | END 65 | END 66 | END ; 67 | Texts.Append(Oberon.Log, W.buf) 68 | END PrintObj; 69 | 70 | PROCEDURE List*; 71 | VAR obj: LSB.Object; 72 | BEGIN obj := LSB.top; 73 | Texts.WriteString(W, "listing "); Texts.WriteString(W, LSB.modname); Texts.WriteLn(W); 74 | WHILE (obj # LSB.root) & (obj # NIL) DO PrintObj(obj, 0); obj := obj.next END ; 75 | Texts.Append(Oberon.Log, W.buf) 76 | END List; 77 | 78 | BEGIN Texts.OpenWriter(W); 79 | C[LSB.const] := "CONST"; C[LSB.typ] := "TYPE"; C[LSB.var] := "VAR"; 80 | C[LSB.lit] := "LIT"; C[LSB.sel] := "MUX"; C[LSB.range] := ": "; C[LSB.cons] := ", "; C[LSB.repl] := "**"; 81 | C[LSB.or] := "| "; C[LSB.xor] := "^ "; C[LSB.and] := "& "; C[LSB.not] := "~ "; 82 | C[LSB.add] := "+ "; C[LSB.sub] := "- "; C[LSB.mul] := "* "; C[LSB.div] := "/ "; 83 | C[LSB.eql] := "= "; C[LSB.neq] := "# "; C[LSB.lss] := "< "; C[LSB.geq] := ">="; C[LSB.leq] := "<="; C[LSB.gtr] := "> "; 84 | C[LSB.then] := " -> "; C[LSB.else] := " :: "; C[LSB.ts] := "TS "; C[LSB.next] := "--" 85 | END LSP. 86 | -------------------------------------------------------------------------------- /people.inf.ethz.ch/wirth/Lola/Sources/LeftShifter.Lola.txt: -------------------------------------------------------------------------------- 1 | MODULE LeftShifter( (*NW 10.11.2016*) 2 | IN x: WORD; sc: [5] BIT; 3 | OUT y: WORD); 4 | 5 | VAR sc0, sc1: [2] BIT; 6 | t1, t2: WORD; 7 | 8 | BEGIN sc0 := sc[1:0]; sc1 := sc[3:2]; 9 | t1 := (sc0 = 3) -> {x[28:0], 0'3} : 10 | (sc0 = 2) -> {x[29:0], 0'2} : 11 | (sc0 = 1) -> {x[30:0], 0'1} : x; 12 | t2 := (sc1 = 3) -> {t1[19:0], 0'12} : 13 | (sc1 = 2) -> {t1[23:0], 0'8} : 14 | (sc1 = 1) -> {t1[27:0], 0'4} : t1; 15 | y := sc.4 -> {t2[15:0], 0'16} : t2 16 | END LeftShifter. 17 | 18 | -------------------------------------------------------------------------------- /people.inf.ethz.ch/wirth/Lola/Sources/MouseP.Lola.txt: -------------------------------------------------------------------------------- 1 | MODULE MouseP ( (*NW 7.9.2015*) 2 | IN clk, rst: BIT; 3 | INOUT msclk, msdat: BIT; 4 | OUT out: [28] BIT); 5 | (* init mouse cmd F4 (start reporting) with start, parity and stop bits added *) 6 | CONST InitBuf = 0FFFFFDE8H; (* 1...1 1 0 1111 0100 0 *) 7 | REG (clk) x, y: [10] BIT; (*counters*) 8 | btns: [3] BIT; 9 | Q0, Q1, run: BIT; 10 | shreg: [32] BIT; 11 | VAR shift, endbit, reply: BIT; 12 | dx, dy: [10] BIT; 13 | msclk0, msdat0: BIT; 14 | BEGIN TS(msclk, msclk0, 0'1, rst); 15 | TS(msdat, msdat0, 0'1, run | shreg.0); 16 | shift := Q1 & ~Q0; (*falling edge detector*) 17 | reply := ~run & ~shreg.1; (*start bit of echoed initBuf, if response*) 18 | endbit := run & ~shreg.0; (*normal packet received*) 19 | dx := {shreg.5 !2, shreg.7 -> 0'8 : shreg[19:12]}; (*sign + ovfl*) 20 | dy := {shreg.6 !2, shreg.8 -> 0'8 : shreg[30:23]}; (*sign + ovfl*) 21 | out := {run, btns, 0'2, y, 0'2, x}; 22 | 23 | run := rst & (reply | run); 24 | Q0 := msclk0; Q1 := Q0; (*edhe detector*) 25 | shreg := ~rst -> 0FFFFFDE8H: 26 | (endbit | reply) -> 0FFFFFFFFH'32: 27 | shift -> {msdat0, shreg[31:1]} : shreg; 28 | x := ~rst -> 0'10 : endbit -> x + dx : x; 29 | y := ~rst -> 0'10 : endbit -> y + dy : y; 30 | btns := ~rst -> 0'3 : endbit -> {shreg.1, shreg.3, shreg.2} : btns 31 | END MouseP. 32 | 33 | MODULE MouseP ( 34 | IN clk, rst, msdat: BIT; 35 | INOUT msclk: BIT; 36 | OUT out: [28] BIT); 37 | 38 | CONST InitBuf := 0; (*0FFFFFBE8H; hex*) 39 | TYPE IOBUF = MODULE (IN I: BIT; OUT O: BIT; INOUT IO: BIT; IN T: BIT) ^; 40 | REG x, y: [10] BIT; (*counters*) 41 | btns: [3] BIT; 42 | Q0, Q1, run: BIT; 43 | shreg: [32] BIT; 44 | iobuf: IOBUF; 45 | VAR shift, endbit, reply, q: BIT; 46 | dx, dy: [10] BIT; 47 | BEGIN iobuf (0, q msclk, rst); 48 | shift := Q1 & ~Q0; (*falling edge detector*) 49 | reply := ~run & ~shreg.11; (*start bit of echoed initBuf, if response*) 50 | endbit := run & ~shreg.0; (*normal packet received*) 51 | dx := {shreg.5 !2, shreg.7 -> 0'8 : shreg[19:12]}; (*sign + ovfl*) 52 | dy := {shreg.6 !2, shreg.8 -> 0'8 : shreg[30:23]}; (*sign + ovfl*) 53 | out := {run, btns, 0'2, y, 0'2, x}; 54 | 55 | run := rst & (reply | run); 56 | Q0 := q; Q1 := Q0; 57 | shreg := ~rst -> InitBuf : (endbit | reply) -> 0FFFFFFFFH'32: shift -> {msdat, shreg[31:1]} : shreg; 58 | x := ~rst -> 0'10 : endbit -> x + dx : x; 59 | y := ~rst -> 0'10 : endbit -> y + dy : y; 60 | btns := ~rst -> 0'3 : endbit -> {shreg.1, shreg.3, shreg.2} : btns 61 | END MouseP. 62 | 63 | MODULE MouseP ( 64 | IN clk, rst: BIT; 65 | INOUT io: [2] BIT; 66 | OUT out: [28] BIT); 67 | 68 | (* init mouse cmd F4 (start reporting) with start, parity and stop bits added *) 69 | CONST InitBuf := 0FFFFFDE8H; (* 1...1 1 0 1111 0100 0 *) 70 | TYPE PS2BUF = MODULE (OUT O: [2] BIT; INOUT IO: [2] BIT; IN T: [2] BIT) ^; 71 | REG x, y: [10] BIT; (*counters*) 72 | btns: [3] BIT; 73 | Q0, Q1, run: BIT; 74 | shreg: [32] BIT; 75 | VAR shift, endbit, reply: BIT; 76 | dx, dy: [10] BIT; 77 | in: [2] BIT; 78 | ps2buf: PS2BUF; 79 | BEGIN ps2buf(in, io, {run | shreg[0], rst}); (*open-collector wiring*) 80 | shift := Q1 & ~Q0; (*falling edge detector*) 81 | reply := ~run & ~shreg.11; (*start bit of echoed initBuf, if response*) 82 | endbit := run & ~shreg.0; (*normal packet received*) 83 | dx := {shreg.5 !2, shreg.7 -> 0'8 : shreg[19:12]}; (*sign + ovfl*) 84 | dy := {shreg.6 !2, shreg.8 -> 0'8 : shreg[30:23]}; (*sign + ovfl*) 85 | out := {run, btns, 0'2, y, 0'2, x}; 86 | 87 | run := rst & (reply | run); 88 | Q0 := in[0]; Q1 := Q0; 89 | shreg := ~rst -> InitBuf : (endbit | reply) -> 0FFFFFFFFH'32: shift -> {in[1], shreg[31:1]} : shreg; 90 | x := ~rst -> 0'10 : endbit -> x + dx : x; 91 | y := ~rst -> 0'10 : endbit -> y + dy : y; 92 | btns := ~rst -> 0'3 : endbit -> {shreg.1, shreg.3, shreg.2} : btns 93 | END MouseP. 94 | -------------------------------------------------------------------------------- /people.inf.ethz.ch/wirth/Lola/Sources/Multiplier.Lola.txt: -------------------------------------------------------------------------------- 1 | MODULE Multiplier ( (*NW 13.9.2014*) 2 | IN clk, run, u: BIT; 3 | OUT stall: BIT; 4 | IN x, y: WORD; (*32 bit*) 5 | OUT z: [64] BIT); 6 | 7 | REG (clk) S: [6] BIT; (*state*) 8 | P: [64] BIT; (*product*) 9 | VAR w0: WORD; 10 | w1: [33] BIT; 11 | 12 | BEGIN stall := run & (S # 33); 13 | w0 := P.0 -> y : 0; 14 | w1 := (S =32) & u -> {P.63, P[63:32]} - {w0.31, w0} : {P.63, P[63:32]} + {w0.31, w0}; 15 | S := run -> S+1 : 0; 16 | P := (S = 0) -> {0'32, x} : {w1[32:0], P[31:1]}; 17 | z := P 18 | END Multiplier. 19 | -------------------------------------------------------------------------------- /people.inf.ethz.ch/wirth/Lola/Sources/PS2.Lola.txt: -------------------------------------------------------------------------------- 1 | MODULE PS2 ( 2 | IN clk, rst, done: BIT; 3 | OUT rdy, shift: BIT; 4 | OUT data: BYTE; 5 | IN PS2C, PS2D: BIT); 6 | 7 | REG (clk) 8 | Q0, Q1: BIT; (*synchronizer and falling edge detector*) 9 | shreg: [11] BIT; 10 | inptr, outptr: [4] BIT; 11 | fifo: [16] BYTE; 12 | VAR endbit: BIT; 13 | 14 | BEGIN endbit := ~shreg.0; (*start bit reached correct pos*) 15 | shift := Q1 & ~Q0; 16 | Q0 := PS2C; Q1 := Q0; 17 | data := fifo[outptr]; 18 | rdy := (inptr # outptr); 19 | 20 | shreg := (~rst | endbit) -> 7FFH'11: 21 | shift -> {PS2D, shreg[10:1]} : shreg; 22 | outptr := ~rst -> 0 : rdy & done -> outptr + 1 : outptr; 23 | inptr := ~rst -> 0 : endbit -> inptr + 1 : inptr; 24 | fifo[inptr] := endbit -> shreg[8:1] : fifo[inptr]; 25 | END PS2. 26 | -------------------------------------------------------------------------------- /people.inf.ethz.ch/wirth/Lola/Sources/RS232R.Lola.txt: -------------------------------------------------------------------------------- 1 | MODULE RS232R ( (*NW 10.8.2015*) 2 | IN clk, rst, done, RxD, fsel: BIT; 3 | OUT rdy: BIT; data: BYTE); 4 | REG (clk) run, stat: BIT; 5 | Q0, Q1: BIT; (*synchronizer and edge detector*) 6 | tick: [12] BIT; 7 | bitcnt: [4] BIT; 8 | shreg: BYTE; 9 | VAR endtick, midtick, endbit: BIT; 10 | limit: [12] BIT; 11 | BEGIN 12 | limit := fsel -> 217 : 1302; 13 | endtick := tick = limit; 14 | midtick := tick = {0'1, limit[11:1]}; (*limit/2*) 15 | endbit := bitcnt = 8; 16 | data := shreg; 17 | rdy := stat; 18 | 19 | Q0 := RxD; Q1 := Q0; 20 | run := (Q1 & ~Q0) | ~(~rst | endtick & endbit) & run; 21 | tick := (run & ~endtick) -> tick + 1 : 0; 22 | bitcnt := (endtick & ~endbit) -> bitcnt + 1 : 23 | (endtick & endbit) -> 0 : bitcnt; 24 | shreg := midtick -> {Q1, shreg[7:1]} : shreg; 25 | stat := (endtick & endbit) | ~(~rst | done) & stat 26 | END RS232R. 27 | 28 | -------------------------------------------------------------------------------- /people.inf.ethz.ch/wirth/Lola/Sources/RS232T.Lola.txt: -------------------------------------------------------------------------------- 1 | MODULE RS232T (IN clk, rst: BIT; (*NW 15.9.2014*) 2 | IN start, fsel: BIT; (*request to send a byte / freq select*) 3 | IN data: BYTE; OUT rdy, TxD: BIT); 4 | REG (clk) run: BIT; 5 | tick: [12] BIT; 6 | bitcnt: [4] BIT; 7 | shreg: [9] BIT; 8 | VAR endtick, endbit: BIT; 9 | limit: [12] BIT; 10 | BEGIN limit := fsel -> 217 : 1302; 11 | endtick := tick = limit; 12 | endbit := bitcnt = 9; 13 | rdy := ~run; 14 | TxD := shreg.0; 15 | 16 | run := (~rst | endtick & endbit) -> 0 : start -> 1 : run; 17 | tick := (run & ~endtick) -> tick + 1 : 0; 18 | bitcnt := (endtick & ~endbit) -> bitcnt + 1 : 19 | (endtick & endbit) -> 0'4 : bitcnt; 20 | shreg := ~rst -> 1 : 21 | start -> {data, 0'1} : 22 | endtick -> {1'1, shreg[8:1]} : shreg; 23 | END RS232T. 24 | -------------------------------------------------------------------------------- /people.inf.ethz.ch/wirth/Lola/Sources/RightShifter.Lola.txt: -------------------------------------------------------------------------------- 1 | MODULE RightShifter( (*NW 11.11.2016*) 2 | IN x: WORD; sc: [5] BIT; md: BIT; (*md = 0 -> rotate; md = 1 -=> arith shift*) 3 | OUT y: WORD); 4 | 5 | VAR sc0, sc1: [2] BIT; 6 | s1, s2: WORD; 7 | 8 | BEGIN sc0 := sc[1:0]; sc1 := sc[3:2]; 9 | s1 := (sc0 = 3) -> {(md -> x[2:0] : {x.31 ! 3}), x[31:3]} : 10 | (sc0 = 2) -> {(md -> x[1:0] : {x.31 ! 2}), x[31:2]} : 11 | (sc0 = 1) -> {(md -> x.0 : x.31), x[31:1]} : x; 12 | s2 := (sc1 = 3) -> {(md -> s1[11:0] : {x.31 ! 12}), s1[31:12]} : 13 | (sc1 = 2) -> {(md -> s1[7:0] : {x.31 ! 8}), s1[31:8]} : 14 | (sc1 = 1) -> {(md -> s1[3:0] : {x.31 ! 4}), s1[31:4]} : s1; 15 | y := sc.4 -> {(md -> s2[15:0] : {s2.31 ! 16}), s2[31:16]} : s2; 16 | END RightShifter. 17 | -------------------------------------------------------------------------------- /people.inf.ethz.ch/wirth/Lola/Sources/SPI.Lola.txt: -------------------------------------------------------------------------------- 1 | MODULE SPI ( 2 | IN clk, rst, start, fast: BIT; dataTx: WORD; 3 | OUT dataRx: WORD; rdy: BIT; 4 | IN MISO: BIT; 5 | OUT MOSI, SCLK: BIT); 6 | 7 | REG (clk) rdyR: BIT; 8 | shreg: WORD; 9 | tick: [6] BIT; 10 | bitcnt: [5] BIT; 11 | VAR endbit, endtick: BIT; 12 | 13 | BEGIN endtick := fast -> (tick = 1) : (tick = 63); (*25 MHz clock*) 14 | endbit := fast -> (bitcnt = 31) : (bitcnt = 7); 15 | rdy := rdyR; 16 | dataRx := fast -> shreg : {0'24, shreg[7:0]}; 17 | MOSI := (~rst | rdyR) -> 1 : shreg.7; 18 | SCLK := (~rst | rdyR) -> 1 : (fast -> tick.0 : tick.5); 19 | 20 | tick := (~rst | rdyR | endtick) -> 0 : tick + 1; 21 | rdyR := (~rst | endtick & endbit) | ~start & rdyR; 22 | bitcnt := (~rst | start) -> 0 : (endtick & ~endbit) -> bitcnt + 1 : bitcnt; 23 | shreg := ~rst -> $FFFFFFFF'32 : start -> dataTx : 24 | endtick -> {shreg[30:24], MISO, shreg[22:16], shreg[31], shreg[14:8], shreg[23], shreg[6:0], (fast -> shreg[15] : MISO)} : shreg; 25 | END SPI. 26 | -------------------------------------------------------------------------------- /people.inf.ethz.ch/wirth/Lola/Sources/SmallPrograms.Lola.txt: -------------------------------------------------------------------------------- 1 | (* LSC.Compile @ LSV.List Test.Lola.v *) 2 | 3 | MODULE Counter (IN CLK50M, rstIn: BIT; 4 | IN swi: BYTE; OUT leds: BYTE); 5 | REG (CLK50M) rst: BIT; 6 | cnt0: [16] BIT; (*milliseconds*) 7 | cnt1: [10] BIT; (*half seconds*) 8 | cnt2: [8] BIT; 9 | VAR tick0, tick1: BIT; 10 | BEGIN leds := swi.7 -> swi : cnt2; 11 | tick0 := (cnt0 = 24999); 12 | tick1 := tick0 & (cnt1 = 499); 13 | rst := ~rstIn; 14 | cnt0 := ~rst -> 0 : tick0 -> 0 : cnt0 + 1; 15 | cnt1 := ~rst -> 0 : tick1 -> 0 : cnt1 + tick0; 16 | cnt2 := ~rst -> 0 : cnt2 + tick1 17 | END Counter. 18 | 19 | MODULE Shifter(IN CLK50M, rstIn: BIT; 20 | IN swi: BYTE; OUT leds: BYTE); 21 | REG (CLK50M) rst, up: BIT; 22 | cnt0: [16] BIT; (*milliseconds*) 23 | cnt1: [10] BIT; (*half seconds*) 24 | shreg: [8] BIT; 25 | VAR tick0, tick1: BIT; 26 | BEGIN leds := swi.7 -> swi : shreg; 27 | tick0 := (cnt0 = 24999); 28 | tick1 := tick0 & (cnt1 = 499); 29 | rst := ~rstIn; 30 | cnt0 := ~rst -> 0 : tick0 -> 0 : cnt0 + 1; 31 | cnt1 := ~rst -> 0 : tick1 -> 0 : cnt1 + tick0; 32 | shreg := ~rst -> 1'8 : 33 | ~tick1 -> shreg : 34 | up -> {shreg[6:0], 0'1} : {0'1, shreg[7:1]}; 35 | up := shreg.0 -> 1 : shreg.7 -> 0 : up 36 | END Shifter. 37 | -------------------------------------------------------------------------------- /people.inf.ethz.ch/wirth/Lola/Sources/VID.Lola.txt: -------------------------------------------------------------------------------- 1 | MODULE VID ( 2 | IN clk, inv: BIT; 3 | viddata: WORD; 4 | OUT req: BIT; (*SRAM read request*) 5 | vidadr: [18] BIT; 6 | hsync, vsync: BIT; (*to display*) 7 | RGB: [3] BIT); 8 | 9 | CONST Org = 37FC0H; (* DFF00: adr of vcnt=1023 *) 10 | TYPE DCMX3 = MODULE (IN CLKIN: BIT; OUT CLKFX: BIT) ^; 11 | VAR hend, vend, vblank, xfer, vid, pclk: BIT; 12 | dcmx3: DCMX3; 13 | REG (pclk) hcnt: [11] BIT; 14 | vcnt: [10] BIT; 15 | hblank: BIT; 16 | pixbuf, vidbuf: WORD; 17 | REG (clk) req1: BIT; 18 | hword: [5] BIT; (*from hcnt, but latched in the clk domain*) 19 | 20 | BEGIN dcmx3 (clk, pclk); (* pixel clock generation *) 21 | hend := (hcnt = 1343); vend := (vcnt = 801); 22 | vblank := (vcnt.8 & vcnt.9); (*vcnt >= 768*) 23 | hsync := ~((hcnt >= 1086) & (hcnt < 1190)); (*-ve polarity*) 24 | vsync := (vcnt >= 771) & (vcnt < 776); (*+ve polarity*) 25 | xfer := (hcnt[4:0] = 6'5); (*data delay > hcnt cycle + req cycle*) 26 | vid := (pixbuf.0 ^ inv) & ~hblank & ~ vblank; 27 | RGB := {vid, vid, vid}; 28 | vidadr := Org + {0'3, ~vcnt, hword}; 29 | (*on pclk:*) 30 | hcnt := hend -> 0 : hcnt + 1; 31 | vcnt := hend -> (vend -> 0 : vcnt + 1) : vcnt; 32 | hblank := xfer -> hcnt.10 : hblank; (*hcnt >= 1024*) 33 | pixbuf := xfer -> vidbuf : {0'1, pixbuf[31:1]}; 34 | (*on clk:*) 35 | hword := hcnt[9:5]; 36 | req := req1; req1 := ~vblank & ~hcnt.10 & (hcnt.5 ^ hword.0); 37 | vidbuf := req -> viddata : vidbuf 38 | END VID. 39 | 40 | MODULE VID ( 41 | IN clk, inv: BIT; 42 | viddata: WORD; 43 | OUT req: BIT; (*SRAM read request*) 44 | vidadr: [18] BIT; 45 | hsync, vsync: BIT; 46 | RGB: [3] BIT); 47 | 48 | CONST Org := 0DFF00H; 49 | REG (clk) hcnt, vcnt: [10] BIT; 50 | buffer: WORD; (*from hcnt, but latched in the clk domain*) 51 | hblank1: BIT; 52 | VAR hend, vend, hblank, vblank, pixel, vid: BIT; 53 | 54 | BEGIN (*25MHz clock; 2 pixels per cycle*) 55 | hend := (hcnt = 591); 56 | vend := (vcnt = 791); 57 | hblank := hcnt.9; (*hcnt = 512*) 58 | vblank := vcnt.8 & vcnt.9; (*vcnt >= 768*) 59 | hsync := (hcnt >= 537) & (hcnt < 553); 60 | vsync := ~((vcnt >= 772) & (vcnt < 776)); 61 | 62 | vidadr := {0'3, ~vcnt, hcnt[8:4]} + 37FC0H'18; 63 | req := ~vblank & ~hcnt.9 & (hcnt[3:0] = 0'4); 64 | pixel := clk -> buffer.0 : buffer.1; 65 | vid := (pixel ^ inv) & ~hblank1 & ~vblank; 66 | RGB := {vid, vid, vid}; 67 | 68 | hcnt := hend -> 0 : hcnt+1; 69 | vcnt := hend -> (vend -> 0 : vcnt+1) : vcnt; 70 | hblank1 := hblank; 71 | buffer := req -> viddata : {0'2, buffer[31:2]} 72 | END VID. 73 | 74 | -------------------------------------------------------------------------------- /people.inf.ethz.ch/wirth/Lola/index.html: -------------------------------------------------------------------------------- 1 | 2 |
3 | 4 | 5 |Lola Compiler for Project Oberon, 2013 Edition
23 | 24 | LSS.Mod 25 | LSB.Mod 26 | LSP.Mod 27 | LSC.Mod 28 | LSV.ModLola Definition of RISC5 Computer
34 | 35 | RISC5.Lola 36 | LeftShifter.Lola 37 | RightShifter.Lola 38 | Multiplier.Lola 39 | Divider.Lola57 | Back to my home page. 58 | 59 | 60 | 61 | -------------------------------------------------------------------------------- /people.inf.ethz.ch/wirth/Miscellaneous/ComputersAndComputing.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Spirit-of-Oberon/wirth-personal/874a6024c1b6b1eff0208225e1004bc1aa62fb79/people.inf.ethz.ch/wirth/Miscellaneous/ComputersAndComputing.pdf -------------------------------------------------------------------------------- /people.inf.ethz.ch/wirth/Miscellaneous/CounterShifter.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Spirit-of-Oberon/wirth-personal/874a6024c1b6b1eff0208225e1004bc1aa62fb79/people.inf.ethz.ch/wirth/Miscellaneous/CounterShifter.pdf -------------------------------------------------------------------------------- /people.inf.ethz.ch/wirth/Miscellaneous/Denkplatz.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Spirit-of-Oberon/wirth-personal/874a6024c1b6b1eff0208225e1004bc1aa62fb79/people.inf.ethz.ch/wirth/Miscellaneous/Denkplatz.pdf -------------------------------------------------------------------------------- /people.inf.ethz.ch/wirth/Miscellaneous/Division.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Spirit-of-Oberon/wirth-personal/874a6024c1b6b1eff0208225e1004bc1aa62fb79/people.inf.ethz.ch/wirth/Miscellaneous/Division.pdf -------------------------------------------------------------------------------- /people.inf.ethz.ch/wirth/Miscellaneous/IEEE-Annals.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Spirit-of-Oberon/wirth-personal/874a6024c1b6b1eff0208225e1004bc1aa62fb79/people.inf.ethz.ch/wirth/Miscellaneous/IEEE-Annals.pdf -------------------------------------------------------------------------------- /people.inf.ethz.ch/wirth/Miscellaneous/Informatik68.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Spirit-of-Oberon/wirth-personal/874a6024c1b6b1eff0208225e1004bc1aa62fb79/people.inf.ethz.ch/wirth/Miscellaneous/Informatik68.pdf -------------------------------------------------------------------------------- /people.inf.ethz.ch/wirth/Miscellaneous/Informatika2008.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Spirit-of-Oberon/wirth-personal/874a6024c1b6b1eff0208225e1004bc1aa62fb79/people.inf.ethz.ch/wirth/Miscellaneous/Informatika2008.pdf -------------------------------------------------------------------------------- /people.inf.ethz.ch/wirth/Miscellaneous/PLD.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Spirit-of-Oberon/wirth-personal/874a6024c1b6b1eff0208225e1004bc1aa62fb79/people.inf.ethz.ch/wirth/Miscellaneous/PLD.pdf -------------------------------------------------------------------------------- /people.inf.ethz.ch/wirth/Miscellaneous/Styles.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Spirit-of-Oberon/wirth-personal/874a6024c1b6b1eff0208225e1004bc1aa62fb79/people.inf.ethz.ch/wirth/Miscellaneous/Styles.pdf -------------------------------------------------------------------------------- /people.inf.ethz.ch/wirth/Miscellaneous/index.html: -------------------------------------------------------------------------------- 1 | 2 |
3 | 4 | 5 |24 | Back to my home page. 25 | 26 | 27 | 28 | -------------------------------------------------------------------------------- /people.inf.ethz.ch/wirth/Oberon/284.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Spirit-of-Oberon/wirth-personal/874a6024c1b6b1eff0208225e1004bc1aa62fb79/people.inf.ethz.ch/wirth/Oberon/284.pdf -------------------------------------------------------------------------------- /people.inf.ethz.ch/wirth/Oberon/285.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Spirit-of-Oberon/wirth-personal/874a6024c1b6b1eff0208225e1004bc1aa62fb79/people.inf.ethz.ch/wirth/Oberon/285.pdf -------------------------------------------------------------------------------- /people.inf.ethz.ch/wirth/Oberon/286.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Spirit-of-Oberon/wirth-personal/874a6024c1b6b1eff0208225e1004bc1aa62fb79/people.inf.ethz.ch/wirth/Oberon/286.pdf -------------------------------------------------------------------------------- /people.inf.ethz.ch/wirth/Oberon/Interrupts.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Spirit-of-Oberon/wirth-personal/874a6024c1b6b1eff0208225e1004bc1aa62fb79/people.inf.ethz.ch/wirth/Oberon/Interrupts.pdf -------------------------------------------------------------------------------- /people.inf.ethz.ch/wirth/Oberon/Oberon.ARM.Compiler.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Spirit-of-Oberon/wirth-personal/874a6024c1b6b1eff0208225e1004bc1aa62fb79/people.inf.ethz.ch/wirth/Oberon/Oberon.ARM.Compiler.pdf -------------------------------------------------------------------------------- /people.inf.ethz.ch/wirth/Oberon/Oberon.Report.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Spirit-of-Oberon/wirth-personal/874a6024c1b6b1eff0208225e1004bc1aa62fb79/people.inf.ethz.ch/wirth/Oberon/Oberon.Report.pdf -------------------------------------------------------------------------------- /people.inf.ethz.ch/wirth/Oberon/Oberon07.Report.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Spirit-of-Oberon/wirth-personal/874a6024c1b6b1eff0208225e1004bc1aa62fb79/people.inf.ethz.ch/wirth/Oberon/Oberon07.Report.pdf -------------------------------------------------------------------------------- /people.inf.ethz.ch/wirth/Oberon/Oberon07.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Spirit-of-Oberon/wirth-personal/874a6024c1b6b1eff0208225e1004bc1aa62fb79/people.inf.ethz.ch/wirth/Oberon/Oberon07.pdf -------------------------------------------------------------------------------- /people.inf.ethz.ch/wirth/Oberon/OberonAtAGlance.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Spirit-of-Oberon/wirth-personal/874a6024c1b6b1eff0208225e1004bc1aa62fb79/people.inf.ethz.ch/wirth/Oberon/OberonAtAGlance.pdf -------------------------------------------------------------------------------- /people.inf.ethz.ch/wirth/Oberon/PIO.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Spirit-of-Oberon/wirth-personal/874a6024c1b6b1eff0208225e1004bc1aa62fb79/people.inf.ethz.ch/wirth/Oberon/PIO.pdf -------------------------------------------------------------------------------- /people.inf.ethz.ch/wirth/Oberon/PortingOberon.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Spirit-of-Oberon/wirth-personal/874a6024c1b6b1eff0208225e1004bc1aa62fb79/people.inf.ethz.ch/wirth/Oberon/PortingOberon.pdf -------------------------------------------------------------------------------- /people.inf.ethz.ch/wirth/Oberon/SETs.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Spirit-of-Oberon/wirth-personal/874a6024c1b6b1eff0208225e1004bc1aa62fb79/people.inf.ethz.ch/wirth/Oberon/SETs.pdf -------------------------------------------------------------------------------- /people.inf.ethz.ch/wirth/Oberon/index.html: -------------------------------------------------------------------------------- 1 | 2 |
3 | 4 | 5 |64 | Back to my home page. 65 | 66 | 67 | -------------------------------------------------------------------------------- /people.inf.ethz.ch/wirth/PICL/PIC.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Spirit-of-Oberon/wirth-personal/874a6024c1b6b1eff0208225e1004bc1aa62fb79/people.inf.ethz.ch/wirth/PICL/PIC.pdf -------------------------------------------------------------------------------- /people.inf.ethz.ch/wirth/PICL/PICL.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Spirit-of-Oberon/wirth-personal/874a6024c1b6b1eff0208225e1004bc1aa62fb79/people.inf.ethz.ch/wirth/PICL/PICL.pdf -------------------------------------------------------------------------------- /people.inf.ethz.ch/wirth/PICL/PICLcompiler.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Spirit-of-Oberon/wirth-personal/874a6024c1b6b1eff0208225e1004bc1aa62fb79/people.inf.ethz.ch/wirth/PICL/PICLcompiler.pdf -------------------------------------------------------------------------------- /people.inf.ethz.ch/wirth/PICL/index.html: -------------------------------------------------------------------------------- 1 | 2 |
3 | 4 | 5 |PICL Compiler for Project Oberon, 2013 Edition
25 | 26 | PICL.Mod 27 | PICS.Mod 28 | 29 | 30 | 31 |33 | Back to my home page. 34 | 35 | 36 | -------------------------------------------------------------------------------- /people.inf.ethz.ch/wirth/ProgInOberon2004.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Spirit-of-Oberon/wirth-personal/874a6024c1b6b1eff0208225e1004bc1aa62fb79/people.inf.ethz.ch/wirth/ProgInOberon2004.pdf -------------------------------------------------------------------------------- /people.inf.ethz.ch/wirth/ProgInOberonWR.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Spirit-of-Oberon/wirth-personal/874a6024c1b6b1eff0208225e1004bc1aa62fb79/people.inf.ethz.ch/wirth/ProgInOberonWR.pdf -------------------------------------------------------------------------------- /people.inf.ethz.ch/wirth/ProjectOberon/PO.Applications.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Spirit-of-Oberon/wirth-personal/874a6024c1b6b1eff0208225e1004bc1aa62fb79/people.inf.ethz.ch/wirth/ProjectOberon/PO.Applications.pdf -------------------------------------------------------------------------------- /people.inf.ethz.ch/wirth/ProjectOberon/PO.Computer.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Spirit-of-Oberon/wirth-personal/874a6024c1b6b1eff0208225e1004bc1aa62fb79/people.inf.ethz.ch/wirth/ProjectOberon/PO.Computer.pdf -------------------------------------------------------------------------------- /people.inf.ethz.ch/wirth/ProjectOberon/PO.System.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Spirit-of-Oberon/wirth-personal/874a6024c1b6b1eff0208225e1004bc1aa62fb79/people.inf.ethz.ch/wirth/ProjectOberon/PO.System.pdf -------------------------------------------------------------------------------- /people.inf.ethz.ch/wirth/ProjectOberon/RISC5.Update.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Spirit-of-Oberon/wirth-personal/874a6024c1b6b1eff0208225e1004bc1aa62fb79/people.inf.ethz.ch/wirth/ProjectOberon/RISC5.Update.pdf -------------------------------------------------------------------------------- /people.inf.ethz.ch/wirth/ProjectOberon/Sources/Blink.Mod.txt: -------------------------------------------------------------------------------- 1 | MODULE Blink; (*NW 30.5.2013*) 2 | IMPORT SYSTEM, Oberon; 3 | VAR z: INTEGER; 4 | T: Oberon.Task; 5 | 6 | PROCEDURE Run*; 7 | BEGIN Oberon.Install(T) 8 | END Run; 9 | 10 | PROCEDURE Stop*; 11 | BEGIN Oberon.Remove(T) 12 | END Stop; 13 | 14 | PROCEDURE Tick; 15 | BEGIN z := 1-z; LED(z) 16 | END Tick; 17 | 18 | BEGIN z := 0; T := Oberon.NewTask(Tick, 500) 19 | END Blink. 20 | -------------------------------------------------------------------------------- /people.inf.ethz.ch/wirth/ProjectOberon/Sources/Checkers.Mod.txt: -------------------------------------------------------------------------------- 1 | MODULE Checkers; (*NW 4.10.90 / 10.3.2013*) 2 | IMPORT SYSTEM, Display, Viewers, Oberon, MenuViewers, TextFrames; 3 | 4 | TYPE Frame = POINTER TO FrameDesc; 5 | 6 | FrameDesc = RECORD (Display.FrameDesc) 7 | col: INTEGER 8 | END ; 9 | 10 | VAR i: INTEGER; 11 | checks: INTEGER; 12 | pat: ARRAY 17 OF INTEGER; 13 | 14 | PROCEDURE Restore(F: Frame); 15 | BEGIN Oberon.RemoveMarks(F.X, F.Y, F.W, F.H); 16 | Display.ReplConst(Display.black, F.X, F.Y, F.W, F.H, Display.replace); (*clear*) 17 | Display.ReplPattern(F.col, checks, F.X+1, F.Y, F.W-1, F.H-1, Display.paint) 18 | END Restore; 19 | 20 | PROCEDURE Handle(G: Display.Frame; VAR M: Display.FrameMsg); 21 | VAR G1: Frame; 22 | BEGIN 23 | CASE G OF Frame: 24 | CASE M OF 25 | Oberon.InputMsg: 26 | IF M.id = Oberon.track THEN Oberon.DrawMouseArrow(M.X, M.Y) END | 27 | Oberon.CopyMsg: 28 | Oberon.RemoveMarks(G.X, G.Y, G.W, G.H); NEW(G1); G1^ := G^; M.F := G1 | 29 | MenuViewers.ModifyMsg: 30 | IF (M.Y # G.Y) OR (M.H # G.H) THEN G.Y := M.Y; G.H := M.H; Restore(G) END 31 | END 32 | END 33 | END Handle; 34 | 35 | PROCEDURE Open*; 36 | VAR F: Frame; V: Viewers.Viewer; X, Y: INTEGER; 37 | BEGIN NEW(F); F.col := 14; F.handle := Handle; 38 | Oberon.AllocateUserViewer(Oberon.Par.vwr.X, X, Y); 39 | V := MenuViewers.New( 40 | TextFrames.NewMenu("CheckerViewer", "System.Close System.Copy System.Grow"), 41 | F, TextFrames.menuH, X, Y) 42 | END Open; 43 | 44 | BEGIN checks := SYSTEM.ADR(pat); pat[0] := 1010H; i := 1; 45 | REPEAT pat[i] := 0FF00FFH; INC(i) UNTIL i = 9; 46 | REPEAT pat[i] := 0FF00FF00H; INC(i) UNTIL i = 17 47 | END Checkers. 48 | -------------------------------------------------------------------------------- /people.inf.ethz.ch/wirth/ProjectOberon/Sources/Draw.Tool.txt: -------------------------------------------------------------------------------- 1 | Draw.Open XX.Graph Draw.Store 2 | Rectangles.Make Curves.MakeCircle 3 | 4 | System.SetFont Oberon10.Scn.Fnt 5 | Draw.SetWidth 2 6 | Draw.ChangeFont Oberon8.Scn.Fnt 7 | Draw.ChangeFont Oberon10b.Scn.Fnt 8 | Draw.ChangeWidth 2 9 | Draw.Macro TTL0 N02 10 | 11 | Blinkers.Make Blinkers.Blink Blinkers.Run Blinkers.Stop -------------------------------------------------------------------------------- /people.inf.ethz.ch/wirth/ProjectOberon/Sources/Fonts.Mod.txt: -------------------------------------------------------------------------------- 1 | MODULE Fonts; (*JG 18.11.90; PDR 8.6.12; NW 18.1.2019*) 2 | IMPORT SYSTEM, Files; 3 | 4 | CONST FontFileId = 0DBH; 5 | 6 | TYPE Font* = POINTER TO FontDesc; 7 | FontDesc* = RECORD 8 | name*: ARRAY 32 OF CHAR; 9 | height*, minX*, maxX*, minY*, maxY*: INTEGER; 10 | next*: Font; 11 | T: ARRAY 128 OF INTEGER; 12 | raster: ARRAY 2360 OF BYTE 13 | END ; 14 | 15 | LargeFontDesc = RECORD (FontDesc) ext: ARRAY 2560 OF BYTE END ; 16 | LargeFont = POINTER TO LargeFontDesc; 17 | RunRec = RECORD beg, end: BYTE END ; 18 | BoxRec = RECORD dx, x, y, w, h: BYTE END ; 19 | 20 | (* raster sizes: Syntax8 1367, Syntax10 1628, Syntax12 1688, Syntax14 1843, Syntax14b 1983, 21 | Syntax16 2271, Syntax20 3034, Syntac24 4274, Syntax24b 4302 *) 22 | 23 | VAR Default*, root*: Font; 24 | 25 | PROCEDURE GetPat*(fnt: Font; ch: CHAR; VAR dx, x, y, w, h, patadr: INTEGER); 26 | VAR pa: INTEGER; dxb, xb, yb, wb, hb: BYTE; 27 | BEGIN pa := fnt.T[ORD(ch) MOD 80H]; patadr := pa; 28 | SYSTEM.GET(pa-3, dxb); SYSTEM.GET(pa-2, xb); SYSTEM.GET(pa-1, yb); SYSTEM.GET(pa, wb); SYSTEM.GET(pa+1, hb); 29 | dx := dxb; x := xb; y := yb; w := wb; h := hb; 30 | IF yb < 128 THEN y := yb ELSE y := yb - 256 END 31 | END GetPat; 32 | 33 | PROCEDURE This*(name: ARRAY OF CHAR): Font; 34 | VAR F: Font; LF: LargeFont; 35 | f: Files.File; R: Files.Rider; 36 | NofRuns, NofBoxes: BYTE; 37 | NofBytes: INTEGER; 38 | height, minX, maxX, minY, maxY: BYTE; 39 | i, j, k, m, n: INTEGER; 40 | a, a0: INTEGER; 41 | b, beg, end: BYTE; 42 | run: ARRAY 16 OF RunRec; 43 | box: ARRAY 512 OF BoxRec; 44 | 45 | PROCEDURE RdInt16(VAR R: Files.Rider; VAR b0: BYTE); 46 | VAR b1: BYTE; 47 | BEGIN Files.ReadByte(R, b0); Files.ReadByte(R, b1) 48 | END RdInt16; 49 | 50 | BEGIN F := root; 51 | WHILE (F # NIL) & (name # F.name) DO F := F.next END; 52 | IF F = NIL THEN 53 | f := Files.Old(name); 54 | IF f # NIL THEN 55 | Files.Set(R, f, 0); Files.ReadByte(R, b); 56 | IF b = FontFileId THEN 57 | Files.ReadByte(R, b); (*abstraction*) 58 | Files.ReadByte(R, b); (*family*) 59 | Files.ReadByte(R, b); (*variant*) 60 | RdInt16(R, height); RdInt16(R, minX); RdInt16(R, maxX); RdInt16(R, minY); RdInt16(R, maxY); RdInt16(R, NofRuns); 61 | NofBoxes := 0; k := 0; 62 | WHILE k # NofRuns DO 63 | RdInt16(R, beg); 64 | run[k].beg := beg; RdInt16(R, end); 65 | run[k].end := end; NofBoxes := NofBoxes + end - beg; INC(k) 66 | END; 67 | NofBytes := 5; j := 0; 68 | WHILE j # NofBoxes DO 69 | RdInt16(R, box[j].dx); RdInt16(R, box[j].x); RdInt16(R, box[j].y); 70 | RdInt16(R, box[j].w); RdInt16(R, box[j].h); 71 | NofBytes := NofBytes + 5 + (box[j].w + 7) DIV 8 * box[j].h; 72 | INC(j) 73 | END; 74 | IF NofBytes < 2300 THEN NEW(F) ELSE NEW(LF); F := LF END ; 75 | F.name := name; 76 | F.height := height; F.minX := minX; F.maxX := maxX; F.maxY := maxY; 77 | IF minY >= 80H THEN F.minY := minY - 100H ELSE F.minY := minY END ; 78 | a0 := SYSTEM.ADR(F.raster); 79 | SYSTEM.PUT(a0, 0X); SYSTEM.PUT(a0+1, 0X); SYSTEM.PUT(a0+2, 0X); SYSTEM.PUT(a0+3, 0X); SYSTEM.PUT(a0+4, 0X); 80 | (*null pattern for characters not in a run*) 81 | INC(a0, 3); a := a0+2; j := 0; k := 0; m := 0; 82 | WHILE k < NofRuns DO 83 | WHILE (m < run[k].beg) & (m < 128) DO F.T[m] := a0; INC(m) END; 84 | WHILE (m < run[k].end) & (m < 128) DO 85 | F.T[m] := a+3; 86 | SYSTEM.PUT(a, box[j].dx); SYSTEM.PUT(a+1, box[j].x); SYSTEM.PUT(a+2, box[j].y); 87 | SYSTEM.PUT(a+3, box[j].w); SYSTEM.PUT(a+4, box[j].h); INC(a, 5); 88 | n := (box[j].w + 7) DIV 8 * box[j].h; 89 | WHILE n # 0 DO DEC(n); Files.ReadByte(R, b); SYSTEM.PUT(a, b); INC(a) END ; 90 | INC(j); INC(m) 91 | END; 92 | INC(k) 93 | END; 94 | WHILE m < 128 DO F.T[m] := a0; INC(m) END ; 95 | F.next := root; root := F 96 | ELSE (*bad file id*) F := Default 97 | END 98 | ELSE (*font file not available*) F := Default 99 | END 100 | END; 101 | RETURN F 102 | END This; 103 | 104 | PROCEDURE Free*; (*remove all but first two from font list*) 105 | BEGIN IF root.next # NIL THEN root.next.next := NIL END 106 | END Free; 107 | 108 | BEGIN root := NIL; Default := This("Oberon10.Scn.Fnt") 109 | END Fonts. 110 | -------------------------------------------------------------------------------- /people.inf.ethz.ch/wirth/ProjectOberon/Sources/Hilbert.Mod.txt: -------------------------------------------------------------------------------- 1 | MODULE Hilbert; (*NW 8.1.2013 for RISC*) 2 | IMPORT Display, Viewers, Texts, Oberon, MenuViewers, TextFrames; 3 | 4 | CONST Menu = "System.Close System.Copy System.Grow"; 5 | 6 | VAR x, y, d: INTEGER; 7 | A, B, C, D: PROCEDURE (i: INTEGER); 8 | 9 | PROCEDURE E; 10 | BEGIN Display.ReplConst(Display.white, x, y, d, 1, Display.paint); INC(x, d) 11 | END E; 12 | 13 | PROCEDURE N; 14 | BEGIN Display.ReplConst(Display.white, x, y, 1, d, Display.paint); INC(y, d) 15 | END N; 16 | 17 | PROCEDURE W; 18 | BEGIN DEC(x, d); Display.ReplConst(Display.white, x, y, d, 1, Display.paint) 19 | END W; 20 | 21 | PROCEDURE S; 22 | BEGIN DEC(y, d); Display.ReplConst(Display.white, x, y, 1, d, Display.paint) 23 | END S; 24 | 25 | PROCEDURE HA(i: INTEGER); 26 | BEGIN 27 | IF i > 0 THEN D(i-1); W; A(i-1); S; A(i-1); E; B(i-1) END 28 | END HA; 29 | 30 | PROCEDURE HB(i: INTEGER); 31 | BEGIN 32 | IF i > 0 THEN C(i-1); N; B(i-1); E; B(i-1); S; A(i-1) END 33 | END HB; 34 | 35 | PROCEDURE HC(i: INTEGER); 36 | BEGIN 37 | IF i > 0 THEN B(i-1); E; C(i-1); N; C(i-1); W; D(i-1) END 38 | END HC; 39 | 40 | PROCEDURE HD(i: INTEGER); 41 | BEGIN 42 | IF i > 0 THEN A(i-1); S; D(i-1); W; D(i-1); N; C(i-1) END 43 | END HD; 44 | 45 | PROCEDURE DrawHilbert(F: Display.Frame); 46 | VAR k, n, w, x0, y0: INTEGER; 47 | BEGIN k := 0; d := 8; 48 | IF F.W < F.H THEN w := F.W ELSE w := F.H END ; 49 | WHILE d*2 < w DO d := d*2; INC(k) END ; 50 | Display.ReplConst(Display.black, F.X, F.Y, F.W, F.H, Display.replace); 51 | x0 := F.W DIV 2; y0 := F.H DIV 2; n := 0; 52 | WHILE n < k DO 53 | d := d DIV 2; INC(x0, d DIV 2); INC(y0, d DIV 2); 54 | x := F.X + x0; y := F.Y + y0; INC(n); HA(n) 55 | END 56 | END DrawHilbert; 57 | 58 | PROCEDURE Handler(F: Display.Frame; VAR M: Display.FrameMsg); 59 | VAR F0: Display.Frame; 60 | BEGIN 61 | IF M IS Oberon.InputMsg THEN 62 | IF M(Oberon.InputMsg).id = Oberon.track THEN 63 | Oberon.DrawMouseArrow(M(Oberon.InputMsg).X, M(Oberon.InputMsg).Y) 64 | END 65 | ELSIF M IS MenuViewers.ModifyMsg THEN 66 | F.Y := M(MenuViewers.ModifyMsg).Y; F.H := M(MenuViewers.ModifyMsg).H; DrawHilbert(F) 67 | ELSIF M IS Oberon.ControlMsg THEN 68 | IF M(Oberon.ControlMsg).id = Oberon.neutralize THEN Oberon.RemoveMarks(F.X, F.Y, F.W, F.H) END 69 | ELSIF M IS Oberon.CopyMsg THEN 70 | NEW(F0); F0^ := F^; M(Oberon.CopyMsg).F := F0 71 | END 72 | END Handler; 73 | 74 | PROCEDURE New(): Display.Frame; 75 | VAR F: Display.Frame; 76 | BEGIN NEW(F); F.handle := Handler; RETURN F 77 | END New; 78 | 79 | PROCEDURE Draw*; 80 | VAR V: Viewers.Viewer; X, Y: INTEGER; 81 | BEGIN Oberon.AllocateUserViewer(Oberon.Par.vwr.X, X, Y); 82 | V := MenuViewers.New(TextFrames.NewMenu("Hilbert", Menu), New(), TextFrames.menuH, X, Y) 83 | END Draw; 84 | 85 | BEGIN A := HA; B := HB; C := HC; D := HD 86 | END Hilbert. 87 | -------------------------------------------------------------------------------- /people.inf.ethz.ch/wirth/ProjectOberon/Sources/Input.Mod.txt: -------------------------------------------------------------------------------- 1 | MODULE Input; (*NW 5.10.86 / 15.11.90 Ceres-2; PDR 21.4.12 / NW 15.5.2013 Ceres-4*) 2 | IMPORT SYSTEM; 3 | 4 | CONST msAdr = -40; kbdAdr = -36; 5 | VAR kbdCode: BYTE; (*last keyboard code read*) 6 | Recd, Up, Shift, Ctrl, Ext: BOOLEAN; 7 | KTabAdr: INTEGER; (*keyboard code translation table*) 8 | MW, MH, MX, MY: INTEGER; (*mouse limits and coords*) 9 | MK: SET; (*mouse keys*) 10 | 11 | (*FIFO implemented in hardware, because every read must be handled, 12 | including tracking the state of the Shift and Ctrl keys*) 13 | 14 | PROCEDURE Peek(); 15 | BEGIN 16 | IF SYSTEM.BIT(msAdr, 28) THEN 17 | SYSTEM.GET(kbdAdr, kbdCode); 18 | IF kbdCode = 0F0H THEN Up := TRUE 19 | ELSIF kbdCode = 0E0H THEN Ext := TRUE 20 | ELSE 21 | IF (kbdCode = 12H) OR (kbdCode = 59H) THEN (*shift*) Shift := ~Up 22 | ELSIF kbdCode = 14H THEN (*ctrl*) Ctrl := ~Up 23 | ELSIF ~Up THEN Recd := TRUE (*real key going down*) 24 | END ; 25 | Up := FALSE; Ext := FALSE 26 | END 27 | END; 28 | END Peek; 29 | 30 | PROCEDURE Available*(): INTEGER; 31 | BEGIN Peek(); 32 | RETURN ORD(Recd) 33 | END Available; 34 | 35 | PROCEDURE Read*(VAR ch: CHAR); 36 | BEGIN 37 | WHILE ~Recd DO Peek() END ; 38 | IF Shift OR Ctrl THEN INC(kbdCode, 80H) END; (*ctrl implies shift*) 39 | (* ch := kbdTab[kbdCode]; *) 40 | SYSTEM.GET(KTabAdr + kbdCode, ch); 41 | IF Ctrl THEN ch := CHR(ORD(ch) MOD 20H) END; 42 | Recd := FALSE 43 | END Read; 44 | 45 | PROCEDURE Mouse*(VAR keys: SET; VAR x, y: INTEGER); 46 | VAR w: INTEGER; 47 | BEGIN SYSTEM.GET(msAdr, w); 48 | keys := SYSTEM.VAL(SET, w DIV 1000000H MOD 8); 49 | x := w MOD 400H; y := (w DIV 1000H) MOD 400H; 50 | IF y >= MH THEN y := MH-1 END 51 | END Mouse; 52 | 53 | PROCEDURE SetMouseLimits*(w, h: INTEGER); 54 | BEGIN MW := w; MH := h 55 | END SetMouseLimits; 56 | 57 | PROCEDURE Init*; 58 | BEGIN Up := FALSE; Shift := FALSE; Ctrl := FALSE; Recd := FALSE; 59 | KTabAdr := SYSTEM.ADR($ 60 | 00 00 00 00 00 1A 00 00 00 00 00 00 00 09 60 00 61 | 00 00 00 00 00 71 31 00 00 00 7A 73 61 77 32 00 62 | 00 63 78 64 65 34 33 00 00 20 76 66 74 72 35 00 63 | 00 6E 62 68 67 79 36 00 00 00 6D 6A 75 37 38 00 64 | 00 2C 6B 69 6F 30 39 00 00 2E 2F 6C 3B 70 2D 00 65 | 00 00 27 00 5B 3D 00 00 00 00 0D 5D 00 5C 00 00 66 | 00 00 00 00 00 00 08 00 00 00 00 00 00 00 00 00 67 | 00 7F 00 00 00 00 1B 00 00 00 00 00 00 00 00 00 68 | 00 00 00 00 00 00 00 00 00 00 00 00 00 09 7E 00 69 | 00 00 00 00 00 51 21 00 00 00 5A 53 41 57 40 00 70 | 00 43 58 44 45 24 23 00 00 20 56 46 54 52 25 00 71 | 00 4E 42 48 47 59 5E 00 00 00 4D 4A 55 26 2A 00 72 | 00 3C 4B 49 4F 29 28 00 00 3E 3F 4C 3A 50 5F 00 73 | 00 00 22 00 7B 2B 00 00 00 00 0D 7D 00 7C 00 00 74 | 00 00 00 00 00 00 08 00 00 00 00 00 00 00 00 00 75 | 00 7F 00 00 00 00 1B 00 00 00 00 00 00 00 00 00$) 76 | END Init; 77 | 78 | BEGIN Init 79 | END Input. 80 | -------------------------------------------------------------------------------- /people.inf.ethz.ch/wirth/ProjectOberon/Sources/MacroTool.Mod.txt: -------------------------------------------------------------------------------- 1 | MODULE MacroTool; (*NW 6.8.2013*) 2 | IMPORT Texts, Oberon, Graphics, GraphicFrames; 3 | VAR W: Texts.Writer; 4 | 5 | PROCEDURE OpenMacro*; 6 | VAR F: GraphicFrames.Frame; sel: Graphics.Object; 7 | BEGIN (*expand selected macro to caret position*) 8 | F := GraphicFrames.Selected(); 9 | IF F # NIL THEN 10 | sel := F.graph.sel; 11 | IF (sel # NIL) & (sel IS Graphics.Macro) THEN 12 | GraphicFrames.Deselect(F); 13 | Graphics.OpenMac(sel(Graphics.Macro).mac, F.graph, F.mark.x - F.x, F.mark.y - F.y); 14 | GraphicFrames.Draw(F) 15 | END 16 | END 17 | END OpenMacro; 18 | 19 | PROCEDURE MakeMacro*; (*lib mac*) 20 | (*compose macro from selected elements into caret area*) 21 | VAR newMac: BOOLEAN; 22 | machead: Graphics.MacHead; 23 | F: GraphicFrames.Frame; 24 | L: Graphics.Library; 25 | S: Texts.Scanner; 26 | Lname, Mname: ARRAY 32 OF CHAR; 27 | BEGIN Texts.OpenScanner(S, Oberon.Par.text, Oberon.Par.pos); Texts.Scan(S); 28 | IF S.class = Texts.Name THEN 29 | Lname := S.s; Texts.Scan(S); 30 | IF (S.class = Texts.Name) OR (S.class = Texts.String) & (S.len <= 8) THEN 31 | F := GraphicFrames.Focus(); Mname := S.s; 32 | IF (F # NIL) & (F.graph.sel # NIL) THEN 33 | Graphics.GetLib(Lname, FALSE, L); 34 | IF L = NIL THEN 35 | Texts.WriteString(W, "new library "); Texts.WriteString(W, Lname); Texts.WriteLn(W); 36 | L := Graphics.NewLib(Lname) 37 | END ; 38 | Graphics.MakeMac(F.graph, machead); 39 | IF machead # NIL THEN 40 | machead.name := Mname; Graphics.InsertMac(machead, L, newMac); Texts.WriteString(W, Mname); 41 | IF newMac THEN Texts.WriteString(W, " inserted in ") ELSE Texts.WriteString(W, " replaced in ") END ; 42 | Texts.WriteString(W, Lname) 43 | ELSE Texts.WriteString(W, " empty macro") 44 | END ; 45 | Texts.WriteLn(W); Texts.Append(Oberon.Log, W.buf) 46 | END 47 | END 48 | END 49 | END MakeMacro; 50 | 51 | PROCEDURE LoadLibrary*; (*lib file name*) 52 | VAR S: Texts.Scanner; L: Graphics.Library; 53 | BEGIN Texts.OpenScanner(S, Oberon.Par.text, Oberon.Par.pos); Texts.Scan(S); 54 | IF S.class = Texts.Name THEN 55 | Texts.WriteString(W, S.s); Graphics.GetLib(S.s, FALSE, L); 56 | IF L # NIL THEN Texts.WriteString(W, " loaded") ELSE Texts.WriteString(W, " not found") END ; 57 | Texts.WriteLn(W); Texts.Append(Oberon.Log, W.buf) 58 | END 59 | END LoadLibrary; 60 | 61 | PROCEDURE StoreLibrary*; (*lib file name*) 62 | VAR i: INTEGER; S: Texts.Scanner; L: Graphics.Library; 63 | BEGIN Texts.OpenScanner(S, Oberon.Par.text, Oberon.Par.pos); Texts.Scan(S); 64 | IF S.class = Texts.Name THEN 65 | Graphics.StoreLib(L, S.s); Texts.WriteString(W, S.s); 66 | IF L # NIL THEN Texts.WriteString(W, " stored") ELSE Texts.WriteString(W, " not found") END ; 67 | Texts.WriteLn(W); Texts.Append(Oberon.Log, W.buf) 68 | END 69 | END StoreLibrary; 70 | 71 | BEGIN Texts.OpenWriter(W); Texts.WriteString(W, "MacroTool - NW 6.8.2013"); 72 | Texts.WriteLn(W); Texts.Append(Oberon.Log, W.buf) 73 | END MacroTool. 74 | -------------------------------------------------------------------------------- /people.inf.ethz.ch/wirth/ProjectOberon/Sources/Math.Mod.txt: -------------------------------------------------------------------------------- 1 | MODULE Math; (*Standard functions; NW 12.10.2013*) 2 | 3 | PROCEDURE sqrt*(x: REAL): REAL; 4 | CONST c1 = 0.70710680; (* 1/sqrt(2) *) 5 | c2 = 0.590162067; 6 | c3 = 1.4142135; (*sqrt(2)*) 7 | VAR s: REAL; e: INTEGER; 8 | BEGIN ASSERT(x >= 0.0); 9 | IF x > 0.0 THEN 10 | UNPK(x, e); 11 | s := c2*(x+c1); 12 | s := s + (x/s); 13 | s := 0.25*s + x/s; 14 | s := 0.5 * (s + x/s); 15 | IF ODD(e) THEN s := c3*s END ; 16 | PACK(s, e DIV 2) 17 | ELSE s := 0.0 18 | END ; 19 | RETURN s 20 | END sqrt; 21 | 22 | PROCEDURE exp*(x: REAL): REAL; 23 | CONST 24 | c1 = 1.4426951; (*1/ln(2) *) 25 | p0 = 1.513864173E3; 26 | p1= 2.020170000E1; 27 | p2 = 2.309432127E-2; 28 | q0 = 4.368088670E3; 29 | q1 = 2.331782320E2; 30 | VAR n: INTEGER; p, y, yy: REAL; 31 | BEGIN y := c1*x; 32 | n := FLOOR(y + 0.5); y := y - FLT(n); 33 | yy := y*y; 34 | p := ((p2*yy + p1)*yy + p0)*y; 35 | p := p/((yy + q1)*yy + q0 - p) + 0.5; 36 | PACK(p, n+1); RETURN p 37 | END exp; 38 | 39 | PROCEDURE ln*(x: REAL): REAL; 40 | CONST c1 = 0.70710680; (* 1/sqrt(2) *) 41 | c2 = 0.69314720; (* ln(2) *) 42 | p0 = -9.01746917E1; 43 | p1 = 9.34639006E1; 44 | p2 = -1.83278704E1; 45 | q0 = -4.50873458E1; 46 | q1 = 6.76106560E1; 47 | q2 = -2.07334879E1; 48 | VAR e: INTEGER; xx, y: REAL; 49 | BEGIN ASSERT(x > 0.0); UNPK(x, e); 50 | IF x < c1 THEN x := x*2.0; e := e-1 END ; 51 | x := (x-1.0)/(x+1.0); 52 | xx := x; 53 | y := c2*FLT(e) + x*((p2*xx + p1)*xx + p0) / (((xx + q2)*xx + q1)*xx + q0); 54 | RETURN y 55 | END ln; 56 | 57 | PROCEDURE sin*(x: REAL): REAL; 58 | CONST 59 | c1 = 6.3661977E-1; (*2/pi*) 60 | p0 = 7.8539816E-1; 61 | p1 = -8.0745512E-2; 62 | p2 = 2.4903946E-3; 63 | p3 = -3.6576204E-5; 64 | p4 = 3.1336162E-7; 65 | p5 = -1.7571493E-9; 66 | p6 = 6.8771004E-12; 67 | q0 = 9.9999999E-1; 68 | q1 = -3.0842514E-1; 69 | q2 = 1.5854344E-2; 70 | q3 = -3.2599189E-4; 71 | q4 = 3.5908591E-6; 72 | q5 = -2.4609457E-8; 73 | q6 = 1.1363813E-10; 74 | VAR n: INTEGER; y, yy, f: REAL; 75 | BEGIN y := c1*x; 76 | IF y >= 0.0 THEN n := FLOOR(y + 0.5) ELSE n := FLOOR(y - 0.5) END ; 77 | y := (y - FLT(n)) * 2.0; yy := y*y; 78 | IF ODD(n) THEN f := (((((q6*yy + q5)*yy + q4)*yy + q3)*yy + q2)*yy + q1)*yy + q0 79 | ELSE f := ((((((p6*yy + p5)*yy + p4)*yy + p3)*yy + p2)*yy + p1)*yy + p0)*y 80 | END ; 81 | IF ODD(n DIV 2) THEN f := -f END ; 82 | RETURN f 83 | END sin; 84 | 85 | PROCEDURE cos*(x: REAL): REAL; 86 | CONST 87 | c1 = 6.3661977E-1; (*2/pi*) 88 | p0 = 7.8539816E-1; 89 | p1 = -8.0745512E-2; 90 | p2 = 2.4903946E-3; 91 | p3 = -3.6576204E-5; 92 | p4 = 3.1336162E-7; 93 | p5 = -1.7571493E-9; 94 | p6 = 6.8771004E-12; 95 | q0 = 9.9999999E-1; 96 | q1 = -3.0842514E-1; 97 | q2 = 1.5854344E-2; 98 | q3 = -3.2599189E-4; 99 | q4 = 3.5908591E-6; 100 | q5 = -2.4609457E-8; 101 | q6 = 1.1363813E-10; 102 | VAR n: INTEGER; y, yy, f: REAL; 103 | BEGIN y := c1*x; 104 | IF y >= 0.0 THEN n := FLOOR(y + 0.5) ELSE n := FLOOR(y - 0.5) END ; 105 | y := (y - FLT(n)) * 2.0; yy := y*y; 106 | IF ~ODD(n) THEN f := (((((q6*yy + q5)*yy + q4)*yy + q3)*yy + q2)*yy + q1)*yy + q0 107 | ELSE f := ((((((p6*yy + p5)*yy + p4)*yy + p3)*yy + p2)*yy + p1)*yy + p0)*y 108 | END ; 109 | IF ODD((n+1) DIV 2) THEN f := -f END ; 110 | RETURN f 111 | END cos; 112 | END Math. 113 | -------------------------------------------------------------------------------- /people.inf.ethz.ch/wirth/ProjectOberon/Sources/OberonSyntax.Text.txt: -------------------------------------------------------------------------------- 1 | digit = "0" | "1" | "2" | "3" | "4" | "5" | "6" | "7" | "8" | "9". 2 | hexDigit = digit | "A" | "B" | "C" | "D" | "E" | "F". 3 | ident = letter {letter | digit}. 4 | qualident = [ident "."] ident. 5 | identdef = ident ["*"]. 6 | integer = digit {digit} | digit {hexDigit} "H". 7 | real = digit {digit} "." {digit} [ScaleFactor]. 8 | ScaleFactor = ("E" |"D") ["+" | "-"] digit {digit}. 9 | number = integer | real. 10 | string = "'" {character} "'" | digit {hexdigit} "X". 11 | ConstDeclaration = identdef "=" ConstExpression. 12 | ConstExpression = expression. 13 | TypeDeclaration = identdef "=" StrucType. 14 | StrucType = ArrayType | RecordType | PointerType | ProcedureType. 15 | type = qualident | StrucType. 16 | ArrayType = "ARRAY" length {"," length} "OF" type. 17 | length = ConstExpression. 18 | RecordType = "RECORD" ["(" BaseType ")"] [FieldListSequence] "END". 19 | BaseType = qualident. 20 | FieldListSequence = FieldList {";" FieldList}. 21 | FieldList = IdentList ":" type. 22 | IdentList = identdef {"," identdef}. 23 | PointerType = "POINTER" "TO" type. 24 | ProcedureType = "PROCEDURE" [FormalParameters]. 25 | VariableDeclaration = IdentList ":" type. 26 | expression = SimpleExpression [relation SimpleExpression]. 27 | relation = "=" | "#" | "<" | "<=" | ">" | ">=" | "IN" | "IS". 28 | SimpleExpression = ["+" | "-"] term {AddOperator term}. 29 | AddOperator = "+" | "-" | "OR". 30 | term = factor {MulOperator factor}. 31 | MulOperator = "*" | "/" | "DIV" | "MOD" | "&". 32 | factor = number | string | "NIL" | "TRUE" | "FALSE" | 33 | set | designator [ActualParameters] | "(" expression ")" | "~" factor. 34 | designator = qualident {selector}. 35 | selector = "." ident | "[" ExpList "]" | "^" | "(" qualident ")". 36 | set = "{" [element {"," element}] "}". 37 | element = expression [".." expression]. 38 | ExpList = expression {"," expression}. 39 | ActualParameters = "(" [ExpList] ")" . 40 | statement = [assignment | ProcedureCall | IfStatement | CaseStatement | 41 | WhileStatement | RepeatStatement | ForStatement]. 42 | assignment = designator ":=" expression. 43 | ProcedureCall = designator [ActualParameters]. 44 | StatementSequence = statement {";" statement}. 45 | IfStatement = "IF" expression "THEN" StatementSequence 46 | {"ELSIF" expression "THEN" StatementSequence} 47 | ["ELSE" StatementSequence] "END". 48 | CaseStatement = "CASE" expression "OF" case {"|" case} "END". 49 | Case = CaseLabelList ":" StatementSequence. 50 | CaseLabelList = LabelRange {"," LabelRange}. 51 | LabelRange = label [".." label]. 52 | label = integer | string | ident. 53 | WhileStatement = "WHILE" expression "DO" StatementSequence 54 | {"ELSIF" expression "DO" StatementSequence} "END". 55 | RepeatStatement = "REPEAT" StatementSequence "UNTIL" expression. 56 | ForStatement = "FOR" ident ":=" expression "TO" expression ["BY" ConstExpression] 57 | "DO" StatementSequence "END". 58 | ProcedureDeclaration = ProcedureHeading ";" ProcedureBody ident. 59 | ProcedureHeading = "PROCEDURE" identdef [FormalParameters]. 60 | ProcedureBody = DeclarationSequence ["BEGIN" StatementSequence] 61 | ["RETURN" expression] "END". 62 | DeclarationSequence = ["CONST" {ConstDeclaration ";"}] 63 | ["TYPE" {TypeDeclaration ";"}] 64 | ["VAR" {VariableDeclaration ";"}] 65 | {ProcedureDeclaration ";"}. 66 | FormalParameters = "(" [FPSection {";" FPSection}] ")" [":" qualident]. 67 | FPSection = ["CONST" | "VAR"] ident {"," ident} ":" FormalType. 68 | FormalType = ["ARRAY" "OF"] qualident. 69 | module = "MODULE" ident ";" [ImportList] DeclarationSequence 70 | ["BEGIN" StatementSequence] "END" ident "." . 71 | ImportList = "IMPORT" import {"," import} ";". 72 | import = ident [":=" ident]. 73 | -------------------------------------------------------------------------------- /people.inf.ethz.ch/wirth/ProjectOberon/Sources/PCLink1.Mod.txt: -------------------------------------------------------------------------------- 1 | MODULE PCLink1; (*NW 25.7.2013 for Oberon on RISC*) 2 | IMPORT SYSTEM, Files, Texts, Oberon; 3 | 4 | CONST data = -56; stat = -52; 5 | BlkLen = 255; 6 | REQ = 20H; REC = 21H; SND = 22H; ACK = 10H; NAK = 11H; 7 | 8 | VAR T: Oberon.Task; 9 | W: Texts.Writer; 10 | 11 | PROCEDURE Rec(VAR x: BYTE); 12 | BEGIN 13 | REPEAT UNTIL SYSTEM.BIT(stat, 0); 14 | SYSTEM.GET(data, x) 15 | END Rec; 16 | 17 | PROCEDURE RecName(VAR s: ARRAY OF CHAR); 18 | VAR i: INTEGER; x: BYTE; 19 | BEGIN i := 0; Rec(x); 20 | WHILE x > 0 DO s[i] := CHR(x); INC(i); Rec(x) END ; 21 | s[i] := 0X 22 | END RecName; 23 | 24 | PROCEDURE Send(x: BYTE); 25 | BEGIN 26 | REPEAT UNTIL SYSTEM.BIT(stat, 1); 27 | SYSTEM.PUT(data, x) 28 | END Send; 29 | 30 | PROCEDURE Task; 31 | VAR len, n, i: INTEGER; 32 | x, ack, len1, code: BYTE; 33 | name: ARRAY 32 OF CHAR; 34 | F: Files.File; R: Files.Rider; 35 | buf: ARRAY 256 OF BYTE; 36 | BEGIN 37 | IF SYSTEM.BIT(stat, 0) THEN (*byte available*) 38 | Rec(code); 39 | IF code = SND THEN (*send file*) 40 | LED(20H); RecName(name); F := Files.Old(name); 41 | IF F # NIL THEN 42 | Texts.WriteString(W, "sending "); Texts.WriteString(W, name); 43 | Texts.Append(Oberon.Log, W.buf); 44 | Send(ACK); len := Files.Length(F); Files.Set(R, F, 0); 45 | REPEAT 46 | IF len >= BlkLen THEN len1 := BlkLen ELSE len1 := len END ; 47 | Send(len1); n := len1; len := len - len1; 48 | WHILE n > 0 DO Files.ReadByte(R, x); Send(x); DEC(n) END ; 49 | Rec(ack); 50 | IF ack # ACK THEN len1 := 0 END 51 | UNTIL len1 < BlkLen; 52 | Texts.WriteString(W, " done"); Texts.WriteLn(W); Texts.Append(Oberon.Log, W.buf) 53 | ELSE Send(11H) 54 | END 55 | ELSIF code = REC THEN (*receive file*) 56 | LED(30H); RecName(name); F := Files.New(name); 57 | IF F # NIL THEN 58 | Texts.WriteString(W, "receiving "); Texts.WriteString(W, name); 59 | Texts.Append(Oberon.Log, W.buf); 60 | Files.Set(R, F, 0); Send(ACK); 61 | REPEAT Rec(x); len := x; i := 0; 62 | WHILE i < len DO Rec(x); buf[i] := x; INC(i) END ; 63 | i := 0; 64 | WHILE i < len DO Files.WriteByte(R, buf[i]); INC(i) END ; 65 | Send(ACK) 66 | UNTIL len < 255; 67 | Files.Register(F); Send(ACK); 68 | Texts.WriteString(W, " done"); Texts.WriteLn(W); Texts.Append(Oberon.Log, W.buf) 69 | ELSE Send(NAK) 70 | END 71 | ELSIF code = REQ THEN Send(ACK) 72 | END ; 73 | LED(0) 74 | END 75 | END Task; 76 | 77 | PROCEDURE Run*; 78 | BEGIN Oberon.Install(T); Texts.WriteString(W, "PCLink started"); 79 | Texts.WriteLn(W); Texts.Append(Oberon.Log, W.buf) 80 | END Run; 81 | 82 | PROCEDURE Stop*; 83 | BEGIN Oberon.Remove(T); Texts.WriteString(W, "PCLink stopped"); 84 | Texts.WriteLn(W); Texts.Append(Oberon.Log, W.buf) 85 | END Stop; 86 | 87 | BEGIN Texts.OpenWriter(W); T := Oberon.NewTask(Task, 0) 88 | END PCLink1. 89 | -------------------------------------------------------------------------------- /people.inf.ethz.ch/wirth/ProjectOberon/Sources/PIO.Mod.txt: -------------------------------------------------------------------------------- 1 | MODULE PIO; (*NW 16.10.2014 PIC Input/Output for RISC*) 2 | IMPORT SYSTEM; 3 | 4 | (* PIC interface, output: 5 | D0 = PIC B7 data out 6 | D1 = PIC B6 clk out 7 | D2 = PIC A4 data in *) 8 | 9 | CONST gpio = -32; gpoc = -28; (*I/O addresses*) 10 | 11 | PROCEDURE del(i: INTEGER); 12 | BEGIN 13 | REPEAT DEC(i) UNTIL i = 0 14 | END del; 15 | 16 | PROCEDURE Send*(x: LONGINT); 17 | VAR i: INTEGER; 18 | BEGIN (*send byte*) 19 | FOR i := 0 TO 7 DO 20 | SYSTEM.PUT(gpio, x MOD 2 + 2); del(60); SYSTEM.PUT(gpio, x MOD 2); del(25); x := x DIV 2 21 | END ; 22 | SYSTEM.PUT(gpio, 0); del(100) 23 | END Send; 24 | 25 | PROCEDURE Receive*(VAR x: LONGINT); 26 | VAR i, x0: INTEGER; 27 | BEGIN (*receive byte*) x0 := 0; 28 | REPEAT UNTIL ~SYSTEM.BIT(gpio, 2); 29 | FOR i := 0 TO 7 DO 30 | SYSTEM.PUT(gpio, 2); del(60); 31 | IF SYSTEM.BIT(gpio, 2) THEN x0 := x0 + 100H END ; 32 | SYSTEM.PUT(gpio, 0); del(25); x0 := ROR(x0, 1) 33 | END ; 34 | x := x0 35 | END Receive; 36 | 37 | PROCEDURE Reset*; 38 | BEGIN SYSTEM.PUT(gpio, 0); SYSTEM.PUT(gpoc, 3) (*set bit 0, 1 to output*) 39 | END Reset; 40 | 41 | BEGIN Reset 42 | END PIO. 43 | -------------------------------------------------------------------------------- /people.inf.ethz.ch/wirth/ProjectOberon/Sources/RISC.Mod.txt: -------------------------------------------------------------------------------- 1 | MODULE RISC; (*NW 22.9.07 / 1.11.2013*) 2 | IMPORT SYSTEM, Texts, Oberon; 3 | CONST 4 | MOV = 0; LSL = 1; ASR = 2; ROR = 3; AND = 4; ANN = 5; IOR = 6; XOR = 7; 5 | ADD = 8; SUB = 9; MUL = 10; Div = 11; 6 | 7 | VAR IR: LONGINT; (*instruction register*) 8 | PC: LONGINT; (*program counter*) 9 | N, Z: BOOLEAN; (*condition flags*) 10 | R: ARRAY 16 OF LONGINT; 11 | H: LONGINT; (*aux register for division*) 12 | 13 | PROCEDURE Execute*(VAR M: ARRAY OF LONGINT; pc: LONGINT; 14 | VAR S: Texts.Scanner; VAR W: Texts.Writer); 15 | VAR a, b, op, im: LONGINT; (*instruction fields*) 16 | adr, A, B, C, n: LONGINT; 17 | MemSize: LONGINT; 18 | BEGIN PC := 0; R[13] := pc * 4; R[14] := LEN(M)*4; n := 0; 19 | REPEAT (*interpretation cycle*) 20 | IR := M[PC]; INC(PC); INC(n); 21 | a := IR DIV 1000000H MOD 10H; 22 | b := IR DIV 100000H MOD 10H; 23 | op := IR DIV 10000H MOD 10H; 24 | im := IR MOD 10000H; 25 | IF ~ODD(IR DIV 80000000H) THEN (*~p: register instruction*) 26 | B := R[b]; 27 | IF ~ODD(IR DIV 40000000H) THEN (*~q*) C := R[IR MOD 10H] 28 | ELSIF ~ODD(IR DIV 10000000H) THEN (*q&~v*) C := im 29 | ELSE (*q&v*) C := im + 0FFFF0000H 30 | END ; 31 | CASE op OF 32 | MOV: IF ~ODD(IR DIV 20000000H) THEN A := C ELSE A := H END | 33 | LSL: A := SYSTEM.LSH(B, C) | 34 | ASR: A := ASH(B, -C) | 35 | ROR: A := SYSTEM.ROT(B, -C) | 36 | AND: A := SYSTEM.VAL(LONGINT, SYSTEM.VAL(SET, B) * SYSTEM.VAL(SET, C)) | 37 | ANN: A := SYSTEM.VAL(LONGINT, SYSTEM.VAL(SET, B) - SYSTEM.VAL(SET, C)) | 38 | IOR: A := SYSTEM.VAL(LONGINT, SYSTEM.VAL(SET, B) + SYSTEM.VAL(SET, C)) | 39 | XOR: A := SYSTEM.VAL(LONGINT, SYSTEM.VAL(SET, B) / SYSTEM.VAL(SET, C)) | 40 | ADD: A := B + C | 41 | SUB: A := B - C | 42 | MUL: A := B * C | 43 | Div: A := B DIV C; H := B MOD C 44 | END ; 45 | R[a] := A; N := A < 0; Z := A = 0 46 | ELSIF ~ODD(IR DIV 40000000H) THEN (*p & ~q: memory instruction*) 47 | adr := (R[b] + IR MOD 100000H) DIV 4; 48 | IF ~ODD(IR DIV 20000000H) THEN 49 | IF adr >= 0 THEN (*load*) R[a] := M[adr]; N := A < 0; Z := A = 0 50 | ELSE (*input*) 51 | IF adr = -1 THEN (*ReadInt*) Texts.Scan(S); R[a] := S.i; 52 | ELSIF adr = -2 THEN (*eot*) Z := S.class # Texts.Int 53 | END 54 | END 55 | ELSE 56 | IF adr >= 0 THEN (*store*) M[adr] := R[a]; 57 | ELSE (*output*) 58 | IF adr = -1 THEN Texts.WriteInt(W, R[a], 4) 59 | ELSIF adr = -2 THEN Texts.Write(W, CHR(R[a] MOD 80H)) 60 | ELSIF adr = -3 THEN Texts.WriteLn(W); Texts.Append(Oberon.Log, W.buf) 61 | END 62 | END 63 | END 64 | ELSE (* p & q: branch instruction*) 65 | IF (a = 0) & N OR (a = 1) & Z OR (a = 5) & N OR (a = 6) & (N OR Z) OR (a = 7) OR 66 | (a = 8) & ~N OR (a = 9) & ~Z OR (a = 13) & ~N OR (a = 14) & ~(N OR Z) THEN 67 | IF ODD(IR DIV 10000000H) THEN R[15] := PC * 4 END ; 68 | IF ODD(IR DIV 20000000H) THEN PC := (PC + (IR MOD 1000000H)) MOD 40000H 69 | ELSE PC := R[IR MOD 10H] DIV 4 70 | END 71 | END 72 | END 73 | UNTIL (PC = 0) OR (n = 100000); 74 | Texts.WriteInt(W, n, 8); 75 | IF n = 100000 THEN Texts.WriteString(W, " aborted") END ; 76 | Texts.WriteLn(W); Texts.Append(Oberon.Log, W.buf) 77 | END Execute; 78 | END RISC. 79 | 80 | 81 | -------------------------------------------------------------------------------- /people.inf.ethz.ch/wirth/ProjectOberon/Sources/RS232.Mod.txt: -------------------------------------------------------------------------------- 1 | MODULE RS232; (*NW 3.1.2012*) 2 | IMPORT SYSTEM; 3 | CONST data = -56; stat = -52; 4 | 5 | PROCEDURE Send*(x: INTEGER); 6 | BEGIN 7 | REPEAT UNTIL SYSTEM.BIT(stat, 1); 8 | SYSTEM.PUT(data, x) 9 | END Send; 10 | 11 | PROCEDURE Rec*(VAR x: INTEGER); 12 | BEGIN 13 | REPEAT UNTIL SYSTEM.BIT(stat, 0); 14 | SYSTEM.GET(data, x) 15 | END Rec; 16 | 17 | PROCEDURE SendInt*(x: INTEGER); 18 | VAR i: INTEGER; 19 | BEGIN Send(1); i := 4; 20 | REPEAT i := i-1; Send(x); x := ROR(x, 8) UNTIL i = 0 21 | END SendInt; 22 | 23 | PROCEDURE SendHex*(x: INTEGER); 24 | VAR i: INTEGER; 25 | BEGIN Send(2); i := 4; 26 | REPEAT i := i-1; Send(x); x := ROR(x, 8) UNTIL i = 0 27 | END SendHex; 28 | 29 | PROCEDURE SendReal*(x: REAL); 30 | VAR i, u: INTEGER; 31 | BEGIN Send(3); u := ORD(x); i := 4; 32 | REPEAT i := i-1; Send(u); u := ROR(u, 8) UNTIL i = 0 33 | END SendReal; 34 | 35 | PROCEDURE SendStr*(x: ARRAY OF CHAR); 36 | VAR i, k: INTEGER; 37 | BEGIN Send(4); i := 0; 38 | REPEAT k := ORD(x[i]); Send(k); INC(i) UNTIL k = 0 39 | END SendStr; 40 | 41 | PROCEDURE RecInt*(VAR x: INTEGER); 42 | VAR i, x0, y: INTEGER; 43 | BEGIN i := 4; x0 := 0; 44 | REPEAT i := i-1; Rec(y); x0 := ROR(x0+y, 8) UNTIL i = 0; 45 | x := x0 46 | END RecInt; 47 | 48 | PROCEDURE RecReal*(VAR x: REAL); 49 | VAR i, x0, y: INTEGER; 50 | BEGIN i := 4; x0 := 0; 51 | REPEAT i := i-1; Rec(y); x0 := ROR(x0+y, 8) UNTIL i = 0; 52 | x := SYSTEM.VAL(REAL, x0) 53 | END RecReal; 54 | 55 | PROCEDURE RecStr*(VAR x: ARRAY OF CHAR); 56 | VAR i, k: INTEGER; 57 | BEGIN i := 0; 58 | REPEAT Rec(k); x[i] := CHR(k); INC(i) UNTIL k = 0 59 | END RecStr; 60 | 61 | PROCEDURE Line*; 62 | BEGIN Send(6) 63 | END Line; 64 | 65 | PROCEDURE End*; 66 | BEGIN Send(7) 67 | END End; 68 | 69 | BEGIN END RS232. 70 | -------------------------------------------------------------------------------- /people.inf.ethz.ch/wirth/ProjectOberon/Sources/Rectangles.Mod.txt: -------------------------------------------------------------------------------- 1 | MODULE Rectangles; (*NW 25.2.90 / 18.4.2013*) 2 | IMPORT SYSTEM, Display, Files, Input, Texts, Oberon, Graphics, GraphicFrames; 3 | 4 | TYPE 5 | Rectangle* = POINTER TO RectDesc; 6 | RectDesc* = RECORD (Graphics.ObjectDesc) 7 | lw*, vers*: INTEGER 8 | END ; 9 | 10 | VAR method*: Graphics.Method; 11 | tack*, grey*: INTEGER; 12 | 13 | PROCEDURE New*; 14 | VAR r: Rectangle; 15 | BEGIN NEW(r); r.do := method; Graphics.New(r) 16 | END New; 17 | 18 | PROCEDURE Copy(src, dst: Graphics.Object); 19 | BEGIN dst.x := src.x; dst.y := src.y; dst.w := src.w; dst.h := src.h; dst.col := src.col; 20 | dst(Rectangle).lw := src(Rectangle).lw; dst(Rectangle).vers := src(Rectangle).vers 21 | END Copy; 22 | 23 | PROCEDURE mark(f: GraphicFrames.Frame; col, x, y: INTEGER); 24 | BEGIN GraphicFrames.ReplConst(f, col, x+1, y+1, 4, 4, 0) 25 | END mark; 26 | 27 | PROCEDURE Draw(obj: Graphics.Object; VAR M: Graphics.Msg); 28 | VAR x, y, w, h, lw, col: INTEGER; f: GraphicFrames.Frame; 29 | 30 | PROCEDURE draw(f: GraphicFrames.Frame; col, x, y, w, h, lw: INTEGER); 31 | BEGIN 32 | GraphicFrames.ReplConst(f, col, x, y, w, lw, Display.replace); 33 | GraphicFrames.ReplConst(f, col, x+w-lw, y, lw, h, Display.replace); 34 | GraphicFrames.ReplConst(f, col, x, y+h-lw, w, lw, Display.replace); 35 | GraphicFrames.ReplConst(f, col, x, y, lw, h, Display.replace) 36 | END draw; 37 | 38 | BEGIN 39 | CASE M OF GraphicFrames.DrawMsg: 40 | x := obj.x + M.x; y := obj.y + M.y; w := obj.w; h := obj.h; f := M.f; 41 | lw := obj(Rectangle).lw; 42 | IF (x < f.X1) & (x+w > f.X) & (y < f.Y1) & (y+h > f.Y) THEN 43 | IF M.col = Display.black THEN col := obj.col ELSE col := M.col END ; 44 | IF M.mode = 0 THEN 45 | draw(f, col, x, y, w, h, lw); 46 | IF obj.selected THEN mark(f, Display.white, x, y) END 47 | ELSIF M.mode = 1 THEN mark(f, Display.white, x, y) (*normal -> selected*) 48 | ELSIF M.mode = 2 THEN mark(f, Display.black, x, y) (*selected -> normal*) 49 | ELSIF M.mode = 3 THEN draw(f, Display.black, x, y, w, h, lw); mark(f, Display.black, x, y) (*erase*) 50 | END 51 | END 52 | END 53 | END Draw; 54 | 55 | PROCEDURE Selectable(obj: Graphics.Object; x, y: INTEGER): BOOLEAN; 56 | BEGIN 57 | RETURN (obj.x <= x) & (x <= obj.x + 4) & (obj.y <= y) & (y <= obj.y + 4) 58 | END Selectable; 59 | 60 | PROCEDURE Change(obj: Graphics.Object; VAR M: Graphics.Msg); 61 | VAR x0, y0, x1, y1, dx, dy: INTEGER; k: SET; 62 | BEGIN 63 | CASE M OF 64 | Graphics.WidMsg: obj(Rectangle).lw := M.w | 65 | Graphics.ColorMsg: obj.col := M.col 66 | END 67 | END Change; 68 | 69 | PROCEDURE Read(obj: Graphics.Object; VAR R: Files.Rider; VAR C: Graphics.Context); 70 | VAR b: BYTE; len: INTEGER; 71 | BEGIN Files.ReadByte(R, b); (*len*); 72 | Files.ReadByte(R, b); obj(Rectangle).lw := b; 73 | Files.ReadByte(R, b); obj(Rectangle).vers := b; 74 | END Read; 75 | 76 | PROCEDURE Write(obj: Graphics.Object; cno: INTEGER; VAR W: Files.Rider; VAR C: Graphics.Context); 77 | BEGIN Graphics.WriteObj(W, cno, obj); Files.WriteByte(W, 2); 78 | Files.WriteByte(W, obj(Rectangle).lw); Files.WriteByte(W, obj(Rectangle).vers) 79 | END Write; 80 | 81 | (* PROCEDURE Print(obj: Graphics.Object; x, y: INTEGER); 82 | VAR w, h, lw, s: INTEGER; 83 | BEGIN INC(x, obj.x * 4); INC(y, obj.y * 4); w := obj.w * 4; h := obj.h * 4; 84 | lw := obj(Rectangle).lw * 2; s := obj(Rectangle).vers; 85 | Printer.ReplConst(x, y, w, lw); 86 | Printer.ReplConst(x+w-lw, y, lw, h); 87 | Printer.ReplConst(x, y+h-lw, w, lw); 88 | Printer.ReplConst(x, y, lw, h); 89 | IF s > 0 THEN Printer.ReplPattern(x, y, w, h, s) END 90 | END Print; *) 91 | 92 | PROCEDURE Make*; (*command*) 93 | VAR x0, x1, y0, y1: INTEGER; 94 | R: Rectangle; 95 | G: GraphicFrames.Frame; 96 | BEGIN G := GraphicFrames.Focus(); 97 | IF (G # NIL) & (G.mark.next # NIL) THEN 98 | GraphicFrames.Deselect(G); 99 | x0 := G.mark.x; y0 := G.mark.y; x1 := G.mark.next.x; y1 := G.mark.next.y; 100 | NEW(R); R.col := Oberon.CurCol; 101 | R.w := ABS(x1-x0); R.h := ABS(y1-y0); 102 | IF x1 < x0 THEN x0 := x1 END ; 103 | IF y1 < y0 THEN y0 := y1 END ; 104 | R.x := x0 - G.x; R.y := y0 - G.y; 105 | R.lw := Graphics.width; R.vers := 0; R.do := method; 106 | Graphics.Add(G.graph, R); 107 | GraphicFrames.Defocus(G); GraphicFrames.DrawObj(G, R) 108 | END 109 | END Make; 110 | 111 | BEGIN NEW(method); 112 | method.module := "Rectangles"; method.allocator := "New"; 113 | method.new := New; method.copy := Copy; method.draw := Draw; 114 | method.selectable := Selectable; method.change := Change; 115 | method.read := Read; method.write := Write; (*method.print := Print*) 116 | tack := SYSTEM.ADR($0707 4122 1408 1422 4100$); 117 | grey := SYSTEM.ADR($2004 0000 1111 1111 0000 0000 4444 4444 0000 0000$) 118 | END Rectangles. 119 | -------------------------------------------------------------------------------- /people.inf.ethz.ch/wirth/ProjectOberon/Sources/Sierpinski.Mod.txt: -------------------------------------------------------------------------------- 1 | MODULE Sierpinski; (*NW 15.1.2013*) 2 | IMPORT Display, Viewers, Oberon, MenuViewers, TextFrames; 3 | 4 | CONST Menu = "System.Close System.Copy System.Grow"; 5 | 6 | VAR x, y, d: INTEGER; 7 | A, B, C, D: PROCEDURE (i: INTEGER); 8 | 9 | PROCEDURE E; 10 | BEGIN Display.ReplConst(Display.white, x, y, d, 1, Display.paint); INC(x, d) 11 | END E; 12 | 13 | PROCEDURE N; 14 | BEGIN Display.ReplConst(Display.white, x, y, 1, d, Display.paint); INC(y, d) 15 | END N; 16 | 17 | PROCEDURE W; 18 | BEGIN DEC(x, d); Display.ReplConst(Display.white, x, y, d, 1, Display.paint) 19 | END W; 20 | 21 | PROCEDURE S; 22 | BEGIN DEC(y, d); Display.ReplConst(Display.white, x, y, 1, d, Display.paint) 23 | END S; 24 | 25 | PROCEDURE NE; 26 | VAR i: INTEGER; 27 | BEGIN i := d; 28 | REPEAT Display.Dot(Display.white, x, y, Display.paint); INC(x); INC(y); DEC(i) UNTIL i = 0 29 | END NE; 30 | 31 | PROCEDURE NW; 32 | VAR i: INTEGER; 33 | BEGIN i := d; 34 | REPEAT Display.Dot(Display.white, x, y, Display.paint); DEC(x); INC(y); DEC(i) UNTIL i = 0 35 | END NW; 36 | 37 | PROCEDURE SW; 38 | VAR i: INTEGER; 39 | BEGIN i := d; 40 | REPEAT Display.Dot(Display.white, x, y, Display.paint); DEC(x); DEC(y); DEC(i) UNTIL i = 0 41 | END SW; 42 | 43 | PROCEDURE SE; 44 | VAR i: INTEGER; 45 | BEGIN i := d; 46 | REPEAT Display.Dot(Display.white, x, y, Display.paint); INC(x); DEC(y); DEC(i) UNTIL i = 0 47 | END SE; 48 | 49 | PROCEDURE SA(i: INTEGER); 50 | BEGIN 51 | IF i > 0 THEN A(i-1); SE; B(i-1); E; E; D(i-1); NE; A(i-1) END 52 | END SA; 53 | 54 | PROCEDURE SB(i: INTEGER); 55 | BEGIN 56 | IF i > 0 THEN B(i-1); SW; C(i-1); S; S; A(i-1); SE; B(i-1) END 57 | END SB; 58 | 59 | PROCEDURE SC(i: INTEGER); 60 | BEGIN 61 | IF i > 0 THEN C(i-1); NW; D(i-1); W; W; B(i-1); SW; C(i-1) END 62 | END SC; 63 | 64 | PROCEDURE SD(i: INTEGER); 65 | BEGIN 66 | IF i > 0 THEN D(i-1); NE; A(i-1); N; N; C(i-1); NW; D(i-1) END 67 | END SD; 68 | 69 | PROCEDURE DrawSierpinski(F: Display.Frame); 70 | VAR k, n, w, x0, y0: INTEGER; 71 | BEGIN; k := 0; d := 4; 72 | IF F.W < F.H THEN w := F.W ELSE w := F.H END ; 73 | WHILE d*8 < w DO d := d*2; INC(k) END ; 74 | Display.ReplConst(Display.black, F.X, F.Y, F.W, F.H, Display.replace); 75 | x0 := F.W DIV 2; y0 := F.H DIV 2 + d; n := 0; 76 | WHILE n < k DO 77 | INC(n); DEC(x0, d); d := d DIV 2; INC(y0, d); 78 | x := F.X + x0; y := F.Y + y0; 79 | SA(n); SE; SB(n); SW; SC(n); NW; SD(n); NE 80 | END 81 | END DrawSierpinski; 82 | 83 | PROCEDURE Handler(F: Display.Frame; VAR M: Display.FrameMsg); 84 | VAR F1: Display.Frame; 85 | BEGIN 86 | IF M IS Oberon.InputMsg THEN 87 | IF M(Oberon.InputMsg).id = Oberon.track THEN 88 | Oberon.DrawMouseArrow(M(Oberon.InputMsg).X, M(Oberon.InputMsg).Y) 89 | END 90 | ELSIF M IS MenuViewers.ModifyMsg THEN 91 | F.Y := M(MenuViewers.ModifyMsg).Y; F.H := M(MenuViewers.ModifyMsg).H; DrawSierpinski(F) 92 | ELSIF M IS Oberon.ControlMsg THEN 93 | IF M(Oberon.ControlMsg).id = Oberon.neutralize THEN Oberon.RemoveMarks(F.X, F.Y, F.W, F.H) END 94 | ELSIF M IS Oberon.CopyMsg THEN 95 | NEW(F1); F1^ := F^; M(Oberon.CopyMsg).F := F1 96 | END 97 | END Handler; 98 | 99 | PROCEDURE New(): Display.Frame; 100 | VAR F: Display.Frame; 101 | BEGIN NEW(F); F.handle := Handler; RETURN F 102 | END New; 103 | 104 | PROCEDURE Draw*; 105 | VAR V: Viewers.Viewer; X, Y: INTEGER; 106 | BEGIN Oberon.AllocateUserViewer(Oberon.Par.vwr.X, X, Y); 107 | V := MenuViewers.New(TextFrames.NewMenu("Sierpinski", Menu), New(), TextFrames.menuH, X, Y) 108 | END Draw; 109 | 110 | BEGIN A := SA; B := SB; C := SC; D := SD 111 | END Sierpinski. 112 | -------------------------------------------------------------------------------- /people.inf.ethz.ch/wirth/ProjectOberon/Sources/Stars.Mod.txt: -------------------------------------------------------------------------------- 1 | MODULE Stars; (*NW 15.1.2013, 15.11.2013*) 2 | IMPORT SYSTEM, Display, Viewers, Texts, Oberon, MenuViewers, TextFrames; 3 | 4 | CONST N = 6; (*nof stars*) 5 | w = 16; (*width of star*) 6 | interval = 200; (*millisec*) 7 | 8 | TYPE Frame = POINTER TO FrameDesc; 9 | Pos = RECORD x, y, dx, dy: INTEGER END ; 10 | FrameDesc = RECORD (Display.FrameDesc) s: ARRAY N OF Pos END ; 11 | RestoreMsg = RECORD (Display.FrameMsg) END ; 12 | StepMsg = RECORD (Display.FrameMsg) END ; 13 | 14 | VAR T: Oberon.Task; 15 | W: Texts.Writer; 16 | 17 | PROCEDURE Draw(x, y: INTEGER); 18 | BEGIN Display.CopyPattern(Display.white, Display.star, x, y, Display.invert) 19 | END Draw; 20 | 21 | PROCEDURE Restore(F: Frame); 22 | VAR x0, y0: INTEGER; 23 | BEGIN Oberon.RemoveMarks(F.X, F.Y, F.W, F.H); 24 | Display.ReplConst(0, F.X+1, F.Y, F.W-1, F.H, 0); 25 | x0 := F.W DIV 2 + F.X; y0 := F.H DIV 2 + F.Y; 26 | F.s[0].x := x0; F.s[0].y := y0; F.s[0].dx := 2; F.s[0].dy := 4; Draw(F.s[0].x, F.s[0].y); 27 | F.s[1].x := x0; F.s[1].y := y0; F.s[1].dx := 3; F.s[1].dy := 9; Draw(F.s[1].x, F.s[1].y); 28 | F.s[2].x := x0; F.s[2].y := y0; F.s[2].dx := -5; F.s[2].dy := -2; Draw(F.s[2].x, F.s[2].y); 29 | F.s[3].x := x0; F.s[3].y := y0; F.s[3].dx := -10; F.s[3].dy := 8; Draw(F.s[3].x, F.s[3].y); 30 | F.s[4].x := x0; F.s[4].y := y0; F.s[4].dx := -7; F.s[4].dy := -4; Draw(F.s[4].x, F.s[4].y); 31 | F.s[5].x := x0; F.s[5].y := y0; F.s[5].dx := 8; F.s[5].dy := -10; Draw(F.s[5].x, F.s[5].y) 32 | END Restore; 33 | 34 | PROCEDURE Move(F: Frame; VAR p: Pos); 35 | VAR X1, Y1: INTEGER; 36 | BEGIN X1 := F.X + F.W - w; Y1 := F.Y + F.H - w; 37 | Draw(p.x, p.y); INC(p.x, p.dx); INC(p.y, p.dy); 38 | IF p.x < F.X THEN p.x := 2*F.X - p.x; p.dx := -p.dx ELSIF p.x >= X1 THEN p.x := 2*X1 - p.x; p.dx := -p.dx END ; 39 | IF p.y < F.Y THEN p.y := 2*F.Y - p.y; p.dy := -p.dy ELSIF p.y >= Y1 THEN p.y := 2*Y1 - p.y; p.dy := -p.dy END ; 40 | Draw(p.x, p.y) 41 | END Move; 42 | 43 | PROCEDURE Steps(F: Frame); 44 | VAR i: INTEGER; 45 | BEGIN i := 0; 46 | WHILE i < N DO Move(F, F.s[i]); INC(i) END 47 | END Steps; 48 | 49 | PROCEDURE Handle(F: Display.Frame; VAR M: Display.FrameMsg); 50 | VAR F1: Frame; 51 | BEGIN 52 | CASE F OF Frame: 53 | CASE M OF 54 | Oberon.InputMsg: 55 | IF M(Oberon.InputMsg).id = Oberon.track THEN 56 | Oberon.DrawMouseArrow(M(Oberon.InputMsg).X, M(Oberon.InputMsg).Y) 57 | END 58 | | StepMsg: Steps(F) 59 | | RestoreMsg: Restore(F) 60 | | Oberon.CopyMsg: Oberon.Remove(T); NEW(F1); F1^ := F^; M.F := F1 61 | | MenuViewers.ModifyMsg: 62 | IF (M.Y # F.Y) OR (M.H # F.H) THEN F.Y := M.Y; F.H := M.H; Restore(F) END 63 | END 64 | END 65 | END Handle; 66 | 67 | PROCEDURE Step*; 68 | VAR k: INTEGER; M: StepMsg; 69 | BEGIN 70 | IF Oberon.Par.vwr.dsc = Oberon.Par.frame THEN Steps(Oberon.Par.frame.next(Frame)) 71 | ELSE Viewers.Broadcast(M) 72 | END 73 | END Step; 74 | 75 | PROCEDURE Open*; 76 | VAR F: Frame; V: Viewers.Viewer; X, Y: INTEGER; 77 | BEGIN NEW(F); F.handle := Handle; 78 | Oberon.AllocateUserViewer(Oberon.Par.vwr.X, X, Y); 79 | V := MenuViewers.New( 80 | TextFrames.NewMenu("Stars", "Stars.Close System.Grow System.Copy Stars.Step Stars.Run Stars.Stop"), 81 | F, TextFrames.menuH, X, Y) 82 | END Open; 83 | 84 | PROCEDURE Run*; 85 | BEGIN Oberon.Install(T) 86 | END Run; 87 | 88 | PROCEDURE Stop*; 89 | BEGIN Oberon.Remove(T) 90 | END Stop; 91 | 92 | PROCEDURE Close*; 93 | BEGIN 94 | IF Oberon.Par.vwr.dsc = Oberon.Par.frame THEN Stop; Viewers.Close(Oberon.Par.vwr) END 95 | END Close; 96 | 97 | PROCEDURE Step1; 98 | VAR M: StepMsg; 99 | BEGIN Viewers.Broadcast(M) 100 | END Step1; 101 | 102 | PROCEDURE SetPeriod*; 103 | VAR S: Texts.Scanner; 104 | BEGIN Texts.OpenScanner(S, Oberon.Par.text, Oberon.Par.pos); Texts.Scan(S); 105 | IF S.class = Texts.Int THEN T.period := S.i END 106 | END SetPeriod; 107 | 108 | BEGIN Texts.OpenWriter(W); T := Oberon.NewTask(Step1, interval); 109 | END Stars. 110 | -------------------------------------------------------------------------------- /people.inf.ethz.ch/wirth/ProjectOberon/Sources/System.Tool.txt: -------------------------------------------------------------------------------- 1 | System.Open ^ System.Recall System.Watch System.Collect 2 | Edit.Open ^ Edit.Recall 3 | Edit.ChangeFont Oberon10i.Scn.Fnt 4 | Edit.ChangeFont Oberon10b.Scn.Fnt 5 | 6 | System.Directory ^ 7 | *.Mod *.Bak *.Tool *.Text *.Scn.Fnt *.smb *.rsc 8 | 9 | ORP.Compile @ ORP.Compile @/s ORP.Compile name~ 10 | System.Free ~ 11 | System.Open Draw.Tool 12 | System.CopyFiles ~ 13 | System.RenameFiles ~ 14 | System.DeleteFiles ~ 15 | 16 | System.ShowModules System.ShowCommands ^ 17 | 18 | PCLink1.Run 19 | Hilbert.Draw Sierpinski.Draw Blink.Run Stars.Open 20 | 21 | Tools.Inspect 0 22 | Tools.Sector 1 23 | Tools.ShowFile 24 | Tools.Recall Tools.Clear 25 | -------------------------------------------------------------------------------- /people.inf.ethz.ch/wirth/ProjectOberon/Sources/Tools.Mod.txt: -------------------------------------------------------------------------------- 1 | MODULE Tools; (*NW 22.2.2014*) 2 | IMPORT SYSTEM, Kernel, Files, Modules, Input, Texts, Viewers, MenuViewers, TextFrames, Oberon; 3 | VAR T: Texts.Text; V: MenuViewers.Viewer; W: Texts.Writer; 4 | 5 | PROCEDURE OpenViewer(T: Texts.Text; title: ARRAY OF CHAR); 6 | VAR X, Y: INTEGER; 7 | BEGIN 8 | Oberon.AllocateUserViewer(0, X, Y); 9 | V := MenuViewers.New( 10 | TextFrames.NewMenu(title, "System.Close System.Copy System.Grow Edit.Search Edit.Store"), 11 | TextFrames.NewText(T, 0), TextFrames.menuH, X, Y) 12 | END OpenViewer; 13 | 14 | PROCEDURE Clear*; (*used to clear output*) 15 | VAR buf: Texts.Buffer; 16 | BEGIN NEW(buf); Texts.OpenBuf(buf); Texts.Delete(T, 0, T.len, buf) 17 | END Clear; 18 | 19 | PROCEDURE Recall*; 20 | VAR M: Viewers.ViewerMsg; 21 | BEGIN 22 | IF (V # NIL) & (V.state = 0) THEN 23 | Viewers.Open(V, V.X, V.Y + V.H); M.id := Viewers.restore; V.handle(V, M) 24 | END 25 | END Recall; 26 | 27 | PROCEDURE Inspect*; 28 | VAR m, n, adr, data: INTEGER; 29 | S: Texts.Scanner; 30 | BEGIN Texts.OpenScanner(S, Oberon.Par.text, Oberon.Par.pos); Texts.Scan(S); 31 | IF S.class = Texts.Int THEN 32 | adr := S.i DIV 20H * 20H; Texts.Scan(S); 33 | IF S.class = Texts.Int THEN n := S.i ELSE n := 8 END ; 34 | REPEAT DEC(n); Texts.WriteLn(W); Texts.WriteHex(W, adr); Texts.Write(W, 9X); m := 8; 35 | REPEAT SYSTEM.GET(adr, data); INC(adr, 4); Texts.WriteHex(W, data); DEC(m) 36 | UNTIL m = 0 37 | UNTIL n = 0; 38 | Texts.WriteLn(W); Texts.Append(T, W.buf) 39 | END 40 | END Inspect; 41 | 42 | PROCEDURE Sector*; 43 | VAR k, m, n, secno: INTEGER; 44 | S: Texts.Scanner; 45 | buf: ARRAY 256 OF INTEGER; 46 | BEGIN Texts.OpenScanner(S, Oberon.Par.text, Oberon.Par.pos); Texts.Scan(S); 47 | IF S.class = Texts.Int THEN 48 | secno := S.i; Texts.Scan(S); 49 | IF S.class = Texts.Int THEN n := S.i ELSE n := 8 END ; 50 | Kernel.GetSector(secno*29, buf); Texts.WriteString(W, "Sector "); Texts.WriteInt(W, S.i, 4); 51 | k := 0; 52 | REPEAT DEC(n); m := 8; Texts.WriteLn(W); Texts.WriteHex(W, k*4); Texts.Write(W, 9X); 53 | REPEAT Texts.WriteHex(W, buf[k]); INC(k); DEC(m) UNTIL m = 0; 54 | UNTIL n = 0; 55 | Texts.WriteLn(W); Texts.Append(T, W.buf) 56 | END 57 | END Sector; 58 | 59 | PROCEDURE ShowFile*; 60 | VAR x, n: INTEGER; 61 | F: Files.File; R: Files.Rider; 62 | S: Texts.Scanner; 63 | BEGIN Texts.OpenScanner(S, Oberon.Par.text, Oberon.Par.pos); Texts.Scan(S); 64 | IF S.class = Texts.Name THEN 65 | Texts.WriteString(W, S.s); F := Files.Old(S.s); 66 | IF F # NIL THEN 67 | n := 0; Files.Set(R, F, 0); Files.ReadInt(R, x); 68 | WHILE ~R.eof DO 69 | IF n MOD 20H = 0 THEN Texts.WriteLn(W); Texts.WriteHex(W, n); Texts.Write(W, 9X) END ; 70 | Texts.WriteHex(W, x); INC(n, 4); Files.ReadInt(R, x) 71 | END ; 72 | Texts.WriteHex(W, x) 73 | ELSE Texts.WriteString(W, " not found") 74 | END ; 75 | Texts.WriteLn(W); Texts.Append(T, W.buf) 76 | END 77 | END ShowFile; 78 | 79 | PROCEDURE Convert*; (*convert selected text to txt-format*) 80 | VAR beg, end, time: LONGINT 81 | ; ch: CHAR; 82 | T: Texts.Text; R: Texts.Reader; (*input*) 83 | F: Files.File; Q: Files.Rider; (*output*) 84 | S: Texts.Scanner; 85 | BEGIN Oberon.GetSelection(T, beg, end, time); 86 | IF time >= 0 THEN 87 | Texts.OpenScanner(S, Oberon.Par.text, Oberon.Par.pos); Texts.Scan(S); 88 | Texts.WriteString(W, "converting to "); Texts.WriteString(W, S.s); 89 | F := Files.New(S.s); Files.Set(Q, F, 0); Texts.OpenReader(R, T, beg); Texts.Read(R, ch); 90 | WHILE ~R.eot DO 91 | IF ch = 0DX THEN Files.Write(Q, 0DX); Files.Write(Q, 0AX) 92 | ELSIF ch = 9X THEN (*TAB*) Files.Write(Q, " "); Files.Write(Q, " ") 93 | ELSE Files.Write(Q, ch) 94 | END ; 95 | Texts.Read(R, ch) 96 | END ; 97 | Files.Register(F); Texts.WriteString(W, " done") 98 | ELSE Texts.WriteString(W, " not found") 99 | END ; 100 | Texts.WriteLn(W); Texts.Append(Oberon.Log, W.buf); Texts.Scan(S) 101 | END Convert; 102 | 103 | PROCEDURE Id*; 104 | BEGIN Texts.WriteHex(W, SYSTEM.H(1)); Texts.WriteLn(W); Texts.Append(T, W.buf) 105 | END Id; 106 | 107 | BEGIN Texts.OpenWriter(W); T := TextFrames.Text(""); OpenViewer(T, "Tools.Text") 108 | END Tools. 109 | 110 | Tools.Clear (clear tool viewer) 111 | Tools.Recall (recall closed tool viewer) 112 | Tools.Inspect adr len 113 | Tools.Sector secno 114 | Tools.ShowFile filename (in hex) 115 | Tools.Convert filename (selected text to txt-format) 116 | Tools.Id (processor id) 117 | -------------------------------------------------------------------------------- /people.inf.ethz.ch/wirth/ProjectOberon/SourcesVerilog/Divider.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps // NW 20.9.2015 2 | 3 | module Divider( 4 | input clk, run, u, 5 | output stall, 6 | input [31:0] x, y, // y > 0 7 | output [31:0] quot, rem); 8 | 9 | reg [5:0] S; // state 10 | reg [63:0] RQ; 11 | wire sign; 12 | wire [31:0] x0, w0, w1; 13 | 14 | assign stall = run & ~(S == 33); 15 | assign sign = x[31] & u; 16 | assign x0 = sign ? -x : x; 17 | assign w0 = RQ[62: 31]; 18 | assign w1 = w0 - y; 19 | assign quot = ~sign ? RQ[31:0] : 20 | (RQ[63:32] == 0) ? -RQ[31:0] : -RQ[31:0] - 1; 21 | assign rem = ~sign ? RQ[63:32] : 22 | (RQ[63:32] == 0) ? 0 : y - RQ[63:32]; 23 | 24 | always @ (posedge(clk)) begin 25 | RQ <= (S == 0) ? {32'b0, x0} : {(w1[31] ? w0 : w1), RQ[30:0], ~w1[31]}; 26 | S <= run ? S+1 : 0; 27 | end 28 | endmodule 29 | -------------------------------------------------------------------------------- /people.inf.ethz.ch/wirth/ProjectOberon/SourcesVerilog/Divider.v.html: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps // NW 20.9.2015 2 | 3 | module Divider( 4 | input clk, run, u, 5 | output stall, 6 | input [31:0] x, y, // y > 0 7 | output [31:0] quot, rem); 8 | 9 | reg [5:0] S; // state 10 | reg [63:0] RQ; 11 | wire sign; 12 | wire [31:0] x0, w0, w1; 13 | 14 | assign stall = run & ~(S == 33); 15 | assign sign = x[31] & u; 16 | assign x0 = sign ? -x : x; 17 | assign w0 = RQ[62: 31]; 18 | assign w1 = w0 - y; 19 | assign quot = ~sign ? RQ[31:0] : 20 | (RQ[63:32] == 0) ? -RQ[31:0] : -RQ[31:0] - 1; 21 | assign rem = ~sign ? RQ[63:32] : 22 | (RQ[63:32] == 0) ? 0 : y - RQ[63:32]; 23 | 24 | always @ (posedge(clk)) begin 25 | RQ <= (S == 0) ? {32'b0, x0} : {(w1[31] ? w0 : w1), RQ[30:0], ~w1[31]}; 26 | S <= run ? S+1 : 0; 27 | end 28 | endmodule 29 | -------------------------------------------------------------------------------- /people.inf.ethz.ch/wirth/ProjectOberon/SourcesVerilog/Divider0.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps // NW 31.10.10 2 | 3 | module Divider( 4 | input clk, run, 5 | output stall, 6 | input [31:0] x, y, // x >= 0, y > 0 7 | output [31:0] quot, rem); 8 | 9 | reg [4:0] S; // state 10 | reg [31:0] R, Q; 11 | wire [31:0] r0, r1, r2, q0, q1, d; 12 | 13 | assign stall = run & ~(S == 31); 14 | assign r0 = (S == 0) ? 0 : R; 15 | assign d = r1 - y; 16 | assign r1 = {r0[30:0], q0[31]}; 17 | assign r2 = d[31] ? r1 : d; 18 | assign q0 = (S == 0) ? x : Q; 19 | assign q1 = {q0[30:0], ~d[31]}; 20 | assign rem = r2; 21 | assign quot = q1; 22 | 23 | always @ (posedge(clk)) begin 24 | R <= r2; Q <= q1; 25 | S <= run ? S+1 : 0; 26 | end 27 | 28 | endmodule 29 | -------------------------------------------------------------------------------- /people.inf.ethz.ch/wirth/ProjectOberon/SourcesVerilog/Divider0.v.html: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps // NW 31.10.10 2 | 3 | module Divider( 4 | input clk, run, 5 | output stall, 6 | input [31:0] x, y, // x >= 0, y > 0 7 | output [31:0] quot, rem); 8 | 9 | reg [4:0] S; // state 10 | reg [31:0] R, Q; 11 | wire [31:0] r0, r1, r2, q0, q1, d; 12 | 13 | assign stall = run & ~(S == 31); 14 | assign r0 = (S == 0) ? 0 : R; 15 | assign d = r1 - y; 16 | assign r1 = {r0[30:0], q0[31]}; 17 | assign r2 = d[31] ? r1 : d; 18 | assign q0 = (S == 0) ? x : Q; 19 | assign q1 = {q0[30:0], ~d[31]}; 20 | assign rem = r2; 21 | assign quot = q1; 22 | 23 | always @ (posedge(clk)) begin 24 | R <= r2; Q <= q1; 25 | S <= run ? S+1 : 0; 26 | end 27 | 28 | endmodule 29 | -------------------------------------------------------------------------------- /people.inf.ethz.ch/wirth/ProjectOberon/SourcesVerilog/FPAdder.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps // NW 4.10.2016 pipelined 2 | // u = 1: FLT; v = 1: FLOOR 3 | 4 | module FPAdder( 5 | input clk, run, u, v, 6 | input [31:0] x, y, 7 | output stall, 8 | output [31:0] z); 9 | 10 | reg [1:0] State; 11 | 12 | wire xs, ys, xn, yn; // signs, null 13 | wire [7:0] xe, ye; 14 | wire [24:0] xm, ym; 15 | 16 | wire [8:0] dx, dy, e0, e1; 17 | wire [7:0] sx, sy; // shift counts 18 | wire [1:0] sx0, sx1, sy0, sy1; 19 | wire sxh, syh; 20 | wire [24:0] x0, x1, x2, y0, y1, y2; 21 | reg [24:0] x3, y3; 22 | 23 | reg [26:0] Sum; 24 | wire [26:0] s; 25 | 26 | wire z24, z22, z20, z18, z16, z14, z12, z10, z8, z6, z4, z2; 27 | wire [4:0] sc; // shift count 28 | wire [1:0] sc0, sc1; 29 | wire [24:0] t1, t2; 30 | reg [24:0] t3; 31 | 32 | assign xs = x[31]; // sign x 33 | assign xe = u ? 8'h96 : x[30:23]; // expo x 34 | assign xm = {~u|x[23], x[22:0], 1'b0}; //mant x 35 | assign xn = (x[30:0] == 0); 36 | assign ys = y[31]; // sign y 37 | assign ye = y[30:23]; // expo y 38 | assign ym = {~u&~v, y[22:0], 1'b0}; //mant y 39 | assign yn = (y[30:0] == 0); 40 | 41 | assign dx = xe - ye; 42 | assign dy = ye - xe; 43 | assign e0 = (dx[8]) ? ye : xe; 44 | assign sx = dy[8] ? 0 : dy; 45 | assign sy = dx[8] ? 0 : dx; 46 | assign sx0 = sx[1:0]; 47 | assign sx1 = sx[3:2]; 48 | assign sy0 = sy[1:0]; 49 | assign sy1 = sy[3:2]; 50 | assign sxh = sx[7] | sx[6] | sx[5]; 51 | assign syh = sy[7] | sy[6] | sy[5]; 52 | 53 | // denormalize, shift right 54 | assign x0 = xs&~u ? -xm : xm; 55 | assign x1 = (sx0 == 3) ? {{3{xs}}, x0[24:3]} : 56 | (sx0 == 2) ? {{2{xs}}, x0[24:2]} : (sx0 == 1) ? {xs, x0[24:1]} : x0; 57 | assign x2 = (sx1 == 3) ? {{12{xs}}, x1[24:12]} : 58 | (sx1 == 2) ? {{8{xs}}, x1[24:8]} : (sx1 == 1) ? {{4{xs}}, x1[24:4]} : x1; 59 | always @ (posedge(clk)) 60 | x3 <= sxh ? {25{xs}} : (sx[4] ? {{16{xs}}, x2[24:16]} : x2); 61 | 62 | assign y0 = ys&~u ? -ym : ym; 63 | assign y1 = (sy0 == 3) ? {{3{ys}}, y0[24:3]} : 64 | (sy0 == 2) ? {{2{ys}}, y0[24:2]} : (sy0 == 1) ? {ys, y0[24:1]} : y0; 65 | assign y2 = (sy1 == 3) ? {{12{ys}}, y1[24:12]} : 66 | (sy1 == 2) ? {{8{ys}}, y1[24:8]} : (sy1 == 1) ? {{4{ys}}, y1[24:4]} : y1; 67 | always @ (posedge(clk)) 68 | y3 <= syh ? {25{ys}} : (sy[4] ? {{16{ys}}, y2[24:16]} : y2); 69 | 70 | // add 71 | always @ (posedge(clk)) Sum <= {xs, xs, x3} + {ys, ys, y3}; 72 | assign s = (Sum[26] ? -Sum : Sum) + 1; 73 | 74 | // post-normalize 75 | assign z24 = ~s[25] & ~ s[24]; 76 | assign z22 = z24 & ~s[23] & ~s[22]; 77 | assign z20 = z22 & ~s[21] & ~s[20]; 78 | assign z18 = z20 & ~s[19] & ~s[18]; 79 | assign z16 = z18 & ~s[17] & ~s[16]; 80 | assign z14 = z16 & ~s[15] & ~s[14]; 81 | assign z12 = z14 & ~s[13] & ~s[12]; 82 | assign z10 = z12 & ~s[11] & ~s[10]; 83 | assign z8 = z10 & ~s[9] & ~s[8]; 84 | assign z6 = z8 & ~s[7] & ~s[6]; 85 | assign z4 = z6 & ~s[5] & ~s[4]; 86 | assign z2 = z4 & ~s[3] & ~s[2]; 87 | 88 | assign sc[4] = z10; // sc = shift count of post normalization 89 | assign sc[3] = z18 & (s[17] | s[16] | s[15] | s[14] | s[13] | s[12] | s[11] | s[10]) 90 | | z2; 91 | assign sc[2] = z22 & (s[21] | s[20] | s[19] | s[18]) 92 | | z14 & (s[13] | s[12] | s[11] | s[10]) 93 | | z6 & (s[5] | s[4] | s[3] | s[2]); 94 | assign sc[1] = z24 & (s[23] | s[22]) 95 | | z20 & (s[19] | s[18]) 96 | | z16 & (s[15] | s[14]) 97 | | z12 & (s[11] | s[10]) 98 | | z8 & (s[7] | s[6]) 99 | | z4 & (s[3] | s[2]); 100 | assign sc[0] = ~s[25] & s[24] 101 | | z24 & ~s[23] & s[22] 102 | | z22 & ~s[21] & s[20] 103 | | z20 & ~s[19] & s[18] 104 | | z18 & ~s[17] & s[16] 105 | | z16 & ~s[15] & s[14] 106 | | z14 & ~s[13] & s[12] 107 | | z12 & ~s[11] & s[10] 108 | | z10 & ~s[9] & s[8] 109 | | z8 & ~s[7] & s[6] 110 | | z6 & ~s[5] & s[4] 111 | | z4 & ~s[3] & s[2]; 112 | 113 | assign e1 = e0 - sc + 1; 114 | assign sc0 = sc[1:0]; 115 | assign sc1 = sc[3:2]; 116 | 117 | assign t1 = (sc0 == 3) ? {s[22:1], 3'b0} : 118 | (sc0 == 2) ? {s[23:1], 2'b0} : (sc0 == 1) ? {s[24:1], 1'b0} : s[25:1]; 119 | assign t2 = (sc1 == 3) ? {t1[12:0], 12'b0} : 120 | (sc1 == 2) ? {t1[16:0], 8'b0} : (sc1 == 1) ? {t1[20:0], 4'b0} : t1; 121 | always @ (posedge(clk)) t3 <= sc[4] ? {t2[8:0], 16'b0} : t2; 122 | 123 | assign stall = run & ~(State == 3); 124 | always @ (posedge(clk)) State <= run ? State + 1 : 0; 125 | 126 | assign z = v ? {{7{Sum[26]}}, Sum[25:1]} : // FLOOR 127 | xn ? (u|yn ? 0 : y) : // FLT or x = y = 0 128 | yn ? x : 129 | ((t3 == 0) | e1[8]) ? 0 : 130 | {Sum[26], e1[7:0], t3[23:1]}; 131 | endmodule 132 | 133 | -------------------------------------------------------------------------------- /people.inf.ethz.ch/wirth/ProjectOberon/SourcesVerilog/FPAdder.v.html: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps // NW 4.10.2016 pipelined 2 | // u = 1: FLT; v = 1: FLOOR 3 | 4 | module FPAdder( 5 | input clk, run, u, v, 6 | input [31:0] x, y, 7 | output stall, 8 | output [31:0] z); 9 | 10 | reg [1:0] State; 11 | 12 | wire xs, ys, xn, yn; // signs, null 13 | wire [7:0] xe, ye; 14 | wire [24:0] xm, ym; 15 | 16 | wire [8:0] dx, dy, e0, e1; 17 | wire [7:0] sx, sy; // shift counts 18 | wire [1:0] sx0, sx1, sy0, sy1; 19 | wire sxh, syh; 20 | wire [24:0] x0, x1, x2, y0, y1, y2; 21 | reg [24:0] x3, y3; 22 | 23 | reg [26:0] Sum; 24 | wire [26:0] s; 25 | 26 | wire z24, z22, z20, z18, z16, z14, z12, z10, z8, z6, z4, z2; 27 | wire [4:0] sc; // shift count 28 | wire [1:0] sc0, sc1; 29 | wire [24:0] t1, t2; 30 | reg [24:0] t3; 31 | 32 | assign xs = x[31]; // sign x 33 | assign xe = u ? 8'h96 : x[30:23]; // expo x 34 | assign xm = {~u|x[23], x[22:0], 1'b0}; //mant x 35 | assign xn = (x[30:0] == 0); 36 | assign ys = y[31]; // sign y 37 | assign ye = y[30:23]; // expo y 38 | assign ym = {~u&~v, y[22:0], 1'b0}; //mant y 39 | assign yn = (y[30:0] == 0); 40 | 41 | assign dx = xe - ye; 42 | assign dy = ye - xe; 43 | assign e0 = (dx[8]) ? ye : xe; 44 | assign sx = dy[8] ? 0 : dy; 45 | assign sy = dx[8] ? 0 : dx; 46 | assign sx0 = sx[1:0]; 47 | assign sx1 = sx[3:2]; 48 | assign sy0 = sy[1:0]; 49 | assign sy1 = sy[3:2]; 50 | assign sxh = sx[7] | sx[6] | sx[5]; 51 | assign syh = sy[7] | sy[6] | sy[5]; 52 | 53 | // denormalize, shift right 54 | assign x0 = xs&~u ? -xm : xm; 55 | assign x1 = (sx0 == 3) ? {{3{xs}}, x0[24:3]} : 56 | (sx0 == 2) ? {{2{xs}}, x0[24:2]} : (sx0 == 1) ? {xs, x0[24:1]} : x0; 57 | assign x2 = (sx1 == 3) ? {{12{xs}}, x1[24:12]} : 58 | (sx1 == 2) ? {{8{xs}}, x1[24:8]} : (sx1 == 1) ? {{4{xs}}, x1[24:4]} : x1; 59 | always @ (posedge(clk)) 60 | x3 <= sxh ? {25{xs}} : (sx[4] ? {{16{xs}}, x2[24:16]} : x2); 61 | 62 | assign y0 = ys&~u ? -ym : ym; 63 | assign y1 = (sy0 == 3) ? {{3{ys}}, y0[24:3]} : 64 | (sy0 == 2) ? {{2{ys}}, y0[24:2]} : (sy0 == 1) ? {ys, y0[24:1]} : y0; 65 | assign y2 = (sy1 == 3) ? {{12{ys}}, y1[24:12]} : 66 | (sy1 == 2) ? {{8{ys}}, y1[24:8]} : (sy1 == 1) ? {{4{ys}}, y1[24:4]} : y1; 67 | always @ (posedge(clk)) 68 | y3 <= syh ? {25{ys}} : (sy[4] ? {{16{ys}}, y2[24:16]} : y2); 69 | 70 | // add 71 | always @ (posedge(clk)) Sum <= {xs, xs, x3} + {ys, ys, y3}; 72 | assign s = (Sum[26] ? -Sum : Sum) + 1; 73 | 74 | // post-normalize 75 | assign z24 = ~s[25] & ~ s[24]; 76 | assign z22 = z24 & ~s[23] & ~s[22]; 77 | assign z20 = z22 & ~s[21] & ~s[20]; 78 | assign z18 = z20 & ~s[19] & ~s[18]; 79 | assign z16 = z18 & ~s[17] & ~s[16]; 80 | assign z14 = z16 & ~s[15] & ~s[14]; 81 | assign z12 = z14 & ~s[13] & ~s[12]; 82 | assign z10 = z12 & ~s[11] & ~s[10]; 83 | assign z8 = z10 & ~s[9] & ~s[8]; 84 | assign z6 = z8 & ~s[7] & ~s[6]; 85 | assign z4 = z6 & ~s[5] & ~s[4]; 86 | assign z2 = z4 & ~s[3] & ~s[2]; 87 | 88 | assign sc[4] = z10; // sc = shift count of post normalization 89 | assign sc[3] = z18 & (s[17] | s[16] | s[15] | s[14] | s[13] | s[12] | s[11] | s[10]) 90 | | z2; 91 | assign sc[2] = z22 & (s[21] | s[20] | s[19] | s[18]) 92 | | z14 & (s[13] | s[12] | s[11] | s[10]) 93 | | z6 & (s[5] | s[4] | s[3] | s[2]); 94 | assign sc[1] = z24 & (s[23] | s[22]) 95 | | z20 & (s[19] | s[18]) 96 | | z16 & (s[15] | s[14]) 97 | | z12 & (s[11] | s[10]) 98 | | z8 & (s[7] | s[6]) 99 | | z4 & (s[3] | s[2]); 100 | assign sc[0] = ~s[25] & s[24] 101 | | z24 & ~s[23] & s[22] 102 | | z22 & ~s[21] & s[20] 103 | | z20 & ~s[19] & s[18] 104 | | z18 & ~s[17] & s[16] 105 | | z16 & ~s[15] & s[14] 106 | | z14 & ~s[13] & s[12] 107 | | z12 & ~s[11] & s[10] 108 | | z10 & ~s[9] & s[8] 109 | | z8 & ~s[7] & s[6] 110 | | z6 & ~s[5] & s[4] 111 | | z4 & ~s[3] & s[2]; 112 | 113 | assign e1 = e0 - sc + 1; 114 | assign sc0 = sc[1:0]; 115 | assign sc1 = sc[3:2]; 116 | 117 | assign t1 = (sc0 == 3) ? {s[22:1], 3'b0} : 118 | (sc0 == 2) ? {s[23:1], 2'b0} : (sc0 == 1) ? {s[24:1], 1'b0} : s[25:1]; 119 | assign t2 = (sc1 == 3) ? {t1[12:0], 12'b0} : 120 | (sc1 == 2) ? {t1[16:0], 8'b0} : (sc1 == 1) ? {t1[20:0], 4'b0} : t1; 121 | always @ (posedge(clk)) t3 <= sc[4] ? {t2[8:0], 16'b0} : t2; 122 | 123 | assign stall = run & ~(State == 3); 124 | always @ (posedge(clk)) State <= run ? State + 1 : 0; 125 | 126 | assign z = v ? {{7{Sum[26]}}, Sum[25:1]} : // FLOOR 127 | xn ? (u|yn ? 0 : y) : // FLT or x = y = 0 128 | yn ? x : 129 | ((t3 == 0) | e1[8]) ? 0 : 130 | {Sum[26], e1[7:0], t3[23:1]}; 131 | endmodule 132 | 133 | -------------------------------------------------------------------------------- /people.inf.ethz.ch/wirth/ProjectOberon/SourcesVerilog/FPDivider.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps // NW 16.9.2016 2 | 3 | module FPDivider( 4 | input clk, run, 5 | input [31:0] x, 6 | input [31:0] y, 7 | output stall, 8 | output [31:0] z); 9 | 10 | reg [4:0] S; // state 11 | reg [23:0] R; 12 | reg [25:0] Q; 13 | 14 | wire sign; 15 | wire [7:0] xe, ye; 16 | wire [8:0] e0, e1; 17 | wire [24:0] r0, r1, d; 18 | wire [25:0] q0; 19 | wire [24:0] z0, z1; 20 | 21 | assign sign = x[31]^y[31]; 22 | assign xe = x[30:23]; 23 | assign ye = y[30:23]; 24 | assign e0 = {1'b0, xe} - {1'b0, ye}; 25 | assign e1 = e0 + 126 + Q[25]; 26 | assign stall = run & ~(S == 26); 27 | 28 | assign r0 = (S == 0) ? {2'b01, x[22:0]} : {R, 1'b0}; 29 | assign r1 = d[24] ? r0 : d; 30 | assign d = r0 - {2'b01, y[22:0]}; 31 | assign q0 = (S == 0) ? 0 : Q; 32 | 33 | assign z0 = Q[25] ? Q[25:1] : Q[24:0]; 34 | assign z1 = z0 + 1; 35 | assign z = (xe == 0) ? 0 : 36 | (ye == 0) ? {sign, 8'b11111111, 23'b0} : // div by 0 37 | (~e1[8]) ? {sign, e1[7:0], z1[23:1]} : 38 | (~e1[7]) ? {sign, 8'b11111111, z0[23:1]} : 0; // NaN 39 | 40 | always @ (posedge(clk)) begin 41 | R <= r1[23:0]; 42 | Q <= {q0[24:0], ~d[24]}; 43 | S <= run ? S+1 : 0; 44 | end 45 | endmodule 46 | -------------------------------------------------------------------------------- /people.inf.ethz.ch/wirth/ProjectOberon/SourcesVerilog/FPDivider.v.html: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps // NW 16.9.2016 2 | 3 | module FPDivider( 4 | input clk, run, 5 | input [31:0] x, 6 | input [31:0] y, 7 | output stall, 8 | output [31:0] z); 9 | 10 | reg [4:0] S; // state 11 | reg [23:0] R; 12 | reg [25:0] Q; 13 | 14 | wire sign; 15 | wire [7:0] xe, ye; 16 | wire [8:0] e0, e1; 17 | wire [24:0] r0, r1, d; 18 | wire [25:0] q0; 19 | wire [24:0] z0, z1; 20 | 21 | assign sign = x[31]^y[31]; 22 | assign xe = x[30:23]; 23 | assign ye = y[30:23]; 24 | assign e0 = {1'b0, xe} - {1'b0, ye}; 25 | assign e1 = e0 + 126 + Q[25]; 26 | assign stall = run & ~(S == 26); 27 | 28 | assign r0 = (S == 0) ? {2'b01, x[22:0]} : {R, 1'b0}; 29 | assign r1 = d[24] ? r0 : d; 30 | assign d = r0 - {2'b01, y[22:0]}; 31 | assign q0 = (S == 0) ? 0 : Q; 32 | 33 | assign z0 = Q[25] ? Q[25:1] : Q[24:0]; 34 | assign z1 = z0 + 1; 35 | assign z = (xe == 0) ? 0 : 36 | (ye == 0) ? {sign, 8'b11111111, 23'b0} : // div by 0 37 | (~e1[8]) ? {sign, e1[7:0], z1[23:1]} : 38 | (~e1[7]) ? {sign, 8'b11111111, z0[23:1]} : 0; // NaN 39 | 40 | always @ (posedge(clk)) begin 41 | R <= r1[23:0]; 42 | Q <= {q0[24:0], ~d[24]}; 43 | S <= run ? S+1 : 0; 44 | end 45 | endmodule 46 | -------------------------------------------------------------------------------- /people.inf.ethz.ch/wirth/ProjectOberon/SourcesVerilog/FPMultiplier.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps // NW 15.9.2015 8.8.2016 2 | module FPMultiplier( 3 | input clk, run, 4 | input [31:0] x, y, 5 | output stall, 6 | output [31:0] z); 7 | 8 | reg [4:0] S; // state 9 | reg [47:0] P; // product 10 | 11 | wire sign; 12 | wire [7:0] xe, ye; 13 | wire [8:0] e0, e1; 14 | wire [24:0] w1, z0; 15 | wire [23:0] w0; 16 | 17 | assign sign = x[31] ^ y[31]; 18 | assign xe = x[30:23]; 19 | assign ye = y[30:23]; 20 | assign e0 = xe + ye; 21 | assign e1 = e0 - 127 + P[47]; 22 | 23 | assign stall = run & ~(S == 25); 24 | assign w0 = P[0] ? {1'b1, y[22:0]} : 0; 25 | assign w1 = {1'b0, P[47:24]} + {1'b0, w0}; 26 | assign z0 = P[47] ? P[47:23]+1 : P[46:22]+1; // round and normalize 27 | assign z = (xe == 0) | (ye == 0) ? 0 : 28 | (~e1[8]) ? {sign, e1[7:0], z0[23:1]} : 29 | (~e1[7]) ? {sign, 8'b11111111, z0[23:1]} : 0; 30 | always @ (posedge(clk)) begin 31 | P <= (S == 0) ? {24'b0, 1'b1, x[22:0]} : {w1, P[23:1]}; 32 | S <= run ? S+1 : 0; 33 | end 34 | endmodule 35 | -------------------------------------------------------------------------------- /people.inf.ethz.ch/wirth/ProjectOberon/SourcesVerilog/FPMultiplier.v.html: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps // NW 15.9.2015 8.8.2016 2 | module FPMultiplier( 3 | input clk, run, 4 | input [31:0] x, y, 5 | output stall, 6 | output [31:0] z); 7 | 8 | reg [4:0] S; // state 9 | reg [47:0] P; // product 10 | 11 | wire sign; 12 | wire [7:0] xe, ye; 13 | wire [8:0] e0, e1; 14 | wire [24:0] w1, z0; 15 | wire [23:0] w0; 16 | 17 | assign sign = x[31] ^ y[31]; 18 | assign xe = x[30:23]; 19 | assign ye = y[30:23]; 20 | assign e0 = xe + ye; 21 | assign e1 = e0 - 127 + P[47]; 22 | 23 | assign stall = run & ~(S == 25); 24 | assign w0 = P[0] ? {1'b1, y[22:0]} : 0; 25 | assign w1 = {1'b0, P[47:24]} + {1'b0, w0}; 26 | assign z0 = P[47] ? P[47:23]+1 : P[46:22]+1; // round and normalize 27 | assign z = (xe == 0) | (ye == 0) ? 0 : 28 | (~e1[8]) ? {sign, e1[7:0], z0[23:1]} : 29 | (~e1[7]) ? {sign, 8'b11111111, z0[23:1]} : 0; 30 | always @ (posedge(clk)) begin 31 | P <= (S == 0) ? {24'b0, 1'b1, x[22:0]} : {w1, P[23:1]}; 32 | S <= run ? S+1 : 0; 33 | end 34 | endmodule 35 | -------------------------------------------------------------------------------- /people.inf.ethz.ch/wirth/ProjectOberon/SourcesVerilog/LeftShifter.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps // NW 9.11.2016 2 | 3 | module LeftShifter( 4 | input [31:0] x, 5 | input [4:0] sc, 6 | output [31:0] y); 7 | 8 | // shifter for LSL 9 | wire [1:0] sc0, sc1; 10 | wire [31:0] t1, t2; 11 | 12 | assign sc0 = sc[1:0]; 13 | assign sc1 = sc[3:2]; 14 | 15 | assign t1 = (sc0 == 3) ? {x[28:0], 3'b0} : 16 | (sc0 == 2) ? {x[29:0], 2'b0} : 17 | (sc0 == 1) ? {x[30:0], 1'b0} : x; 18 | assign t2 = (sc1 == 3) ? {t1[19:0], 12'b0} : 19 | (sc1 == 2) ? {t1[23:0], 8'b0} : 20 | (sc1 == 1) ? {t1[27:0], 4'b0} : t1; 21 | assign y = sc[4] ? {t2[15:0], 16'b0} : t2; 22 | endmodule -------------------------------------------------------------------------------- /people.inf.ethz.ch/wirth/ProjectOberon/SourcesVerilog/LeftShifter.v.html: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps // NW 9.11.2016 2 | 3 | module LeftShifter( 4 | input [31:0] x, 5 | input [4:0] sc, 6 | output [31:0] y); 7 | 8 | // shifter for LSL 9 | wire [1:0] sc0, sc1; 10 | wire [31:0] t1, t2; 11 | 12 | assign sc0 = sc[1:0]; 13 | assign sc1 = sc[3:2]; 14 | 15 | assign t1 = (sc0 == 3) ? {x[28:0], 3'b0} : 16 | (sc0 == 2) ? {x[29:0], 2'b0} : 17 | (sc0 == 1) ? {x[30:0], 1'b0} : x; 18 | assign t2 = (sc1 == 3) ? {t1[19:0], 12'b0} : 19 | (sc1 == 2) ? {t1[23:0], 8'b0} : 20 | (sc1 == 1) ? {t1[27:0], 4'b0} : t1; 21 | assign y = sc[4] ? {t2[15:0], 16'b0} : t2; 22 | endmodule -------------------------------------------------------------------------------- /people.inf.ethz.ch/wirth/ProjectOberon/SourcesVerilog/MouseP.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps // PS/2 Logitech mouse PDR 14.10.2013 / 8.9.2015 2 | module MouseP( 3 | input clk, rst, 4 | inout msclk, msdat, 5 | output [27:0] out); 6 | 7 | reg [9:0] x, y; 8 | reg [2:0] btns; 9 | reg Q0, Q1, run; 10 | reg [31:0] shreg; 11 | wire shift, endbit, reply; 12 | wire [9:0] dx, dy; 13 | 14 | // 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 bit 15 | // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 16 | // =============================================================== 17 | // p y y y y y y y y 0 1 p x x x x x x x x 0 1 p Y X t s 1 M R L 0 normal 18 | // --------------------------------------------------------------- 19 | // p ----response--- 0 1 --InitBuf echoed--- 1 1 1 1 1 1 1 1 1 1 1 init 20 | // --------------------------------------------------------------- 21 | // p = parity (ignored); X, Y = overflow; s, t = x, y sign bits 22 | 23 | // initially need to send F4 cmd (start reporting); add start and parity bits 24 | localparam InitBuf = 32'b11111111111111111111110_11110100_0; 25 | assign msclk = ~rst ? 0 : 1'bz; // initial drive clock low 26 | assign msdat = ~run & ~shreg[0] ? 0 : 1'bz; 27 | assign shift = Q1 & ~Q0; // falling edge detector 28 | assign reply = ~run & ~shreg[11]; // start bit of echoed InitBuf, if response 29 | assign endbit = run & ~shreg[0]; // normal packet received 30 | assign dx = {{2{shreg[5]}}, shreg[7] ? 8'b0 : shreg[19:12]}; //sign+overfl 31 | assign dy = {{2{shreg[6]}}, shreg[8] ? 8'b0 : shreg[30:23]}; //sign+overfl 32 | assign out = {run, btns, 2'b0, y, 2'b0, x}; 33 | 34 | always @ (posedge clk) begin 35 | run <= rst & (reply | run); Q0 <= msclk; Q1 <= Q0; 36 | shreg <= ~rst ? InitBuf : (endbit | reply) ? -1 : shift ? {msdat, 37 | shreg[31:1]} : shreg; 38 | x <= ~rst ? 0 : endbit ? x + dx : x; y <= ~rst ? 0 : endbit ? y + dy 39 | : y; 40 | btns <= ~rst ? 0 : endbit ? {shreg[1], shreg[3], shreg[2]} : btns; 41 | end 42 | 43 | endmodule 44 | 45 | -------------------------------------------------------------------------------- /people.inf.ethz.ch/wirth/ProjectOberon/SourcesVerilog/MouseP.v.html: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps // PS/2 Logitech mouse PDR 14.10.2013 / 8.9.2015 2 | module MouseP( 3 | input clk, rst, 4 | inout msclk, msdat, 5 | output [27:0] out); 6 | 7 | reg [9:0] x, y; 8 | reg [2:0] btns; 9 | reg Q0, Q1, run; 10 | reg [31:0] shreg; 11 | wire shift, endbit, reply; 12 | wire [9:0] dx, dy; 13 | 14 | // 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 bit 15 | // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 16 | // =============================================================== 17 | // p y y y y y y y y 0 1 p x x x x x x x x 0 1 p Y X t s 1 M R L 0 normal 18 | // --------------------------------------------------------------- 19 | // p ----response--- 0 1 --InitBuf echoed--- 1 1 1 1 1 1 1 1 1 1 1 init 20 | // --------------------------------------------------------------- 21 | // p = parity (ignored); X, Y = overflow; s, t = x, y sign bits 22 | 23 | // initially need to send F4 cmd (start reporting); add start and parity bits 24 | localparam InitBuf = 32'b11111111111111111111110_11110100_0; 25 | assign msclk = ~rst ? 0 : 1'bz; // initial drive clock low 26 | assign msdat = ~run & ~shreg[0] ? 0 : 1'bz; 27 | assign shift = Q1 & ~Q0; // falling edge detector 28 | assign reply = ~run & ~shreg[11]; // start bit of echoed InitBuf, if response 29 | assign endbit = run & ~shreg[0]; // normal packet received 30 | assign dx = {{2{shreg[5]}}, shreg[7] ? 8'b0 : shreg[19:12]}; //sign+overfl 31 | assign dy = {{2{shreg[6]}}, shreg[8] ? 8'b0 : shreg[30:23]}; //sign+overfl 32 | assign out = {run, btns, 2'b0, y, 2'b0, x}; 33 | 34 | always @ (posedge clk) begin 35 | run <= rst & (reply | run); Q0 <= msclk; Q1 <= Q0; 36 | shreg <= ~rst ? InitBuf : (endbit | reply) ? -1 : shift ? {msdat, 37 | shreg[31:1]} : shreg; 38 | x <= ~rst ? 0 : endbit ? x + dx : x; y <= ~rst ? 0 : endbit ? y + dy 39 | : y; 40 | btns <= ~rst ? 0 : endbit ? {shreg[1], shreg[3], shreg[2]} : btns; 41 | end 42 | 43 | endmodule 44 | 45 | -------------------------------------------------------------------------------- /people.inf.ethz.ch/wirth/ProjectOberon/SourcesVerilog/MouseX.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | // N.Wirth 10.10.2012 3 | module MouseX( 4 | input clk, 5 | input [6:0] in, 6 | output [27:0] out); 7 | 8 | reg x00, x01, x10, x11, y00, y01, y10, y11; 9 | reg ML, MM, MR; // keys 10 | reg [9:0] x, y; // counters 11 | 12 | wire xup, xdn, yup, ydn; 13 | 14 | assign xup = ~x00&~x01&~x10&x11 | ~x00&x01&x10&x11 | x00&~x01&~x10&~x11 | x00&x01&x10&~x11; 15 | assign yup = ~y00&~y01&~y10&y11 | ~y00&y01&y10&y11 | y00&~y01&~y10&~y11 | y00&y01&y10&~y11; 16 | assign xdn = ~x00&~x01&x10&~x11 | ~x00&x01&~x10&~x11 | x00&~x01&x10&x11 | x00&x01&~x10&x11; 17 | assign ydn = ~y00&~y01&y10&~y11 | ~y00&y01&~y10&~y11 | y00&~y01&y10&y11 | y00&y01&~y10&y11; 18 | assign out = {1'b0, ML, MM, MR, 2'b0, y, 2'b0, x}; 19 | 20 | always @ (posedge clk) begin 21 | x00 <= in[3]; x01 <= x00; x10 <= in[2]; x11 <= x10; 22 | y00 <= in[1]; y01 <= y00; y10 <= in[0]; y11 <= y10; 23 | MR <= ~in[4]; MM <= ~in[5]; ML <= ~in[6]; 24 | x <= xup ? x+1 : xdn ? x-1 : x; 25 | y <= yup ? y+1 : ydn ? y-1 : y; 26 | end 27 | endmodule 28 | 29 | -------------------------------------------------------------------------------- /people.inf.ethz.ch/wirth/ProjectOberon/SourcesVerilog/MouseX.v.html: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | // N.Wirth 10.10.2012 3 | module MouseX( 4 | input clk, 5 | input [6:0] in, 6 | output [27:0] out); 7 | 8 | reg x00, x01, x10, x11, y00, y01, y10, y11; 9 | reg ML, MM, MR; // keys 10 | reg [9:0] x, y; // counters 11 | 12 | wire xup, xdn, yup, ydn; 13 | 14 | assign xup = ~x00&~x01&~x10&x11 | ~x00&x01&x10&x11 | x00&~x01&~x10&~x11 | x00&x01&x10&~x11; 15 | assign yup = ~y00&~y01&~y10&y11 | ~y00&y01&y10&y11 | y00&~y01&~y10&~y11 | y00&y01&y10&~y11; 16 | assign xdn = ~x00&~x01&x10&~x11 | ~x00&x01&~x10&~x11 | x00&~x01&x10&x11 | x00&x01&~x10&x11; 17 | assign ydn = ~y00&~y01&y10&~y11 | ~y00&y01&~y10&~y11 | y00&~y01&y10&y11 | y00&y01&~y10&y11; 18 | assign out = {1'b0, ML, MM, MR, 2'b0, y, 2'b0, x}; 19 | 20 | always @ (posedge clk) begin 21 | x00 <= in[3]; x01 <= x00; x10 <= in[2]; x11 <= x10; 22 | y00 <= in[1]; y01 <= y00; y10 <= in[0]; y11 <= y10; 23 | MR <= ~in[4]; MM <= ~in[5]; ML <= ~in[6]; 24 | x <= xup ? x+1 : xdn ? x-1 : x; 25 | y <= yup ? y+1 : ydn ? y-1 : y; 26 | end 27 | endmodule 28 | 29 | -------------------------------------------------------------------------------- /people.inf.ethz.ch/wirth/ProjectOberon/SourcesVerilog/Multiplier.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps // NW 14.9.2015 2 | 3 | module Multiplier( 4 | input clk, run, u, 5 | output stall, 6 | input [31:0] x, y, 7 | output [63:0] z); 8 | 9 | reg [5:0] S; // state 10 | reg [63:0] P; // product 11 | wire [31:0] w0; 12 | wire [32:0] w1; 13 | 14 | assign stall = run & ~(S == 33); 15 | assign w0 = P[0] ? y : 0; 16 | assign w1 = (S == 32) & u ? {P[63], P[63:32]} - {w0[31], w0} : 17 | {P[63], P[63:32]} + {w0[31], w0}; 18 | assign z = P; 19 | 20 | always @ (posedge(clk)) begin 21 | P <= (S == 0) ? {32'b0, x} : {w1[32:0], P[31:1]}; 22 | S <= run ? S+1 : 0; 23 | end 24 | 25 | endmodule 26 | -------------------------------------------------------------------------------- /people.inf.ethz.ch/wirth/ProjectOberon/SourcesVerilog/Multiplier.v.html: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps // NW 14.9.2015 2 | 3 | module Multiplier( 4 | input clk, run, u, 5 | output stall, 6 | input [31:0] x, y, 7 | output [63:0] z); 8 | 9 | reg [5:0] S; // state 10 | reg [63:0] P; // product 11 | wire [31:0] w0; 12 | wire [32:0] w1; 13 | 14 | assign stall = run & ~(S == 33); 15 | assign w0 = P[0] ? y : 0; 16 | assign w1 = (S == 32) & u ? {P[63], P[63:32]} - {w0[31], w0} : 17 | {P[63], P[63:32]} + {w0[31], w0}; 18 | assign z = P; 19 | 20 | always @ (posedge(clk)) begin 21 | P <= (S == 0) ? {32'b0, x} : {w1[32:0], P[31:1]}; 22 | S <= run ? S+1 : 0; 23 | end 24 | 25 | endmodule 26 | -------------------------------------------------------------------------------- /people.inf.ethz.ch/wirth/ProjectOberon/SourcesVerilog/Multiplier1.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps // NW 29.4.2011 2 | module Multiplier1( 3 | input clk, run, u, 4 | output stall, 5 | input [31:0] x, y, 6 | output [63:0] z); 7 | 8 | reg S; // state 9 | reg [15:0] z0; 10 | reg [47:0] z1, z2; 11 | wire [35:0] p0, p1, p2, p3; 12 | 13 | assign stall = run & ~S; 14 | assign z[15:0] = z0; 15 | assign z[63:16] = z1 + z2; 16 | 17 | MULT18X18 mult0(.P(p0), .A({2'b0, x[15:0]}), .B({2'b0, y[15:0]})); 18 | MULT18X18 mult1(.P(p1), .A({{2{u&x[31]}}, x[31:16]}), .B({2'b0, y[15:0]})); 19 | MULT18X18 mult2(.P(p2), .A({2'b0, x[15:0]}), .B({{2{u&y[31]}}, y[31:16]})); 20 | MULT18X18 mult3(.P(p3), .A({{2{u&x[31]}}, x[31:16]}), .B({{2{u&y[31]}}, y[31:16]})); 21 | 22 | always @(posedge clk) begin 23 | S <= stall; 24 | z0 <= p0[15:0]; 25 | z1 <= {{32'b0}, p0[31:16]} + {{16{u&p1[31]}}, p1[31:0]}; 26 | z2 <= {{16{u&p2[31]}}, p2[31:0]} + {p3[31:0], 16'b0}; 27 | end 28 | endmodule 29 | -------------------------------------------------------------------------------- /people.inf.ethz.ch/wirth/ProjectOberon/SourcesVerilog/Multiplier1.v.html: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps // NW 29.4.2011 2 | module Multiplier1( 3 | input clk, run, u, 4 | output stall, 5 | input [31:0] x, y, 6 | output [63:0] z); 7 | 8 | reg S; // state 9 | reg [15:0] z0; 10 | reg [47:0] z1, z2; 11 | wire [35:0] p0, p1, p2, p3; 12 | 13 | assign stall = run & ~S; 14 | assign z[15:0] = z0; 15 | assign z[63:16] = z1 + z2; 16 | 17 | MULT18X18 mult0(.P(p0), .A({2'b0, x[15:0]}), .B({2'b0, y[15:0]})); 18 | MULT18X18 mult1(.P(p1), .A({{2{u&x[31]}}, x[31:16]}), .B({2'b0, y[15:0]})); 19 | MULT18X18 mult2(.P(p2), .A({2'b0, x[15:0]}), .B({{2{u&y[31]}}, y[31:16]})); 20 | MULT18X18 mult3(.P(p3), .A({{2{u&x[31]}}, x[31:16]}), .B({{2{u&y[31]}}, y[31:16]})); 21 | 22 | always @(posedge clk) begin 23 | S <= stall; 24 | z0 <= p0[15:0]; 25 | z1 <= {{32'b0}, p0[31:16]} + {{16{u&p1[31]}}, p1[31:0]}; 26 | z2 <= {{16{u&p2[31]}}, p2[31:0]} + {p3[31:0], 16'b0}; 27 | end 28 | endmodule 29 | -------------------------------------------------------------------------------- /people.inf.ethz.ch/wirth/ProjectOberon/SourcesVerilog/PROM.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps // 32-bit PROM initialised from hex file PDR 23.12.13 2 | 3 | module PROM (input clk, 4 | input [8:0] adr, 5 | output reg [31:0] data); 6 | 7 | reg [31:0] mem [511: 0]; 8 | initial $readmemh("../prom.mem", mem); 9 | always @(posedge clk) data <= mem[adr]; 10 | 11 | endmodule 12 | 13 | -------------------------------------------------------------------------------- /people.inf.ethz.ch/wirth/ProjectOberon/SourcesVerilog/PROM.v.html: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps // 32-bit PROM initialised from hex file PDR 23.12.13 2 | 3 | module PROM (input clk, 4 | input [8:0] adr, 5 | output reg [31:0] data); 6 | 7 | reg [31:0] mem [511: 0]; 8 | initial $readmemh("../prom.mem", mem); 9 | always @(posedge clk) data <= mem[adr]; 10 | 11 | endmodule 12 | 13 | -------------------------------------------------------------------------------- /people.inf.ethz.ch/wirth/ProjectOberon/SourcesVerilog/PS2.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps // NW 20.10.2012 2 | // PS2 receiver for keyboard, 8 bit data 3 | // clock is 25 MHz; 25000 / 1302 = 19.2 KHz 4 | 5 | module PS2( 6 | input clk, rst, 7 | input done, // "byte has been read" 8 | output rdy, // "byte is available" 9 | output shift, // shift in, tramsmitter 10 | output [7:0] data, 11 | input PS2C, // serial input 12 | input PS2D); 13 | 14 | reg Q0, Q1; // synchronizer and falling edge detector 15 | reg [10:0] shreg; 16 | reg [3:0] inptr, outptr; 17 | reg [7:0] fifo [15:0]; // 16 byte buffer 18 | wire endbit; 19 | 20 | assign endbit = ~shreg[0]; //start bit reached correct pos 21 | assign shift = Q1 & ~Q0; 22 | assign data = fifo[outptr]; 23 | assign rdy = ~(inptr == outptr); 24 | 25 | always @ (posedge clk) begin 26 | Q0 <= PS2C; Q1 <= Q0; 27 | shreg <= (~rst | endbit) ? 11'h7FF : 28 | shift ? {PS2D, shreg[10:1]} : shreg; 29 | outptr <= ~rst ? 0 : rdy & done ? outptr+1 : outptr; 30 | inptr <= ~rst ? 0 : endbit ? inptr+1 : inptr; 31 | if (endbit) fifo[inptr] <= shreg[8:1]; 32 | end 33 | endmodule 34 | -------------------------------------------------------------------------------- /people.inf.ethz.ch/wirth/ProjectOberon/SourcesVerilog/PS2.v.html: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps // NW 20.10.2012 2 | // PS2 receiver for keyboard, 8 bit data 3 | // clock is 25 MHz; 25000 / 1302 = 19.2 KHz 4 | 5 | module PS2( 6 | input clk, rst, 7 | input done, // "byte has been read" 8 | output rdy, // "byte is available" 9 | output shift, // shift in, tramsmitter 10 | output [7:0] data, 11 | input PS2C, // serial input 12 | input PS2D); 13 | 14 | reg Q0, Q1; // synchronizer and falling edge detector 15 | reg [10:0] shreg; 16 | reg [3:0] inptr, outptr; 17 | reg [7:0] fifo [15:0]; // 16 byte buffer 18 | wire endbit; 19 | 20 | assign endbit = ~shreg[0]; //start bit reached correct pos 21 | assign shift = Q1 & ~Q0; 22 | assign data = fifo[outptr]; 23 | assign rdy = ~(inptr == outptr); 24 | 25 | always @ (posedge clk) begin 26 | Q0 <= PS2C; Q1 <= Q0; 27 | shreg <= (~rst | endbit) ? 11'h7FF : 28 | shift ? {PS2D, shreg[10:1]} : shreg; 29 | outptr <= ~rst ? 0 : rdy & done ? outptr+1 : outptr; 30 | inptr <= ~rst ? 0 : endbit ? inptr+1 : inptr; 31 | if (endbit) fifo[inptr] <= shreg[8:1]; 32 | end 33 | endmodule 34 | -------------------------------------------------------------------------------- /people.inf.ethz.ch/wirth/ProjectOberon/SourcesVerilog/RISC5.ucf: -------------------------------------------------------------------------------- 1 | NET "CLK50M" LOC = "T9" ; 2 | 3 | NET "TxD" LOC = "R13"; 4 | NET "RxD" LOC = "T13"; 5 | 6 | NET "btn[0]" LOC = "M13"; 7 | NET "btn[1]" LOC = "M14"; 8 | NET "btn[2]" LOC = "L13"; 9 | NET "btn[3]" LOC = "L14"; 10 | 11 | NET "swi[0]" LOC = "F12"; 12 | NET "swi[1]" LOC = "G12"; 13 | NET "swi[2]" LOC = "H14"; 14 | NET "swi[3]" LOC = "H13"; 15 | NET "swi[4]" LOC = "J14"; 16 | NET "swi[5]" LOC = "J13"; 17 | NET "swi[6]" LOC = "K14"; 18 | NET "swi[7]" LOC = "K13"; 19 | 20 | NET "leds[0]" LOC = "K12"; 21 | NET "leds[1]" LOC = "P14"; 22 | NET "leds[2]" LOC = "L12"; 23 | NET "leds[3]" LOC = "N14"; 24 | NET "leds[4]" LOC = "P13"; 25 | NET "leds[5]" LOC = "N12"; 26 | NET "leds[6]" LOC = "P12"; 27 | NET "leds[7]" LOC = "P11"; 28 | 29 | # SRAM 30 | NET "SRce0" LOC = "P7"; 31 | NET "SRce1" LOC = "N5"; 32 | NET "SRwe" LOC = "G3"; 33 | NET "SRoe" LOC = "K4"; 34 | NET "SRbe[0]" LOC = "P6"; 35 | NET "SRbe[1]" LOC = "T4"; 36 | NET "SRbe[2]" LOC = "P5"; 37 | NET "SRbe[3]" LOC = "R4"; 38 | NET "SRadr[0]" LOC = "L5"; 39 | NET "SRadr[1]" LOC = "N3"; 40 | NET "SRadr[2]" LOC = "M4"; 41 | NET "SRadr[3]" LOC = "M3"; 42 | NET "SRadr[4]" LOC = "L4"; 43 | NET "SRadr[5]" LOC = "G4"; 44 | NET "SRadr[6]" LOC = "F3"; 45 | NET "SRadr[7]" LOC = "F4"; 46 | NET "SRadr[8]" LOC = "E3"; 47 | NET "SRadr[9]" LOC = "E4"; 48 | NET "SRadr[10]" LOC = "G5"; 49 | NET "SRadr[11]" LOC = "H3"; 50 | NET "SRadr[12]" LOC = "H4"; 51 | NET "SRadr[13]" LOC = "J4"; 52 | NET "SRadr[14]" LOC = "J3"; 53 | NET "SRadr[15]" LOC = "K3"; 54 | NET "SRadr[16]" LOC = "K5"; 55 | NET "SRadr[17]" LOC = "L3"; 56 | NET "SRdat[0]" LOC = "N7"; 57 | NET "SRdat[1]" LOC = "T8"; 58 | NET "SRdat[2]" LOC = "R6"; 59 | NET "SRdat[3]" LOC = "T5"; 60 | NET "SRdat[4]" LOC = "R5"; 61 | NET "SRdat[5]" LOC = "C2"; 62 | NET "SRdat[6]" LOC = "C1"; 63 | NET "SRdat[7]" LOC = "B1"; 64 | NET "SRdat[8]" LOC = "D3"; 65 | NET "SRdat[9]" LOC = "P8"; 66 | NET "SRdat[10]" LOC = "F2"; 67 | NET "SRdat[11]" LOC = "H1"; 68 | NET "SRdat[12]" LOC = "J2"; 69 | NET "SRdat[13]" LOC = "L2"; 70 | NET "SRdat[14]" LOC = "P1"; 71 | NET "SRdat[15]" LOC = "R1"; 72 | NET "SRdat[16]" LOC = "P2"; 73 | NET "SRdat[17]" LOC = "N2"; 74 | NET "SRdat[18]" LOC = "M2"; 75 | NET "SRdat[19]" LOC = "K1"; 76 | NET "SRdat[20]" LOC = "J1"; 77 | NET "SRdat[21]" LOC = "G2"; 78 | NET "SRdat[22]" LOC = "E1"; 79 | NET "SRdat[23]" LOC = "D1"; 80 | NET "SRdat[24]" LOC = "D2"; 81 | NET "SRdat[25]" LOC = "E2"; 82 | NET "SRdat[26]" LOC = "G1"; 83 | NET "SRdat[27]" LOC = "F5"; 84 | NET "SRdat[28]" LOC = "C3"; 85 | NET "SRdat[29]" LOC = "K2"; 86 | NET "SRdat[30]" LOC = "M1"; 87 | NET "SRdat[31]" LOC = "N1"; 88 | 89 | # VGA port 90 | NET "Hsync" LOC = "R9"; 91 | NET "Vsync" LOC = "T10"; 92 | NET "RGB[0]" LOC = "R11"; 93 | NET "RGB[1]" LOC = "T12"; 94 | NET "RGB[2]" LOC = "R12"; 95 | 96 | # keyboard 97 | NET "PS2C" LOC = "M16" |PULLUP; 98 | NET "PS2D" LOC = "M15" |PULLUP; 99 | 100 | # PS/2 mouse and SPI (SD-Card and Network) on A2 connector 101 | NET "msclk" LOC = "E6" |PULLUP; # pin 4 102 | NET "msdat" LOC = "C5" |PULLUP; # pin 6 103 | NET "MOSI[0]" LOC = "D6"; # pin 7 104 | NET "MOSI[1]" LOC = "B11"; # pin 29 105 | NET "SCLK[0]" LOC = "D8"; # pin 13 106 | NET "SCLK[1]" LOC = "B12"; # pin 30 107 | NET "SS[0]" LOC = "D5"; # pin 5 108 | NET "SS[1]" LOC = "A12"; # pin 31 109 | NET "MISO[0]" LOC = "B4" |PULLUP; # pin 17 110 | NET "MISO[1]" LOC = "A10" |PULLUP; # pin 28 111 | NET "NEN" LOC = "B13"; # pin 32 112 | 113 | # general-purpose I/O port 114 | NET "gpio[0]" LOC = "C10"; 115 | NET "gpio[1]" LOC = "E10"; 116 | NET "gpio[2]" LOC = "C11"; 117 | NET "gpio[3]" LOC = "D11"; 118 | NET "gpio[4]" LOC = "C12"; 119 | NET "gpio[5]" LOC = "D12"; 120 | NET "gpio[6]" LOC = "E11"; 121 | NET "gpio[7]" LOC = "B16"; 122 | -------------------------------------------------------------------------------- /people.inf.ethz.ch/wirth/ProjectOberon/SourcesVerilog/RISC5.ucf.html: -------------------------------------------------------------------------------- 1 | NET "CLK50M" LOC = "T9" ; 2 | 3 | NET "TxD" LOC = "R13"; 4 | NET "RxD" LOC = "T13"; 5 | 6 | NET "btn[0]" LOC = "M13"; 7 | NET "btn[1]" LOC = "M14"; 8 | NET "btn[2]" LOC = "L13"; 9 | NET "btn[3]" LOC = "L14"; 10 | 11 | NET "swi[0]" LOC = "F12"; 12 | NET "swi[1]" LOC = "G12"; 13 | NET "swi[2]" LOC = "H14"; 14 | NET "swi[3]" LOC = "H13"; 15 | NET "swi[4]" LOC = "J14"; 16 | NET "swi[5]" LOC = "J13"; 17 | NET "swi[6]" LOC = "K14"; 18 | NET "swi[7]" LOC = "K13"; 19 | 20 | NET "leds[0]" LOC = "K12"; 21 | NET "leds[1]" LOC = "P14"; 22 | NET "leds[2]" LOC = "L12"; 23 | NET "leds[3]" LOC = "N14"; 24 | NET "leds[4]" LOC = "P13"; 25 | NET "leds[5]" LOC = "N12"; 26 | NET "leds[6]" LOC = "P12"; 27 | NET "leds[7]" LOC = "P11"; 28 | 29 | # SRAM 30 | NET "SRce0" LOC = "P7"; 31 | NET "SRce1" LOC = "N5"; 32 | NET "SRwe" LOC = "G3"; 33 | NET "SRoe" LOC = "K4"; 34 | NET "SRbe[0]" LOC = "P6"; 35 | NET "SRbe[1]" LOC = "T4"; 36 | NET "SRbe[2]" LOC = "P5"; 37 | NET "SRbe[3]" LOC = "R4"; 38 | NET "SRadr[0]" LOC = "L5"; 39 | NET "SRadr[1]" LOC = "N3"; 40 | NET "SRadr[2]" LOC = "M4"; 41 | NET "SRadr[3]" LOC = "M3"; 42 | NET "SRadr[4]" LOC = "L4"; 43 | NET "SRadr[5]" LOC = "G4"; 44 | NET "SRadr[6]" LOC = "F3"; 45 | NET "SRadr[7]" LOC = "F4"; 46 | NET "SRadr[8]" LOC = "E3"; 47 | NET "SRadr[9]" LOC = "E4"; 48 | NET "SRadr[10]" LOC = "G5"; 49 | NET "SRadr[11]" LOC = "H3"; 50 | NET "SRadr[12]" LOC = "H4"; 51 | NET "SRadr[13]" LOC = "J4"; 52 | NET "SRadr[14]" LOC = "J3"; 53 | NET "SRadr[15]" LOC = "K3"; 54 | NET "SRadr[16]" LOC = "K5"; 55 | NET "SRadr[17]" LOC = "L3"; 56 | NET "SRdat[0]" LOC = "N7"; 57 | NET "SRdat[1]" LOC = "T8"; 58 | NET "SRdat[2]" LOC = "R6"; 59 | NET "SRdat[3]" LOC = "T5"; 60 | NET "SRdat[4]" LOC = "R5"; 61 | NET "SRdat[5]" LOC = "C2"; 62 | NET "SRdat[6]" LOC = "C1"; 63 | NET "SRdat[7]" LOC = "B1"; 64 | NET "SRdat[8]" LOC = "D3"; 65 | NET "SRdat[9]" LOC = "P8"; 66 | NET "SRdat[10]" LOC = "F2"; 67 | NET "SRdat[11]" LOC = "H1"; 68 | NET "SRdat[12]" LOC = "J2"; 69 | NET "SRdat[13]" LOC = "L2"; 70 | NET "SRdat[14]" LOC = "P1"; 71 | NET "SRdat[15]" LOC = "R1"; 72 | NET "SRdat[16]" LOC = "P2"; 73 | NET "SRdat[17]" LOC = "N2"; 74 | NET "SRdat[18]" LOC = "M2"; 75 | NET "SRdat[19]" LOC = "K1"; 76 | NET "SRdat[20]" LOC = "J1"; 77 | NET "SRdat[21]" LOC = "G2"; 78 | NET "SRdat[22]" LOC = "E1"; 79 | NET "SRdat[23]" LOC = "D1"; 80 | NET "SRdat[24]" LOC = "D2"; 81 | NET "SRdat[25]" LOC = "E2"; 82 | NET "SRdat[26]" LOC = "G1"; 83 | NET "SRdat[27]" LOC = "F5"; 84 | NET "SRdat[28]" LOC = "C3"; 85 | NET "SRdat[29]" LOC = "K2"; 86 | NET "SRdat[30]" LOC = "M1"; 87 | NET "SRdat[31]" LOC = "N1"; 88 | 89 | # VGA port 90 | NET "Hsync" LOC = "R9"; 91 | NET "Vsync" LOC = "T10"; 92 | NET "RGB[0]" LOC = "R11"; 93 | NET "RGB[1]" LOC = "T12"; 94 | NET "RGB[2]" LOC = "R12"; 95 | 96 | # keyboard 97 | NET "PS2C" LOC = "M16" |PULLUP; 98 | NET "PS2D" LOC = "M15" |PULLUP; 99 | 100 | # PS/2 mouse and SPI (SD-Card and Network) on A2 connector 101 | NET "msclk" LOC = "E6" |PULLUP; # pin 4 102 | NET "msdat" LOC = "C5" |PULLUP; # pin 6 103 | NET "MOSI[0]" LOC = "D6"; # pin 7 104 | NET "MOSI[1]" LOC = "B11"; # pin 29 105 | NET "SCLK[0]" LOC = "D8"; # pin 13 106 | NET "SCLK[1]" LOC = "B12"; # pin 30 107 | NET "SS[0]" LOC = "D5"; # pin 5 108 | NET "SS[1]" LOC = "A12"; # pin 31 109 | NET "MISO[0]" LOC = "B4" |PULLUP; # pin 17 110 | NET "MISO[1]" LOC = "A10" |PULLUP; # pin 28 111 | NET "NEN" LOC = "B13"; # pin 32 112 | 113 | # general-purpose I/O port 114 | NET "gpio[0]" LOC = "C10"; 115 | NET "gpio[1]" LOC = "E10"; 116 | NET "gpio[2]" LOC = "C11"; 117 | NET "gpio[3]" LOC = "D11"; 118 | NET "gpio[4]" LOC = "C12"; 119 | NET "gpio[5]" LOC = "D12"; 120 | NET "gpio[6]" LOC = "E11"; 121 | NET "gpio[7]" LOC = "B16"; 122 | -------------------------------------------------------------------------------- /people.inf.ethz.ch/wirth/ProjectOberon/SourcesVerilog/RISC5Top.v.html: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps // 14.6.2018 2 | // with SRAM, and gpio 3 | // PS/2 mouse and network 7.1.2014 PDR 4 | 5 | module RISC5Top( 6 | input CLK50M, 7 | input [3:0] btn, 8 | input [7:0] swi, 9 | input RxD, // RS-232 10 | output TxD, 11 | output [7:0] leds, 12 | output SRce0, SRce1, SRwe, SRoe, //SRAM 13 | output [3:0] SRbe, 14 | output [17:0] SRadr, 15 | inout [31:0] SRdat, 16 | input [1:0] MISO, // SPI - SD card & network 17 | output [1:0] SCLK, MOSI, 18 | output [1:0] SS, 19 | output NEN, // network enable 20 | output hsync, vsync, // video controller 21 | output [2:0] RGB, 22 | input PS2C, PS2D, // keyboard 23 | inout msclk, msdat, 24 | inout [7:0] gpio); 25 | 26 | // IO addresses for input / output 27 | // 0 -64 FFFFC0 milliseconds / -- 28 | // 1 -60 FFFFC4 switches / LEDs 29 | // 2 -56 FFFFC8 RS-232 data / RS-232 data (start) 30 | // 3 -52 FFFFCC RS-232 status / RS-232 control 31 | // 4 -48 FFFFD0 SPI data / SPI data (start) 32 | // 5 -44 FFFFD4 SPI status / SPI control 33 | // 6 -40 FFFFD8 PS2 mouse data, keyboard status / -- 34 | // 7 -36 FFFFDC keyboard data / -- 35 | // 8 -32 FFFFE0 general-purpose I/O data 36 | // 9 -28 FFFFE4 general-purpose I/O tri-state control 37 | 38 | reg rst, clk; 39 | wire[23:0] adr; 40 | wire [3:0] iowadr; // word address 41 | wire [31:0] inbus, inbus0; // data to RISC core 42 | wire [31:0] outbus; // data from RISC core 43 | wire [31:0] romout, codebus; // code to RISC core 44 | wire SRbe0, SRbe1; 45 | wire rd, wr, ben, ioenb, vidreq; 46 | 47 | wire [7:0] dataTx, dataRx, dataKbd; 48 | wire rdyRx, doneRx, startTx, rdyTx, rdyKbd, doneKbd; 49 | wire [27:0] dataMs; 50 | reg bitrate; // for RS232 51 | wire limit; // of cnt0 52 | 53 | reg [7:0] Lreg; 54 | reg [15:0] cnt0; 55 | reg [31:0] cnt1; // milliseconds 56 | 57 | wire [31:0] spiRx; 58 | wire spiStart, spiRdy; 59 | reg [3:0] spiCtrl; 60 | wire [17:0] vidadr; 61 | reg [7:0] gpout, gpoc; 62 | wire [7:0] gpin; 63 | 64 | RISC5 riscx(.clk(clk), .rst(rst), .irq(limit), 65 | .rd(rd), .wr(wr), .ben(ben), .stallX(vidreq), 66 | .adr(adr), .codebus(codebus), .inbus(inbus), 67 | .outbus(outbus)); 68 | PROM PM (.adr(adr[10:2]), .data(romout), .clk(~clk)); 69 | RS232R receiver(.clk(clk), .rst(rst), .RxD(RxD), .fsel(bitrate), 70 | .done(doneRx), .data(dataRx), .rdy(rdyRx)); 71 | RS232T transmitter(.clk(clk), .rst(rst), .start(startTx), 72 | .fsel(bitrate), .data(dataTx), .TxD(TxD), .rdy(rdyTx)); 73 | SPI spi(.clk(clk), .rst(rst), .start(spiStart), .dataTx(outbus), 74 | .fast(spiCtrl[2]), .dataRx(spiRx), .rdy(spiRdy), 75 | .SCLK(SCLK[0]), .MOSI(MOSI[0]), .MISO(MISO[0] & MISO[1])); 76 | VID vid(.clk(clk), .req(vidreq), .inv(swi[7]), 77 | .vidadr(vidadr), .viddata(inbus0), .RGB(RGB), 78 | .hsync(hsync), .vsync(vsync)); 79 | PS2 kbd(.clk(clk), .rst(rst), .done(doneKbd), .rdy(rdyKbd), .shift(), 80 | .data(dataKbd), .PS2C(PS2C), .PS2D(PS2D)); 81 | MouseP Ms(.clk(clk), .rst(rst), .msclk(msclk), 82 | .msdat(msdat), .out(dataMs)); 83 | 84 | assign codebus = (adr[23:14] == 10'h3FF) ? romout : inbus0; 85 | assign iowadr = adr[5:2]; 86 | assign ioenb = (adr[23:6] == 18'h3FFFF); 87 | assign inbus = ~ioenb ? inbus0 : 88 | ((iowadr == 0) ? cnt1 : 89 | (iowadr == 1) ? {20'b0, btn, swi} : 90 | (iowadr == 2) ? {24'b0, dataRx} : 91 | (iowadr == 3) ? {30'b0, rdyTx, rdyRx} : 92 | (iowadr == 4) ? spiRx : 93 | (iowadr == 5) ? {31'b0, spiRdy} : 94 | (iowadr == 6) ? {3'b0, rdyKbd, dataMs} : 95 | (iowadr == 7) ? {24'b0, dataKbd} : 96 | (iowadr == 8) ? {24'b0, gpin} : 97 | (iowadr == 9) ? {24'b0, gpoc} : 0); 98 | 99 | assign SRce0 = ~(~ben | ~adr[1]); 100 | assign SRce1 = ~(~ben | adr[1]); 101 | assign SRbe0 = ~(~ben | ~adr[0]); 102 | assign SRbe1 = ~(~ben | adr[0]); 103 | assign SRwe = ~wr | clk; 104 | assign SRoe = wr; 105 | assign SRbe = {SRbe1, SRbe0, SRbe1, SRbe0}; 106 | assign SRadr = vidreq ? vidadr : adr[19:2]; 107 | 108 | genvar i; 109 | generate // tri-state buffer for SRAM 110 | for (i = 0; i < 32; i = i+1) 111 | begin: bufblock 112 | IOBUF SRbuf (.I(outbus[i]), .O(inbus0[i]), .IO(SRdat[i]), .T(~wr)); 113 | end 114 | endgenerate 115 | 116 | generate // tri-state buffer for gpio port 117 | for (i = 0; i < 8; i = i+1) 118 | begin: gpioblock 119 | IOBUF gpiobuf (.I(gpout[i]), .O(gpin[i]), .IO(gpio[i]), .T(~gpoc[i])); 120 | end 121 | endgenerate 122 | 123 | assign dataTx = outbus[7:0]; 124 | assign startTx = wr & ioenb & (iowadr == 2); 125 | assign doneRx = rd & ioenb & (iowadr == 2); 126 | assign limit = (cnt0 == 24999); 127 | assign leds = Lreg; 128 | assign spiStart = wr & ioenb & (iowadr == 4); 129 | assign SS = ~spiCtrl[1:0]; //active low slave select 130 | assign MOSI[1] = MOSI[0], SCLK[1] = SCLK[0], NEN = spiCtrl[3]; 131 | assign doneKbd = rd & ioenb & (iowadr == 7); 132 | 133 | always @(posedge clk) 134 | begin 135 | rst <= ((cnt1[4:0] == 0) & limit) ? ~btn[3] : rst; 136 | Lreg <= ~rst ? 0 : (wr & ioenb & (iowadr == 1)) ? outbus[7:0] : Lreg; 137 | cnt0 <= limit ? 0 : cnt0 + 1; 138 | cnt1 <= cnt1 + limit; 139 | spiCtrl <= ~rst ? 0 : (wr & ioenb & (iowadr == 5)) ? outbus[3:0] : spiCtrl; 140 | bitrate <= ~rst ? 0 : (wr & ioenb & (iowadr == 3)) ? outbus[0] : bitrate; 141 | gpout <= (wr & ioenb & (iowadr == 8)) ? outbus[7:0] : gpout; 142 | gpoc <= ~rst ? 0 : (wr & ioenb & (iowadr == 9)) ? outbus[7:0] : gpoc; 143 | end 144 | 145 | always @ (posedge CLK50M) clk <= ~clk; 146 | endmodule 147 | -------------------------------------------------------------------------------- /people.inf.ethz.ch/wirth/ProjectOberon/SourcesVerilog/RISC5a.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps // 1.9.2018 2 | //no interrupt, no floating-point 3 | 4 | module RISC5( 5 | input clk, rst, irq, stallX, 6 | input [31:0] inbus, codebus, 7 | output [23:0] adr, 8 | output rd, wr, ben, 9 | output [31:0] outbus); 10 | 11 | localparam StartAdr = 22'h3FF800; 12 | 13 | reg [21:0] PC; 14 | reg [31:0] IR; // instruction register 15 | reg N, Z, C, OV; // condition flags 16 | reg [31:0] H; // aux register 17 | reg stallL1; 18 | 19 | wire [21:0] pcmux, nxpc; 20 | wire cond, S; 21 | wire sa, sb, sc; 22 | 23 | wire p, q, u, v; // instruction fields 24 | wire [3:0] op, ira, ira0, irb, irc; 25 | wire [2:0] cc; 26 | wire [15:0] imm; 27 | wire [19:0] off; 28 | wire [21:0] disp; 29 | 30 | wire regwr; 31 | wire stall, stallL0, stallM, stallD; 32 | wire [31:0] A, B, C0, C1, aluRes, regmux, inbus1; 33 | wire [31:0] lshout, rshout; 34 | wire [31:0] quotient, remainder; 35 | wire [63:0] product; 36 | 37 | wire ADD, SUB, MUL, DIV; 38 | wire LDR, STR, BR; 39 | 40 | Registers regs (.clk(clk), .wr(regwr), .rno0(ira0), .rno1(irb), 41 | .rno2(irc), .din(regmux), .dout0(A), .dout1(B), .dout2(C0)); 42 | 43 | Multiplier mulUnit (.clk(clk), .run(MUL), .stall(stallM), 44 | .u(~u), .x(B), .y(C1), .z(product)); 45 | 46 | Divider divUnit (.clk(clk), .run(DIV), .stall(stallD), 47 | .u(~u), .x(B), .y(C1), .quot(quotient), .rem(remainder)); 48 | 49 | LeftShifter LSUnit (.x(B), .y(lshout), .sc(C1[4:0])); 50 | 51 | RightShifter RSUnit(.x(B), .y(rshout), .sc(C1[4:0]), .md(IR[16])); 52 | 53 | assign p = IR[31]; 54 | assign q = IR[30]; 55 | assign u = IR[29]; 56 | assign v = IR[28]; 57 | assign cc = IR[26:24]; 58 | assign ira = IR[27:24]; 59 | assign irb = IR[23:20]; 60 | assign op = IR[19:16]; 61 | assign irc = IR[3:0]; 62 | assign imm = IR[15:0]; // reg instr. 63 | assign off = IR[19:0]; // mem instr. 64 | assign disp = IR[21:0]; // branch instr. 65 | 66 | assign ADD = ~p & (op == 8); 67 | assign SUB = ~p & (op == 9); 68 | assign MUL = ~p & (op == 10); 69 | assign DIV = ~p & (op == 11); 70 | 71 | assign LDR = p & ~q & ~u; 72 | assign STR = p & ~q & u; 73 | assign BR = p & q; 74 | 75 | // Arithmetic-logical unit (ALU) 76 | assign ira0 = BR ? 15 : ira; 77 | assign C1 = q ? {{16{v}}, imm} : C0; 78 | assign adr = stallL0 ? B[23:0] + {{4{off[19]}}, off} : {pcmux, 2'b00}; 79 | assign rd = LDR & ~stallX & stallL0; 80 | assign wr = STR & ~stallX & stallL0; 81 | assign ben = p & ~q & v & ~stallX & stallL0; // byte enable 82 | 83 | assign aluRes = 84 | ~op[3] ? 85 | (~op[2] ? 86 | (~op[1] ? 87 | (~op[0] ? 88 | (q ? // MOV 89 | (~u ? {{16{v}}, imm} : {imm, 16'b0}) : 90 | (~u ? C0 : (~v ? H : {N, Z, C, OV, 20'b0, 8'h54}))) : 91 | lshout) : // LSL 92 | rshout) : // ASR, ROR 93 | (~op[1] ? 94 | (~op[0] ? B & C1 : B & ~C1) : // AND, ANN 95 | (~op[0] ? B | C1 : B ^ C1))) : // IOR. XOR 96 | (~op[2] ? 97 | (~op[1] ? 98 | (~op[0] ? B + C1 + (u&C) : B - C1 - (u&C)) : // ADD, SUB 99 | (~op[0] ? product[31:0] : quotient)) : // MUL, DIV 100 | 0); 101 | 102 | assign regwr = ~p & ~stall | (LDR & ~stallX & ~stallL1) | (BR & cond & v & ~stallX); 103 | assign inbus1 = ~ben ? inbus : 104 | {24'b0, (adr[1] ? (adr[0] ? inbus[31:24] : inbus[23:16]) : 105 | (adr[0] ? inbus[15:8] : inbus[7:0]))}; 106 | assign regmux = LDR ? inbus1 : (BR & v) ? {8'b0, nxpc, 2'b0} : aluRes; 107 | assign outbus = ~ben ? A : 108 | adr[1] ? (adr[0] ? {A[7:0], 24'b0} : {8'b0, A[7:0], 16'b0}) : 109 | (adr[0] ? {16'b0, A[7:0], 8'b0} : {24'b0, A[7:0]}); 110 | 111 | // Control unit CU 112 | assign S = N ^ OV; 113 | assign nxpc = PC + 1; 114 | assign cond = IR[27] ^ 115 | ((cc == 0) & N | // MI, PL 116 | (cc == 1) & Z | // EQ, NE 117 | (cc == 2) & C | // CS, CC 118 | (cc == 3) & OV | // VS, VC 119 | (cc == 4) & (C|Z) | // LS, HI 120 | (cc == 5) & S | // LT, GE 121 | (cc == 6) & (S|Z) | // LE, GT 122 | (cc == 7)); // T, F 123 | 124 | assign pcmux = ~rst | stall ? 125 | (~rst ? StartAdr : PC) : 126 | (BR & cond) ? (u ? nxpc + disp : C0[23:2]) : nxpc; 127 | 128 | assign sa = aluRes[31]; 129 | assign sb = B[31]; 130 | assign sc = C1[31]; 131 | 132 | assign stall = stallL0 | stallM | stallD | stallX; 133 | assign stallL0 = (LDR|STR) & ~stallL1; 134 | 135 | always @ (posedge clk) begin 136 | PC <= pcmux; 137 | IR <= stall ? IR : codebus; 138 | stallL1 <= stallX ? stallL1 : stallL0; 139 | N <= regwr ? regmux[31] : N; 140 | Z <= regwr ? (regmux == 0) : Z; 141 | C <= ADD ? (~sb&sc&~sa) | (sb&sc&sa) | (sb&~sa) : 142 | SUB ? (~sb&sc&~sa) | (sb&sc&sa) | (~sb&sa) : C; 143 | OV <= ADD ? (sa&~sb&~sc) | (~sa&sb&sc): 144 | SUB ? (sa&~sb&sc) | (~sa&sb&~sc) : OV; 145 | H <= MUL ? product[63:32] : DIV ? remainder : H; 146 | end 147 | endmodule 148 | -------------------------------------------------------------------------------- /people.inf.ethz.ch/wirth/ProjectOberon/SourcesVerilog/RISC5a.v.html: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps // 1.9.2018 2 | //no interrupt, no floating-point 3 | 4 | module RISC5( 5 | input clk, rst, irq, stallX, 6 | input [31:0] inbus, codebus, 7 | output [23:0] adr, 8 | output rd, wr, ben, 9 | output [31:0] outbus); 10 | 11 | localparam StartAdr = 22'h3FF800; 12 | 13 | reg [21:0] PC; 14 | reg [31:0] IR; // instruction register 15 | reg N, Z, C, OV; // condition flags 16 | reg [31:0] H; // aux register 17 | reg stallL1; 18 | 19 | wire [21:0] pcmux, nxpc; 20 | wire cond, S; 21 | wire sa, sb, sc; 22 | 23 | wire p, q, u, v; // instruction fields 24 | wire [3:0] op, ira, ira0, irb, irc; 25 | wire [2:0] cc; 26 | wire [15:0] imm; 27 | wire [19:0] off; 28 | wire [21:0] disp; 29 | 30 | wire regwr; 31 | wire stall, stallL0, stallM, stallD; 32 | wire [31:0] A, B, C0, C1, aluRes, regmux, inbus1; 33 | wire [31:0] lshout, rshout; 34 | wire [31:0] quotient, remainder; 35 | wire [63:0] product; 36 | 37 | wire ADD, SUB, MUL, DIV; 38 | wire LDR, STR, BR; 39 | 40 | Registers regs (.clk(clk), .wr(regwr), .rno0(ira0), .rno1(irb), 41 | .rno2(irc), .din(regmux), .dout0(A), .dout1(B), .dout2(C0)); 42 | 43 | Multiplier mulUnit (.clk(clk), .run(MUL), .stall(stallM), 44 | .u(~u), .x(B), .y(C1), .z(product)); 45 | 46 | Divider divUnit (.clk(clk), .run(DIV), .stall(stallD), 47 | .u(~u), .x(B), .y(C1), .quot(quotient), .rem(remainder)); 48 | 49 | LeftShifter LSUnit (.x(B), .y(lshout), .sc(C1[4:0])); 50 | 51 | RightShifter RSUnit(.x(B), .y(rshout), .sc(C1[4:0]), .md(IR[16])); 52 | 53 | assign p = IR[31]; 54 | assign q = IR[30]; 55 | assign u = IR[29]; 56 | assign v = IR[28]; 57 | assign cc = IR[26:24]; 58 | assign ira = IR[27:24]; 59 | assign irb = IR[23:20]; 60 | assign op = IR[19:16]; 61 | assign irc = IR[3:0]; 62 | assign imm = IR[15:0]; // reg instr. 63 | assign off = IR[19:0]; // mem instr. 64 | assign disp = IR[21:0]; // branch instr. 65 | 66 | assign ADD = ~p & (op == 8); 67 | assign SUB = ~p & (op == 9); 68 | assign MUL = ~p & (op == 10); 69 | assign DIV = ~p & (op == 11); 70 | 71 | assign LDR = p & ~q & ~u; 72 | assign STR = p & ~q & u; 73 | assign BR = p & q; 74 | 75 | // Arithmetic-logical unit (ALU) 76 | assign ira0 = BR ? 15 : ira; 77 | assign C1 = q ? {{16{v}}, imm} : C0; 78 | assign adr = stallL0 ? B[23:0] + {{4{off[19]}}, off} : {pcmux, 2'b00}; 79 | assign rd = LDR & ~stallX & stallL0; 80 | assign wr = STR & ~stallX & stallL0; 81 | assign ben = p & ~q & v & ~stallX & stallL0; // byte enable 82 | 83 | assign aluRes = 84 | ~op[3] ? 85 | (~op[2] ? 86 | (~op[1] ? 87 | (~op[0] ? 88 | (q ? // MOV 89 | (~u ? {{16{v}}, imm} : {imm, 16'b0}) : 90 | (~u ? C0 : (~v ? H : {N, Z, C, OV, 20'b0, 8'h54}))) : 91 | lshout) : // LSL 92 | rshout) : // ASR, ROR 93 | (~op[1] ? 94 | (~op[0] ? B & C1 : B & ~C1) : // AND, ANN 95 | (~op[0] ? B | C1 : B ^ C1))) : // IOR. XOR 96 | (~op[2] ? 97 | (~op[1] ? 98 | (~op[0] ? B + C1 + (u&C) : B - C1 - (u&C)) : // ADD, SUB 99 | (~op[0] ? product[31:0] : quotient)) : // MUL, DIV 100 | 0); 101 | 102 | assign regwr = ~p & ~stall | (LDR & ~stallX & ~stallL1) | (BR & cond & v & ~stallX); 103 | assign inbus1 = ~ben ? inbus : 104 | {24'b0, (adr[1] ? (adr[0] ? inbus[31:24] : inbus[23:16]) : 105 | (adr[0] ? inbus[15:8] : inbus[7:0]))}; 106 | assign regmux = LDR ? inbus1 : (BR & v) ? {8'b0, nxpc, 2'b0} : aluRes; 107 | assign outbus = ~ben ? A : 108 | adr[1] ? (adr[0] ? {A[7:0], 24'b0} : {8'b0, A[7:0], 16'b0}) : 109 | (adr[0] ? {16'b0, A[7:0], 8'b0} : {24'b0, A[7:0]}); 110 | 111 | // Control unit CU 112 | assign S = N ^ OV; 113 | assign nxpc = PC + 1; 114 | assign cond = IR[27] ^ 115 | ((cc == 0) & N | // MI, PL 116 | (cc == 1) & Z | // EQ, NE 117 | (cc == 2) & C | // CS, CC 118 | (cc == 3) & OV | // VS, VC 119 | (cc == 4) & (C|Z) | // LS, HI 120 | (cc == 5) & S | // LT, GE 121 | (cc == 6) & (S|Z) | // LE, GT 122 | (cc == 7)); // T, F 123 | 124 | assign pcmux = ~rst | stall ? 125 | (~rst ? StartAdr : PC) : 126 | (BR & cond) ? (u ? nxpc + disp : C0[23:2]) : nxpc; 127 | 128 | assign sa = aluRes[31]; 129 | assign sb = B[31]; 130 | assign sc = C1[31]; 131 | 132 | assign stall = stallL0 | stallM | stallD | stallX; 133 | assign stallL0 = (LDR|STR) & ~stallL1; 134 | 135 | always @ (posedge clk) begin 136 | PC <= pcmux; 137 | IR <= stall ? IR : codebus; 138 | stallL1 <= stallX ? stallL1 : stallL0; 139 | N <= regwr ? regmux[31] : N; 140 | Z <= regwr ? (regmux == 0) : Z; 141 | C <= ADD ? (~sb&sc&~sa) | (sb&sc&sa) | (sb&~sa) : 142 | SUB ? (~sb&sc&~sa) | (sb&sc&sa) | (~sb&sa) : C; 143 | OV <= ADD ? (sa&~sb&~sc) | (~sa&sb&sc): 144 | SUB ? (sa&~sb&sc) | (~sa&sb&~sc) : OV; 145 | H <= MUL ? product[63:32] : DIV ? remainder : H; 146 | end 147 | endmodule 148 | -------------------------------------------------------------------------------- /people.inf.ethz.ch/wirth/ProjectOberon/SourcesVerilog/RS232R.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps // NW 4.5.09 / 15.11.10 2 | 3 | // RS232 receiver for 19200 or 115200 bps, 8 bit data 4 | // clock is 25 MHz 5 | 6 | module RS232R( 7 | input clk, rst, 8 | input RxD, 9 | input fsel, 10 | input done, // "byte has been read" 11 | output rdy, 12 | output [7:0] data); 13 | 14 | wire endtick, midtick, endbit; 15 | wire [11:0] limit; 16 | reg run, stat; 17 | reg Q0, Q1; // synchronizer and edge detector 18 | reg [11:0] tick; 19 | reg [3:0] bitcnt; 20 | reg [7:0] shreg; 21 | 22 | assign limit = fsel ? 217 : 1302; 23 | assign endtick = tick == limit; 24 | assign midtick = tick == {1'b0, limit[11:1]}; // limit/2 25 | assign endbit = bitcnt == 8; 26 | assign data = shreg; 27 | assign rdy = stat; 28 | 29 | always @ (posedge clk) begin 30 | Q0 <= RxD; Q1 <= Q0; 31 | run <= (Q1 & ~Q0) | ~(~rst | endtick & endbit) & run; 32 | tick <= (run & ~endtick) ? tick+1 : 0; 33 | bitcnt <= (endtick & ~endbit) ? bitcnt + 1 : 34 | (endtick & endbit) ? 0 : bitcnt; 35 | shreg <= midtick ? {Q1, shreg[7:1]} : shreg; 36 | stat <= (endtick & endbit) | ~(~rst | done) & stat; 37 | end 38 | endmodule 39 | -------------------------------------------------------------------------------- /people.inf.ethz.ch/wirth/ProjectOberon/SourcesVerilog/RS232R.v.html: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps // NW 4.5.09 / 15.11.10 2 | 3 | // RS232 receiver for 19200 or 115200 bps, 8 bit data 4 | // clock is 25 MHz 5 | 6 | module RS232R( 7 | input clk, rst, 8 | input RxD, 9 | input fsel, 10 | input done, // "byte has been read" 11 | output rdy, 12 | output [7:0] data); 13 | 14 | wire endtick, midtick, endbit; 15 | wire [11:0] limit; 16 | reg run, stat; 17 | reg Q0, Q1; // synchronizer and edge detector 18 | reg [11:0] tick; 19 | reg [3:0] bitcnt; 20 | reg [7:0] shreg; 21 | 22 | assign limit = fsel ? 217 : 1302; 23 | assign endtick = tick == limit; 24 | assign midtick = tick == {1'b0, limit[11:1]}; // limit/2 25 | assign endbit = bitcnt == 8; 26 | assign data = shreg; 27 | assign rdy = stat; 28 | 29 | always @ (posedge clk) begin 30 | Q0 <= RxD; Q1 <= Q0; 31 | run <= (Q1 & ~Q0) | ~(~rst | endtick & endbit) & run; 32 | tick <= (run & ~endtick) ? tick+1 : 0; 33 | bitcnt <= (endtick & ~endbit) ? bitcnt + 1 : 34 | (endtick & endbit) ? 0 : bitcnt; 35 | shreg <= midtick ? {Q1, shreg[7:1]} : shreg; 36 | stat <= (endtick & endbit) | ~(~rst | done) & stat; 37 | end 38 | endmodule 39 | -------------------------------------------------------------------------------- /people.inf.ethz.ch/wirth/ProjectOberon/SourcesVerilog/RS232T.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps // NW 4.5.09 / 15.8.10 / 15.11.10 2 | 3 | // RS232 transmitter for 19200 bps, 8 bit data 4 | // clock is 25 MHz; 25000 / 1302 = 19.2 KHz 5 | 6 | module RS232T( 7 | input clk, rst, 8 | input start, // request to accept and send a byte 9 | input fsel, // frequency selection 10 | input [7:0] data, 11 | output rdy, 12 | output TxD); 13 | 14 | wire endtick, endbit; 15 | wire [11:0] limit; 16 | reg run; 17 | reg [11:0] tick; 18 | reg [3:0] bitcnt; 19 | reg [8:0] shreg; 20 | 21 | assign limit = fsel ? 217 : 1302; 22 | assign endtick = tick == limit; 23 | assign endbit = bitcnt == 9; 24 | assign rdy = ~run; 25 | assign TxD = shreg[0]; 26 | 27 | always @ (posedge clk) begin 28 | run <= (~rst | endtick & endbit) ? 0 : start ? 1 : run; 29 | tick <= (run & ~endtick) ? tick + 1 : 0; 30 | bitcnt <= (endtick & ~endbit) ? bitcnt + 1 : 31 | (endtick & endbit) ? 0 : bitcnt; 32 | shreg <= (~rst) ? 1 : start ? {data, 1'b0} : 33 | endtick ? {1'b1, shreg[8:1]} : shreg; 34 | end 35 | endmodule 36 | -------------------------------------------------------------------------------- /people.inf.ethz.ch/wirth/ProjectOberon/SourcesVerilog/RS232T.v.html: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps // NW 4.5.09 / 15.8.10 / 15.11.10 2 | 3 | // RS232 transmitter for 19200 bps, 8 bit data 4 | // clock is 25 MHz; 25000 / 1302 = 19.2 KHz 5 | 6 | module RS232T( 7 | input clk, rst, 8 | input start, // request to accept and send a byte 9 | input fsel, // frequency selection 10 | input [7:0] data, 11 | output rdy, 12 | output TxD); 13 | 14 | wire endtick, endbit; 15 | wire [11:0] limit; 16 | reg run; 17 | reg [11:0] tick; 18 | reg [3:0] bitcnt; 19 | reg [8:0] shreg; 20 | 21 | assign limit = fsel ? 217 : 1302; 22 | assign endtick = tick == limit; 23 | assign endbit = bitcnt == 9; 24 | assign rdy = ~run; 25 | assign TxD = shreg[0]; 26 | 27 | always @ (posedge clk) begin 28 | run <= (~rst | endtick & endbit) ? 0 : start ? 1 : run; 29 | tick <= (run & ~endtick) ? tick + 1 : 0; 30 | bitcnt <= (endtick & ~endbit) ? bitcnt + 1 : 31 | (endtick & endbit) ? 0 : bitcnt; 32 | shreg <= (~rst) ? 1 : start ? {data, 1'b0} : 33 | endtick ? {1'b1, shreg[8:1]} : shreg; 34 | end 35 | endmodule 36 | -------------------------------------------------------------------------------- /people.inf.ethz.ch/wirth/ProjectOberon/SourcesVerilog/Registers.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps // 1.2.2018 2 | // register file, triple-port 3 | 4 | module Registers( 5 | input clk,wr, 6 | input [3:0] rno0, rno1, rno2, 7 | input [31:0] din, 8 | output [31:0] dout0, dout1, dout2); 9 | genvar i; 10 | generate //triple port register file, duplicated LUT array 11 | for (i = 0; i < 32; i = i+1) 12 | begin: rf32 13 | RAM16X1D # (.INIT(16'h0000)) 14 | rfb( 15 | .DPO(dout1[i]), // data out 16 | .SPO(dout0[i]), 17 | .A0(rno0[0]), // R/W address, controls D and SPO 18 | .A1(rno0[1]), 19 | .A2(rno0[2]), 20 | .A3(rno0[3]), 21 | .D(din[i]), // data in 22 | .DPRA0(rno1[0]), // read-only adr, controls DPO 23 | .DPRA1(rno1[1]), 24 | .DPRA2(rno1[2]), 25 | .DPRA3(rno1[3]), 26 | .WCLK(clk), 27 | .WE(wr)); 28 | 29 | RAM16X1D # (.INIT(16'h0000)) 30 | rfc( 31 | .DPO(dout2[i]), // data out 32 | .SPO(), 33 | .A0(rno0[0]), // R/W address, controls D and SPO 34 | .A1(rno0[1]), 35 | .A2(rno0[2]), 36 | .A3(rno0[3]), 37 | .D(din[i]), // data in 38 | .DPRA0(rno2[0]), // read-only adr, controls DPO 39 | .DPRA1(rno2[1]), 40 | .DPRA2(rno2[2]), 41 | .DPRA3(rno2[3]), 42 | .WCLK(clk), 43 | .WE(wr)); 44 | end 45 | endgenerate 46 | endmodule 47 | -------------------------------------------------------------------------------- /people.inf.ethz.ch/wirth/ProjectOberon/SourcesVerilog/Registers.v.html: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps // 1.2.2018 2 | // register file, triple-port 3 | 4 | module Registers( 5 | input clk,wr, 6 | input [3:0] rno0, rno1, rno2, 7 | input [31:0] din, 8 | output [31:0] dout0, dout1, dout2); 9 | genvar i; 10 | generate //triple port register file, duplicated LUT array 11 | for (i = 0; i < 32; i = i+1) 12 | begin: rf32 13 | RAM16X1D # (.INIT(16'h0000)) 14 | rfb( 15 | .DPO(dout1[i]), // data out 16 | .SPO(dout0[i]), 17 | .A0(rno0[0]), // R/W address, controls D and SPO 18 | .A1(rno0[1]), 19 | .A2(rno0[2]), 20 | .A3(rno0[3]), 21 | .D(din[i]), // data in 22 | .DPRA0(rno1[0]), // read-only adr, controls DPO 23 | .DPRA1(rno1[1]), 24 | .DPRA2(rno1[2]), 25 | .DPRA3(rno1[3]), 26 | .WCLK(clk), 27 | .WE(wr)); 28 | 29 | RAM16X1D # (.INIT(16'h0000)) 30 | rfc( 31 | .DPO(dout2[i]), // data out 32 | .SPO(), 33 | .A0(rno0[0]), // R/W address, controls D and SPO 34 | .A1(rno0[1]), 35 | .A2(rno0[2]), 36 | .A3(rno0[3]), 37 | .D(din[i]), // data in 38 | .DPRA0(rno2[0]), // read-only adr, controls DPO 39 | .DPRA1(rno2[1]), 40 | .DPRA2(rno2[2]), 41 | .DPRA3(rno2[3]), 42 | .WCLK(clk), 43 | .WE(wr)); 44 | end 45 | endgenerate 46 | endmodule 47 | -------------------------------------------------------------------------------- /people.inf.ethz.ch/wirth/ProjectOberon/SourcesVerilog/RightShifter.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps // NW 9.11.2016 2 | 3 | module RightShifter( 4 | input [31:0] x, 5 | input [4:0] sc, 6 | input md, 7 | output [31:0] y); 8 | 9 | // shifter for ASR and ROR 10 | wire [1:0] sc0, sc1; 11 | wire [31:0] s1, s2; 12 | 13 | assign sc0 = sc[1:0]; 14 | assign sc1 = sc[3:2]; 15 | 16 | assign s1 = (sc0 == 3) ? {(md ? x[2:0] : {3{x[31]}}), x[31:3]} : 17 | (sc0 == 2) ? {(md ? x[1:0] : {2{x[31]}}), x[31:2]} : 18 | (sc0 == 1) ? {(md ? x[0] : x[31]), x[31:1]} : x; 19 | 20 | assign s2 = (sc1 == 3) ? {(md ? s1[11:0] : {12{s1[31]}}), s1[31:12]} : 21 | (sc1 == 2) ? {(md ? s1[7:0] : {8{s1[31]}}), s1[31:8]} : 22 | (sc1 == 1) ? {(md ? s1[3:0] : {4{s1[31]}}), s1[31:4]} : s1; 23 | assign y = sc[4] ? {(md ? s2[15:0] : {16{s2[31]}}), s2[31:16]} : s2; 24 | endmodule -------------------------------------------------------------------------------- /people.inf.ethz.ch/wirth/ProjectOberon/SourcesVerilog/RightShifter.v.html: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps // NW 9.11.2016 2 | 3 | module RightShifter( 4 | input [31:0] x, 5 | input [4:0] sc, 6 | input md, 7 | output [31:0] y); 8 | 9 | // shifter for ASR and ROR 10 | wire [1:0] sc0, sc1; 11 | wire [31:0] s1, s2; 12 | 13 | assign sc0 = sc[1:0]; 14 | assign sc1 = sc[3:2]; 15 | 16 | assign s1 = (sc0 == 3) ? {(md ? x[2:0] : {3{x[31]}}), x[31:3]} : 17 | (sc0 == 2) ? {(md ? x[1:0] : {2{x[31]}}), x[31:2]} : 18 | (sc0 == 1) ? {(md ? x[0] : x[31]), x[31:1]} : x; 19 | 20 | assign s2 = (sc1 == 3) ? {(md ? s1[11:0] : {12{s1[31]}}), s1[31:12]} : 21 | (sc1 == 2) ? {(md ? s1[7:0] : {8{s1[31]}}), s1[31:8]} : 22 | (sc1 == 1) ? {(md ? s1[3:0] : {4{s1[31]}}), s1[31:4]} : s1; 23 | assign y = sc[4] ? {(md ? s2[15:0] : {16{s2[31]}}), s2[31:16]} : s2; 24 | endmodule -------------------------------------------------------------------------------- /people.inf.ethz.ch/wirth/ProjectOberon/SourcesVerilog/SPI.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | // Motorola Serial Peripheral Interface (SPI) PDR 23.3.12 / 16.10.13 4 | // transmitter / receiver of words (fast, clk/3) or bytes (slow, clk/64) 5 | // e.g 8.33MHz or ~400KHz respectively at 25MHz (slow needed for SD-card init) 6 | // note: bytes are always MSbit first; but if fast, words are LSByte first 7 | 8 | module SPI( 9 | input clk, rst, 10 | input start, fast, 11 | input [31:0] dataTx, 12 | output [31:0] dataRx, 13 | output reg rdy, 14 | input MISO, output MOSI, output SCLK); 15 | 16 | wire endbit, endtick; 17 | reg [31:0] shreg; 18 | reg [5:0] tick; 19 | reg [4:0] bitcnt; 20 | 21 | assign endtick = fast ? (tick == 2) : (tick == 63); //25MHz clk 22 | assign endbit = fast ? (bitcnt == 31) : (bitcnt == 7); 23 | assign dataRx = fast ? shreg : {24'b0, shreg[7:0]}; 24 | assign MOSI = (~rst | rdy) ? 1 : shreg[7]; 25 | assign SCLK = (~rst | rdy) ? 0 : fast ? endtick : tick[5]; 26 | 27 | always @ (posedge clk) begin 28 | tick <= (~rst | rdy | endtick) ? 0 : tick + 1; 29 | rdy <= (~rst | endtick & endbit) ? 1 : start ? 0 : rdy; 30 | bitcnt <= (~rst | start) ? 0 : (endtick & ~endbit) ? bitcnt + 1 : bitcnt; 31 | shreg <= ~rst ? -1 : start ? dataTx : endtick ? 32 | {shreg[30:24], MISO, shreg[22:16], shreg[31], shreg[14:8], 33 | shreg[23], shreg[6:0], (fast ? shreg[15] : MISO)} : shreg; 34 | end 35 | 36 | endmodule -------------------------------------------------------------------------------- /people.inf.ethz.ch/wirth/ProjectOberon/SourcesVerilog/SPI.v.html: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | // Motorola Serial Peripheral Interface (SPI) PDR 23.3.12 / 16.10.13 4 | // transmitter / receiver of words (fast, clk/3) or bytes (slow, clk/64) 5 | // e.g 8.33MHz or ~400KHz respectively at 25MHz (slow needed for SD-card init) 6 | // note: bytes are always MSbit first; but if fast, words are LSByte first 7 | 8 | module SPI( 9 | input clk, rst, 10 | input start, fast, 11 | input [31:0] dataTx, 12 | output [31:0] dataRx, 13 | output reg rdy, 14 | input MISO, output MOSI, output SCLK); 15 | 16 | wire endbit, endtick; 17 | reg [31:0] shreg; 18 | reg [5:0] tick; 19 | reg [4:0] bitcnt; 20 | 21 | assign endtick = fast ? (tick == 2) : (tick == 63); //25MHz clk 22 | assign endbit = fast ? (bitcnt == 31) : (bitcnt == 7); 23 | assign dataRx = fast ? shreg : {24'b0, shreg[7:0]}; 24 | assign MOSI = (~rst | rdy) ? 1 : shreg[7]; 25 | assign SCLK = (~rst | rdy) ? 0 : fast ? endtick : tick[5]; 26 | 27 | always @ (posedge clk) begin 28 | tick <= (~rst | rdy | endtick) ? 0 : tick + 1; 29 | rdy <= (~rst | endtick & endbit) ? 1 : start ? 0 : rdy; 30 | bitcnt <= (~rst | start) ? 0 : (endtick & ~endbit) ? bitcnt + 1 : bitcnt; 31 | shreg <= ~rst ? -1 : start ? dataTx : endtick ? 32 | {shreg[30:24], MISO, shreg[22:16], shreg[31], shreg[14:8], 33 | shreg[23], shreg[6:0], (fast ? shreg[15] : MISO)} : shreg; 34 | end 35 | 36 | endmodule -------------------------------------------------------------------------------- /people.inf.ethz.ch/wirth/ProjectOberon/SourcesVerilog/VID.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | // 1024x768 display controller NW/PR 24.1.2014 3 | 4 | module VID( 5 | input clk, inv, 6 | input [31:0] viddata, 7 | output reg req, // SRAM read request 8 | output [17:0] vidadr, 9 | output hsync, vsync, // to display 10 | output [2:0] RGB); 11 | 12 | localparam Org = 18'b1101_1111_1111_0000_00; // DFF00: adr of vcnt=1023 13 | reg [10:0] hcnt; 14 | reg [9:0] vcnt; 15 | reg [4:0] hword; // from hcnt, but latched in the clk domain 16 | reg [31:0] vidbuf, pixbuf; 17 | reg hblank; 18 | wire pclk, hend, vend, vblank, xfer, vid; 19 | 20 | assign hend = (hcnt == 1343), vend = (vcnt == 801); 21 | assign vblank = (vcnt[8] & vcnt[9]); // (vcnt >= 768) 22 | assign hsync = ~((hcnt >= 1080+6) & (hcnt < 1184+6)); // -ve polarity 23 | assign vsync = (vcnt >= 771) & (vcnt < 776); // +ve polarity 24 | assign xfer = (hcnt[4:0] == 6); // data delay > hcnt cycle + req cycle 25 | assign vid = (pixbuf[0] ^ inv) & ~hblank & ~vblank; 26 | assign RGB = {vid, vid, vid}; 27 | assign vidadr = Org + {3'b0, ~vcnt, hword}; 28 | 29 | always @(posedge pclk) begin // pixel clock domain 30 | hcnt <= hend ? 0 : hcnt+1; 31 | vcnt <= hend ? (vend ? 0 : (vcnt+1)) : vcnt; 32 | hblank <= xfer ? hcnt[10] : hblank; // hcnt >= 1024 33 | pixbuf <= xfer ? vidbuf : {1'b0, pixbuf[31:1]}; 34 | end 35 | 36 | always @(posedge clk) begin // CPU (SRAM) clock domain 37 | hword <= hcnt[9:5]; 38 | req <= ~vblank & ~hcnt[10] & (hcnt[5] ^ hword[0]); // i.e. adr changed 39 | vidbuf <= req ? viddata : vidbuf; 40 | end 41 | 42 | // pixel clock generation 43 | (* LOC = "DCM_X1Y1" *) DCM #(.CLKFX_MULTIPLY(3), .CLK_FEEDBACK("NONE")) 44 | dcm(.CLKIN(clk), .CLKFX(pclk)); 45 | 46 | endmodule 47 | -------------------------------------------------------------------------------- /people.inf.ethz.ch/wirth/ProjectOberon/UsingOberon.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Spirit-of-Oberon/wirth-personal/874a6024c1b6b1eff0208225e1004bc1aa62fb79/people.inf.ethz.ch/wirth/ProjectOberon/UsingOberon.pdf -------------------------------------------------------------------------------- /people.inf.ethz.ch/wirth/ProjectOberon/index.html: -------------------------------------------------------------------------------- 1 | 2 |
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105 | Back to my home page. 106 | 107 | 108 | -------------------------------------------------------------------------------- /people.inf.ethz.ch/wirth/ProjectOberon/license.txt: -------------------------------------------------------------------------------- 1 | Project Oberon, Revised Edition 2013 2 | 3 | Book copyright (C)2013 Niklaus Wirth and Juerg Gutknecht; 4 | software copyright (C)2013 Niklaus Wirth (NW), Juerg Gutknecht (JG), Paul 5 | Reed (PR/PDR). 6 | 7 | Permission to use, copy, modify, and/or distribute this software and its 8 | accompanying documentation (the "Software") for any purpose with or 9 | without fee is hereby granted, provided that the above copyright notice 10 | and this permission notice appear in all copies. 11 | 12 | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHORS DISCLAIM ALL WARRANTIES 13 | WITH REGARD TO THE SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF 14 | MERCHANTABILITY, FITNESS AND NONINFRINGEMENT. IN NO EVENT SHALL THE 15 | AUTHORS BE LIABLE FOR ANY CLAIM, SPECIAL, DIRECT, INDIRECT, OR 16 | CONSEQUENTIAL DAMAGES OR ANY DAMAGES OR LIABILITY WHATSOEVER, WHETHER IN 17 | AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 18 | CONNECTION WITH THE DEALINGS IN OR USE OR PERFORMANCE OF THE SOFTWARE. 19 | -------------------------------------------------------------------------------- /people.inf.ethz.ch/wirth/ProjectOberon1992.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Spirit-of-Oberon/wirth-personal/874a6024c1b6b1eff0208225e1004bc1aa62fb79/people.inf.ethz.ch/wirth/ProjectOberon1992.pdf -------------------------------------------------------------------------------- /people.inf.ethz.ch/wirth/SelectedArticles.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Spirit-of-Oberon/wirth-personal/874a6024c1b6b1eff0208225e1004bc1aa62fb79/people.inf.ethz.ch/wirth/SelectedArticles.pdf -------------------------------------------------------------------------------- /people.inf.ethz.ch/wirth/SelectedHonours.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Spirit-of-Oberon/wirth-personal/874a6024c1b6b1eff0208225e1004bc1aa62fb79/people.inf.ethz.ch/wirth/SelectedHonours.pdf -------------------------------------------------------------------------------- /people.inf.ethz.ch/wirth/news.txt: -------------------------------------------------------------------------------- 1 | 6.3.2020 - ORB.Mod.txt updated. See ORB.ThisModule. Error in Import with alias corrected. 2 | 8.2.2020 - ORP.Mod.txt correction suggested by A. Pirklbauer in ORP.Module (ORP.Import) 3 | 26.1.2020 change aborted 4 | 31.5.2019 - ORP.Mod.txt, ORG.Mod.txt updated in TypeTest 5 | 15.5.2019 - Floating-point rounding corrected 6 | update Texts.WriteReal and ORS.Number 7 | 20190301 - ORB.Mod.txt updated, see InType (variable last) 8 | 20290118 - Fonts.Mod.txt cleanup and correction in Fonts.Load 9 | 20190117 - Oberon System updates: 10 | Dinsplay.Mod.txt CopyPattern, now pattern width w <= 32 (not < 32) 11 | Modules.Mod.txt at end of Load: res >= 3 (not res = 3) 12 | Texts.Mod.txt: IF T.notify # NIL THEN T.notify ... in 13 | Insert, Delete and ChangeLooks 14 | 20190109 - Syntax change in Lola: Use "=" in (const and type) declarations; 15 | use ":=" in statements (like in Oberon) 16 | Update LSC.Mod.txt, RISC5.Lola.txt, RISC5a.Lola.txt, RISC5Top.Lola.txt, MouseP.Lola.txt, VID.Lola.txt 17 | 20190108 - Update Texts.Mod.txt (see Insert, Delete, ChangeLooks) and 18 | Modules.Mod.txt (Load) 19 | 20181201 - Update Texts.Mod.txt (Read), and ORB.Mod.txt (outType) 20 | 20180918 - Update Oberon compiler 21 | Compiler now consumes considerably less heap space -- ORS.Mod.txt 22 | 20180912 - Update Oberon compiler 23 | Type tests other than for pointers and record parameters detected as illegal. 24 | see ORP.TypeTest 25 | Reexport of objects from aliased modules fixed. See ORB.OutType. 26 | Updated files are ORP.Mod.txt, ORG.Mod.txt, ORB.Mod.txt 27 | 20180804 - Update RISC5 definition in Lola, according to changes on 2018 06 28 28 | RISC5.Lola RISC5Top.Lola 29 | 20180720 - Update compiler: ORP.Mod.txt and ORG.Mod.txt 30 | Cash for base adr of global variables "curSB" has been removed from ORG.Mod. 31 | Removal of this optimization makes compiler simpler. 32 | 20180628 - Update of RISC5, see RISC5.Update. 33 | Cleanup; new feature: Interrupts. Instruction set unchanged. 34 | New source files: RISC5Top.v, RISC5.v, RISC5a.v, Registers.v 35 | (RISC5a is RISC5 without floating-point and without interrupt) 36 | 20170211 - TextFrames.Mod.txt updated (GetSelection) 37 | 20161116 - LeftShifter.v, RightShifter.v as new separate sub-modules, changed: RISC5.v 38 | also added LeftShifter.Lola, RightShifter.Lola, changed RISC5.Lola 39 | 20161003 - FPAdder corrected. x = 0.0, y = 0.0, x - y 40 | 20160918 - RISC5.v , RISC5.Lola adr: offset with sign extension 41 | FPDivider.v FP.Divider.Lola.txt proper rounding 42 | ORP.Mod, ORG.Mod, ORB.Mod "aesthetic" improvements 43 | LSC.Mod , LSV.Mod corrections 44 | 20160808 - FPMultiplier.v FPMultiplier.Lola.txt correct rounding 45 | 20160704 - Display.Mod updated 46 | guard against w < 0 in Display.ReplConst 47 | 20160620 - System.Mod updated (see procedure Clear) 48 | 20160601 - TextFrames.Mod.txt updated 49 | see TextFrames.Extend WHILE ... & (curY >= botY) ... 50 | 20160508 - Oberon07.Report.pdf see syntax of module (";" removed) 51 | see ORP.Declarations (OR (sym = ORB.return)) 52 | 20160501 - Oberon07.Report.pdf see defintion of Type 53 | 20160418 - corrections: ORP.Mod.txt ORG.Mod.txt 54 | 20160410 - updates 55 | ORP.Mod.txt see CompTypes 56 | ORG.Mod.txt see StoreStruct 57 | Modules.Mod.txt see Error() (recompilation not needed) 58 | Graphics.Mod.txt 59 | 20160307 - compiler ORP updated 60 | ORP.Statsequence (assignment) 61 | ORP.CompTypes (dyn arrays: t1.len = -1) 62 | 20160304 - compiler updated 63 | comparison of Booleans re-restablished (ORP.expression, ORG.IntRelation) 64 | assignment of arrays: lengths of source and destination must be equal (ORP.CompTypes) 65 | -------------------------------------------------------------------------------- /people.inf.ethz.ch/wirth/portrait.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Spirit-of-Oberon/wirth-personal/874a6024c1b6b1eff0208225e1004bc1aa62fb79/people.inf.ethz.ch/wirth/portrait.jpg -------------------------------------------------------------------------------- /wirth.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | #cd www.inf.ethz.ch 3 | 4 | git pull 5 | 6 | #cd .. 7 | 8 | wget --user-agent="Mozilla/5.0 (X11; Linux x86_64) AppleWebKit/536.5 (KHTML, like Gecko) Chrome/19.0.1084.9 Safari/536.5" -r -k -l 7 -p -E -np 'https://people.inf.ethz.ch/wirth/' 9 | 10 | #cd www.inf.ethz.ch 11 | 12 | git status 13 | 14 | git commit -a -m "upd" 15 | 16 | git push --------------------------------------------------------------------------------