├── gen ├── .create └── src │ ├── .create │ ├── verilog │ └── .create │ └── vhdl │ └── .create ├── support ├── openocd │ ├── gen │ │ └── .create │ ├── common │ │ └── init │ ├── target │ │ ├── sim │ │ │ └── tcp │ │ └── adafruit │ │ │ └── FT232H │ ├── command │ │ ├── resumeJ1 │ │ ├── stallJ1 │ │ ├── resetJ1 │ │ └── progJ1 │ ├── cpu │ │ └── J1 │ └── bin │ │ ├── progJ1Sim │ │ ├── resetJ1Sim │ │ ├── stallJ1Sim │ │ ├── progJ1 │ │ ├── resetJ1 │ │ ├── resumeJ1Sim │ │ ├── stallJ1 │ │ └── resumeJ1 └── e4thcom │ └── swapforth-j1sc.efc ├── toolchain └── forth │ ├── python │ ├── log │ ├── go │ ├── runtests.fs │ └── swapforth.fs │ ├── build │ ├── .create │ └── 16bit │ │ └── .create │ ├── common │ ├── float0.fs │ ├── exception.fs │ ├── core-ext0.fs │ ├── forth2012.fs │ ├── facilityext.fs │ ├── string0.fs │ ├── deferred.fs │ ├── core0.fs │ ├── mini-oof.fs │ ├── localwords.fs │ ├── value.fs │ ├── comus.fs │ ├── string.fs │ ├── structures.fs │ ├── double0.fs │ ├── double.fs │ ├── core-ext.fs │ ├── tools-ext.fs │ ├── file.fs │ ├── core.fs │ └── peripheral.fs │ ├── bin │ ├── confhost │ ├── confs0 │ ├── confs1 │ ├── confs2 │ └── confs3 │ ├── README.md │ ├── counter.fs │ ├── Makefile │ ├── demos │ ├── irqdemo.fs │ ├── factorials.fs │ ├── newyear.fs │ ├── easter.fs │ ├── vga2.fs │ └── ps2.fs │ ├── LICENSE │ ├── shell.py │ ├── simshell.py │ ├── basewords.fs │ └── swapforth.fs ├── src ├── main │ ├── xilinx │ │ ├── nexys4 │ │ │ ├── Debug.xdc │ │ │ └── Clocks.xdc │ │ └── nexys4ddr │ │ │ ├── Debug.xdc │ │ │ └── Clocks.xdc │ ├── lattice │ │ ├── IceStick │ │ │ └── Pins.pcf │ │ ├── IceBreaker │ │ │ ├── clocks │ │ │ ├── J1Ice.ys │ │ │ └── J1Ice.pcf │ │ └── IcoBoard │ │ │ ├── clocks │ │ │ ├── J1Ico.ys │ │ │ └── J1Ico.pcf │ ├── scala │ │ ├── J1Stack.scala │ │ ├── SingleStepUnit.scala │ │ ├── J1Decoder.scala │ │ ├── DBPinArray.scala │ │ ├── J1JtagData.scala │ │ ├── LEDArray.scala │ │ ├── J1RStack.scala │ │ ├── J1Alu.scala │ │ ├── J1Bus.scala │ │ ├── J1DStack.scala │ │ ├── J1PC.scala │ │ ├── GPIO.scala │ │ ├── J1BusSlaveFactory.scala │ │ ├── PWM.scala │ │ ├── MainMemory.scala │ │ ├── J1.scala │ │ ├── Timer.scala │ │ ├── InterruptCtrl.scala │ │ └── J1Core.scala │ ├── verilog │ │ └── arch │ │ │ ├── IceStick │ │ │ └── PLL.v │ │ │ ├── IcoBoard │ │ │ ├── PLL.v │ │ │ └── Board_IcoBoard.v │ │ │ ├── IceBreaker │ │ │ ├── PLL.v │ │ │ └── Board_IceBreaker.v │ │ │ ├── Nexys4 │ │ │ └── Board_Nexys4.v │ │ │ └── Nexys4DDR │ │ │ └── Board_Nexys4DDR.v │ └── vhdl │ │ └── arch │ │ ├── Nexys4 │ │ └── Board_Nexys4.vhd │ │ └── Nexys4DDR │ │ └── Board_Nexys4DDR.vhd └── test │ └── vhdl │ ├── J1Nexys4X_IRQ_tb.vhd │ └── J1Nexys4X_tb.vhd ├── _config.yml ├── project └── build.properties ├── vprj └── vhdl │ └── J1Sc │ ├── J1Sc │ ├── J1Sc.sim │ │ └── sim_1 │ │ │ └── behav │ │ │ └── xsim │ │ │ ├── xvhdl.log │ │ │ ├── xsim.ini │ │ │ ├── xvhdl.pb │ │ │ ├── xsim.dir │ │ │ ├── Board_Nexys4DDR_behav │ │ │ │ ├── xsimcrash.log │ │ │ │ ├── xsim.svtype │ │ │ │ ├── TempBreakPointFile.txt │ │ │ │ ├── webtalk │ │ │ │ │ ├── .xsim_webtallk.info │ │ │ │ │ ├── usage_statistics_ext_xsim.wdm │ │ │ │ │ └── xsim_webtalk.tcl │ │ │ │ ├── xsimk │ │ │ │ ├── xsim.dbg │ │ │ │ ├── xsim.mem │ │ │ │ ├── xsim.reloc │ │ │ │ ├── xsim.rtti │ │ │ │ ├── xsim.type │ │ │ │ ├── xsim.xdbg │ │ │ │ ├── obj │ │ │ │ │ ├── xsim_0.lnx64.o │ │ │ │ │ └── xsim_1.lnx64.o │ │ │ │ ├── Compile_Options.txt │ │ │ │ ├── xsimkernel.log │ │ │ │ ├── xsim.rlx │ │ │ │ └── xsimSettings.ini │ │ │ └── work │ │ │ │ ├── j1.vdb │ │ │ │ ├── pll.vdb │ │ │ │ ├── pwm.vdb │ │ │ │ ├── ssd.vdb │ │ │ │ ├── gpio.vdb │ │ │ │ ├── j1core.vdb │ │ │ │ ├── timer.vdb │ │ │ │ ├── buffercc.vdb │ │ │ │ ├── ledarray.vdb │ │ │ │ ├── pkg_enum.vdb │ │ │ │ ├── uartctrl.vdb │ │ │ │ ├── buffercc_1.vdb │ │ │ │ ├── buffercc_2.vdb │ │ │ │ ├── dbpinarray.vdb │ │ │ │ ├── j1nexys4x.vdb │ │ │ │ ├── mainmemory.vdb │ │ │ │ ├── streamfifo.vdb │ │ │ │ ├── uartctrlrx.vdb │ │ │ │ ├── uartctrltx.vdb │ │ │ │ ├── dbpinarray_1.vdb │ │ │ │ ├── interruptctrl.vdb │ │ │ │ ├── pkg_scala2hdl.vdb │ │ │ │ ├── board_nexys4ddr.vdb │ │ │ │ └── work.rlx │ │ │ ├── simulate.log │ │ │ ├── xelab.pb │ │ │ ├── Board_Nexys4DDR_behav.wdb │ │ │ ├── Board_Nexys4DDR_vhdl.prj │ │ │ ├── Board_Nexys4DDR.tcl │ │ │ ├── elaborate.log │ │ │ ├── simulate.sh │ │ │ ├── compile.sh │ │ │ ├── elaborate.sh │ │ │ ├── webtalk.jou │ │ │ ├── webtalk_31943.backup.jou │ │ │ ├── webtalk.log │ │ │ ├── webtalk_31943.backup.log │ │ │ └── compile.log │ ├── J1Sc.srcs │ │ ├── constrs_1 │ │ │ └── imports │ │ │ │ └── nexys4ddr │ │ │ │ ├── Debug.xdc │ │ │ │ └── Clocks.xdc │ │ └── sources_1 │ │ │ └── imports │ │ │ └── J1Sc │ │ │ └── src │ │ │ └── main │ │ │ └── vhdl │ │ │ └── arch │ │ │ └── Nexys4DDR │ │ │ └── Board_Nexys4DDR.vhd │ ├── J1Sc.ip_user_files │ │ └── README.txt │ ├── J1Sc.runs │ │ └── .jobs │ │ │ ├── vrs_config_2.xml │ │ │ ├── vrs_config_1.xml │ │ │ ├── vrs_config_3.xml │ │ │ ├── vrs_config_4.xml │ │ │ ├── vrs_config_5.xml │ │ │ ├── vrs_config_6.xml │ │ │ └── vrs_config_7.xml │ └── J1Sc.hw │ │ ├── J1Sc.lpr │ │ └── hw_1 │ │ └── hw.xml │ └── J1SoC_tb_behav.wcfg ├── doc ├── jtag │ ├── JTag.jpg │ └── JTagSmall.jpg ├── misc │ ├── J1ScOnIco.png │ ├── OwnIcoBoard.jpg │ ├── pwm_dc_100.bmp │ ├── pwm_dc_200.bmp │ ├── FirstSimulation.png │ ├── J1Sc_AES_IcoBoard.jpg │ ├── Simulation_with_GUI.png │ ├── Screen Shot 2017-02-19 at 15.05.57.png │ └── Screen Shot 2017-02-19 at 15.23.26.png ├── lattice │ └── IcoBoard.jpg ├── forth │ ├── gforth-0.7.0.pdf │ ├── thinking-forth-color.pdf │ └── README.md ├── xilinx │ └── Nexys4DDRJtag.jpg └── udev │ └── 55-tty-tnt.rules ├── .gitmodules ├── .gitattributes ├── scripts └── installTTY ├── .gitignore └── LICENSE /gen/.create: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /gen/src/.create: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /gen/src/verilog/.create: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /gen/src/vhdl/.create: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /support/openocd/gen/.create: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /toolchain/forth/python/log: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /src/main/xilinx/nexys4/Debug.xdc: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /toolchain/forth/build/.create: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /_config.yml: -------------------------------------------------------------------------------- 1 | theme: jekyll-theme-cayman -------------------------------------------------------------------------------- /src/main/xilinx/nexys4ddr/Debug.xdc: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /toolchain/forth/build/16bit/.create: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /project/build.properties: -------------------------------------------------------------------------------- 1 | sbt.version=0.13.16 2 | -------------------------------------------------------------------------------- /vprj/vhdl/J1Sc/J1Sc/J1Sc.sim/sim_1/behav/xsim/xvhdl.log: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /vprj/vhdl/J1Sc/J1Sc/J1Sc.srcs/constrs_1/imports/nexys4ddr/Debug.xdc: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /support/openocd/common/init: -------------------------------------------------------------------------------- 1 | echo "Init jtag" 2 | init 3 | jtag_init 4 | 5 | -------------------------------------------------------------------------------- /vprj/vhdl/J1Sc/J1Sc/J1Sc.sim/sim_1/behav/xsim/xsim.ini: -------------------------------------------------------------------------------- 1 | work=xsim.dir/work 2 | -------------------------------------------------------------------------------- /toolchain/forth/common/float0.fs: -------------------------------------------------------------------------------- 1 | : faligned aligned ; 2 | : floats cells ; 3 | -------------------------------------------------------------------------------- /vprj/vhdl/J1Sc/J1Sc/J1Sc.sim/sim_1/behav/xsim/xvhdl.pb: -------------------------------------------------------------------------------- 1 | 2 |  3 | 4 | End Record -------------------------------------------------------------------------------- /doc/jtag/JTag.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/SteffenReith/J1Sc/HEAD/doc/jtag/JTag.jpg -------------------------------------------------------------------------------- /vprj/vhdl/J1Sc/J1Sc/J1Sc.sim/sim_1/behav/xsim/xsim.dir/Board_Nexys4DDR_behav/xsimcrash.log: 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-------------------------------------------------------------------------------- /vprj/vhdl/J1Sc/J1Sc/J1Sc.sim/sim_1/behav/xsim/xsim.dir/Board_Nexys4DDR_behav/xsim.svtype: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /.gitmodules: -------------------------------------------------------------------------------- 1 | [submodule "tty0tty"] 2 | path = tty0tty 3 | url = https://github.com/SteffenReith/tty0tty.git 4 | -------------------------------------------------------------------------------- /doc/misc/FirstSimulation.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/SteffenReith/J1Sc/HEAD/doc/misc/FirstSimulation.png -------------------------------------------------------------------------------- /doc/misc/J1Sc_AES_IcoBoard.jpg: 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set_io lock 95 5 | 6 | -------------------------------------------------------------------------------- /vprj/vhdl/J1Sc/J1Sc/J1Sc.sim/sim_1/behav/xsim/simulate.log: -------------------------------------------------------------------------------- 1 | Vivado Simulator 2018.1 2 | Time resolution is 1 ps 3 | -------------------------------------------------------------------------------- /doc/forth/thinking-forth-color.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/SteffenReith/J1Sc/HEAD/doc/forth/thinking-forth-color.pdf -------------------------------------------------------------------------------- /src/main/xilinx/nexys4/Clocks.xdc: -------------------------------------------------------------------------------- 1 | create_clock -period 10.000 -name clk -waveform {0.000 5.000} [get_ports clk100Mhz] 2 | -------------------------------------------------------------------------------- /src/main/lattice/IceBreaker/clocks: -------------------------------------------------------------------------------- 1 | ctx.addClock("clk12Mhz", 12) 2 | ctx.addClock("boardClk", 18) 3 | ctx.addClock("tck", 10) 4 | 5 | -------------------------------------------------------------------------------- /src/main/lattice/IcoBoard/clocks: -------------------------------------------------------------------------------- 1 | ctx.addClock("clk100Mhz", 100) 2 | ctx.addClock("boardClk", 40) 3 | ctx.addClock("tck", 10) 4 | 5 | -------------------------------------------------------------------------------- /vprj/vhdl/J1Sc/J1Sc/J1Sc.sim/sim_1/behav/xsim/xsim.dir/Board_Nexys4DDR_behav/TempBreakPointFile.txt: -------------------------------------------------------------------------------- 1 | Breakpoint File Version 1.0 2 | -------------------------------------------------------------------------------- /support/openocd/target/sim/tcp: -------------------------------------------------------------------------------- 1 | interface jtag_tcp 2 | 3 | adapter_khz 1000 4 | adapter_nsrst_delay 260 5 | jtag_ntrst_delay 250 6 | 7 | -------------------------------------------------------------------------------- /toolchain/forth/bin/confhost: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | export PYTHONPATH=shell:$PYTHONPATH 4 | python simshell.py -h /dev/tnt0 -p common/ 5 | 6 | -------------------------------------------------------------------------------- /toolchain/forth/bin/confs0: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | export PYTHONPATH=shell:$PYTHONPATH 4 | python shell.py -h /dev/ttyUSB0 -p common/ 5 | 6 | -------------------------------------------------------------------------------- /toolchain/forth/bin/confs1: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | export PYTHONPATH=shell:$PYTHONPATH 4 | python shell.py -h /dev/ttyUSB1 -p common/ 5 | 6 | -------------------------------------------------------------------------------- /toolchain/forth/bin/confs2: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | export PYTHONPATH=shell:$PYTHONPATH 4 | python shell.py -h /dev/ttyUSB2 -p common/ 5 | 6 | -------------------------------------------------------------------------------- /toolchain/forth/bin/confs3: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | export PYTHONPATH=shell:$PYTHONPATH 4 | python shell.py -h /dev/ttyUSB3 -p common/ 5 | 6 | -------------------------------------------------------------------------------- /doc/misc/Screen Shot 2017-02-19 at 15.05.57.png: -------------------------------------------------------------------------------- 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J1Sc.cpu $_STALL_width $_ocdTrue 4 | runtest 2 5 | 6 | -------------------------------------------------------------------------------- /support/openocd/cpu/J1: -------------------------------------------------------------------------------- 1 | set _CPUTAPID 0x01234567 2 | set _CHIPNAME J1Sc 3 | 4 | jtag newtap $_CHIPNAME cpu -expected-id $_CPUTAPID -irlen $_irwidth 5 | 6 | -------------------------------------------------------------------------------- /.gitattributes: -------------------------------------------------------------------------------- 1 | *.scala filter=keywords 2 | *.vhdl filter=keywords 3 | *.vhd filter=keywords 4 | *.fs filter=keywords 5 | *.v filter=keywords 6 | 7 | -------------------------------------------------------------------------------- /doc/udev/55-tty-tnt.rules: -------------------------------------------------------------------------------- 1 | KERNEL=="tnt0", SUBSYSTEM=="tty", GROUP="dialout", MODE="666" 2 | KERNEL=="tnt1", SUBSYSTEM=="tty", GROUP="dialout", MODE="666" 3 | 4 | -------------------------------------------------------------------------------- /toolchain/forth/README.md: -------------------------------------------------------------------------------- 1 | This toolchain is derived from SwapForth (https://github.com/jamesbowman/j1) by James Bowman. See LICENSE for legal details. 2 | 3 | -------------------------------------------------------------------------------- /vprj/vhdl/J1Sc/J1Sc/J1Sc.sim/sim_1/behav/xsim/xelab.pb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/SteffenReith/J1Sc/HEAD/vprj/vhdl/J1Sc/J1Sc/J1Sc.sim/sim_1/behav/xsim/xelab.pb -------------------------------------------------------------------------------- /vprj/vhdl/J1Sc/J1Sc/J1Sc.srcs/constrs_1/imports/nexys4ddr/Clocks.xdc: -------------------------------------------------------------------------------- 1 | create_clock -period 10.000 -name clk100Mhz -waveform {0.000 5.000} [get_ports clk100Mhz] 2 | -------------------------------------------------------------------------------- /toolchain/forth/python/go: -------------------------------------------------------------------------------- 1 | # time echo | PYTHONPATH=../shell/:$PYTHONPATH python nuc.py 2 | set -e 3 | PYTHONPATH=../shell/:$PYTHONPATH python3 nuc.py -c 2 -b 4 | echo PASSED 5 | -------------------------------------------------------------------------------- /toolchain/forth/counter.fs: -------------------------------------------------------------------------------- 1 | : CNT 0 DO I . 500 ms LOOP ; 2 | : CNTFAST 0 DO I . 100 ms LOOP ; 3 | : CNTSIM 0 DO I . 50 ms LOOP ; 4 | : CNTSIMFAST 0 DO I . 10 ms LOOP ; 5 | 6 | 7 | -------------------------------------------------------------------------------- /vprj/vhdl/J1Sc/J1Sc/J1Sc.ip_user_files/README.txt: -------------------------------------------------------------------------------- 1 | The files in this directory structure are automatically generated and managed by Vivado. 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adapter_khz 1000 8 | 9 | transport select jtag 10 | 11 | -------------------------------------------------------------------------------- /support/openocd/bin/progJ1Sim: -------------------------------------------------------------------------------- 1 | #!/usr/local/openocd/bin/openocd -f 2 | 3 | source [find gen/jinfo] 4 | 5 | source [find target/sim/tcp] 6 | source [find cpu/J1] 7 | source [find common/init] 8 | 9 | source [find command/progJ1] 10 | 11 | exit 12 | 13 | -------------------------------------------------------------------------------- /support/openocd/bin/resetJ1Sim: -------------------------------------------------------------------------------- 1 | #!/usr/local/openocd/bin/openocd -f 2 | 3 | source [find gen/jinfo] 4 | 5 | source [find target/sim/tcp] 6 | source [find cpu/J1] 7 | source [find common/init] 8 | 9 | source [find command/resetJ1] 10 | 11 | exit 12 | 13 | -------------------------------------------------------------------------------- /support/openocd/bin/stallJ1Sim: -------------------------------------------------------------------------------- 1 | #!/usr/local/openocd/bin/openocd -f 2 | 3 | source [find gen/jinfo] 4 | 5 | source [find target/sim/tcp] 6 | source [find cpu/J1] 7 | source [find common/init] 8 | 9 | source [find command/stallJ1] 10 | 11 | exit 12 | 13 | -------------------------------------------------------------------------------- /support/openocd/bin/progJ1: -------------------------------------------------------------------------------- 1 | #!/usr/local/openocd/bin/openocd -f 2 | 3 | source [find gen/jinfo] 4 | 5 | source [find target/adafruit/FT232H] 6 | source [find cpu/J1] 7 | source [find common/init] 8 | 9 | source [find command/progJ1] 10 | 11 | exit 12 | 13 | -------------------------------------------------------------------------------- /support/openocd/bin/resetJ1: -------------------------------------------------------------------------------- 1 | #!/usr/local/openocd/bin/openocd -f 2 | 3 | source [find gen/jinfo] 4 | 5 | source [find target/adafruit/FT232H] 6 | source [find cpu/J1] 7 | source [find common/init] 8 | 9 | source [find command/resetJ1] 10 | 11 | exit 12 | 13 | -------------------------------------------------------------------------------- /support/openocd/bin/resumeJ1Sim: -------------------------------------------------------------------------------- 1 | #!/usr/local/openocd/bin/openocd -f 2 | 3 | source [find gen/jinfo] 4 | 5 | source [find target/sim/tcp] 6 | source [find cpu/J1] 7 | source [find common/init] 8 | 9 | source [find command/resumeJ1] 10 | 11 | exit 12 | 13 | -------------------------------------------------------------------------------- /support/openocd/bin/stallJ1: -------------------------------------------------------------------------------- 1 | #!/usr/local/openocd/bin/openocd -f 2 | 3 | source [find gen/jinfo] 4 | 5 | source [find target/adafruit/FT232H] 6 | source [find cpu/J1] 7 | source [find common/init] 8 | 9 | source [find command/stallJ1] 10 | 11 | exit 12 | 13 | -------------------------------------------------------------------------------- /support/openocd/bin/resumeJ1: -------------------------------------------------------------------------------- 1 | #!/usr/local/openocd/bin/openocd -f 2 | 3 | source [find gen/jinfo] 4 | 5 | source [find target/adafruit/FT232H] 6 | source [find cpu/J1] 7 | source [find common/init] 8 | 9 | source [find command/resumeJ1] 10 | 11 | exit 12 | 13 | -------------------------------------------------------------------------------- /vprj/vhdl/J1Sc/J1Sc/J1Sc.sim/sim_1/behav/xsim/xsim.dir/Board_Nexys4DDR_behav/Compile_Options.txt: -------------------------------------------------------------------------------- 1 | -wto "28d8c42bf4ea4dbdaf7c1c1f04676d10" --incr --debug "typical" --relax --mt "8" -L "work" -L "secureip" --snapshot "Board_Nexys4DDR_behav" "work.Board_Nexys4DDR" -log "elaborate.log" 2 | -------------------------------------------------------------------------------- /src/main/lattice/IcoBoard/J1Ico.ys: -------------------------------------------------------------------------------- 1 | # Read all design files 2 | read_verilog src/main/verilog/arch/IcoBoard/PLL.v gen/src/verilog/J1Ico.v src/main/verilog/arch/IcoBoard/Board_IcoBoard.v 3 | 4 | synth_ice40 -top IcoBoard -json gen/src/verilog/J1Ico.json -blif gen/src/verilog/J1Ico.blif 5 | 6 | -------------------------------------------------------------------------------- /toolchain/forth/common/exception.fs: -------------------------------------------------------------------------------- 1 | variable abortmsg 2 | 3 | : (abort") ( x1 caddr u -- ) 4 | swap if 5 | abortmsg ! -2 throw 6 | else 7 | drop 8 | then 9 | ; 10 | 11 | : abort" 12 | postpone c" 13 | postpone (abort") 14 | ; immediate 15 | 16 | -------------------------------------------------------------------------------- /src/main/lattice/IceBreaker/J1Ice.ys: -------------------------------------------------------------------------------- 1 | # Read all design files 2 | read_verilog src/main/verilog/arch/IceBreaker/PLL.v gen/src/verilog/J1Ice.v src/main/verilog/arch/IceBreaker/Board_IceBreaker.v 3 | 4 | synth_ice40 -top IceBreaker -json gen/src/verilog/J1Ice.json -blif gen/src/verilog/J1Ice.blif 5 | 6 | -------------------------------------------------------------------------------- /support/openocd/command/resetJ1: -------------------------------------------------------------------------------- 1 | echo "Activate Reset" 2 | irscan J1Sc.cpu $_RESET_id 3 | drscan J1Sc.cpu $_RESET_width $_ocdTrue 4 | runtest 2 5 | 6 | sleep 500 7 | 8 | echo "Deactive Reset" 9 | irscan J1Sc.cpu $_RESET_id 10 | drscan J1Sc.cpu $_RESET_width $_ocdFalse 11 | runtest 2 12 | 13 | -------------------------------------------------------------------------------- /toolchain/forth/common/core-ext0.fs: -------------------------------------------------------------------------------- 1 | : roll 2 | ?dup if 3 | swap >r 4 | 1- recurse 5 | r> swap 6 | then 7 | ; 8 | 9 | : pick 10 | ?dup if 11 | swap >r 12 | 1- recurse 13 | r> swap 14 | else 15 | dup 16 | then 17 | ; 18 | -------------------------------------------------------------------------------- /vprj/vhdl/J1Sc/J1Sc/J1Sc.runs/.jobs/vrs_config_2.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | -------------------------------------------------------------------------------- /toolchain/forth/common/forth2012.fs: -------------------------------------------------------------------------------- 1 | \ These definitions for Forth2012 taken from the standard 2 | \ http://www.forth200x.org/documents/html/core.html 3 | 4 | : HOLDS ( addr u -- ) 5 | BEGIN DUP WHILE 1- 2DUP + C@ HOLD REPEAT 2DROP 6 | ; 7 | 8 | : BUFFER: ( u "" -- ; -- addr ) 9 | CREATE ALLOT 10 | ; 11 | -------------------------------------------------------------------------------- /toolchain/forth/Makefile: -------------------------------------------------------------------------------- 1 | all: nucleus 2 | mv build/nuc.binary build/16bit/nuc.binary 3 | mv build/nuc.hex build/16bit/nuc.hex 4 | mv build/nuc.lst build/16bit/nuc.lst 5 | 6 | nucleus: cross.fs basewords.fs nuc.fs 7 | gforth cross.fs basewords.fs nuc.fs 8 | 9 | clean: 10 | rm build/16bit/nuc.hex build/16bit/nuc.binary build/16bit/nuc.lst 11 | -------------------------------------------------------------------------------- /vprj/vhdl/J1Sc/J1Sc/J1Sc.hw/J1Sc.lpr: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | -------------------------------------------------------------------------------- /toolchain/forth/common/facilityext.fs: -------------------------------------------------------------------------------- 1 | \ ####### FACILITY EXT #################################### 2 | 3 | : csi \ Control Sequence Introducer 4 | 27 emit '[' emit 5 | ; 6 | 7 | : at-xy ( u1 u2 ) \ cursor to column u1, row u2 8 | csi 9 | 1+ 0 u.r 10 | ';' emit 11 | 1+ 0 u.r 12 | 'H' emit 13 | ; 14 | 15 | : page 16 | 0 0 at-xy 17 | csi 'J' emit 18 | ; 19 | -------------------------------------------------------------------------------- /toolchain/forth/common/string0.fs: -------------------------------------------------------------------------------- 1 | : same? ( c-addr1 c-addr2 u -- -1|0|1 ) 2 | bounds ?do 3 | i c@ over c@ - ?dup if 4 | 0> 2* 1+ 5 | nip unloop exit 6 | then 7 | 1+ 8 | loop 9 | drop 0 10 | ; 11 | 12 | : compare 13 | rot 2dup swap - >r \ ca1 ca2 u2 u1 r: u1-u2 14 | min same? ?dup 15 | if r> drop exit then 16 | r> dup if 0< 2* 1+ then ; 17 | -------------------------------------------------------------------------------- /vprj/vhdl/J1Sc/J1Sc/J1Sc.sim/sim_1/behav/xsim/Board_Nexys4DDR_vhdl.prj: -------------------------------------------------------------------------------- 1 | # compile vhdl design source files 2 | vhdl work \ 3 | "../../../../J1Sc.srcs/sources_1/imports/J1Sc/src/main/vhdl/arch/Nexys4DDR/PLL.vhd" \ 4 | "../../../../J1Sc.srcs/sources_1/imports/J1Sc/gen/src/vhdl/J1Nexys4X.vhd" \ 5 | "../../../../J1Sc.srcs/sources_1/imports/J1Sc/src/main/vhdl/arch/Nexys4DDR/Board_Nexys4DDR.vhd" \ 6 | 7 | # Do not sort compile order 8 | nosort 9 | -------------------------------------------------------------------------------- /vprj/vhdl/J1Sc/J1Sc/J1Sc.sim/sim_1/behav/xsim/xsim.dir/Board_Nexys4DDR_behav/xsimkernel.log: -------------------------------------------------------------------------------- 1 | Running: xsim.dir/Board_Nexys4DDR_behav/xsimk -simmode gui -wdb Board_Nexys4DDR_behav.wdb -simrunnum 0 -socket 48990 2 | Design successfully loaded 3 | Design Loading Memory Usage: 43548 KB (Peak: 43548 KB) 4 | Design Loading CPU Usage: 0 ms 5 | Simulation completed 6 | Simulation Memory Usage: 133484 KB (Peak: 190820 KB) 7 | Simulation CPU Usage: 10 ms 8 | -------------------------------------------------------------------------------- /toolchain/forth/common/deferred.fs: -------------------------------------------------------------------------------- 1 | : defer ( "name" -- ) 2 | create ['] abort , 3 | does> ( ... -- ... ) 4 | @ execute ; 5 | 6 | : defer@ ( xt1 -- xt2 ) 7 | >body @ ; 8 | 9 | : defer! ( xt2 xt1 -- ) 10 | >body ! ; 11 | 12 | : is 13 | state @ if 14 | POSTPONE ['] POSTPONE defer! 15 | else 16 | ' defer! 17 | then ; immediate 18 | 19 | : action-of 20 | state @ if 21 | POSTPONE ['] POSTPONE defer@ 22 | else 23 | ' defer@ 24 | then ; immediate 25 | -------------------------------------------------------------------------------- /vprj/vhdl/J1Sc/J1Sc/J1Sc.runs/.jobs/vrs_config_1.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | -------------------------------------------------------------------------------- /vprj/vhdl/J1Sc/J1Sc/J1Sc.runs/.jobs/vrs_config_3.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | -------------------------------------------------------------------------------- /vprj/vhdl/J1Sc/J1Sc/J1Sc.runs/.jobs/vrs_config_4.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | -------------------------------------------------------------------------------- /vprj/vhdl/J1Sc/J1Sc/J1Sc.runs/.jobs/vrs_config_5.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | -------------------------------------------------------------------------------- /vprj/vhdl/J1Sc/J1Sc/J1Sc.runs/.jobs/vrs_config_6.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | -------------------------------------------------------------------------------- /vprj/vhdl/J1Sc/J1Sc/J1Sc.runs/.jobs/vrs_config_7.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | -------------------------------------------------------------------------------- /vprj/vhdl/J1Sc/J1Sc/J1Sc.sim/sim_1/behav/xsim/Board_Nexys4DDR.tcl: -------------------------------------------------------------------------------- 1 | set curr_wave [current_wave_config] 2 | if { [string length $curr_wave] == 0 } { 3 | if { [llength [get_objects]] > 0} { 4 | add_wave / 5 | set_property needs_save false [current_wave_config] 6 | } else { 7 | send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." 8 | } 9 | } 10 | 11 | run 1000ns 12 | -------------------------------------------------------------------------------- /vprj/vhdl/J1Sc/J1Sc/J1Sc.sim/sim_1/behav/xsim/elaborate.log: -------------------------------------------------------------------------------- 1 | Vivado Simulator 2018.1 2 | Copyright 1986-1999, 2001-2017 Xilinx, Inc. All Rights Reserved. 3 | Running: /opt/Xilinx/Vivado/2018.1/bin/unwrapped/lnx64.o/xelab -wto 28d8c42bf4ea4dbdaf7c1c1f04676d10 --incr --debug typical --relax --mt 8 -L work -L secureip --snapshot Board_Nexys4DDR_behav work.Board_Nexys4DDR -log elaborate.log 4 | Using 8 slave threads. 5 | Starting static elaboration 6 | Completed static elaboration 7 | INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel 8 | -------------------------------------------------------------------------------- /toolchain/forth/common/core0.fs: -------------------------------------------------------------------------------- 1 | : char+ 1+ ; 2 | : chars ; 3 | 4 | : abort -1 throw ; 5 | 6 | : ' 7 | parse-name 8 | sfind 9 | 0= -13 and throw 10 | ; 11 | 12 | : ['] 13 | ' postpone literal 14 | ; immediate 15 | 16 | : char 17 | parse-name drop c@ 18 | ; 19 | 20 | : [char] 21 | char postpone literal 22 | ; immediate 23 | 24 | : ( 25 | [char] ) parse 2drop 26 | ; immediate 27 | 28 | : else 29 | postpone ahead 30 | swap 31 | postpone then 32 | ; immediate 33 | 34 | : while 35 | postpone if 36 | swap 37 | ; immediate 38 | 39 | : repeat 40 | postpone again 41 | postpone then 42 | ; immediate 43 | -------------------------------------------------------------------------------- /src/main/scala/J1Stack.scala: -------------------------------------------------------------------------------- 1 | /* 2 | * Author: Steffen Reith (Steffen.Reith@hs-rm.de) 3 | * 4 | * Create Date: Mon Jun 22 23:54:55 CEST 2020 5 | * Module Name: J1Stack - An abstract stack which can be extended for the data and return stack 6 | * Project Name: J1Sc - A simple J1 implementation in Scala using Spinal HDL 7 | * 8 | */ 9 | import spinal.core._ 10 | 11 | class J1Stack(idxWidth : Int) extends Area { 12 | 13 | // Enable signal for writing to the stack 14 | val stackWriteEnable = Bool 15 | 16 | // Stack pointer and next signal for the data stack 17 | val stackPtrN = UInt(idxWidth bits) 18 | val stackPtr = Reg(UInt(idxWidth bits)) init (0) 19 | 20 | } 21 | -------------------------------------------------------------------------------- /vprj/vhdl/J1Sc/J1Sc/J1Sc.hw/hw_1/hw.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | -------------------------------------------------------------------------------- /toolchain/forth/python/runtests.fs: -------------------------------------------------------------------------------- 1 | \ ANS Forth tests - run all tests 2 | 3 | \ Adjust the file paths as appropriate to your system 4 | \ Select the appropriate test harness, either the simple tester.fr 5 | \ or the more complex ttester.fs 6 | 7 | CR .( Running ANS Forth and Forth 2012 test programs, version 0.11) CR 8 | 9 | include tester.fr 10 | include core.fr 11 | include coreplustest.fth 12 | include errorreport.fth 13 | include coreexttest.fth 14 | include doubletest.fth 15 | include exceptiontest.fth 16 | include facilitytest.fth 17 | \ include filetest.fth 18 | \ include localstest.fth 19 | include memorytest.fth 20 | \ include toolstest.fth 21 | \ include searchordertest.fth 22 | include stringtest.fth 23 | REPORT-ERRORS 24 | 25 | CR CR .( Forth tests completed ) CR CR 26 | 27 | 28 | 29 | -------------------------------------------------------------------------------- /toolchain/forth/common/mini-oof.fs: -------------------------------------------------------------------------------- 1 | \ Mini-OOF 12apr98py 2 | : method ( m v "name" -- m' v ) Create over , swap cell+ swap 3 | DOES> ( ... o -- ... ) @ over @ + @ execute ; 4 | : var ( m v size "name" -- m v' ) Create over , + 5 | DOES> ( o -- addr ) @ + ; 6 | : class ( class -- class methods vars ) dup 2@ ; 7 | : end-class ( class methods vars "name" -- ) 8 | Create here >r , dup , 2 cells ?DO ['] noop , 1 cells +LOOP 9 | cell+ dup cell+ r> rot @ 2 cells /string move ; 10 | : >vt ( class "name" -- addr ) ' >body @ + ; 11 | : bind ( class "name" -- xt ) >vt @ ; 12 | : defines ( xt class "name" -- ) >vt ! ; 13 | : anew ( class -- o ) align here over @ allot tuck ! ; 14 | : :: ( class "name" -- ) bind compile, ; 15 | Create object 1 cells , 2 cells , 16 | -------------------------------------------------------------------------------- /vprj/vhdl/J1Sc/J1Sc/J1Sc.sim/sim_1/behav/xsim/xsim.dir/Board_Nexys4DDR_behav/xsim.rlx: -------------------------------------------------------------------------------- 1 | 2 | { 3 | crc : 8812314718631989034 , 4 | ccp_crc : 0 , 5 | cmdline : " -wto 28d8c42bf4ea4dbdaf7c1c1f04676d10 --incr --debug typical --relax --mt 8 -L work -L secureip --snapshot Board_Nexys4DDR_behav work.Board_Nexys4DDR" , 6 | buildDate : "Apr 4 2018" , 7 | buildTime : "18:43:17" , 8 | linkCmd : "/usr/bin/gcc -Wa,-W -O -fPIC -m64 -Wl,--unresolved-symbols=ignore-all -o \"xsim.dir/Board_Nexys4DDR_behav/xsimk\" \"xsim.dir/Board_Nexys4DDR_behav/obj/xsim_0.lnx64.o\" \"xsim.dir/Board_Nexys4DDR_behav/obj/xsim_1.lnx64.o\" \"/opt/Xilinx/Vivado/2018.1/lib/lnx64.o/librdi_simulator_kernel.so\" \"/opt/Xilinx/Vivado/2018.1/lib/lnx64.o/librdi_simbridge_kernel.so\"" , 9 | aggregate_nets : 10 | [ 11 | ] 12 | } -------------------------------------------------------------------------------- /toolchain/forth/common/localwords.fs: -------------------------------------------------------------------------------- 1 | \ Start a local word definition region 2 | \ These words will not be globally visible. 3 | \ Usage: 4 | \ 5 | \ localwords \ { 6 | \ ... define local words ... 7 | \ publicwords \ }{ 8 | \ ... define public words ... 9 | \ donewords \ } 10 | \ 11 | 12 | : LOCALWORDS 13 | get-current 14 | get-order wordlist swap 1+ set-order definitions 15 | ; 16 | 17 | : PUBLICWORDS 18 | set-current 19 | ; 20 | 21 | : DONEWORDS 22 | previous 23 | ; 24 | 25 | marker testing-localwords 26 | : k0 100 ; 27 | t{ k0 -> 100 }t 28 | localwords 29 | : k0 200 ; 30 | : k1 300 ; 31 | publicwords 32 | t{ k0 k1 -> 200 300 }t 33 | : k01 k0 k1 ; 34 | donewords 35 | t{ k0 -> 100 }t 36 | t{ k01 -> 200 300 }t 37 | t{ bl word k1 find nip -> 0 }t 38 | testing-localwords 39 | -------------------------------------------------------------------------------- /src/main/verilog/arch/IceStick/PLL.v: -------------------------------------------------------------------------------- 1 | // 2 | // Author: Steffen Reith (steffen.reith@hs-rm.de) 3 | // Committer: Steffen Reith 4 | // 5 | // Creation Date: Sat Apr 29 20:32:17 CEST 2017 6 | // Module Name: PLL for an ICEStick 7 | // Project Name: J1Sc - A simple J1 implementation in Scala using Spinal HDL 8 | // 9 | module PLL(clkIn, clkOut, isLocked); 10 | 11 | // Input ports 12 | input clkIn; 13 | 14 | // Output ports 15 | output clkOut; 16 | output isLocked; 17 | 18 | SB_PLL40_CORE #( 19 | .FEEDBACK_PATH("SIMPLE"), 20 | .PLLOUT_SELECT("GENCLK"), 21 | .DIVR(4'b0000), 22 | .DIVF(7'b1001111), 23 | .DIVQ(3'b100), 24 | .FILTER_RANGE(3'b001) 25 | ) uut ( 26 | .LOCK(isLocked), 27 | .RESETB(1'b1), 28 | .BYPASS(1'b0), 29 | .REFERENCECLK(clkIn), 30 | .PLLOUTCORE(clkOut) 31 | ); 32 | endmodule 33 | -------------------------------------------------------------------------------- /vprj/vhdl/J1Sc/J1Sc/J1Sc.sim/sim_1/behav/xsim/simulate.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash -f 2 | # **************************************************************************** 3 | # Vivado (TM) v2018.1 (64-bit) 4 | # 5 | # Filename : simulate.sh 6 | # Simulator : Xilinx Vivado Simulator 7 | # Description : Script for simulating the design by launching the simulator 8 | # 9 | # Generated by Vivado on Fri May 04 01:52:44 CEST 2018 10 | # SW Build 2188600 on Wed Apr 4 18:39:19 MDT 2018 11 | # 12 | # Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. 13 | # 14 | # usage: simulate.sh 15 | # 16 | # **************************************************************************** 17 | ExecStep() 18 | { 19 | "$@" 20 | RETVAL=$? 21 | if [ $RETVAL -ne 0 ] 22 | then 23 | exit $RETVAL 24 | fi 25 | } 26 | ExecStep xsim Board_Nexys4DDR_behav -key {Behavioral:sim_1:Functional:Board_Nexys4DDR} -tclbatch Board_Nexys4DDR.tcl -log simulate.log 27 | -------------------------------------------------------------------------------- /vprj/vhdl/J1Sc/J1Sc/J1Sc.sim/sim_1/behav/xsim/compile.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash -f 2 | # **************************************************************************** 3 | # Vivado (TM) v2018.1 (64-bit) 4 | # 5 | # Filename : compile.sh 6 | # Simulator : Xilinx Vivado Simulator 7 | # Description : Script for compiling the simulation design source files 8 | # 9 | # Generated by Vivado on Fri May 04 01:52:42 CEST 2018 10 | # SW Build 2188600 on Wed Apr 4 18:39:19 MDT 2018 11 | # 12 | # Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. 13 | # 14 | # usage: compile.sh 15 | # 16 | # **************************************************************************** 17 | ExecStep() 18 | { 19 | "$@" 20 | RETVAL=$? 21 | if [ $RETVAL -ne 0 ] 22 | then 23 | exit $RETVAL 24 | fi 25 | } 26 | echo "xvhdl --incr --relax -prj Board_Nexys4DDR_vhdl.prj" 27 | ExecStep xvhdl --incr --relax -prj Board_Nexys4DDR_vhdl.prj 2>&1 | tee -a compile.log 28 | -------------------------------------------------------------------------------- /vprj/vhdl/J1Sc/J1Sc/J1Sc.sim/sim_1/behav/xsim/elaborate.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash -f 2 | # **************************************************************************** 3 | # Vivado (TM) v2018.1 (64-bit) 4 | # 5 | # Filename : elaborate.sh 6 | # Simulator : Xilinx Vivado Simulator 7 | # Description : Script for elaborating the compiled design 8 | # 9 | # Generated by Vivado on Fri May 04 01:52:43 CEST 2018 10 | # SW Build 2188600 on Wed Apr 4 18:39:19 MDT 2018 11 | # 12 | # Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. 13 | # 14 | # usage: elaborate.sh 15 | # 16 | # **************************************************************************** 17 | ExecStep() 18 | { 19 | "$@" 20 | RETVAL=$? 21 | if [ $RETVAL -ne 0 ] 22 | then 23 | exit $RETVAL 24 | fi 25 | } 26 | ExecStep xelab -wto 28d8c42bf4ea4dbdaf7c1c1f04676d10 --incr --debug typical --relax --mt 8 -L work -L secureip --snapshot Board_Nexys4DDR_behav work.Board_Nexys4DDR -log elaborate.log 27 | -------------------------------------------------------------------------------- /src/main/verilog/arch/IcoBoard/PLL.v: -------------------------------------------------------------------------------- 1 | // 2 | // Author: Steffen Reith (steffen.reith@hs-rm.de) 3 | // Committer: Steffen Reith 4 | // 5 | // Creation Date: Mon Nov 20 10:37:12 CET 2017 6 | // Module Name: PLL for an IcoBoard (make 25 Mhz out of 100 Mhz) 7 | // Project Name: J1Sc - A simple J1 implementation in Scala using Spinal HDL 8 | // 9 | module PLL(clkIn, clkOut, isLocked); 10 | 11 | // Input ports 12 | input clkIn; 13 | 14 | // Output ports 15 | output clkOut; 16 | output isLocked; 17 | 18 | // In: 100Mhz / Out: 40Mhz 19 | SB_PLL40_CORE #( 20 | .FEEDBACK_PATH("SIMPLE"), 21 | .PLLOUT_SELECT("GENCLK"), 22 | .DIVR(4'b0100), 23 | .DIVF(7'b0011111), 24 | .DIVQ(3'b100), 25 | .FILTER_RANGE(3'b010) 26 | ) uut ( 27 | .LOCK(isLocked), 28 | .RESETB(1'b1), 29 | .BYPASS(1'b0), 30 | .REFERENCECLK(clkIn), 31 | .PLLOUTCORE(clkOut) 32 | ); 33 | endmodule 34 | 35 | -------------------------------------------------------------------------------- /toolchain/forth/common/value.fs: -------------------------------------------------------------------------------- 1 | \ Portable implementation of VALUE, etc 2 | \ The first cell of a VALUE is the XT of the "TO" word. 3 | \ Subsequent cells are the value itself. 4 | \ 5 | \ For example, "3 VALUE FOO" makes 6 | \ 7 | \ FOO: +---------+ 8 | \ | ! | 9 | \ +---------+ 10 | \ | 3 | 11 | \ +---------+ 12 | \ 13 | \ and "100 200 2VALUE BAR" makes 14 | \ 15 | \ BAR: +---------+ 16 | \ | 2! | 17 | \ +---------+ 18 | \ | 200 | 19 | \ +---------+ 20 | \ | 100 | 21 | \ +---------+ 22 | \ 23 | 24 | : value 25 | create ['] ! , , 26 | does> cell+ @ 27 | ; 28 | 29 | : 2value 30 | create ['] 2! , , , 31 | does> cell+ 2@ 32 | ; 33 | 34 | : to 35 | ' >body 36 | dup cell+ 37 | state @ if 38 | postpone literal 39 | @ compile, 40 | else 41 | swap @ execute 42 | then 43 | ; immediate 44 | -------------------------------------------------------------------------------- /toolchain/forth/common/comus.fs: -------------------------------------------------------------------------------- 1 | \ Comus explains some common Forth words that aren't in the ANS Forth Standard. The name Comus was suggested by Neil Bawd. 2 | \ 3 | \ http://www.murphywong.net/hello/comus.htm 4 | 5 | : noop ; 6 | : off false swap ! ; 7 | : on true swap ! ; 8 | 9 | \ ####### RANDOM ########################################## 10 | 11 | \ setseed sets the random number seed 12 | \ random returns a random 32-bit number 13 | \ 14 | \ based on "Xorshift RNGs" by George Marsaglia 15 | \ http://www.jstatsoft.org/v08/i14/paper 16 | 17 | variable seed 18 | $7a92764b seed ! 19 | 20 | : setseed ( u -- ) 21 | dup 0= or \ map 0 to -1 22 | seed ! 23 | ; 24 | 25 | : random ( -- u ) 26 | seed @ 27 | dup 13 lshift xor 28 | dup 17 rshift xor 29 | dup 5 lshift xor 30 | dup seed ! 31 | ; 32 | 33 | : randrange ( u0 -- u1 ) \ u1 is a random number less than u0 34 | random um* nip 35 | ; 36 | 37 | : not 0= ; 38 | -------------------------------------------------------------------------------- /vprj/vhdl/J1Sc/J1Sc/J1Sc.sim/sim_1/behav/xsim/xsim.dir/work/work.rlx: -------------------------------------------------------------------------------- 1 | 0.6 2 | 2018.1 3 | Apr 4 2018 4 | 18:43:17 5 | /home/streit/src/scala/J1Sc/vprj/vhdl/J1Sc/J1Sc/J1Sc.srcs/sources_1/imports/J1Sc/gen/src/vhdl/J1Nexys4X.vhd,1521724658,vhdl,/home/streit/src/scala/J1Sc/vprj/vhdl/J1Sc/J1Sc/J1Sc.srcs/sources_1/imports/J1Sc/src/main/vhdl/arch/Nexys4DDR/Board_Nexys4DDR.vhd,,,buffercc;buffercc_1;buffercc_2;dbpinarray;dbpinarray_1;gpio;interruptctrl;j1;j1core;j1nexys4x;ledarray;mainmemory;pkg_enum;pkg_scala2hdl;pwm;ssd;streamfifo;timer;uartctrl;uartctrlrx;uartctrltx,,,,,,,, 6 | /home/streit/src/scala/J1Sc/vprj/vhdl/J1Sc/J1Sc/J1Sc.srcs/sources_1/imports/J1Sc/src/main/vhdl/arch/Nexys4DDR/Board_Nexys4DDR.vhd,1514110635,vhdl,,,,board_nexys4ddr,,,,,,,, 7 | /home/streit/src/scala/J1Sc/vprj/vhdl/J1Sc/J1Sc/J1Sc.srcs/sources_1/imports/J1Sc/src/main/vhdl/arch/Nexys4DDR/PLL.vhd,1514110635,vhdl,/home/streit/src/scala/J1Sc/vprj/vhdl/J1Sc/J1Sc/J1Sc.srcs/sources_1/imports/J1Sc/src/main/vhdl/arch/Nexys4DDR/Board_Nexys4DDR.vhd,,,pll,,,,,,,, 8 | -------------------------------------------------------------------------------- /src/main/verilog/arch/IceBreaker/PLL.v: -------------------------------------------------------------------------------- 1 | // 2 | // Author: Steffen Reith (steffen.reith@hs-rm.de) 3 | // Committer: Steffen Reith 4 | // 5 | // Creation Date: Fri Feb 15 21:00:38 CET 2019 6 | // Module Name: PLL for an IceBreaker board (make 42 Mhz out of 12 Mhz) 7 | // Project Name: J1Sc - A simple J1 implementation in Scala using Spinal HDL 8 | // 9 | module PLL(clkIn, clkOut, isLocked); 10 | 11 | // Input ports 12 | input clkIn; 13 | 14 | // Output ports 15 | output clkOut; 16 | output isLocked; 17 | 18 | // In: 12Mhz / Out: 18Mhz 19 | SB_PLL40_PAD #( 20 | .FEEDBACK_PATH("SIMPLE"), 21 | .DIVR(4'b0000), // DIVR = 0 22 | .DIVF(7'b0101111), // DIVF = 47 23 | .DIVQ(3'b101), // DIVQ = 5 24 | .FILTER_RANGE(3'b001) // FILTER_RANGE = 1 25 | ) global_pll_inst ( 26 | .LOCK(isLocked), 27 | .RESETB(1'b1), 28 | .BYPASS(1'b0), 29 | .PACKAGEPIN(clkIn), 30 | .PLLOUTGLOBAL(clkOut) 31 | ); 32 | endmodule 33 | -------------------------------------------------------------------------------- /src/main/scala/SingleStepUnit.scala: -------------------------------------------------------------------------------- 1 | /* 2 | * Author: Steffen Reith (Steffen.Reith@hs-rm.de) 3 | * 4 | * Create Date: Sat May 12 00:46:16 GMT+2 2018 5 | * Module Name: SingleStepUnit - Implements a trigger mechanism for the single step mode 6 | * Project Name: J1Sc - A simple J1 implementation in Scala using Spinal HDL 7 | * 8 | */ 9 | import spinal.core._ 10 | 11 | class SingleStepUnit { 12 | 13 | val internal = new Bundle { 14 | 15 | // Enable the single step mode (registered) 16 | val enableSingleStep = in Bool 17 | 18 | // Trigger the next step for exactly one time 19 | val triggerStep = in Bool 20 | 21 | // Do a step (fetch the next instruction) 22 | val doStep = out Bool 23 | 24 | }.setName("") 25 | 26 | // Register the step mode 27 | val stepMode = RegNext(internal.enableSingleStep) init(False) 28 | 29 | // Check whether we in step mode and if we have a rising edge for the trigger 30 | internal.doStep := !stepMode || internal.triggerStep.rise(False) 31 | 32 | } 33 | -------------------------------------------------------------------------------- /vprj/vhdl/J1Sc/J1Sc/J1Sc.sim/sim_1/behav/xsim/webtalk.jou: -------------------------------------------------------------------------------- 1 | #----------------------------------------------------------- 2 | # Webtalk v2018.1 (64-bit) 3 | # SW Build 2188600 on Wed Apr 4 18:39:19 MDT 2018 4 | # IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 5 | # Start of session at: Fri May 4 01:49:58 2018 6 | # Process ID: 771 7 | # Current directory: /home/streit/src/scala/J1Sc/vprj/vhdl/J1Sc/J1Sc/J1Sc.sim/sim_1/behav/xsim 8 | # Command line: wbtcv -mode batch -source /home/streit/src/scala/J1Sc/vprj/vhdl/J1Sc/J1Sc/J1Sc.sim/sim_1/behav/xsim/xsim.dir/Board_Nexys4DDR_behav/webtalk/xsim_webtalk.tcl -notrace 9 | # Log file: /home/streit/src/scala/J1Sc/vprj/vhdl/J1Sc/J1Sc/J1Sc.sim/sim_1/behav/xsim/webtalk.log 10 | # Journal file: /home/streit/src/scala/J1Sc/vprj/vhdl/J1Sc/J1Sc/J1Sc.sim/sim_1/behav/xsim/webtalk.jou 11 | #----------------------------------------------------------- 12 | source /home/streit/src/scala/J1Sc/vprj/vhdl/J1Sc/J1Sc/J1Sc.sim/sim_1/behav/xsim/xsim.dir/Board_Nexys4DDR_behav/webtalk/xsim_webtalk.tcl -notrace 13 | -------------------------------------------------------------------------------- /vprj/vhdl/J1Sc/J1Sc/J1Sc.sim/sim_1/behav/xsim/webtalk_31943.backup.jou: -------------------------------------------------------------------------------- 1 | #----------------------------------------------------------- 2 | # Webtalk v2018.1 (64-bit) 3 | # SW Build 2188600 on Wed Apr 4 18:39:19 MDT 2018 4 | # IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 5 | # Start of session at: Fri May 4 01:47:59 2018 6 | # Process ID: 31943 7 | # Current directory: /home/streit/src/scala/J1Sc/vprj/vhdl/J1Sc/J1Sc/J1Sc.sim/sim_1/behav/xsim 8 | # Command line: wbtcv -mode batch -source /home/streit/src/scala/J1Sc/vprj/vhdl/J1Sc/J1Sc/J1Sc.sim/sim_1/behav/xsim/xsim.dir/Board_Nexys4DDR_behav/webtalk/xsim_webtalk.tcl -notrace 9 | # Log file: /home/streit/src/scala/J1Sc/vprj/vhdl/J1Sc/J1Sc/J1Sc.sim/sim_1/behav/xsim/webtalk.log 10 | # Journal file: /home/streit/src/scala/J1Sc/vprj/vhdl/J1Sc/J1Sc/J1Sc.sim/sim_1/behav/xsim/webtalk.jou 11 | #----------------------------------------------------------- 12 | source /home/streit/src/scala/J1Sc/vprj/vhdl/J1Sc/J1Sc/J1Sc.sim/sim_1/behav/xsim/xsim.dir/Board_Nexys4DDR_behav/webtalk/xsim_webtalk.tcl -notrace 13 | -------------------------------------------------------------------------------- /toolchain/forth/common/string.fs: -------------------------------------------------------------------------------- 1 | \ ####### STRING ########################################## 2 | 3 | : blank 4 | bl fill 5 | ; 6 | 7 | : -trailing 8 | begin 9 | 2dup + 1- c@ bl = 10 | over and 11 | while 12 | 1- 13 | repeat 14 | ; 15 | 16 | \ Search the string specified by c-addr1 u1 for the string 17 | \ specified by c-addr2 u2. If flag is true, a match was found 18 | \ at c-addr3 with u3 characters remaining. If flag is false 19 | \ there was no match and c-addr3 is c-addr1 and u3 is u1. 20 | 21 | : search ( c-addr1 u1 c-addr2 u2 -- c-addr3 u3 flag ) 22 | dup 0= if \ special-case zero-length search 23 | 2drop true exit 24 | then 25 | 26 | 2>r 2dup 27 | begin 28 | dup 29 | while 30 | 2dup 2r@ ( c-addr1 u1 c-addr2 u2 ) 31 | rot over min -rot ( c-addr1 min_u1_u2 c-addr2 u2 ) 32 | compare 0= if 33 | 2swap 2drop 2r> 2drop true exit 34 | then 35 | 1 /string 36 | repeat 37 | 2drop 2r> 2drop 38 | false 39 | ; 40 | -------------------------------------------------------------------------------- /toolchain/forth/demos/irqdemo.fs: -------------------------------------------------------------------------------- 1 | \ \ 2 | \ 3 | \ Author: Steffen Reith (Steffen.Reith@hs-rm.de) 4 | \ 5 | \ Creation Date: Sat Sep 9 16:21:25 GMT+2 2017 6 | \ Module Name: irqdemo - A simple demo of the interruptsystem of J1Sc 7 | \ Project Name: J1Sc - A simple J1 implementation in Scala using Spinal HDL 8 | \ 9 | \ \ 10 | 11 | : blink leds@ invert leds! ; 12 | 13 | : rotate16 14 | leds@ 15 | dup 16 | 1 and if 17 | 2/ 18 | $7fff and 19 | $8000 or 20 | else 21 | 2/ 22 | $7fff and 23 | then 24 | leds! 25 | ; 26 | 27 | : rotate8 28 | leds@ 29 | dup 30 | 1 and if 31 | 2/ 32 | $7f and 33 | $80 or 34 | else 35 | 2/ $7f and 36 | then 37 | leds! 38 | ; 39 | 40 | : isr rotate8 ; 41 | 42 | : iDemo \ Simple interrupt demo 43 | \ Init leds 44 | $80 leds! 45 | \ Set timerA to 250 * 2^16 ticks 46 | 0 ltA! 47 | 250 htA! 48 | \ Use word isr as isr for interrupt 1 49 | ['] isr 50 | 1 ivec! 51 | \ Enable interrupt 1 by setting the correct mask 52 | 2 imask! 53 | \ Start timerA 54 | entA 55 | ; 56 | -------------------------------------------------------------------------------- /vprj/vhdl/J1Sc/J1Sc/J1Sc.sim/sim_1/behav/xsim/webtalk.log: -------------------------------------------------------------------------------- 1 | #----------------------------------------------------------- 2 | # Webtalk v2018.1 (64-bit) 3 | # SW Build 2188600 on Wed Apr 4 18:39:19 MDT 2018 4 | # IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 5 | # Start of session at: Fri May 4 01:49:58 2018 6 | # Process ID: 771 7 | # Current directory: /home/streit/src/scala/J1Sc/vprj/vhdl/J1Sc/J1Sc/J1Sc.sim/sim_1/behav/xsim 8 | # Command line: wbtcv -mode batch -source /home/streit/src/scala/J1Sc/vprj/vhdl/J1Sc/J1Sc/J1Sc.sim/sim_1/behav/xsim/xsim.dir/Board_Nexys4DDR_behav/webtalk/xsim_webtalk.tcl -notrace 9 | # Log file: /home/streit/src/scala/J1Sc/vprj/vhdl/J1Sc/J1Sc/J1Sc.sim/sim_1/behav/xsim/webtalk.log 10 | # Journal file: /home/streit/src/scala/J1Sc/vprj/vhdl/J1Sc/J1Sc/J1Sc.sim/sim_1/behav/xsim/webtalk.jou 11 | #----------------------------------------------------------- 12 | source /home/streit/src/scala/J1Sc/vprj/vhdl/J1Sc/J1Sc/J1Sc.sim/sim_1/behav/xsim/xsim.dir/Board_Nexys4DDR_behav/webtalk/xsim_webtalk.tcl -notrace 13 | INFO: [Common 17-206] Exiting Webtalk at Fri May 4 01:49:58 2018... 14 | -------------------------------------------------------------------------------- /vprj/vhdl/J1Sc/J1Sc/J1Sc.sim/sim_1/behav/xsim/webtalk_31943.backup.log: -------------------------------------------------------------------------------- 1 | #----------------------------------------------------------- 2 | # Webtalk v2018.1 (64-bit) 3 | # SW Build 2188600 on Wed Apr 4 18:39:19 MDT 2018 4 | # IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018 5 | # Start of session at: Fri May 4 01:47:59 2018 6 | # Process ID: 31943 7 | # Current directory: /home/streit/src/scala/J1Sc/vprj/vhdl/J1Sc/J1Sc/J1Sc.sim/sim_1/behav/xsim 8 | # Command line: wbtcv -mode batch -source /home/streit/src/scala/J1Sc/vprj/vhdl/J1Sc/J1Sc/J1Sc.sim/sim_1/behav/xsim/xsim.dir/Board_Nexys4DDR_behav/webtalk/xsim_webtalk.tcl -notrace 9 | # Log file: /home/streit/src/scala/J1Sc/vprj/vhdl/J1Sc/J1Sc/J1Sc.sim/sim_1/behav/xsim/webtalk.log 10 | # Journal file: /home/streit/src/scala/J1Sc/vprj/vhdl/J1Sc/J1Sc/J1Sc.sim/sim_1/behav/xsim/webtalk.jou 11 | #----------------------------------------------------------- 12 | source /home/streit/src/scala/J1Sc/vprj/vhdl/J1Sc/J1Sc/J1Sc.sim/sim_1/behav/xsim/xsim.dir/Board_Nexys4DDR_behav/webtalk/xsim_webtalk.tcl -notrace 13 | INFO: [Common 17-206] Exiting Webtalk at Fri May 4 01:47:59 2018... 14 | -------------------------------------------------------------------------------- /toolchain/forth/common/structures.fs: -------------------------------------------------------------------------------- 1 | : begin-structure \ -- addr 0 ; -- size 2 | \ *G Begin definition of a new structure. Use in the form 3 | \ ** *\fo{BEGIN-STRUCTURE }. At run time *\fo{} 4 | \ ** returns the size of the structure. 5 | create 6 | here 0 0 , \ mark stack, lay dummy 7 | does> @ ; \ -- rec-len 8 | 9 | : end-structure \ addr n -- 10 | \ *G Terminate definition of a structure. 11 | swap ! ; \ set len 12 | 13 | : +FIELD \ n <"name"> -- ; Exec: addr -- 'addr 14 | \ *G Create a new field within a structure definition of size n bytes. 15 | create 16 | over , + 17 | does> 18 | @ + 19 | ; 20 | 21 | : cfield: \ n1 <"name"> -- n2 ; Exec: addr -- 'addr 22 | \ *G Create a new field within a structure definition of size 1 CHARS. 23 | 1 chars +FIELD 24 | ; 25 | 26 | : field: \ n1 <"name"> -- n2 ; Exec: addr -- 'addr 27 | \ *G Create a new field within a structure definition of size 1 CELLS. 28 | \ ** The field is ALIGNED. 29 | aligned 1 cells +FIELD 30 | ; 31 | 32 | : ffield: \ n1 <"name"> -- n2 ; Exec: addr -- 'addr 33 | \ *G Create a new field within a structure definition of size 1 FLOATS. 34 | \ ** The field is FALIGNED. 35 | faligned 1 floats +FIELD 36 | ; 37 | -------------------------------------------------------------------------------- /vprj/vhdl/J1Sc/J1Sc/J1Sc.sim/sim_1/behav/xsim/xsim.dir/Board_Nexys4DDR_behav/webtalk/usage_statistics_ext_xsim.wdm: -------------------------------------------------------------------------------- 1 | version = "1.0"; 2 | clients = 3 | ( 4 | { client_name = "project"; 5 | rules = ( 6 | { 7 | context="software_version_and_target_device"; 8 | xml_map="software_version_and_target_device"; 9 | html_map="software_version_and_target_device"; 10 | html_format="UserEnvStyle"; 11 | }, 12 | { 13 | context="user_environment"; 14 | xml_map="user_environment"; 15 | html_map="user_environment"; 16 | html_format="UserEnvStyle"; 17 | } 18 | ); 19 | }, 20 | 21 | { client_name = "xsim"; 22 | rules = ( 23 | { 24 | context="xsim\\command_line_options"; 25 | xml_map="xsim\\command_line_options"; 26 | html_map="xsim\\command_line_options"; 27 | html_format="UnisimStatsStyle"; 28 | }, 29 | { 30 | context="xsim\\usage"; 31 | xml_map="xsim\\usage"; 32 | html_map="xsim\\usage"; 33 | html_format="UnisimStatsStyle"; 34 | } 35 | ); 36 | } 37 | ); 38 | 39 | -------------------------------------------------------------------------------- /src/main/lattice/IceBreaker/J1Ice.pcf: -------------------------------------------------------------------------------- 1 | # External clock 2 | set_io --warn-no-port clk12Mhz 35 3 | 4 | # Use button UButton as reset 5 | set_io --warn-no-port nreset 10 6 | 7 | # Use button 3 as external interrupt 8 | set_io --warn-no-port extInt 18 9 | 10 | # Map button 1 and 2 as simple push buttons 11 | set_io --warn-no-port pButtons[0] 20 12 | set_io --warn-no-port pButtons[1] 19 13 | 14 | # The use the centered red led for pwm 15 | set_io --warn-no-port pwmLeds 26 16 | 17 | # Green leds 18 | set_io --warn-no-port leds[0] 27 19 | set_io --warn-no-port leds[1] 25 20 | set_io --warn-no-port leds[2] 23 21 | set_io --warn-no-port leds[3] 21 22 | 23 | # PmodA connected to PMOD1A 24 | set_io --warn-no-port pmodA[0] 4 25 | set_io --warn-no-port pmodA[1] 2 26 | set_io --warn-no-port pmodA[2] 47 27 | set_io --warn-no-port pmodA[3] 45 28 | set_io --warn-no-port pmodA[4] 44 29 | set_io --warn-no-port pmodA[5] 46 30 | set_io --warn-no-port pmodA[6] 48 31 | set_io --warn-no-port pmodA[7] 3 32 | 33 | # Connection to the UART 34 | set_io --warn-no-port rx 6 35 | set_io --warn-no-port tx 9 36 | 37 | # Indicator LED for UART 38 | set_io --warn-no-port uartLed 37 39 | 40 | # JTAG connected to PMOD1B (upper row) 41 | set_io --warn-no-port tck 43 42 | set_io --warn-no-port tdi 38 43 | set_io --warn-no-port tdo 34 44 | set_io --warn-no-port tms 31 45 | 46 | -------------------------------------------------------------------------------- /vprj/vhdl/J1Sc/J1Sc/J1Sc.sim/sim_1/behav/xsim/xsim.dir/Board_Nexys4DDR_behav/xsimSettings.ini: -------------------------------------------------------------------------------- 1 | [General] 2 | ARRAY_DISPLAY_LIMIT=1024 3 | RADIX=hex 4 | TIME_UNIT=ns 5 | TRACE_LIMIT=65536 6 | VHDL_ENTITY_SCOPE_FILTER=true 7 | VHDL_PACKAGE_SCOPE_FILTER=false 8 | VHDL_BLOCK_SCOPE_FILTER=true 9 | VHDL_PROCESS_SCOPE_FILTER=false 10 | VHDL_PROCEDURE_SCOPE_FILTER=false 11 | VERILOG_MODULE_SCOPE_FILTER=true 12 | VERILOG_PACKAGE_SCOPE_FILTER=false 13 | VERILOG_BLOCK_SCOPE_FILTER=false 14 | VERILOG_TASK_SCOPE_FILTER=false 15 | VERILOG_PROCESS_SCOPE_FILTER=false 16 | INPUT_OBJECT_FILTER=true 17 | OUTPUT_OBJECT_FILTER=true 18 | INOUT_OBJECT_FILTER=true 19 | INTERNAL_OBJECT_FILTER=true 20 | CONSTANT_OBJECT_FILTER=true 21 | VARIABLE_OBJECT_FILTER=true 22 | SCOPE_NAME_COLUMN_WIDTH=75 23 | SCOPE_DESIGN_UNIT_COLUMN_WIDTH=361 24 | SCOPE_BLOCK_TYPE_COLUMN_WIDTH=-1 25 | OBJECT_NAME_COLUMN_WIDTH=336 26 | OBJECT_VALUE_COLUMN_WIDTH=132 27 | OBJECT_DATA_TYPE_COLUMN_WIDTH=75 28 | PROCESS_NAME_COLUMN_WIDTH=75 29 | PROCESS_TYPE_COLUMN_WIDTH=75 30 | FRAME_INDEX_COLUMN_WIDTH=75 31 | FRAME_NAME_COLUMN_WIDTH=75 32 | FRAME_FILE_NAME_COLUMN_WIDTH=75 33 | FRAME_LINE_NUM_COLUMN_WIDTH=336 34 | LOCAL_NAME_COLUMN_WIDTH=132 35 | LOCAL_VALUE_COLUMN_WIDTH=75 36 | INPUT_LOCAL_FILTER=1 37 | OUTPUT_LOCAL_FILTER=1 38 | INOUT_LOCAL_FILTER=1 39 | INTERNAL_LOCAL_FILTER=1 40 | CONSTANT_LOCAL_FILTER=1 41 | VARIABLE_LOCAL_FILTER=1 42 | -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | .DS_Store 2 | **/.DS_Store 3 | log 4 | obj_dir/ 5 | build/ 6 | *.vcd 7 | .idea/ 8 | gen/ 9 | lib/ 10 | project/target 11 | target/ 12 | tmp/ 13 | simWorkspace/ 14 | tty0tty/module/.tmp_versions/tty0tty.mod 15 | tty0tty/module/.cache.mk 16 | tty0tty/module/.tty0tty.mod.cmd 17 | tty0tty/module/tty0tty.mod 18 | 19 | toolchain/forth/nuc.fs.orig 20 | vprj/vhdl/J1Sc/J1Sc.cache/ 21 | vprj/vhdl/J1Sc/J1Sc.hw/ 22 | vprj/vhdl/J1Sc/J1Sc.ip_user_files/ 23 | vprj/vhdl/J1Sc/J1Sc.runs/ 24 | vprj/vhdl/J1Sc/J1Sc.sim/ 25 | vprj/vhdl/J1Sc/J1Sc.srcs/ 26 | vprj/vhdl/J1Sc/J1Sc/J1Sc.cache/ 27 | vprj/vhdl/J1Sc/J1Sc/J1Sc.hw/ 28 | vprj/vhdl/J1Sc/J1Sc/J1Sc.ip_user_files/ 29 | vprj/vhdl/J1Sc/J1Sc/J1Sc.runs/ 30 | vprj/vhdl/J1Sc/J1Sc/J1Sc.sim/ 31 | vprj/vhdl/J1Sc/J1Sc/J1Sc.srcs/ 32 | vprj/vhdl/J1Sc/J1Sc/J1Sc.cache 33 | vprj/verilog/J1Sc/J1Sc.cache/ 34 | vprj/verilog/J1Sc/J1Sc.hw/ 35 | vprj/verilog/J1Sc/J1Sc.ip_user_files/ 36 | vprj/verilog/J1Sc/J1Sc.runs/ 37 | vprj/verilog/J1Sc/J1Sc.sim/ 38 | vprj/verilog/J1Sc/J1Sc.srcs/ 39 | toolchain/forth/shell/__pycache__/ 40 | toolchain/forth/shell/dpansf.pyc 41 | toolchain/forth/shell/swapforth.pyc 42 | J1Ico.v_toplevel_coreArea_cpu_mainMem_ramList_0.bin 43 | J1Ico.v_toplevel_coreArea_cpu_mainMem_ramList_1.bin 44 | J1Ice.v_toplevel_coreArea_cpu_mainMem_ramList_0.bin 45 | J1Ice.v_toplevel_coreArea_cpu_mainMem_ramList_1.bin 46 | verbose.log 47 | support/openocd/gen/jinfo 48 | 49 | -------------------------------------------------------------------------------- /toolchain/forth/common/double0.fs: -------------------------------------------------------------------------------- 1 | \ ####### DOUBLE low-level primmitives #################### 2 | 3 | : 2@ \ ( a -- lo hi ) 4 | dup cell+ @ swap @ 5 | ; 6 | 7 | : 2! \ ( lo hi a -- ) 8 | tuck ! 9 | cell+ ! 10 | ; 11 | 12 | : 2rot 13 | >r >r 2swap r> r> 2swap 14 | ; 15 | 16 | : 2literal 17 | swap postpone literal postpone literal 18 | ; immediate 19 | 20 | : dnegate 21 | invert swap invert swap 22 | 1. d+ 23 | ; 24 | 25 | : dabs 26 | dup 0< if dnegate then 27 | ; 28 | 29 | : s>d dup 0< ; 30 | : d>s drop ; 31 | 32 | : d= \ a b c d -- f ) 33 | >r \ a b c 34 | rot = \ b a=c 35 | swap r> = \ a=c b=d 36 | and 37 | ; 38 | 39 | : d< \ ( al ah bl bh -- flag ) 40 | rot \ al bl bh ah 41 | 2dup = 42 | if 43 | 2drop u< 44 | else 45 | > nip nip 46 | then 47 | ; 48 | 49 | : du< \ ( al ah bl bh -- flag ) 50 | rot \ al bl bh ah 51 | 2dup = 52 | if 53 | 2drop u< 54 | else 55 | u> nip nip 56 | then 57 | ; 58 | 59 | : d- 60 | dnegate d+ 61 | ; 62 | 63 | : d0< 64 | nip 0< 65 | ; 66 | 67 | : d0= 68 | or 0= 69 | ; 70 | 71 | : d2* 72 | 2dup d+ 73 | ; 74 | 75 | : d2/ 76 | >r 1 rshift r@ 77 | [ 8 cells 1- ] literal lshift 78 | or r> 2/ 79 | ; 80 | -------------------------------------------------------------------------------- /src/main/lattice/IcoBoard/J1Ico.pcf: -------------------------------------------------------------------------------- 1 | # External clock 2 | set_io --warn-no-port clk100Mhz R9 3 | 4 | # Use button S1 as reset 5 | set_io --warn-no-port reset K11 6 | 7 | # Use button S3 as external interrupt 8 | set_io --warn-no-port extInt P13 9 | 10 | # The IcoBoard has 3 LEDs on the PCB. Connect them via PWM 11 | set_io --warn-no-port pwmLeds[0] C8 12 | set_io --warn-no-port pwmLeds[1] F7 13 | set_io --warn-no-port pwmLeds[2] K9 14 | 15 | # Pmod8LD connected to P1 16 | set_io --warn-no-port leds[0] D8 17 | set_io --warn-no-port leds[1] B9 18 | set_io --warn-no-port leds[2] B10 19 | set_io --warn-no-port leds[3] B11 20 | set_io --warn-no-port leds[4] B8 21 | set_io --warn-no-port leds[5] A9 22 | set_io --warn-no-port leds[6] A10 23 | set_io --warn-no-port leds[7] A11 24 | 25 | # PmodA connected to P2 26 | set_io --warn-no-port pmodA[0] B4 27 | set_io --warn-no-port pmodA[1] C3 28 | set_io --warn-no-port pmodA[2] A2 29 | set_io --warn-no-port pmodA[3] A5 30 | set_io --warn-no-port pmodA[4] B5 31 | set_io --warn-no-port pmodA[5] B3 32 | set_io --warn-no-port pmodA[6] B6 33 | set_io --warn-no-port pmodA[7] B7 34 | 35 | # PmodUSBUART connected to P3 (upper row of P3) 36 | set_io --warn-no-port rx L7 37 | set_io --warn-no-port tx G5 38 | 39 | # JTAG connected to P4 (lower row of P4) 40 | set_io --warn-no-port tck T9 41 | set_io --warn-no-port tdi T10 42 | set_io --warn-no-port tdo T13 43 | set_io --warn-no-port tms R14 44 | 45 | -------------------------------------------------------------------------------- /support/openocd/command/progJ1: -------------------------------------------------------------------------------- 1 | echo "Stop J1 for upload" 2 | irscan J1Sc.cpu $_STALL_id 3 | drscan J1Sc.cpu $_STALL_width $_ocdTrue 4 | runtest 2 5 | 6 | echo "Open prog file" 7 | set fp [open ../../toolchain/forth/build/16bit/nuc.hex r] 8 | 9 | echo "Start programming" 10 | 11 | # Set address counter 12 | set adr 0 13 | 14 | # For all lines of file 15 | while {[gets $fp line] != -1} { 16 | 17 | # Debug message 18 | puts "Set value $line @ $adr" 19 | 20 | # Set word address 21 | irscan J1Sc.cpu $_SETADR_id 22 | drscan J1Sc.cpu $_SETADR_width $adr 23 | runtest 2 24 | 25 | # Set word data 26 | irscan J1Sc.cpu $_SETDATA_id 27 | drscan J1Sc.cpu $_SETDATA_width [expr 0x$line] 28 | runtest 2 29 | 30 | # Write to memory 31 | irscan J1Sc.cpu $_CAPTUREMEM_id 32 | drscan J1Sc.cpu $_CAPTUREMEM_width $_ocdTrue 33 | irscan J1Sc.cpu $_CAPTUREMEM_id 34 | drscan J1Sc.cpu $_CAPTUREMEM_width $_ocdFalse 35 | runtest 2 36 | 37 | # Next adr 38 | incr adr 39 | 40 | } 41 | 42 | echo "Programming done" 43 | 44 | echo "Activate Reset" 45 | irscan J1Sc.cpu $_RESET_id 46 | drscan J1Sc.cpu $_RESET_width $_ocdTrue 47 | runtest 2 48 | 49 | sleep 500 50 | 51 | echo "Deactive Reset" 52 | irscan J1Sc.cpu $_RESET_id 53 | drscan J1Sc.cpu $_RESET_width $_ocdFalse 54 | runtest 2 55 | 56 | sleep 500 57 | 58 | echo "Continue CPU" 59 | irscan J1Sc.cpu $_STALL_id 60 | drscan J1Sc.cpu $_STALL_width $_ocdFalse 61 | runtest 2 62 | 63 | -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | Copyright (c) 2017,2018,2019 Steffen Reith 2 | All rights reserved. 3 | 4 | Redistribution and use in source and binary forms, with or without 5 | modification, are permitted provided that the following conditions are met: 6 | 7 | * Redistributions of source code must retain the above copyright notice, this 8 | list of conditions and the following disclaimer. 9 | 10 | * Redistributions in binary form must reproduce the above copyright notice, 11 | this list of conditions and the following disclaimer in the documentation 12 | and/or other materials provided with the distribution. 13 | 14 | * Neither the name of J1Sc nor the names of its 15 | contributors may be used to endorse or promote products derived from 16 | this software without specific prior written permission. 17 | 18 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 21 | DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 22 | FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 | DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 24 | SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 25 | CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 26 | OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 27 | OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 | 29 | -------------------------------------------------------------------------------- /toolchain/forth/LICENSE: -------------------------------------------------------------------------------- 1 | Copyright (c) 2015, James Bowman 2 | All rights reserved. 3 | 4 | Redistribution and use in source and binary forms, with or without 5 | modification, are permitted provided that the following conditions are met: 6 | 7 | * Redistributions of source code must retain the above copyright notice, this 8 | list of conditions and the following disclaimer. 9 | 10 | * Redistributions in binary form must reproduce the above copyright notice, 11 | this list of conditions and the following disclaimer in the documentation 12 | and/or other materials provided with the distribution. 13 | 14 | * Neither the name of swapforth nor the names of its 15 | contributors may be used to endorse or promote products derived from 16 | this software without specific prior written permission. 17 | 18 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 21 | DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 22 | FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 | DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 24 | SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 25 | CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 26 | OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 27 | OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 | 29 | -------------------------------------------------------------------------------- /toolchain/forth/demos/factorials.fs: -------------------------------------------------------------------------------- 1 | \ Large factorials 2 | \ 3 | \ Original Jupiter Ace version by J Yale. 4 | \ "Practical Computing" September 1982, page 151. 5 | \ 6 | \ http://www.jupiter-ace.co.uk/Forth_general_PC8209p151.html 7 | \ 8 | \ Slightly modified for ANS Forth compliance, James Bowman 9 | \ 10 | \ This is an ANS Forth program: 11 | \ Requiring the Core Extensions word set 12 | \ 13 | 14 | \ : BYTE-ARRAY 15 | \ CREATE ALLOT 16 | \ DOES> + 17 | \ ; 18 | 19 | 1000 CONSTANT MAX-DIGITS 20 | 21 | \ MAX-DIGITS BYTE-ARRAY F-BUFF 22 | : F-BUFF pad + ; 23 | 24 | VARIABLE LAST 0 LAST ! ( Last buff element ) 25 | 26 | : *BUFF ( Multiplier ) 27 | 0 ( Carry ) 28 | LAST @ 1+ 0 29 | DO 30 | OVER I F-BUFF C@ 31 | * + 10 /MOD 32 | SWAP I F-BUFF C! 33 | LOOP 34 | BEGIN ( Extend buffer to accept final carry ) 35 | ?DUP 36 | WHILE 37 | 10 /MOD SWAP 38 | 1 LAST +! 39 | LAST @ DUP 1+ 40 | MAX-DIGITS > 41 | IF 42 | ." Out of buffer" abort 43 | THEN 44 | F-BUFF C! 45 | REPEAT 46 | DROP ; 47 | 48 | : SETUP 49 | 1 0 F-BUFF C! ( Start buff=1 ) 50 | 0 LAST ! ; 51 | 52 | : .FAC 53 | LAST @ 1+ 0 54 | DO 55 | LAST @ I - 56 | DUP 1+ 3 MOD 57 | 0= I 0= 0= AND 58 | IF 59 | [CHAR] , EMIT 60 | THEN 61 | F-BUFF C@ [CHAR] 0 + EMIT 62 | LOOP ; 63 | 64 | : FAC 65 | SETUP 1+ 1 66 | DO 67 | I *BUFF 68 | LOOP ; 69 | 70 | : FACS 71 | SETUP 1+ 1 72 | DO 73 | I *BUFF ." Factorial" 74 | I 3 U.R 75 | ." = " .FAC CR 76 | LOOP ; 77 | 78 | .( "20 FACS" gives:) cr 79 | \ 20 FACS 80 | 81 | .( and "100 FAC .FAC" gives:) cr 82 | \ 100 FAC .FAC 83 | -------------------------------------------------------------------------------- /vprj/vhdl/J1Sc/J1Sc/J1Sc.sim/sim_1/behav/xsim/compile.log: -------------------------------------------------------------------------------- 1 | INFO: [VRFC 10-163] Analyzing VHDL file "/home/streit/src/scala/J1Sc/vprj/vhdl/J1Sc/J1Sc/J1Sc.srcs/sources_1/imports/J1Sc/src/main/vhdl/arch/Nexys4DDR/PLL.vhd" into library work 2 | INFO: [VRFC 10-307] analyzing entity PLL 3 | INFO: [VRFC 10-163] Analyzing VHDL file "/home/streit/src/scala/J1Sc/vprj/vhdl/J1Sc/J1Sc/J1Sc.srcs/sources_1/imports/J1Sc/gen/src/vhdl/J1Nexys4X.vhd" into library work 4 | INFO: [VRFC 10-307] analyzing entity BufferCC 5 | INFO: [VRFC 10-307] analyzing entity J1Core 6 | INFO: [VRFC 10-307] analyzing entity MainMemory 7 | INFO: [VRFC 10-307] analyzing entity UartCtrlTx 8 | INFO: [VRFC 10-307] analyzing entity UartCtrlRx 9 | INFO: [VRFC 10-307] analyzing entity BufferCC_1 10 | INFO: [VRFC 10-307] analyzing entity BufferCC_2 11 | INFO: [VRFC 10-307] analyzing entity J1 12 | INFO: [VRFC 10-307] analyzing entity LEDArray 13 | INFO: [VRFC 10-307] analyzing entity PWM 14 | INFO: [VRFC 10-307] analyzing entity SSD 15 | INFO: [VRFC 10-307] analyzing entity GPIO 16 | INFO: [VRFC 10-307] analyzing entity DBPinArray 17 | INFO: [VRFC 10-307] analyzing entity DBPinArray_1 18 | INFO: [VRFC 10-307] analyzing entity Timer 19 | INFO: [VRFC 10-307] analyzing entity UartCtrl 20 | INFO: [VRFC 10-307] analyzing entity StreamFifo 21 | INFO: [VRFC 10-307] analyzing entity InterruptCtrl 22 | INFO: [VRFC 10-307] analyzing entity J1Nexys4X 23 | INFO: [VRFC 10-163] Analyzing VHDL file "/home/streit/src/scala/J1Sc/vprj/vhdl/J1Sc/J1Sc/J1Sc.srcs/sources_1/imports/J1Sc/src/main/vhdl/arch/Nexys4DDR/Board_Nexys4DDR.vhd" into library work 24 | INFO: [VRFC 10-307] analyzing entity Board_Nexys4DDR 25 | -------------------------------------------------------------------------------- /src/main/scala/J1Decoder.scala: -------------------------------------------------------------------------------- 1 | /* 2 | * Author: Steffen Reith (Steffen.Reith@hs-rm.de) 3 | * 4 | * Create Date: Sat Apr 11 13:56:45 CEST 2020 5 | * Module Name: J1Decoder - Decodes the current instruction to determine the dstack top for the next clock 6 | * Project Name: J1Sc - A simple J1 implementation in Scala using Spinal HDL 7 | * 8 | */ 9 | import spinal.core._ 10 | 11 | case class J1Decoder(cfg : J1Config) { 12 | 13 | def apply(pc : UInt, instr : Bits, dtos : Bits, dnos : Bits, aluResult : Bits) : Bits = { 14 | 15 | val dtosN = Bits(cfg.wordSize bits) 16 | 17 | // Instruction decoder 18 | switch (pc.msb ## instr(instr.high downto (instr.high - 3) + 1)) { 19 | 20 | // If there is a high call then push the instruction (== memory access) to the data stack 21 | is (M"1_---") { 22 | dtosN := instr 23 | } 24 | 25 | // Literal instruction (Push value) 26 | is (M"0_1--") { 27 | dtosN := instr(instr.high - 1 downto 0).resized 28 | } 29 | 30 | // Jump and call instruction (do not change dtos) 31 | is (M"0_000", M"0_010") { 32 | dtosN := dtos 33 | } 34 | 35 | // Conditional jump (pop a 0 at dtos by adjusting the dstack pointer) 36 | is (M"0_001") { 37 | dtosN := dnos 38 | } 39 | 40 | // Check for ALU operation 41 | is (M"0_011") { 42 | dtosN := aluResult 43 | } 44 | 45 | // Set all bits of top of stack to true by default 46 | default { 47 | dtosN := (default -> True) 48 | } 49 | 50 | } 51 | 52 | // Next top of data stack 53 | dtosN 54 | 55 | } 56 | 57 | } 58 | -------------------------------------------------------------------------------- /toolchain/forth/common/double.fs: -------------------------------------------------------------------------------- 1 | \ ####### DOUBLE ########################################## 2 | 3 | : 2variable 4 | create 2 cells allot 5 | ; 6 | 7 | : 2constant 8 | create , , 9 | does> 2@ 10 | ; 11 | 12 | : dmax 13 | 2over 2over d< if 14 | 2swap 15 | then 16 | 2drop 17 | ; 18 | 19 | : dmin 20 | 2over 2over d< invert if 21 | 2swap 22 | then 23 | 2drop 24 | ; 25 | 26 | : m+ s>d d+ ; 27 | 28 | : m* 29 | 2dup xor >r 30 | abs swap abs um* 31 | r> 0< if dnegate then 32 | ; 33 | 34 | \ From Wil Baden's "FPH Popular Extensions" 35 | \ http://www.wilbaden.com/neil_bawd/fphpop.txt 36 | 37 | : tnegate ( t . . -- -t . . ) 38 | >r 2dup or dup if drop dnegate 1 then 39 | r> + negate ; 40 | 41 | : t* ( d . n -- t . . ) 42 | ( d0 d1 n) 43 | 2dup xor >r ( r: sign) 44 | >r dabs r> abs 45 | 2>r ( d0)( r: sign d1 n) 46 | r@ um* 0 ( t0 d1 0) 47 | 2r> um* ( t0 d1 0 d1*n .)( r: sign) 48 | d+ ( t0 t1 t2) 49 | r> 0< if tnegate then ; 50 | 51 | : t/ ( t . . u -- d . ) 52 | ( t0 t1 t2 u) 53 | over >r >r ( t0 t1 t2)( r: t2 u) 54 | dup 0< if tnegate then 55 | r@ um/mod ( t0 rem d1) 56 | rot rot ( d1 t0 rem) 57 | r> um/mod ( d1 rem' d0)( r: t2) 58 | nip swap ( d0 d1) 59 | r> 0< if dnegate then ; 60 | 61 | : m*/ ( d . n u -- d . ) >r t* r> t/ ; 62 | 63 | -------------------------------------------------------------------------------- /toolchain/forth/common/core-ext.fs: -------------------------------------------------------------------------------- 1 | \ ####### CORE EXT ######################################## 2 | 3 | \ : source-id (source-id) @ ; 4 | 5 | : erase 0 fill ; 6 | 7 | : within over - >r - r> u< ; 8 | 9 | : .( 10 | [char] ) parse type 11 | ; immediate 12 | 13 | : find 14 | count sfind 15 | dup 0= if 16 | 2drop 1- 0 17 | then 18 | ; 19 | 20 | : [compile] 21 | ' compile, 22 | ; immediate 23 | 24 | create _ 80 allot \ The "temporary buffer" in ANS: A.11.6.1.2165 25 | 26 | : s" 27 | [char] " parse 28 | state @ if 29 | postpone sliteral 30 | else 31 | tuck _ swap cmove 32 | _ swap 33 | then 34 | ; immediate 35 | 36 | ( CASE JCB 09:15 07/18/14) 37 | \ From ANS specification A.3.2.3.2 38 | 39 | 0 constant case immediate ( init count of ofs ) 40 | 41 | : of ( #of -- orig #of+1 / x -- ) 42 | 1+ ( count ofs ) 43 | postpone over postpone = ( copy and test case value) 44 | postpone if ( add orig to control flow stack ) 45 | postpone drop ( discards case value if = ) 46 | swap ( bring count back now ) 47 | ; immediate 48 | 49 | : endof ( orig1 #of -- orig2 #of ) 50 | >r ( move off the stack in case the control-flow ) 51 | ( stack is the data stack. ) 52 | postpone else 53 | r> ( we can bring count back now ) 54 | ; immediate 55 | 56 | : endcase ( orig1..orign #of -- ) 57 | postpone drop ( discard case value ) 58 | begin 59 | dup 60 | while 61 | swap postpone then 1- 62 | repeat drop 63 | ; immediate 64 | 65 | : hex 66 | 16 base ! 67 | ; 68 | 69 | : save-input 70 | >in @ 1 71 | ; 72 | 73 | : restore-input 74 | drop >in ! 75 | true 76 | ; 77 | 78 | \ From ANS specification A.6.2.0970 79 | : convert 1+ 511 >number drop ; 80 | -------------------------------------------------------------------------------- /src/main/scala/DBPinArray.scala: -------------------------------------------------------------------------------- 1 | /* 2 | * Author: Steffen Reith (Steffen.Reith@hs-rm.de) 3 | * 4 | * Creation Date: Tue Oct 31 11:11:13 GMT+1 2017 5 | * Module Name: DBPinArray - Provides an array of debounced input pins 6 | * Project Name: J1Sc - A simple J1 implementation in Scala using Spinal HDL 7 | * 8 | */ 9 | 10 | import spinal.core._ 11 | import spinal.lib._ 12 | import spinal.lib.bus.misc.BusSlaveFactory 13 | 14 | class DBPinArray(j1Cfg : J1Config, 15 | dbPinArrayCfg : DBPinArrayConfig) extends Component { 16 | 17 | // Check the generic parameters 18 | assert(Bool(dbPinArrayCfg.numOfPins <= j1Cfg.wordSize), "Error: Too many pins in one array!", FAILURE) 19 | 20 | // Signals used for the internal bus 21 | val bus = new Bundle { 22 | 23 | // Debounced pins 24 | val dbPins = out Bits (j1Cfg.wordSize bits) 25 | 26 | } 27 | 28 | // Signals for a physical connection 29 | val io = new Bundle { 30 | 31 | // Physical input pins 32 | val inputPins = in Bits(dbPinArrayCfg.numOfPins bits) 33 | 34 | } 35 | 36 | // Create the register holding the debounced inputs 37 | val debounced = Reg(Bits(dbPinArrayCfg.numOfPins bits)) 38 | 39 | // Create an alarm timer for the timeout 40 | val timeOut = Timeout(dbPinArrayCfg.waitTime) 41 | 42 | // Clear the timeout if the input data has not changed 43 | when (debounced === io.inputPins) {timeOut.clear()} 44 | 45 | // When the alarm is active the new input is taken 46 | when (timeOut) {debounced := io.inputPins} 47 | 48 | // Clone the register holding the debounced input signals 49 | bus.dbPins := debounced.resize(j1Cfg.wordSize) 50 | 51 | // Implement the bus interface 52 | def driveFrom(busCtrl : BusSlaveFactory, baseAddress : BigInt) : Area = new Area { 53 | 54 | // A r/w register access for the ith interrupt vector 55 | busCtrl.read(bus.dbPins, baseAddress, bitOffset = 0) 56 | 57 | } 58 | 59 | } 60 | -------------------------------------------------------------------------------- /src/main/scala/J1JtagData.scala: -------------------------------------------------------------------------------- 1 | /* 2 | * Author: Steffen Reith (steffen.reith@hs-rm.de) 3 | * 4 | * Creation Date: Fri Jan 3 11:55:50 CET 2020 5 | * Module Name: J1JtagData - Contains a bundle of data provided by the jtag interface 6 | * Project Name: J1Sc - A simple J1 implementation in Scala using Spinal HDL 7 | * 8 | */ 9 | import spinal.core._ 10 | import spinal.lib.IMasterSlave 11 | 12 | case class J1JtagData(j1Cfg : J1Config) extends Bundle with IMasterSlave { 13 | 14 | // The data provided by the interface is valid 15 | val jtagDataValid = Bool 16 | 17 | // Indicate that the CPU has to halted 18 | val jtagStall = Bool 19 | 20 | // Indicate that the CPU memory is managed by the jtag interface 21 | val jtagCaptureMemory = Bool 22 | 23 | // Hold address and data for the CPU memory 24 | val jtagCPUAdr = Bits(j1Cfg.adrWidth bits) 25 | val jtagCPUWord = Bits(j1Cfg.wordSize bits) 26 | 27 | def init(adr : Int = 0, data : Int = 0) : J1JtagData = { 28 | 29 | // Make a clone 30 | val ret = cloneOf(this) 31 | 32 | // Init the bundle (deactivate stall, reset and capture memory) 33 | ret.jtagDataValid := False 34 | ret.jtagStall := False 35 | ret.jtagCaptureMemory := False 36 | ret.jtagCPUAdr := B(adr, j1Cfg.adrWidth bits) 37 | ret.jtagCPUWord := B(data, j1Cfg.wordSize bits) 38 | 39 | // Return the clone 40 | ret 41 | 42 | } 43 | 44 | // Clear the instance 45 | def clear() : Unit = { 46 | 47 | // Init all members 48 | this.jtagDataValid := False 49 | this.jtagStall := False 50 | this.jtagCaptureMemory := False 51 | this.jtagCPUAdr := B(0, j1Cfg.adrWidth bits) 52 | this.jtagCPUWord := B(0, j1Cfg.wordSize bits) 53 | 54 | } 55 | 56 | // Set the data directions when used as a master 57 | override def asMaster() : Unit = { 58 | 59 | // Write data to the bus 60 | out(jtagStall, jtagCaptureMemory, jtagCPUAdr, jtagCPUWord) 61 | 62 | } 63 | 64 | } 65 | -------------------------------------------------------------------------------- /src/main/scala/LEDArray.scala: -------------------------------------------------------------------------------- 1 | /* 2 | * Author: Steffen Reith (steffen.reith@hs-rm.de) 3 | * 4 | * Creation Date: Tue Nov 1 00:19:43 GMT+1 2016 5 | * Module Name: LEDBank - A simple LED bank 6 | * Project Name: J1Sc - A simple J1 implementation in Scala using Spinal HDL 7 | * 8 | */ 9 | import spinal.core._ 10 | import spinal.lib.bus.misc.BusSlaveFactory 11 | 12 | class LEDArray(j1Cfg : J1Config, 13 | ledCfg : LEDArrayConfig) extends Component { 14 | 15 | // Check the generic parameters 16 | assert(ledCfg.width <= j1Cfg.wordSize, message = "ERROR: Too many pwm channels!") 17 | 18 | val bus = new Bundle { 19 | 20 | // Bus signals for the internal register 21 | val writeEnable = in Bool 22 | val ledValue = in Bits (ledCfg.width bits) 23 | 24 | }.setName("") 25 | 26 | val io = new Bundle { 27 | 28 | // The physical led registers 29 | val leds = out Bits(ledCfg.width bits) 30 | 31 | }.setName("") 32 | 33 | // Register for holding the bit-vector storing the LED states 34 | val ledReg = Reg(Bits(ledCfg.width bits)) init (0) 35 | 36 | // Check for write mode 37 | when(bus.writeEnable) { 38 | 39 | // Set register value 40 | ledReg := bus.ledValue 41 | 42 | } 43 | 44 | // Set output for the leds (invert it if asked for by the generic parameter) 45 | if (ledCfg.lowActive) io.leds := ~ledReg else io.leds := ledReg 46 | 47 | // Implement the bus interface 48 | def driveFrom(busCtrl : BusSlaveFactory, baseAddress : BigInt) = new Area { 49 | 50 | // The register is mapped at address 0 and is of type r/w 51 | if (ledCfg.lowActive) { 52 | 53 | // Negate to get the register content 54 | busCtrl.read(~io.leds, baseAddress + 0, 0) 55 | 56 | } else { 57 | 58 | // Simply give back the register content 59 | busCtrl.read(io.leds, baseAddress + 0, 0) 60 | 61 | } 62 | busCtrl.nonStopWrite(bus.ledValue, 0) // ledState will be constantly driven by the data of the memory bus 63 | bus.writeEnable := busCtrl.isWriting(baseAddress + 0) 64 | 65 | } 66 | 67 | } 68 | -------------------------------------------------------------------------------- /toolchain/forth/shell.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python 2 | from __future__ import print_function 3 | 4 | import sys 5 | import time 6 | import array 7 | import os 8 | 9 | sys.path.append("shell") 10 | import swapforth 11 | 12 | class TetheredJ1a(swapforth.TetheredTarget): 13 | cellsize = 2 14 | 15 | def open_ser(self, port, speed): 16 | try: 17 | import serial 18 | except: 19 | print("This tool needs PySerial, but it was not found") 20 | sys.exit(1) 21 | self.ser = serial.Serial(port, 115200, timeout=None, rtscts=0) 22 | 23 | def reset(self, fullreset = True): 24 | ser = self.ser 25 | ser.setDTR(1) 26 | if fullreset: 27 | ser.setRTS(1) 28 | ser.setRTS(0) 29 | ser.setDTR(0) 30 | 31 | def waitcr(): 32 | while ser.read(1) != chr(10): 33 | pass 34 | 35 | waitcr() 36 | ser.write(b'\r') 37 | waitcr() 38 | 39 | for c in ' 1 tth !': 40 | ser.write(c.encode('utf-8')) 41 | ser.flush() 42 | time.sleep(0.001) 43 | ser.flushInput() 44 | # print("In: ", c, "Out: ", repr(ser.read(ser.inWaiting()))) 45 | ser.write(b'\r') 46 | 47 | while 1: 48 | c = ser.read(1) 49 | # print(repr(c)) 50 | if c == b'\x1e': 51 | break 52 | 53 | def boot(self, bootfile = None): 54 | sys.stdout.write('Contacting... ') 55 | self.reset() 56 | print('established') 57 | 58 | def interrupt(self): 59 | self.reset(False) 60 | 61 | def serialize(self): 62 | l = self.command_response('0 here dump') 63 | lines = l.strip().replace('\r', '').split('\n') 64 | s = [] 65 | for l in lines: 66 | l = l.split() 67 | s += [int(b, 16) for b in l[1:17]] 68 | s = array.array('B', s).tostring().ljust(8192, chr(0xff)) 69 | return array.array('H', s) 70 | 71 | if __name__ == '__main__': 72 | swapforth.main(TetheredJ1a) 73 | -------------------------------------------------------------------------------- /toolchain/forth/simshell.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python 2 | from __future__ import print_function 3 | 4 | import sys 5 | import time 6 | import array 7 | import os 8 | 9 | sys.path.append("shell") 10 | import swapforth 11 | 12 | class TetheredJ1a(swapforth.TetheredTarget): 13 | cellsize = 2 14 | 15 | def open_ser(self, port, speed): 16 | try: 17 | import serial 18 | except: 19 | print("This tool needs PySerial, but it was not found") 20 | sys.exit(1) 21 | self.ser = serial.Serial(port, 38400, timeout=None, rtscts=0) 22 | 23 | def reset(self, fullreset = True): 24 | ser = self.ser 25 | ser.setDTR(1) 26 | if fullreset: 27 | ser.setRTS(1) 28 | ser.setRTS(0) 29 | ser.setDTR(0) 30 | 31 | def waitcr(): 32 | while ser.read(1) != chr(10): 33 | pass 34 | 35 | waitcr() 36 | ser.write(b'\r') 37 | waitcr() 38 | 39 | for c in ' 1 tth !': 40 | ser.write(c.encode('utf-8')) 41 | ser.flush() 42 | time.sleep(0.001) 43 | ser.flushInput() 44 | #print("In: ", c, "Out: ", repr(ser.read(ser.inWaiting()))) 45 | ser.write(b'\r') 46 | 47 | while 1: 48 | c = ser.read(1) 49 | # print(repr(c)) 50 | if c == b'\x1e': 51 | break 52 | 53 | def boot(self, bootfile = None): 54 | sys.stdout.write('Contacting... ') 55 | self.reset() 56 | print('established') 57 | 58 | def interrupt(self): 59 | self.reset(False) 60 | 61 | def serialize(self): 62 | l = self.command_response('0 here dump') 63 | lines = l.strip().replace('\r', '').split('\n') 64 | s = [] 65 | for l in lines: 66 | l = l.split() 67 | s += [int(b, 16) for b in l[1:17]] 68 | s = array.array('B', s).tostring().ljust(8192, chr(0xff)) 69 | return array.array('H', s) 70 | 71 | if __name__ == '__main__': 72 | swapforth.main(TetheredJ1a) 73 | -------------------------------------------------------------------------------- /src/main/scala/J1RStack.scala: -------------------------------------------------------------------------------- 1 | /* 2 | * Author: Steffen Reith (Steffen.Reith@hs-rm.de) 3 | * 4 | * Create Date: Thu Jun 25 12:55:38 CEST 2020 5 | * Module Name: J1DStack - The return stack 6 | * Project Name: J1Sc - A simple J1 implementation in Scala using Spinal HDL 7 | * 8 | */ 9 | import spinal.core._ 10 | 11 | case class J1RStack(cfg : J1Config) extends J1Stack(cfg.dataStackIdxWidth) { 12 | 13 | def apply(stall : Bool, rtosN : Bits) : Bits = { 14 | 15 | // Change the stack pointer only when the CPU is not stalled 16 | when(!stall) { stackPtr := stackPtrN } 17 | 18 | // Return stack with write and read port 19 | val stackMem = Mem(Bits(cfg.wordSize bits), wordCount = (1 << cfg.returnStackIdxWidth)) 20 | stackMem.write(address = stackPtrN, 21 | data = rtosN, 22 | enable = stackWriteEnable & !stall) 23 | val rtos = stackMem.readAsync(address = stackPtr, readUnderWrite = writeFirst) 24 | 25 | // Return the top of stack 26 | rtos 27 | 28 | } 29 | 30 | def updateRStack(msb : Bool, instr : Bits, funcTtoR : Bool) : Unit = { 31 | 32 | // Increment for return stack pointer 33 | val stackPtrInc = SInt(cfg.returnStackIdxWidth bits) 34 | 35 | // Handle the update of the return stack 36 | switch(msb ## instr(instr.high downto (instr.high - 3) + 1)) { 37 | 38 | // When we do a high call (the msb of the PC is set) do a pop of return address 39 | is(M"1_---") {stackWriteEnable := False; stackPtrInc := -1} 40 | 41 | // Call instruction or interrupt (push return address to stack) 42 | is(M"0_010") {stackWriteEnable := True; stackPtrInc := 1} 43 | 44 | // Conditional jump (maybe we have to push) 45 | is(M"0_011") {stackWriteEnable := funcTtoR; stackPtrInc := instr(3 downto 2).asSInt.resized} 46 | 47 | // Don't change the return stack by default 48 | default {stackWriteEnable := False; stackPtrInc := 0} 49 | 50 | } 51 | 52 | // Update the return stack pointer 53 | stackPtrN := (stackPtr.asSInt + stackPtrInc).asUInt 54 | 55 | } 56 | 57 | } 58 | -------------------------------------------------------------------------------- /src/main/scala/J1Alu.scala: -------------------------------------------------------------------------------- 1 | /* 2 | * Author: Steffen Reith (Steffen.Reith@hs-rm.de) 3 | * 4 | * Create Date: Fri Apr 3 21:34:07 CEST 2020 5 | * Module Name: J1Alu - The ALU for J1Sc 6 | * Project Name: J1Sc - A simple J1 implementation in Scala using Spinal HDL 7 | * 8 | */ 9 | import spinal.core._ 10 | 11 | case class J1Alu(cfg : J1Config) { 12 | 13 | // Slice the ALU operation out of an instruction 14 | private def getALUOp(instr : Bits) = instr((instr.high - 4) downto ((instr.high - 8) + 1)) 15 | 16 | // Create and execute a ALU operation 17 | def apply(instr : Bits, dtos : Bits, dnos : Bits, dStackPtr : UInt, rtos : Bits, toRead : Bits) : Bits = { 18 | 19 | // Calculate difference (- dtos + dnos) and sign to be reused multiple times 20 | val difference = dnos.resize(cfg.wordSize + 1).asSInt - dtos.resize(cfg.wordSize + 1).asSInt 21 | val nosIsLess = (dtos.msb ^ dnos.msb) ? dnos.msb | difference.msb 22 | 23 | // Calculate the ALU result (mux all possible cases) 24 | getALUOp(instr).mux( 25 | 26 | B"0000" -> dtos, 27 | B"0001" -> dnos, 28 | 29 | // Arithmetic and logical operations 30 | B"0010" -> (dtos.asUInt + dnos.asUInt).asBits, 31 | B"1100" -> difference.resize(cfg.wordSize).asBits, 32 | B"0011" -> (dtos & dnos), 33 | B"0100" -> (dtos | dnos), 34 | B"0101" -> (dtos ^ dnos), 35 | B"0110" -> (~dtos), 36 | B"1001" -> (dtos(dtos.high) ## dtos(dtos.high downto 1).asUInt), 37 | B"1010" -> (dtos(dtos.high - 1 downto 0) ## B"b0"), 38 | 39 | // Push rtos to dtos 40 | B"1011" -> rtos, 41 | 42 | // Compare operations (equal, dtos > dnos, signed and unsigned) 43 | B"0111" -> B(cfg.wordSize bits, default -> (difference === 0)), 44 | B"1000" -> B(cfg.wordSize bits, default -> nosIsLess), 45 | B"1111" -> B(cfg.wordSize bits, default -> difference.msb), 46 | 47 | // Memory / IO read operations 48 | B"1101" -> toRead, 49 | 50 | // Misc operations (depth of dstack) 51 | B"1110" -> dStackPtr.resize(cfg.wordSize bits).asBits) 52 | 53 | } 54 | 55 | } 56 | -------------------------------------------------------------------------------- /support/e4thcom/swapforth-j1sc.efc: -------------------------------------------------------------------------------- 1 | e4thcom: 0.6.3 \ swapforth-j1sc.efc MM-180213 2 | \ ------------------------------------------------------------------------------ 3 | \ Plugin for SwapForth on J1Sc targets. Written for and tested by Steffen Reith. 4 | \ 5 | \ (C) 2018 manfred.mahlow@forth-ev.de 6 | \ 7 | \ ------------------------------------------------------------------------------ 8 | cr 9 | 10 | cr 11 | ." Use the " ." key to cancel an upload process." 12 | 13 | 14 | here bl c, char o c, char k c, ^CR c, ^NL c, 0 c, constant $_ok^CR^NL 15 | 16 | __e4thcom definitions decimal 17 | 18 | \ Protocol handler 19 | :noname ( oid -- flag ) \ stm8ef 20 | \ Wait while the target evalutes a line of uploaded source code. Return 21 | \ a true flag on error or if the [TAB] key was pressed. Otherwise return 22 | \ a false flag. 23 | >self self rx-buf erase white bright letters 24 | begin 25 | self rx?break ( c f ) if drop true exit then \ exit on break 26 | ( c ) dup self rx-buf append dup self ?emit 27 | dup ^NL = 28 | if 29 | drop $_ok^CR^NL 5 0 self rx-buf compare$ 0= if false exit then 30 | else 31 | [char] ? = 32 | if 33 | s" ?" 0 self rx-buf compare$ 0= 34 | if 35 | 500 self timeout ! self rx?timeout ( c f ) 36 | if drop cr true exit then ( c ) dup self rx-buf append self ?emit 37 | then 38 | then 39 | then 40 | again ; 41 | 42 | terminal plugin ! 43 | terminal upper-case off 44 | warning off 45 | 46 | \ Last Revision: MM-180213 Plugin created 47 | 48 | \\ 49 | 50 | Results of test file with e4thcom -t test option : 51 | 52 | drop|> ok^0D^0A 53 | 54 | cr|> ^0D^0A ok^0D^0A 55 | 56 | ' base drop|> ok^0D^0A 57 | 58 | ' x|> ? 59 | 60 | x|> ? 61 | 62 | quit|> 63 | 64 | abort|> ? 65 | 66 | 67 | Results of uploading code with e4thcom -t anyforth : 68 | 69 | : ['] ok 70 | ' postpone literal ok 71 | ; immediate ok 72 | 73 | 74 | : new ok 75 | s" | marker |" evaluate ? 76 | ; ok 77 | 78 | 79 | -------------------------------------------------------------------------------- /toolchain/forth/common/tools-ext.fs: -------------------------------------------------------------------------------- 1 | \ ####### TOOLS ########################################### 2 | 3 | : ? 4 | @ . 5 | ; 6 | 7 | : (.s) 8 | depth if 9 | >r recurse r> 10 | dup . 11 | then 12 | ; 13 | 14 | : .s 15 | [char] < emit depth 0 .r [char] > emit space 16 | (.s) 17 | ; 18 | 19 | : hex2. ( u -- ) 20 | base @ swap 21 | hex 22 | s>d <# # # #> type space 23 | base ! 24 | ; 25 | 26 | : dump 27 | ?dup 28 | if 29 | base @ >r hex 30 | 1- 4 rshift 1+ 31 | 0 do 32 | cr dup dup [ 2 cells ] literal u.r space space 33 | 16 0 do 34 | dup c@ hex2. 1+ 35 | loop 36 | space swap 37 | 16 0 do 38 | dup c@ 39 | dup bl 127 within invert 40 | if drop [char] . then 41 | emit 1+ 42 | loop 43 | drop 44 | loop 45 | r> base ! 46 | then 47 | drop 48 | ; 49 | 50 | \ ####### TOOLS EXT ####################################### 51 | 52 | \ From ANS specification A.15.6.2.2533 53 | \ Using PARSE-NAME instead of "BL WORD COUNT" 54 | 55 | : [ELSE] ( -- ) 56 | 1 begin \ level 57 | begin 58 | parse-name dup while \ level adr len 59 | 2dup s" [IF]" compare 0= 60 | if \ level adr len 61 | 2drop 1+ \ level' 62 | else \ level adr len 63 | 2dup s" [ELSE]" 64 | compare 0= if \ level adr len 65 | 2drop 1- dup if 1+ then \ level' 66 | else \ level adr len 67 | s" [THEN]" compare 0= if \ level 68 | 1- \ level' 69 | then 70 | then 71 | then ?dup 0= if exit then \ level' 72 | repeat 2drop \ level 73 | refill 0= until \ level 74 | drop 75 | ; immediate 76 | 77 | : [IF] ( flag -- ) 78 | 0= if postpone [ELSE] then ; immediate 79 | 80 | : [THEN] ( -- ) ; immediate 81 | 82 | : cs-pick pick ; 83 | : cs-roll roll ; 84 | 85 | : [defined] parse-name sfind nip 0<> ?dup and ; immediate 86 | : [undefined] postpone [defined] 0= ; immediate 87 | -------------------------------------------------------------------------------- /src/main/scala/J1Bus.scala: -------------------------------------------------------------------------------- 1 | /* 2 | * Author: Steffen Reith (steffen.reith@hs-rm.de) 3 | * 4 | * Creation Date: Sat Nov 12 15:36:19 GMT+1 2016 5 | * Module Name: JBus - A simple bus used for the components of the J1 ecosystem 6 | * Project Name: J1Sc - A simple J1 implementation in Scala using Spinal HDL 7 | * 8 | * Remark: Initial code provided by Charles Papon (charles.papon.90@gmail.com) 9 | * 10 | */ 11 | import spinal.core._ 12 | import spinal.lib._ 13 | 14 | case class J1Bus(cfg : J1Config) extends Bundle with IMasterSlave { 15 | 16 | // Width of addresses and data 17 | def adrWidth : Int = cfg.wordSize 18 | def dataWidth : Int = cfg.wordSize 19 | 20 | // Data and control signals used by 'SimpleBus' 21 | val enable = Bool // Bus can be used when 'enable' is high 22 | val writeMode = Bool // High to write data, low to read data 23 | val address = UInt(adrWidth bits) // Address (byte-aligned) 24 | val writeData = Bits(dataWidth bits) 25 | val readData = Bits(dataWidth bits) 26 | 27 | // Created a copy of the current bus which signals are delayed by 'delayCnt' ticks 28 | def delayIt(ticks : Int = 1) : J1Bus = { 29 | 30 | // Check for proper parameter 31 | require (ticks >= 0, "Error: ticks has to be at least 0") 32 | 33 | // Make a copy 34 | val retVal = cloneOf(this) 35 | 36 | // Don't delay the data to be read hence we have one wait state for a read operation 37 | this.readData := retVal.readData 38 | 39 | // Delay all other signals and wire them 40 | retVal.address := Delay(this.address, ticks) 41 | retVal.enable := Delay(this.enable, ticks) 42 | retVal.writeMode := Delay(this.writeMode, ticks) 43 | retVal.writeData := Delay(this.writeData, ticks) 44 | 45 | // Return the delayed version of the actual SimpleBus object 46 | retVal 47 | 48 | } 49 | 50 | // Methods to connect SimpleBus objects 51 | def << (that : J1Bus) : Unit = { 52 | 53 | // Simply wire the signals of 'this' and 'that' 54 | that.enable := this.enable 55 | that.writeMode := this.writeMode 56 | that.address := this.address 57 | that.writeData := this.writeData 58 | this.readData := that.readData 59 | 60 | } 61 | def >>(that : J1Bus) : Unit = that << this 62 | 63 | // Set the data directions when used as a master 64 | override def asMaster() : Unit = { 65 | 66 | // Write data to the bus 67 | out(enable, writeMode, address, writeData) 68 | 69 | // Read data from the bus 70 | in(readData) 71 | 72 | } 73 | 74 | } 75 | -------------------------------------------------------------------------------- /src/main/scala/J1DStack.scala: -------------------------------------------------------------------------------- 1 | /* 2 | * Author: Steffen Reith (Steffen.Reith@hs-rm.de) 3 | * 4 | * Create Date: Fri Jun 19 10:19:44 CEST 2020 5 | * Module Name: J1DStack - The data stack 6 | * Project Name: J1Sc - A simple J1 implementation in Scala using Spinal HDL 7 | * 8 | */ 9 | import spinal.core._ 10 | 11 | case class J1DStack(cfg : J1Config) extends J1Stack(cfg.dataStackIdxWidth) { 12 | 13 | // Enable signal for writing to the stack 14 | //override val stackWriteEnable = Bool 15 | 16 | // Stack pointer and next signal for the data stack 17 | //val stackPtrN = UInt(cfg.dataStackIdxWidth bits) 18 | //val stackPtr = Reg(UInt(cfg.dataStackIdxWidth bits)) init (0) 19 | 20 | def apply(stall : Bool, dtosN : Bits) : (Bits, Bits, UInt) = { 21 | 22 | // Change the stack pointer only when the CPU is not stalled 23 | when(!stall) { stackPtr := stackPtrN } 24 | 25 | // Top of stack and next value 26 | val dtos = RegNext(dtosN) init(0) 27 | 28 | // Stack memory with read and write port 29 | val stackMem = Mem(Bits(cfg.wordSize bits), wordCount = (1 << cfg.dataStackIdxWidth)) 30 | stackMem.write(address = stackPtrN, 31 | data = dtos, 32 | enable = stackWriteEnable & !stall) 33 | val dnos = stackMem.readAsync(address = stackPtr, readUnderWrite = writeFirst) 34 | 35 | // Return top and next of stack as a pair and the dstack pointer 36 | (dtos, dnos, stackPtr) 37 | 38 | } 39 | 40 | def updateDStack(msb : Bool, instr : Bits, funcTtoN : Bool) : Unit = { 41 | 42 | // Increment for data stack pointer 43 | val stackPtrInc = SInt(cfg.dataStackIdxWidth bits) 44 | 45 | // Handle the update of the data stack 46 | switch(msb ## instr(instr.high downto (instr.high - 3) + 1)) { 47 | 48 | // For a high call push the instruction (== memory access) and for a literal push the value to the data stack 49 | is (M"1_---", M"0_1--") {stackWriteEnable := True; stackPtrInc := 1} 50 | 51 | // Conditional jump (pop DTOS from data stack) 52 | is (M"0_001") {stackWriteEnable := False; stackPtrInc := -1} 53 | 54 | // ALU instruction (check for a possible push of data, ISA bug can be fixed by '| (instr(1 downto 0) === B"b01")') 55 | is (M"0_011") {stackWriteEnable := funcTtoN; stackPtrInc := instr(1 downto 0).asSInt.resized} 56 | 57 | // Don't change the data stack by default 58 | default {stackWriteEnable := False; stackPtrInc := 0} 59 | 60 | } 61 | 62 | // Calculate the new value of the data stack pointer 63 | stackPtrN := (stackPtr.asSInt + stackPtrInc).asUInt 64 | 65 | } 66 | 67 | } 68 | -------------------------------------------------------------------------------- /src/main/verilog/arch/IcoBoard/Board_IcoBoard.v: -------------------------------------------------------------------------------- 1 | // 2 | // Author: Steffen Reith (steffen.reith@hs-rm.de) 3 | // 4 | // Creation Date: Mon Nov 20 10:49:12 CET 2017 5 | // Module Name: Board_Nexys4 - Behavioral 6 | // Project Name: J1Sc - A simple J1 implementation in Scala using Spinal HDL 7 | // 8 | // 9 | 10 | module IcoBoard (reset, 11 | clk100Mhz, 12 | extInt, 13 | leds, 14 | pwmLeds, 15 | pmodA, 16 | tck, 17 | tms, 18 | tdi, 19 | tdo, 20 | rx, 21 | tx); 22 | 23 | // Input ports 24 | input reset; 25 | input clk100Mhz; 26 | input [0:0] extInt; 27 | input rx; 28 | input tck; 29 | input tms; 30 | input tdi; 31 | 32 | // Output ports 33 | output [7:0] leds; 34 | output [2:0] pwmLeds; 35 | output tx; 36 | output tdo; 37 | 38 | // Bidirectional port 39 | inout [7:0] pmodA; 40 | 41 | // Clock generation 42 | wire boardClk; 43 | wire boardClkLocked; 44 | 45 | // Internal wiring 46 | wire [7:0] pmodA_read; 47 | wire [7:0] pmodA_write; 48 | wire [7:0] pmodA_writeEnable; 49 | 50 | // Instantiate a PLL/MMCM (makes a 25Mhz clock) 51 | PLL makeClk (.clkIn (clk100Mhz), 52 | .clkOut (boardClk), 53 | .isLocked (boardClkLocked)); 54 | 55 | // Instantiate the J1SoC core generated by Spinal 56 | J1Ico core (.reset (reset), 57 | .boardClk (boardClk), 58 | .boardClkLocked (boardClkLocked), 59 | .extInt (extInt), 60 | .leds (leds), 61 | .pwmLeds (pwmLeds), 62 | .tck (tck), 63 | .tms (tms), 64 | .tdi (tdi), 65 | .tdo (tdo), 66 | .pmodA_read (pmodA_read), 67 | .pmodA_write (pmodA_write), 68 | .pmodA_writeEnable (pmodA_writeEnable), 69 | .rx (rx), 70 | .tx (tx)); 71 | 72 | // Generate the write port and equip it with tristate functionality 73 | genvar i; 74 | generate 75 | for (i = 0; i < 8; i = i + 1) begin 76 | 77 | // Instantiate the ith tristate buffer 78 | SB_IO #(.PIN_TYPE(6'b 1010_01), 79 | .PULLUP(1'b 0) 80 | ) iobuf ( 81 | .PACKAGE_PIN(pmodA[i]), 82 | .OUTPUT_ENABLE(pmodA_writeEnable[i]), 83 | .D_OUT_0(pmodA_write[i]), 84 | .D_IN_0(pmodA_read[i])); 85 | end 86 | endgenerate 87 | 88 | endmodule 89 | 90 | -------------------------------------------------------------------------------- /src/main/verilog/arch/IceBreaker/Board_IceBreaker.v: -------------------------------------------------------------------------------- 1 | // 2 | // Author: Steffen Reith (steffen.reith@hs-rm.de) 3 | // 4 | // Creation Date: Fri Feb 15 20:53:58 CET 2019 5 | // Module Name: Board_IceBreaker - Behavioral 6 | // Project Name: J1Sc - A simple J1 implementation in Scala using Spinal HDL 7 | // 8 | // 9 | 10 | module IceBreaker (nreset, 11 | clk12Mhz, 12 | extInt, 13 | leds, 14 | pwmLeds, 15 | pButtons, 16 | pmodA, 17 | rx, 18 | tx, 19 | uartLed); 20 | 21 | // Input ports 22 | input nreset; 23 | input clk12Mhz; 24 | input [0:0] extInt; 25 | input [1:0] pButtons; 26 | input rx; 27 | 28 | // Output ports 29 | output [3:0] leds; 30 | output [0:0] pwmLeds; 31 | output tx; 32 | output uartLed; 33 | 34 | // Bidirectional port 35 | inout [7:0] pmodA; 36 | 37 | // Clock generation 38 | wire boardClk; 39 | wire boardClkLocked; 40 | 41 | // Internal wiring 42 | wire [7:0] pmodA_read; 43 | wire [7:0] pmodA_write; 44 | wire [7:0] pmodA_writeEnable; 45 | 46 | // Internal wire for reset 47 | wire reset; 48 | 49 | // Instantiate a PLL to make a 18Mhz clock 50 | PLL makeClk (.clkIn (clk12Mhz), 51 | .clkOut (boardClk), 52 | .isLocked (boardClkLocked)); 53 | 54 | // Instantiate the J1SoC core generated by Spinal 55 | J1Ice core (.reset (reset), 56 | .boardClk (boardClk), 57 | .boardClkLocked (boardClkLocked), 58 | .extInt (extInt), 59 | .leds (leds), 60 | .pwmLeds (pwmLeds), 61 | .pButtons (pButtons), 62 | .pmodA_read (pmodA_read), 63 | .pmodA_write (pmodA_write), 64 | .pmodA_writeEnable (pmodA_writeEnable), 65 | .rx (rx), 66 | .tx (tx), 67 | .uartLed (uartLed)); 68 | 69 | // Invert the negative reset 70 | assign reset = !nreset; 71 | 72 | // Generate the write port and equip it with tristate functionality 73 | genvar i; 74 | generate 75 | for (i = 0; i < 8; i = i + 1) begin 76 | 77 | // Instantiate the ith tristate buffer 78 | SB_IO #(.PIN_TYPE(6'b 1010_01), 79 | .PULLUP(1'b 0) 80 | ) iobuf ( 81 | .PACKAGE_PIN(pmodA[i]), 82 | .OUTPUT_ENABLE(pmodA_writeEnable[i]), 83 | .D_OUT_0(pmodA_write[i]), 84 | .D_IN_0(pmodA_read[i])); 85 | end 86 | endgenerate 87 | 88 | endmodule 89 | 90 | -------------------------------------------------------------------------------- /toolchain/forth/common/file.fs: -------------------------------------------------------------------------------- 1 | 0 value fib 2 | 3 | : refill 4 | source-id 0> if 5 | fib 256 source-id read-line throw 6 | if 7 | fib swap tosource 8 | >in off 9 | true 10 | else 11 | drop false 12 | then 13 | else 14 | refill 15 | then 16 | ; 17 | 18 | : include-file ( fileid -- ) 19 | fib >r 20 | 256 allocate throw to fib 21 | source 2>r 22 | >in @ >r 23 | source-id >r 24 | \ Store fileid in SOURCE-ID. 25 | \ Make the file specified by fileid the input source. 26 | \ Store zero in BLK. 27 | 28 | (source-id) ! 29 | 1 >r 30 | begin 31 | fib 256 (source-id) @ read-line throw 32 | while 33 | fib swap tosource 34 | >in off 35 | ['] interpret catch 36 | \ cr .s [char] | emit source type 37 | ?dup if 38 | \ produce a friendly error message 39 | \ XXX - how to generate filename? 40 | \ XXX - should try to match a vim errorformat 41 | decimal 42 | cr ." At line " r@ u. ." column " >inwas @ u. 43 | cr source type 44 | throw 45 | then 46 | r> 1+ >r 47 | repeat 48 | r> 2drop 49 | (source-id) @ close-file throw 50 | 51 | r> (source-id) ! 52 | r> >in ! 53 | 2r> tosource 54 | fib free throw 55 | r> to fib 56 | ; 57 | 58 | : included ( c-addr u -- ) 59 | r/o open-file throw 60 | include-file 61 | ; 62 | 63 | : include ( "filename" -- ) 64 | parse-name included decimal 65 | ; 66 | 67 | \ ####### TOOLS EXT ####################################### 68 | 69 | ( [IF] [ELSE] [THEN] JCB 10:59 07/18/14) 70 | \ From ANS specification A.15.6.2.2533 71 | 72 | : [ELSE] ( -- ) 73 | 1 BEGIN \ level 74 | BEGIN 75 | BL WORD COUNT DUP WHILE \ level adr len 76 | 2DUP S" [IF]" COMPARE 0= 77 | IF \ level adr len 78 | 2DROP 1+ \ level' 79 | ELSE \ level adr len 80 | 2DUP S" [ELSE]" 81 | COMPARE 0= IF \ level adr len 82 | 2DROP 1- DUP IF 1+ THEN \ level' 83 | ELSE \ level adr len 84 | S" [THEN]" COMPARE 0= IF \ level 85 | 1- \ level' 86 | THEN 87 | THEN 88 | THEN ?DUP 0= IF EXIT THEN \ level' 89 | REPEAT 2DROP \ level 90 | REFILL 0= UNTIL \ level 91 | DROP 92 | ; IMMEDIATE 93 | 94 | : [IF] ( flag -- ) 95 | 0= IF POSTPONE [ELSE] THEN ; IMMEDIATE 96 | 97 | : [THEN] ( -- ) ; IMMEDIATE 98 | -------------------------------------------------------------------------------- /src/main/scala/J1PC.scala: -------------------------------------------------------------------------------- 1 | /* 2 | * Author: Steffen Reith (Steffen.Reith@hs-rm.de) 3 | * 4 | * Create Date: Fr 10. Apr 12:02:44 CEST 2020 5 | * Module Name: J1PCNext - Update logic for the program counter 6 | * Project Name: J1Sc - A simple J1 implementation in Scala using Spinal HDL 7 | * 8 | */ 9 | import spinal.core._ 10 | 11 | case class J1PC(cfg : J1Config) { 12 | 13 | // Program counter (note that the MSB is used to control dstack and rstack, hence make is one bit larger) 14 | val pc = Reg(UInt(cfg.adrWidth + 1 bits)) init(cfg.startAddress) 15 | val pcPlusOne = UInt(cfg.adrWidth + 1 bits) 16 | 17 | def apply(pcN : UInt, clrActive : Bool, irq : Bool) : (UInt, Bits) = { 18 | 19 | // Update the PC if no synchronous reset is active 20 | when(!clrActive) {pc := pcN} 21 | pcPlusOne := pc + 1 22 | 23 | // Check for interrupt mode, because afterwards the current instruction has to be executed 24 | val returnPC = Mux(irq, pc.asBits, pcPlusOne.asBits) 25 | 26 | // Return the new program counter 27 | (pc, returnPC) 28 | 29 | } 30 | 31 | def updatePC(stall : Bool, clrActive : Bool, instr : Bits, dtos : Bits, rtos : Bits) : UInt = { 32 | 33 | // The signal for the next pc value 34 | val pcN = UInt(cfg.adrWidth + 1 bits) 35 | 36 | // Handle the PC (remember cfg.adrWidth - 1 is the high indicator and instr(7) is the R -> PC field) 37 | switch(stall ## // CPU stalled 38 | clrActive ## // Check for reset state 39 | pc.msb ## // Used to check for high jumps 40 | instr(instr.high downto (instr.high - 3) + 1) ## // Holds information about jumps and relevant ALU instructions 41 | instr(7) ## // The R -> PC field in ALU instructions 42 | dtos.orR) { // Jump if dtos is zero 43 | 44 | // Don't change the PC in stall mode 45 | is (M"1_-_-_---_-_-") { 46 | pcN := pc 47 | } 48 | 49 | // Check if we are in reset state 50 | is (M"0_1_-_---_-_-") { 51 | pcN := cfg.startAddress 52 | } 53 | 54 | // Check for jump, call instruction or conditional jump 55 | is (M"0_0_0_000_-_-", M"0_0_0_010_-_-", M"0_0_0_001_-_0") { 56 | pcN := instr(cfg.adrWidth downto 0).asUInt 57 | } 58 | 59 | // Check either for a high call or R -> PC field of an ALU instruction and load PC from return stack 60 | is (M"0_0_1_---_-_-", M"0_0_0_011_1_-") { 61 | pcN := rtos(cfg.adrWidth + 1 downto 1).asUInt 62 | } 63 | 64 | // By default goto next instruction 65 | default { 66 | pcN := pcPlusOne 67 | } 68 | 69 | } 70 | 71 | // The program counter for the next clock 72 | pcN 73 | 74 | } 75 | 76 | } 77 | -------------------------------------------------------------------------------- /src/main/scala/GPIO.scala: -------------------------------------------------------------------------------- 1 | /* 2 | * Author: Steffen Reith (Steffen.Reith@hs-rm.de) 3 | * 4 | * Creation Date: Sun Mar 12 00:53:59 GMT+1 2017 5 | * Module Name: PMod - An interface to a Digilent PMOD interface 6 | * Project Name: J1Sc - A simple J1 implementation in Scala using Spinal HDL 7 | * 8 | */ 9 | import spinal.core._ 10 | import spinal.lib.bus.misc.BusSlaveFactory 11 | 12 | class GPIO(gpioCfg : GPIOConfig) extends Component { 13 | 14 | // Check for the typical PMOD width 15 | if (gpioCfg.width != 8) { 16 | 17 | // Give a warning 18 | println("[J1Sc] WARNING: A PMod according to the digilent specification has width 8!") 19 | 20 | } 21 | 22 | // Signals used for the internal bus 23 | val bus = new Bundle { 24 | 25 | // Ports used for the direction register 26 | val dirEnable = in Bool 27 | val dirValue = in Bits (gpioCfg.width bits) 28 | 29 | // Ports used the the data register 30 | val dataEnable = in Bool 31 | val dataValue = in Bits (gpioCfg.width bits) 32 | 33 | }.setName("") 34 | 35 | // Physically connected signals 36 | val io = new Bundle { 37 | 38 | val directions = out Bits(gpioCfg.width bits) 39 | val dataIn = in Bits(gpioCfg.width bits) 40 | val dataOut = out Bits(gpioCfg.width bits) 41 | 42 | }.setName("") 43 | 44 | // Register for holding the direction of the GPIO register 45 | val dirReg = RegNextWhen(bus.dirValue, bus.dirEnable) init (0) 46 | 47 | // Propagate the contents of the direction register to the interface 48 | io.directions := dirReg 49 | 50 | // Register for holding the IO data 51 | val dataRegN = Bits(gpioCfg.width bits) 52 | val dataReg = RegNext(dataRegN) init(0) 53 | 54 | // Check if the register was addressed by a bus transfer 55 | when (bus.dataEnable) { 56 | 57 | // Select and update the bits to be read / written 58 | dataRegN := (io.dataIn & (~io.directions)) | (bus.dataValue & io.directions) 59 | 60 | }.otherwise { 61 | 62 | // Update only bits to be read 63 | dataRegN := dataReg | (io.dataIn & (~io.directions)) 64 | 65 | } 66 | 67 | // Propagate the contents of the data register to the interface 68 | io.dataOut := dataReg 69 | 70 | // Implement the bus interface 71 | def driveFrom(busCtrl : BusSlaveFactory, baseAddress : BigInt) : Area = new Area { 72 | 73 | // The direction register is mapped at address 0 and is of type r/w 74 | busCtrl.read(io.directions, baseAddress + 0, bitOffset = 0) 75 | busCtrl.nonStopWrite(bus.dirValue, bitOffset = 0) // contents of direction register will be constantly driven by the bus 76 | bus.dirEnable := busCtrl.isWriting(baseAddress + 0) 77 | 78 | // The data register is mapped at address 4 and is of type r/w 79 | busCtrl.read(io.dataOut, baseAddress + 4, bitOffset = 0) 80 | busCtrl.nonStopWrite(bus.dataValue, bitOffset = 0) // contents of direction register will be constantly driven by the bus 81 | bus.dataEnable := busCtrl.isWriting(baseAddress + 4) 82 | 83 | } 84 | 85 | } 86 | -------------------------------------------------------------------------------- /src/main/scala/J1BusSlaveFactory.scala: -------------------------------------------------------------------------------- 1 | /* 2 | * Author: Steffen Reith (steffen.reith@hs-rm.de) 3 | * 4 | * Creation Date: Sat Nov 25 11:43:36 GMT+1 2017 5 | * Module Name: JBusSlaveFactory - Creates a slave factory of the JBus 6 | * Project Name: J1Sc - A simple J1 implementation in Scala using Spinal HDL 7 | * 8 | * Remark: Initial code provided by Charles Papon (charles.papon.90@gmail.com) 9 | * 10 | */ 11 | import spinal.core._ 12 | import spinal.lib.bus.misc._ 13 | 14 | object J1BusSlaveFactory { 15 | 16 | // Make a factory for the JBus 17 | def apply(bus : J1Bus) = new J1BusSlaveFactory(bus) 18 | 19 | } 20 | 21 | class J1BusSlaveFactory(bus : J1Bus) extends BusSlaveFactoryDelayed { 22 | 23 | // Get read/write address used on the bus 24 | def readAddress() : UInt = bus.address 25 | def writeAddress() : UInt = bus.address 26 | 27 | // Peripherals cannot stop bus cycles 28 | def readHalt() : Unit = throw new Exception("Unsupported feature") 29 | def writeHalt() : Unit = throw new Exception("Unsupported feature") 30 | 31 | // Ask for read/write access 32 | val askWrite = bus.enable && bus.writeMode 33 | val askRead = bus.enable && !bus.writeMode 34 | 35 | // Simple bus has no halting signal, hence do read/write means ask for read/write 36 | def doWrite = askWrite 37 | def doRead = askRead 38 | 39 | // Tell the width of the data bus 40 | override def busDataWidth : Int = bus.dataWidth 41 | 42 | // Build the bridging logic between master and slave 43 | override def build() : Unit = { 44 | 45 | // Init the read data wire to avoid a latch 46 | bus.readData := 0 47 | 48 | // Write permanently to the bus 49 | super.doNonStopWrite(bus.writeData) 50 | 51 | // Describe one data package transfered on the bus 52 | def doMappedElements(jobs : Seq[BusSlaveFactoryElement]) : Unit = super.doMappedElements ( 53 | 54 | // Do the mapping of all bus signals 55 | jobs = jobs, 56 | askWrite = askWrite, 57 | askRead = askRead, 58 | doWrite = doWrite, 59 | doRead = doRead, 60 | writeData = bus.writeData, 61 | readData = bus.readData 62 | 63 | ) 64 | 65 | // Check the current address on the bus (address decoder) 66 | switch(bus.address) { 67 | 68 | // For all jobs (e.g. registers) having a single address 69 | for ((address, jobs) <- elementsPerAddress if address.isInstanceOf[SingleMapping]) { 70 | 71 | is(address.asInstanceOf[SingleMapping].address) { 72 | 73 | // Wire the single address object to the bus 74 | doMappedElements(jobs) 75 | 76 | } 77 | 78 | } 79 | 80 | } 81 | 82 | // For all addresses that are not a single address (but a range) like RAMs etc. 83 | for ((address, jobs) <- elementsPerAddress if !address.isInstanceOf[SingleMapping]) { 84 | 85 | // Check if the current address on the bus is in the range 86 | when(address.hit(bus.address)) { 87 | 88 | // Handle the job by wiring the actual device to the bus 89 | doMappedElements(jobs) 90 | 91 | } 92 | 93 | } 94 | 95 | } 96 | 97 | } 98 | -------------------------------------------------------------------------------- /src/test/vhdl/J1Nexys4X_IRQ_tb.vhd: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- 2 | -- Author: Steffen Reith (Steffen.Reith@hs-rm.de) 3 | -- 4 | -- Creation Date: Sun Dec 11 11:46:48 GMT+1 2016 5 | -- Creator: Steffen Reith 6 | -- Module Name: J1SoC_IRQ_TB - A simple testbench for testing the interrupts 7 | -- of the J1 SoC 8 | -- Project Name: J1Sc - A simple J1 implementation in scala 9 | -- 10 | -------------------------------------------------------------------------------- 11 | library ieee; 12 | use ieee.std_logic_1164.all; 13 | use ieee.numeric_std.all; 14 | 15 | library std; 16 | use std.textio.all; 17 | 18 | entity J1Nexys4X_IRQ_tb is 19 | end J1Nexys4X_IRQ_tb; 20 | 21 | architecture Behavioral of J1Nexys4X_IRQ_tb is 22 | 23 | -- Clock period definition (100Mhz) 24 | constant clk_period : time := 10 ns; 25 | 26 | -- Interrupts 27 | signal extInt : std_logic_vector(0 downto 0) := "0"; 28 | 29 | -- PModA-Interface 30 | signal pmodA_read : std_logic_vector(7 downto 0); 31 | signal pmodA_write : std_logic_vector(7 downto 0); 32 | signal pmodA_writeEnable : std_logic_vector(7 downto 0); 33 | 34 | -- UART signals 35 | signal rx : std_logic := '0'; 36 | signal tx : std_logic; 37 | 38 | -- I/O signals 39 | signal leds : std_logic_vector(15 downto 0); 40 | 41 | -- Clock and reset 42 | signal boardClkLocked : std_logic; 43 | signal boardClk : std_logic; 44 | signal reset : std_logic; 45 | 46 | begin 47 | 48 | uut : entity work.J1Nexys4X 49 | port map (boardClk => boardClk, 50 | boardClkLocked => boardClkLocked, 51 | reset => reset, 52 | extInt => extInt, 53 | pmodA_read => pmodA_read, 54 | pmodA_write => pmodA_write, 55 | pmodA_writeEnable => pmodA_writeEnable, 56 | rx => rx, 57 | tx => tx, 58 | leds => leds); 59 | 60 | -- Clock process definitions 61 | clk_process : process 62 | begin 63 | 64 | -- Tell that the clock is stable 65 | boardClkLocked <= '1'; 66 | 67 | boardClk <= '0'; 68 | wait for clk_period/2; 69 | 70 | boardClk <= '1'; 71 | wait for clk_period/2; 72 | 73 | end process; 74 | 75 | reboot_proc : process 76 | begin 77 | 78 | -- Reset the CPU (asynchron) 79 | reset <= '1'; 80 | 81 | -- Wait 107ns 82 | wait for 107 ns; 83 | 84 | -- Revoke the the reset 85 | reset <= '0'; 86 | 87 | -- Wait forever 88 | wait; 89 | 90 | end process; 91 | 92 | 93 | -- Stimulus process 94 | stim_proc : process 95 | 96 | -- Text I/O 97 | variable lineBuffer : line; 98 | 99 | begin 100 | 101 | -- Give a info message 102 | write(lineBuffer, string'("Start the simulation of the CPU")); 103 | writeline(output, lineBuffer); 104 | 105 | -- Simply wait forever 106 | wait; 107 | 108 | end process; 109 | 110 | end architecture; 111 | 112 | -------------------------------------------------------------------------------- /toolchain/forth/common/core.fs: -------------------------------------------------------------------------------- 1 | \ ####### CORE ############################################ 2 | 3 | : variable 4 | create 0 , 5 | ; 6 | 7 | : constant : postpone literal postpone ; ; 8 | 9 | : sgn ( u1 n1 -- n2 ) \ n2 is u1 with the sign of n1 10 | 0< if negate then 11 | ; 12 | 13 | \ Divide d1 by n1, giving the symmetric quotient n3 and the remainder 14 | \ n2. 15 | : sm/rem ( d1 n1 -- n2 n3 ) 16 | 2dup xor >r \ combined sign, for quotient 17 | over >r \ sign of dividend, for remainder 18 | abs >r dabs r> 19 | um/mod ( remainder quotient ) 20 | swap r> sgn \ apply to remainder 21 | swap r> sgn \ apply to quotient 22 | ; 23 | 24 | \ Divide d1 by n1, giving the floored quotient n3 and the remainder n2. 25 | \ Adapted from hForth 26 | : fm/mod ( d1 n1 -- n2 n3 ) 27 | dup >r 2dup xor >r 28 | >r dabs r@ abs 29 | um/mod 30 | r> 0< if 31 | swap negate swap 32 | then 33 | r> 0< if 34 | negate \ negative quotient 35 | over if 36 | r@ rot - swap 1- 37 | then 38 | then 39 | r> drop 40 | ; 41 | 42 | : */mod >r m* r> sm/rem ; 43 | : */ */mod nip ; 44 | 45 | : spaces 46 | begin 47 | dup 0> 48 | while 49 | space 1- 50 | repeat 51 | drop 52 | ; 53 | 54 | ( Pictured numeric output JCB 08:06 07/18/14) 55 | \ Adapted from hForth 56 | 57 | \ "The size of the pictured numeric output string buffer shall 58 | \ be at least (2*n) + 2 characters, where n is the number of 59 | \ bits in a cell." 60 | \ 61 | \ The size of the region identified by WORD shall be at least 62 | \ 33 characters. 63 | 64 | create BUF0 65 | 16 cells 2 + 33 max 66 | allot here constant BUF 67 | 68 | variable hld 69 | 70 | : <# 71 | BUF hld ! 72 | ; 73 | 74 | : hold 75 | -1 hld +! hld @ c! 76 | ; 77 | 78 | : sign 79 | 0< if 80 | [char] - hold 81 | then 82 | ; 83 | 84 | : # 85 | 0 base @ um/mod >r base @ um/mod swap 86 | 9 over < [ char A char 9 1 + - ] literal and + 87 | [char] 0 + hold r> 88 | ; 89 | 90 | : #s 91 | begin 92 | # 93 | 2dup d0= 94 | until 95 | ; 96 | 97 | : #> 98 | 2drop hld @ BUF over - 99 | ; 100 | 101 | : d.r ( d n -- ) 102 | >r 103 | dup >r dabs <# #s r> sign #> 104 | r> over - spaces type 105 | ; 106 | 107 | : d. ( d -- ) 108 | 0 d.r space 109 | ; 110 | 111 | : . ( n -- ) 112 | s>d d. 113 | ; 114 | 115 | : u. ( u -- ) 116 | 0 d. 117 | ; 118 | 119 | : .r ( n1 n2 -- ) 120 | >r s>d r> d.r 121 | ; 122 | 123 | : u.r ( u n -- ) 124 | 0 swap d.r 125 | ; 126 | 127 | ( Memory operations JCB 18:02 05/31/15) 128 | 129 | : move \ ( addr1 addr2 u -- ) 130 | >r 2dup u< if 131 | r> cmove> 132 | else 133 | r> cmove 134 | then 135 | ; 136 | 137 | : word 138 | begin 139 | source >r >in @ + c@ over = 140 | r> >in @ xor and 141 | while 142 | 1 >in +! 143 | repeat 144 | 145 | parse 146 | dup BUF0 c! 147 | BUF0 1+ swap cmove 148 | BUF0 149 | ; 150 | -------------------------------------------------------------------------------- /src/main/scala/PWM.scala: -------------------------------------------------------------------------------- 1 | /* 2 | * Author: Steffen Reith (Steffen.Reith@hs-rm.de) 3 | * 4 | * Creation Date: Thu Sep 28 10:52:01 GMT+2 2017 5 | * Module Name: PWM - A simple PWM component for the J1Sc project 6 | * Project Name: J1Sc - A simple J1 implementation in Scala using Spinal HDL 7 | * 8 | */ 9 | import spinal.core._ 10 | import spinal.lib.bus.misc.BusSlaveFactory 11 | 12 | class PWM(j1Cfg : J1Config, 13 | pwmCfg : PWMConfig) extends Component { 14 | 15 | // Check the generic parameters 16 | assert(isPow2(pwmCfg.numOfDutyCycles), message = "ERROR: The number of duty cycles has to be a power of 2!") 17 | assert(pwmCfg.numOfChannels <= j1Cfg.wordSize, message = "ERROR: Too many pwm channels!") 18 | 19 | // Signals used for the internal bus 20 | val bus = new Bundle { 21 | 22 | // A new value for the compare register 23 | val newCompareValue = in Bits(j1Cfg.wordSize bits) 24 | 25 | // The write enable signals and the mapped compare registers 26 | val writeEnable = in Bits(pwmCfg.numOfChannels bits) 27 | val compareRegs = out Vec(Bits(log2Up(pwmCfg.numOfDutyCycles) bits), pwmCfg.numOfChannels) 28 | 29 | }.setName("") 30 | 31 | // Signals for a physical connection 32 | val io = new Bundle { 33 | 34 | // The physical pwm signal 35 | val pwmChannels = out Bits(pwmCfg.numOfChannels bits) 36 | 37 | }.setName("") 38 | 39 | // Write a message about the PWM-frequency (given by a generic parameter) 40 | println("[J1Sc] PWM-frequency is " + pwmCfg.pwmFrequency.toBigDecimal + "Hz") 41 | 42 | // Create a slowed down clock domain for the PWM 43 | val pwmClockDomain = ClockDomain.current.newSlowedClockDomain(pwmCfg.pwmFrequency * pwmCfg.numOfDutyCycles) 44 | 45 | // Create an area for the slowed down duty cycle counter 46 | val pwmArea = new ClockingArea(pwmClockDomain) { 47 | 48 | // Create a free running duty cycle counter 49 | val cycle = Reg(UInt(log2Up(pwmCfg.numOfDutyCycles) bits)) 50 | cycle := cycle + 1 51 | 52 | } 53 | 54 | // Create all compare registers 55 | val compareRegs = Vec(for(i <- 0 until pwmCfg.numOfChannels) yield { 56 | 57 | // Create the ith register 58 | RegNextWhen(bus.newCompareValue.resize(log2Up(pwmCfg.numOfDutyCycles)).asUInt, 59 | bus.writeEnable(i), 60 | U(log2Up(pwmCfg.numOfDutyCycles) bits, default -> false)) 61 | 62 | }) 63 | (bus.compareRegs, compareRegs).zipped.foreach(_ := _.asBits) 64 | 65 | // Create the compare logic for all channels 66 | compareRegs.zipWithIndex.foreach{case (reg, i) => (io.pwmChannels(i) := (reg > pwmArea.cycle))} 67 | 68 | // Implement the bus interface 69 | def driveFrom(busCtrl : BusSlaveFactory, baseAddress : BigInt) : Area = new Area { 70 | 71 | // The value to be used as a new compare value is constantly driven by the bus 72 | busCtrl.nonStopWrite(bus.newCompareValue, bitOffset = 0) 73 | 74 | // Make the compare register R/W 75 | for (i <- 0 until pwmCfg.numOfChannels) { 76 | 77 | // A r/w register access for the ith compare register 78 | busCtrl.read(bus.compareRegs(i), baseAddress + i, bitOffset = 0) 79 | 80 | // Generate the write enable signal for the ith compare register 81 | bus.writeEnable(i) := busCtrl.isWriting(baseAddress + i) 82 | 83 | } 84 | 85 | } 86 | 87 | } 88 | -------------------------------------------------------------------------------- /toolchain/forth/demos/newyear.fs: -------------------------------------------------------------------------------- 1 | include screenshot.fs 2 | 3 | 160 constant NSPARKS 4 | 5 | GD.init 6 | 7 | \ 0 64 64 * GD.cmd_memwrite 8 | \ include star.fs 9 | \ 0 GD.L8 64 64 GD.cmd_setbitmap 10 | \ $0000ff GD.ClearColorRGB# 11 | \ GD.Clear 12 | \ GD.BITMAPS GD.Begin 13 | \ 100 100 31 64 GD.Vertex2ii 14 | \ 100 200 0 0 GD.Vertex2ii 15 | \ GD.swap 16 | 17 | : srandom ( n -- x ) dup 2* randrange - ; 18 | 19 | object class 20 | 1 cells var x 21 | 1 cells var y 22 | 1 cells var dx 23 | 1 cells var dy 24 | 1 cells var age 25 | method park \ 26 | method born \ randomize position, velocity 27 | method move \ compute new position 28 | method draw \ draw self 29 | end-class spark 30 | 31 | : rr ( a b -- u ) over - randrange + ; 32 | 33 | :noname ( dx dy x -- ) 34 | >r 35 | -8000 r@ x ! 36 | 16 768 * r@ y ! 37 | 0 r@ dx ! 38 | 0 r@ dy ! 39 | 999 r@ age ! 40 | r> drop 41 | ; spark defines park 42 | 43 | :noname ( dx dy x -- ) 44 | >r 45 | r@ x ! 46 | -3 3 rr + r@ dx ! 47 | -230 r@ dy ! 48 | 768 16 * -16 16 rr + r@ y ! 49 | 0 8 rr r@ age ! 50 | r> drop 51 | ; spark defines born 52 | 53 | :noname 54 | >r 55 | r@ x @ 56 | r@ y @ GD.Vertex2f 57 | r> drop 58 | ; spark defines draw 59 | 60 | : lin ( x x0 x255 ) 61 | over - >r 62 | - 63 | 255 r> */ 64 | 0 max 255 min 65 | ; 66 | 67 | :noname 68 | >r 69 | r@ age @ 60 = if 70 | -50 50 rr r@ dx +! 71 | -30 50 rr r@ dy +! 72 | then 73 | r@ dx @ r@ x +! 74 | r@ dy @ r@ y +! 75 | 3 r@ dy +! 76 | 1 r@ age +! 77 | r> drop 78 | ; spark defines move 79 | 80 | \ create bb NSPARKS cells allot 81 | \ : b[] ( u -- a ) cells bb + @ ; 82 | \ 83 | \ :noname 84 | \ NSPARKS 0 do 85 | \ spark anew 86 | \ i cells bb + ! 87 | \ loop 88 | \ ; execute 89 | 90 | :noname 91 | NSPARKS 0 do 92 | spark anew drop 93 | loop 94 | ; 95 | create bb execute 96 | 97 | : b[] ( u -- a ) spark @ * bb + ; 98 | 99 | : kind ( color i ) 100 | b[] age @ dup 101 | 2* 80 max GD.PointSize 102 | 160 120 lin GD.ColorA 103 | GD.ColorRGB# 104 | ; 105 | 106 | : x 107 | NSPARKS 0 do 108 | i b[] park 109 | loop 110 | 111 | 0 34 GD.cmd_romfont 112 | 113 | GD.REG_FRAMES GD.@ 114 | 6000 0 do 115 | i 40 mod 0= if 116 | -16 16 rr 1024 16 * randrange 117 | i NSPARKS mod dup 40 + swap do 118 | 2dup i b[] born 119 | loop 120 | 2drop 121 | then 122 | GD.Clear 123 | 124 | $808080 GD.ColorRGB# 125 | 512 200 0 GD.OPT_CENTER s" HAPPY" GD.cmd_text 126 | 512 300 0 GD.OPT_CENTER s" NEW" GD.cmd_text 127 | 512 400 0 GD.OPT_CENTER s" YEAR" GD.cmd_text 128 | 512 500 0 GD.OPT_CENTER s" 2016" GD.cmd_text 129 | 130 | GD.SRC_ALPHA 1 GD.BlendFunc 131 | GD.POINTS GD.Begin 132 | NSPARKS 0 do 133 | i case 134 | 0 of $f08040 i kind endof 135 | 40 of $80f040 i kind endof 136 | 80 of $8040f0 i kind endof 137 | 120 of $4080f0 i kind endof 138 | endcase 139 | i b[] dup move draw 140 | loop 141 | 142 | GD.swap 143 | \ i 1 and if GD.screenshot then 144 | loop 145 | GD.finish GD.REG_FRAMES GD.@ swap - . 146 | ; 147 | -------------------------------------------------------------------------------- /src/main/scala/MainMemory.scala: -------------------------------------------------------------------------------- 1 | /* 2 | * Author: Steffen Reith (Steffen.Reith@hs-rm.de) 3 | * 4 | * Creation Date: Sun Jan 22 12:51:03 GMT+1 2017 5 | * Module Name: MainMemory - implementation of 64k words main memory 6 | * Project Name: J1Sc - A simple J1 implementation in Scala using Spinal HDL 7 | * 8 | * Note: This module takes "small" blocks of BRAM and uses Spinal to tie them 9 | * together. The reason for doing so is the incapability of Xilinx Vivado 2016.4 10 | * the generate a dual ported BRAM bigger than 64K (one port one gives 0 as 11 | * a value back). Warning: The simulation works, but the real hardware causes 12 | * pain 13 | * 14 | */ 15 | import spinal.core._ 16 | 17 | class MainMemory(cfg : J1Config) extends Component { 18 | 19 | // Check the generic parameters 20 | assert(cfg.wordSize >= cfg.adrWidth, message = "ERROR: The width of addresses are too large") 21 | assert(isPow2(cfg.numOfRAMs), message = "ERROR: Number of RAMs has to be a power of 2") 22 | assert(cfg.numOfRAMs >= 2, message = "ERROR: Number of RAMs has to be at least 2") 23 | 24 | // I/O ports 25 | val internal = new Bundle { 26 | 27 | // Instruction port (read only) 28 | val readDataAdr = in UInt (cfg.adrWidth bits) 29 | val readData = out Bits (cfg.wordSize bits) 30 | 31 | // Memory port (write only) 32 | val writeEnable = in Bool 33 | val writeDataAdr = in UInt (cfg.adrWidth bits) 34 | val writeData = in Bits (cfg.wordSize bits) 35 | 36 | }.setName("") 37 | 38 | // Calculate the number of bits needed to address the RAMs 39 | def ramAdrWidth = log2Up(cfg.numOfRAMs) 40 | 41 | // Number of cells of a RAM 42 | def numOfCells = 1 << (cfg.adrWidth - ramAdrWidth) 43 | 44 | // Give some information about RAM-size and used bank layout 45 | println("[J1Sc] Create " + cfg.numOfRAMs + " RAMs which have " + numOfCells + " cells each") 46 | println("[J1Sc] Total size is " + cfg.numOfRAMs * numOfCells + " cells") 47 | 48 | // Create a complete list of memory blocks (start with first block) 49 | val ramList = for (i <- 0 until cfg.numOfRAMs) yield { 50 | 51 | // Write a message 52 | println("[J1Sc] Filling RAM " + 53 | i + 54 | " (Range from " + 55 | (i * numOfCells) + 56 | " to " + 57 | (i * numOfCells + numOfCells - 1) + 58 | ")") 59 | 60 | // Create the ith RAM and fill it with the appropriate part of the bootcode 61 | Mem(Bits(cfg.wordSize bits), cfg.bootCode().slice(i * numOfCells, (i + 1) * numOfCells)) 62 | 63 | } 64 | 65 | // Convert the list to a spinal vector 66 | val rPortsVec = Vec(for((ram,i) <- ramList.zipWithIndex) yield { 67 | 68 | // Create the write port of the ith RAM 69 | ram.write(enable = internal.writeEnable && 70 | (U(i) === internal.writeDataAdr(internal.writeDataAdr.high downto 71 | internal.writeDataAdr.high - ramAdrWidth + 1)), 72 | address = internal.writeDataAdr((internal.writeDataAdr.high - ramAdrWidth) downto 0), 73 | data = internal.writeData) 74 | 75 | // Create the read port of the ith RAM 76 | ram.readSync(address = internal.readDataAdr((internal.readDataAdr.high - ramAdrWidth) downto 0)) 77 | 78 | }) 79 | 80 | // Multiplex the read port 81 | internal.readData := rPortsVec(RegNext(internal.readDataAdr(internal.readDataAdr.high downto 82 | internal.readDataAdr.high - ramAdrWidth + 1))) 83 | 84 | } 85 | -------------------------------------------------------------------------------- /toolchain/forth/basewords.fs: -------------------------------------------------------------------------------- 1 | ( J1 base words implemented in assembler JCB 17:27 12/31/11) 2 | 3 | : T h# 0000 ; 4 | : N h# 0100 ; 5 | : T+N h# 0200 ; 6 | : T&N h# 0300 ; 7 | : T|N h# 0400 ; 8 | : T^N h# 0500 ; 9 | : ~T h# 0600 ; 10 | : N==T h# 0700 ; 11 | : NN h# 0010 or ; 21 | : T->R h# 0020 or ; 22 | : N->[T] h# 0030 or ; 23 | : N->io[T] h# 0040 or ; 24 | : _IORD_ h# 0050 or ; 25 | : RET h# 0080 or ; 26 | 27 | : d-1 h# 0003 or ; 28 | : d+1 h# 0001 or ; 29 | : r-1 h# 000c or ; 30 | : r-2 h# 0008 or ; 31 | : r+1 h# 0004 or ; 32 | 33 | : imm h# 8000 or tcode, ; 34 | : alu h# 6000 or tcode, ; 35 | : ubranch h# 0000 or tcode, ; 36 | : 0branch h# 2000 or tcode, ; 37 | : scall h# 4000 or tcode, ; 38 | 39 | 40 | :: noop T alu ; 41 | :: + T+N d-1 alu ; 42 | :: - N-T d-1 alu ; 43 | :: xor T^N d-1 alu ; 44 | :: and T&N d-1 alu ; 45 | :: or T|N d-1 alu ; 46 | :: invert ~T alu ; 47 | :: = N==T d-1 alu ; 48 | :: < NN alu ; 51 | :: dup T T->N d+1 alu ; 52 | :: drop N d-1 alu ; 53 | :: over N T->N d+1 alu ; 54 | :: nip T d-1 alu ; 55 | :: >r N T->R r+1 d-1 alu ; 56 | :: r> rT T->N r-1 d+1 alu ; 57 | :: r@ rT T->N d+1 alu ; 58 | :: io@ 59 | io[T] _IORD_ alu 60 | io[T] _IORD_ alu ; 61 | :: ! 62 | T N->[T] d-1 alu 63 | N d-1 alu ; 64 | :: io! 65 | T N->io[T] d-1 alu 66 | N d-1 alu ; 67 | 68 | :: 2/ T2/ alu ; 69 | :: 2* T2* alu ; 70 | :: depth status T->N d+1 alu ; 71 | :: exit T RET r-1 alu ; 72 | :: hack T N->io[T] alu 73 | N alu ; 74 | 75 | \ Elided words 76 | \ These words are supported by the hardware but are not 77 | \ part of ANS Forth. They are named after the word-pair 78 | \ that matches their effect 79 | \ Using these elided words instead of 80 | \ the pair saves one cycle and one instruction. 81 | 82 | :: 2dupand T&N T->N d+1 alu ; 83 | :: 2dup< NN d+1 alu ; 84 | :: 2dup= N==T T->N d+1 alu ; 85 | :: 2dupor T|N T->N d+1 alu ; 86 | :: 2dup+ T+N T->N d+1 alu ; 87 | :: 2dupu< NuN d+1 alu ; 88 | :: 2dupxor T^N T->N d+1 alu ; 89 | :: dup>r T T->R r+1 alu ; 90 | :: overand T&N alu ; 91 | :: over> N Nu[T] d-1 alu ; 99 | -------------------------------------------------------------------------------- /toolchain/forth/python/swapforth.fs: -------------------------------------------------------------------------------- 1 | : \ source nip >in ! ; immediate \ Now can use comments! 2 | \ 3 | \ This file contains definitions in high-level Forth for the 4 | \ rest of Swapforth. Many words were already defined in 5 | \ nucleus -- this file fills in the gaps. 6 | \ 7 | \ This file is divided into sections for each word set in ANS 8 | \ Forth. 9 | \ 10 | \ The only definitions in this file should be specific to 11 | \ Swapforth Python (sfpy). 12 | 13 | \ ####### CORE AND DOUBLE ################################# 14 | 15 | : false 0 ; 16 | : true -1 ; 17 | : 1+ 1 + ; 18 | : 1- -1 + ; 19 | : 0= 0 = ; 20 | : <> = invert ; 21 | : > swap < ; 22 | : 0< 0 < ; 23 | : 0> 0 > ; 24 | : 0<> 0 <> ; 25 | : u> swap u< ; 26 | : rot >r swap r> swap ; 27 | : -rot swap >r swap r> ; 28 | : ?dup dup if dup then ; 29 | : abs dup 0< if negate then ; 30 | : +! tuck @ + swap ! ; 31 | : 2* dup + ; 32 | : cells 0 cell+ * ; 33 | : count dup 1+ swap c@ ; 34 | 35 | include core0.fs 36 | include double0.fs 37 | 38 | : aligned ; 39 | : align ; 40 | 41 | : 2>r swap >r >r ; 42 | : 2r> r> r> swap ; 43 | : 2r@ 2r> 2dup 2>r ; 44 | 45 | : create 46 | : 47 | align here postpone literal 48 | postpone ; 49 | ; 50 | 51 | include double.fs 52 | 53 | : bounds 54 | over + swap 55 | ; 56 | 57 | : type 58 | bounds ?do 59 | i c@ emit 60 | loop 61 | ; 62 | 63 | : fill \ ( c-addr u char -- ) ( 6.1.1540 ) 64 | >r bounds 65 | begin 66 | 2dup xor 67 | while 68 | r@ over c! 1+ 69 | repeat 70 | r> drop 2drop 71 | ; 72 | 73 | : cmove \ ( addr1 addr2 u -- ) 74 | bounds rot >r 75 | begin 76 | 2dup xor 77 | while 78 | r@ c@ over c! 79 | r> 1+ >r 80 | 1+ 81 | repeat 82 | r> drop 2drop 83 | ; 84 | 85 | : cmove> \ ( addr1 addr2 u -- ) 86 | begin 87 | dup 88 | while 89 | 1- >r 90 | over r@ + c@ 91 | over r@ + c! 92 | r> 93 | repeat 94 | drop 2drop 95 | ; 96 | 97 | include core.fs 98 | 99 | : /mod >r s>d r> sm/rem ; 100 | : / /mod nip ; 101 | : mod /mod drop ; 102 | 103 | \ ####### CORE EXT ######################################## 104 | 105 | : s, 106 | dup c, 107 | bounds ?do 108 | i c@ c, 109 | loop 110 | ; 111 | 112 | : c" 113 | here postpone literal 114 | [char] " parse 115 | s, 116 | ; immediate 117 | 118 | : sliteral 119 | here postpone literal 120 | postpone count 121 | s, 122 | ; immediate 123 | 124 | : (.") 125 | count 2dup type + 1+ >r 126 | ; 127 | 128 | : ." 129 | [char] " parse 130 | state @ if 131 | here postpone literal 132 | postpone (.") 133 | s, 134 | else 135 | type 136 | then 137 | ; immediate 138 | 139 | : unused here negate ; 140 | 141 | create pad 65536 allot 142 | 143 | include core-ext0.fs 144 | include core-ext.fs 145 | 146 | \ ####### EVERYTHING ELSE ################################# 147 | 148 | include float0.fs 149 | include string0.fs 150 | include string.fs 151 | include tools-ext.fs 152 | include value.fs 153 | include exception.fs 154 | 155 | : LOCALWORDS ; 156 | : PUBLICWORDS ; 157 | : DONEWORDS ; 158 | 159 | include escaped.fs 160 | include deferred.fs 161 | include forth2012.fs 162 | 163 | include structures.fs 164 | include memory.fs 165 | 166 | \ include runtests.fs 167 | -------------------------------------------------------------------------------- /toolchain/forth/demos/easter.fs: -------------------------------------------------------------------------------- 1 | \ Date of Easter According to Knuth 2 | 3 | \ Donald E. Knuth, _The Art of Computer Programming_, 1.3.2 Exercise 4 | \ 14-15. 5 | 6 | \ [Commentary by Knuth, Forth by Wil Baden. This is not well-suited 7 | \ for Forth, but there's no advantage in purifying it.] 8 | 9 | \ The following algorithm, due to the Neapolitan astronomer Aloysius 10 | \ Lilius and the German Jesuit mathematician Christopher Clavius in 11 | \ the late 16th century, is used by most Western churches to 12 | \ determine the date of Easter Sunday for any year after 1582. 13 | 14 | : ANDIF S" DUP IF DROP " EVALUATE ; IMMEDIATE 15 | 16 | : ORIF S" DUP 0= IF DROP " EVALUATE ; IMMEDIATE 17 | 18 | 19 | \ Counters. 20 | 21 | \ Y 22 | \ Year. 23 | 24 | \ G 25 | \ Golden number. 26 | 27 | \ C 28 | \ Century. 29 | 30 | \ X 31 | \ Century leap year adjustment. 32 | 33 | \ Z 34 | \ Moon's orbit adjustment. 35 | 36 | \ D 37 | \ Sunday date. 38 | 39 | \ E 40 | \ Epact. 41 | 42 | \ N 43 | \ Day of month. 44 | 45 | VARIABLE Y \ Year 46 | VARIABLE G \ Golden number 47 | VARIABLE C \ Century 48 | VARIABLE X \ Century leap year adjustment 49 | VARIABLE Z \ Moon's orbit adjustment 50 | VARIABLE D \ Sunday date 51 | VARIABLE E \ Epact 52 | VARIABLE N \ Day of month 53 | 54 | \ EASTER ( yyyyy -- dd mm yyyyy ) 55 | \ Compute date of Easter for year _yyyyy_. 56 | 57 | : EASTER ( yyyyy -- dd mm yyyyy ) 58 | 59 | Y ! ( ) 60 | 61 | \ E1. Golden number. 62 | \ _G_ is the so-called "golden number" of the year in the 63 | \ 19-year Metonic cycle. 64 | 65 | Y @ 19 MOD 1+ G ! 66 | 67 | \ E2. Century. 68 | \ When _Y_ is not a multiple of 100, _C_ is the century number; 69 | \ for example, 1984 is in the twentieth century. 70 | 71 | Y @ 100 / 1+ C ! 72 | 73 | \ E3. Corrections. 74 | \ Here _X_ is the number of years, such as 1900, in which leap 75 | \ year was dropped in order to keep in step with the sun; _Z_ is 76 | \ a special correction designed to synchronize Easter with the 77 | \ moon's orbit. 78 | 79 | C @ 3 4 */ 12 - X ! 80 | C @ 8 * 5 + 25 / 5 - Z ! 81 | 82 | \ E4. Find Sunday. 83 | \ March ((-_D_) mod 7) actually will be a Sunday. 84 | 85 | Y @ 5 4 */ X @ - 10 - D ! 86 | 87 | \ E5. Epact. 88 | \ This number _E_ is the _epact_, which specifies when a full 89 | \ moon occurs. 90 | 91 | G @ 11 * 20 + Z @ + X @ - 30 MOD 92 | dup 0< IF 30 + THEN 93 | E ! 94 | E @ 25 = ANDIF G @ 11 > THEN 95 | ORIF E @ 24 = THEN 96 | IF 1 E +! THEN 97 | 98 | \ E6. Find full moon. 99 | \ Easter is supposedly the first Sunday following the first full 100 | \ moon that occurs on or after March 21. Actually perturbations 101 | \ in the moon's orbit do not make this strictly true, but we are 102 | \ concerned here with the "calendar moon" rather than the actual 103 | \ moon. The _N_th of March is a calendar full moon. 104 | 105 | 44 E @ - N ! 106 | N @ 21 < IF 30 N +! THEN 107 | 108 | \ E7. Advance to Sunday. 109 | 110 | N @ 7 + 111 | D @ N @ + 7 MOD - 112 | N ! 113 | 114 | \ E8. Get month. 115 | 116 | N @ 31 > IF 117 | N @ 31 - 4 Y @ 118 | ELSE 119 | N @ 3 Y @ 120 | THEN ; 121 | 122 | \ .EASTER ( yyyyy -- ) 123 | \ Display date of Easter for year _yyyyy_. 124 | 125 | : .EASTER ( yyyyy -- ) 126 | EASTER . 4 = IF ." April " ELSE ." March " THEN . ; 127 | 128 | -------------------------------------------------------------------------------- /toolchain/forth/swapforth.fs: -------------------------------------------------------------------------------- 1 | \ 2 | \ This file contains definitions in high-level Forth for the 3 | \ rest of SwapForth. Many words were already defined in 4 | \ nucleus -- this file fills in the gaps. 5 | \ 6 | \ This file is divided into sections for each word set in ANS 7 | \ Forth. 8 | \ 9 | \ The only definitions in this file should be specific to 10 | \ J1a SwapForth. 11 | 12 | \ ####### CORE AND DOUBLE ################################# 13 | 14 | : ['] 15 | ' postpone literal 16 | ; immediate 17 | 18 | : [char] 19 | char postpone literal 20 | ; immediate 21 | 22 | : ( 23 | [char] ) parse 2drop 24 | ; immediate 25 | 26 | : else 27 | postpone ahead 28 | swap 29 | postpone then 30 | ; immediate 31 | 32 | : while 33 | postpone if 34 | swap 35 | ; immediate 36 | 37 | : repeat 38 | postpone again 39 | postpone then 40 | ; immediate 41 | 42 | : >body 43 | 4 + 44 | ; 45 | 46 | : create 47 | : 48 | here >body postpone literal 49 | postpone ; 50 | ; 51 | 52 | #include common/core.fs 53 | #include common/peripheral.fs 54 | 55 | : /mod >r s>d r> sm/rem ; 56 | : / /mod nip ; 57 | : mod /mod drop ; 58 | 59 | : ." 60 | [char] " parse 61 | state @ if 62 | postpone sliteral 63 | postpone type 64 | else 65 | type 66 | then 67 | ; immediate 68 | 69 | : abort" 70 | postpone if 71 | postpone ." 72 | postpone abort 73 | postpone then 74 | ; immediate 75 | 76 | \ ####### CORE EXT ######################################## 77 | 78 | : unused 79 | $2000 here - 80 | ; 81 | 82 | : pad 83 | here aligned 84 | ; 85 | 86 | #include common/core-ext.fs 87 | 88 | : marker 89 | forth 2@ \ preserve FORTH and DP 90 | create 91 | , , 92 | does> 93 | 2@ forth 2! \ restore FORTH and DP 94 | ; 95 | 96 | ( x -- ) \ wait x ms 9937 equals 80MHz core clock 97 | : ms 0 do 12421 0 do loop loop ; 98 | 99 | : new 100 | s" | marker |" evaluate 101 | ; 102 | marker | 103 | 104 | : .xt ( xt -- ) \ print XT's address and name, if valid 105 | dup .x 106 | dup 107 | begin 108 | 2 - 109 | dup c@ $20 < 110 | until 111 | \ confirm by looking up with FIND 112 | tuck ( caddr xt caddr ) 113 | find ( caddr xt xt n | caddr xt caddr 0 ) 114 | 0<> and = if 115 | count type 116 | else 117 | drop \ not valid, so discard 118 | then 119 | ; 120 | 121 | \ Construct a 4-entry jump table called _ 122 | \ for the four J1 opcodes 123 | 124 | ( 3:ALU ) :noname ." alu: " 2/ .x ; 125 | ( 2:CALL ) :noname [char] C emit space .xt ; 126 | ( 1:0BRANCH ) :noname [char] Z emit space .x ; 127 | ( 0:JUMP ) :noname [char] J emit space .xt ; 128 | create _ , , , , 129 | 130 | : see 131 | ' 132 | 48 bounds 133 | begin 134 | cr dup .x 135 | dup @ 136 | dup .x 137 | 6 spaces 138 | dup 0< if 139 | [char] $ emit 140 | 32767 and .x 141 | else 142 | dup 8191 and 2* 143 | swap 13 rshift cells _ + @ execute 144 | then 145 | cell+ 146 | 2dup = 147 | until 148 | 2drop 149 | ; 150 | 151 | : dump 152 | ?dup 153 | if 154 | 1- 4 rshift 1+ 155 | 0 do 156 | cr dup dup .x space space 157 | 16 0 do 158 | dup c@ .x2 1+ 159 | loop 160 | space swap 161 | 16 0 do 162 | dup c@ dup bl 127 within invert if 163 | drop [char] . 164 | then 165 | emit 1+ 166 | loop 167 | drop 168 | loop 169 | then 170 | drop 171 | ; 172 | -------------------------------------------------------------------------------- /toolchain/forth/demos/vga2.fs: -------------------------------------------------------------------------------- 1 | ( Setup for Ken Boak's VGA shield, which uses an FT812 ) 2 | 3 | 9 constant CS 4 | 5 | : gd2-sel 0 CS io! ; 6 | : gd2-unsel 1 CS io! ; 7 | : gd2-spi-init 8 | OUTPUT CS pinMode 9 | gd2-unsel 10 | spi-init 11 | ; 12 | 13 | include gd2.fs 14 | 15 | \ H and Vsync parameters start at GD.REG_HCYCLE, VCYCLE 16 | \ and are ordered: HCYCLE HOFFSET HSIZE HSYNC0 HSYNC1 17 | 18 | : setsync ( visible sync back whole REG -- ) 19 | 20 GD.cmd_memwrite 20 | GD.c \ CYCLE 21 | over + GD.c \ OFFSET 22 | swap GD.c \ SIZE 23 | 0 GD.c \ SYNC0 24 | GD.c \ SYNC1 25 | ; 26 | 27 | : hs GD.REG_HCYCLE setsync ; 28 | : vs GD.REG_VCYCLE setsync ; 29 | 30 | : pll ( pll -- ) \ set PLL clock multiplier 31 | dup GD.pll GD.crystal 32 | 13000000 * GD.REG_FREQUENCY GD.! 33 | ; 34 | 35 | : pclk ( pclk -- ) \ common register settings for EVITA display 36 | 0 GD.REG_CSPREAD GD.! 37 | 0 GD.REG_SWIZZLE GD.! 38 | 0 GD.REG_ROTATE GD.! 39 | GD.REG_PCLK GD.! 40 | ; 41 | 42 | \ H/V timing parameters order: visible sync back whole 43 | 44 | : res create , does> @ GD.setcustom ; 45 | :noname 5 pll 1024 136 160 1344 hs 768 6 29 806 vs 1 pclk ; 46 | :noname 3 pll 800 128 88 1056 hs 600 4 23 628 vs 1 pclk ; 47 | :noname 4 pll 640 96 48 800 hs 480 2 33 542 vs 2 pclk ; 48 | res 640x480 res 800x600 res 1024x768 49 | 50 | 1024x768 \ default resolution 51 | 52 | : GD.calibrate ; ( there is no touch screen ) 53 | 54 | : test-page 55 | GD.init 56 | 57 | 0 34 GD.cmd_romfont 58 | 59 | begin 60 | 0 0 $00ff00 1024 768 $ff0000 GD.cmd_gradient 61 | 16 16 GD.SCISSORXY 62 | 1024 32 - 768 32 - GD.SCISSORSIZE 63 | GD.Clear 64 | 65 | 512 50 GD.SCISSORSIZE 66 | 3 0 do 67 | 256 i 100 * 484 + GD.SCISSORXY 68 | 256 i 100 * 484 + $000000 69 | 768 i 100 * 484 + $0000ff i 8 * lshift 70 | GD.cmd_gradient 71 | loop 72 | GD.RestoreContext 73 | 74 | 512 186 150 0 75 | ms@ 1000 /mod 2>r 76 | r@ 3600 / 12 mod ( hours ) 77 | r@ 60 / 60 mod ( minutes ) 78 | r> 60 mod ( seconds ) 79 | r> ( ms ) 80 | GD.cmd_clock 81 | 82 | 32 32 30 0 83 | GD.wh s>d <# #s 2drop 'x' hold s>d #s #> 84 | GD.cmd_text 85 | 512 404 0 GD.OPT_CENTER s" Hello world" GD.cmd_text 86 | 87 | GD.swap 88 | GD.finish 89 | again 90 | ; 91 | 92 | 128 48 * 2* constant NB \ bytes in 1024x768 text mode 93 | 94 | : test-vga 95 | GD.init 96 | 97 | 0 GD.TEXTVGA 1024 768 GD.cmd_setbitmap 98 | 99 | GD.Clear 100 | 1 0 GD.BlendFunc 101 | GD.BITMAPS GD.Begin 102 | 0 0 0 0 GD.Vertex2ii 103 | GD.swap 104 | begin 105 | 0 NB GD.cmd_memwrite 106 | NB 0 do 107 | random GD.c 108 | 4 +loop 109 | 1000 ms 110 | again 111 | ; 112 | 113 | : .3 ( u -- ) \ print as 3-digit decimal 114 | s>d <# # # # '.' hold #s #> type space 115 | ; 116 | 117 | : sync \ wait until REG_FRAMES changes 118 | GD.REG_FRAMES GD.c@ 119 | begin 120 | dup GD.REG_FRAMES GD.c@ xor 121 | until 122 | drop 123 | ; 124 | 125 | : report 126 | cr 127 | \ GD.@ . 128 | 129 | ." REG_ID " 130 | GD.REG_ID GD.@ hex2. cr 131 | 132 | ." resolution " 133 | GD.wh swap 0 .r 'x' emit . cr 134 | 135 | ." Measured core freq. " 136 | GD.REG_CLOCK GD.@ 137 | 1000 ms 138 | GD.REG_CLOCK GD.@ 139 | swap - 1000 / .3 140 | ." MHz" cr 141 | 142 | ." Measured frame rate " 143 | sync ms@ 144 | 100 0 do sync loop 145 | ms@ swap - 146 | 100000000 swap / .3 147 | ." Hz" cr 148 | ; 149 | -------------------------------------------------------------------------------- /vprj/vhdl/J1Sc/J1Sc/J1Sc.sim/sim_1/behav/xsim/xsim.dir/Board_Nexys4DDR_behav/webtalk/xsim_webtalk.tcl: -------------------------------------------------------------------------------- 1 | webtalk_init -webtalk_dir /home/streit/src/scala/J1Sc/vprj/vhdl/J1Sc/J1Sc/J1Sc.sim/sim_1/behav/xsim/xsim.dir/Board_Nexys4DDR_behav/webtalk/ 2 | webtalk_register_client -client project 3 | webtalk_add_data -client project -key date_generated -value "Fri May 4 12:58:03 2018" -context "software_version_and_target_device" 4 | webtalk_add_data -client project -key product_version -value "XSIM v2018.1 (64-bit)" -context "software_version_and_target_device" 5 | webtalk_add_data -client project -key build_version -value "2188600" -context "software_version_and_target_device" 6 | webtalk_add_data -client project -key os_platform -value "LIN64" -context "software_version_and_target_device" 7 | webtalk_add_data -client project -key registration_id -value "202041034_1777501815_210671918_324" -context "software_version_and_target_device" 8 | webtalk_add_data -client project -key tool_flow -value "xsim_vivado" -context "software_version_and_target_device" 9 | webtalk_add_data -client project -key beta -value "FALSE" -context "software_version_and_target_device" 10 | webtalk_add_data -client project -key route_design -value "FALSE" -context "software_version_and_target_device" 11 | webtalk_add_data -client project -key target_family -value "not_applicable" -context "software_version_and_target_device" 12 | webtalk_add_data -client project -key target_device -value "not_applicable" -context "software_version_and_target_device" 13 | webtalk_add_data -client project -key target_package -value "not_applicable" -context "software_version_and_target_device" 14 | webtalk_add_data -client project -key target_speed -value "not_applicable" -context "software_version_and_target_device" 15 | webtalk_add_data -client project -key random_id -value "c2fed4ed-5207-41cf-8987-6efa2549dd9d" -context "software_version_and_target_device" 16 | webtalk_add_data -client project -key project_id -value "28d8c42bf4ea4dbdaf7c1c1f04676d10" -context "software_version_and_target_device" 17 | webtalk_add_data -client project -key project_iteration -value "4" -context "software_version_and_target_device" 18 | webtalk_add_data -client project -key os_name -value "Ubuntu" -context "user_environment" 19 | webtalk_add_data -client project -key os_release -value "Ubuntu 16.04.4 LTS" -context "user_environment" 20 | webtalk_add_data -client project -key cpu_name -value "Intel(R) Core(TM) i7-4980HQ CPU @ 2.80GHz" -context "user_environment" 21 | webtalk_add_data -client project -key cpu_speed -value "2793.532 MHz" -context "user_environment" 22 | webtalk_add_data -client project -key total_processors -value "1" -context "user_environment" 23 | webtalk_add_data -client project -key system_ram -value "4.000 GB" -context "user_environment" 24 | webtalk_register_client -client xsim 25 | webtalk_add_data -client xsim -key Command -value "xsim" -context "xsim\\command_line_options" 26 | webtalk_add_data -client xsim -key trace_waveform -value "true" -context "xsim\\usage" 27 | webtalk_add_data -client xsim -key runtime -value "1 us" -context "xsim\\usage" 28 | webtalk_add_data -client xsim -key iteration -value "1" -context "xsim\\usage" 29 | webtalk_add_data -client xsim -key Simulation_Time -value "0.01_sec" -context "xsim\\usage" 30 | webtalk_add_data -client xsim -key Simulation_Memory -value "133484_KB" -context "xsim\\usage" 31 | webtalk_transmit -clientid 888600713 -regid "202041034_1777501815_210671918_324" -xml /home/streit/src/scala/J1Sc/vprj/vhdl/J1Sc/J1Sc/J1Sc.sim/sim_1/behav/xsim/xsim.dir/Board_Nexys4DDR_behav/webtalk/usage_statistics_ext_xsim.xml -html /home/streit/src/scala/J1Sc/vprj/vhdl/J1Sc/J1Sc/J1Sc.sim/sim_1/behav/xsim/xsim.dir/Board_Nexys4DDR_behav/webtalk/usage_statistics_ext_xsim.html -wdm /home/streit/src/scala/J1Sc/vprj/vhdl/J1Sc/J1Sc/J1Sc.sim/sim_1/behav/xsim/xsim.dir/Board_Nexys4DDR_behav/webtalk/usage_statistics_ext_xsim.wdm -intro "

XSIM Usage Report


" 32 | webtalk_terminate 33 | -------------------------------------------------------------------------------- /src/main/scala/J1.scala: -------------------------------------------------------------------------------- 1 | /* 2 | * Author: Steffen Reith (Steffen.Reith@hs-rm.de) 3 | * 4 | * Create Date: Tue Sep 20 15:07:10 CEST 2016 5 | * Module Name: J1 - Toplevel CPU (Core, Memory) 6 | * Project Name: J1Sc - A simple J1 implementation in Scala using Spinal HDL 7 | * 8 | */ 9 | import spinal.core._ 10 | import spinal.lib._ 11 | 12 | class J1(cfg : J1Config) extends Component { 13 | 14 | // Internal signals 15 | val internal = new Bundle { 16 | 17 | // Stall signal of CPU 18 | val stall = in Bool 19 | 20 | // Interface for the interrupt system 21 | val irq = in Bool 22 | val intVec = in Bits (cfg.adrWidth bits) 23 | 24 | }.setName("") 25 | 26 | // I/O signals for the jtag interface (if needed) 27 | val jtagCondIOArea = cfg.hasJtag generate new Area { 28 | 29 | // Create the interface bundle 30 | val jtagMemBus = new Bundle { 31 | 32 | // Signal from jtag for memory bus 33 | val captureMemory = in Bool 34 | val jtagMemAdr = in Bits (cfg.adrWidth bits) 35 | val jtagMemWord = in Bits (cfg.wordSize bits) 36 | 37 | }.setName("") 38 | 39 | } 40 | 41 | // Peripheral bus 42 | val bus = new Bundle { 43 | 44 | // I/O signals for peripheral data port 45 | val cpuBus = master(J1Bus(cfg)) 46 | 47 | }.setName("") 48 | 49 | // Create a new CPU core 50 | val coreJ1CPU = new J1Core(cfg) 51 | 52 | // Create the main memory 53 | val mainMem = new MainMemory(cfg) 54 | 55 | // Instruction port (read only) 56 | mainMem.internal.readDataAdr <> coreJ1CPU.internal.nextInstrAdr 57 | coreJ1CPU.internal.memInstr <> mainMem.internal.readData 58 | 59 | // Check if we have a jtag interface 60 | if (cfg.hasJtag) { 61 | 62 | // Check whether the cpu is stalled (otherwise we have no access to the memory) 63 | when (internal.stall) { 64 | 65 | // Connect the synchronized hold register of the jtag interface 66 | mainMem.internal.writeEnable <> jtagCondIOArea.jtagMemBus.captureMemory 67 | mainMem.internal.writeDataAdr <> jtagCondIOArea.jtagMemBus.jtagMemAdr.asUInt 68 | mainMem.internal.writeData <> jtagCondIOArea.jtagMemBus.jtagMemWord 69 | 70 | }.otherwise { 71 | 72 | // Connect the CPU core with the main memory (convert the byte address to a cell address) 73 | mainMem.internal.writeEnable <> coreJ1CPU.internal.memWriteMode 74 | mainMem.internal.writeDataAdr <> coreJ1CPU.internal.extAdr(cfg.adrWidth downto 1) 75 | mainMem.internal.writeData <> coreJ1CPU.internal.extToWrite 76 | 77 | } 78 | 79 | } else { 80 | 81 | // Connect the CPU core with the main memory (convert the byte address to a cell address) 82 | mainMem.internal.writeEnable <> coreJ1CPU.internal.memWriteMode 83 | mainMem.internal.writeDataAdr <> coreJ1CPU.internal.extAdr(cfg.adrWidth downto 1) 84 | mainMem.internal.writeData <> coreJ1CPU.internal.extToWrite 85 | 86 | } 87 | 88 | // Check whether data should be read for I/O space else provide a constant zero value 89 | val coreMemRead = coreJ1CPU.internal.ioReadMode ? bus.cpuBus.readData | B(0, cfg.wordSize bits) 90 | 91 | // Read port of CPU core (multiplexed) 92 | coreJ1CPU.internal.toRead <> coreMemRead 93 | 94 | // Connect the external bus to the core (remember coreJ1CPU.io.extAdr is one clock too early) 95 | bus.cpuBus.enable := coreJ1CPU.internal.ioWriteMode || coreJ1CPU.internal.ioReadMode 96 | bus.cpuBus.writeMode <> coreJ1CPU.internal.ioWriteMode 97 | bus.cpuBus.address <> Delay(coreJ1CPU.internal.extAdr, 1) 98 | bus.cpuBus.writeData <> coreJ1CPU.internal.extToWrite 99 | 100 | // Connect the stall 101 | coreJ1CPU.internal.stall <> internal.stall 102 | 103 | // Connect the interrupts 104 | coreJ1CPU.internal.intVec <> internal.intVec 105 | coreJ1CPU.internal.irq <> internal.irq 106 | 107 | } 108 | -------------------------------------------------------------------------------- /src/main/verilog/arch/Nexys4/Board_Nexys4.v: -------------------------------------------------------------------------------- 1 | // 2 | // Author: Steffen Reith (steffen.reith@hs-rm.de) 3 | // 4 | // Creation Date: Sat May 6 16:32:24 GMT+2 2017 5 | // Module Name: Board_Nexys4 - Behavioral 6 | // Project Name: J1Sc - A simple J1 implementation in Scala using Spinal HDL 7 | // 8 | // 9 | 10 | module Board_Nexys4 (nreset, 11 | clk100Mhz, 12 | extInt, 13 | leds, 14 | rgbLeds, 15 | segments_a, 16 | segments_b, 17 | segments_c, 18 | segments_d, 19 | segments_e, 20 | segments_f, 21 | segments_g, 22 | dot, 23 | selector, 24 | pmodA, 25 | sSwitches, 26 | pButtons, 27 | tck, 28 | tms, 29 | tdi, 30 | tdo, 31 | rx, 32 | tx); 33 | 34 | // Input ports 35 | input nreset; 36 | input clk100Mhz; 37 | input [0:0] extInt; 38 | input [15:0] sSwitches; 39 | input [4:0] pButtons; 40 | input tck; 41 | input tms; 42 | input tdi; 43 | input rx; 44 | 45 | // Output ports 46 | output [15:0] leds; 47 | output [5:0] rgbLeds; 48 | output tdo; 49 | output tx; 50 | output segments_a; 51 | output segments_b; 52 | output segments_c; 53 | output segments_d; 54 | output segments_e; 55 | output segments_f; 56 | output segments_g; 57 | output dot; 58 | output [7:0] selector; 59 | 60 | // Bidirectional port 61 | inout [7:0] pmodA; 62 | 63 | // Internal reset 64 | wire reset; 65 | 66 | // Clock generation 67 | wire boardClk; 68 | wire boardClkLocked; 69 | 70 | // Internal wiring 71 | wire [7:0] pmodA_read; 72 | wire [7:0] pmodA_write; 73 | wire [7:0] pmodA_writeEnable; 74 | 75 | // Instantiate a PLL/MMCM (makes a 80Mhz clock) 76 | PLL makeClk (.clkIn (clk100Mhz), 77 | .clkOut (boardClk), 78 | .isLocked (boardClkLocked)); 79 | 80 | // Instantiate the J1SoC core generated by Spinal 81 | J1Nexys4X core (.reset (reset), 82 | .boardClk (boardClk), 83 | .boardClkLocked (boardClkLocked), 84 | .extInt (extInt), 85 | .leds (leds), 86 | .rgbLeds (rgbLeds), 87 | .segments_a (segments_a), 88 | .segments_b (segments_b), 89 | .segments_c (segments_c), 90 | .segments_d (segments_d), 91 | .segments_e (segments_e), 92 | .segments_f (segments_f), 93 | .segments_g (segments_g), 94 | .dot (dot), 95 | .selector (selector), 96 | .pmodA_read (pmodA_read), 97 | .pmodA_write (pmodA_write), 98 | .pmodA_writeEnable (pmodA_writeEnable), 99 | .sSwitches (sSwitches), 100 | .pButtons (pButtons), 101 | .tck (tck), 102 | .tms (tms), 103 | .tdi (tdi), 104 | .tdo (tdo), 105 | .rx (rx), 106 | .tx (tx)); 107 | 108 | // Make the reset high active 109 | assign reset = !nreset; 110 | 111 | // Connect the pmodA read port 112 | assign pmodA_read = pmodA; 113 | 114 | // Generate the write port and equip it with tristate functionality 115 | genvar i; 116 | generate 117 | for (i = 0; i < 8; i = i + 1) begin 118 | assign pmodA[i] = pmodA_writeEnable[i] ? pmodA_write[i] : 1'bZ; 119 | end 120 | endgenerate 121 | 122 | endmodule 123 | 124 | -------------------------------------------------------------------------------- /src/main/verilog/arch/Nexys4DDR/Board_Nexys4DDR.v: -------------------------------------------------------------------------------- 1 | // 2 | // Author: Steffen Reith (Steffen.Reith@hs-rm.de) 3 | // 4 | // Creation Date: Sat Apr 8 21:13:17 GMT+2 2017 5 | // Module Name: Board_Nexys4DDR - Behavioral 6 | // Project Name: J1Sc - A simple J1 implementation in Scala using Spinal HDL 7 | // 8 | // 9 | 10 | module Board_Nexys4DDR (nreset, 11 | clk100Mhz, 12 | extInt, 13 | leds, 14 | rgbLeds, 15 | segments_a, 16 | segments_b, 17 | segments_c, 18 | segments_d, 19 | segments_e, 20 | segments_f, 21 | segments_g, 22 | dot, 23 | selector, 24 | pmodA, 25 | sSwitches, 26 | pButtons, 27 | tck, 28 | tms, 29 | tdi, 30 | tdo, 31 | rx, 32 | tx); 33 | 34 | // Input ports 35 | input nreset; 36 | input clk100Mhz; 37 | input [0:0] extInt; 38 | input [15:0] sSwitches; 39 | input [4:0] pButtons; 40 | input tck; 41 | input tms; 42 | input tdi; 43 | input rx; 44 | 45 | // Output ports 46 | output [15:0] leds; 47 | output [5:0] rgbLeds; 48 | output tdo; 49 | output tx; 50 | output segments_a; 51 | output segments_b; 52 | output segments_c; 53 | output segments_d; 54 | output segments_e; 55 | output segments_f; 56 | output segments_g; 57 | output dot; 58 | output [7:0] selector; 59 | 60 | // Bidirectional port 61 | inout [7:0] pmodA; 62 | 63 | // Internal reset 64 | wire reset; 65 | 66 | // Clock generation 67 | wire boardClk; 68 | wire boardClkLocked; 69 | 70 | // Internal wiring 71 | wire [7:0] pmodA_read; 72 | wire [7:0] pmodA_write; 73 | wire [7:0] pmodA_writeEnable; 74 | 75 | // Instantiate a PLL/MMCM (makes a 80Mhz clock) 76 | PLL makeClk (.clkIn (clk100Mhz), 77 | .clkOut (boardClk), 78 | .isLocked (boardClkLocked)); 79 | 80 | // Instantiate the J1SoC core generated by Spinal 81 | J1Nexys4X core (.reset (reset), 82 | .boardClk (boardClk), 83 | .boardClkLocked (boardClkLocked), 84 | .extInt (extInt), 85 | .leds (leds), 86 | .rgbLeds (rgbLeds), 87 | .segments_a (segments_a), 88 | .segments_b (segments_b), 89 | .segments_c (segments_c), 90 | .segments_d (segments_d), 91 | .segments_e (segments_e), 92 | .segments_f (segments_f), 93 | .segments_g (segments_g), 94 | .dot (dot), 95 | .selector (selector), 96 | .pmodA_read (pmodA_read), 97 | .pmodA_write (pmodA_write), 98 | .pmodA_writeEnable (pmodA_writeEnable), 99 | .sSwitches (sSwitches), 100 | .pButtons (pButtons), 101 | .tck (tck), 102 | .tms (tms), 103 | .tdi (tdi), 104 | .tdo (tdo), 105 | .rx (rx), 106 | .tx (tx)); 107 | 108 | // Make the reset high active 109 | assign reset = !nreset; 110 | 111 | // Connect the pmodA read port 112 | assign pmodA_read = pmodA; 113 | 114 | // Generate the write port and equip it with tristate functionality 115 | genvar i; 116 | generate 117 | for (i = 0; i < 8; i = i + 1) begin 118 | assign pmodA[i] = pmodA_writeEnable[i] ? pmodA_write[i] : 1'bZ; 119 | end 120 | endgenerate 121 | 122 | endmodule 123 | -------------------------------------------------------------------------------- /src/main/scala/Timer.scala: -------------------------------------------------------------------------------- 1 | /* 2 | * Author: Steffen Reith (Steffen.Reith@hs-rm.de) 3 | * 4 | * Creation Date: Sat Dec 3 17:33:06 GMT+1 2016 5 | * Module Name: Timer16 - A programmable timer which generates interrupts for a 16 bit bus interface 6 | * Project Name: J1Sc - A simple J1 implementation in Scala using Spinal HDL 7 | * 8 | */ 9 | import spinal.core._ 10 | import spinal.lib.bus.misc.BusSlaveFactory 11 | 12 | class Timer(cfg : TimerConfig) extends Component { 13 | 14 | // The width has to be even to be split into two halfs 15 | assert(cfg.width % 2 == 0, message = "ERROR: Timer width has to be even!") 16 | 17 | val io = new Bundle { 18 | 19 | val loadHigh = in Bool 20 | val loadLow = in Bool 21 | val cmpHigh = in UInt(cfg.width / 2 bits) 22 | val cmpLow = in UInt(cfg.width / 2 bits) 23 | 24 | val enable = in Bits(cfg.width / 2 bits) 25 | val accessEnableWrite = in Bool 26 | val enableState = out Bits(cfg.width / 2 bits) 27 | 28 | val highState = out UInt(cfg.width / 2 bits) 29 | val lowState = out UInt(cfg.width / 2 bits) 30 | 31 | val interrupt = out Bool 32 | 33 | }.setName("") 34 | 35 | // Register for holding the counter 36 | val cnt = Reg(UInt(cfg.width bits)) init(0) 37 | 38 | // Compare register (maximal values to count to) 39 | val cmp = Reg(UInt(cfg.width bits)) init(0) 40 | 41 | // Split the compare register into high and low part 42 | io.highState := cmp(cmp.high downto cfg.width / 2) 43 | io.lowState := cmp(cfg.width / 2 - 1 downto 0) 44 | 45 | // Register the enable flag (adapt the width for the 1 bit register) 46 | val isEnabled = RegNextWhen(io.enable.orR, io.accessEnableWrite) init(False) 47 | io.enableState := (default -> isEnabled) 48 | 49 | // Check if the low word of the compare register has to be loaded 50 | when(io.loadLow) { 51 | 52 | // Load the compare value, reset the timer and disable it 53 | cmp(cfg.width / 2 - 1 downto 0) := io.cmpLow 54 | isEnabled := False 55 | cnt := 0 56 | 57 | } 58 | 59 | // Check if the high word of the compare register has to be loaded 60 | when(io.loadHigh) { 61 | 62 | // Load the compare value, reset the timer and disable it 63 | cmp(cmp.high downto cfg.width / 2) := io.cmpHigh 64 | isEnabled := False 65 | cnt := 0 66 | 67 | } 68 | 69 | // Maximal value of counter 70 | val maxCnt = cmp - 1 71 | 72 | // Check if the timer is enabled 73 | when(isEnabled && !(io.loadHigh || io.loadLow)) { 74 | 75 | // Count modulo 76 | when(cnt < maxCnt) { 77 | 78 | // Increment the timer 79 | cnt := cnt + 1 80 | 81 | }.otherwise { 82 | 83 | // Reset the timer 84 | cnt := 0 85 | 86 | } 87 | 88 | } 89 | 90 | // Generate the interrupt signal 91 | io.interrupt := isEnabled && (cnt === maxCnt) && !(io.loadHigh || io.loadLow) 92 | 93 | // Implement the bus interface 94 | def driveFrom(busCtrl : BusSlaveFactory, baseAddress : BigInt) : Area = new Area { 95 | 96 | // The lower part of the compare register is mapped at address 0 and is of type r/w 97 | busCtrl.read(io.lowState, baseAddress + 0, bitOffset = 0) 98 | busCtrl.nonStopWrite(io.cmpLow, bitOffset = 0) // value will be constantly driven by the data of the memory bus 99 | 100 | // The higher part of the compare register is mapped at address 0 and is of type r/w 101 | busCtrl.read(io.highState, baseAddress + 1, bitOffset = 0) 102 | busCtrl.nonStopWrite(io.cmpHigh, bitOffset = 0) // value will be constantly driven by the data of the memory bus 103 | 104 | // Generate the write enable signals for loading the compare value 105 | io.loadLow := busCtrl.isWriting(baseAddress + 0) 106 | io.loadHigh := busCtrl.isWriting(baseAddress + 1) 107 | 108 | // A r/w register for enabling the timer (anything != 0 means true) 109 | busCtrl.read(io.enableState, baseAddress + 2, bitOffset = 0) 110 | busCtrl.nonStopWrite(io.enable, bitOffset = 0) // the enable signal is constantly driven by the data of the memory bus 111 | 112 | // Generate a flag for write access of io.enable 113 | io.accessEnableWrite := busCtrl.isWriting(baseAddress + 2) 114 | 115 | } 116 | 117 | } 118 | -------------------------------------------------------------------------------- /toolchain/forth/demos/ps2.fs: -------------------------------------------------------------------------------- 1 | here cp @ 2 | 5 constant CLK 4 constant DAT 3 | : CLK@ CLK io@ ; : DAT@ DAT io@ ; 4 | 5 | : fall begin CLK@ until begin CLK@ 0= until ; 6 | : getbit ( -- u ) fall DAT@ ; 7 | : kb? CLK@ DAT@ + 0= ; 8 | : rx ( -- code ) 9 | begin kb? until 10 | 0 11 | 8 0 do getbit i lshift + loop 12 | getbit getbit 2drop ; 13 | 14 | : low ( pin ) 0 over io! OUTPUT swap pinMode ; 15 | : release ( pin ) INPUT swap pinMode ; 16 | : tx1 1 and if 4 release else 4 low then fall ; 17 | : tx ( code -- ) 18 | CLK low 1 ms DAT low CLK release fall 19 | 0 8 0 do 20 | over i rshift dup tx1 21 | + \ accumulate parity 22 | loop 23 | 1+ tx1 drop \ send odd parity 24 | DAT release 25 | fall begin CLK@ DAT@ and until ; 26 | : leds ( x -- ) $ed tx rx drop tx rx drop ; 27 | 28 | variable make \ is this a key-make event? 29 | variable mods \ Modifiers. Mask bits are: 30 | \ 1 2 4 8 31 | \ shift caps ctrl 32 | 33 | : ismake ( code -- code|0 ) make @ and make on ; 34 | : ?m ( msk -- f ) mods @ and 0<> ; 35 | : mx ( mask -- 0 ) ismake mods @ xor mods ! 0 ; 36 | : m! ( msk -- 0 ) dup invert mods @ and mods ! mx ; 37 | 38 | : alpha ( u -- ) 39 | 1 ?m 2 ?m xor $20 and - \ upper/lower case 40 | 4 ?m if $1f and then \ control key 41 | ismake ; 42 | : shift 43 | 1 ?m if nip else drop then 44 | ismake ; 45 | 46 | create _ $80 cells allot : dx cells _ + ; 47 | : ;op postpone ; swap dx ! ; immediate 48 | 49 | $00 :noname 0 ;op 50 | $12 :noname 1 m! ;op ( LEFT SHIFT ) 51 | $12 dx @ $59 dx ! ( RIGHT SHIFT ) 52 | $58 :noname 2 mx ;op ( CAPS ) 53 | $14 :noname 4 m! ;op ( CONTROL ) 54 | 55 | $0d :noname $09 ismake ;op ( TAB ) 56 | $29 :noname $20 ismake ;op ( SPACE ) 57 | $5a :noname $0a ismake ;op ( ENTER ) 58 | $66 :noname $08 ismake ;op ( BKSP ) 59 | $7c :noname '*' ismake ;op ( ASTERISK ) 60 | $7b :noname '-' ismake ;op ( MINUS ) 61 | $79 :noname '+' ismake ;op ( PLUS ) 62 | 63 | $15 :noname 'q' alpha ;op $31 :noname 'n' alpha ;op 64 | $1a :noname 'z' alpha ;op $32 :noname 'b' alpha ;op 65 | $1b :noname 's' alpha ;op $33 :noname 'h' alpha ;op 66 | $1c :noname 'a' alpha ;op $34 :noname 'g' alpha ;op 67 | $1d :noname 'w' alpha ;op $35 :noname 'y' alpha ;op 68 | $21 :noname 'c' alpha ;op $3a :noname 'm' alpha ;op 69 | $22 :noname 'x' alpha ;op $3b :noname 'j' alpha ;op 70 | $23 :noname 'd' alpha ;op $3c :noname 'u' alpha ;op 71 | $24 :noname 'e' alpha ;op $42 :noname 'k' alpha ;op 72 | $2a :noname 'v' alpha ;op $43 :noname 'i' alpha ;op 73 | $2b :noname 'f' alpha ;op $44 :noname 'o' alpha ;op 74 | $2c :noname 't' alpha ;op $4b :noname 'l' alpha ;op 75 | $2d :noname 'r' alpha ;op $4d :noname 'p' alpha ;op 76 | 77 | $0e :noname '`' '~' shift ;op $46 :noname '9' '(' shift ;op 78 | $16 :noname '1' '!' shift ;op $49 :noname '.' '>' shift ;op 79 | $1e :noname '2' '@' shift ;op $4a :noname '/' '?' shift ;op 80 | $25 :noname '4' '$' shift ;op $4c :noname ';' ':' shift ;op 81 | $26 :noname '3' '#' shift ;op $4e :noname '-' '_' shift ;op 82 | $2e :noname '5' '%' shift ;op $52 :noname ''' '"' shift ;op 83 | $36 :noname '6' '^' shift ;op $54 :noname '[' '{' shift ;op 84 | $3d :noname '7' '&' shift ;op $55 :noname '=' '+' shift ;op 85 | $3e :noname '8' '*' shift ;op $5b :noname ']' '}' shift ;op 86 | $41 :noname ',' '<' shift ;op $5d :noname '\' '|' shift ;op 87 | $45 :noname '0' ')' shift ;op 88 | 89 | : graw 90 | rx 91 | $f0 over = if drop 0 make off then 92 | $e0 over = if drop 0 then 93 | dx @ execute ; 94 | 95 | : /kb mods off make on ; 96 | 97 | : debug begin rx hex2. again ; 98 | 99 | : x 100 | /kb 101 | begin graw .x depth throw cr again ; 102 | 103 | : q /kb begin graw ?dup if emit then again ; 104 | 105 | cp @ swap - . cr 106 | here swap - . cr 107 | 108 | : x 8 0 do i leds 100 ms loop ; 109 | 110 | : soak 111 | 0 112 | begin 113 | dup . 114 | dup 7 and leds 115 | 1+ 116 | again ; 117 | -------------------------------------------------------------------------------- /src/test/vhdl/J1Nexys4X_tb.vhd: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- 2 | -- Author: Steffen.Reith (Steffen.Reith@hs-rm.de) 3 | -- 4 | -- Creation Date: Thu Oct 13 20:44:40 GMT+2 2016 5 | -- Creator: Steffen Reith 6 | -- Module Name: J1SoC_TB - A simple testbench for the J1 SoC 7 | -- Project Name: J1Sc - A simple J1 implementation in scala 8 | -- 9 | -------------------------------------------------------------------------------- 10 | library ieee; 11 | use ieee.std_logic_1164.all; 12 | use ieee.numeric_std.all; 13 | 14 | library std; 15 | use std.textio.all; 16 | 17 | entity J1Nexys4X_tb is 18 | end J1Nexys4X_tb; 19 | 20 | architecture Behavioral of J1Nexys4X_tb is 21 | 22 | -- Clock period definition (100Mhz) 23 | constant clk_period : time := 10 ns; 24 | 25 | -- Interrupts 26 | signal extInt : std_logic_vector(0 downto 0) := "0"; 27 | 28 | -- PModA-Interface 29 | signal pmodA_read : std_logic_vector(7 downto 0); 30 | signal pmodA_write : std_logic_vector(7 downto 0); 31 | signal pmodA_writeEnable : std_logic_vector(7 downto 0); 32 | 33 | -- UART signals 34 | signal rx : std_logic := '0'; 35 | signal tx : std_logic; 36 | 37 | -- I/O signals 38 | signal leds : std_logic_vector(15 downto 0); 39 | signal rgbLeds : std_logic_vector(5 downto 0); 40 | signal segments_a : std_logic; 41 | signal segments_b : std_logic; 42 | signal segments_c : std_logic; 43 | signal segments_d : std_logic; 44 | signal segments_e : std_logic; 45 | signal segments_f : std_logic; 46 | signal segments_g : std_logic; 47 | signal dot : std_logic; 48 | signal selector : std_logic_vector(7 downto 0); 49 | signal sSwitches : std_logic_vector(15 downto 0) := (others => '0'); 50 | signal pButtons : std_logic_vector(4 downto 0) := (others => '0'); 51 | 52 | -- Clock and reset 53 | signal boardClkLocked : std_logic; 54 | signal boardClk : std_logic; 55 | signal reset : std_logic; 56 | 57 | begin 58 | 59 | uut : entity work.J1Nexys4X 60 | port map (boardClk => boardClk, 61 | boardClkLocked => boardClkLocked, 62 | reset => reset, 63 | extInt => extInt, 64 | pmodA_read => pmodA_read, 65 | pmodA_write => pmodA_write, 66 | pmodA_writeEnable => pmodA_writeEnable, 67 | rgbLeds => rgbLeds, 68 | segments_a => segments_a, 69 | segments_b => segments_b, 70 | segments_c => segments_c, 71 | segments_d => segments_d, 72 | segments_e => segments_e, 73 | segments_f => segments_f, 74 | segments_g => segments_g, 75 | dot => dot, 76 | selector => selector, 77 | sSwitches => sSwitches, 78 | pButtons => pButtons, 79 | rx => rx, 80 | tx => tx, 81 | leds => leds); 82 | 83 | -- Clock process definitions 84 | clk_process : process 85 | begin 86 | 87 | -- Tell that the clock is stable 88 | boardClkLocked <= '1'; 89 | 90 | boardClk <= '0'; 91 | wait for clk_period/2; 92 | 93 | boardClk <= '1'; 94 | wait for clk_period/2; 95 | 96 | end process; 97 | 98 | reboot_proc : process 99 | begin 100 | 101 | -- Init the read port of PModA 102 | pmodA_read <= (others => '0'); 103 | 104 | -- Reset the CPU (asynchronous) 105 | reset <= '1'; 106 | 107 | -- Wait 57ns 108 | wait for 57 ns; 109 | 110 | -- Revoke the the reset 111 | reset <= '0'; 112 | 113 | -- Wait forever 114 | wait; 115 | 116 | end process; 117 | 118 | 119 | -- Stimulus process 120 | stim_proc : process 121 | 122 | -- Text I/O 123 | variable lineBuffer : line; 124 | 125 | begin 126 | 127 | -- Give a info message 128 | write(lineBuffer, string'("Start the simulation of the CPU")); 129 | writeline(output, lineBuffer); 130 | 131 | -- Simply wait forever 132 | wait; 133 | 134 | end process; 135 | 136 | end architecture; 137 | -------------------------------------------------------------------------------- /src/main/vhdl/arch/Nexys4/Board_Nexys4.vhd: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- 2 | -- 3 | -- Creation Date: Sat May 6 16:30:50 GMT+2 2017 4 | -- Creator: Steffen Reith 5 | -- Module Name: Board_Nexys4 - Behavioral 6 | -- Project Name: J1Sc - A simple J1 implementation in Scala using Spinal HDL 7 | -- 8 | -- Remark: The pmod pins are renumberd as follows 1 -> 0, 2 -> 1, 3 -> 2, 9 | -- 4 -> 3, 7 -> 4, 8 -> 5, 9 -> 6, 10 -> 7 10 | -- 11 | -------------------------------------------------------------------------------- 12 | 13 | library ieee; 14 | use ieee.std_logic_1164.all; 15 | 16 | entity Board_Nexys4 is 17 | 18 | port (nreset : in std_logic; 19 | clk100Mhz : in std_logic; 20 | extInt : in std_logic_vector(0 downto 0); 21 | leds : out std_logic_vector(15 downto 0); 22 | rgbLeds : out std_logic_vector(5 downto 0); 23 | segments_a : out std_logic; 24 | segments_b : out std_logic; 25 | segments_c : out std_logic; 26 | segments_d : out std_logic; 27 | segments_e : out std_logic; 28 | segments_f : out std_logic; 29 | segments_g : out std_logic; 30 | dot : out std_logic; 31 | selector : out std_logic_vector(7 downto 0); 32 | pmodA : inout std_logic_vector(7 downto 0); 33 | sSwitches : in std_logic_vector(15 downto 0); 34 | pButtons : in std_logic_vector(4 downto 0); 35 | tck : in std_logic; 36 | tms : in std_logic; 37 | tdi : in std_logic; 38 | tdo : out std_logic; 39 | rx : in std_logic; 40 | tx : out std_logic); 41 | 42 | end Board_Nexys4; 43 | 44 | architecture Structural of Board_Nexys4 is 45 | 46 | -- Positive reset signal 47 | signal reset : std_logic; 48 | 49 | -- Signals related to the board clk 50 | signal boardClk : std_logic; 51 | signal boardClkLocked : std_logic; 52 | 53 | -- Interface for PModA 54 | signal pmodA_read : std_logic_vector(7 downto 0); 55 | signal pmodA_write : std_logic_vector(7 downto 0); 56 | signal pmodA_writeEnable : std_logic_vector(7 downto 0); 57 | 58 | begin 59 | 60 | -- Instantiate a PLL/MMCM (makes a 80Mhz clock) 61 | makeClk : entity work.PLL(Structural) 62 | port map (clkIn => clk100Mhz, 63 | clkOut => boardClk, 64 | isLocked => boardClkLocked); 65 | 66 | -- Make the reset high active 67 | reset <= not nreset; 68 | 69 | -- Instantiate the J1SoC core created by Spinal 70 | core : entity work.J1Nexys4X 71 | port map (reset => reset, 72 | boardClk => boardClk, 73 | boardClkLocked => boardClkLocked, 74 | extInt => extInt, 75 | leds => leds, 76 | rgbLeds => rgbLeds, 77 | segments_a => segments_a, 78 | segments_b => segments_b, 79 | segments_c => segments_c, 80 | segments_d => segments_d, 81 | segments_e => segments_e, 82 | segments_f => segments_f, 83 | segments_g => segments_g, 84 | dot => dot, 85 | selector => selector, 86 | pmodA_read => pmodA_read, 87 | pmodA_write => pmodA_write, 88 | pmodA_writeEnable => pmodA_writeEnable, 89 | sSwitches => sSwitches, 90 | pButtons => pButtons, 91 | tck => tck, 92 | tms => tms, 93 | tdi => tdi, 94 | tdo => tdo, 95 | rx => rx, 96 | tx => tx); 97 | 98 | -- Connect the pmodA read port 99 | pmodA_read <= pmodA; 100 | 101 | -- generate the write port and equip it with tristate functionality 102 | pmodAGen : for i in pmodA'range generate 103 | pmodA(i) <= pmodA_write(i) when pmodA_writeEnable(i) = '1' else 'Z'; 104 | end generate; 105 | 106 | end architecture; 107 | 108 | -------------------------------------------------------------------------------- /src/main/vhdl/arch/Nexys4DDR/Board_Nexys4DDR.vhd: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- 2 | -- 3 | -- Creation Date: Fri Apr 7 16:00:52 GMT+2 2017 4 | -- Creator: Steffen Reith 5 | -- Module Name: Board_Nexys4DDR - Behavioral 6 | -- Project Name: J1Sc - A simple J1 implementation in Scala using Spinal HDL 7 | -- 8 | -- Remark: The pmod pins are renumberd as follows 1 -> 0, 2 -> 1, 3 -> 2, 9 | -- 4 -> 3, 7 -> 4, 8 -> 5, 9 -> 6, 10 -> 7 10 | -- 11 | -------------------------------------------------------------------------------- 12 | 13 | library ieee; 14 | use ieee.std_logic_1164.all; 15 | 16 | entity Board_Nexys4DDR is 17 | 18 | port (nreset : in std_logic; 19 | clk100Mhz : in std_logic; 20 | extInt : in std_logic_vector(0 downto 0); 21 | leds : out std_logic_vector(15 downto 0); 22 | rgbLeds : out std_logic_vector(5 downto 0); 23 | segments_a : out std_logic; 24 | segments_b : out std_logic; 25 | segments_c : out std_logic; 26 | segments_d : out std_logic; 27 | segments_e : out std_logic; 28 | segments_f : out std_logic; 29 | segments_g : out std_logic; 30 | dot : out std_logic; 31 | selector : out std_logic_vector(7 downto 0); 32 | pmodA : inout std_logic_vector(7 downto 0); 33 | sSwitches : in std_logic_vector(15 downto 0); 34 | pButtons : in std_logic_vector(4 downto 0); 35 | tck : in std_logic; 36 | tms : in std_logic; 37 | tdi : in std_logic; 38 | tdo : out std_logic; 39 | rx : in std_logic; 40 | tx : out std_logic); 41 | 42 | end Board_Nexys4DDR; 43 | 44 | architecture Structural of Board_Nexys4DDR is 45 | 46 | -- Positive reset signal 47 | signal reset : std_logic; 48 | 49 | -- Signals related to the board clk 50 | signal boardClk : std_logic; 51 | signal boardClkLocked : std_logic; 52 | 53 | -- Interface for PModA 54 | signal pmodA_read : std_logic_vector(7 downto 0); 55 | signal pmodA_write : std_logic_vector(7 downto 0); 56 | signal pmodA_writeEnable : std_logic_vector(7 downto 0); 57 | 58 | begin 59 | 60 | -- Instantiate a PLL/MMCM (makes a 80Mhz clock) 61 | makeClk : entity work.PLL(Structural) 62 | port map (clkIn => clk100Mhz, 63 | clkOut => boardClk, 64 | isLocked => boardClkLocked); 65 | 66 | -- Make the reset positive 67 | reset <= not nreset; 68 | 69 | -- Instantiate the J1SoC core created by Spinal 70 | core : entity work.J1Nexys4X 71 | port map (reset => reset, 72 | boardClk => boardClk, 73 | boardClkLocked => boardClkLocked, 74 | extInt => extInt, 75 | leds => leds, 76 | rgbLeds => rgbLeds, 77 | segments_a => segments_a, 78 | segments_b => segments_b, 79 | segments_c => segments_c, 80 | segments_d => segments_d, 81 | segments_e => segments_e, 82 | segments_f => segments_f, 83 | segments_g => segments_g, 84 | dot => dot, 85 | selector => selector, 86 | pmodA_read => pmodA_read, 87 | pmodA_write => pmodA_write, 88 | pmodA_writeEnable => pmodA_writeEnable, 89 | sSwitches => sSwitches, 90 | pButtons => pButtons, 91 | tck => tck, 92 | tms => tms, 93 | tdi => tdi, 94 | tdo => tdo, 95 | rx => rx, 96 | tx => tx); 97 | 98 | -- Connect the pmodA read port 99 | pmodA_read <= pmodA; 100 | 101 | -- generate the write port and equip it with tristate functionality 102 | pmodAGen : for i in pmodA'range generate 103 | pmodA(i) <= pmodA_write(i) when pmodA_writeEnable(i) = '1' else 'Z'; 104 | end generate; 105 | 106 | end architecture; 107 | -------------------------------------------------------------------------------- /src/main/scala/InterruptCtrl.scala: -------------------------------------------------------------------------------- 1 | /* 2 | * Author: Steffen Reith (Steffen.Reith@hs-rm.de) 3 | * 4 | * Creation Date: Fri Nov 25 13:04:23 GMT+1 2016 5 | * Module Name: InterruptCtrl - A small interrupt controller for the J1 CPU 6 | * Project Name: J1Sc - A simple J1 implementation in Scala using Spinal HDL 7 | * 8 | */ 9 | import spinal.core._ 10 | import spinal.lib._ 11 | import spinal.lib.bus.misc.BusSlaveFactory 12 | 13 | class InterruptCtrl(cfg : J1Config) extends Component { 14 | 15 | // Check the number of interrupts 16 | assert(isPow2(cfg.irqConfig.numOfInterrupts), "WARNING: Specify a power of 2 as number of interrupts") 17 | 18 | // Physical interrupt request signals 19 | val io = new Bundle { 20 | 21 | val irqReqs = in Bits (cfg.irqConfig.numOfInterrupts bits) 22 | 23 | }.setName("") 24 | 25 | // Signals used for the internal bus 26 | val bus = new Bundle { 27 | 28 | val enableWriteNewMask = in Bool 29 | val enableWriteIrqVec = in Bits (cfg.irqConfig.numOfInterrupts bits) 30 | 31 | val irqSetData = in Bits (cfg.wordSize bits) 32 | 33 | val irqGetMask = out Bits (cfg.wordSize bits) 34 | val irqVectors = out Vec(Bits(cfg.wordSize bits), cfg.irqConfig.numOfInterrupts) 35 | 36 | }.setName("") 37 | 38 | // Internally used signals 39 | val internal = new Bundle { 40 | 41 | val intVec = out Bits(cfg.wordSize bits) 42 | val irq = out Bool 43 | 44 | }.setName("") 45 | 46 | // Register the irq mask (disable all interrupts after reset) 47 | val irqMask = RegNextWhen(bus.irqSetData.resize(cfg.irqConfig.numOfInterrupts), 48 | bus.enableWriteNewMask, 49 | B(cfg.irqConfig.numOfInterrupts bits, default -> False)) 50 | 51 | // Generate an output version of the current mask 52 | bus.irqGetMask := irqMask.resize(cfg.wordSize) 53 | 54 | // Enable signals for the interrupt vectors 55 | val irqVecWriteEnable = Bits(cfg.irqConfig.numOfInterrupts bits) 56 | irqVecWriteEnable := bus.enableWriteIrqVec.resize(cfg.irqConfig.numOfInterrupts) 57 | 58 | // Create a register file for storing the interrupt vectors 59 | val irqVectors = Vec(for(i <- 0 until cfg.irqConfig.numOfInterrupts) yield { 60 | 61 | // Create the ith register and truncate data read from the bus 62 | RegNextWhen((bus.irqSetData >> 1).resize(cfg.adrWidth), 63 | irqVecWriteEnable(i), 64 | B(cfg.adrWidth bits, default -> False)) 65 | 66 | }) 67 | 68 | // Wire all interrupt vectors to an IO-port 69 | (bus.irqVectors, irqVectors).zipped.foreach(_ := _.resize(cfg.wordSize)) 70 | 71 | // All interrupts are asynchronous, hence make them synchron 72 | val irqSync = BufferCC(io.irqReqs, 73 | init = B(0, cfg.irqConfig.numOfInterrupts bits), 74 | bufferDepth = cfg.irqConfig.irqLatency) 75 | 76 | // Check all interrupts with priority from 0 (high) to noOfInterrupts - 1 (low) 77 | val intNo = OHToUInt(OHMasking.first(irqSync)) 78 | 79 | // Provide the corresponding interrupt vector 80 | internal.intVec := irqVectors(intNo).resize(cfg.wordSize) 81 | 82 | // Generate a rising edge when an interrupt has happened (init value is false) 83 | internal.irq := (irqSync & irqMask).orR.rise(False) 84 | 85 | // Implement the bus interface 86 | def driveFrom(busCtrl : BusSlaveFactory, baseAddress : BigInt) = new Area { 87 | 88 | // A read port for the interrupt mask 89 | busCtrl.read(bus.irqGetMask, baseAddress + cfg.irqConfig.numOfInterrupts, 0) 90 | 91 | // The enable signal is constantly driven by the data of the memory bus 92 | busCtrl.nonStopWrite(bus.irqSetData, 0) 93 | 94 | // Generate the write enable signal for the interrupt mask 95 | bus.enableWriteNewMask := busCtrl.isWriting(baseAddress + cfg.irqConfig.numOfInterrupts) 96 | 97 | // r/w-registers for all irq-vectors 98 | for (i <- 0 until cfg.irqConfig.numOfInterrupts) { 99 | 100 | // A r/w register access for the ith interrupt vector 101 | busCtrl.read(bus.irqVectors(i), baseAddress + i, 0) 102 | 103 | // Generate the write enable signal for the ith interrupt vector 104 | bus.enableWriteIrqVec(i) := busCtrl.isWriting(baseAddress + i) 105 | 106 | } 107 | 108 | } 109 | 110 | } 111 | -------------------------------------------------------------------------------- /vprj/vhdl/J1Sc/J1Sc/J1Sc.srcs/sources_1/imports/J1Sc/src/main/vhdl/arch/Nexys4DDR/Board_Nexys4DDR.vhd: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- 2 | -- 3 | -- Creation Date: Fri Apr 7 16:00:52 GMT+2 2017 4 | -- Creator: Steffen Reith 5 | -- Module Name: Board_Nexys4DDR - Behavioral 6 | -- Project Name: J1Sc - A simple J1 implementation in Scala using Spinal HDL 7 | -- 8 | -- Remark: The pmod pins are renumberd as follows 1 -> 0, 2 -> 1, 3 -> 2, 9 | -- 4 -> 3, 7 -> 4, 8 -> 5, 9 -> 6, 10 -> 7 10 | -- 11 | -------------------------------------------------------------------------------- 12 | 13 | library ieee; 14 | use ieee.std_logic_1164.all; 15 | 16 | entity Board_Nexys4DDR is 17 | 18 | port (nreset : in std_logic; 19 | clk100Mhz : in std_logic; 20 | extInt : in std_logic_vector(0 downto 0); 21 | leds : out std_logic_vector(15 downto 0); 22 | rgbLeds : out std_logic_vector(5 downto 0); 23 | segments_a : out std_logic; 24 | segments_b : out std_logic; 25 | segments_c : out std_logic; 26 | segments_d : out std_logic; 27 | segments_e : out std_logic; 28 | segments_f : out std_logic; 29 | segments_g : out std_logic; 30 | dot : out std_logic; 31 | selector : out std_logic_vector(7 downto 0); 32 | pmodA : inout std_logic_vector(7 downto 0); 33 | sSwitches : in std_logic_vector(15 downto 0); 34 | pButtons : in std_logic_vector(4 downto 0); 35 | tck : in std_logic; 36 | tms : in std_logic; 37 | tdi : in std_logic; 38 | tdo : out std_logic; 39 | rx : in std_logic; 40 | tx : out std_logic); 41 | 42 | end Board_Nexys4DDR; 43 | 44 | architecture Structural of Board_Nexys4DDR is 45 | 46 | -- Positive reset signal 47 | signal reset : std_logic; 48 | 49 | -- Signals related to the board clk 50 | signal boardClk : std_logic; 51 | signal boardClkLocked : std_logic; 52 | 53 | -- Interface for PModA 54 | signal pmodA_read : std_logic_vector(7 downto 0); 55 | signal pmodA_write : std_logic_vector(7 downto 0); 56 | signal pmodA_writeEnable : std_logic_vector(7 downto 0); 57 | 58 | begin 59 | 60 | -- Instantiate a PLL/MMCM (makes a 80Mhz clock) 61 | makeClk : entity work.PLL(Structural) 62 | port map (clkIn => clk100Mhz, 63 | clkOut => boardClk, 64 | isLocked => boardClkLocked); 65 | 66 | -- Make the reset positive 67 | reset <= not nreset; 68 | 69 | -- Instantiate the J1SoC core created by Spinal 70 | core : entity work.J1Nexys4X 71 | port map (reset => reset, 72 | boardClk => boardClk, 73 | boardClkLocked => boardClkLocked, 74 | extInt => extInt, 75 | leds => leds, 76 | rgbLeds => rgbLeds, 77 | segments_a => segments_a, 78 | segments_b => segments_b, 79 | segments_c => segments_c, 80 | segments_d => segments_d, 81 | segments_e => segments_e, 82 | segments_f => segments_f, 83 | segments_g => segments_g, 84 | dot => dot, 85 | selector => selector, 86 | pmodA_read => pmodA_read, 87 | pmodA_write => pmodA_write, 88 | pmodA_writeEnable => pmodA_writeEnable, 89 | sSwitches => sSwitches, 90 | pButtons => pButtons, 91 | tck => tck, 92 | tms => tms, 93 | tdi => tdi, 94 | tdo => tdo, 95 | rx => rx, 96 | tx => tx); 97 | 98 | -- Connect the pmodA read port 99 | pmodA_read <= pmodA; 100 | 101 | -- generate the write port and equip it with tristate functionality 102 | pmodAGen : for i in pmodA'range generate 103 | pmodA(i) <= pmodA_write(i) when pmodA_writeEnable(i) = '1' else 'Z'; 104 | end generate; 105 | 106 | end architecture; 107 | -------------------------------------------------------------------------------- /vprj/vhdl/J1Sc/J1SoC_tb_behav.wcfg: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | boardClk 30 | boardClk 31 | 32 | 33 | core_reset 34 | core_reset 35 | 36 | 37 | pc[12:0] 38 | pc[12:0] 39 | 40 | 41 | memInstr[15:0] 42 | memInstr[15:0] 43 | 44 | 45 | memWriteMode 46 | memWriteMode 47 | 48 | 49 | isALU 50 | isALU 51 | 52 | 53 | isCall 54 | isCall 55 | 56 | 57 | isHighCall 58 | isHighCall 59 | 60 | 61 | dStackWrite 62 | dStackWrite 63 | 64 | 65 | dtos[15:0] 66 | dtos[15:0] 67 | 68 | 69 | dnos[15:0] 70 | dnos[15:0] 71 | 72 | 73 | rStackWrite 74 | rStackWrite 75 | 76 | 77 | rtos[15:0] 78 | rtos[15:0] 79 | 80 | 81 | leds[15:0] 82 | leds[15:0] 83 | 84 | 85 | -------------------------------------------------------------------------------- /toolchain/forth/common/peripheral.fs: -------------------------------------------------------------------------------- 1 | \ \ 2 | \ 3 | \ Author: Steffen Reith (Steffen.Reith@hs-rm.de) 4 | \ 5 | \ Creation Date: Wed Feb 22 22:05:05 GMT+1 2017 6 | \ Module Name: peripheral - holds all words to work with the common peripherals 7 | \ provided by a Nexys4 DDR2 board from Digilent 8 | \ Project Name: J1Sc - A simple J1 implementation in Scala using Spinal HDL 9 | \ 10 | \ \ 11 | 12 | : ledsbase ( -- c) \ push the base address of the LED array 13 | $40 14 | ; 15 | 16 | ( c -- ) \ write value to LED-register 17 | : leds! 18 | ledsbase io! 19 | ; 20 | 21 | ( -- c) \ read the current value of the LED-register 22 | : leds@ 23 | ledsbase io@ 24 | ; 25 | 26 | : rgbbase ( -- c) \ push the base address of RGB leds 27 | $50 28 | ; 29 | 30 | : rgbled! ( r g b n -- ) \ write the rgb value to the n-th rgb-led 31 | dup 2* + rgbbase + \ calculate the base address of n-th rgb-led 32 | dup -rot \ duplicate base address and save it for later use 33 | 2 + io! \ write blue 34 | dup -rot \ duplicate base address and save it for later use 35 | 1 + io! \ write green 36 | io! \ write red 37 | ; 38 | 39 | : rgbled@ ( n -- r g b) \ read the rgb value of the n-th rgb-led 40 | dup 2* + rgbbase + \ calculate the base addresse of the n-th rgb-led 41 | dup io@ \ read the red value 42 | swap \ get the base address again 43 | dup 1 + io@ \ read the green value 44 | swap \ get the base address again 45 | 2 + io@ \ read the blue value 46 | ; 47 | 48 | : ssdbase ( -- c) \ push the base address for the seven segment displays 49 | $60 50 | ; 51 | 52 | : ssd@ ( n -- v) \ read the value of the nth display 53 | ssdbase + \ calulate the address of the nth display 54 | io@ \ push the value 55 | ; 56 | 57 | : ssd! ( v n -- ) \ write the value v to the n-th display 58 | ssdbase + \ calculate address of n-th display 59 | io! \ write the value 60 | ; 61 | 62 | : ssdMask@ ( -- v) \ read the current ssd mask 63 | ssdbase 8 + \ get address of ssd mask register 64 | io@ \ push the value 65 | ; 66 | 67 | : ssdMask! ( v -- ) \ write value to the ssd mask register 68 | ssdbase 8 + \ get address of ssd mask register 69 | io! \ write the value 70 | ; 71 | 72 | : setDot ( n -- ) \ set dot of n-th display 73 | dup \ save display number 74 | ssd@ \ get value of display 75 | $8000 or \ set the dot 76 | swap \ get display number on stack top 77 | ssd! \ write the new value 78 | ; 79 | 80 | : clearDot ( n -- ) \ clear dot of n-th display 81 | dup \ save display number 82 | ssd@ \ get value of display 83 | $7fff and \ clear the dot 84 | swap \ get display number on stack top 85 | ssd! \ write the new value 86 | ; 87 | 88 | : pmodAbase ( -- c) \ push the base address of port A 89 | $70 90 | ; 91 | 92 | : pmodADir! ( c -- ) \ write to the directions register of port A 93 | pmodAbase io! 94 | ; 95 | 96 | : pmodADir@ ( -- c) \ read from the directions register of port A 97 | pmodAbase io@ 98 | ; 99 | 100 | : pmodA! ( c -- ) \ write value to port A 101 | pmodAbase 4 + io! 102 | ; 103 | 104 | : pmodA@ ( -- c) \ read the value from port A 105 | pmodAbase 4 + io@ 106 | ; 107 | 108 | : sSwitchBase ( -- c) \ push the base address of slider switch array 109 | $80 110 | ; 111 | 112 | : sSw@ ( -- c) \ read the debounced value from the slider switch array 113 | sSwitchBase io@ 114 | ; 115 | 116 | : pBtnBase ( -- c ) \ push the base address of push button array 117 | $90 118 | ; 119 | 120 | : pBtn@ ( -- c) \ read the debounced value from the push button array 121 | pBtnBase io@ 122 | ; 123 | 124 | : tABase ( -- c ) \ push the base address of timer A 125 | $c0 126 | ; 127 | 128 | : ltA! ( c -- ) \ write the value on tos to the low part of timer A 129 | tABase 0 + io! 130 | ; 131 | 132 | : htA! ( c -- ) \ write the value on tos to the high part of timer A 133 | tABase 1 + io! 134 | ; 135 | 136 | : entA ( -- ) \ enable timer A 137 | 1 tABase 2 + io! 138 | ; 139 | 140 | : distA ( -- ) \ disable timer A 141 | 0 tABase 2 + io! 142 | ; 143 | 144 | : iBase ( -- c ) \ push the interrupt controller base address 145 | $e0 146 | ; 147 | 148 | : ivec! ( a c -- ) \ write address a to interrupt vector c 149 | iBase + io! 150 | ; 151 | 152 | : imask! ( c -- ) \ write interrupt mask 153 | iBase 4 + io! 154 | ; 155 | 156 | : imask@ ( -- c) \ get interrupt mask 157 | iBase 4 + io@ 158 | ; 159 | -------------------------------------------------------------------------------- /src/main/scala/J1Core.scala: -------------------------------------------------------------------------------- 1 | /* 2 | * Author: Steffen Reith (Steffen.Reith@hs-rm.de) 3 | * 4 | * Create Date: Tue Sep 20 15:07:10 CEST 2016 5 | * Module Name: J1Core - CPU core (ALU, Decoder, Stacks, etc) 6 | * Project Name: J1Sc - A simple J1 implementation in Scala using Spinal HDL 7 | * 8 | */ 9 | import spinal.core._ 10 | 11 | class J1Core(cfg : J1Config) extends Component { 12 | 13 | // Check the generic parameters 14 | assert(cfg.wordSize == 16, message = "ERROR: Only wordsize 16 was tested!") 15 | assert((cfg.wordSize - 3) >= cfg.adrWidth, message = "ERROR: The width of an address is too large") 16 | 17 | // Internally used signals 18 | val internal = new Bundle { 19 | 20 | // Signals for memory and io port 21 | val memWriteMode = out Bool 22 | val ioWriteMode = out Bool 23 | val ioReadMode = out Bool 24 | val extAdr = out UInt(cfg.wordSize bits) 25 | val extToWrite = out Bits(cfg.wordSize bits) 26 | val toRead = in Bits(cfg.wordSize bits) 27 | 28 | // Signal to stall the CPU 29 | val stall = in Bool 30 | 31 | // Interface for the interrupt system 32 | val irq = in Bool 33 | val intVec = in Bits (cfg.adrWidth bits) 34 | 35 | // I/O port for instructions 36 | val nextInstrAdr = out UInt(cfg.adrWidth bits) 37 | val memInstr = in Bits(cfg.wordSize bits) 38 | 39 | }.setName("") 40 | 41 | // The stall signal is allowed to be pruned (if we have no JTAG) 42 | internal.stall.allowPruning() 43 | 44 | // Used for checking whether a reset is active 45 | val clrActive = ClockDomain.current.isResetActive 46 | 47 | // Create the programm counter (the MSB is used to control the stacks, hence make it one bit larger) 48 | val pcObj = J1PC(cfg) 49 | val pcN = UInt(cfg.adrWidth + 1 bits) 50 | val pcInfo = pcObj(pcN, clrActive, internal.irq) 51 | val pc = pcInfo._1 52 | val returnPC = pcInfo._2 53 | 54 | // Check status and inject nop (stall mode) or call-instruction (interrupt mode) when needed 55 | val stateSelect = internal.stall ## internal.irq 56 | val instr = stateSelect.mux(B"b00" -> internal.memInstr, // Normal mode 57 | B"b01" -> B"b010" ## internal.intVec.resize(cfg.wordSize - 3), // Interrupt mode 58 | B"b10" -> J1Config.instrNOP(cfg.wordSize), // Stall mode 59 | B"b11" -> J1Config.instrNOP(cfg.wordSize)) // Stall overrides interrupt 60 | 61 | // Create the data stack 62 | val dStack = J1DStack(cfg) 63 | val dtosN = Bits(cfg.wordSize bits) 64 | val dStackInfo = dStack(internal.stall, dtosN) 65 | val dtos = dStackInfo._1 66 | val dnos = dStackInfo._2 67 | val dStackPtr = dStackInfo._3 68 | 69 | // Set next value for RTOS (check call / interrupt or T -> R ALU instruction) 70 | val rtosN = Mux(!instr(instr.high - 3 + 1), (returnPC ## B"b0").resized, dtos) 71 | 72 | // Create the return stack 73 | val rStack = J1RStack(cfg) 74 | val rtos = rStack(internal.stall, rtosN) 75 | 76 | // Create an ALU (the AluOp is taken out of the instruction) 77 | val alu = J1Alu(cfg) 78 | val aluResult = alu(instr, dtos, dnos, dStackPtr, rtos, internal.toRead) 79 | 80 | // Decode instruction and calculate next top of data stack 81 | dtosN := J1Decoder(cfg)(pc, instr, dtos, dnos, aluResult) 82 | 83 | // Internal control signals 84 | val funcTtoN = instr(6 downto 4) === B"001" // Copy DTOS to DNOS 85 | val funcTtoR = instr(6 downto 4) === B"010" // Copy DTOS to return stack 86 | val funcWriteMem = instr(6 downto 4) === B"011" // Write to RAM 87 | val funcWriteIO = instr(6 downto 4) === B"100" // I/O write operation 88 | val funcReadIO = instr(6 downto 4) === B"101" // I/O read operation 89 | val isALU = !pc.msb && (instr(instr.high downto (instr.high - 3) + 1) === B"b011") // ALU operation 90 | 91 | // Control signals used for external memory 92 | internal.memWriteMode := !clrActive && isALU && funcWriteMem 93 | internal.ioWriteMode := !clrActive && isALU && funcWriteIO 94 | internal.ioReadMode := !clrActive && isALU && funcReadIO 95 | internal.extAdr := dtosN.asUInt 96 | internal.extToWrite := dnos 97 | 98 | // Update the data stack 99 | dStack.updateDStack(pc.msb, instr, funcTtoN) 100 | 101 | // Handle the update of the return stack 102 | rStack.updateRStack(pc.msb, instr, funcTtoR) 103 | 104 | // Create the PC update logic 105 | pcN := pcObj.updatePC(stall = internal.stall, 106 | clrActive = clrActive, 107 | instr = instr, 108 | dtos = dtos, 109 | rtos = rtos) 110 | 111 | // Use next PC as address of instruction memory (do not use the MSB) 112 | internal.nextInstrAdr := pcN(pcN.high - 1 downto 0) 113 | 114 | } 115 | --------------------------------------------------------------------------------