├── .gitignore ├── README.md ├── magic ├── OR_Gate │ ├── CED18I051_2_INPUT_OR_GATE │ │ ├── OR_gate_simp.ext │ │ ├── OR_gate_simp.mag │ │ ├── OR_gate_simp.sim │ │ └── Submission.png │ ├── CMOS_OR.png │ ├── OR_gate.ext │ ├── OR_gate.mag │ ├── OR_gate.sim │ ├── OR_gate_simp.ext │ ├── OR_gate_simp.mag │ ├── OR_gate_simp.sim │ └── scmos100.prm └── inverter │ ├── CMOS_Inverter.png │ ├── final_output.png │ ├── inverter.ext │ ├── inverter.mag │ ├── inverter.sim │ └── scmos100.prm └── verilog ├── 32bit-Ripple-carry-adder ├── 16_bit_full_adder.v ├── 1_bit_full_adder.v ├── 32_bit_full_adder.v ├── 4_bit_full_adder.v ├── 8_bit_full_adder.v ├── a.out ├── output.png └── testbench.v ├── 32bit-recursive-doubling-CLA ├── 32rdcla.v ├── a.out ├── output.png └── tb.v ├── 32bit-wallace-multiplier ├── a.out ├── carry_save_adder.v ├── output.png ├── partial_products.v ├── testbench.v └── wallace.v └── 8bit-shift-register ├── 2bit.v ├── 4:1-MUX.v ├── 4bit.v ├── 8bit.v ├── 8bit_sr.vcd ├── a.out ├── dff.v ├── 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