├── 1_VerilogSourceCode ├── 1_CPUCore_src │ ├── ALU.v │ ├── BRAMModule │ │ ├── DataRam.v │ │ └── InstructionRam.v │ ├── BranchDecisionMaking.v │ ├── ControlUnit.v │ ├── DataExt.v │ ├── EXSegReg.v │ ├── HarzardUnit.v │ ├── IDSegReg.v │ ├── IFSegReg.v │ ├── ImmOperandUnit.v │ ├── MEMSegReg.v │ ├── NPC_Generator.v │ ├── Parameters.v │ ├── RV32Core.v │ ├── RegisterFile.v │ └── WBSegReg.v └── 2_Simulation │ ├── 1testAll.data │ ├── 1testAll.inst │ ├── 1testAll.txt │ ├── 2testAll.data │ ├── 2testAll.inst │ ├── 2testAll.txt │ ├── 3testAll.data │ ├── 3testAll.inst │ ├── 3testAll.txt │ └── testBench.v ├── 2_BRAMInputFileGenerator ├── ExampleCode │ ├── ASMCode │ │ ├── Fibonacci.S │ │ ├── Number2Ascii.S │ │ └── QuickSort.S │ └── RISCVTest_rv32ui │ │ ├── 1testAll.S │ │ ├── 2testAll.S │ │ ├── 3testAll.S │ │ ├── LICENCE │ │ ├── README.md │ │ └── SourceCode │ │ ├── 1testAll.S │ │ ├── 2testAll.S │ │ ├── 3testAll.S │ │ ├── encoding.h │ │ ├── riscv_test.h │ │ └── test_macros.h ├── Makefile ├── README.md └── Utils │ ├── Bin2Data.c │ ├── riscv32-unknown-elf-as │ ├── riscv32-unknown-elf-ld │ ├── riscv32-unknown-elf-objcopy │ └── riscv32-unknown-elf-objdump ├── 3_CacheLab ├── ASM-Benchmark │ ├── generate_data │ │ ├── generate_mem_for_matmul.py │ │ └── generate_mem_for_quicksort.py │ └── generate_inst │ │ ├── MatMul.S │ │ ├── QuickSort.S │ │ ├── asm2verilogrom.py │ │ └── riscv32-gnu-toolchain-windows │ │ ├── mips-elf-addr2line.exe │ │ ├── mips-elf-ar.exe │ │ ├── mips-elf-as.exe │ │ ├── mips-elf-c++.exe │ │ ├── mips-elf-c++filt.exe │ │ ├── mips-elf-cpp.exe │ │ ├── mips-elf-elfedit.exe │ │ ├── mips-elf-g++.exe │ │ ├── mips-elf-gcc-7.2.0.exe │ │ ├── mips-elf-gcc-ar.exe │ │ ├── mips-elf-gcc-nm.exe │ │ ├── mips-elf-gcc-ranlib.exe │ │ ├── mips-elf-gcc.exe │ │ ├── mips-elf-gcov-dump.exe │ │ ├── mips-elf-gcov-tool.exe │ │ ├── mips-elf-gcov.exe │ │ ├── mips-elf-ld.bfd.exe │ │ ├── mips-elf-ld.exe │ │ ├── mips-elf-nm.exe │ │ ├── mips-elf-objcopy.exe │ │ ├── mips-elf-objdump.exe │ │ ├── mips-elf-ranlib.exe │ │ ├── mips-elf-readelf.exe │ │ ├── mips-elf-size.exe │ │ ├── mips-elf-strings.exe │ │ ├── mips-elf-strip.exe │ │ ├── riscv32-elf-addr2line.exe │ │ ├── riscv32-elf-ar.exe │ │ ├── riscv32-elf-as.exe │ │ ├── riscv32-elf-c++.exe │ │ ├── riscv32-elf-c++filt.exe │ │ ├── riscv32-elf-cpp.exe │ │ ├── riscv32-elf-elfedit.exe │ │ ├── riscv32-elf-g++.exe │ │ ├── riscv32-elf-gcc-7.2.0.exe │ │ ├── riscv32-elf-gcc-ar.exe │ │ ├── riscv32-elf-gcc-nm.exe │ │ ├── riscv32-elf-gcc-ranlib.exe │ │ ├── riscv32-elf-gcc.exe │ │ ├── riscv32-elf-gcov-dump.exe │ │ ├── riscv32-elf-gcov-tool.exe │ │ ├── riscv32-elf-gcov.exe │ │ ├── riscv32-elf-gprof.exe │ │ ├── riscv32-elf-ld.bfd.exe │ │ ├── riscv32-elf-ld.exe │ │ ├── riscv32-elf-nm.exe │ │ ├── riscv32-elf-objcopy.exe │ │ ├── riscv32-elf-objdump.exe │ │ ├── riscv32-elf-ranlib.exe │ │ ├── riscv32-elf-readelf.exe │ │ ├── riscv32-elf-size.exe │ │ ├── riscv32-elf-strings.exe │ │ └── riscv32-elf-strip.exe ├── CPUSrcCode │ ├── Testbench │ │ └── cpu_tb.v │ └── Verilog │ │ ├── ALU.v │ │ ├── ControlUnit.v │ │ ├── DataExt.v │ │ ├── EXSegReg.v │ │ ├── HarzardUnit.v │ │ ├── IDSegReg.v │ │ ├── IFSegReg.v │ │ ├── ImmOperandUnit.v │ │ ├── InstructionRam.sv │ │ ├── InstructionRamNoCache.v │ │ ├── MEMSegReg.v │ │ ├── Parameters.v │ │ ├── RV32Core.v │ │ ├── RegisterFile.v │ │ └── WBSegReg.v ├── CacheSrcCode │ ├── README.md │ ├── cache.sv │ ├── cache_tb.sv │ ├── cache_tb.v │ ├── generate_cache_tb.py │ ├── main_mem.sv │ └── mem.sv └── README.md ├── 4_ProjectDesignFiles └── CPU设计图.pdf ├── 5_DetailDocuments ├── Lab1-CPU设计报告.docx ├── Lab1-CPU设计报告.pdf ├── Lab2-CPU代码实现验收标准和实验报告要求.docx ├── Lab2-CPU代码实现验收标准和实验报告要求.pdf ├── Lab3-Cache 实验常见疑问.docx ├── Lab3-Cache实验-实验要求.docx ├── Lab3-王轩-cache实验指导.docx ├── Lab3-王轩-cache编写指导.docx ├── Lab5-多Cache一致性与Tomasulo模拟器使用.docx ├── lab4-分支预测.pdf ├── 课堂ppt │ ├── lab4-分支预测-实验指导.pptx │ └── 夏昊珺-Lab1总结和Lab2讲解.pptx └── 资料 │ ├── RISC-V 指令集卷1-用户级指令-中文版.pdf │ ├── RISC-V 指令集卷2-特权级指令-中文版.pdf │ ├── RISCV指令集总览表格.pdf │ ├── The RISC-V Instruction Set Manual Volume I User-Level ISA-V2.2.pdf │ └── The RISC-V Instruction Set Manual Volume II Privileged Architecture V1.9.1.pdf ├── 6_branch_prediction ├── README.md ├── cpu_rtl │ ├── ALU.v │ ├── BRAMModule │ │ ├── DataRam.v │ │ └── InstructionRam.v │ ├── BranchDecisionMaking.v │ ├── ControlUnit.v │ ├── DataExt.v │ ├── EXSegReg.v │ ├── HarzardUnit.v │ ├── IDSegReg.v │ ├── IFSegReg.v │ ├── ImmOperandUnit.v │ ├── MEMSegReg.v │ ├── NPC_Generator.v │ ├── Parameters.v │ ├── RV32Core.v │ ├── RegisterFile.v │ └── WBSegReg.v └── test │ ├── bht.S │ ├── bht.data │ ├── bht.inst │ ├── btb.S │ ├── btb.data │ └── btb.inst ├── 7_VerilogSourceCode_Complete_Version ├── ALU.v ├── BRAMModule │ ├── DataRam.v │ └── InstructionRam.v ├── BranchDecisionMaking.v ├── ControlUnit.v ├── DataExt.v ├── EXSegReg.v ├── HarzardUnit.v ├── IDSegReg.v ├── IFSegReg.v ├── ImmOperandUnit.v ├── MEMSegReg.v ├── NPC_Generator.v ├── Parameters.v ├── RV32Core.v ├── RegisterFile.v └── WBSegReg.v ├── LICENSE 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