├── .UDS_S32K144_APP.g_c ├── .UDS_S32K144_APP.g_x ├── .cproject ├── .gitattributes ├── .github └── FUNDING.yml ├── .gitignore ├── .project ├── Documentation ├── UDS_S32K144_APP.txt ├── UDS_S32K144_APP_Settings.previous.xml └── UDS_S32K144_APP_Settings.xml ├── Generated_Code ├── Cpu.c ├── Cpu.h ├── canCom1.c ├── canCom1.h ├── clockMan1.c ├── clockMan1.h ├── dmaController1.c ├── dmaController1.h ├── lpTmr1.c ├── lpTmr1.h ├── lpuart1.c ├── lpuart1.h ├── pin_mux.c ├── pin_mux.h ├── pwrMan1.c ├── pwrMan1.h ├── watchdog1.c └── watchdog1.h ├── LinkSetting_ForUsageFault_00.png ├── LinkSetting_ForUsageFault_01.png ├── LinkSetting_ForUsageFault_02.png ├── Ozone_UDS_S32K144_APP.jdebug ├── Ozone_UDS_S32K144_APP.jdebug.user ├── Pic_ZCANPRO_ECU_Refresh.png ├── Pic_ZCANPRO_ECU_Refresh_Note_ProgramSession.png ├── Pic_ZCANPRO_ECU_Refresh_Note_ResetECU.png ├── ProcessorExpert.pe ├── Project_Settings ├── Linker_Files │ ├── S32K144_64_flash.ld │ └── S32K144_64_ram.ld └── Startup_Code │ └── startup_S32K144.S ├── README.md ├── SDK ├── platform │ ├── devices │ │ ├── S32K144 │ │ │ ├── include │ │ │ │ ├── S32K144.h │ │ │ │ └── S32K144_features.h │ │ │ └── startup │ │ │ │ ├── system_S32K144.c │ │ │ │ └── system_S32K144.h │ │ ├── callbacks.h │ │ ├── common │ │ │ └── s32_core_cm4.h │ │ ├── devassert.h │ │ ├── device_registers.h │ │ ├── startup.c │ │ ├── startup.h │ │ └── status.h │ └── drivers │ │ ├── inc │ │ ├── clock.h │ │ ├── clock_manager.h │ │ ├── edma_driver.h │ │ ├── flexcan_driver.h │ │ ├── interrupt_manager.h │ │ ├── lptmr_driver.h │ │ ├── lpuart_driver.h │ │ ├── pins_driver.h │ │ ├── power_manager.h │ │ └── wdog_driver.h │ │ └── src │ │ ├── clock │ │ └── S32K1xx │ │ │ ├── clock_S32K1xx.c │ │ │ ├── clock_S32K1xx.h │ │ │ ├── pcc_hw_access.h │ │ │ ├── pmc_hw_access.h │ │ │ ├── scg_hw_access.h │ │ │ ├── sim_hw_access.h │ │ │ └── smc_hw_access.h │ │ ├── edma │ │ ├── edma_driver.c │ │ ├── edma_hw_access.c │ │ ├── edma_hw_access.h │ │ ├── edma_irq.c │ │ └── edma_irq.h │ │ ├── flexcan │ │ ├── flexcan_driver.c │ │ ├── flexcan_hw_access.c │ │ ├── flexcan_hw_access.h │ │ ├── flexcan_irq.c │ │ └── flexcan_irq.h │ │ ├── interrupt │ │ └── interrupt_manager.c │ │ ├── lptmr │ │ ├── lptmr_driver.c │ │ ├── lptmr_hw_access.c │ │ └── lptmr_hw_access.h │ │ ├── lpuart │ │ ├── lpuart_driver.c │ │ ├── lpuart_hw_access.c │ │ ├── lpuart_hw_access.h │ │ ├── lpuart_irq.c │ │ └── lpuart_irq.h │ │ ├── pins │ │ ├── pins_driver.c │ │ ├── pins_gpio_hw_access.h │ │ ├── pins_port_hw_access.c │ │ └── pins_port_hw_access.h │ │ ├── power │ │ ├── S32K1xx │ │ │ ├── power_manager_S32K1xx.c │ │ │ ├── power_manager_S32K1xx.h │ │ │ ├── power_rcm_hw_access.h │ │ │ ├── power_scg_hw_access.h │ │ │ ├── power_smc_hw_access.c │ │ │ └── power_smc_hw_access.h │ │ └── power_manager.c │ │ └── wdog │ │ ├── wdog_driver.c │ │ ├── wdog_hw_access.c │ │ └── wdog_hw_access.h └── rtos │ └── osif │ ├── osif.h │ └── osif_baremetal.c ├── Sources ├── SEGGER_RTT │ ├── SEGGER_RTT.c │ ├── SEGGER_RTT.h │ ├── SEGGER_RTT_ASM_ARMv7M.S │ ├── SEGGER_RTT_Conf.h │ ├── SEGGER_RTT_Syscalls_GCC.c │ └── SEGGER_RTT_printf.c └── main.c ├── UDS_DriverConfig ├── can_cfg.c ├── can_cfg.h ├── can_driver.c ├── can_driver.h ├── flash.c ├── flash.h ├── flash_cfg.c ├── flash_cfg.h └── 一键格式化所有代码(包括子目录)_精简版.bat ├── UDS_PortingFiles ├── AES.c ├── AES.h ├── CRC_hal.c ├── CRC_hal.h ├── UDS_alg_hal.c ├── UDS_alg_hal.h ├── ZLGKey.c ├── ZLGKey.h ├── boot.c ├── boot.h ├── boot_Cfg.c ├── boot_Cfg.h ├── bootloader_debug.c ├── bootloader_debug.h ├── common_types.h ├── debug_IO.c ├── debug_IO.h ├── debug_timer.c ├── debug_timer.h ├── flash_hal.c ├── flash_hal.h ├── flash_hal_Cfg.c ├── flash_hal_Cfg.h ├── includes.h ├── timer_hal.c ├── timer_hal.h ├── toolchain.h ├── user_config.h ├── watchdog_hal.c ├── watchdog_hal.h └── 一键格式化所有代码(包括子目录)_精简版.bat ├── UDS_ProtocolStack ├── LIN_tp.c ├── LIN_tp.h ├── LIN_tp_cfg.c ├── LIN_tp_cfg.h ├── TP.c ├── TP.h ├── TP_cfg.c ├── TP_cfg.h ├── autolibc.c ├── autolibc.h ├── bootloader_main.c ├── bootloader_main.h ├── can_tp.c ├── can_tp.h ├── can_tp_cfg.c ├── can_tp_cfg.h ├── fls_app.c ├── fls_app.h ├── multi_cyc_fifo.c ├── multi_cyc_fifo.h ├── uds_app.c ├── uds_app.h ├── uds_app_cfg.c ├── uds_app_cfg.h └── 一键格式化所有代码(包括子目录)_精简版.bat ├── donate_Alipay.jpg └── donate_Wechat.png /.gitattributes: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/SummerFalls/UDS_S32K144_APP/1b2a3961f03ecf3ca39563031fc24a1d2443b8fc/.gitattributes -------------------------------------------------------------------------------- /.github/FUNDING.yml: -------------------------------------------------------------------------------- 1 | custom: paypal.me/37LINN 2 | -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | /Debug/ 2 | .settings/ 3 | 4 | # Locally stored "Eclipse launch configurations" 5 | *.launch 6 | 7 | # Prerequisites 8 | *.d 9 | 10 | # Object files 11 | *.o 12 | *.ko 13 | *.obj 14 | *.elf 15 | 16 | # Linker output 17 | *.ilk 18 | *.map 19 | *.exp 20 | *.list 21 | 22 | # Precompiled Headers 23 | *.gch 24 | *.pch 25 | 26 | # Libraries 27 | # *.lib 28 | # *.a 29 | # *.la 30 | # *.lo 31 | 32 | # Shared objects (inc. Windows DLLs) 33 | *.dll 34 | *.so 35 | *.so.* 36 | *.dylib 37 | 38 | # Executables 39 | # *.exe 40 | *.out 41 | *.app 42 | *.i*86 43 | *.x86_64 44 | # *.hex 45 | 46 | # Debug files 47 | *.dSYM/ 48 | *.su 49 | *.idb 50 | *.pdb 51 | 52 | # Kernel Module Compile Results 53 | *.mod* 54 | # *.cmd 55 | .tmp_versions/ 56 | modules.order 57 | Module.symvers 58 | Mkfile.old 59 | dkms.conf 60 | /Debug_FLASH/ 61 | -------------------------------------------------------------------------------- /.project: -------------------------------------------------------------------------------- 1 | 2 | 3 | UDS_S32K144_APP 4 | 5 | 6 | 7 | 8 | 9 | com.freescale.processorexpert.core.expertprojectbuilder 10 | 11 | 12 | 13 | 14 | org.eclipse.cdt.managedbuilder.core.genmakebuilder 15 | clean,full,incremental, 16 | 17 | 18 | 19 | 20 | org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder 21 | full,incremental, 22 | 23 | 24 | 25 | 26 | 27 | com.freescale.processorexpert.core.expertprojectnature 28 | org.eclipse.cdt.core.cnature 29 | org.eclipse.cdt.managedbuilder.core.managedBuildNature 30 | org.eclipse.cdt.managedbuilder.core.ScannerConfigNature 31 | 32 | 33 | -------------------------------------------------------------------------------- /Documentation/UDS_S32K144_APP_Settings.previous.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | 45 | 46 | 47 | 48 | 49 | 50 | 51 | 52 | 53 | 54 | 55 | 56 | 57 | 58 | 59 | 60 | 61 | 62 | 63 | 64 | 65 | 66 | 67 | 68 | 69 | 70 | 71 | 72 | 73 | 74 | 75 | 76 | 77 | 78 | 79 | 80 | 81 | 82 | 83 | 84 | 85 | 86 | 87 | 88 | 89 | 90 | 91 | 92 | 93 | 94 | 95 | 96 | 97 | 98 | 99 | 100 | 101 | 102 | 103 | 104 | 105 | 106 | 107 | 108 | 109 | 110 | 111 | 112 | 113 | 114 | 115 | 116 | 117 | 118 | 119 | 120 | 121 | 122 | 123 | 124 | 125 | 126 | 127 | 128 | 129 | 130 | 131 | 132 | 133 | 134 | 135 | 136 | 137 | 138 | 139 | 140 | 141 | 142 | 143 | 144 | 145 | 146 | 147 | 148 | 149 | 150 | 151 | 152 | 153 | 154 | 155 | 156 | 157 | 158 | 159 | -------------------------------------------------------------------------------- /Documentation/UDS_S32K144_APP_Settings.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | 45 | 46 | 47 | 48 | 49 | 50 | 51 | 52 | 53 | 54 | 55 | 56 | 57 | 58 | 59 | 60 | 61 | 62 | 63 | 64 | 65 | 66 | 67 | 68 | 69 | 70 | 71 | 72 | 73 | 74 | 75 | 76 | 77 | 78 | 79 | 80 | 81 | 82 | 83 | 84 | 85 | 86 | 87 | 88 | 89 | 90 | 91 | 92 | 93 | 94 | 95 | 96 | 97 | 98 | 99 | 100 | 101 | 102 | 103 | 104 | 105 | 106 | 107 | 108 | 109 | 110 | 111 | 112 | 113 | 114 | 115 | 116 | 117 | 118 | 119 | 120 | 121 | 122 | 123 | 124 | 125 | 126 | 127 | 128 | 129 | 130 | 131 | 132 | 133 | 134 | 135 | 136 | 137 | 138 | 139 | 140 | 141 | 142 | 143 | 144 | 145 | 146 | 147 | 148 | 149 | 150 | 151 | 152 | 153 | 154 | 155 | 156 | 157 | 158 | 159 | 160 | 161 | 162 | 163 | 164 | 165 | 166 | 167 | 168 | 169 | 170 | 171 | 172 | -------------------------------------------------------------------------------- /Generated_Code/Cpu.c: -------------------------------------------------------------------------------- 1 | /** ################################################################### 2 | ** This component module is generated by Processor Expert. Do not modify it. 3 | ** Filename : Cpu.c 4 | ** Project : UDS_S32K144_APP 5 | ** Processor : S32K144_100 6 | ** Component : S32K144_100 7 | ** Version : Component 01.197, Driver 01.00, CPU db: 3.00.000 8 | ** Datasheet : S32K14XRM Rev. 2, 02/2017 9 | ** Compiler : GNU C Compiler 10 | ** Date/Time : 2021-05-21, 21:54, # CodeGen: 5 11 | ** Abstract : 12 | ** 13 | ** Settings : 14 | ** 15 | ** Contents : 16 | ** SystemInit - void SystemInit(void); 17 | ** SystemCoreClockUpdate - void SystemCoreClockUpdate(void); 18 | ** SystemSoftwareReset - void SystemSoftwareReset(void); 19 | ** 20 | ** (c) Freescale Semiconductor, Inc. 21 | ** 2004 All Rights Reserved 22 | ** 23 | ** Copyright 1997 - 2015 Freescale Semiconductor, Inc. 24 | ** Copyright 2016-2017 NXP 25 | ** All Rights Reserved. 26 | ** 27 | ** THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR 28 | ** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 29 | ** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 30 | ** IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 31 | ** INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 32 | ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 33 | ** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 34 | ** HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 35 | ** STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 36 | ** IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 37 | ** THE POSSIBILITY OF SUCH DAMAGE. 38 | ** ###################################################################*/ 39 | /*! 40 | ** @file Cpu.c 41 | ** @version 01.00 42 | ** @brief 43 | ** 44 | */ 45 | /*! 46 | ** @addtogroup Cpu_module Cpu module documentation 47 | ** @{ 48 | */ 49 | 50 | /* MODULE Cpu. */ 51 | 52 | /* {Default RTOS Adapter} No RTOS includes */ 53 | #include "Cpu.h" 54 | 55 | #ifdef __cplusplus 56 | extern "C" { 57 | #endif 58 | 59 | /* TBD Cpu configuration will be generated here. */ 60 | 61 | #ifdef __cplusplus 62 | } 63 | #endif 64 | 65 | /* END Cpu. */ 66 | 67 | /*! 68 | ** @} 69 | */ 70 | /* 71 | ** ################################################################### 72 | ** 73 | ** This file was created by Processor Expert 10.1 [05.21] 74 | ** for the Freescale S32K series of microcontrollers. 75 | ** 76 | ** ################################################################### 77 | */ 78 | -------------------------------------------------------------------------------- /Generated_Code/Cpu.h: -------------------------------------------------------------------------------- 1 | /* ################################################################### 2 | ** This component module is generated by Processor Expert. Do not modify it. 3 | ** Filename : Cpu.h 4 | ** Project : UDS_S32K144_APP 5 | ** Processor : S32K144_100 6 | ** Component : S32K144_100 7 | ** Version : Component 01.197, Driver 01.00, CPU db: 3.00.000 8 | ** Datasheet : S32K14XRM Rev. 2, 02/2017 9 | ** Compiler : GNU C Compiler 10 | ** Date/Time : 2021-05-22, 21:59, # CodeGen: 12 11 | ** Abstract : 12 | ** 13 | ** Settings : 14 | ** 15 | ** Contents : 16 | ** SystemInit - void SystemInit(void); 17 | ** SystemCoreClockUpdate - void SystemCoreClockUpdate(void); 18 | ** SystemSoftwareReset - void SystemSoftwareReset(void); 19 | ** 20 | ** (c) Freescale Semiconductor, Inc. 21 | ** 2004 All Rights Reserved 22 | ** 23 | ** Copyright 1997 - 2015 Freescale Semiconductor, Inc. 24 | ** Copyright 2016-2017 NXP 25 | ** All Rights Reserved. 26 | ** 27 | ** THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR 28 | ** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 29 | ** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 30 | ** IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 31 | ** INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 32 | ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 33 | ** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 34 | ** HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 35 | ** STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 36 | ** IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 37 | ** THE POSSIBILITY OF SUCH DAMAGE. 38 | ** ###################################################################*/ 39 | /*! 40 | ** @file Cpu.h 41 | ** @version 01.00 42 | ** @brief 43 | ** 44 | */ 45 | /*! 46 | ** @addtogroup Cpu_module Cpu module documentation 47 | ** @{ 48 | */ 49 | 50 | #ifndef Cpu_H 51 | #define Cpu_H 52 | 53 | 54 | /* MODULE Cpu. */ 55 | 56 | 57 | /*Include shared modules, which are used for whole project*/ 58 | #include "device_registers.h" 59 | 60 | #include "interrupt_manager.h" 61 | #include "clock.h" 62 | #include "edma_driver.h" 63 | #include "osif.h" 64 | #include "lpuart_driver.h" 65 | #include "lptmr_driver.h" 66 | #include "wdog_driver.h" 67 | #include "flexcan_driver.h" 68 | #include "power_manager.h" 69 | #include "system_S32K144.h" 70 | 71 | /* Including needed modules to compile this module/procedure */ 72 | #include "pin_mux.h" 73 | #include "clockMan1.h" 74 | #include "lpuart1.h" 75 | #include "dmaController1.h" 76 | #include "lpTmr1.h" 77 | #include "watchdog1.h" 78 | #include "canCom1.h" 79 | #include "pwrMan1.h" 80 | 81 | #ifdef __cplusplus 82 | extern "C" { 83 | #endif 84 | 85 | /* TBD Cpu configuration will be declared here. */ 86 | 87 | 88 | 89 | 90 | #ifdef __cplusplus 91 | } 92 | #endif 93 | 94 | /* END Cpu. */ 95 | 96 | #endif 97 | /* Cpu_H */ 98 | 99 | /*! 100 | ** @} 101 | */ 102 | /* 103 | ** ################################################################### 104 | ** 105 | ** This file was created by Processor Expert 10.1 [05.21] 106 | ** for the Freescale S32K series of microcontrollers. 107 | ** 108 | ** ################################################################### 109 | */ 110 | -------------------------------------------------------------------------------- /Generated_Code/canCom1.c: -------------------------------------------------------------------------------- 1 | /* ################################################################### 2 | ** This component module is generated by Processor Expert. Do not modify it. 3 | ** Filename : canCom1.c 4 | ** Project : UDS_S32K144_APP 5 | ** Processor : S32K144_100 6 | ** Component : flexcan 7 | ** Version : Component SDK_S32K1xx_15, Driver 01.00, CPU db: 3.00.000 8 | ** Repository : SDK_S32K1xx_15 9 | ** Compiler : GNU C Compiler 10 | ** Date/Time : 2021-02-20, 11:57, # CodeGen: 2 11 | ** 12 | ** Copyright 1997 - 2015 Freescale Semiconductor, Inc. 13 | ** Copyright 2016-2017 NXP 14 | ** All Rights Reserved. 15 | ** 16 | ** THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR 17 | ** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 | ** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 | ** IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 20 | ** INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 21 | ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 22 | ** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 | ** HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 24 | ** STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 25 | ** IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 26 | ** THE POSSIBILITY OF SUCH DAMAGE. 27 | ** ###################################################################*/ 28 | /*! 29 | ** @file canCom1.c 30 | ** @version 01.00 31 | */ 32 | /*! 33 | ** @addtogroup canCom1_module canCom1 module documentation 34 | ** @{ 35 | */ 36 | 37 | /* MODULE canCom1. 38 | * 39 | * @page misra_violations MISRA-C:2012 violations 40 | * 41 | * @section [global] 42 | * Violates MISRA 2012 Advisory Rule 8.7, External variable could be made static. 43 | * The external variables will be used in other source files that user initialize 44 | * to use this module. 45 | * 46 | * @section [global] 47 | * Violates MISRA 2012 Advisory Rule 2.5, Global macro not referenced. 48 | * This is required to enable the use of a macro needed by the application (even 49 | * if the macro is not used inside the driver code). 50 | */ 51 | 52 | #include "canCom1.h" 53 | 54 | flexcan_state_t canCom1_State; 55 | 56 | const flexcan_user_config_t canCom1_InitConfig0 = { 57 | .fd_enable = false, 58 | .pe_clock = FLEXCAN_CLK_SOURCE_PERIPH, 59 | .max_num_mb = 32, 60 | .num_id_filters = FLEXCAN_RX_FIFO_ID_FILTERS_8, 61 | .is_rx_fifo_needed = false, 62 | .flexcanMode = FLEXCAN_NORMAL_MODE, 63 | .payload = FLEXCAN_PAYLOAD_SIZE_8, 64 | .bitrate = { 65 | .propSeg = 7, 66 | .phaseSeg1 = 4, 67 | .phaseSeg2 = 1, 68 | .preDivider = 5, 69 | .rJumpwidth = 1 70 | }, 71 | .bitrate_cbt = { 72 | .propSeg = 7, 73 | .phaseSeg1 = 4, 74 | .phaseSeg2 = 1, 75 | .preDivider = 5, 76 | .rJumpwidth = 1 77 | }, 78 | .transfer_type = FLEXCAN_RXFIFO_USING_INTERRUPTS, 79 | .rxFifoDMAChannel = 0U 80 | }; 81 | 82 | 83 | /* END canCom1. */ 84 | 85 | /*! 86 | ** @} 87 | */ 88 | /* 89 | ** ################################################################### 90 | ** 91 | ** This file was created by Processor Expert 10.1 [05.21] 92 | ** for the Freescale S32K series of microcontrollers. 93 | ** 94 | ** ################################################################### 95 | */ 96 | 97 | 98 | -------------------------------------------------------------------------------- /Generated_Code/canCom1.h: -------------------------------------------------------------------------------- 1 | /* ################################################################### 2 | ** This component module is generated by Processor Expert. Do not modify it. 3 | ** Filename : canCom1.h 4 | ** Project : UDS_S32K144_APP 5 | ** Processor : S32K144_100 6 | ** Component : flexcan 7 | ** Version : Component SDK_S32K1xx_15, Driver 01.00, CPU db: 3.00.000 8 | ** Repository : SDK_S32K1xx_15 9 | ** Compiler : GNU C Compiler 10 | ** Date/Time : 2021-02-20, 11:57, # CodeGen: 2 11 | ** Contents : 12 | ** FLEXCAN_DRV_SetBitrate - void FLEXCAN_DRV_SetBitrate(uint8_t instance,const flexcan_time_segment_t *... 13 | ** FLEXCAN_DRV_GetBitrate - void FLEXCAN_DRV_GetBitrate(uint8_t instance,flexcan_time_segment_t * bitrate); 14 | ** FLEXCAN_DRV_SetRxMaskType - void FLEXCAN_DRV_SetRxMaskType(uint8_t instance,flexcan_rx_mask_type_t type); 15 | ** FLEXCAN_DRV_SetRxFifoGlobalMask - void FLEXCAN_DRV_SetRxFifoGlobalMask(uint8_t... 16 | ** FLEXCAN_DRV_SetRxMbGlobalMask - void FLEXCAN_DRV_SetRxMbGlobalMask(uint8_t instance,flexcan_msgbuff_id_type_t... 17 | ** FLEXCAN_DRV_SetRxIndividualMask - status_t FLEXCAN_DRV_SetRxIndividualMask(uint8_t... 18 | ** FLEXCAN_DRV_Init - status_t FLEXCAN_DRV_Init(uint8_t instance,flexcan_state_t * state,const... 19 | ** FLEXCAN_DRV_Deinit - status_t FLEXCAN_DRV_Deinit(uint8_t instance); 20 | ** FLEXCAN_DRV_ConfigTxMb - status_t FLEXCAN_DRV_ConfigTxMb(uint8_t instance,uint8_t mb_idx,const... 21 | ** FLEXCAN_DRV_ConfigRemoteResponseMb - status_t FLEXCAN_DRV_ConfigRemoteResponseMb(uint8_t instance,uint8_t... 22 | ** FLEXCAN_DRV_SendBlocking - status_t FLEXCAN_DRV_SendBlocking(uint8_t instance,uint8_t mb_idx,const... 23 | ** FLEXCAN_DRV_Send - status_t FLEXCAN_DRV_Send(uint8_t instance,uint8_t mb_idx,const... 24 | ** FLEXCAN_DRV_AbortTransfer - status_t FLEXCAN_DRV_AbortTransfer(uint8_t instance,uint8_t mb_idx); 25 | ** FLEXCAN_DRV_ConfigRxMb - status_t FLEXCAN_DRV_ConfigRxMb(uint8_t instance,uint8_t mb_idx,const... 26 | ** FLEXCAN_DRV_ConfigRxFifo - void FLEXCAN_DRV_ConfigRxFifo(uint8_t i... 27 | ** FLEXCAN_DRV_ReceiveBlocking - status_t FLEXCAN_DRV_ReceiveBlocking(uint8_t instance,uint8_t... 28 | ** FLEXCAN_DRV_Receive - status_t FLEXCAN_DRV_Receive(uint8_t instance,uint8_t... 29 | ** FLEXCAN_DRV_RxFifoBlocking - status_t FLEXCAN_DRV_RxFifoBlocking(uint8_t instance,flexcan_msgbuff_t *... 30 | ** FLEXCAN_DRV_RxFifo - status_t FLEXCAN_DRV_RxFifo(uint8_t instance,flexcan_msgbuff_t * data); 31 | ** FLEXCAN_DRV_GetTransferStatus - status_t FLEXCAN_DRV_GetTransferStatus(uint8_t instance,uint8_t mb_idx); 32 | ** FLEXCAN_DRV_InstallErrorCallback - void FLEXCAN_DRV_InstallErrorCallback(uint8_t... 33 | ** FLEXCAN_DRV_InstallEventCallback - void FLEXCAN_DRV_InstallEventCallback(uint8_t instance,flexcan_callback_t... 34 | ** FLEXCAN_DRV_GetDefaultConfig - void FLEXCAN_DRV_GetDefaultConfig(flexcan_user_config_t * config); 35 | ** FLEXCAN_DRV_SetRxMb14Mask - void FLEXCAN_DRV_SetRxMb14Mask(uint8_t instance, flexcan_msgbuff_id_type_t... 36 | ** FLEXCAN_DRV_SetRxMb15Mask - void FLEXCAN_DRV_SetRxMb15Mask(uint8_t instance, flexcan_msgbuff_id_type_t... 37 | ** FLEXCAN_DRV_GetErrorStatus - uint32_t FLEXCAN_DRV_GetErrorStatus(uint8_t instance); 38 | ** FLEXCAN_DRV_ConfigPN - void FLEXCAN_DRV_ConfigPN(uint8_t instance,bool enable,const... 39 | ** FLEXCAN_DRV_GetWMB - void FLEXCAN_DRV_GetWMB(uint8_t instance, uint8_t wmbIndex, flexcan_msgbuff_t... 40 | ** FLEXCAN_DRV_SetBitrateCbt - void FLEXCAN_DRV_SetBitrateCbt(uint8_t instance,const flexcan_time_segment_t... 41 | ** FLEXCAN_DRV_GetBitrateFD - void FLEXCAN_DRV_GetBitrateFD(uint8_t instance,flexcan_time_segment_t *... 42 | ** FLEXCAN_DRV_SetTDCOffset - void FLEXCAN_DRV_SetTDCOffset(uint8_t instance, bool enable, uint8_t offset); 43 | ** FLEXCAN_DRV_GetTDCValue - uint8_t FLEXCAN_DRV_GetTDCValue(uint8_t instance); 44 | ** FLEXCAN_DRV_GetTDCFail - bool FLEXCAN_DRV_GetTDCFail(uint8_t instance); 45 | ** FLEXCAN_DRV_ClearTDCFail - void FLEXCAN_DRV_ClearTDCFail(uint8_t instance); 46 | ** 47 | ** Copyright 1997 - 2015 Freescale Semiconductor, Inc. 48 | ** Copyright 2016-2017 NXP 49 | ** All Rights Reserved. 50 | ** 51 | ** THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR 52 | ** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 53 | ** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 54 | ** IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 55 | ** INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 56 | ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 57 | ** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 58 | ** HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 59 | ** STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 60 | ** IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 61 | ** THE POSSIBILITY OF SUCH DAMAGE. 62 | ** ###################################################################*/ 63 | /*! 64 | ** @file canCom1.h 65 | ** @version 01.00 66 | */ 67 | /*! 68 | ** @addtogroup canCom1_module canCom1 module documentation 69 | ** @{ 70 | */ 71 | #ifndef canCom1_H 72 | #define canCom1_H 73 | /* MODULE canCom1. */ 74 | 75 | /* Include inherited beans */ 76 | #include "clockMan1.h" 77 | #include "dmaController1.h" 78 | #include "Cpu.h" 79 | 80 | /** 81 | * @page misra_violations MISRA-C:2012 violations 82 | * 83 | * @section [global] 84 | * Violates MISRA 2012 Advisory Rule 2.5, global macro not referenced 85 | * There are global macros defined to be used by the integrator and another one used as include guard. 86 | */ 87 | 88 | /*! @brief Device instance number */ 89 | #define INST_CANCOM1 (0U) 90 | /*! @brief Driver state structure which holds driver runtime data */ 91 | extern flexcan_state_t canCom1_State; 92 | extern const flexcan_user_config_t canCom1_InitConfig0; 93 | 94 | 95 | #endif 96 | /* ifndef canCom1_H */ 97 | /*! 98 | ** @} 99 | */ 100 | /* 101 | ** ################################################################### 102 | ** 103 | ** This file was created by Processor Expert 10.1 [05.21] 104 | ** for the Freescale S32K series of microcontrollers. 105 | ** 106 | ** ################################################################### 107 | */ 108 | 109 | -------------------------------------------------------------------------------- /Generated_Code/clockMan1.h: -------------------------------------------------------------------------------- 1 | /* ################################################################### 2 | ** This component module is generated by Processor Expert. Do not modify it. 3 | ** Filename : clockMan1.h 4 | ** Project : UDS_S32K144_APP 5 | ** Processor : S32K144_100 6 | ** Component : clock_manager 7 | ** Version : Component SDK_S32K1xx_15, Driver 01.00, CPU db: 3.00.000 8 | ** Repository : SDK_S32K1xx_15 9 | ** Compiler : GNU C Compiler 10 | ** Date/Time : 2021-02-20, 11:57, # CodeGen: 2 11 | ** Contents : 12 | ** CLOCK_DRV_Init - status_t CLOCK_DRV_Init(clock_manager_user_config_t const * config); 13 | ** CLOCK_DRV_GetFreq - status_t CLOCK_DRV_GetFreq(clock_names_t clockName, uint32_t * frequency); 14 | ** CLOCK_DRV_SetModuleClock - void CLOCK_DRV_SetModuleClock(clock_names_t peripheralClock, const... 15 | ** CLOCK_DRV_SetSystemClock - status_t CLOCK_DRV_SetSystemClock(const pwr_modes_t * mode, const... 16 | ** CLOCK_DRV_GetSystemClockSource - void CLOCK_DRV_GetSystemClockSource(sys_clk_config_t *sysClkConfig); 17 | ** CLOCK_DRV_SetClockSource - status_t CLOCK_DRV_SetClockSource(clock_names_t clockSource, const... 18 | ** 19 | ** Copyright 1997 - 2015 Freescale Semiconductor, Inc. 20 | ** Copyright 2016-2017 NXP 21 | ** All Rights Reserved. 22 | ** 23 | ** THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR 24 | ** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 | ** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 | ** IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 27 | ** INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28 | ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 29 | ** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 | ** HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 31 | ** STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 32 | ** IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 | ** THE POSSIBILITY OF SUCH DAMAGE. 34 | ** ###################################################################*/ 35 | /*! 36 | ** @file clockMan1.h 37 | ** @version 01.00 38 | */ 39 | /*! 40 | ** @addtogroup clockMan1_module clockMan1 module documentation 41 | ** @{ 42 | */ 43 | #ifndef clockMan1_H 44 | #define clockMan1_H 45 | /* MODULE clockMan1. */ 46 | 47 | #include 48 | #include 49 | 50 | /* Include inherited beans */ 51 | #include "Cpu.h" 52 | 53 | /** 54 | * @page misra_violations MISRA-C:2012 violations 55 | * 56 | * @section [global] 57 | * Violates MISRA 2012 Advisory Rule 2.5, Global macro not referenced. 58 | * Application or driver example may not use all symbols that are 59 | * generated by configurations generator. 60 | * 61 | * @section [global] 62 | * Violates MISRA 2012 Advisory Rule 8.11, When an array with external linkage 63 | * is declared, its size should be explicitly specified. 64 | * The number of configurations/callbacks can be zero. 65 | * On the other side C language forbids declaring array of size zero. 66 | * 67 | * @section [global] 68 | * Violates MISRA 2012 Advisory Rule 8.7, External variable could be made static. 69 | * The external variables will be used in other source files in application code. 70 | * 71 | */ 72 | 73 | /*! @brief User configuration structure 0 */ 74 | extern clock_manager_user_config_t clockMan1_InitConfig0; 75 | 76 | /*! @brief Count of user configuration structures */ 77 | #define CLOCK_MANAGER_CONFIG_CNT 1U 78 | 79 | /*! @brief Array of pointers to User configuration structures */ 80 | extern clock_manager_user_config_t const *g_clockManConfigsArr[]; 81 | 82 | /*! @brief User peripheral configuration structure 0 */ 83 | extern peripheral_clock_config_t peripheralClockConfig0[]; 84 | 85 | /*! @brief Count of peripheral clock user configurations */ 86 | #define NUM_OF_PERIPHERAL_CLOCKS_0 15U 87 | 88 | 89 | /*! @brief Count of user Callbacks */ 90 | #define CLOCK_MANAGER_CALLBACK_CNT 0U 91 | 92 | /*! @brief Array of User callbacks */ 93 | extern clock_manager_callback_user_config_t *g_clockManCallbacksArr[]; 94 | #endif 95 | /* ifndef clockMan1_H */ 96 | /*! 97 | ** @} 98 | */ 99 | /* 100 | ** ################################################################### 101 | ** 102 | ** This file was created by Processor Expert 10.1 [05.21] 103 | ** for the Freescale S32K series of microcontrollers. 104 | ** 105 | ** ################################################################### 106 | */ 107 | 108 | -------------------------------------------------------------------------------- /Generated_Code/dmaController1.c: -------------------------------------------------------------------------------- 1 | /* ################################################################### 2 | ** This component module is generated by Processor Expert. Do not modify it. 3 | ** Filename : dmaController1.c 4 | ** Project : UDS_S32K144_APP 5 | ** Processor : S32K144_100 6 | ** Component : edma 7 | ** Version : Component SDK_S32K1xx_15, Driver 01.00, CPU db: 3.00.000 8 | ** Repository : SDK_S32K1xx_15 9 | ** Compiler : GNU C Compiler 10 | ** Date/Time : 2021-02-20, 11:57, # CodeGen: 2 11 | ** 12 | ** Copyright 1997 - 2015 Freescale Semiconductor, Inc. 13 | ** Copyright 2016-2017 NXP 14 | ** All Rights Reserved. 15 | ** 16 | ** THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR 17 | ** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 | ** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 | ** IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 20 | ** INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 21 | ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 22 | ** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 | ** HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 24 | ** STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 25 | ** IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 26 | ** THE POSSIBILITY OF SUCH DAMAGE. 27 | ** ###################################################################*/ 28 | /*! 29 | ** @file dmaController1.c 30 | ** @version 01.00 31 | */ 32 | /*! 33 | ** @addtogroup dmaController1_module dmaController1 module documentation 34 | ** @{ 35 | */ 36 | 37 | /* dmaController1. */ 38 | 39 | /* MODULE dmaController1. 40 | * 41 | * @page misra_violations MISRA-C:2012 violations 42 | * 43 | * @section [global] 44 | * Violates MISRA 2012 Advisory Rule 8.7, External variable could be made static. 45 | * The external variables will be used in other source files that user initialize 46 | * to use this module. 47 | */ 48 | 49 | #include "dmaController1.h" 50 | 51 | edma_state_t dmaController1_State; 52 | 53 | edma_chn_state_t dmaController1Chn0_State; 54 | 55 | edma_chn_state_t * const edmaChnStateArray[] = { 56 | &dmaController1Chn0_State 57 | }; 58 | 59 | edma_channel_config_t dmaController1Chn0_Config = { 60 | .channelPriority = EDMA_CHN_DEFAULT_PRIORITY, 61 | .virtChnConfig = EDMA_CHN0_NUMBER, 62 | .source = EDMA_REQ_FLEXCAN0, 63 | .callback = NULL, 64 | .callbackParam = NULL, 65 | .enableTrigger = false 66 | }; 67 | const edma_channel_config_t * const edmaChnConfigArray[] = { 68 | &dmaController1Chn0_Config 69 | }; 70 | 71 | const edma_user_config_t dmaController1_InitConfig0 = { 72 | .chnArbitration = EDMA_ARBITRATION_FIXED_PRIORITY, 73 | .haltOnError = false 74 | }; 75 | 76 | /* END dmaController1. */ 77 | 78 | /*! 79 | ** @} 80 | */ 81 | /* 82 | ** ################################################################### 83 | ** 84 | ** This file was created by Processor Expert 10.1 [05.21] 85 | ** for the Freescale S32K series of microcontrollers. 86 | ** 87 | ** ################################################################### 88 | */ 89 | -------------------------------------------------------------------------------- /Generated_Code/dmaController1.h: -------------------------------------------------------------------------------- 1 | /* ################################################################### 2 | ** This component module is generated by Processor Expert. Do not modify it. 3 | ** Filename : dmaController1.h 4 | ** Project : UDS_S32K144_APP 5 | ** Processor : S32K144_100 6 | ** Component : edma 7 | ** Version : Component SDK_S32K1xx_15, Driver 01.00, CPU db: 3.00.000 8 | ** Repository : SDK_S32K1xx_15 9 | ** Compiler : GNU C Compiler 10 | ** Date/Time : 2021-02-20, 11:57, # CodeGen: 2 11 | ** Contents : 12 | ** EDMA_DRV_Init - status_t EDMA_DRV_Init(edma_state_t *edmaState, const edma_user_config_t... 13 | ** EDMA_DRV_Deinit - status_t EDMA_DRV_Deinit(void); 14 | ** EDMA_DRV_ChannelInit - status_t EDMA_DRV_ChannelInit(edma_chn_state_t * edmaChannelState,const... 15 | ** EDMA_DRV_ReleaseChannel - status_t EDMA_DRV_ReleaseChannel(uint8_t channel); 16 | ** EDMA_DRV_StartChannel - status_t EDMA_DRV_StartChannel(uint8_t channel); 17 | ** EDMA_DRV_StopChannel - status_t EDMA_DRV_StopChannel(uint8_t channel); 18 | ** EDMA_DRV_InstallCallback - status_t EDMA_DRV_InstallCallback(uint8_t channel,edma_callback_t... 19 | ** EDMA_DRV_GetChannelStatus - edma_chn_status_t EDMA_DRV_GetChannelStatus(uint8_t channel); 20 | ** EDMA_DRV_PushConfigToReg - void EDMA_DRV_PushConfigToReg(uint8_t channel,edma_transfer_config_t * config); 21 | ** EDMA_DRV_PushConfigToSTCD - void EDMA_DRV_PushConfigToSTCD(uint8_t channel,edma_transfer_config_t *... 22 | ** EDMA_DRV_ConfigSingleBlockTransfer - status_t EDMA_DRV_ConfigSingleBlockTransfer(uint8_t... 23 | ** EDMA_DRV_ConfigLoopTransfer - status_t EDMA_DRV_ConfigLoopTransfer(uint8_t channel,edma_transfer_config_t *... 24 | ** EDMA_DRV_ConfigScatterGatherTransfer - status_t EDMA_DRV_ConfigScatterGatherTransfer(uint8_t... 25 | ** EDMA_DRV_ConfigMultiBlockTransfer - status_t EDMA_DRV_ConfigMultiBlockTransfer(uint8_t... 26 | ** EDMA_DRV_CancelTransfer - void EDMA_DRV_CancelTransfer(bool error); 27 | ** EDMA_DRV_SetChannelRequestAndTrigger - status_t EDMA_DRV_SetChannelRequestAndTrigger(uint8_t virtualChannel, uint8_t... 28 | ** EDMA_DRV_ClearTCD - void EDMA_DRV_ClearTCD(uint8_t channel); 29 | ** EDMA_DRV_SetSrcAddr - void EDMA_DRV_SetSrcAddr(uint8_t channel, uint32_t address); 30 | ** EDMA_DRV_SetSrcOffset - void EDMA_DRV_SetSrcOffset(uint8_t channel, int16_t offset); 31 | ** EDMA_DRV_SetSrcReadChunkSize - void EDMA_DRV_SetSrcReadChunkSize(uint8_t channel, edma_transfer_size_t size); 32 | ** EDMA_DRV_SetDestAddr - void EDMA_DRV_SetDestAddr(uint8_t channel, uint32_t address); 33 | ** EDMA_DRV_SetDestOffset - void EDMA_DRV_SetDestOffset(uint8_t channel, int16_t offset); 34 | ** EDMA_DRV_SetDestWriteChunkSize - void EDMA_DRV_SetDestWriteChunkSize(uint8_t channel, edma_transfer_size_t size); 35 | ** EDMA_DRV_SetMinorLoopBlockSize - void EDMA_DRV_SetMinorLoopBlockSize(uint8_t channel, uint32_t nbytes); 36 | ** EDMA_DRV_SetMajorLoopIterationCount - void EDMA_DRV_SetMajorLoopIterationCount(uint8_t channel, uint32_t... 37 | ** EDMA_DRV_GetRemainingMajorIterationsCount - uint32_t EDMA_DRV_GetRemainingMajorIterationsCount(uint8_t channel); 38 | ** EDMA_DRV_SetScatterGatherLink - void EDMA_DRV_SetScatterGatherLink(uint8_t channel, uint32_t nextTCDAddr); 39 | ** EDMA_DRV_DisableRequestsOnTransferComplete - void EDMA_DRV_DisableRequestsOnTransferComplete(uint8_t channel, bool disable); 40 | ** EDMA_DRV_SetSrcLastAddrAdjustment - void EDMA_DRV_SetSrcLastAddrAdjustment(uint8_t channel, int32_t adjust); 41 | ** EDMA_DRV_SetDestLastAddrAdjustment - void EDMA_DRV_SetDestLastAddrAdjustment(uint8_t channel, int32_t adjust); 42 | ** EDMA_DRV_ConfigureInterrupt - void EDMA_DRV_ConfigureInterrupt(uint8_t channel, edma_channel_interrupt_t... 43 | ** EDMA_DRV_TriggerSwRequest - void EDMA_DRV_TriggerSwRequest(uint8_t channel); 44 | ** 45 | ** Copyright 1997 - 2015 Freescale Semiconductor, Inc. 46 | ** Copyright 2016-2017 NXP 47 | ** All Rights Reserved. 48 | ** 49 | ** THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR 50 | ** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 51 | ** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 52 | ** IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 53 | ** INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 54 | ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 55 | ** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 56 | ** HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 57 | ** STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 58 | ** IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 59 | ** THE POSSIBILITY OF SUCH DAMAGE. 60 | ** ###################################################################*/ 61 | /*! 62 | ** @file dmaController1.h 63 | ** @version 01.00 64 | */ 65 | /*! 66 | ** @addtogroup dmaController1_module dmaController1 module documentation 67 | ** @{ 68 | */ 69 | 70 | /* MODULE dmaController1 71 | * 72 | * @page misra_violations MISRA-C:2012 violations 73 | * 74 | * @section [global] 75 | * Violates MISRA 2012 Advisory Rule 2.5, Global macro not referenced. 76 | * The macros are defined to be used by application code. 77 | */ 78 | 79 | #ifndef dmaController1_H 80 | #define dmaController1_H 81 | 82 | /* Include inherited beans */ 83 | #include "clockMan1.h" 84 | #include "Cpu.h" 85 | 86 | /*! @brief Physical channel number for channel configuration #0 */ 87 | #define EDMA_CHN0_NUMBER 0U 88 | 89 | /*! @brief The total number of configured channels */ 90 | #define EDMA_CONFIGURED_CHANNELS_COUNT 1U 91 | 92 | /*! @brief Driver state structure which holds driver runtime data */ 93 | extern edma_state_t dmaController1_State; 94 | 95 | /*! @brief eDma channel state structure 0. Holds channel runtime data */ 96 | extern edma_chn_state_t dmaController1Chn0_State; 97 | 98 | /*! @brief Array of channel state structures */ 99 | extern edma_chn_state_t * const edmaChnStateArray[EDMA_CONFIGURED_CHANNELS_COUNT]; 100 | 101 | /*! @brief eDma channel configuration 0 */ 102 | extern edma_channel_config_t dmaController1Chn0_Config; 103 | 104 | /*! @brief Array of channel configuration structures */ 105 | extern const edma_channel_config_t * const edmaChnConfigArray[EDMA_CONFIGURED_CHANNELS_COUNT]; 106 | 107 | /*! @brief Configuration declaration */ 108 | extern const edma_user_config_t dmaController1_InitConfig0; 109 | 110 | 111 | #endif /* ifndef dmaController1_H */ 112 | /*! 113 | ** @} 114 | */ 115 | /* 116 | ** ################################################################### 117 | ** 118 | ** This file was created by Processor Expert 10.1 [05.21] 119 | ** for the Freescale S32K series of microcontrollers. 120 | ** 121 | ** ################################################################### 122 | */ 123 | 124 | -------------------------------------------------------------------------------- /Generated_Code/lpTmr1.c: -------------------------------------------------------------------------------- 1 | /* ################################################################### 2 | ** This component module is generated by Processor Expert. Do not modify it. 3 | ** Filename : lpTmr1.c 4 | ** Project : UDS_S32K144_APP 5 | ** Processor : S32K144_100 6 | ** Component : lptmr 7 | ** Version : Component SDK_S32K1xx_15, Driver 01.00, CPU db: 3.00.000 8 | ** Repository : SDK_S32K1xx_15 9 | ** Compiler : GNU C Compiler 10 | ** Date/Time : 2021-05-24, 10:45, # CodeGen: 13 11 | ** 12 | ** Copyright 1997 - 2015 Freescale Semiconductor, Inc. 13 | ** Copyright 2016-2017 NXP 14 | ** All Rights Reserved. 15 | ** 16 | ** THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR 17 | ** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 | ** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 | ** IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 20 | ** INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 21 | ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 22 | ** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 | ** HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 24 | ** STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 25 | ** IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 26 | ** THE POSSIBILITY OF SUCH DAMAGE. 27 | ** ###################################################################*/ 28 | /*! 29 | ** @file lpTmr1.c 30 | ** @version 01.00 31 | */ 32 | /*! 33 | ** @addtogroup lpTmr1_module lpTmr1 module documentation 34 | ** @{ 35 | */ 36 | 37 | /* MODULE lpTmr1. */ 38 | 39 | /** 40 | * @page misra_violations MISRA-C:2012 violations 41 | * 42 | * @section [global] 43 | * Violates MISRA 2012 Advisory Rule 8.7, External variable could be made static. 44 | * The external variables will be used in other source files, with the same initialized values. 45 | */ 46 | 47 | #include "lpTmr1.h" 48 | 49 | 50 | /*! lpTmr1 configuration structure */ 51 | 52 | 53 | const lptmr_config_t lpTmr1_config0 = { 54 | .workMode = LPTMR_WORKMODE_TIMER, 55 | .dmaRequest = false, 56 | .interruptEnable = true, 57 | .freeRun = false, 58 | .compareValue = 1000U, 59 | .counterUnits = LPTMR_COUNTER_UNITS_MICROSECONDS, 60 | .clockSelect = LPTMR_CLOCKSOURCE_PCC, 61 | .prescaler = LPTMR_PRESCALE_2, 62 | .bypassPrescaler = false, 63 | .pinSelect = LPTMR_PINSELECT_TRGMUX, 64 | .pinPolarity = LPTMR_PINPOLARITY_RISING, 65 | }; 66 | 67 | 68 | /* END lpTmr1. */ 69 | /*! 70 | ** @} 71 | */ 72 | /* 73 | ** ################################################################### 74 | ** 75 | ** This file was created by Processor Expert 10.1 [05.21] 76 | ** for the Freescale S32K series of microcontrollers. 77 | ** 78 | ** ################################################################### 79 | */ 80 | 81 | -------------------------------------------------------------------------------- /Generated_Code/lpTmr1.h: -------------------------------------------------------------------------------- 1 | /* ################################################################### 2 | ** This component module is generated by Processor Expert. Do not modify it. 3 | ** Filename : lpTmr1.h 4 | ** Project : UDS_S32K144_APP 5 | ** Processor : S32K144_100 6 | ** Component : lptmr 7 | ** Version : Component SDK_S32K1xx_15, Driver 01.00, CPU db: 3.00.000 8 | ** Repository : SDK_S32K1xx_15 9 | ** Compiler : GNU C Compiler 10 | ** Date/Time : 2021-02-20, 11:57, # CodeGen: 2 11 | ** Contents : 12 | ** LPTMR_DRV_InitConfigStruct - void LPTMR_DRV_InitConfigStruct(lptmr_config_t *const config); 13 | ** LPTMR_DRV_Init - void LPTMR_DRV_Init(const uint32_t instance,const lptmr_config_t *const... 14 | ** LPTMR_DRV_SetConfig - void LPTMR_DRV_SetConfig(const uint32_t instance,const lptmr_config_t * const... 15 | ** LPTMR_DRV_GetConfig - void LPTMR_DRV_GetConfig(const uint32_t instance,lptmr_config_t * const config); 16 | ** LPTMR_DRV_Deinit - void LPTMR_DRV_Deinit(const uint32_t instance); 17 | ** LPTMR_DRV_SetCompareValueByCount - status_t LPTMR_DRV_SetCompareValueByCount(const uint32_t instance,const... 18 | ** LPTMR_DRV_GetCompareValueByCount - void LPTMR_DRV_GetCompareValueByCount(const uint32_t instance,uint16_t *... 19 | ** LPTMR_DRV_SetCompareValueByUs - status_t LPTMR_DRV_SetCompareValueByUs(const uint32_t instance,const uint16_t... 20 | ** LPTMR_DRV_GetCompareValueByUs - void LPTMR_DRV_GetCompareValueByUs(const uint32_t instance,uint16_t * const... 21 | ** LPTMR_DRV_GetCompareFlag - bool LPTMR_DRV_GetCompareFlag(const uint32_t instance); 22 | ** LPTMR_DRV_ClearCompareFlag - void LPTMR_DRV_ClearCompareFlag(const uint32_t instance); 23 | ** LPTMR_DRV_IsRunning - bool LPTMR_DRV_IsRunning(const uint32_t instance); 24 | ** LPTMR_DRV_SetInterrupt - void LPTMR_DRV_SetInterrupt(const uint32_t instance,const bool enableInterrupt); 25 | ** LPTMR_DRV_GetCounterValueByCount - uint16_t LPTMR_DRV_GetCounterValueByCount(const uint32_t instance); 26 | ** LPTMR_DRV_StartCounter - void LPTMR_DRV_StartCounter(const uint32_t instance); 27 | ** LPTMR_DRV_StopCounter - void LPTMR_DRV_StopCounter(const uint32_t instance); 28 | ** LPTMR_DRV_SetPinConfiguration - void LPTMR_DRV_SetPinConfiguration(const uint32_t instance,const... 29 | ** 30 | ** Copyright 1997 - 2015 Freescale Semiconductor, Inc. 31 | ** Copyright 2016-2017 NXP 32 | ** All Rights Reserved. 33 | ** 34 | ** THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR 35 | ** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 36 | ** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 37 | ** IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 38 | ** INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 39 | ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 40 | ** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 41 | ** HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 42 | ** STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 43 | ** IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 44 | ** THE POSSIBILITY OF SUCH DAMAGE. 45 | ** ###################################################################*/ 46 | /*! 47 | ** @file lpTmr1.h 48 | ** @version 01.00 49 | */ 50 | /*! 51 | ** @addtogroup lpTmr1_module lpTmr1 module documentation 52 | ** @{ 53 | */ 54 | #ifndef lpTmr1_H 55 | #define lpTmr1_H 56 | /* MODULE lpTmr1. */ 57 | 58 | /** 59 | * @page misra_violations MISRA-C:2012 violations 60 | * 61 | * @section [global] 62 | * Violates MISRA 2012 Advisory Rule 2.5, global macro not referenced 63 | * There are global macros defined to be used by the integrator and another one used as include guard. 64 | */ 65 | 66 | /* Include inherited beans */ 67 | #include "clockMan1.h" 68 | #include "Cpu.h" 69 | #include "lptmr_driver.h" 70 | 71 | /*! @brief Device instance number */ 72 | #define INST_LPTMR1 0U 73 | 74 | 75 | 76 | /*! @brief Configuration declaration */ 77 | extern const lptmr_config_t lpTmr1_config0; 78 | 79 | #endif /* ifndef lpTmr1_H */ 80 | /*! 81 | ** @} 82 | */ 83 | /* 84 | ** ################################################################### 85 | ** 86 | ** This file was created by Processor Expert 10.1 [05.21] 87 | ** for the Freescale S32K series of microcontrollers. 88 | ** 89 | ** ################################################################### 90 | */ 91 | -------------------------------------------------------------------------------- /Generated_Code/lpuart1.c: -------------------------------------------------------------------------------- 1 | /* ################################################################### 2 | ** This component module is generated by Processor Expert. Do not modify it. 3 | ** Filename : lpuart1.c 4 | ** Project : UDS_S32K144_APP 5 | ** Processor : S32K144_100 6 | ** Component : lpuart 7 | ** Version : Component SDK_S32K1xx_15, Driver 01.00, CPU db: 3.00.000 8 | ** Repository : SDK_S32K1xx_15 9 | ** Compiler : GNU C Compiler 10 | ** Date/Time : 2021-02-20, 11:57, # CodeGen: 2 11 | ** Abstract : 12 | ** 13 | ** 14 | ** Copyright 1997 - 2015 Freescale Semiconductor, Inc. 15 | ** Copyright 2016-2017 NXP 16 | ** All Rights Reserved. 17 | ** 18 | ** THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR 19 | ** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 | ** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 | ** IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 22 | ** INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 23 | ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 24 | ** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 | ** HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 26 | ** STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 27 | ** IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 28 | ** THE POSSIBILITY OF SUCH DAMAGE. 29 | ** ###################################################################*/ 30 | /*! 31 | ** @file lpuart1.c 32 | ** @version 01.00 33 | ** @brief 34 | ** 35 | */ 36 | /*! 37 | ** @addtogroup lpuart1_module lpuart1 module documentation 38 | ** @{ 39 | */ 40 | 41 | /* MODULE lpuart1 42 | * 43 | * @page misra_violations MISRA-C:2012 violations 44 | * 45 | * @section [global] 46 | * Violates MISRA 2012 Advisory Rule 8.7, External could be made static. 47 | * Structure is defined for usage by application code. 48 | */ 49 | 50 | #include "lpuart1.h" 51 | 52 | /*! lpuart1 configuration structure */ 53 | const lpuart_user_config_t lpuart1_InitConfig0 = { 54 | .transferType = LPUART_USING_INTERRUPTS, 55 | .baudRate = 115200U, 56 | .parityMode = LPUART_PARITY_DISABLED, 57 | .stopBitCount = LPUART_ONE_STOP_BIT, 58 | .bitCountPerChar = LPUART_8_BITS_PER_CHAR, 59 | .rxDMAChannel = 0U, 60 | .txDMAChannel = 0U, 61 | }; 62 | 63 | 64 | /*! Driver state structure */ 65 | lpuart_state_t lpuart1_State; 66 | 67 | /* END lpuart1. */ 68 | /*! 69 | ** @} 70 | */ 71 | /* 72 | ** ################################################################### 73 | ** 74 | ** This file was created by Processor Expert 10.1 [05.21] 75 | ** for the Freescale S32K series of microcontrollers. 76 | ** 77 | ** ################################################################### 78 | */ 79 | -------------------------------------------------------------------------------- /Generated_Code/lpuart1.h: -------------------------------------------------------------------------------- 1 | /* ################################################################### 2 | ** This component module is generated by Processor Expert. Do not modify it. 3 | ** Filename : lpuart1.h 4 | ** Project : UDS_S32K144_APP 5 | ** Processor : S32K144_100 6 | ** Component : lpuart 7 | ** Version : Component SDK_S32K1xx_15, Driver 01.00, CPU db: 3.00.000 8 | ** Repository : SDK_S32K1xx_15 9 | ** Compiler : GNU C Compiler 10 | ** Date/Time : 2021-02-20, 11:57, # CodeGen: 2 11 | ** Abstract : 12 | ** 13 | ** Contents : 14 | ** LPUART_DRV_GetDefaultConfig - void LPUART_DRV_GetDefaultConfig(lpuart_user_config_t * lpuartUserConfig); 15 | ** LPUART_DRV_Init - status_t LPUART_DRV_Init(uint32 instance,lpuart_state_t *... 16 | ** LPUART_DRV_Deinit - status_t LPUART_DRV_Deinit(uint32 instance); 17 | ** LPUART_DRV_InstallRxCallback - uart_callback_t LPUART_DRV_InstallRxCallback(uint32 instance,uart_callback_t... 18 | ** LPUART_DRV_InstallTxCallback - uart_callback_t LPUART_DRV_InstallTxCallback(uint32 instance,uart_callback_t... 19 | ** LPUART_DRV_SendDataBlocking - status_t LPUART_DRV_SendDataBlocking(uint32 instance,const uint8 *... 20 | ** LPUART_DRV_SendDataPolling - status_t LPUART_DRV_SendDataPolling(uint32 instance,const uint8 *... 21 | ** LPUART_DRV_SendData - status_t LPUART_DRV_SendData(uint32 instance,const uint8 * txBuff,uint32... 22 | ** LPUART_DRV_GetTransmitStatus - status_t LPUART_DRV_GetTransmitStatus(uint32 instance,uint32 * bytesRemaining); 23 | ** LPUART_DRV_AbortSendingData - status_t LPUART_DRV_AbortSendingData(uint32 instance); 24 | ** LPUART_DRV_ReceiveDataBlocking - status_t LPUART_DRV_ReceiveDataBlocking(uint32 instance,uint8 * rxBuff,uint32... 25 | ** LPUART_DRV_ReceiveDataPolling - status_t LPUART_DRV_ReceiveDataPolling(uint32 instance,uint8 * rxBuff,uint32... 26 | ** LPUART_DRV_ReceiveData - status_t LPUART_DRV_ReceiveData(uint32 instance,uint8 * rxBuff,uint32 rxSize); 27 | ** LPUART_DRV_GetReceiveStatus - status_t LPUART_DRV_GetReceiveStatus(uint32 instance,uint32 * bytesRemaining); 28 | ** LPUART_DRV_AbortReceivingData - status_t LPUART_DRV_AbortReceivingData(uint32 instance); 29 | ** LPUART_DRV_SetBaudRate - status_t LPUART_DRV_SetBaudRate(uint32_t instance,uint32_t desiredBaudRate); 30 | ** LPUART_DRV_GetBaudRate - void LPUART_DRV_GetBaudRate(uint32_t instance, uint32_t * configuredBaudRate); 31 | ** LPUART_DRV_SetTxBuffer - status_t LPUART_DRV_SetTxBuffer(uint32 instance,const uint8 * txBuff,uint32... 32 | ** LPUART_DRV_SetRxBuffer - status_t LPUART_DRV_SetRxBuffer(uint32 instance,uint8 * rxBuff,uint32 rxSize); 33 | ** 34 | ** Copyright 1997 - 2015 Freescale Semiconductor, Inc. 35 | ** Copyright 2016-2017 NXP 36 | ** All Rights Reserved. 37 | ** 38 | ** THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR 39 | ** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 40 | ** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 41 | ** IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 42 | ** INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 43 | ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 44 | ** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 45 | ** HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 46 | ** STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 47 | ** IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 48 | ** THE POSSIBILITY OF SUCH DAMAGE. 49 | ** ###################################################################*/ 50 | /*! 51 | ** @file lpuart1.h 52 | ** @version 01.00 53 | ** @brief 54 | ** 55 | */ 56 | /*! 57 | ** @addtogroup lpuart1_module lpuart1 module documentation 58 | ** @{ 59 | */ 60 | 61 | /* MODULE lpuart1 62 | * 63 | * @page misra_violations MISRA-C:2012 violations 64 | * 65 | * @section [global] 66 | * Violates MISRA 2012 Advisory Rule 2.5, Global macro not referenced. 67 | * The macros are defined to be used by application code. 68 | */ 69 | 70 | #ifndef lpuart1_H 71 | #define lpuart1_H 72 | 73 | /* Include inherited beans */ 74 | #include "clockMan1.h" 75 | #include "dmaController1.h" 76 | #include "Cpu.h" 77 | 78 | /*! @brief Device instance number */ 79 | #define INST_LPUART1 (1U) 80 | 81 | /*! Driver state structure */ 82 | extern lpuart_state_t lpuart1_State; 83 | 84 | /*! @brief Configuration declaration */ 85 | extern const lpuart_user_config_t lpuart1_InitConfig0; 86 | 87 | #endif /* ifndef lpuart1_H */ 88 | /*! 89 | ** @} 90 | */ 91 | /* 92 | ** ################################################################### 93 | ** 94 | ** This file was created by Processor Expert 10.1 [05.21] 95 | ** for the Freescale S32K series of microcontrollers. 96 | ** 97 | ** ################################################################### 98 | */ 99 | -------------------------------------------------------------------------------- /Generated_Code/pin_mux.c: -------------------------------------------------------------------------------- 1 | /* ################################################################### 2 | ** This component module is generated by Processor Expert. Do not modify it. 3 | ** Filename : pin_mux.c 4 | ** Project : UDS_S32K144_APP 5 | ** Processor : S32K144_100 6 | ** Component : PinSettings 7 | ** Version : Component 1.2.0, Driver 1.4, CPU db: 3.00.000 8 | ** Repository : SDK_S32K1xx_15 9 | ** Compiler : GNU C Compiler 10 | ** Date/Time : 2021-02-20, 11:57, # CodeGen: 2 11 | ** Abstract : 12 | ** 13 | ** 14 | ** Copyright 1997 - 2015 Freescale Semiconductor, Inc. 15 | ** Copyright 2016-2017 NXP 16 | ** All Rights Reserved. 17 | ** 18 | ** THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR 19 | ** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 | ** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 | ** IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 22 | ** INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 23 | ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 24 | ** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 | ** HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 26 | ** STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 27 | ** IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 28 | ** THE POSSIBILITY OF SUCH DAMAGE. 29 | ** ###################################################################*/ 30 | /*! 31 | ** @file pin_mux.c 32 | ** @version 1.4 33 | ** @brief 34 | ** 35 | */ 36 | /*! 37 | ** @addtogroup pin_mux_module pin_mux module documentation 38 | ** @{ 39 | */ 40 | 41 | /* MODULE pin_mux. */ 42 | #include "device_registers.h" 43 | #include "pin_mux.h" 44 | 45 | /** 46 | * @page misra_violations MISRA-C:2012 violations 47 | * 48 | * 49 | * @section [global] 50 | * Violates MISRA 2012 Advisory Rule 11.4, A conversion should not be performed 51 | * between a pointer to object and an integer type. 52 | * The cast is required to initialize a pointer with an unsigned int define, 53 | * representing an address. 54 | * 55 | * @section [global] 56 | * Violates MISRA 2012 Required Rule 11.6, A cast shall not be performed 57 | * between pointer to void and an arithmetic type. 58 | * The cast is required to initialize a pointer with an unsigned int define, 59 | * representing an address. 60 | * 61 | * @section [global] 62 | * Violates MISRA 2012 Advisory Rule 8.7, External variable could be made static. 63 | * The external variables will be used in other source files in application code. 64 | * 65 | * @section [global] 66 | * Violates MISRA 2012 Required Rule 9.3, partial array initialization. 67 | * The object array is initialized sequentially. 68 | * 69 | * @section [global] 70 | * Violates MISRA 2012 Required Rule 9.4, Duplicate initialization of object element. 71 | * The object array is initialized sequentially. 72 | * 73 | */ 74 | 75 | /*! @brief Array of pin configuration structures */ 76 | pin_settings_config_t g_pin_mux_InitConfigArr[NUM_OF_CONFIGURED_PINS] = 77 | { 78 | { 79 | .base = PORTD, 80 | .pinPortIdx = 0u, 81 | .pullConfig = PORT_INTERNAL_PULL_NOT_ENABLED, 82 | .passiveFilter = false, 83 | .driveSelect = PORT_LOW_DRIVE_STRENGTH, 84 | .mux = PORT_MUX_AS_GPIO, 85 | .pinLock = false, 86 | .intConfig = PORT_DMA_INT_DISABLED, 87 | .clearIntFlag = false, 88 | .gpioBase = PTD, 89 | .direction = GPIO_OUTPUT_DIRECTION, 90 | .digitalFilter = false, 91 | .initValue = 1u, 92 | }, 93 | { 94 | .base = PORTE, 95 | .pinPortIdx = 5u, 96 | .pullConfig = PORT_INTERNAL_PULL_NOT_ENABLED, 97 | .passiveFilter = false, 98 | .driveSelect = PORT_LOW_DRIVE_STRENGTH, 99 | .mux = PORT_MUX_ALT5, 100 | .pinLock = false, 101 | .intConfig = PORT_DMA_INT_DISABLED, 102 | .clearIntFlag = false, 103 | .gpioBase = NULL, 104 | .digitalFilter = false, 105 | }, 106 | { 107 | .base = PORTE, 108 | .pinPortIdx = 4u, 109 | .pullConfig = PORT_INTERNAL_PULL_NOT_ENABLED, 110 | .passiveFilter = false, 111 | .driveSelect = PORT_LOW_DRIVE_STRENGTH, 112 | .mux = PORT_MUX_ALT5, 113 | .pinLock = false, 114 | .intConfig = PORT_DMA_INT_DISABLED, 115 | .clearIntFlag = false, 116 | .gpioBase = NULL, 117 | .digitalFilter = false, 118 | }, 119 | { 120 | .base = PORTD, 121 | .pinPortIdx = 16u, 122 | .pullConfig = PORT_INTERNAL_PULL_NOT_ENABLED, 123 | .passiveFilter = false, 124 | .driveSelect = PORT_LOW_DRIVE_STRENGTH, 125 | .mux = PORT_MUX_AS_GPIO, 126 | .pinLock = false, 127 | .intConfig = PORT_DMA_INT_DISABLED, 128 | .clearIntFlag = false, 129 | .gpioBase = PTD, 130 | .direction = GPIO_OUTPUT_DIRECTION, 131 | .digitalFilter = false, 132 | .initValue = 1u, 133 | }, 134 | { 135 | .base = PORTD, 136 | .pinPortIdx = 15u, 137 | .pullConfig = PORT_INTERNAL_PULL_NOT_ENABLED, 138 | .passiveFilter = false, 139 | .driveSelect = PORT_LOW_DRIVE_STRENGTH, 140 | .mux = PORT_MUX_AS_GPIO, 141 | .pinLock = false, 142 | .intConfig = PORT_DMA_INT_DISABLED, 143 | .clearIntFlag = false, 144 | .gpioBase = PTD, 145 | .direction = GPIO_OUTPUT_DIRECTION, 146 | .digitalFilter = false, 147 | .initValue = 1u, 148 | }, 149 | { 150 | .base = PORTC, 151 | .pinPortIdx = 13u, 152 | .pullConfig = PORT_INTERNAL_PULL_DOWN_ENABLED, 153 | .passiveFilter = false, 154 | .driveSelect = PORT_LOW_DRIVE_STRENGTH, 155 | .mux = PORT_MUX_AS_GPIO, 156 | .pinLock = false, 157 | .intConfig = PORT_DMA_INT_DISABLED, 158 | .clearIntFlag = false, 159 | .gpioBase = PTC, 160 | .direction = GPIO_INPUT_DIRECTION, 161 | .digitalFilter = false, 162 | }, 163 | { 164 | .base = PORTC, 165 | .pinPortIdx = 12u, 166 | .pullConfig = PORT_INTERNAL_PULL_DOWN_ENABLED, 167 | .passiveFilter = false, 168 | .driveSelect = PORT_LOW_DRIVE_STRENGTH, 169 | .mux = PORT_MUX_AS_GPIO, 170 | .pinLock = false, 171 | .intConfig = PORT_DMA_INT_DISABLED, 172 | .clearIntFlag = false, 173 | .gpioBase = PTC, 174 | .direction = GPIO_INPUT_DIRECTION, 175 | .digitalFilter = false, 176 | }, 177 | { 178 | .base = PORTC, 179 | .pinPortIdx = 7u, 180 | .pullConfig = PORT_INTERNAL_PULL_NOT_ENABLED, 181 | .passiveFilter = false, 182 | .driveSelect = PORT_LOW_DRIVE_STRENGTH, 183 | .mux = PORT_MUX_ALT2, 184 | .pinLock = false, 185 | .intConfig = PORT_DMA_INT_DISABLED, 186 | .clearIntFlag = false, 187 | .gpioBase = NULL, 188 | .digitalFilter = false, 189 | }, 190 | { 191 | .base = PORTC, 192 | .pinPortIdx = 6u, 193 | .pullConfig = PORT_INTERNAL_PULL_NOT_ENABLED, 194 | .passiveFilter = false, 195 | .driveSelect = PORT_LOW_DRIVE_STRENGTH, 196 | .mux = PORT_MUX_ALT2, 197 | .pinLock = false, 198 | .intConfig = PORT_DMA_INT_DISABLED, 199 | .clearIntFlag = false, 200 | .gpioBase = NULL, 201 | .digitalFilter = false, 202 | }, 203 | }; 204 | 205 | /* END pin_mux. */ 206 | /*! 207 | ** @} 208 | */ 209 | /* 210 | ** ################################################################### 211 | ** 212 | ** This file was created by Processor Expert 10.1 [05.21] 213 | ** for the Freescale S32K series of microcontrollers. 214 | ** 215 | ** ################################################################### 216 | */ 217 | -------------------------------------------------------------------------------- /Generated_Code/pwrMan1.c: -------------------------------------------------------------------------------- 1 | /* ################################################################### 2 | ** This component module is generated by Processor Expert. Do not modify it. 3 | ** Filename : pwrMan1.c 4 | ** Project : UDS_S32K144_APP 5 | ** Processor : S32K144_100 6 | ** Component : power_manager 7 | ** Version : Component SDK_S32K1xx_15, Driver 01.00, CPU db: 3.00.000 8 | ** Repository : SDK_S32K1xx_15 9 | ** Compiler : GNU C Compiler 10 | ** Date/Time : 2021-05-22, 21:59, # CodeGen: 12 11 | ** 12 | ** Copyright 1997 - 2015 Freescale Semiconductor, Inc. 13 | ** Copyright 2016-2017 NXP 14 | ** All Rights Reserved. 15 | ** 16 | ** THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR 17 | ** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 | ** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 | ** IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 20 | ** INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 21 | ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 22 | ** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 | ** HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 24 | ** STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 25 | ** IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 26 | ** THE POSSIBILITY OF SUCH DAMAGE. 27 | ** ###################################################################*/ 28 | /*! 29 | ** @file pwrMan1.c 30 | ** @version 01.00 31 | */ 32 | /*! 33 | ** @addtogroup pwrMan1_module pwrMan1 module documentation 34 | ** @{ 35 | */ 36 | /* pwrMan1. */ 37 | 38 | /* MODULE pwrMan1. 39 | * 40 | * @page misra_violations MISRA-C:2012 violations 41 | * 42 | * @section [global] 43 | * Violates MISRA 2012 Advisory Rule 8.7, External variable could be made static. 44 | * The external variables will be used in other source files that user initialize 45 | * to use this module. 46 | */ 47 | #include "pwrMan1.h" 48 | #include 49 | 50 | /* ************************************************************************* 51 | * Configuration structure for Power Manager Configuration 0 52 | * ************************************************************************* */ 53 | /*! @brief User Configuration structure power_managerCfg_0 */ 54 | power_manager_user_config_t pwrMan1_InitConfig0 = { 55 | .powerMode = POWER_MANAGER_RUN, /*!< Power manager mode */ 56 | .sleepOnExitValue = false, /*!< Sleep on exit value */ 57 | }; 58 | 59 | /*! @brief Array of pointers to User configuration structures */ 60 | power_manager_user_config_t * powerConfigsArr[] = { 61 | &pwrMan1_InitConfig0 62 | }; 63 | /*! @brief Array of pointers to User defined Callbacks configuration structures */ 64 | power_manager_callback_user_config_t * powerStaticCallbacksConfigsArr[] = {(void *)0}; 65 | 66 | 67 | /* END pwrMan1. */ 68 | /*! 69 | ** @} 70 | */ 71 | /* 72 | ** ################################################################### 73 | ** 74 | ** This file was created by Processor Expert 10.1 [05.21] 75 | ** for the Freescale S32K series of microcontrollers. 76 | ** 77 | ** ################################################################### 78 | */ 79 | -------------------------------------------------------------------------------- /Generated_Code/pwrMan1.h: -------------------------------------------------------------------------------- 1 | /* ################################################################### 2 | ** This component module is generated by Processor Expert. Do not modify it. 3 | ** Filename : pwrMan1.h 4 | ** Project : UDS_S32K144_APP 5 | ** Processor : S32K144_100 6 | ** Component : power_manager 7 | ** Version : Component SDK_S32K1xx_15, Driver 01.00, CPU db: 3.00.000 8 | ** Repository : SDK_S32K1xx_15 9 | ** Compiler : GNU C Compiler 10 | ** Date/Time : 2021-05-22, 21:59, # CodeGen: 12 11 | ** Contents : 12 | ** POWER_SYS_Init - status_t POWER_SYS_Init(power_manager_user_config_t *(*)... 13 | ** POWER_SYS_Deinit - status_t POWER_SYS_Deinit(void); 14 | ** POWER_SYS_SetMode - status_t POWER_SYS_SetMode(uint8_t powerModeIndex,power_manager_policy_t... 15 | ** POWER_SYS_GetLastMode - status_t POWER_SYS_GetLastMode(uint8_t* powerModeIndexPtr); 16 | ** POWER_SYS_GetLastModeConfig - status_t POWER_SYS_GetLastModeConfig(power_manager_user_config_t**... 17 | ** POWER_SYS_GetCurrentMode - power_manager_modes_t POWER_SYS_GetCurrentMode(void); 18 | ** POWER_SYS_GetErrorCallbackIndex - uint8_t POWER_SYS_GetErrorCallbackIndex(void); 19 | ** POWER_SYS_GetErrorCallback - power_manager_callback_user_config_t* POWER_SYS_GetErrorCallback(void); 20 | ** POWER_SYS_GetDefaultConfig - void POWER_SYS_GetDefaultConfig(power_manager_user_config_t * const config); 21 | ** POWER_SYS_GetResetSrcStatusCmd - bool POWER_SYS_GetResetSrcStatusCmd(const RCM_Type * const baseAddr , const... 22 | ** 23 | ** Copyright 1997 - 2015 Freescale Semiconductor, Inc. 24 | ** Copyright 2016-2017 NXP 25 | ** All Rights Reserved. 26 | ** 27 | ** THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR 28 | ** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 29 | ** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 30 | ** IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 31 | ** INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 32 | ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 33 | ** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 34 | ** HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 35 | ** STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 36 | ** IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 37 | ** THE POSSIBILITY OF SUCH DAMAGE. 38 | ** ###################################################################*/ 39 | /*! 40 | ** @file pwrMan1.h 41 | ** @version 01.00 42 | */ 43 | /*! 44 | ** @addtogroup pwrMan1_module pwrMan1 module documentation 45 | ** @{ 46 | */ 47 | #ifndef pwrMan1_H 48 | #define pwrMan1_H 49 | /* MODULE pwrMan1. */ 50 | /* Include inherited beans */ 51 | #include "clockMan1.h" 52 | #include "Cpu.h" 53 | #include "power_manager.h" 54 | 55 | /** 56 | * @page misra_violations MISRA-C:2012 violations 57 | * 58 | * @section [global] 59 | * Violates MISRA 2012 Advisory Rule 8.11, When an array with external linkage 60 | * is declared, its size should be explicitly specified. 61 | * The number of configurations/callbacks can be zero. 62 | * On the other side C language forbids declaring array of size zero. 63 | * 64 | * @section [global] 65 | * Violates MISRA 2012 Advisory Rule 2.5, Global macro not referenced. 66 | * Application or driver example may not use all symbols that are 67 | * generated by configurations generator. 68 | */ 69 | 70 | 71 | /*! @brief User configuration structure 0 */ 72 | extern power_manager_user_config_t pwrMan1_InitConfig0; 73 | /*! @brief Count of user configuration structures */ 74 | #define POWER_MANAGER_CONFIG_CNT 1U 75 | /*! @brief Array of pointers to User configuration structures */ 76 | extern power_manager_user_config_t * powerConfigsArr[]; 77 | /*! @brief Count of user Callbacks */ 78 | #define POWER_MANAGER_CALLBACK_CNT 0U 79 | 80 | /*! @brief Array of pointers to User defined static Callbacks configuration structures */ 81 | extern power_manager_callback_user_config_t * powerStaticCallbacksConfigsArr[]; 82 | 83 | 84 | #endif 85 | /* ifndef pwrMan1_H */ 86 | /*! 87 | ** @} 88 | */ 89 | /* 90 | ** ################################################################### 91 | ** 92 | ** This file was created by Processor Expert 10.1 [05.21] 93 | ** for the Freescale S32K series of microcontrollers. 94 | ** 95 | ** ################################################################### 96 | */ 97 | 98 | -------------------------------------------------------------------------------- /Generated_Code/watchdog1.c: -------------------------------------------------------------------------------- 1 | /* ################################################################### 2 | ** This component module is generated by Processor Expert. Do not modify it. 3 | ** Filename : watchdog1.c 4 | ** Project : UDS_S32K144_APP 5 | ** Processor : S32K144_100 6 | ** Component : wdog 7 | ** Version : Component SDK_S32K1xx_15, Driver 01.00, CPU db: 3.00.000 8 | ** Repository : SDK_S32K1xx_15 9 | ** Compiler : GNU C Compiler 10 | ** Date/Time : 2021-02-20, 11:57, # CodeGen: 2 11 | ** 12 | ** Copyright 1997 - 2015 Freescale Semiconductor, Inc. 13 | ** Copyright 2016-2017 NXP 14 | ** All Rights Reserved. 15 | ** 16 | ** THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR 17 | ** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 | ** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 | ** IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 20 | ** INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 21 | ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 22 | ** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 | ** HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 24 | ** STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 25 | ** IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 26 | ** THE POSSIBILITY OF SUCH DAMAGE. 27 | ** ###################################################################*/ 28 | /*! 29 | ** @file watchdog1.c 30 | ** @version 01.00 31 | */ 32 | /*! 33 | ** @addtogroup watchdog1_module watchdog1 module documentation 34 | ** @{ 35 | */ 36 | 37 | /* MODULE watchdog1. 38 | * 39 | * @page misra_violations MISRA-C:2012 violations 40 | * 41 | * @section [global] 42 | * Violates MISRA 2012 Advisory Rule 8.7, External variable could be made static. 43 | * The external variables will be used in other source files by the user. 44 | */ 45 | 46 | #include "watchdog1.h" 47 | 48 | 49 | /*! watchdog1 configuration structures */ 50 | 51 | const wdog_user_config_t watchdog1_Config0 = { 52 | .clkSource = WDOG_LPO_CLOCK, /* WDOG clock source */ 53 | .opMode = { 54 | false, /* Wait Mode */ 55 | false, /* Stop Mode */ 56 | false /* Debug Mode */ 57 | }, 58 | .updateEnable = true, /* Enable/Disable further updates of the WDOG configuration */ 59 | .intEnable = false, /* Timeout interrupt disabled */ 60 | .winEnable = false, /* Enable/Disable Window mode */ 61 | .windowValue = 0U, /* Window value */ 62 | .timeoutValue = 60000U, /* Timeout value */ 63 | .prescalerEnable = false /* WDOG prescaler */ 64 | }; 65 | 66 | /* END watchdog1. */ 67 | /*! 68 | ** @} 69 | */ 70 | /* 71 | ** ################################################################### 72 | ** 73 | ** This file was created by Processor Expert 10.1 [05.21] 74 | ** for the Freescale S32K series of microcontrollers. 75 | ** 76 | ** ################################################################### 77 | */ 78 | -------------------------------------------------------------------------------- /Generated_Code/watchdog1.h: -------------------------------------------------------------------------------- 1 | /* ################################################################### 2 | ** This component module is generated by Processor Expert. Do not modify it. 3 | ** Filename : watchdog1.h 4 | ** Project : UDS_S32K144_APP 5 | ** Processor : S32K144_100 6 | ** Component : wdog 7 | ** Version : Component SDK_S32K1xx_15, Driver 01.00, CPU db: 3.00.000 8 | ** Repository : SDK_S32K1xx_15 9 | ** Compiler : GNU C Compiler 10 | ** Date/Time : 2021-02-20, 11:57, # CodeGen: 2 11 | ** Contents : 12 | ** WDOG_DRV_Init - status_t WDOG_DRV_Init(uint32_t instance, const wdog_user_config_t *... 13 | ** WDOG_DRV_Deinit - status_t WDOG_DRV_Deinit(uint32_t instance); 14 | ** WDOG_DRV_GetConfig - void WDOG_DRV_GetConfig(uint32_t instance, wdog_user_config_t * const config); 15 | ** WDOG_DRV_GetDefaultConfig - void WDOG_DRV_GetDefaultConfig(wdog_user_config_t * const config); 16 | ** WDOG_DRV_SetInt - status_t WDOG_DRV_SetInt(uint32_t instance,bool enable); 17 | ** WDOG_DRV_ClearIntFlag - void WDOG_DRV_ClearIntFlag(uint32_t instance); 18 | ** WDOG_DRV_Trigger - void WDOG_DRV_Trigger(uint32_t instance); 19 | ** WDOG_DRV_GetCounter - uint16_t WDOG_DRV_GetCounter(uint32_t instance); 20 | ** WDOG_DRV_SetWindow - status_t WDOG_DRV_SetWindow(uint32_t instance, bool enable, uint16_t... 21 | ** WDOG_DRV_SetMode - status_t WDOG_DRV_SetMode(uint32_t instance, bool enable, wdog_set_mode_t... 22 | ** WDOG_DRV_SetTimeout - status_t WDOG_DRV_SetTimeout(uint32_t instance, uint16_t timeout); 23 | ** WDOG_DRV_SetTestMode - status_t WDOG_DRV_SetTestMode(uint32_t instance, wdog_test_mode_t testMode); 24 | ** WDOG_DRV_GetTestMode - wdog_test_mode_t WDOG_DRV_GetTestMode(uint32_t instance); 25 | ** 26 | ** Copyright 1997 - 2015 Freescale Semiconductor, Inc. 27 | ** Copyright 2016-2017 NXP 28 | ** All Rights Reserved. 29 | ** 30 | ** THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR 31 | ** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 32 | ** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 33 | ** IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 34 | ** INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 35 | ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 36 | ** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 37 | ** HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 38 | ** STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 39 | ** IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 40 | ** THE POSSIBILITY OF SUCH DAMAGE. 41 | ** ###################################################################*/ 42 | /*! 43 | ** @file watchdog1.h 44 | ** @version 01.00 45 | */ 46 | /*! 47 | ** @addtogroup watchdog1_module watchdog1 module documentation 48 | ** @{ 49 | */ 50 | #ifndef watchdog1_H 51 | #define watchdog1_H 52 | 53 | /* MODULE watchdog1. 54 | * 55 | * @page misra_violations MISRA-C:2012 violations 56 | * 57 | * @section [global] 58 | * Violates MISRA 2012 Advisory Rule 2.5, Global macro not referenced. 59 | * The global macro will be used in function call of the module. 60 | */ 61 | 62 | /* Include inherited beans */ 63 | #include "clockMan1.h" 64 | #include "Cpu.h" 65 | #include "wdog_driver.h" 66 | 67 | /*! @brief Device instance number */ 68 | #define INST_WATCHDOG1 0U 69 | 70 | extern const wdog_user_config_t watchdog1_Config0; 71 | 72 | #endif 73 | /* ifndef watchdog1_H */ 74 | /*! 75 | ** @} 76 | */ 77 | /* 78 | ** ################################################################### 79 | ** 80 | ** This file was created by Processor Expert 10.1 [05.21] 81 | ** for the Freescale S32K series of microcontrollers. 82 | ** 83 | ** ################################################################### 84 | */ 85 | -------------------------------------------------------------------------------- /LinkSetting_ForUsageFault_00.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/SummerFalls/UDS_S32K144_APP/1b2a3961f03ecf3ca39563031fc24a1d2443b8fc/LinkSetting_ForUsageFault_00.png -------------------------------------------------------------------------------- /LinkSetting_ForUsageFault_01.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/SummerFalls/UDS_S32K144_APP/1b2a3961f03ecf3ca39563031fc24a1d2443b8fc/LinkSetting_ForUsageFault_01.png -------------------------------------------------------------------------------- /LinkSetting_ForUsageFault_02.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/SummerFalls/UDS_S32K144_APP/1b2a3961f03ecf3ca39563031fc24a1d2443b8fc/LinkSetting_ForUsageFault_02.png -------------------------------------------------------------------------------- /Ozone_UDS_S32K144_APP.jdebug.user: -------------------------------------------------------------------------------- 1 | 2 | OpenDocument="multi_cyc_fifo.c", FilePath="D:/SrcCode/S32DS_2.2/UDS_S32K144_APP/UDS_ProtocolStack/multi_cyc_fifo.c", Line=340 3 | OpenDocument="main.c", FilePath="D:/SrcCode/S32DS_2.2/UDS_S32K144_APP/Sources/main.c", Line=91 4 | OpenDocument="can_tp.c", FilePath="D:/SrcCode/S32DS_2.2/UDS_S32K144_APP/UDS_ProtocolStack/can_tp.c", Line=633 5 | OpenDocument="TP.c", FilePath="D:/SrcCode/S32DS_2.2/UDS_S32K144_APP/UDS_ProtocolStack/TP.c", Line=52 6 | OpenDocument="bootloader_main.c", FilePath="D:/SrcCode/S32DS_2.2/UDS_S32K144_APP/UDS_ProtocolStack/bootloader_main.c", Line=99 7 | OpenDocument="can_tp_cfg.c", FilePath="D:/SrcCode/S32DS_2.2/UDS_S32K144_APP/UDS_ProtocolStack/can_tp_cfg.c", Line=120 8 | OpenDocument="autolibc.c", FilePath="D:/SrcCode/S32DS_2.2/UDS_S32K144_APP/UDS_ProtocolStack/autolibc.c", Line=0 9 | OpenDocument="startup_S32K144.S", FilePath="D:/SrcCode/S32DS_2.2/UDS_S32K144_APP/Project_Settings/Startup_Code/startup_S32K144.S", Line=352 10 | OpenToolbar="Debug", Floating=0, x=0, y=0 11 | OpenWindow="Call Stack", DockArea=BOTTOM, x=0, y=0, w=1713, h=281, TabPos=0, TopOfStack=1, FilterBarShown=0, TotalValueBarShown=1, ToolBarShown=0 12 | OpenWindow="Registers 1", DockArea=LEFT, x=0, y=0, w=344, h=489, TabPos=1, TopOfStack=0, FilterBarShown=0, TotalValueBarShown=0, ToolBarShown=0, FilteredItems=[], RefreshRate=1 13 | OpenWindow="Disassembly", DockArea=RIGHT, x=0, y=0, w=622, h=183, FilterBarShown=0, TotalValueBarShown=0, ToolBarShown=0 14 | OpenWindow="Break & Tracepoints", DockArea=BOTTOM, x=0, y=0, w=1713, h=281, TabPos=3, TopOfStack=0, FilterBarShown=0, TotalValueBarShown=0, ToolBarShown=0, VectorCatchIndexMask=254 15 | OpenWindow="Memory 1", DockArea=BOTTOM, x=0, y=0, w=1713, h=281, TabPos=2, TopOfStack=0, FilterBarShown=0, TotalValueBarShown=0, ToolBarShown=0, EditorAddress=0x20006F68 16 | OpenWindow="Global Data", DockArea=RIGHT, x=0, y=2, w=622, h=152, TabPos=1, TopOfStack=1, FilterBarShown=0, TotalValueBarShown=0, ToolBarShown=0 17 | OpenWindow="Local Data", DockArea=RIGHT, x=0, y=2, w=622, h=152, TabPos=0, TopOfStack=0, FilterBarShown=0, TotalValueBarShown=0, ToolBarShown=0 18 | OpenWindow="Watched Data 1", DockArea=RIGHT, x=0, y=1, w=622, h=152, FilterBarShown=0, TotalValueBarShown=0, ToolBarShown=0 19 | OpenWindow="Functions", DockArea=LEFT, x=0, y=0, w=344, h=489, TabPos=2, TopOfStack=0, FilterBarShown=0, TotalValueBarShown=0, ToolBarShown=0 20 | OpenWindow="Call Graph", DockArea=BOTTOM, x=0, y=0, w=1713, h=281, TabPos=4, TopOfStack=0, FilterBarShown=0, TotalValueBarShown=0, ToolBarShown=0 21 | OpenWindow="Memory Usage", DockArea=LEFT, x=0, y=0, w=344, h=489, TabPos=0, TopOfStack=1, FilterBarShown=0, TotalValueBarShown=0, ToolBarShown=0 22 | OpenWindow="Data Sampling", DockArea=BOTTOM, x=0, y=0, w=1713, h=281, TabPos=1, TopOfStack=0, FilterBarShown=0, TotalValueBarShown=0, ToolBarShown=0, VisibleTab=0, UniformSampleSpacing=0 23 | OpenWindow="Console", DockArea=BOTTOM, x=0, y=0, w=1713, h=281, TabPos=5, TopOfStack=0, FilterBarShown=0, TotalValueBarShown=0, ToolBarShown=0 24 | TableHeader="Global Data", SortCol="Location", SortOrder="ASCENDING", VisibleCols=["Name";"Value";"Location";"Size";"Type";"Scope"], ColWidths=[100;100;100;100;100;406] 25 | TableHeader="Registers 1", SortCol="Name", SortOrder="ASCENDING", VisibleCols=["Name";"Value";"Description"], ColWidths=[191;160;392] 26 | TableHeader="Call Stack", SortCol="Function", SortOrder="ASCENDING", VisibleCols=["Function";"Stack Frame";"Source";"PC";"Return Address";"Stack Used"], ColWidths=[877;185;209;107;216;119] 27 | TableHeader="Functions", SortCol="Name", SortOrder="ASCENDING", VisibleCols=["Name";"Address";"Size";"#Insts";"Source"], ColWidths=[944;100;100;100;203] 28 | TableHeader="Call Graph", SortCol="Name", SortOrder="ASCENDING", VisibleCols=["Name";"Stack Total";"Stack Local";"Code Total";"Code Local";"Depth";"Called From"], ColWidths=[910;100;100;100;100;100;100] 29 | TableHeader="Vector Catches", SortCol="None", SortOrder="ASCENDING", VisibleCols=["";"Vector Catch";"Description"], ColWidths=[50;300;1363] 30 | TableHeader="Break & Tracepoints", SortCol="None", SortOrder="ASCENDING", VisibleCols=["";"Type";"Location";"Extras"], ColWidths=[100;100;100;100] 31 | TableHeader="Data Sampling Table", SortCol="Index", SortOrder="ASCENDING", VisibleCols=["Index";"Time"], ColWidths=[100;100] 32 | TableHeader="Data Sampling Setup", SortCol="Expression", SortOrder="ASCENDING", VisibleCols=["Expression";"Type";"Value";"Min";"Max";"Average";"# Changes";"Min. Change";"Max. Change"], ColWidths=[100;100;100;100;100;100;100;100;101] 33 | TableHeader="Local Data", SortCol="Name", SortOrder="ASCENDING", VisibleCols=["Name";"Value";"Location";"Size";"Type";"Scope"], ColWidths=[100;100;100;100;100;122] 34 | TableHeader="Power Sampling", SortCol="Index", SortOrder="ASCENDING", VisibleCols=["Index";"Time";"Ch 0"], ColWidths=[100;100;100] 35 | TableHeader="Watched Data 1", SortCol="Expression", SortOrder="ASCENDING", VisibleCols=["Expression";"Value";"Location";"Refresh"], ColWidths=[100;100;100;322] 36 | TableHeader="RegisterSelectionDialog", SortCol="None", SortOrder="ASCENDING", VisibleCols=[], ColWidths=[] 37 | TableHeader="TargetExceptionDialog", SortCol="Name", SortOrder="ASCENDING", VisibleCols=["Name";"Value";"Address";"Description"], ColWidths=[200;100;100;890] -------------------------------------------------------------------------------- /Pic_ZCANPRO_ECU_Refresh.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/SummerFalls/UDS_S32K144_APP/1b2a3961f03ecf3ca39563031fc24a1d2443b8fc/Pic_ZCANPRO_ECU_Refresh.png -------------------------------------------------------------------------------- /Pic_ZCANPRO_ECU_Refresh_Note_ProgramSession.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/SummerFalls/UDS_S32K144_APP/1b2a3961f03ecf3ca39563031fc24a1d2443b8fc/Pic_ZCANPRO_ECU_Refresh_Note_ProgramSession.png -------------------------------------------------------------------------------- /Pic_ZCANPRO_ECU_Refresh_Note_ResetECU.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/SummerFalls/UDS_S32K144_APP/1b2a3961f03ecf3ca39563031fc24a1d2443b8fc/Pic_ZCANPRO_ECU_Refresh_Note_ResetECU.png -------------------------------------------------------------------------------- /Project_Settings/Linker_Files/S32K144_64_flash.ld: -------------------------------------------------------------------------------- 1 | /* 2 | ** ################################################################### 3 | ** Processor: S32K144 with 64 KB SRAM 4 | ** Compiler: GNU C Compiler 5 | ** 6 | ** Abstract: 7 | ** Linker file for the GNU C Compiler 8 | ** 9 | ** Copyright (c) 2015-2016 Freescale Semiconductor, Inc. 10 | ** Copyright 2017-2018 NXP 11 | ** All rights reserved. 12 | ** 13 | ** THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR 14 | ** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 15 | ** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 16 | ** IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 17 | ** INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 18 | ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 19 | ** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 | ** HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 21 | ** STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 22 | ** IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 23 | ** THE POSSIBILITY OF SUCH DAMAGE. 24 | ** 25 | ** http: www.freescale.com 26 | ** mail: support@freescale.com 27 | ** 28 | ** ################################################################### 29 | */ 30 | 31 | /* Entry Point */ 32 | ENTRY(Reset_Handler) 33 | 34 | HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x00000400; 35 | STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x00000800; 36 | 37 | /* If symbol __flash_vector_table__=1 is defined at link time 38 | * the interrupt vector will not be copied to RAM. 39 | * Warning: Using the interrupt vector from Flash will not allow 40 | * INT_SYS_InstallHandler because the section is Read Only. 41 | */ 42 | M_VECTOR_RAM_SIZE = DEFINED(__flash_vector_table__) ? 0x0 : 0x0400; 43 | 44 | /* Specify the memory areas */ 45 | MEMORY 46 | { 47 | /* Flash */ 48 | /* APP */ 49 | /*m_APP (RX) : ORIGIN = 0x00014200, LENGTH = 0x0006BE00*//*512K - 80K - 512B*/ 50 | /*m_interrupts (RX) : ORIGIN = 0x00014200, LENGTH = 0x00000400*/ 51 | /*m_flash_config (RX) : ORIGIN = 0x00014600, LENGTH = 0x00000010*/ 52 | /*m_text (RX) : ORIGIN = 0x00014610, LENGTH = 0x0006B9F0*/ 53 | 54 | m_interrupts (RX) : ORIGIN = 0x00014200, LENGTH = 0x00000400 55 | m_text (RX) : ORIGIN = 0x00014600, LENGTH = 0x0006BA00 56 | 57 | /* SRAM_L */ 58 | m_data (RW) : ORIGIN = 0x1FFF8000, LENGTH = 0x00008000 59 | 60 | /* SRAM_U */ 61 | m_data_2 (RW) : ORIGIN = 0x20000000, LENGTH = 0x00006FF0 62 | m_exchange_info (RW) : ORIGIN = 0x20006FF0, LENGTH = 0x00000010 /*16B*/ 63 | } 64 | 65 | /* Define output sections */ 66 | SECTIONS 67 | { 68 | /* The startup code goes first into internal flash */ 69 | .interrupts : 70 | { 71 | __VECTOR_TABLE = .; 72 | __interrupts_start__ = .; 73 | . = ALIGN(4); 74 | KEEP(*(.isr_vector)) /* Startup code */ 75 | __interrupts_end__ = .; 76 | . = ALIGN(4); 77 | } > m_interrupts 78 | 79 | /* .flash_config : */ 80 | /* { */ 81 | /* . = ALIGN(4); */ 82 | /* KEEP(*(.FlashConfig)) */ /* Flash Configuration Field (FCF) */ 83 | /* . = ALIGN(4); */ 84 | /* } > m_flash_config */ 85 | 86 | /* The program code and other data goes into internal flash */ 87 | .text : 88 | { 89 | . = ALIGN(4); 90 | *(.text) /* .text sections (code) */ 91 | *(.text*) /* .text* sections (code) */ 92 | *(.rodata) /* .rodata sections (constants, strings, etc.) */ 93 | *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ 94 | *(.init) /* section used in crti.o files */ 95 | *(.fini) /* section used in crti.o files */ 96 | *(.eh_frame) /* section used in crtbegin.o files */ 97 | . = ALIGN(4); 98 | } > m_text 99 | 100 | /* Section used by the libgcc.a library for fvp4 */ 101 | .ARM : 102 | { 103 | __exidx_start = .; 104 | *(.ARM.exidx*) 105 | __exidx_end = .; 106 | } > m_text 107 | 108 | __etext = .; /* Define a global symbol at end of code. */ 109 | __DATA_ROM = .; /* Symbol is used by startup for data initialization. */ 110 | 111 | .interrupts_ram : 112 | { 113 | . = ALIGN(4); 114 | __VECTOR_RAM__ = .; 115 | __RAM_START = .; 116 | __interrupts_ram_start__ = .; /* Create a global symbol at data start. */ 117 | *(.m_interrupts_ram) /* This is a user defined section. */ 118 | . += M_VECTOR_RAM_SIZE; 119 | . = ALIGN(4); 120 | __interrupts_ram_end__ = .; /* Define a global symbol at data end. */ 121 | } > m_data 122 | 123 | __VECTOR_RAM = DEFINED(__flash_vector_table__) ? ORIGIN(m_interrupts) : __VECTOR_RAM__ ; 124 | __RAM_VECTOR_TABLE_SIZE = DEFINED(__flash_vector_table__) ? 0x0 : (__interrupts_ram_end__ - __interrupts_ram_start__) ; 125 | 126 | .data : AT(__DATA_ROM) 127 | { 128 | . = ALIGN(4); 129 | __DATA_RAM = .; 130 | __data_start__ = .; /* Create a global symbol at data start. */ 131 | *(.data) /* .data sections */ 132 | *(.data*) /* .data* sections */ 133 | . = ALIGN(4); 134 | __data_end__ = .; /* Define a global symbol at data end. */ 135 | } > m_data 136 | 137 | __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); 138 | __CODE_ROM = __DATA_END; /* Symbol is used by code initialization. */ 139 | 140 | .code : AT(__CODE_ROM) 141 | { 142 | . = ALIGN(4); 143 | __CODE_RAM = .; 144 | __code_start__ = .; /* Create a global symbol at code start. */ 145 | __code_ram_start__ = .; 146 | *(.code_ram) /* Custom section for storing code in RAM */ 147 | . = ALIGN(4); 148 | __code_end__ = .; /* Define a global symbol at code end. */ 149 | __code_ram_end__ = .; 150 | } > m_data 151 | 152 | __CODE_END = __CODE_ROM + (__code_end__ - __code_start__); 153 | __CUSTOM_ROM = __CODE_END; 154 | 155 | /* Custom Section Block that can be used to place data at absolute address. */ 156 | /* Use __attribute__((section (".customSection"))) to place data here. */ 157 | .customSectionBlock ORIGIN(m_data_2) : AT(__CUSTOM_ROM) 158 | { 159 | __customSection_start__ = .; 160 | KEEP(*(.customSection)) /* Keep section even if not referenced. */ 161 | __customSection_end__ = .; 162 | } > m_data_2 163 | __CUSTOM_END = __CUSTOM_ROM + (__customSection_end__ - __customSection_start__); 164 | __rom_end = __CUSTOM_END; 165 | 166 | /* Uninitialized data section. */ 167 | .bss : 168 | { 169 | /* This is used by the startup in order to initialize the .bss section. */ 170 | . = ALIGN(4); 171 | __BSS_START = .; 172 | __bss_start__ = .; 173 | *(.bss) 174 | *(.bss*) 175 | *(COMMON) 176 | . = ALIGN(4); 177 | __bss_end__ = .; 178 | __BSS_END = .; 179 | } > m_data_2 180 | 181 | /* Put heap section after the program data */ 182 | .heap : 183 | { 184 | . = ALIGN(8); 185 | __end__ = .; 186 | __heap_start__ = .; 187 | PROVIDE(end = .); 188 | PROVIDE(_end = .); 189 | PROVIDE(__end = .); 190 | __HeapBase = .; 191 | . += HEAP_SIZE; 192 | __HeapLimit = .; 193 | __heap_limit = .; 194 | __heap_end__ = .; 195 | } > m_data_2 196 | 197 | /* Initializes stack on the end of block */ 198 | __StackTop = ORIGIN(m_data_2) + LENGTH(m_data_2); 199 | __StackLimit = __StackTop - STACK_SIZE; 200 | PROVIDE(__stack = __StackTop); 201 | __RAM_END = __StackTop; 202 | 203 | .stack __StackLimit : 204 | { 205 | . = ALIGN(8); 206 | __stack_start__ = .; 207 | . += STACK_SIZE; 208 | __stack_end__ = .; 209 | } > m_data_2 210 | 211 | .ARM.attributes 0 : { *(.ARM.attributes) } 212 | 213 | /* Memory validation */ 214 | ASSERT(__rom_end <= (ORIGIN(m_text) + LENGTH(m_text)), "Region m_text overflowed!") 215 | 216 | ASSERT(__StackLimit >= __HeapLimit, "region m_data_2 overflowed with stack and heap") 217 | } 218 | -------------------------------------------------------------------------------- /Project_Settings/Linker_Files/S32K144_64_ram.ld: -------------------------------------------------------------------------------- 1 | /* 2 | ** ################################################################### 3 | ** Processor: S32K144 with 64 KB SRAM 4 | ** Compiler: GNU C Compiler 5 | ** 6 | ** Abstract: 7 | ** Linker file for the GNU C Compiler 8 | ** 9 | ** Copyright (c) 2015-2016 Freescale Semiconductor, Inc. 10 | ** Copyright 2017-2018 NXP 11 | ** All rights reserved. 12 | ** 13 | ** THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR 14 | ** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 15 | ** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 16 | ** IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 17 | ** INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 18 | ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 19 | ** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 | ** HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 21 | ** STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 22 | ** IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 23 | ** THE POSSIBILITY OF SUCH DAMAGE. 24 | ** 25 | ** http: www.freescale.com 26 | ** mail: support@freescale.com 27 | ** 28 | ** ################################################################### 29 | */ 30 | 31 | /* Entry Point */ 32 | ENTRY(Reset_Handler) 33 | 34 | HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x00000400; 35 | STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x00000400; 36 | 37 | /* Specify the memory areas */ 38 | MEMORY 39 | { 40 | /* SRAM_L */ 41 | m_interrupts (RX) : ORIGIN = 0x1FFF8000, LENGTH = 0x00000400 42 | m_text (RX) : ORIGIN = 0x1FFF8400, LENGTH = 0x00007C00 43 | 44 | /* SRAM_U */ 45 | m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00007000 46 | } 47 | 48 | /* Define output sections */ 49 | SECTIONS 50 | { 51 | /* The startup code goes first into internal RAM */ 52 | .interrupts : 53 | { 54 | __VECTOR_TABLE = .; 55 | __interrupts_start__ = .; 56 | . = ALIGN(4); 57 | KEEP(*(.isr_vector)) /* Startup code */ 58 | __interrupts_end__ = .; 59 | . = ALIGN(4); 60 | } > m_interrupts 61 | 62 | __VECTOR_RAM = __VECTOR_TABLE; 63 | __RAM_VECTOR_TABLE_SIZE = 0x0; 64 | 65 | /* The program code and other data goes into internal RAM */ 66 | .text : 67 | { 68 | . = ALIGN(4); 69 | *(.text) /* .text sections (code) */ 70 | *(.text*) /* .text* sections (code) */ 71 | *(.rodata) /* .rodata sections (constants, strings, etc.) */ 72 | *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ 73 | *(.init) /* section used in crti.o files */ 74 | *(.fini) /* section used in crti.o files */ 75 | *(.eh_frame) /* section used in crtbegin.o files */ 76 | . = ALIGN(4); 77 | } > m_text 78 | 79 | /* Section used by the libgcc.a library for fvp4 */ 80 | .ARM : 81 | { 82 | __exidx_start = .; 83 | *(.ARM.exidx*) 84 | __exidx_end = .; 85 | } > m_text 86 | 87 | /* Section for storing functions that needs to execute from RAM */ 88 | .code_ram : 89 | { 90 | . = ALIGN(4); 91 | __CODE_RAM = .; 92 | __code_ram_start__ = .; 93 | *(.code_ram) /* Custom section for storing code in RAM */ 94 | __CODE_ROM = .; /* Symbol is used by start-up for data initialization. */ 95 | __CODE_END = .; /* No copy */ 96 | __code_ram_end__ = .; 97 | . = ALIGN(4); 98 | } > m_text 99 | 100 | __etext = .; /* Define a global symbol at end of code. */ 101 | __DATA_ROM = .; /* Symbol is used by startup for data initialization. */ 102 | __DATA_END = __DATA_ROM; /* No copy */ 103 | 104 | /* Custom Section Block that can be used to place data at absolute address. */ 105 | /* Use __attribute__((section (".customSection"))) to place data here. */ 106 | .customSectionBlock ORIGIN(m_data) : 107 | { 108 | __customSection_start__ = .; 109 | KEEP(*(.customSection)) /* Keep section even if not referenced. */ 110 | __customSection_end__ = .; 111 | __CUSTOM_ROM = .; 112 | __CUSTOM_END = .; 113 | } > m_data 114 | 115 | .data : 116 | { 117 | . = ALIGN(4); 118 | __DATA_RAM = .; 119 | __data_start__ = .; /* Create a global symbol at data start. */ 120 | *(.data) /* .data sections */ 121 | *(.data*) /* .data* sections */ 122 | . = ALIGN(4); 123 | __data_end__ = .; /* Define a global symbol at data end. */ 124 | } > m_data 125 | 126 | /* Uninitialized data section. */ 127 | .bss : 128 | { 129 | /* This is used by the startup in order to initialize the .bss section. */ 130 | . = ALIGN(4); 131 | __BSS_START = .; 132 | __bss_start__ = .; 133 | *(.bss) 134 | *(.bss*) 135 | *(COMMON) 136 | . = ALIGN(4); 137 | __bss_end__ = .; 138 | __BSS_END = .; 139 | } > m_data 140 | 141 | /* Put heap section after the program data */ 142 | .heap : 143 | { 144 | . = ALIGN(8); 145 | __end__ = .; 146 | __heap_start__ = .; 147 | PROVIDE(end = .); 148 | PROVIDE(_end = .); 149 | PROVIDE(__end = .); 150 | __HeapBase = .; 151 | . += HEAP_SIZE; 152 | __HeapLimit = .; 153 | __heap_limit = .; 154 | __heap_end__ = .; 155 | } > m_data 156 | 157 | /* Initializes stack on the end of block */ 158 | __StackTop = ORIGIN(m_data) + LENGTH(m_data); 159 | __StackLimit = __StackTop - STACK_SIZE; 160 | PROVIDE(__stack = __StackTop); 161 | 162 | .stack __StackLimit : 163 | { 164 | . = ALIGN(8); 165 | __stack_start__ = .; 166 | . += STACK_SIZE; 167 | __stack_end__ = .; 168 | } > m_data 169 | 170 | .ARM.attributes 0 : { *(.ARM.attributes) } 171 | 172 | ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") 173 | 174 | /DISCARD/ : { 175 | *(.FlashConfig) 176 | } 177 | } 178 | 179 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # :beers: UDS_S32K144_APP 2 | 3 | ```c 4 | /* 5 | * ___ ___ ___ 6 | * / /\ / /\ / /\ 7 | * / /::\ / /::\ / /::\ 8 | * / /:/\:\ / /:/\:\ / /:/\:\ 9 | * / /:/~/::\ / /:/~/:/ / /:/~/:/ 10 | * /__/:/ /:/\:\ /__/:/ /:/ /__/:/ /:/ 11 | * \ \:\/:/__\/ \ \:\/:/ \ \:\/:/ 12 | * \ \::/ \ \::/ \ \::/ 13 | * \ \:\ \ \:\ \ \:\ 14 | * \ \:\ \ \:\ \ \:\ 15 | * \__\/ \__\/ \__\/ 16 | */ 17 | ``` 18 | 19 | ## :warning: 特别注意 20 | 21 |

22 | 23 | 本工程代码仅作学习用途，不可用于实际量产环境，尚存在许多已知 BUG，`可自行调试解决` 或 `付费获取技术支持` 24 | 25 |

26 | 27 | 联系方式： 28 | 29 | :e-mail: e-mail: ro7enkranz@qq.com 30 | 31 | ## :book: 简介 32 | 33 | S32K1xx 的 CAN 接 `周立功 USBCANFD-100U-mini`，使用 `ZCANPRO` 软件的 `ECU刷新` 功能进行测试。在加载相应的安全访问算法 DLL 文件 :package: [UDS_SecurityAccess][UDS_SecurityAccess] 之后，通过相应的 UDS 服务将 :package: [UDS_S32K144_FlashDriver][UDS_S32K144_FlashDriver] 的 hex 文件下载至 :package: [UDS_S32K144_Bootloader][UDS_S32K144_Bootloader] 在链接文件中为其预先指定起始地址的 RAM 空间中，并通过 `Flash Driver` 内实际包含的相应的 Flash 驱动函数的相对偏移量以及驱动函数本身来计算相应驱动函数的入口点在 RAM 内的偏移地址后，再通过函数指针的方式调用相应的编程、擦写、校验等 `Flash API` 以实现将 :package: [UDS_S32K144_APP][UDS_S32K144_APP] 烧写至 Flash 的 APP 片区，最终实现 `ECU刷新` 的整个 APP 更新流程。 34 | 35 | :warning: 注意：S32K144-EVB 开发板需要 12V 独立供电，CAN Transceiver 方可正常工作。 36 | 37 | :game_die: 已做通用性适配，目前一套代码理论同时支持多个型号，已测试 `S32K144` 和 `S32K118` 可以同时支持。 38 | 39 | ![Pic_ZCANPRO_ECU_Refresh][Pic_ZCANPRO_ECU_Refresh] 40 | 41 | ## :link: 关联工程 42 | 43 | - :package: [UDS_SecurityAccess][UDS_SecurityAccess] 44 | - :package: [UDS_S32K144_Bootloader][UDS_S32K144_Bootloader] 45 | - :package: [UDS_S32K144_FlashDriver][UDS_S32K144_FlashDriver] 46 | - :package: [UDS_S32K144_APP][UDS_S32K144_APP] 47 | 48 | ## :gear: 硬件 & 软件 需求 49 | 50 | ### 硬件需求 51 | 52 | - S32K144-EVB 53 | - J-Link 54 | - USBCANFD-100U-mini 55 | - 12V External Power Supply 56 | 57 | ### 软件需求 58 | 59 | - S32 Design Studio for ARM Version 2.2 60 | - ZCANPRO 61 | - J-Flash 62 | 63 |
64 | 65 | --- 66 | 67 |
68 | 69 | ### :warning: 注意 70 | 71 | ![Pic_ZCANPRO_ECU_Refresh_Note_ProgramSession][Pic_ZCANPRO_ECU_Refresh_Note_ProgramSession] 72 | ![Pic_ZCANPRO_ECU_Refresh_Note_ResetECU][Pic_ZCANPRO_ECU_Refresh_Note_ResetECU] 73 | 74 | --- 75 | 76 | ### :warning: 特别注意 77 | 78 | < :ok_hand: 已解决 > 关于 `S32K144 APP 工程` 调用 `Flash_EraseFlashDriverInRAM()` 会导致程序卡死的问题进行说明记录： 79 | 80 | - 根据 Ozone 调试得知，实际现象为出现 `HardFault` ， `HFSR` 寄存器 `FORCED` 位被置 1，所以可以判断由其它 Fault 异常提升而来，实际为 `UsageFault` ， `INVSTATE` 位被置 1，如下图所示： 81 | - ![LinkSetting_ForUsageFault_00][LinkSetting_ForUsageFault_00] 82 | - 由于程序卡死的位置并不是每次都在同一位置，故初期的排查非常困难。由于同样的代码，在 `S32K118 APP 工程` 中被调用时，并不会产生该问题，所以需要从两个不同芯片的工程的不同之处寻找原因。经过比对，初步判断与两芯片的链接文件空间分配有关联，具体为两个芯片的 `Flash Driver` 所占用的 RAM 地址空间不同。其中，在 `S32K144` 的 `Bootloader 工程` 中，`m_flash_driver` 地址空间在 `APP 工程` 中会与 `m_data` 地址空间合并，从 Bootloader 跳转至 APP 时，会先调用 `Reset_Handler` 汇编函数，此汇编函数会进行相关初始化之后再跳转到 `main` 函数，其中在初始化时，会调用 `init_data_bss()` 函数，此函数其中的一个工作就是将位于 ROM 中（即 `m_interrupts` 地址空间内）的中断向量表拷贝到 RAM 中（即 `m_data` 地址空间内）的起始地址处，此时，如若在 `APP 工程` 中尝试调用 `Flash_EraseFlashDriverInRAM()` ，会对 `0x1FFF8000` 起始地址处连续 `0x800` 个字节的内容进行清零操作，而 `0x1FFF8000` ~ `0x1FFF8800` 地址空间段已经完全属于 `m_data` ，如若再执行 `Flash_EraseFlashDriverInRAM()` 则会将 RAM 中的中断向量表擦除，导致中断响应出现异常，故最终会导致程序卡死，详细配合以下截图进行分析。 83 | - ![LinkSetting_ForUsageFault_01][LinkSetting_ForUsageFault_01] 84 | - ![LinkSetting_ForUsageFault_02][LinkSetting_ForUsageFault_02] 85 | - 解决方法有两种：APP 工程中一律不调用 `Flash_EraseFlashDriverInRAM()` 或将链接文件内 `m_flash_driver` 的地址空间从 `m_data_2` 地址空间的后半段进行划分。 86 | - 但经过评估，显然前者为更恰当的解决方法，因为在 APP 工程中，已不存在 `m_flash_driver` 地址空间，此时就算在 Bootloader 中将 `m_data_2` 的后半段空间划分给 `m_flash_driver` ，在 APP 工程中再对该片空间进行自行清零的操作是不妥的，因为 `m_data_2` 会用于存放 `customSectionBlock`、 `bss`、 `heap`、 `stack`， 此时如若再在 APP 中调用 `Flash_EraseFlashDriverInRAM()` ，同样有可能会将这些数据清零。 87 | 88 | [Pic_ZCANPRO_ECU_Refresh]: ./Pic_ZCANPRO_ECU_Refresh.png 89 | [Pic_ZCANPRO_ECU_Refresh_Note_ProgramSession]: ./Pic_ZCANPRO_ECU_Refresh_Note_ProgramSession.png 90 | [Pic_ZCANPRO_ECU_Refresh_Note_ResetECU]: ./Pic_ZCANPRO_ECU_Refresh_Note_ResetECU.png 91 | [LinkSetting_ForUsageFault_00]: ./LinkSetting_ForUsageFault_00.png 92 | [LinkSetting_ForUsageFault_01]: ./LinkSetting_ForUsageFault_01.png 93 | [LinkSetting_ForUsageFault_02]: ./LinkSetting_ForUsageFault_02.png 94 | 95 | [UDS_SecurityAccess]: https://github.com/SummerFalls/UDS_SecurityAccess 96 | [UDS_S32K144_Bootloader]: https://github.com/SummerFalls/UDS_S32K144_Bootloader 97 | [UDS_S32K144_FlashDriver]: https://github.com/SummerFalls/UDS_S32K144_FlashDriver 98 | [UDS_S32K144_APP]: https://github.com/SummerFalls/UDS_S32K144_APP 99 | -------------------------------------------------------------------------------- /SDK/platform/devices/S32K144/startup/system_S32K144.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2015 Freescale Semiconductor, Inc. 3 | * Copyright 2016-2017 NXP 4 | * All rights reserved. 5 | * 6 | * THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR 7 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 8 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 9 | * IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 10 | * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 11 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 12 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 13 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 14 | * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 15 | * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 16 | * THE POSSIBILITY OF SUCH DAMAGE. 17 | */ 18 | 19 | 20 | /*! @addtogroup soc_support_S32K144*/ 21 | /*! @{*/ 22 | 23 | /*! 24 | * @file system_S32K144.h 25 | * @brief Device specific configuration file for S32K144 26 | */ 27 | 28 | #ifndef SYSTEM_S32K144_H_ 29 | #define SYSTEM_S32K144_H_ /**< Symbol preventing repeated inclusion */ 30 | 31 | #include 32 | 33 | #ifdef __cplusplus 34 | extern "C" { 35 | #endif 36 | 37 | /****************************************************************************** 38 | * CPU Settings. 39 | *****************************************************************************/ 40 | 41 | /* Watchdog disable */ 42 | #ifndef DISABLE_WDOG 43 | #define DISABLE_WDOG 1 44 | #endif 45 | 46 | /* Cache enablement */ 47 | #ifndef ICACHE_ENABLE 48 | #define ICACHE_ENABLE 0 49 | #endif 50 | 51 | /* Value of the external crystal or oscillator clock frequency in Hz */ 52 | #ifndef CPU_XTAL_CLK_HZ 53 | #define CPU_XTAL_CLK_HZ 8000000u 54 | #endif 55 | 56 | /* Value of the fast internal oscillator clock frequency in Hz */ 57 | #ifndef CPU_INT_FAST_CLK_HZ 58 | #define CPU_INT_FAST_CLK_HZ 48000000u 59 | #endif 60 | 61 | /* Default System clock value */ 62 | #ifndef DEFAULT_SYSTEM_CLOCK 63 | #define DEFAULT_SYSTEM_CLOCK 48000000u 64 | #endif 65 | 66 | /** 67 | * @brief System clock frequency (core clock) 68 | * 69 | * The system clock frequency supplied to the SysTick timer and the processor 70 | * core clock. This variable can be used by the user application to setup the 71 | * SysTick timer or configure other parameters. It may also be used by debugger to 72 | * query the frequency of the debug timer or configure the trace clock speed 73 | * SystemCoreClock is initialized with a correct predefined value. 74 | */ 75 | extern uint32_t SystemCoreClock; 76 | 77 | /** 78 | * @brief Setup the SoC. 79 | * 80 | * This function disables the watchdog, enables FPU. 81 | * if the corresponding feature macro is enabled. 82 | * SystemInit is called from startup_device file. 83 | */ 84 | void SystemInit(void); 85 | 86 | /** 87 | * @brief Updates the SystemCoreClock variable. 88 | * 89 | * It must be called whenever the core clock is changed during program 90 | * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates 91 | * the current core clock. 92 | * This function must be called when user does not want to use clock manager component. 93 | * If clock manager is used, the CLOCK_SYS_GetFreq function must be used with CORE_CLOCK 94 | * parameter. 95 | * 96 | */ 97 | void SystemCoreClockUpdate(void); 98 | 99 | /** 100 | * @brief Initiates a system reset. 101 | * 102 | * This function is used to initiate a system reset 103 | */ 104 | void SystemSoftwareReset(void); 105 | 106 | #ifdef __cplusplus 107 | } 108 | #endif 109 | 110 | /*! @}*/ 111 | #endif /* #if !defined(SYSTEM_S32K144_H_) */ 112 | -------------------------------------------------------------------------------- /SDK/platform/devices/callbacks.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright 2017 NXP 3 | * All rights reserved. 4 | * 5 | * THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR 6 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 7 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 8 | * IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 9 | * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 10 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 11 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 12 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 13 | * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 14 | * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 15 | * THE POSSIBILITY OF SUCH DAMAGE. 16 | */ 17 | 18 | #ifndef CALLBACKS_H 19 | #define CALLBACKS_H 20 | #include 21 | /** 22 | * @page misra_violations MISRA-C:2012 violations 23 | * 24 | * 25 | * @section [global] 26 | * Violates MISRA 2012 Advisory Rule 2.3, A project should not contain 27 | * unused type declarations. 28 | * The header defines callback types for all PAL modules. 29 | */ 30 | 31 | #include 32 | 33 | /******************************************************************************* 34 | * Definitions 35 | ******************************************************************************/ 36 | 37 | /*! 38 | * @brief Define the enum of the events which can trigger I2C slave callback 39 | * 40 | * This enum should include the events for all platforms 41 | */ 42 | typedef enum 43 | { 44 | I2C_SLAVE_EVENT_RX_FULL = 0x00U, 45 | I2C_SLAVE_EVENT_TX_EMPTY = 0x01U, 46 | I2C_SLAVE_EVENT_TX_REQ = 0x02U, 47 | I2C_SLAVE_EVENT_RX_REQ = 0x03U, 48 | I2C_SLAVE_EVENT_STOP = 0X04U, 49 | }i2c_slave_event_t; 50 | 51 | /*! 52 | * @brief Define the enum of the events which can trigger I2C master callback 53 | * 54 | * This enum should include the events for all platforms 55 | * 56 | */ 57 | typedef enum 58 | { 59 | I2C_MASTER_EVENT_END_TRANSFER = 0x4U, 60 | }i2c_master_event_t; 61 | 62 | 63 | /* Callback for all peripherals which supports I2C features for slave mode */ 64 | typedef void (*i2c_slave_callback_t)(i2c_slave_event_t event, void *userData); 65 | 66 | /* Callback for all peripherals which supports I2C features for master mode */ 67 | typedef void (*i2c_master_callback_t)(i2c_master_event_t event, void *userData); 68 | 69 | /* Define the enum of the events which can trigger SPI callback 70 | * This enum should include the events for all platforms 71 | */ 72 | typedef enum 73 | { 74 | SPI_EVENT_END_TRANSFER = 0 75 | } spi_event_t; 76 | 77 | /* Callback for all peripherals which supports SPI features */ 78 | typedef void (*spi_callback_t)(void *driverState, spi_event_t event, void *userData); 79 | 80 | /*! 81 | * @brief Define the enum of the events which can trigger UART callback 82 | * 83 | * This enum should include the events for all platforms 84 | * 85 | * Implements : uart_event_t_Class 86 | */ 87 | typedef enum 88 | { 89 | UART_EVENT_RX_FULL = 0x00U, /*!< Rx buffer is full */ 90 | UART_EVENT_TX_EMPTY = 0x01U, /*!< Tx buffer is empty */ 91 | UART_EVENT_END_TRANSFER = 0x02U, /*!< The current transfer is ending */ 92 | UART_EVENT_ERROR = 0x03U, /*!< An error occured during transfer */ 93 | } uart_event_t; 94 | 95 | /*! 96 | * @brief Callback for all peripherals which support UART features 97 | * 98 | * Implements : uart_callback_t_Class 99 | */ 100 | typedef void (*uart_callback_t)(void *driverState, uart_event_t event, void *userData); 101 | 102 | 103 | /* Callback for all peripherals which support TIMING features */ 104 | typedef void (*timer_callback_t)(void *userData); 105 | 106 | 107 | /*! @brief Defines a structure used to pass information to the ADC PAL callback 108 | * 109 | * Implements : adc_callback_info_t_Class 110 | */ 111 | typedef struct 112 | { 113 | uint32_t groupIndex; /*!< Index of the group executing the callback. */ 114 | uint16_t resultBufferTail; /*!< Offset of the most recent conversion result in the result buffer. */ 115 | } adc_callback_info_t; 116 | 117 | /*! @brief Defines the callback used to be called by ADC PAL after the last conversion result in a group 118 | * has been copied to the result buffer. 119 | */ 120 | typedef void (* const adc_callback_t)(const adc_callback_info_t * const callbackInfo, void * userData); 121 | 122 | /* I2S */ 123 | /* Define the enum of the events which can trigger i2s callback */ 124 | /* Events for all peripherals which support i2s 125 | * 126 | * Implements : i2s_event_t_Class 127 | */ 128 | typedef enum 129 | { 130 | I2S_EVENT_RX_FULL = 0x00U, /*!< Rx buffer is full */ 131 | I2S_EVENT_TX_EMPTY = 0x01U, /*!< Tx buffer is empty */ 132 | I2S_EVENT_END_TRANSFER = 0x02U, /*!< The current transfer is ending. Only FLEXIO instance uses this event. The difference between this and event TX_EMPTY is: 133 | TX_EMPTY is generated when all data has been pushed to hardware fifo, users should not call DeInit here or some last data will be lost; 134 | END_TRANSFER is generated when all data has been pushed to line, the transmission will be stopped before users can start transmit again, user can call DeInit here. 135 | For receiving case, this event is the same as RX_FULL. 136 | */ 137 | I2S_EVENT_ERROR = 0x03U, /*!< An error occurred during transfer */ 138 | } i2s_event_t; 139 | 140 | /* Callback for all peripherals which support i2s 141 | * 142 | * Implements : i2s_callback_t_Class 143 | */ 144 | typedef void (*i2s_callback_t)(i2s_event_t event, void *userData); 145 | 146 | /*! @brief Define the enum of the events which can trigger CAN callback 147 | * This enum should include the events for all platforms 148 | * Implements : can_event_t_Class 149 | */ 150 | typedef enum { 151 | CAN_EVENT_RX_COMPLETE, /*!< A frame was received in the configured Rx buffer. */ 152 | CAN_EVENT_TX_COMPLETE, /*!< A frame was sent from the configured Tx buffer. */ 153 | } can_event_t; 154 | 155 | /*! @brief Callback for all peripherals which support CAN features 156 | * Implements : can_callback_t_Class 157 | */ 158 | typedef void (*can_callback_t)(uint32_t instance, 159 | can_event_t eventType, 160 | uint32_t objIdx, 161 | void *driverState); 162 | 163 | /*! 164 | * @brief Callback for security modules 165 | * Implements : security_callback_t_Class 166 | */ 167 | typedef void (*security_callback_t)(uint32_t completedCmd, void *callbackParam); 168 | 169 | /* Define the enum of the events which can trigger the output compare callback */ 170 | typedef enum 171 | { 172 | OC_EVENT_GENERATION_OUTPUT_COMPLETE = 0x00U /*!< Generation output signal is completed */ 173 | } oc_event_t; 174 | 175 | /* Callback for all peripherals which support OC feature */ 176 | typedef void (*oc_callback_t)(oc_event_t event, void *userData); 177 | /* Define the enum of the events which can trigger the input capture callback */ 178 | typedef enum 179 | { 180 | IC_EVENT_MEASUREMENT_COMPLETE = 0x00U /*!< Capture input signal is completed */ 181 | } ic_event_t; 182 | 183 | /* Callback for all peripherals which support IC feature */ 184 | typedef void (*ic_callback_t)(ic_event_t event, void *userData); 185 | 186 | #endif /* CALLBACKS_H */ 187 | 188 | /******************************************************************************* 189 | * EOF 190 | ******************************************************************************/ 191 | -------------------------------------------------------------------------------- /SDK/platform/devices/common/s32_core_cm4.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2015-2016 Freescale Semiconductor, Inc. 3 | * Copyright 2016-2017 NXP 4 | * All rights reserved. 5 | * 6 | * THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR 7 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 8 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 9 | * IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 10 | * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 11 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 12 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 13 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 14 | * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 15 | * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 16 | * THE POSSIBILITY OF SUCH DAMAGE. 17 | * 18 | */ 19 | /*! 20 | * @file s32_core_cm4.h 21 | * 22 | * @page misra_violations MISRA-C:2012 violations 23 | * 24 | * @section [global] 25 | * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 26 | * Function-like macros are used instead of inline functions in order to ensure 27 | * that the performance will not be decreased if the functions will not be 28 | * inlined by the compiler. 29 | * 30 | * @section [global] 31 | * Violates MISRA 2012 Advisory Rule 2.5, Global macro not referenced. 32 | * The macros defined are used only on some of the drivers, so this might be reported 33 | * when the analysis is made only on one driver. 34 | */ 35 | 36 | /* 37 | * Tool Chains: 38 | * GNUC flag is defined also by ARM compiler - it shows the current major version of the compatible GCC version 39 | * __GNUC__ : GNU Compiler Collection 40 | * __ghs__ : Green Hills ARM Compiler 41 | * __ICCARM__ : IAR ARM Compiler 42 | * __DCC__ : Wind River Diab Compiler 43 | * __ARMCC_VERSION: ARM Compiler 44 | */ 45 | 46 | #if !defined (CORE_CM4_H) 47 | #define CORE_CM4_H 48 | 49 | 50 | #ifdef __cplusplus 51 | extern "C" { 52 | #endif 53 | 54 | /** \brief BKPT_ASM 55 | * 56 | * Macro to be used to trigger an debug interrupt 57 | */ 58 | #define BKPT_ASM __asm("BKPT #0\n\t") 59 | 60 | 61 | /** \brief Enable FPU 62 | * 63 | * ENABLE_FPU indicates whether SystemInit will enable the Floating point unit (FPU) 64 | */ 65 | #if defined (__GNUC__) || defined (__ARMCC_VERSION) 66 | #if defined (__VFP_FP__) && !defined (__SOFTFP__) 67 | #define ENABLE_FPU 68 | #endif 69 | 70 | #elif defined (__ICCARM__) 71 | #if defined __ARMVFP__ 72 | #define ENABLE_FPU 73 | #endif 74 | 75 | #elif defined (__ghs__) || defined (__DCC__) 76 | #if defined (__VFP__) 77 | #define ENABLE_FPU 78 | #endif 79 | #endif /* if defined (__GNUC__) */ 80 | 81 | /** \brief Enable interrupts 82 | */ 83 | #if defined (__GNUC__) 84 | #define ENABLE_INTERRUPTS() __asm volatile ("cpsie i" : : : "memory"); 85 | #else 86 | #define ENABLE_INTERRUPTS() __asm("cpsie i") 87 | #endif 88 | 89 | 90 | /** \brief Disable interrupts 91 | */ 92 | #if defined (__GNUC__) 93 | #define DISABLE_INTERRUPTS() __asm volatile ("cpsid i" : : : "memory"); 94 | #else 95 | #define DISABLE_INTERRUPTS() __asm("cpsid i") 96 | #endif 97 | 98 | 99 | /** \brief Enter low-power standby state 100 | * WFI (Wait For Interrupt) makes the processor suspend execution (Clock is stopped) until an IRQ interrupts. 101 | */ 102 | #if defined (__GNUC__) 103 | #define STANDBY() __asm volatile ("wfi") 104 | #else 105 | #define STANDBY() __asm("wfi") 106 | #endif 107 | 108 | /** \brief No-op 109 | */ 110 | #define NOP() __asm volatile ("nop") 111 | 112 | /** \brief Reverse byte order in a word. 113 | */ 114 | #if defined (__GNUC__) || defined (__ICCARM__) || defined (__ghs__) || defined (__ARMCC_VERSION) 115 | #define REV_BYTES_32(a, b) __asm volatile ("rev %0, %1" : "=r" (b) : "r" (a)) 116 | #else 117 | #define REV_BYTES_32(a, b) (b = ((a & 0xFF000000U) >> 24U) | ((a & 0xFF0000U) >> 8U) \ 118 | | ((a & 0xFF00U) << 8U) | ((a & 0xFFU) << 24U)) 119 | #endif 120 | 121 | /** \brief Reverse byte order in each halfword independently. 122 | */ 123 | #if defined (__GNUC__) || defined (__ICCARM__) || defined (__ghs__) || defined (__ARMCC_VERSION) 124 | #define REV_BYTES_16(a, b) __asm volatile ("rev16 %0, %1" : "=r" (b) : "r" (a)) 125 | #else 126 | #define REV_BYTES_16(a, b) (b = ((a & 0xFF000000U) >> 8U) | ((a & 0xFF0000U) << 8U) \ 127 | | ((a & 0xFF00U) >> 8U) | ((a & 0xFFU) << 8U)) 128 | #endif 129 | 130 | /** \brief Places a function in RAM. 131 | */ 132 | #if defined ( __GNUC__ ) || defined (__ARMCC_VERSION) 133 | #define START_FUNCTION_DECLARATION_RAMSECTION 134 | #define END_FUNCTION_DECLARATION_RAMSECTION __attribute__((section (".code_ram"))); 135 | #elif defined ( __ghs__ ) 136 | #define START_FUNCTION_DECLARATION_RAMSECTION _Pragma("ghs callmode=far") 137 | #define END_FUNCTION_DECLARATION_RAMSECTION __attribute__((section (".code_ram")));\ 138 | _Pragma("ghs callmode=default") 139 | #elif defined ( __ICCARM__ ) 140 | #define START_FUNCTION_DECLARATION_RAMSECTION __ramfunc 141 | #define END_FUNCTION_DECLARATION_RAMSECTION ; 142 | #elif defined ( __DCC__ ) 143 | #define START_FUNCTION_DECLARATION_RAMSECTION _Pragma("section CODE \".code_ram\"") \ 144 | _Pragma("use_section CODE") 145 | #define END_FUNCTION_DECLARATION_RAMSECTION ; \ 146 | _Pragma("section CODE \".text\"") 147 | #else 148 | /* Keep compatibility with software analysis tools */ 149 | #define START_FUNCTION_DECLARATION_RAMSECTION 150 | #define END_FUNCTION_DECLARATION_RAMSECTION ; 151 | #endif 152 | 153 | /* For GCC, IAR, GHS, Diab and ARMC there is no need to specify the section when 154 | defining a function, it is enough to specify it at the declaration. This 155 | also enables compatibility with software analysis tools. */ 156 | #define START_FUNCTION_DEFINITION_RAMSECTION 157 | #define END_FUNCTION_DEFINITION_RAMSECTION 158 | 159 | #if defined (__ICCARM__) 160 | #define DISABLE_CHECK_RAMSECTION_FUNCTION_CALL _Pragma("diag_suppress=Ta022") 161 | #define ENABLE_CHECK_RAMSECTION_FUNCTION_CALL _Pragma("diag_default=Ta022") 162 | #else 163 | #define DISABLE_CHECK_RAMSECTION_FUNCTION_CALL 164 | #define ENABLE_CHECK_RAMSECTION_FUNCTION_CALL 165 | #endif 166 | 167 | /** \brief Get Core ID 168 | * 169 | * GET_CORE_ID returns the processor identification number for cm4 170 | */ 171 | #define GET_CORE_ID() 0U 172 | 173 | /** \brief Data alignment. 174 | */ 175 | #if defined ( __GNUC__ ) || defined ( __ghs__ ) || defined ( __DCC__ ) || defined (__ARMCC_VERSION) 176 | #define ALIGNED(x) __attribute__((aligned(x))) 177 | #elif defined ( __ICCARM__ ) 178 | #define stringify(s) tostring(s) 179 | #define tostring(s) #s 180 | #define ALIGNED(x) _Pragma(stringify(data_alignment=x)) 181 | #else 182 | /* Keep compatibility with software analysis tools */ 183 | #define ALIGNED(x) 184 | #endif 185 | 186 | /** \brief Endianness. 187 | */ 188 | #define CORE_LITTLE_ENDIAN 189 | 190 | #ifdef __cplusplus 191 | } 192 | #endif 193 | 194 | #endif /* CORE_CM4_H */ 195 | 196 | /******************************************************************************* 197 | * EOF 198 | ******************************************************************************/ 199 | -------------------------------------------------------------------------------- /SDK/platform/devices/devassert.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2015, Freescale Semiconductor, Inc. 3 | * Copyright 2016-2017 NXP 4 | * All rights reserved. 5 | * 6 | * THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR 7 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 8 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 9 | * IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 10 | * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 11 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 12 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 13 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 14 | * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 15 | * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 16 | * THE POSSIBILITY OF SUCH DAMAGE. 17 | */ 18 | 19 | #ifndef DEVASSERT_H 20 | #define DEVASSERT_H 21 | 22 | #include 23 | 24 | /** 25 | * @page misra_violations MISRA-C:2012 violations 26 | * 27 | * @section [global] 28 | * Violates MISRA 2012 Advisory Rule 2.5, global macro not referenced. 29 | * The macro is defined to be used by drivers to validate input parameters and can be disabled. 30 | * 31 | * @section [global] 32 | * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro defined. 33 | * The macros are used to validate input parameters to driver functions. 34 | * 35 | */ 36 | 37 | /** 38 | \page Error_detection_and_reporting Error detection and reporting 39 | 40 | S32 SDK drivers can use a mechanism to validate data coming from upper software layers (application code) by performing 41 | a number of checks on input parameters' range or other invariants that can be statically checked (not dependent on 42 | runtime conditions). A failed validation is indicative of a software bug in application code, therefore it is important 43 | to use this mechanism during development. 44 | 45 | The validation is performed by using DEV_ASSERT macro. 46 | A default implementation of this macro is provided in this file. However, application developers can provide their own 47 | implementation in a custom file. This requires defining the CUSTOM_DEVASSERT symbol with the specific file name in the 48 | project configuration (for example: -DCUSTOM_DEVASSERT="custom_devassert.h") 49 | 50 | The default implementation accommodates two behaviors, based on DEV_ERROR_DETECT symbol: 51 | - When DEV_ERROR_DETECT symbol is defined in the project configuration (for example: -DDEV_ERROR_DETECT), the validation 52 | performed by the DEV_ASSERT macro is enabled, and a failed validation triggers a software breakpoint and further execution is 53 | prevented (application spins in an infinite loop) 54 | This configuration is recommended for development environments, as it prevents further execution and allows investigating 55 | potential problems from the point of error detection. 56 | - When DEV_ERROR_DETECT symbol is not defined, the DEV_ASSERT macro is implemented as no-op, therefore disabling all validations. 57 | This configuration can be used to eliminate the overhead of development-time checks. 58 | 59 | It is the application developer's responsibility to decide the error detection strategy for production code: one can opt to 60 | disable development-time checking altogether (by not defining DEV_ERROR_DETECT symbol), or one can opt to keep the checks 61 | in place and implement a recovery mechanism in case of a failed validation, by defining CUSTOM_DEVASSERT to point 62 | to the file containing the custom implementation. 63 | */ 64 | 65 | #if defined (CUSTOM_DEVASSERT) 66 | /* If the CUSTOM_DEVASSERT symbol is defined, then add the custom implementation */ 67 | #include CUSTOM_DEVASSERT 68 | #elif defined (DEV_ERROR_DETECT) 69 | /* Implement default assert macro */ 70 | static inline void DevAssert(volatile bool x) 71 | { 72 | if(x) { } else { BKPT_ASM; for(;;) {} } 73 | } 74 | #define DEV_ASSERT(x) DevAssert(x) 75 | #else 76 | /* Assert macro does nothing */ 77 | #define DEV_ASSERT(x) ((void)0) 78 | #endif 79 | 80 | #endif /* DEVASSERT_H */ 81 | 82 | /******************************************************************************* 83 | * EOF 84 | ******************************************************************************/ 85 | -------------------------------------------------------------------------------- /SDK/platform/devices/startup.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc. 3 | * Copyright 2016-2017 NXP 4 | * All rights reserved. 5 | * 6 | * THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR 7 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 8 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 9 | * IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 10 | * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 11 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 12 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 13 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 14 | * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 15 | * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 16 | * THE POSSIBILITY OF SUCH DAMAGE. 17 | */ 18 | 19 | #ifndef STARTUP_H 20 | #define STARTUP_H 21 | 22 | #include 23 | #include "device_registers.h" 24 | /** 25 | * @page misra_violations MISRA-C:2012 violations 26 | * 27 | * @section [global] 28 | * Violates MISRA 2012 Advisory Rule 2.5, Local macro not referenced. 29 | * The defined macro is used as include guard. 30 | * 31 | * @section [global] 32 | * Violates MISRA 2012 Advisory Rule 8.9, An object should be defined at block 33 | * scope if its identifier only appears in a single function. 34 | * All variables with this problem are defined in the linker files. 35 | * 36 | */ 37 | 38 | /******************************************************************************* 39 | * API 40 | ******************************************************************************/ 41 | 42 | /*! 43 | * @brief define symbols that specific start and end addres of some basic sections. 44 | */ 45 | #if (defined(S32K14x_SERIES) || defined(S32K11x_SERIES) || defined(S32V234_SERIES) || defined(MPC574x_SERIES) || defined(S32R_SERIES) || defined(S32MTV_SERIES) || defined(SJA1110_SERIES)) 46 | #if (defined(__ICCARM__)) 47 | #define INTERRUPTS_SECTION_START __section_begin(".intvec") 48 | #define INTERRUPTS_SECTION_END __section_end(".intvec") 49 | #define BSS_SECTION_START __section_begin(".bss") 50 | #define BSS_SECTION_END __section_end(".bss") 51 | #define DATA_SECTION_START __section_begin(".data") 52 | #define DATA_SECTION_END __section_end(".data") 53 | #define CUSTOMSECTION_SECTION_START __section_begin(".customSection") 54 | #define CUSTOMSECTION_SECTION_END __section_end(".customSection") 55 | #define CODE_RAM_SECTION_START __section_begin("__CODE_RAM") 56 | #define CODE_RAM_SECTION_END __section_end("__CODE_RAM") 57 | #define DATA_INIT_SECTION_START __section_begin(".data_init") 58 | #define DATA_INIT_SECTION_END __section_end(".data_init") 59 | #define CODE_ROM_SECTION_START __section_begin("__CODE_ROM") 60 | #define CODE_ROM_SECTION_END __section_end("__CODE_ROM") 61 | 62 | #elif (defined(__ARMCC_VERSION)) 63 | #define INTERRUPTS_SECTION_START (uint8_t *)__VECTOR_ROM_START 64 | #define INTERRUPTS_SECTION_END (uint8_t *)__VECTOR_ROM_END 65 | #define BSS_SECTION_START (uint8_t *)__BSS_START 66 | #define BSS_SECTION_END (uint8_t *)__BSS_END 67 | #define DATA_SECTION_START (uint8_t *)__DATA_RAM_START 68 | #define DATA_SECTION_END (uint8_t *)__DATA_RAM_END 69 | #define CUSTOMSECTION_SECTION_START (uint8_t *)__CUSTOM_SECTION_START 70 | #define CUSTOMSECTION_SECTION_END (uint8_t *)__CUSTOM_SECTION_END 71 | #define CODE_RAM_SECTION_START (uint8_t *)__CODE_RAM_START 72 | #define CODE_RAM_SECTION_END (uint8_t *)__CODE_RAM_END 73 | 74 | extern uint32_t __VECTOR_ROM_START; 75 | extern uint32_t __VECTOR_ROM_END; 76 | extern uint32_t __BSS_START; 77 | extern uint32_t __BSS_END; 78 | extern uint32_t __DATA_RAM_START; 79 | extern uint32_t __DATA_RAM_END; 80 | extern uint32_t __CUSTOM_SECTION_START; 81 | extern uint32_t __CUSTOM_SECTION_END; 82 | extern uint32_t __CODE_RAM_START; 83 | extern uint32_t __CODE_RAM_END; 84 | #else 85 | #define INTERRUPTS_SECTION_START (uint8_t *)&__interrupts_start__ 86 | #define INTERRUPTS_SECTION_END (uint8_t *)&__interrupts_end__ 87 | #define BSS_SECTION_START (uint8_t *)&__bss_start__ 88 | #define BSS_SECTION_END (uint8_t *)&__bss_end__ 89 | #define DATA_SECTION_START (uint8_t *)&__data_start__ 90 | #define DATA_SECTION_END (uint8_t *)&__data_end__ 91 | #define CUSTOMSECTION_SECTION_START (uint8_t *)&__customSection_start__ 92 | #define CUSTOMSECTION_SECTION_END (uint8_t *)&__customSection_end__ 93 | #define CODE_RAM_SECTION_START (uint8_t *)&__code_ram_start__ 94 | #define CODE_RAM_SECTION_END (uint8_t *)&__code_ram_end__ 95 | 96 | extern uint32_t __interrupts_start__; 97 | extern uint32_t __interrupts_end__; 98 | extern uint32_t __bss_start__; 99 | extern uint32_t __bss_end__; 100 | extern uint32_t __data_start__; 101 | extern uint32_t __data_end__; 102 | extern uint32_t __customSection_start__; 103 | extern uint32_t __customSection_end__; 104 | extern uint32_t __code_ram_start__; 105 | extern uint32_t __code_ram_end__; 106 | #endif 107 | #endif 108 | 109 | #if (defined(__ICCARM__)) 110 | #pragma section = ".data" 111 | #pragma section = ".data_init" 112 | #pragma section = ".bss" 113 | #pragma section = ".intvec" 114 | #pragma section = ".customSection" 115 | #pragma section = ".customSection_init" 116 | #pragma section = "__CODE_RAM" 117 | #pragma section = "__CODE_ROM" 118 | #endif 119 | 120 | /*! 121 | * @brief Make necessary initializations for RAM. 122 | * 123 | * - Copy initialized data from ROM to RAM. 124 | * - Clear the zero-initialized data section. 125 | * - Copy the vector table from ROM to RAM. This could be an option. 126 | */ 127 | void init_data_bss(void); 128 | 129 | #endif /* STARTUP_H*/ 130 | /******************************************************************************* 131 | * EOF 132 | ******************************************************************************/ 133 | 134 | -------------------------------------------------------------------------------- /SDK/platform/drivers/inc/clock.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc. 3 | * Copyright 2016-2017 NXP 4 | * All rights reserved. 5 | * 6 | * THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR 7 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 8 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 9 | * IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 10 | * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 11 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 12 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 13 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 14 | * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 15 | * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 16 | * THE POSSIBILITY OF SUCH DAMAGE. 17 | */ 18 | 19 | #if !defined(CLOCK_H) 20 | #define CLOCK_H 21 | 22 | #include "device_registers.h" 23 | #include "status.h" 24 | 25 | /* 26 | * Include the cpu specific clock API header files. 27 | */ 28 | 29 | #if (defined(S32K14x_SERIES) || defined(S32K11x_SERIES)) 30 | /* S32K144 Clock System Level API header file */ 31 | #include "../src/clock/S32K1xx/clock_S32K1xx.h" 32 | #elif (defined(S32MTV_SERIES)) 33 | /* S32MTV Clock System Level API header file */ 34 | #include "../src/clock/S32Mxx/clock_S32Mxx.h" 35 | #elif (defined(MPC5777C_SERIES)) 36 | /* MPC5777C Clock System Level API header file */ 37 | #include "../src/clock/MPC5777C/clock_MPC5777C.c" 38 | #elif (defined(MPC574x_SERIES) || defined(S32R_SERIES)) 39 | /* MPC574x Clock System Level API header file */ 40 | #include "../src/clock/MPC57xx/clock_MPC57xx.h" 41 | #elif (defined(S32S247_SERIES)) 42 | /* S32S247 Clock System Level API header file */ 43 | #include "../src/clock/S32Sxx/clock_S32Sxx.h" 44 | #elif (defined(SJA1110_SERIES)) 45 | /* SJA1110 Clock System Level API header file */ 46 | #include "../src/clock/SJA1110x/clock_SJA1110x.h" 47 | #elif (defined(S32V234_SERIES)) 48 | /* S32Vxx Clock System Level API header file */ 49 | #include "../src/clock/S32Vxx/clock_S32Vxx.h" 50 | #else 51 | #error "No valid CPU defined!" 52 | #endif 53 | 54 | /*! 55 | * @file clock.h 56 | */ 57 | 58 | /*! @addtogroup clock*/ 59 | /*! @{*/ 60 | 61 | /******************************************************************************* 62 | * Definitions 63 | ******************************************************************************/ 64 | 65 | 66 | #if defined(__cplusplus) 67 | extern "C" { 68 | #endif /* __cplusplus*/ 69 | 70 | /******************************************************************************* 71 | * API 72 | ******************************************************************************/ 73 | 74 | /*! 75 | * @name Dynamic clock setting 76 | * @{ 77 | */ 78 | 79 | /******************************************************************************* 80 | * API 81 | ******************************************************************************/ 82 | 83 | /*! 84 | * @brief Gets the clock frequency for a specific clock name. 85 | * 86 | * This function checks the current clock configurations and then calculates 87 | * the clock frequency for a specific clock name defined in clock_names_t. 88 | * Clock modules must be properly configured before using this function. 89 | * See features.h for supported clock names for different chip families. 90 | * The returned value is in Hertz. If it cannot find the clock name 91 | * or the name is not supported for a specific chip family, it returns an 92 | * STATUS_UNSUPPORTED. If frequency is required for a peripheral and the 93 | * module is not clocked, then STATUS_MCU_GATED_OFF status is returned. 94 | * Frequency is returned if a valid address is provided. If frequency is 95 | * required for a peripheral that doesn't support protocol clock, the zero 96 | * value is provided. 97 | * 98 | * @param[in] clockName Clock names defined in clock_names_t 99 | * @param[out] frequency Returned clock frequency value in Hertz 100 | * @return status Error code defined in status_t 101 | */ 102 | status_t CLOCK_DRV_GetFreq(clock_names_t clockName, 103 | uint32_t *frequency); 104 | 105 | 106 | /*! 107 | * @brief Set clock configuration according to pre-defined structure. 108 | * 109 | * This function sets system to target clock configuration; It sets the 110 | * clock modules registers for clock mode change. 111 | * 112 | * @param[in] config Pointer to configuration structure. 113 | * 114 | * @return Error code. 115 | * 116 | * @note If external clock is used in the target mode, please make sure it is 117 | * enabled, for example, if the external oscillator is used, please setup correctly. 118 | * 119 | * @note If the configuration structure is NULL, the function will set a default 120 | * configuration for clock. 121 | */ 122 | status_t CLOCK_DRV_Init(clock_user_config_t const * config); 123 | 124 | /*! @} */ 125 | 126 | 127 | #if defined(__cplusplus) 128 | } 129 | #endif /* __cplusplus*/ 130 | 131 | /*! @}*/ 132 | 133 | #endif /* CLOCK_H */ 134 | /******************************************************************************* 135 | * EOF 136 | ******************************************************************************/ 137 | 138 | -------------------------------------------------------------------------------- /SDK/platform/drivers/inc/clock_manager.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc. 3 | * Copyright 2016-2018 NXP 4 | * All rights reserved. 5 | * 6 | * THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR 7 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 8 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 9 | * IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 10 | * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 11 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 12 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 13 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 14 | * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 15 | * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 16 | * THE POSSIBILITY OF SUCH DAMAGE. 17 | */ 18 | #if !defined(CLOCK_MANAGER_H) 19 | #define CLOCK_MANAGER_H 20 | #include "clock.h" 21 | /*! 22 | * @file clock_manager.h 23 | * 24 | * @page misra_violations MISRA-C:2012 violations 25 | * 26 | * @section [global] 27 | * Violates MISRA 2012 Advisory Rule 2.5, Global macro not referenced. 28 | * This header file is included by application only. It was created 29 | * for backward compatibility reasons. 30 | */ 31 | #endif /* CLOCK_MANAGER_H */ 32 | /******************************************************************************* 33 | * EOF 34 | ******************************************************************************/ 35 | -------------------------------------------------------------------------------- /SDK/platform/drivers/src/clock/S32K1xx/pcc_hw_access.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc. 3 | * Copyright 2016 NXP 4 | * All rights reserved. 5 | * 6 | * THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR 7 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 8 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 9 | * IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 10 | * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 11 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 12 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 13 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 14 | * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 15 | * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 16 | * THE POSSIBILITY OF SUCH DAMAGE. 17 | */ 18 | 19 | #if !defined(PCC_HW_ACCESS_H) 20 | #define PCC_HW_ACCESS_H 21 | 22 | #include "device_registers.h" 23 | #include 24 | #include 25 | 26 | /*! 27 | * @file pcc_hw_access.h 28 | * 29 | * @page misra_violations MISRA-C:2012 violations 30 | * 31 | */ 32 | 33 | /*! 34 | * @ingroup pcc_hw_access 35 | * @defgroup pcc_hw_access 36 | * @{ 37 | */ 38 | 39 | 40 | /*! @brief Clock name mappings 41 | * Constant array storing the mappings between clock names and peripheral clock control indexes. 42 | * If there is no peripheral clock control index for a clock name, then the corresponding value is 43 | * PCC_INVALID_INDEX. 44 | */ 45 | extern const uint16_t clockNameMappings[CLOCK_NAME_COUNT]; 46 | 47 | #if defined(__cplusplus) 48 | extern "C" { 49 | #endif /* __cplusplus*/ 50 | 51 | 52 | /*! 53 | * @brief Sets SOSC control register 54 | * 55 | * @param[in] base pcc base pointer 56 | * @param[in] monitorMode clock monitor enablement 57 | * @param[in] clockGate control register can be written or not 58 | */ 59 | static inline void PCC_SetPeripheralClockControl(PCC_Type* base, clock_names_t clockName, bool clockGate, uint32_t clockSource, uint32_t divider, uint32_t multiplier) 60 | { 61 | /* Configure the peripheral clock source, the fractional clock divider and the clock gate */ 62 | uint32_t value = PCC_PCCn_PCS(clockSource) | 63 | PCC_PCCn_FRAC(multiplier) | 64 | PCC_PCCn_PCD(divider) | 65 | PCC_PCCn_CGC(clockGate ? 1UL : 0UL ); 66 | 67 | base->PCCn[clockNameMappings[clockName]] = value; 68 | } 69 | 70 | /*! 71 | * @brief Enables/disables the clock for a given peripheral. 72 | * For example, to enable the ADC0 clock, use like this: 73 | * @code 74 | * PCC_SetClockMode(PCC, PCC_ADC0_CLOCK, true); 75 | * @endcode 76 | * 77 | * @param[in] base pcc base pointer 78 | * @param[in] clockName is the name of the peripheral clock 79 | * must be one of the following values (see the clock_names_t type from S32K144_clock_names.h) 80 | * PCC_DMA0_CLOCK 81 | * PCC_MPU0_CLOCK 82 | * ... 83 | * PCC_LPUART3_CLOCK 84 | * @param[in] isClockEnabled is the value of the command that enables/disables the clock 85 | */ 86 | static inline void PCC_SetClockMode(PCC_Type* const base, 87 | const clock_names_t clockName, 88 | const bool isClockEnabled) 89 | { 90 | if (isClockEnabled) 91 | { 92 | base->PCCn[clockNameMappings[clockName]] |= PCC_PCCn_CGC(1UL); 93 | } 94 | else 95 | { 96 | base->PCCn[clockNameMappings[clockName]] &= (uint32_t)(~(PCC_PCCn_CGC_MASK)); 97 | } 98 | } 99 | 100 | 101 | 102 | /*! 103 | * @brief Gets the clock gate control mode. 104 | * 105 | * @param[in] base pcc base pointer 106 | * @param[in] clockName is the name of the peripheral clock 107 | * must be one of the following values (see the clock_names_t type from S32K144_clock_names.h) 108 | * PCC_DMA0_CLOCK 109 | * PCC_MPU0_CLOCK 110 | * ... 111 | * PCC_LPUART3_CLOCK 112 | * @return the clock gate control mode 113 | * - false : Clock is disabled 114 | * - true : Clock is enabled 115 | */ 116 | static inline bool PCC_GetClockMode(const PCC_Type* const base, 117 | const clock_names_t clockName) 118 | { 119 | uint32_t regValue = (uint32_t)base->PCCn[clockNameMappings[clockName]]; 120 | regValue = (regValue & PCC_PCCn_CGC_MASK) >> PCC_PCCn_CGC_SHIFT; 121 | return (regValue == 0U) ? false : true; 122 | } 123 | 124 | /*! 125 | * @brief Gets the selection of a clock source for a specific peripheral 126 | * 127 | * @param[in] base pcc base pointer 128 | * @param[in] clockName is the name of the peripheral clock 129 | * must be one of the following values (see the clock_names_t type from S32K144_clock_names.h) 130 | * PCC_DMA0_CLOCK 131 | * PCC_MPU0_CLOCK 132 | * ... 133 | * PCC_LPUART3_CLOCK 134 | * @return the clock source 135 | */ 136 | static inline uint32_t PCC_GetClockSourceSel(const PCC_Type* const base, 137 | const clock_names_t clockName) 138 | { 139 | return ((base->PCCn[clockNameMappings[clockName]] & PCC_PCCn_PCS_MASK) >> PCC_PCCn_PCS_SHIFT); 140 | } 141 | 142 | /*! 143 | * @brief Gets the selection of the fractional value for a specific peripheral 144 | * 145 | * @param[in] base pcc base pointer 146 | * @param[in] clockName is the name of the peripheral clock 147 | * must be one of the following values (see the clock_names_t type from S32K144_clock_names.h) 148 | * PCC_DMA0_CLOCK 149 | * PCC_MPU0_CLOCK 150 | * ... 151 | * PCC_LPUART3_CLOCK 152 | * @return the fractional value 153 | * - PCC_MULTPCCnLY_BY_ONE : Fractional value is zero 154 | * - PCC_MULTPCCnLY_BY_TWO : Fractional value is one 155 | */ 156 | static inline uint32_t PCC_GetFracValueSel(const PCC_Type* const base, 157 | const clock_names_t clockName) 158 | { 159 | return ((base->PCCn[clockNameMappings[clockName]] & PCC_PCCn_FRAC_MASK) >> PCC_PCCn_FRAC_SHIFT); 160 | } 161 | 162 | /*! 163 | * @brief Gets the selection of the divider value for a specific peripheral 164 | * 165 | * @param[in] base pcc base pointer 166 | * @param[in] clockName is the name of the peripheral clock 167 | * must be one of the following values (see the clock_names_t type from S32K144_clock_names.h) 168 | * PCC_DMA0_CLOCK 169 | * PCC_MPU0_CLOCK 170 | * ... 171 | * PCC_LPUART3_CLOCK 172 | * @return the divider value 173 | * - PCC_DIVIDE_BY_ONE : Divide by 1 174 | * - PCC_DIVIDE_BY_TWO : Divide by 2 175 | * - PCC_DIVIDE_BY_THREE : Divide by 3 176 | * - PCC_DIVIDE_BY_FOUR : Divide by 4 177 | * - PCC_DIVIDE_BY_FIVE : Divide by 5 178 | * - PCC_DIVIDE_BY_SIX : Divide by 6 179 | * - PCC_DIVIDE_BY_SEVEN : Divide by 7 180 | * - PCC_DIVIDE_BY_EIGTH : Divide by 8 181 | */ 182 | static inline uint32_t PCC_GetDividerSel(const PCC_Type* const base, 183 | const clock_names_t clockName) 184 | { 185 | return ((base->PCCn[clockNameMappings[clockName]] & PCC_PCCn_PCD_MASK) >> PCC_PCCn_PCD_SHIFT); 186 | } 187 | 188 | 189 | 190 | 191 | 192 | #if defined(__cplusplus) 193 | } 194 | #endif /* __cplusplus*/ 195 | 196 | 197 | /*! @}*/ 198 | 199 | #endif /* PCC_HW_ACCESS_H */ 200 | /******************************************************************************* 201 | * EOF 202 | ******************************************************************************/ 203 | 204 | -------------------------------------------------------------------------------- /SDK/platform/drivers/src/clock/S32K1xx/pmc_hw_access.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc. 3 | * Copyright 2016 NXP 4 | * All rights reserved. 5 | * 6 | * THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR 7 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 8 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 9 | * IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 10 | * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 11 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 12 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 13 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 14 | * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 15 | * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 16 | * THE POSSIBILITY OF SUCH DAMAGE. 17 | */ 18 | 19 | #if !defined(PMC_HW_ACCESS_H) 20 | #define PMC_HW_ACCESS_H 21 | 22 | #include "device_registers.h" 23 | #include 24 | #include 25 | 26 | /*! 27 | * @file pmc_hw_access.h 28 | * 29 | * @page misra_violations MISRA-C:2012 violations 30 | * 31 | */ 32 | 33 | /*! 34 | * @ingroup pmc_hw_access 35 | * @defgroup pmc_hw_access 36 | * @{ 37 | */ 38 | 39 | 40 | #if defined(__cplusplus) 41 | extern "C" { 42 | #endif /* __cplusplus*/ 43 | 44 | 45 | /*! 46 | * @brief Enables/Disables the Low Power Oscillator. 47 | * 48 | * This function enables/disables the Low Power Oscillator. 49 | * 50 | * @param[in] baseAddr Base address for current PMC instance. 51 | * @param[in] enable enable/disable the Low Power Oscillator. 52 | */ 53 | static inline void PMC_SetLpoMode(PMC_Type* const baseAddr, const bool enable) 54 | { 55 | uint8_t regValue = baseAddr->REGSC; 56 | regValue &= (uint8_t)(~(PMC_REGSC_LPODIS_MASK)); 57 | regValue |= (uint8_t)PMC_REGSC_LPODIS(enable?0U:1U); 58 | baseAddr->REGSC = regValue; 59 | } 60 | 61 | /*! 62 | * @brief Gets the Low Power Oscillator status. 63 | * 64 | * This function gets the Low Power Oscillator status. 65 | * 66 | * @param[in] baseAddr Base address for current PMC instance. 67 | * @return value LPO status 68 | * false - LPO is disabled 69 | * true - LPO is enabled 70 | */ 71 | static inline bool PMC_GetLpoMode(const PMC_Type * const baseAddr) 72 | { 73 | uint8_t regValue = baseAddr->REGSC; 74 | regValue = (uint8_t)((regValue & PMC_REGSC_LPODIS_MASK) >> PMC_REGSC_LPODIS_SHIFT); 75 | return (regValue == 0U) ? true : false; 76 | } 77 | 78 | 79 | /*! 80 | * @brief Low Power Oscillator Trimming Value 81 | * 82 | * This function sets the trimming value for the low power oscillator 83 | * 84 | * @param[in] baseAddr Base address for current PMC instance. 85 | * @param[in] value Trimming value 86 | */ 87 | static inline void PMC_SetLpoTrimValue(PMC_Type* const baseAddr, const int8_t decimalValue) 88 | { 89 | int8_t decValue = decimalValue; 90 | uint8_t lpotrim, trimval, regValue; 91 | 92 | if (decValue < 0) 93 | { 94 | lpotrim = ((uint8_t)1U) << (PMC_LPOTRIM_LPOTRIM_WIDTH); 95 | decValue = (int8_t)(decValue + (int8_t)(lpotrim)); 96 | } 97 | trimval = (uint8_t)decValue; 98 | 99 | DEV_ASSERT(trimval <= (1U << PMC_LPOTRIM_LPOTRIM_WIDTH)); 100 | 101 | regValue = baseAddr->LPOTRIM; 102 | regValue &= (uint8_t)(~(PMC_LPOTRIM_LPOTRIM_MASK)); 103 | regValue |= (uint8_t)PMC_LPOTRIM_LPOTRIM(trimval); 104 | baseAddr->LPOTRIM = regValue; 105 | } 106 | 107 | 108 | #if defined(__cplusplus) 109 | } 110 | #endif /* __cplusplus*/ 111 | 112 | 113 | /*! @}*/ 114 | 115 | #endif /* PMC_HW_ACCESS_H */ 116 | /******************************************************************************* 117 | * EOF 118 | ******************************************************************************/ 119 | 120 | -------------------------------------------------------------------------------- /SDK/platform/drivers/src/clock/S32K1xx/smc_hw_access.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc. 3 | * Copyright 2016 NXP 4 | * All rights reserved. 5 | * 6 | * THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR 7 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 8 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 9 | * IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 10 | * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 11 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 12 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 13 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 14 | * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 15 | * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 16 | * THE POSSIBILITY OF SUCH DAMAGE. 17 | */ 18 | 19 | #if !defined(SMC_HW_ACCESS_H) 20 | #define SMC_HW_ACCESS_H 21 | 22 | #include "device_registers.h" 23 | #include 24 | #include 25 | 26 | /*! 27 | * @file smc_hw_access.h 28 | * 29 | * @page misra_violations MISRA-C:2012 violations 30 | * 31 | */ 32 | 33 | /*! 34 | * @ingroup smc_hw_access 35 | * @defgroup smc_hw_access 36 | * @{ 37 | */ 38 | 39 | 40 | #if defined(__cplusplus) 41 | extern "C" { 42 | #endif /* __cplusplus*/ 43 | 44 | 45 | /*! 46 | * @brief Gets the current running power mode. 47 | * 48 | * This function returns the current running power mode. 49 | * 50 | * @param[in] baseAddr Base address for current SMC instance. 51 | * @return stat Current power mode stat 52 | */ 53 | static inline uint32_t SMC_GetCurrentRunningMode(const SMC_Type* const baseAddr) 54 | { 55 | return (baseAddr->PMSTAT & SMC_PMSTAT_PMSTAT_MASK) >> SMC_PMSTAT_PMSTAT_SHIFT; 56 | } 57 | 58 | 59 | #if defined(__cplusplus) 60 | } 61 | #endif /* __cplusplus*/ 62 | 63 | 64 | /*! @}*/ 65 | 66 | #endif /* SMC_HW_ACCESS_H */ 67 | /******************************************************************************* 68 | * EOF 69 | ******************************************************************************/ 70 | 71 | -------------------------------------------------------------------------------- /SDK/platform/drivers/src/edma/edma_irq.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc. 3 | * Copyright 2016 - 2018 NXP 4 | * All rights reserved. 5 | * 6 | * THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR 7 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 8 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 9 | * IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 10 | * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 11 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 12 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 13 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 14 | * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 15 | * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 16 | * THE POSSIBILITY OF SUCH DAMAGE. 17 | */ 18 | 19 | /*! 20 | * @file edma_irq.h 21 | */ 22 | 23 | #include "edma_hw_access.h" 24 | 25 | /*! @brief DMA channel interrupt handler, implemented in driver c file. */ 26 | void EDMA_DRV_IRQHandler(uint8_t virtualChannel); 27 | #ifdef FEATURE_DMA_HAS_ERROR_IRQ 28 | /*! @brief DMA error interrupt handler, implemented in driver c file. */ 29 | void EDMA_DRV_ErrorIRQHandler(uint8_t virtualChannel); 30 | #endif 31 | 32 | /******************************************************************************* 33 | * EOF 34 | ******************************************************************************/ 35 | -------------------------------------------------------------------------------- /SDK/platform/drivers/src/lptmr/lptmr_hw_access.c: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright 2017 NXP 3 | * All rights reserved. 4 | * 5 | * THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR 6 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 7 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 8 | * IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 9 | * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 10 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 11 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 12 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 13 | * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 14 | * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 15 | * THE POSSIBILITY OF SUCH DAMAGE. 16 | */ 17 | 18 | /*! 19 | * @file lptmr_hw_access.c 20 | * 21 | * @page misra_violations MISRA-C:2012 violations 22 | * 23 | * @section [global] 24 | * Violates MISRA 2012 Advisory Rule 8.7, External could be made static. 25 | * Function is defined for usage by application code. 26 | * 27 | */ 28 | 29 | #include "lptmr_hw_access.h" 30 | 31 | /******************************************************************************* 32 | * Code 33 | ******************************************************************************/ 34 | 35 | /*FUNCTION********************************************************************** 36 | * 37 | * Function Name : LPTMR_Init 38 | * Description : This function configures all registers of the LPTMR instance to reset value. 39 | * 40 | *END**************************************************************************/ 41 | void LPTMR_Init(LPTMR_Type* const base) 42 | { 43 | DEV_ASSERT(base != NULL); 44 | 45 | /* First, disable the module so we can write the registers */ 46 | uint32_t tmp = base->CSR; 47 | tmp &= ~(LPTMR_CSR_TEN_MASK | LPTMR_CSR_TCF_MASK); 48 | tmp |= LPTMR_CSR_TEN(0u); 49 | base->CSR = tmp; 50 | 51 | base->CSR = LPTMR_CSR_TEN(0u) | \ 52 | LPTMR_CSR_TMS(0u) | \ 53 | LPTMR_CSR_TFC(0u) | \ 54 | LPTMR_CSR_TPP(0u) | \ 55 | LPTMR_CSR_TPS(0u) | \ 56 | LPTMR_CSR_TIE(0u) | \ 57 | LPTMR_CSR_TCF(0u) | \ 58 | LPTMR_CSR_TDRE(0u); 59 | 60 | base->PSR = LPTMR_PSR_PCS(0u) | \ 61 | LPTMR_PSR_PBYP(0u) | \ 62 | LPTMR_PSR_PRESCALE(0u); 63 | 64 | base->CMR = LPTMR_CMR_COMPARE(0u); 65 | } 66 | /******************************************************************************* 67 | * EOF 68 | ******************************************************************************/ 69 | -------------------------------------------------------------------------------- /SDK/platform/drivers/src/lpuart/lpuart_irq.c: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc. 3 | * Copyright 2016-2017 NXP 4 | * All rights reserved. 5 | * 6 | * THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR 7 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 8 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 9 | * IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 10 | * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 11 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 12 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 13 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 14 | * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 15 | * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 16 | * THE POSSIBILITY OF SUCH DAMAGE. 17 | */ 18 | 19 | /*! 20 | * @file lpuart_irq.c 21 | * 22 | * @page misra_violations MISRA-C:2012 violations 23 | * 24 | * @section [global] 25 | * Violates MISRA 2012 Advisory Rule 8.7, Function not defined with external linkage. 26 | * The functions are not defined static because they are referenced in .s startup files. 27 | * 28 | * @section [global] 29 | * Violates MISRA 2012 Advisory Rule 8.9, Could define variable at block scope 30 | * The variable is used in driver c file, so it must remain global. 31 | */ 32 | 33 | #include "lpuart_irq.h" 34 | 35 | /******************************************************************************* 36 | * Code 37 | ******************************************************************************/ 38 | 39 | #if (LPUART_INSTANCE_COUNT > 0U) 40 | /* Implementation of LPUART0 handler named in startup code. */ 41 | void LPUART0_IrqHandler(void) 42 | { 43 | LPUART_DRV_IRQHandler(0); 44 | } 45 | #endif 46 | 47 | #if (LPUART_INSTANCE_COUNT > 1U) 48 | /* Implementation of LPUART1 handler named in startup code. */ 49 | void LPUART1_IrqHandler(void) 50 | { 51 | LPUART_DRV_IRQHandler(1); 52 | } 53 | #endif 54 | 55 | #if (LPUART_INSTANCE_COUNT > 2U) 56 | /* Implementation of LPUART2 handler named in startup code. */ 57 | void LPUART2_IrqHandler(void) 58 | { 59 | LPUART_DRV_IRQHandler(2); 60 | } 61 | #endif 62 | 63 | #if (LPUART_INSTANCE_COUNT > 3U) 64 | /* Implementation of LPUART3 handler named in startup code. */ 65 | void LPUART3_IrqHandler(void) 66 | { 67 | LPUART_DRV_IRQHandler(3); 68 | } 69 | #endif 70 | 71 | /* Array storing references to LPUART irq handlers */ 72 | isr_t g_lpuartIsr[LPUART_INSTANCE_COUNT] = 73 | { 74 | #if (LPUART_INSTANCE_COUNT > 0U) 75 | LPUART0_IrqHandler, 76 | #endif 77 | #if (LPUART_INSTANCE_COUNT > 1U) 78 | LPUART1_IrqHandler, 79 | #endif 80 | #if (LPUART_INSTANCE_COUNT > 2U) 81 | LPUART2_IrqHandler, 82 | #endif 83 | #if (LPUART_INSTANCE_COUNT > 3U) 84 | LPUART3_IrqHandler, 85 | #endif 86 | }; 87 | 88 | /******************************************************************************* 89 | * EOF 90 | ******************************************************************************/ 91 | -------------------------------------------------------------------------------- /SDK/platform/drivers/src/lpuart/lpuart_irq.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc. 3 | * Copyright 2016-2017 NXP 4 | * All rights reserved. 5 | * 6 | * THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR 7 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 8 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 9 | * IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 10 | * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 11 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 12 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 13 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 14 | * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 15 | * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 16 | * THE POSSIBILITY OF SUCH DAMAGE. 17 | */ 18 | 19 | #ifndef LPUART_IRQ_H__ 20 | #define LPUART_IRQ_H__ 21 | 22 | #include "device_registers.h" 23 | #include "interrupt_manager.h" 24 | 25 | /******************************************************************************* 26 | * Prototypes 27 | ******************************************************************************/ 28 | void LPUART_DRV_IRQHandler(uint32_t instance); 29 | 30 | /******************************************************************************* 31 | * Default interrupt handlers signatures 32 | ******************************************************************************/ 33 | 34 | #if (LPUART_INSTANCE_COUNT > 0U) 35 | /*! @brief LPUART0 interrupt handler. */ 36 | void LPUART0_IrqHandler(void); 37 | #endif 38 | 39 | #if (LPUART_INSTANCE_COUNT > 1U) 40 | /*! @brief LPUART1 interrupt handler. */ 41 | void LPUART1_IrqHandler(void); 42 | #endif 43 | 44 | #if (LPUART_INSTANCE_COUNT > 2U) 45 | /*! @brief LPUART2 interrupt handler. */ 46 | void LPUART2_IrqHandler(void); 47 | #endif 48 | 49 | #if (LPUART_INSTANCE_COUNT > 3U) 50 | /*! @brief LPUART3 interrupt handler. */ 51 | void LPUART3_IrqHandler(void); 52 | #endif 53 | 54 | /*! Array storing references to LPUART irq handlers */ 55 | extern isr_t g_lpuartIsr[LPUART_INSTANCE_COUNT]; 56 | 57 | #endif /* LPUART_IRQ_H__ */ 58 | /******************************************************************************* 59 | * EOF 60 | ******************************************************************************/ 61 | -------------------------------------------------------------------------------- /SDK/platform/drivers/src/power/S32K1xx/power_rcm_hw_access.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc. 3 | * Copyright 2016-2018 NXP 4 | * All rights reserved. 5 | * 6 | * THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR 7 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 8 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 9 | * IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 10 | * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 11 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 12 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 13 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 14 | * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 15 | * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 16 | * THE POSSIBILITY OF SUCH DAMAGE. 17 | */ 18 | 19 | #ifndef POWER_RCM_HW_ACCESS_H 20 | #define POWER_RCM_HW_ACCESS_H 21 | 22 | #include "device_registers.h" 23 | #include "power_manager_S32K1xx.h" 24 | 25 | /*! @file power_rcm_hw_access.h */ 26 | 27 | /*! 28 | * @ingroup power_rcm_hw_access 29 | * @defgroup power_rcm_hw_access 30 | * @{ 31 | */ 32 | 33 | /******************************************************************************* 34 | * Definitions 35 | ******************************************************************************/ 36 | 37 | /******************************************************************************* 38 | * API 39 | ******************************************************************************/ 40 | #if defined(__cplusplus) 41 | extern "C" { 42 | #endif /* __cplusplus*/ 43 | 44 | /*! @name Reset Control Module APIs*/ 45 | /*@{*/ 46 | 47 | static inline bool RCM_GetSrcStatusCmd(const RCM_Type * const baseAddr, 48 | const rcm_source_names_t srcName) 49 | { 50 | bool retValue; 51 | uint32_t regValue = (uint32_t)baseAddr->SRS; 52 | 53 | DEV_ASSERT(srcName < RCM_SRC_NAME_MAX); 54 | 55 | switch (srcName) 56 | { 57 | case RCM_LOW_VOLT_DETECT: /* low voltage detect reset */ 58 | regValue = (regValue & RCM_SRS_LVD_MASK) >> RCM_SRS_LVD_SHIFT; 59 | break; 60 | case RCM_LOSS_OF_CLK: /* loss of clock reset */ 61 | regValue = (regValue & RCM_SRS_LOC_MASK) >> RCM_SRS_LOC_SHIFT; 62 | break; 63 | case RCM_LOSS_OF_LOCK: /* loss of lock reset */ 64 | regValue = (regValue & RCM_SRS_LOL_MASK) >> RCM_SRS_LOL_SHIFT; 65 | break; 66 | #if FEATURE_RCM_HAS_CMU_LOSS_OF_CLOCK /*!< CMU Loss of lock reset */ 67 | case RCM_CMU_LOC: 68 | regValue = (regValue & RCM_SRS_CMU_LOC_MASK) >> RCM_SRS_CMU_LOC_SHIFT; 69 | break; 70 | #endif 71 | case RCM_WATCH_DOG: /* watch dog reset */ 72 | regValue = (regValue & RCM_SRS_WDOG_MASK) >> RCM_SRS_WDOG_SHIFT; 73 | break; 74 | case RCM_EXTERNAL_PIN: /* external pin reset */ 75 | regValue = (regValue & RCM_SRS_PIN_MASK) >> RCM_SRS_PIN_SHIFT; 76 | break; 77 | case RCM_POWER_ON: /* power on reset */ 78 | regValue = (regValue & RCM_SRS_POR_MASK) >> RCM_SRS_POR_SHIFT; 79 | break; 80 | case RCM_SJTAG: /* JTAG generated reset */ 81 | regValue = (regValue & RCM_SSRS_SJTAG_MASK) >> RCM_SSRS_SJTAG_SHIFT; 82 | break; 83 | case RCM_CORE_LOCKUP: /* core lockup reset */ 84 | regValue = (regValue & RCM_SRS_LOCKUP_MASK) >> RCM_SRS_LOCKUP_SHIFT; 85 | break; 86 | case RCM_SOFTWARE: /* software reset */ 87 | regValue = (regValue & RCM_SRS_SW_MASK) >> RCM_SRS_SW_SHIFT; 88 | break; 89 | case RCM_SMDM_AP: /* MDM-AP system reset */ 90 | regValue = (regValue & RCM_SSRS_SMDM_AP_MASK) >> RCM_SSRS_SMDM_AP_SHIFT; 91 | break; 92 | case RCM_STOP_MODE_ACK_ERR: /* stop mode ack error reset */ 93 | regValue = (regValue & RCM_SRS_SACKERR_MASK) >> RCM_SRS_SACKERR_SHIFT; 94 | break; 95 | default: 96 | /* invalid command */ 97 | regValue = 0U; 98 | break; 99 | } 100 | 101 | retValue = (regValue == 0UL) ? false : true; 102 | 103 | return retValue; 104 | } 105 | 106 | /*@}*/ 107 | 108 | #if defined(__cplusplus) 109 | } 110 | #endif /* __cplusplus*/ 111 | 112 | /*! @}*/ 113 | 114 | #endif /* POWER_RCM_HW_ACCESS_H */ 115 | /******************************************************************************* 116 | * EOF 117 | ******************************************************************************/ 118 | -------------------------------------------------------------------------------- /SDK/platform/drivers/src/power/S32K1xx/power_scg_hw_access.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright 2018 NXP 3 | * All rights reserved. 4 | * 5 | * THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR 6 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 7 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 8 | * IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 9 | * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 10 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 11 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 12 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 13 | * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 14 | * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 15 | * THE POSSIBILITY OF SUCH DAMAGE. 16 | */ 17 | 18 | #ifndef POWER_SCG_HW_ACCESS_H 19 | #define POWER_SCG_HW_ACCESS_H 20 | 21 | #include "device_registers.h" 22 | 23 | /*! 24 | * @file power_scg_hw_access.h 25 | * 26 | * @page misra_violations MISRA-C:2012 violations 27 | * 28 | * @section [global] 29 | * Violates MISRA 2012 Required Rule 11.6, A cast shall not be performed 30 | * between pointer to void and an arithmetic type. 31 | * The address of hardware modules is provided as integer so 32 | * it needs to be cast to pointer. 33 | * 34 | * @section [global] 35 | * Violates MISRA 2012 Advisory Rule 11.4, A conversion should not be performed 36 | * between a pointer to object and an integer type. 37 | * The address of hardware modules is provided as integer so 38 | * a conversion between a pointer and an integer has to be performed 39 | */ 40 | 41 | /*! 42 | * power_scg_hw_access 43 | * @{ 44 | */ 45 | 46 | /******************************************************************************* 47 | * API 48 | ******************************************************************************/ 49 | 50 | #if defined(__cplusplus) 51 | extern "C" { 52 | #endif /* __cplusplus*/ 53 | 54 | #if FEATURE_HAS_SPLL_CLK 55 | /*! 56 | * @brief Set the SPLL clock source was enabled or disabled 57 | * 58 | * This function sets SPLL clock source enable or disabled. 59 | * This one is used in the switching very low power mode sequence. 60 | * 61 | * @param[in] enable This variable select the SPLL available or not. 62 | */ 63 | static inline void SCG_SetEnableSPLL(bool enable) 64 | { 65 | uint32_t regValue = SCG->SPLLCSR; 66 | regValue &= ~SCG_SPLLCSR_SPLLEN_MASK; 67 | if (enable == true) 68 | { 69 | regValue |= SCG_SPLLCSR_SPLLEN(1U); 70 | } 71 | else 72 | { 73 | regValue |= SCG_SPLLCSR_SPLLEN(0U); 74 | } 75 | SCG->SPLLCSR = regValue; 76 | } 77 | 78 | /*! 79 | * @brief Get status of SPLL clock source was enabled or disabled 80 | * 81 | * This function gets SPLL clock source enable or disabled. 82 | * This one is used in the switching very low power mode sequence. 83 | * 84 | * @return true : SPLL enabled 85 | false : SPLL disable 86 | */ 87 | static inline bool SCG_GetEnableSPLL(void) 88 | { 89 | uint32_t regValue = SCG->SPLLCSR; 90 | regValue = (regValue & SCG_SPLLCSR_SPLLEN_MASK) >> SCG_SPLLCSR_SPLLEN_SHIFT; 91 | 92 | return (regValue == 0U) ? false : true; 93 | } 94 | 95 | /*! 96 | * @brief Check clock source in HSRUN mode 97 | * 98 | * This function checks SPLL as source in HSRUN mode. 99 | * This one is used in the switching very low power mode sequence. 100 | * 101 | * @return true : SPLL is clock source in HSRUN. 102 | false : SPLL is not clock source in HSRUN. 103 | */ 104 | static inline bool SCG_GetHsrunSelectSPLL(void) 105 | { 106 | uint32_t regValue = SCG->HCCR; 107 | regValue = (regValue & SCG_HCCR_SCS_MASK) >> SCG_HCCR_SCS_SHIFT; 108 | 109 | return (regValue == FEATURE_SCG_SPLL_VALUE) ? true : false; 110 | } 111 | 112 | #endif 113 | 114 | /*! 115 | * @brief Set the FIRC clock source was enabled or disabled 116 | * 117 | * This function sets FIRC clock source enable or disabled. 118 | * This one is used in the switching very low power mode sequence. 119 | * 120 | * @param[in] enable This variable select the FIRC available or not. 121 | */ 122 | static inline void SCG_SetEnableFIRC(bool enable) 123 | { 124 | uint32_t regValue = SCG->FIRCCSR; 125 | regValue &= ~SCG_FIRCCSR_FIRCEN_MASK; 126 | if (enable == true) 127 | { 128 | regValue |= SCG_FIRCCSR_FIRCEN(1U); 129 | } 130 | else 131 | { 132 | regValue |= SCG_FIRCCSR_FIRCEN(0U); 133 | } 134 | SCG->FIRCCSR = regValue; 135 | } 136 | 137 | /*! 138 | * @brief Get status of FIRC clock source was enabled or disabled 139 | * 140 | * This function gets FIRC clock source enable or disabled. 141 | * This one is used in the switching very low power mode sequence. 142 | * 143 | * @return true : FIRC enabled 144 | false : FIRC disable 145 | */ 146 | static inline bool SCG_GetEnableFIRC(void) 147 | { 148 | uint32_t regValue = SCG->FIRCCSR; 149 | regValue = (regValue & SCG_FIRCCSR_FIRCEN_MASK) >> SCG_FIRCCSR_FIRCEN_SHIFT; 150 | 151 | return (regValue == 0U) ? false : true; 152 | } 153 | 154 | /*! 155 | * @brief Set the SOSC clock source was enabled or disabled 156 | * 157 | * This function sets SOSC clock source enable or disabled. 158 | * This one is used in the switching very low power mode sequence. 159 | * 160 | * @param[in] enable This variable select the SOSC available or not. 161 | */ 162 | static inline void SCG_SetEnableSOSC(bool enable) 163 | { 164 | uint32_t regValue = SCG->SOSCCSR; 165 | regValue &= ~SCG_SOSCCSR_SOSCEN_MASK; 166 | if (enable == true) 167 | { 168 | regValue |= SCG_SOSCCSR_SOSCEN(1U); 169 | } 170 | else 171 | { 172 | regValue |= SCG_SOSCCSR_SOSCEN(0U); 173 | } 174 | SCG->SOSCCSR = regValue; 175 | } 176 | 177 | /*! 178 | * @brief Get status of SOSC clock source was enabled or disabled 179 | * 180 | * This function gets SOSC clock source enable or disabled. 181 | * This one is used in the switching very low power mode sequence. 182 | * 183 | * @return true : SOSC enabled 184 | false : SOSC disable 185 | */ 186 | static inline bool SCG_GetEnableSOSC(void) 187 | { 188 | uint32_t regValue = SCG->SOSCCSR; 189 | regValue = (regValue & SCG_SOSCCSR_SOSCEN_MASK) >> SCG_SOSCCSR_SOSCEN_SHIFT; 190 | 191 | return (regValue == 0U) ? false : true; 192 | } 193 | 194 | /*@}*/ 195 | 196 | #if defined(__cplusplus) 197 | } 198 | #endif /* __cplusplus*/ 199 | 200 | /*! @}*/ 201 | 202 | #endif /* POWER_SCG_HW_ACCESS_H */ 203 | /******************************************************************************* 204 | * EOF 205 | ******************************************************************************/ 206 | -------------------------------------------------------------------------------- /SDK/platform/drivers/src/wdog/wdog_hw_access.c: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2015, Freescale Semiconductor, Inc. 3 | * Copyright 2016-2018 NXP 4 | * All rights reserved. 5 | * 6 | * THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR 7 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 8 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 9 | * IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 10 | * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 11 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 12 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 13 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 14 | * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 15 | * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 16 | * THE POSSIBILITY OF SUCH DAMAGE. 17 | */ 18 | 19 | /*! 20 | * @file wdog_hw_access.c 21 | * 22 | * @page misra_violations MISRA-C:2012 violations 23 | * 24 | * @section [global] 25 | * Violates MISRA 2012 Advisory Rule 8.7, External could be made static. 26 | * The function is defined for use by application code. 27 | */ 28 | 29 | #include "wdog_hw_access.h" 30 | 31 | /******************************************************************************* 32 | * Code 33 | ******************************************************************************/ 34 | 35 | /*FUNCTION********************************************************************** 36 | * 37 | * Function Name : WDOG_Deinit 38 | * Description : De-init WDOG module. 39 | * 40 | *END**************************************************************************/ 41 | void WDOG_Deinit(WDOG_Type * const base) 42 | { 43 | /* Unlock WDOG register */ 44 | WDOG_UNLOCK(base); 45 | /* Disable WDOG, enables support for 32-bit refresh/unlock command, LPO clock source, 46 | allow updates and disable watchdog interrupts, window mode, wait/debug/stop mode */ 47 | base->CS = FEATURE_WDOG_CS_RESET_VALUE; 48 | /* Default timeout value */ 49 | base->TOVAL = FEATURE_WDOG_TO_RESET_VALUE; 50 | /* Clear window value */ 51 | base->WIN = FEATURE_WDOG_WIN_RESET_VALUE; 52 | 53 | /* Refresh counter value */ 54 | WDOG_Trigger(base); 55 | 56 | while (!WDOG_IsReconfigurationComplete(base)) 57 | { 58 | /* Wait until the reconfiguration successful */ 59 | } 60 | } 61 | 62 | /*FUNCTION********************************************************************** 63 | * 64 | * Function Name : WDOG_SetInt 65 | * Description : enable/disable the WDOG timeout interrupt 66 | * 67 | *END**************************************************************************/ 68 | void WDOG_SetInt(WDOG_Type * const base, 69 | bool enable) 70 | { 71 | /* Unlock WDOG register */ 72 | WDOG_UNLOCK(base); 73 | /*LDRA_NOANALYSIS*/ 74 | /* The comment LDRA_NOANALYSIS only use to run code coverage */ 75 | /* Enable/disable WDOG interrupt */ 76 | base->CS = (base->CS & ~WDOG_CS_INT_MASK) | WDOG_CS_INT(enable? 1UL : 0UL); 77 | /*LDRA_ANALYSIS*/ 78 | /* The comment LDRA_ANALYSIS only use to run code coverage */ 79 | 80 | while (!WDOG_IsReconfigurationComplete(base)) 81 | { 82 | /* Wait until the reconfiguration successful */ 83 | } 84 | } 85 | 86 | /*FUNCTION********************************************************************** 87 | * 88 | * Function Name : WDOG_Config 89 | * Description : Configures all WDOG registers. 90 | * 91 | *END**************************************************************************/ 92 | status_t WDOG_Config(WDOG_Type * const base, 93 | const wdog_user_config_t * wdogUserConfig) 94 | { 95 | status_t status = STATUS_SUCCESS; 96 | uint32_t cs = base->CS; 97 | bool tmp1 = WDOG_IsEnabled(base); 98 | bool tmp2 = WDOG_IsUpdateEnabled(base); 99 | 100 | INT_SYS_DisableIRQGlobal(); 101 | 102 | if ((tmp1 == false) && (tmp2 == true)) 103 | { 104 | /* Clear the bits used for configuration */ 105 | cs &= ~(WDOG_CS_WIN_MASK | WDOG_CS_PRES_MASK | WDOG_CS_CLK_MASK | WDOG_CS_INT_MASK | 106 | WDOG_CS_UPDATE_MASK | WDOG_CS_DBG_MASK | WDOG_CS_WAIT_MASK | WDOG_CS_STOP_MASK); 107 | /* Construct CS register new value */ 108 | cs |= WDOG_CS_WIN(wdogUserConfig->winEnable ? 1UL : 0UL); 109 | cs |= WDOG_CS_PRES(wdogUserConfig->prescalerEnable ? 1UL : 0UL); 110 | cs |= WDOG_CS_CLK(wdogUserConfig->clkSource); 111 | cs |= WDOG_CS_INT(wdogUserConfig->intEnable ? 1UL : 0UL); 112 | cs |= WDOG_CS_UPDATE(wdogUserConfig->updateEnable ? 1UL : 0UL); 113 | if (wdogUserConfig->opMode.debug) 114 | { 115 | cs |= WDOG_CS_DBG_MASK; 116 | } 117 | if (wdogUserConfig->opMode.wait) 118 | { 119 | cs |= WDOG_CS_WAIT_MASK; 120 | } 121 | if (wdogUserConfig->opMode.stop) 122 | { 123 | cs |= WDOG_CS_STOP_MASK; 124 | } 125 | /* Reset interrupt flags */ 126 | cs |= WDOG_CS_FLG_MASK; 127 | /* Enable WDOG in 32-bit mode */ 128 | cs |= WDOG_CS_EN_MASK | WDOG_CS_CMD32EN_MASK; 129 | 130 | WDOG_UNLOCK(base); 131 | /*LDRA_NOANALYSIS*/ 132 | /* The comment LDRA_NOANALYSIS only use to run code coverage */ 133 | while (!WDOG_IsUnlocked(base)) 134 | { 135 | /* Wait until registers are unlocked */ 136 | } 137 | 138 | base->CS = cs; 139 | base->TOVAL = wdogUserConfig->timeoutValue; 140 | if (wdogUserConfig->winEnable) 141 | { 142 | base->WIN = wdogUserConfig->windowValue; 143 | } 144 | /*LDRA_ANALYSIS*/ 145 | /* The comment LDRA_ANALYSIS only use to run code coverage */ 146 | 147 | while (WDOG_IsUnlocked(base)) 148 | { 149 | /* Wait until the unlock window closes */ 150 | } 151 | 152 | while (!WDOG_IsReconfigurationComplete(base)) 153 | { 154 | /* Wait until the reconfiguration successful */ 155 | } 156 | } 157 | else 158 | { 159 | status = STATUS_ERROR; 160 | } 161 | 162 | INT_SYS_EnableIRQGlobal(); 163 | 164 | return status; 165 | } 166 | 167 | /*FUNCTION********************************************************************** 168 | * 169 | * Function Name : WDOG_GetConfig 170 | * Description : Gets the current WDOG configuration. 171 | * 172 | *END**************************************************************************/ 173 | wdog_user_config_t WDOG_GetConfig(const WDOG_Type *base) 174 | { 175 | wdog_user_config_t config; 176 | uint32_t cs = base->CS; 177 | 178 | /* Construct CS register new value */ 179 | config.winEnable = ((cs & WDOG_CS_WIN_MASK) != 0U); 180 | config.prescalerEnable = ((cs & WDOG_CS_PRES_MASK) != 0U); 181 | config.intEnable = ((cs & WDOG_CS_INT_MASK) != 0U); 182 | config.updateEnable = ((cs & WDOG_CS_UPDATE_MASK) != 0U); 183 | config.opMode.debug = ((cs & WDOG_CS_DBG_MASK) != 0U); 184 | config.opMode.wait = ((cs & WDOG_CS_WAIT_MASK) != 0U); 185 | config.opMode.stop = ((cs & WDOG_CS_STOP_MASK) != 0U); 186 | config.timeoutValue = (uint16_t)base->TOVAL; 187 | config.windowValue = (uint16_t)base->WIN; 188 | 189 | switch((cs & WDOG_CS_CLK_MASK) >> WDOG_CS_CLK_SHIFT) 190 | { 191 | case 0U: 192 | config.clkSource = WDOG_BUS_CLOCK; 193 | break; 194 | case 1U: 195 | config.clkSource = WDOG_LPO_CLOCK; 196 | break; 197 | case 2U: 198 | config.clkSource = WDOG_SOSC_CLOCK; 199 | break; 200 | case 3U: 201 | config.clkSource = WDOG_SIRC_CLOCK; 202 | break; 203 | default: 204 | config.clkSource = WDOG_BUS_CLOCK; 205 | break; 206 | } 207 | 208 | return config; 209 | } 210 | 211 | /******************************************************************************* 212 | * EOF 213 | ******************************************************************************/ 214 | 215 | -------------------------------------------------------------------------------- /SDK/rtos/osif/osif.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2016, Freescale Semiconductor, Inc. 3 | * Copyright 2016-2018 NXP 4 | * All rights reserved. 5 | * 6 | * THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR 7 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 8 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 9 | * IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 10 | * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 11 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 12 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 13 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 14 | * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 15 | * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 16 | * THE POSSIBILITY OF SUCH DAMAGE. 17 | */ 18 | 19 | #ifndef OSIF_H 20 | #define OSIF_H 21 | 22 | #include 23 | 24 | /** 25 | * @page misra_violations MISRA-C:2012 violations 26 | * 27 | * @section [global] 28 | * Violates MISRA 2012 Advisory Rule 2.5, Global macro not referenced. 29 | * The macro defines a value that will be interpreted as an infinite timeout. 30 | * 31 | */ 32 | 33 | /*! @file */ 34 | 35 | /*! 36 | * @addtogroup osif 37 | * @{ 38 | */ 39 | 40 | /******************************************************************************* 41 | * Definitions 42 | ******************************************************************************/ 43 | 44 | /*! @cond DRIVER_INTERNAL_USE_ONLY */ 45 | 46 | #ifdef USING_OS_FREERTOS 47 | /* FreeRTOS implementation */ 48 | #include "FreeRTOS.h" 49 | #include "semphr.h" 50 | 51 | #if configSUPPORT_STATIC_ALLOCATION == 1 52 | typedef struct { 53 | SemaphoreHandle_t handle; 54 | StaticSemaphore_t buffer; 55 | } semaphore_t; 56 | 57 | typedef semaphore_t mutex_t; 58 | #else /* configSUPPORT_STATIC_ALLOCATION == 0, it's dynamic allocation */ 59 | /*! @brief Type for a mutex. */ 60 | typedef SemaphoreHandle_t mutex_t; 61 | /*! @brief Type for a semaphore. */ 62 | typedef SemaphoreHandle_t semaphore_t; 63 | #endif /* configSUPPORT_STATIC_ALLOCATION == 1 */ 64 | #else 65 | /* Bare-metal implementation */ 66 | /*! @brief Type for a mutex. */ 67 | typedef uint8_t mutex_t; 68 | /*! @brief Type for a semaphore. */ 69 | typedef volatile uint8_t semaphore_t; 70 | #endif /* ifdef USING_OS_FREERTOS */ 71 | 72 | /*! @endcond */ 73 | 74 | #define OSIF_WAIT_FOREVER 0xFFFFFFFFu 75 | 76 | #include "status.h" 77 | 78 | /******************************************************************************* 79 | * API 80 | ******************************************************************************/ 81 | 82 | #if defined (__cplusplus) 83 | extern "C" { 84 | #endif 85 | 86 | /*! 87 | * @brief Delays execution for a number of milliseconds. 88 | * 89 | * @param[in] delay Time delay in milliseconds. 90 | */ 91 | void OSIF_TimeDelay(const uint32_t delay); 92 | 93 | /*! 94 | * @brief Returns the number of miliseconds elapsed since starting the internal timer 95 | * or starting the scheduler. 96 | * 97 | * @return the number of miliseconds elapsed 98 | */ 99 | uint32_t OSIF_GetMilliseconds(void); 100 | 101 | /*! 102 | * @brief Waits for a mutex and locks it. 103 | * 104 | * @param[in] pMutex reference to the mutex object 105 | * @param[in] timeout time-out value in milliseconds 106 | * @return One of the possible status codes: 107 | * - STATUS_SUCCESS: mutex lock operation success 108 | * - STATUS_ERROR: mutex already owned by current thread 109 | * - STATUS_TIMEOUT: mutex lock operation timed out 110 | * 111 | */ 112 | status_t OSIF_MutexLock(const mutex_t * const pMutex, 113 | const uint32_t timeout); 114 | 115 | /*! 116 | * @brief Unlocks a previously locked mutex. 117 | * 118 | * @param[in] pMutex reference to the mutex object 119 | * @return One of the possible status codes: 120 | * - STATUS_SUCCESS: mutex unlock operation success 121 | * - STATUS_ERROR: mutex unlock failed 122 | */ 123 | status_t OSIF_MutexUnlock(const mutex_t * const pMutex); 124 | 125 | 126 | /*! 127 | * @brief Create an unlocked mutex. 128 | * 129 | * @param[in] pMutex reference to the mutex object 130 | * @return One of the possible status codes: 131 | * - STATUS_SUCCESS: mutex created 132 | * - STATUS_ERROR: mutex could not be created 133 | */ 134 | status_t OSIF_MutexCreate(mutex_t * const pMutex); 135 | 136 | /*! 137 | * @brief Destroys a previously created mutex. 138 | * 139 | * @param[in] pMutex reference to the mutex object 140 | * @return One of the possible status codes: 141 | * - STATUS_SUCCESS: mutex destroyed 142 | */ 143 | status_t OSIF_MutexDestroy(const mutex_t * const pMutex); 144 | 145 | 146 | /*! 147 | * @brief Decrement a semaphore with timeout. 148 | * 149 | * @param[in] pSem reference to the semaphore object 150 | * @param[in] timeout time-out value in milliseconds 151 | * @return One of the possible status codes: 152 | * - STATUS_SUCCESS: semaphore wait operation success 153 | * - STATUS_TIMEOUT: semaphore wait timed out 154 | */ 155 | status_t OSIF_SemaWait(semaphore_t * const pSem, 156 | const uint32_t timeout); 157 | 158 | 159 | /*! 160 | * @brief Increment a semaphore 161 | * 162 | * @param[in] pSem reference to the semaphore object 163 | * @return One of the possible status codes: 164 | * - STATUS_SUCCESS: semaphore post operation success 165 | * - STATUS_ERROR: semaphore could not be incremented 166 | */ 167 | status_t OSIF_SemaPost(semaphore_t * const pSem); 168 | 169 | 170 | /*! 171 | * @brief Creates a semaphore with a given value. 172 | * 173 | * @param[in] pSem reference to the semaphore object 174 | * @param[in] initValue initial value of the semaphore 175 | * @return One of the possible status codes: 176 | * - STATUS_SUCCESS: semaphore created 177 | * - STATUS_ERROR: semaphore could not be created 178 | */ 179 | status_t OSIF_SemaCreate(semaphore_t * const pSem, 180 | const uint8_t initValue); 181 | 182 | 183 | /*! 184 | * @brief Destroys a previously created semaphore. 185 | * 186 | * @param[in] pSem reference to the semaphore object 187 | * @return One of the possible status codes: 188 | * - STATUS_SUCCESS: semaphore destroyed 189 | */ 190 | status_t OSIF_SemaDestroy(const semaphore_t * const pSem); 191 | 192 | /*! @}*/ 193 | #if defined (__cplusplus) 194 | } 195 | #endif 196 | 197 | /*! @}*/ 198 | 199 | #endif /* OSIF_H */ 200 | /******************************************************************************* 201 | * EOF 202 | ******************************************************************************/ 203 | -------------------------------------------------------------------------------- /Sources/SEGGER_RTT/SEGGER_RTT_Syscalls_GCC.c: -------------------------------------------------------------------------------- 1 | /********************************************************************* 2 | * SEGGER Microcontroller GmbH * 3 | * The Embedded Experts * 4 | ********************************************************************** 5 | * * 6 | * (c) 1995 - 2021 SEGGER Microcontroller GmbH * 7 | * * 8 | * www.segger.com Support: support@segger.com * 9 | * * 10 | ********************************************************************** 11 | * * 12 | * SEGGER RTT * Real Time Transfer for embedded targets * 13 | * * 14 | ********************************************************************** 15 | * * 16 | * All rights reserved. * 17 | * * 18 | * SEGGER strongly recommends to not make any changes * 19 | * to or modify the source code of this software in order to stay * 20 | * compatible with the RTT protocol and J-Link. * 21 | * * 22 | * Redistribution and use in source and binary forms, with or * 23 | * without modification, are permitted provided that the following * 24 | * condition is met: * 25 | * * 26 | * o Redistributions of source code must retain the above copyright * 27 | * notice, this condition and the following disclaimer. * 28 | * * 29 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND * 30 | * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, * 31 | * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * 32 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * 33 | * DISCLAIMED. IN NO EVENT SHALL SEGGER Microcontroller BE LIABLE FOR * 34 | * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * 35 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT * 36 | * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * 37 | * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF * 38 | * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * 39 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE * 40 | * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH * 41 | * DAMAGE. * 42 | * * 43 | ********************************************************************** 44 | * * 45 | * RTT version: 7.20a * 46 | * * 47 | ********************************************************************** 48 | 49 | ---------------------------END-OF-HEADER------------------------------ 50 | File : SEGGER_RTT_Syscalls_GCC.c 51 | Purpose : Low-level functions for using printf() via RTT in GCC. 52 | To use RTT for printf output, include this file in your 53 | application. 54 | Revision: $Rev: 20755 $ 55 | ---------------------------------------------------------------------- 56 | */ 57 | #if (defined __GNUC__) && !(defined __SES_ARM) && !(defined __CROSSWORKS_ARM) && !(defined __ARMCC_VERSION) && !(defined __CC_ARM) 58 | 59 | #include // required for _write_r 60 | #include "SEGGER_RTT.h" 61 | 62 | 63 | /********************************************************************* 64 | * 65 | * Types 66 | * 67 | ********************************************************************** 68 | */ 69 | // 70 | // If necessary define the _reent struct 71 | // to match the one passed by the used standard library. 72 | // 73 | struct _reent; 74 | 75 | /********************************************************************* 76 | * 77 | * Function prototypes 78 | * 79 | ********************************************************************** 80 | */ 81 | _ssize_t _write (int file, const void *ptr, size_t len); 82 | _ssize_t _write_r(struct _reent *r, int file, const void *ptr, size_t len); 83 | 84 | /********************************************************************* 85 | * 86 | * Global functions 87 | * 88 | ********************************************************************** 89 | */ 90 | 91 | /********************************************************************* 92 | * 93 | * _write() 94 | * 95 | * Function description 96 | * Low-level write function. 97 | * libc subroutines will use this system routine for output to all files, 98 | * including stdout. 99 | * Write data via RTT. 100 | */ 101 | _ssize_t _write(int file, const void *ptr, size_t len) { 102 | (void) file; /* Not used, avoid warning */ 103 | SEGGER_RTT_Write(0, ptr, len); 104 | return len; 105 | } 106 | 107 | /********************************************************************* 108 | * 109 | * _write_r() 110 | * 111 | * Function description 112 | * Low-level reentrant write function. 113 | * libc subroutines will use this system routine for output to all files, 114 | * including stdout. 115 | * Write data via RTT. 116 | */ 117 | _ssize_t _write_r(struct _reent *r, int file, const void *ptr, size_t len) { 118 | (void) file; /* Not used, avoid warning */ 119 | (void) r; /* Not used, avoid warning */ 120 | SEGGER_RTT_Write(0, ptr, len); 121 | return len; 122 | } 123 | 124 | #endif 125 | /****** End Of File *************************************************/ 126 | -------------------------------------------------------------------------------- /Sources/main.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/SummerFalls/UDS_S32K144_APP/1b2a3961f03ecf3ca39563031fc24a1d2443b8fc/Sources/main.c -------------------------------------------------------------------------------- /UDS_DriverConfig/can_cfg.c: -------------------------------------------------------------------------------- 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