2 |
3 | ```c
4 | /*
5 | * ___ ___ _____ ___
6 | * /__/\ ___ /__/\ / /::\ / /\ ___
7 | * \ \:\ /__/\ | |::\ / /:/\:\ / /::\ /__/\
8 | * \ \:\ \ \:\ | |:|:\ / /:/ \:\ / /:/\:\ \ \:\
9 | * _____\__\:\ \ \:\ __|__|:|\:\ /__/:/ \__\:| / /:/~/:/ \ \:\
10 | * /__/::::::::\ ___ \__\:\ /__/::::| \:\ \ \:\ / /:/ /__/:/ /:/___ ___ \__\:\
11 | * \ \:\~~\~~\/ /__/\ | |:| \ \:\~~\__\/ \ \:\ /:/ \ \:\/:::::/ /__/\ | |:|
12 | * \ \:\ ~~~ \ \:\| |:| \ \:\ \ \:\/:/ \ \::/~~~~ \ \:\| |:|
13 | * \ \:\ \ \:\__|:| \ \:\ \ \::/ \ \:\ \ \:\__|:|
14 | * \ \:\ \__\::::/ \ \:\ \__\/ \ \:\ \__\::::/
15 | * \__\/ ~~~~ \__\/ \__\/ ~~~~
16 | */
17 | ```
18 |
19 | ## :book: 简介
20 |
21 | S32K1xx 的 CAN 接 `周立功 USBCANFD-100U-mini`，使用 `ZCANPRO` 软件的 `ECU刷新` 功能进行测试。在加载相应的安全访问算法 DLL 文件 :package: [UDS_SecurityAccess][UDS_SecurityAccess] 之后，通过相应的 UDS 服务将 :package: [UDS_S32K144_FlashDriver][UDS_S32K144_FlashDriver] 的 hex 文件下载至 :package: [UDS_S32K144_Bootloader][UDS_S32K144_Bootloader] 在链接文件中为其预先指定起始地址的 RAM 空间中，并通过 `Flash Driver` 内实际包含的相应的 Flash 驱动函数的相对偏移量以及驱动函数本身来计算相应驱动函数的入口点在 RAM 内的偏移地址后，再通过函数指针的方式调用相应的编程、擦写、校验等 `Flash API` 以实现将 :package: [UDS_S32K144_APP][UDS_S32K144_APP] 烧写至 Flash 的 APP 片区，最终实现 `ECU刷新` 的整个 APP 更新流程。
22 |
23 | ![Pic_ZCANPRO_ECU_Refresh][Pic_ZCANPRO_ECU_Refresh]
24 |
25 | ## :link: 关联工程
26 |
27 | - :package: [UDS_SecurityAccess][UDS_SecurityAccess]
28 | - :package: [UDS_S32K144_Bootloader][UDS_S32K144_Bootloader]
29 | - :package: [UDS_S32K144_FlashDriver][UDS_S32K144_FlashDriver]
30 | - :package: [UDS_S32K144_APP][UDS_S32K144_APP]
31 |
32 | ## :gear: 硬件 & 软件 需求
33 |
34 | ### 硬件需求
35 |
36 | - S32K144-EVB
37 | - J-Link
38 | - USBCANFD-100U-mini
39 | - 12V External Power Supply
40 |
41 | ### 软件需求
42 |
43 | - S32 Design Studio for ARM Version 2.2
44 | - ZCANPRO
45 | - J-Flash
46 |
47 | 48 | 49 | --- 50 | 51 |
52 | 53 | ### :warning: 注意 54 | 55 | ![Note_00][Note_00] 56 | ![Note_01][Note_01] 57 | ![Note_02][Note_02] 58 | 59 | [Pic_ZCANPRO_ECU_Refresh]: ./Pic_ZCANPRO_ECU_Refresh.png 60 | [Note_00]: ./Note_00.png 61 | [Note_01]: ./Note_01.png 62 | [Note_02]: ./Note_02.png 63 | 64 | [UDS_SecurityAccess]: https://github.com/SummerFalls/UDS_SecurityAccess 65 | [UDS_S32K144_Bootloader]: https://github.com/SummerFalls/UDS_S32K144_Bootloader 66 | [UDS_S32K144_FlashDriver]: https://github.com/SummerFalls/UDS_S32K144_FlashDriver 67 | [UDS_S32K144_APP]: https://github.com/SummerFalls/UDS_S32K144_APP 68 | -------------------------------------------------------------------------------- /SDK/platform/devices/S32K144/startup/system_S32K144.c: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2015 Freescale Semiconductor, Inc. 3 | * Copyright 2016-2017 NXP 4 | * All rights reserved. 5 | * 6 | * THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR 7 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 8 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 9 | * IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 10 | * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 11 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 12 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 13 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 14 | * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 15 | * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 16 | * THE POSSIBILITY OF SUCH DAMAGE. 17 | */ 18 | 19 | /** 20 | * @page misra_violations MISRA-C:2012 violations 21 | * 22 | * @section [global] 23 | * Violates MISRA 2012 Advisory Rule 8.9, An object should be defined at block 24 | * scope if its identifier only appears in a single function. 25 | * An object with static storage duration declared at block scope cannot be 26 | * accessed directly from outside the block. 27 | * 28 | * @section [global] 29 | * Violates MISRA 2012 Advisory Rule 11.4, A conversion should not be performed 30 | * between a pointer to object and an integer type. 31 | * The cast is required to initialize a pointer with an unsigned int define, 32 | * representing an address. 33 | * 34 | * @section [global] 35 | * Violates MISRA 2012 Required Rule 11.6, A cast shall not be performed 36 | * between pointer to void and an arithmetic type. 37 | * The cast is required to initialize a pointer with an unsigned int define, 38 | * representing an address. 39 | * 40 | * @section [global] 41 | * Violates MISRA 2012 Advisory Rule 8.7, External could be made static. 42 | * Function is defined for usage by application code. 43 | * 44 | */ 45 | 46 | #include "device_registers.h" 47 | #include "system_S32K144.h" 48 | #include "stdbool.h" 49 | 50 | /* ---------------------------------------------------------------------------- 51 | -- Core clock 52 | ---------------------------------------------------------------------------- */ 53 | 54 | uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK; 55 | 56 | /*FUNCTION********************************************************************** 57 | * 58 | * Function Name : SystemInit 59 | * Description : This function disables the watchdog, enables FPU 60 | * and the power mode protection if the corresponding feature macro 61 | * is enabled. SystemInit is called from startup_device file. 62 | * 63 | * Implements : SystemInit_Activity 64 | *END**************************************************************************/ 65 | void SystemInit(void) 66 | { 67 | /**************************************************************************/ 68 | /* FPU ENABLE*/ 69 | /**************************************************************************/ 70 | #ifdef ENABLE_FPU 71 | /* Enable CP10 and CP11 coprocessors */ 72 | S32_SCB->CPACR |= (S32_SCB_CPACR_CP10_MASK | S32_SCB_CPACR_CP11_MASK); 73 | #ifdef ERRATA_E6940 74 | /* Disable lazy context save of floating point state by clearing LSPEN bit 75 | * Workaround for errata e6940 */ 76 | S32_SCB->FPCCR &= ~(S32_SCB_FPCCR_LSPEN_MASK); 77 | #endif 78 | #endif /* ENABLE_FPU */ 79 | 80 | /**************************************************************************/ 81 | /* WDOG DISABLE*/ 82 | /**************************************************************************/ 83 | 84 | #if (DISABLE_WDOG) 85 | /* Write of the WDOG unlock key to CNT register, must be done in order to allow any modifications*/ 86 | WDOG->CNT = (uint32_t ) FEATURE_WDOG_UNLOCK_VALUE; 87 | /* The dummy read is used in order to make sure that the WDOG registers will be configured only 88 | * after the write of the unlock value was completed. */ 89 | (void)WDOG->CNT; 90 | 91 | /* Initial write of WDOG configuration register: 92 | * enables support for 32-bit refresh/unlock command write words, 93 | * clock select from LPO, update enable, watchdog disabled */ 94 | WDOG->CS = (uint32_t ) ( (1UL << WDOG_CS_CMD32EN_SHIFT) | 95 | (FEATURE_WDOG_CLK_FROM_LPO << WDOG_CS_CLK_SHIFT) | 96 | (0U << WDOG_CS_EN_SHIFT) | 97 | (1U << WDOG_CS_UPDATE_SHIFT) ); 98 | 99 | /* Configure timeout */ 100 | WDOG->TOVAL = (uint32_t )0xFFFF; 101 | #endif /* (DISABLE_WDOG) */ 102 | 103 | /**************************************************************************/ 104 | /* ENABLE CACHE */ 105 | /**************************************************************************/ 106 | #if defined(I_CACHE) && (ICACHE_ENABLE == 1) 107 | /* Invalidate and enable code cache */ 108 | LMEM->PCCCR = LMEM_PCCCR_INVW0(1) | LMEM_PCCCR_INVW1(1) | LMEM_PCCCR_GO(1) | LMEM_PCCCR_ENCACHE(1); 109 | #endif /* defined(I_CACHE) && (ICACHE_ENABLE == 1) */ 110 | } 111 | 112 | /*FUNCTION********************************************************************** 113 | * 114 | * Function Name : SystemCoreClockUpdate 115 | * Description : This function must be called whenever the core clock is changed 116 | * during program execution. It evaluates the clock register settings and calculates 117 | * the current core clock. 118 | * 119 | * Implements : SystemCoreClockUpdate_Activity 120 | *END**************************************************************************/ 121 | void SystemCoreClockUpdate(void) 122 | { 123 | uint32_t SCGOUTClock = 0U; /* Variable to store output clock frequency of the SCG module */ 124 | uint32_t regValue; /* Temporary variable */ 125 | uint32_t divider, prediv, multi; 126 | bool validSystemClockSource = true; 127 | static const uint32_t fircFreq[] = { 128 | FEATURE_SCG_FIRC_FREQ0, 129 | }; 130 | 131 | divider = ((SCG->CSR & SCG_CSR_DIVCORE_MASK) >> SCG_CSR_DIVCORE_SHIFT) + 1U; 132 | 133 | switch ((SCG->CSR & SCG_CSR_SCS_MASK) >> SCG_CSR_SCS_SHIFT) { 134 | case 0x1: 135 | /* System OSC */ 136 | SCGOUTClock = CPU_XTAL_CLK_HZ; 137 | break; 138 | case 0x2: 139 | /* Slow IRC */ 140 | regValue = (SCG->SIRCCFG & SCG_SIRCCFG_RANGE_MASK) >> SCG_SIRCCFG_RANGE_SHIFT; 141 | 142 | if (regValue != 0U) 143 | { 144 | SCGOUTClock = FEATURE_SCG_SIRC_HIGH_RANGE_FREQ; 145 | } 146 | 147 | break; 148 | case 0x3: 149 | /* Fast IRC */ 150 | regValue = (SCG->FIRCCFG & SCG_FIRCCFG_RANGE_MASK) >> SCG_FIRCCFG_RANGE_SHIFT; 151 | SCGOUTClock= fircFreq[regValue]; 152 | break; 153 | case 0x6: 154 | /* System PLL */ 155 | SCGOUTClock = CPU_XTAL_CLK_HZ; 156 | prediv = ((SCG->SPLLCFG & SCG_SPLLCFG_PREDIV_MASK) >> SCG_SPLLCFG_PREDIV_SHIFT) + 1U; 157 | multi = ((SCG->SPLLCFG & SCG_SPLLCFG_MULT_MASK) >> SCG_SPLLCFG_MULT_SHIFT) + 16U; 158 | SCGOUTClock = SCGOUTClock * multi / (prediv * 2U); 159 | break; 160 | default: 161 | validSystemClockSource = false; 162 | break; 163 | } 164 | 165 | if (validSystemClockSource == true) { 166 | SystemCoreClock = (SCGOUTClock / divider); 167 | } 168 | } 169 | 170 | /*FUNCTION********************************************************************** 171 | * 172 | * Function Name : SystemSoftwareReset 173 | * Description : This function is used to initiate a system reset 174 | * 175 | * Implements : SystemSoftwareReset_Activity 176 | *END**************************************************************************/ 177 | void SystemSoftwareReset(void) 178 | { 179 | uint32_t regValue; 180 | 181 | /* Read Application Interrupt and Reset Control Register */ 182 | regValue = S32_SCB->AIRCR; 183 | 184 | /* Clear register key */ 185 | regValue &= ~( S32_SCB_AIRCR_VECTKEY_MASK); 186 | 187 | /* Configure System reset request bit and Register Key */ 188 | regValue |= S32_SCB_AIRCR_VECTKEY(FEATURE_SCB_VECTKEY); 189 | regValue |= S32_SCB_AIRCR_SYSRESETREQ(0x1u); 190 | 191 | /* Write computed register value */ 192 | S32_SCB->AIRCR = regValue; 193 | } 194 | 195 | /******************************************************************************* 196 | * EOF 197 | ******************************************************************************/ 198 | -------------------------------------------------------------------------------- /SDK/platform/devices/S32K144/startup/system_S32K144.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2015 Freescale Semiconductor, Inc. 3 | * Copyright 2016-2017 NXP 4 | * All rights reserved. 5 | * 6 | * THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR 7 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 8 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 9 | * IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 10 | * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 11 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 12 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 13 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 14 | * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 15 | * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 16 | * THE POSSIBILITY OF SUCH DAMAGE. 17 | */ 18 | 19 | 20 | /*! @addtogroup soc_support_S32K144*/ 21 | /*! @{*/ 22 | 23 | /*! 24 | * @file system_S32K144.h 25 | * @brief Device specific configuration file for S32K144 26 | */ 27 | 28 | #ifndef SYSTEM_S32K144_H_ 29 | #define SYSTEM_S32K144_H_ /**< Symbol preventing repeated inclusion */ 30 | 31 | #include
50 | * PORT HAL provides the API for reading and writing register bit-fields belonging to the PORT module. 51 | *
52 | * @{ 53 | */ 54 | 55 | /******************************************************************************* 56 | * Definitions 57 | ******************************************************************************/ 58 | /******************************************************************************* 59 | * API 60 | ******************************************************************************/ 61 | 62 | #if defined(__cplusplus) 63 | extern "C" { 64 | #endif 65 | 66 | /*! 67 | * @name Configuration 68 | * @{ 69 | */ 70 | 71 | /*! 72 | * @brief Initializes the pins with the given configuration structure 73 | * 74 | * This function configures the pins with the options provided in the 75 | * given structure. 76 | * 77 | * @param[in] config the configuration structure 78 | */ 79 | void PINS_Init(const pin_settings_config_t * config); 80 | 81 | #if FEATURE_PINS_HAS_PULL_SELECTION 82 | /*! 83 | * @brief Configures the internal resistor. 84 | * 85 | * Pull configuration is valid in all digital pin muxing modes. 86 | * 87 | * @param[in] base port base pointer. 88 | * @param[in] pin port pin number 89 | * @param[in] pullConfig internal resistor pull feature selection 90 | * - PORT_PULL_NOT_ENABLED: internal pull-down or pull-up resistor is not enabled. 91 | * - PORT_PULL_DOWN_ENABLED: internal pull-down resistor is enabled. 92 | * - PORT_PULL_UP_ENABLED: internal pull-up resistor is enabled. 93 | */ 94 | static inline void PINS_SetPullSel(PORT_Type * const base, 95 | uint32_t pin, 96 | port_pull_config_t pullConfig) 97 | { 98 | DEV_ASSERT(pin < PORT_PCR_COUNT); 99 | switch (pullConfig) 100 | { 101 | case PORT_INTERNAL_PULL_NOT_ENABLED: 102 | { 103 | base->PCR[pin] &= ~(PORT_PCR_PE_MASK); 104 | } 105 | break; 106 | case PORT_INTERNAL_PULL_DOWN_ENABLED: 107 | { 108 | uint32_t regValue = base->PCR[pin]; 109 | regValue &= ~(PORT_PCR_PS_MASK); 110 | regValue |= PORT_PCR_PE(1U); 111 | base->PCR[pin] = regValue; 112 | } 113 | break; 114 | case PORT_INTERNAL_PULL_UP_ENABLED: 115 | { 116 | uint32_t regValue = base->PCR[pin]; 117 | regValue |= PORT_PCR_PE(1U); 118 | regValue |= PORT_PCR_PS(1U); 119 | base->PCR[pin] = regValue; 120 | } 121 | break; 122 | default: 123 | /* invalid command */ 124 | DEV_ASSERT(false); 125 | break; 126 | } 127 | } 128 | 129 | #endif /* if FEATURE_PINS_HAS_PULL_SELECTION */ 130 | 131 | /*! 132 | * @brief Configures the pin muxing. 133 | * 134 | * @param[in] base port base pointer 135 | * @param[in] pin port pin number 136 | * @param[in] mux pin muxing slot selection 137 | * - PORT_PIN_DISABLED: Pin disabled. 138 | * - PORT_MUX_AS_GPIO : Set as GPIO. 139 | * - PORT_MUX_ADC_INTERLEAVE : For ADC interleaved 140 | * - others : chip-specific. 141 | */ 142 | void PINS_SetMuxModeSel(PORT_Type * const base, 143 | uint32_t pin, 144 | port_mux_t mux); 145 | 146 | /*! 147 | * @brief Configures the port pin interrupt/DMA request. 148 | * 149 | * @param[in] base port base pointer. 150 | * @param[in] pin port pin number 151 | * @param[in] intConfig interrupt configuration 152 | * - PORT_INT_DISABLED : Interrupt/DMA request disabled. 153 | * - PORT_DMA_RISING_EDGE : DMA request on rising edge. 154 | * - PORT_DMA_FALLING_EDGE : DMA request on falling edge. 155 | * - PORT_DMA_EITHER_EDGE : DMA request on either edge. 156 | * - PORT_FLAG_RISING_EDGE : Flag sets on rising edge only. 157 | * - PORT_FLAG_FALLING_EDGE: Flag sets on falling edge only. 158 | * - PORT_FLAG_EITHER_EDGE : Flag sets on either edge only. 159 | * - PORT_INT_LOGIC_ZERO : Interrupt when logic zero. 160 | * - PORT_INT_RISING_EDGE : Interrupt on rising edge. 161 | * - PORT_INT_FALLING_EDGE : Interrupt on falling edge. 162 | * - PORT_INT_EITHER_EDGE : Interrupt on either edge. 163 | * - PORT_INT_LOGIC_ONE : Interrupt when logic one. 164 | * - PORT_HIGH_TRIGGER_OUT : Enable active high trigger output, flag is disabled. 165 | * - PORT_LOW_TRIGGER_OUT : Enable active low trigger output, flag is disabled. 166 | */ 167 | static inline void PINS_SetPinIntSel(PORT_Type * const base, 168 | uint32_t pin, 169 | port_interrupt_config_t intConfig) 170 | { 171 | DEV_ASSERT(pin < PORT_PCR_COUNT); 172 | uint32_t regValue = base->PCR[pin]; 173 | regValue &= ~(PORT_PCR_IRQC_MASK); 174 | regValue |= PORT_PCR_IRQC(intConfig); 175 | base->PCR[pin] = regValue; 176 | } 177 | 178 | /*! 179 | * @brief Gets the current port pin interrupt/DMA request configuration. 180 | * 181 | * @param[in] base port base pointer 182 | * @param[in] pin port pin number 183 | * @return interrupt configuration 184 | * - PORT_INT_DISABLED : Interrupt/DMA request disabled. 185 | * - PORT_DMA_RISING_EDGE : DMA request on rising edge. 186 | * - PORT_DMA_FALLING_EDGE : DMA request on falling edge. 187 | * - PORT_DMA_EITHER_EDGE : DMA request on either edge. 188 | * - PORT_FLAG_RISING_EDGE : Flag sets on rising edge only. 189 | * - PORT_FLAG_FALLING_EDGE: Flag sets on falling edge only. 190 | * - PORT_FLAG_EITHER_EDGE : Flag sets on either edge only. 191 | * - PORT_INT_LOGIC_ZERO : Interrupt when logic zero. 192 | * - PORT_INT_RISING_EDGE : Interrupt on rising edge. 193 | * - PORT_INT_FALLING_EDGE : Interrupt on falling edge. 194 | * - PORT_INT_EITHER_EDGE : Interrupt on either edge. 195 | * - PORT_INT_LOGIC_ONE : Interrupt when logic one. 196 | * - PORT_HIGH_TRIGGER_OUT : Enable active high trigger output, flag is disabled. 197 | * - PORT_LOW_TRIGGER_OUT : Enable active low trigger output, flag is disabled. 198 | */ 199 | static inline port_interrupt_config_t PINS_GetPinIntSel(const PORT_Type * const base, 200 | uint32_t pin) 201 | { 202 | DEV_ASSERT(pin < PORT_PCR_COUNT); 203 | uint32_t regValue = base->PCR[pin]; 204 | regValue = (regValue & PORT_PCR_IRQC_MASK) >> PORT_PCR_IRQC_SHIFT; 205 | 206 | return (port_interrupt_config_t)regValue; 207 | } 208 | 209 | /*! 210 | * @brief Clears the individual pin-interrupt status flag. 211 | * 212 | * @param[in] base port base pointer 213 | * @param[in] pin port pin number 214 | */ 215 | static inline void PINS_ClearPinIntFlagCmd(PORT_Type * const base, 216 | uint32_t pin) 217 | { 218 | DEV_ASSERT(pin < PORT_PCR_COUNT); 219 | uint32_t regValue = base->PCR[pin]; 220 | regValue &= ~(PORT_PCR_ISF_MASK); 221 | regValue |= PORT_PCR_ISF(1U); 222 | base->PCR[pin] = regValue; 223 | } 224 | 225 | /*! 226 | * @brief Enables digital filter for digital pin muxing 227 | * 228 | * @param[in] base port base pointer 229 | * @param[in] pin port pin number 230 | */ 231 | static inline void PINS_EnableDigitalFilter(PORT_Type * const base, 232 | uint32_t pin) 233 | { 234 | DEV_ASSERT(pin < PORT_PCR_COUNT); 235 | base->DFER |= (uint32_t)1U << pin; 236 | } 237 | 238 | /*! 239 | * @brief Disables digital filter for digital pin muxing 240 | * 241 | * @param[in] base port base pointer 242 | * @param[in] pin port pin number 243 | */ 244 | static inline void PINS_DisableDigitalFilter(PORT_Type * const base, 245 | uint32_t pin) 246 | { 247 | DEV_ASSERT(pin < PORT_PCR_COUNT); 248 | base->DFER &= ~((uint32_t)1U << pin); 249 | } 250 | 251 | /*! 252 | * @brief Configures digital filter clock for port with given configuration 253 | * 254 | * @param[in] base port base pointer 255 | * @param[in] config configuration struct 256 | */ 257 | static inline void PINS_ConfigDigitalFilter(PORT_Type * const base, 258 | const port_digital_filter_config_t * const config) 259 | { 260 | DEV_ASSERT(config->width <= PORT_DFWR_FILT_MASK); 261 | base->DFCR = PORT_DFCR_CS(config->clock); 262 | base->DFWR = PORT_DFWR_FILT(config->width); 263 | } 264 | 265 | /*! 266 | * @brief Reads the entire port interrupt status flag. 267 | * 268 | * @param[in] base port base pointer 269 | * @return all 32 pin interrupt status flags. For specific bit: 270 | * - 0: interrupt is not detected. 271 | * - 1: interrupt is detected. 272 | */ 273 | static inline uint32_t PINS_GetPortIntFlag(const PORT_Type * const base) 274 | { 275 | uint32_t regValue = base->ISFR; 276 | 277 | return regValue; 278 | } 279 | 280 | /*! 281 | * @brief Clears the entire port interrupt status flag. 282 | * 283 | * @param[in] base port base pointer 284 | */ 285 | static inline void PINS_ClearPortIntFlagCmd(PORT_Type * const base) 286 | { 287 | base->ISFR = PORT_ISFR_ISF_MASK; 288 | } 289 | 290 | /*! 291 | * @brief Quickly configures multiple pins with the same pin configuration. 292 | * 293 | * @param[in] base port base pointer 294 | * @param[in] pins pin mask where each bit represents one pin 295 | * @param[in] value the config value will be updated for the pins are set to '1' 296 | * @param[in] halfPort the lower or upper half of pin registers at the same port 297 | */ 298 | void PINS_SetGlobalPinControl(PORT_Type * const base, 299 | uint16_t pins, 300 | uint16_t value, 301 | port_global_control_pins_t halfPort); 302 | 303 | /*! 304 | * @brief Quickly configures multiple pins with the same interrupt configuration. 305 | * 306 | * @param[in] base port base pointer 307 | * @param[in] pins pin mask where each bit represents one pin 308 | * @param[in] value the config value will be updated for the pins are set to '1' 309 | * @param[in] halfPort the lower or upper half of pin registers at the same port 310 | */ 311 | void PINS_SetGlobalIntControl(PORT_Type * const base, 312 | uint16_t pins, 313 | uint16_t value, 314 | port_global_control_pins_t halfPort); 315 | 316 | 317 | #if FEATURE_PINS_HAS_OVER_CURRENT 318 | /*! 319 | * @brief Reads the entire over current port interrupt status flag. 320 | * 321 | * @param[in] base port base pointer 322 | * @return all 32 pin interrupt status flags. For specific bit: 323 | * - 0: interrupt is not detected. 324 | * - 1: interrupt is detected. 325 | */ 326 | static inline uint32_t PINS_GetOverCurPortIntFlag(const PORT_Type * const base) 327 | { 328 | return ((uint32_t)(base->OCFR)); 329 | } 330 | 331 | /*! 332 | * @brief Clears the entire over current port interrupt status flag. 333 | * 334 | * @param[in] base port base pointer 335 | */ 336 | static inline void PINS_ClearOverCurPortIntFlag(PORT_Type * const base) 337 | { 338 | base->ISFR = PORT_OCFR_OCF_MASK; 339 | } 340 | #endif /* FEATURE_PINS_HAS_OVER_CURRENT */ 341 | 342 | /*! @} */ 343 | 344 | /*! @} */ 345 | 346 | #if defined(__cplusplus) 347 | } 348 | #endif 349 | 350 | /*! @} */ 351 | 352 | #endif /* PINS_PORT_HW_ACCESS_H */ 353 | /******************************************************************************* 354 | * EOF 355 | ******************************************************************************/ 356 | -------------------------------------------------------------------------------- /Sources/NVM_Flash.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/SummerFalls/UDS_S32K144_FlashDriver/cd5289c1df01f55d19ab565eebd82d6800d8b9bd/Sources/NVM_Flash.c -------------------------------------------------------------------------------- /Sources/NVM_Flash.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/SummerFalls/UDS_S32K144_FlashDriver/cd5289c1df01f55d19ab565eebd82d6800d8b9bd/Sources/NVM_Flash.h -------------------------------------------------------------------------------- /Sources/main.c: -------------------------------------------------------------------------------- 1 | /* ################################################################### 2 | ** Filename : main.c 3 | ** Processor : S32K1xx 4 | ** Abstract : 5 | ** Main module. 6 | ** This module contains user's application code. 7 | ** Settings : 8 | ** Contents : 9 | ** No public methods 10 | ** 11 | ** ###################################################################*/ 12 | /*! 13 | ** @file main.c 14 | ** @version 01.00 15 | ** @brief 16 | ** Main module. 17 | ** This module contains user's application code. 18 | */ 19 | /*! 20 | ** @addtogroup main_module main module documentation 21 | ** @{ 22 | */ 23 | /* MODULE main */ 24 | 25 | /* Including necessary module. Cpu.h contains other modules needed for compiling.*/ 26 | #include "Cpu.h" 27 | #include "NVM_Flash.h" 28 | 29 | volatile int exit_code = 0; 30 | 31 | /* User includes (#include below this line is not maintained by Processor Expert) */ 32 | 33 | /*! 34 | \brief The main function for the project. 35 | \details The startup initialization sequence is the following: 36 | * - startup asm routine 37 | * - main() 38 | */ 39 | int main(void) 40 | { 41 | /* Write your local variable definition here */ 42 | /*** Processor Expert internal initialization. DON'T REMOVE THIS CODE!!! ***/ 43 | #ifdef PEX_RTOS_INIT 44 | PEX_RTOS_INIT(); /* Initialization of the selected RTOS. Macro is defined by the RTOS component. */ 45 | #endif 46 | /*** End of Processor Expert internal initialization. ***/ 47 | /* Write your code here */ 48 | NVM_TestFlashDriver(); 49 | /* For example: for(;;) { } */ 50 | /*** Don't write any code pass this line, or it will be deleted during code generation. ***/ 51 | /*** RTOS startup code. Macro PEX_RTOS_START is defined by the RTOS component. DON'T MODIFY THIS CODE!!! ***/ 52 | #ifdef PEX_RTOS_START 53 | PEX_RTOS_START(); /* Startup of the selected RTOS. Macro is defined by the RTOS component. */ 54 | #endif 55 | /*** End of RTOS startup code. ***/ 56 | /*** Processor Expert end of main routine. DON'T MODIFY THIS CODE!!! ***/ 57 | for(;;) { 58 | if(exit_code != 0) { 59 | break; 60 | } 61 | } 62 | return exit_code; 63 | /*** Processor Expert end of main routine. DON'T WRITE CODE BELOW!!! ***/ 64 | } /*** End of main routine. DO NOT MODIFY THIS TEXT!!! ***/ 65 | 66 | /* END main */ 67 | /*! 68 | ** @} 69 | */ 70 | /* 71 | ** ################################################################### 72 | ** 73 | ** This file was created by Processor Expert 10.1 [05.21] 74 | ** for the NXP S32K series of microcontrollers. 75 | ** 76 | ** ################################################################### 77 | */ 78 | -------------------------------------------------------------------------------- /Sources/一键格式化所有代码(包括子目录)_精简版.bat: -------------------------------------------------------------------------------- 1 | for /R %%f in (*.c;*.h) do AStyle.exe -A1 -s4 -xV -S -w -Y -M60 -f -p -xg -H -xe -k3 -W3 -xb -j -xf -xh -c -xC200 -n -v %%f 2 | pause -------------------------------------------------------------------------------- /UDS_S32K144_FlashDriverExtracted.hex: -------------------------------------------------------------------------------- 1 | :020000041FFFDC 2 | :10800000110000004901000065020000B1030000FA 3 | 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