├── assignment-2 ├── benchtest │ ├── en & clear │ │ ├── en & clear.run │ │ ├── en & clear.ans │ │ ├── en & clear.mem │ │ ├── en & clear.in │ │ ├── en & clear.txt │ │ └── en & clear.out │ ├── ad hoc │ │ ├── ad hoc.run │ │ ├── ad hoc.mem │ │ ├── ad hoc.ans │ │ ├── ad hoc.in │ │ ├── ad hoc.txt │ │ └── ad hoc.out │ ├── quick multiply │ │ ├── quick multiply.ans │ │ ├── quick multiply.run │ │ ├── quick multiply.mem │ │ ├── quick multiply.in │ │ ├── quick multiply.txt │ │ └── quick multiply.out │ ├── i-type │ │ ├── i-type.ans │ │ ├── i-type.run │ │ ├── i-type.mem │ │ ├── i-type.in │ │ ├── i-type.txt │ │ └── i-type.out │ ├── bisection │ │ ├── bisection.run │ │ ├── bisection.mem │ │ ├── bisection.in │ │ ├── bisection.data │ │ ├── bisection.ans │ │ ├── bisection.txt │ │ └── bisection.out │ ├── mutual recursion │ │ ├── mutual recursion.out │ │ ├── mutual recursion.run │ │ ├── mutual recursion.ans │ │ ├── mutual recursion.mem │ │ ├── mutual recursion.txt │ │ └── mutual recursion.in │ ├── gcd │ │ ├── gcd.mem │ │ ├── gcd.in │ │ ├── gcd.ans │ │ ├── gcd.txt │ │ ├── gcd.out │ │ └── gcd.run │ ├── bubble sort │ │ ├── bubble sort.mem │ │ ├── bubble sort.in │ │ ├── bubble sort.data │ │ ├── bubble sort.ans │ │ ├── bubble sort.txt │ │ ├── bubble sort.out │ │ └── bubble sort.run │ ├── testjr │ │ ├── testjr.ans │ │ ├── testjr.run │ │ ├── testjr.mem │ │ ├── testjr.in │ │ ├── testjr.txt │ │ └── testjr.out │ ├── factorial │ │ ├── factorial.mem │ │ ├── factorial.run │ │ ├── factorial.ans │ │ ├── factorial.in │ │ ├── factorial.txt │ │ └── factorial.out │ ├── run_simulation.tcl │ ├── assembler.py │ └── cpu_tb.sv ├── makefile ├── check.sh ├── check.py └── index.md ├── assignment-3(I) ├── benchtest │ ├── en & clear │ │ ├── en & clear.run │ │ ├── en & clear.ans │ │ ├── en & clear.mem │ │ ├── en & clear.in │ │ ├── en & clear.txt │ │ └── en & clear.out │ ├── ad hoc │ │ ├── ad hoc.run │ │ ├── ad hoc.mem │ │ ├── ad hoc.ans │ │ ├── ad hoc.in │ │ ├── ad hoc.txt │ │ └── ad hoc.out │ ├── quick multiply │ │ ├── quick multiply.ans │ │ ├── quick multiply.run │ │ ├── quick multiply.mem │ │ ├── quick multiply.in │ │ ├── quick multiply.txt │ │ └── quick multiply.out │ ├── i-type │ │ ├── i-type.ans │ │ ├── i-type.run │ │ ├── i-type.mem │ │ ├── i-type.in │ │ ├── i-type.txt │ │ └── i-type.out │ ├── writeback │ │ ├── writeback.mem │ │ ├── writeback.in │ │ ├── writeback.txt │ │ └── writeback.out │ ├── bisection │ │ ├── bisection.run │ │ ├── bisection.mem │ │ ├── bisection.in │ │ ├── bisection.data │ │ ├── bisection.ans │ │ ├── bisection.txt │ │ └── bisection.out │ ├── mutual recursion │ │ ├── mutual recursion.out │ │ ├── mutual recursion.run │ │ ├── mutual recursion.ans │ │ ├── mutual recursion.mem │ │ ├── mutual recursion.txt │ │ └── mutual recursion.in │ ├── random write │ │ ├── random write.mem │ │ ├── random write.in │ │ ├── random write.txt │ │ ├── random write.out │ │ ├── random write.ans │ │ └── random write.run │ ├── gcd │ │ ├── gcd.mem │ │ ├── gcd.in │ │ ├── gcd.ans │ │ ├── gcd.txt │ │ ├── gcd.out │ │ └── gcd.run │ ├── bubble sort │ │ ├── bubble sort.mem │ │ ├── bubble sort.in │ │ ├── bubble sort.data │ │ ├── bubble sort.ans │ │ ├── bubble sort.txt │ │ ├── bubble sort.out │ │ └── bubble sort.run │ ├── testjr │ │ ├── testjr.ans │ │ ├── testjr.run │ │ ├── testjr.mem │ │ ├── testjr.in │ │ ├── testjr.txt │ │ └── testjr.out │ ├── factorial │ │ ├── factorial.mem │ │ ├── factorial.run │ │ ├── factorial.ans │ │ ├── factorial.in │ │ ├── factorial.txt │ │ └── factorial.out │ ├── run_simulation.tcl │ ├── README.md │ ├── assembler.py │ └── cpu_tb.sv ├── img │ └── cache.png ├── makefile ├── src │ ├── cache.vh │ ├── line.v │ ├── cache_controller.v │ ├── set.v │ └── cache.v └── index.md ├── logo.png ├── assignment-1 ├── benchtest │ ├── ad hoc │ │ ├── ad hoc.run │ │ ├── ad hoc.mem │ │ ├── ad hoc.ans │ │ ├── ad hoc.in │ │ ├── ad hoc.txt │ │ └── ad hoc.out │ ├── quick multiply │ │ ├── quick multiply.ans │ │ ├── quick multiply.run │ │ ├── quick multiply.mem │ │ ├── quick multiply.in │ │ ├── quick multiply.txt │ │ └── quick multiply.out │ ├── testzeroext │ │ ├── testzeroext.run │ │ ├── testzeroext.mem │ │ ├── testzeroext.ans │ │ ├── testzeroext.in │ │ ├── testzeroext.txt │ │ └── testzeroext.out │ ├── bisection │ │ ├── bisection.run │ │ ├── bisection.mem │ │ ├── bisection.in │ │ ├── bisection.data │ │ ├── bisection.ans │ │ ├── bisection.txt │ │ └── bisection.out │ ├── gcd │ │ ├── gcd.mem │ │ ├── gcd.in │ │ ├── gcd.txt │ │ ├── gcd.ans │ │ ├── gcd.out │ │ └── gcd.run │ ├── bubble sort │ │ ├── bubble sort.mem │ │ ├── bubble sort.in │ │ ├── bubble sort.data │ │ ├── bubble sort.ans │ │ ├── bubble sort.txt │ │ ├── bubble sort.out │ │ └── bubble sort.run │ ├── factorial │ │ ├── factorial.mem │ │ ├── factorial.run │ │ ├── factorial.ans │ │ ├── factorial.in │ │ ├── factorial.txt │ │ └── factorial.out │ ├── run_simulation.tcl │ ├── cpu_tb.sv │ └── assembler.py ├── makefile └── index.md ├── logo-rev.png ├── assignment-3(II) ├── img │ └── tech.png ├── src │ ├── bpb.vh │ └── bpb.v └── index.md ├── .gitignore ├── README.md └── index.html /assignment-2/benchtest/en & clear/en & clear.run: -------------------------------------------------------------------------------- 1 | [0x00000004]=0x0000000b -------------------------------------------------------------------------------- /assignment-3(I)/benchtest/en & clear/en & clear.run: -------------------------------------------------------------------------------- 1 | [0x00000004]=0x0000000b -------------------------------------------------------------------------------- /assignment-2/benchtest/en & clear/en & clear.ans: -------------------------------------------------------------------------------- 1 | 00000030 2 | 00000000 3 | 0000000b -------------------------------------------------------------------------------- /assignment-3(I)/benchtest/en & clear/en & clear.ans: -------------------------------------------------------------------------------- 1 | 00000030 2 | 00000000 3 | 0000000b -------------------------------------------------------------------------------- /logo.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/SunflowerAries/ICS-Spring20-Fudan/HEAD/logo.png -------------------------------------------------------------------------------- /assignment-1/benchtest/ad hoc/ad hoc.run: -------------------------------------------------------------------------------- 1 | [0x00000050]=0x00000007 2 | [0x00000054]=0x00000007 -------------------------------------------------------------------------------- /assignment-2/benchtest/ad hoc/ad hoc.run: -------------------------------------------------------------------------------- 1 | [0x00000050]=0x00000007 2 | [0x00000054]=0x00000007 -------------------------------------------------------------------------------- /logo-rev.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/SunflowerAries/ICS-Spring20-Fudan/HEAD/logo-rev.png -------------------------------------------------------------------------------- /assignment-3(I)/benchtest/ad hoc/ad hoc.run: -------------------------------------------------------------------------------- 1 | [0x00000050]=0x00000007 2 | [0x00000054]=0x00000007 -------------------------------------------------------------------------------- /assignment-1/benchtest/quick multiply/quick multiply.ans: -------------------------------------------------------------------------------- 1 | 00000034 2 | 00000063 3 | 000001ef 4 | 00000e4f -------------------------------------------------------------------------------- /assignment-1/benchtest/testzeroext/testzeroext.run: -------------------------------------------------------------------------------- 1 | [0x00000020]=0x0000ffff 2 | [0x00000028]=0x0000ffff -------------------------------------------------------------------------------- /assignment-2/benchtest/quick multiply/quick multiply.ans: -------------------------------------------------------------------------------- 1 | 00000040 2 | 00000063 3 | 000001ef 4 | 00000e4f -------------------------------------------------------------------------------- /assignment-3(I)/benchtest/quick multiply/quick multiply.ans: -------------------------------------------------------------------------------- 1 | 00000040 2 | 00000063 3 | 000001ef 4 | 00000e4f -------------------------------------------------------------------------------- /assignment-2/benchtest/i-type/i-type.ans: -------------------------------------------------------------------------------- 1 | 00000044 2 | 00000000 3 | 00000001 4 | 0000f81c 5 | 0000781c 6 | 0000fff9 7 | fffffffc -------------------------------------------------------------------------------- /assignment-3(I)/img/cache.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/SunflowerAries/ICS-Spring20-Fudan/HEAD/assignment-3(I)/img/cache.png -------------------------------------------------------------------------------- /assignment-3(II)/img/tech.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/SunflowerAries/ICS-Spring20-Fudan/HEAD/assignment-3(II)/img/tech.png -------------------------------------------------------------------------------- /assignment-3(I)/benchtest/i-type/i-type.ans: -------------------------------------------------------------------------------- 1 | 00000044 2 | 00000000 3 | 00000001 4 | 0000f81c 5 | 0000781c 6 | 0000fff9 7 | fffffffc -------------------------------------------------------------------------------- /assignment-1/benchtest/quick multiply/quick multiply.run: -------------------------------------------------------------------------------- 1 | [0x00000000]=0x00000063 2 | [0x00000004]=0x000001ef 3 | [0x00000008]=0x00000e4f -------------------------------------------------------------------------------- /assignment-2/benchtest/quick multiply/quick multiply.run: -------------------------------------------------------------------------------- 1 | [0x00000000]=0x00000063 2 | [0x00000004]=0x000001ef 3 | [0x00000008]=0x00000e4f -------------------------------------------------------------------------------- /assignment-3(I)/benchtest/quick multiply/quick multiply.run: -------------------------------------------------------------------------------- 1 | [0x00000000]=0x00000063 2 | [0x00000004]=0x000001ef 3 | [0x00000008]=0x00000e4f -------------------------------------------------------------------------------- /assignment-3(I)/benchtest/writeback/writeback.mem: -------------------------------------------------------------------------------- 1 | 00002020 2 | 20060200 3 | 8c850000 4 | 20840008 5 | 14c4fffd 6 | 00000000 7 | 00000000 8 | 00000000 -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | index.html.bk 2 | assignment-3(I)/cache-test/ 3 | assignment-3(I)/README* 4 | Assignment-3.md 5 | #assignment-1/benchtest/assembler.py 6 | -------------------------------------------------------------------------------- /assignment-1/benchtest/bisection/bisection.run: -------------------------------------------------------------------------------- 1 | [0x00000080]=0x0000000f 2 | [0x00000084]=0x00000017 3 | [0x00000088]=0x00000013 4 | [0x0000008c]=0x00000011 -------------------------------------------------------------------------------- /assignment-2/benchtest/bisection/bisection.run: -------------------------------------------------------------------------------- 1 | [0x00000080]=0x0000000f 2 | [0x00000084]=0x00000017 3 | [0x00000088]=0x00000013 4 | [0x0000008c]=0x00000011 -------------------------------------------------------------------------------- /assignment-3(I)/benchtest/bisection/bisection.run: -------------------------------------------------------------------------------- 1 | [0x00000080]=0x0000000f 2 | [0x00000084]=0x00000017 3 | [0x00000088]=0x00000013 4 | [0x0000008c]=0x00000011 -------------------------------------------------------------------------------- /assignment-2/benchtest/mutual recursion/mutual recursion.out: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/SunflowerAries/ICS-Spring20-Fudan/HEAD/assignment-2/benchtest/mutual recursion/mutual recursion.out -------------------------------------------------------------------------------- /assignment-3(I)/benchtest/mutual recursion/mutual recursion.out: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/SunflowerAries/ICS-Spring20-Fudan/HEAD/assignment-3(I)/benchtest/mutual recursion/mutual recursion.out -------------------------------------------------------------------------------- /assignment-2/benchtest/i-type/i-type.run: -------------------------------------------------------------------------------- 1 | [0x00000000]=0x00000000 2 | [0x00000004]=0x00000001 3 | [0x00000008]=0x0000f81c 4 | [0x0000000c]=0x0000781c 5 | [0x00000010]=0x0000fff9 6 | [0x00000014]=0xfffffffc -------------------------------------------------------------------------------- /assignment-3(I)/benchtest/writeback/writeback.in: -------------------------------------------------------------------------------- 1 | add $a0, $0, $0 2 | addi $a2, $0, 512 3 | start: 4 | lw $a1, 0($a0) 5 | addi $a0, $a0, 8 6 | bne $a0, $a2, start 7 | nop 8 | nop 9 | nop 10 | -------------------------------------------------------------------------------- /assignment-1/benchtest/testzeroext/testzeroext.mem: -------------------------------------------------------------------------------- 1 | 2004ffff 2 | 20050000 3 | 201d0020 4 | 3084ffff 5 | 34a5ffff 6 | afa40000 7 | afa50008 8 | 00000000 9 | 00000000 10 | 00000000 11 | 00000000 12 | -------------------------------------------------------------------------------- /assignment-3(I)/benchtest/i-type/i-type.run: -------------------------------------------------------------------------------- 1 | [0x00000000]=0x00000000 2 | [0x00000004]=0x00000001 3 | [0x00000008]=0x0000f81c 4 | [0x0000000c]=0x0000781c 5 | [0x00000010]=0x0000fff9 6 | [0x00000014]=0xfffffffc -------------------------------------------------------------------------------- /assignment-3(II)/src/bpb.vh: -------------------------------------------------------------------------------- 1 | `ifndef BPB_VH 2 | `define BPB_VH 3 | 4 | `timescale 1ns / 1ps 5 | 6 | // number of entries 7 | `define BPB_E 8 8 | // index bits 9 | `define BPB_T 10 10 | 11 | `endif -------------------------------------------------------------------------------- /assignment-2/benchtest/en & clear/en & clear.mem: -------------------------------------------------------------------------------- 1 | 20020005 2 | 2003000c 3 | 2067fff7 4 | 00e22025 5 | 00642824 6 | 00a42820 7 | 14050001 8 | 00a42820 9 | ac050004 10 | 00000000 11 | 00000000 12 | 00000000 13 | -------------------------------------------------------------------------------- /assignment-1/benchtest/testzeroext/testzeroext.ans: -------------------------------------------------------------------------------- 1 | 0000001c 2 | 00000000 3 | 00000000 4 | 00000000 5 | 00000000 6 | 00000000 7 | 00000000 8 | 00000000 9 | 00000000 10 | 0000ffff 11 | 00000000 12 | 0000ffff 13 | -------------------------------------------------------------------------------- /assignment-3(I)/benchtest/en & clear/en & clear.mem: -------------------------------------------------------------------------------- 1 | 20020005 2 | 2003000c 3 | 2067fff7 4 | 00e22025 5 | 00642824 6 | 00a42820 7 | 14050001 8 | 00a42820 9 | ac050004 10 | 00000000 11 | 00000000 12 | 00000000 13 | -------------------------------------------------------------------------------- /assignment-1/benchtest/gcd/gcd.mem: -------------------------------------------------------------------------------- 1 | 200200bd 2 | 2003011f 3 | 00002020 4 | ac820000 5 | ac830004 6 | 20840008 7 | 10620007 8 | 0043082a 9 | 10010003 10 | 00400820 11 | 00601020 12 | 00201820 13 | 00431022 14 | 08000003 15 | 00000000 -------------------------------------------------------------------------------- /assignment-1/benchtest/testzeroext/testzeroext.in: -------------------------------------------------------------------------------- 1 | addi $a0, $0, -1 2 | addi $a1, $0, 0 3 | addi $sp, $0, 32 4 | andi $a0, $a0, -1 5 | ori $a1, $a1, -1 6 | sw $a0, 0($sp) 7 | sw $a1, 8($sp) 8 | nop 9 | nop 10 | nop 11 | nop 12 | nop -------------------------------------------------------------------------------- /assignment-1/benchtest/quick multiply/quick multiply.mem: -------------------------------------------------------------------------------- 1 | 20080063 2 | 20090025 3 | 20100000 4 | 20040000 5 | 10090008 6 | 312a0001 7 | 100a0003 8 | 02088020 9 | ac900000 10 | 20840004 11 | 00084040 12 | 00094842 13 | 08000004 14 | 00000000 -------------------------------------------------------------------------------- /assignment-3(I)/benchtest/writeback/writeback.txt: -------------------------------------------------------------------------------- 1 | RAM[0] <= 32'h00002020; 2 | RAM[1] <= 32'h20060200; 3 | RAM[2] <= 32'h8c850000; 4 | RAM[3] <= 32'h20840008; 5 | RAM[4] <= 32'h14c4fffd; 6 | RAM[5] <= 32'h00000000; 7 | RAM[6] <= 32'h00000000; 8 | RAM[7] <= 32'h00000000; -------------------------------------------------------------------------------- /assignment-2/benchtest/gcd/gcd.mem: -------------------------------------------------------------------------------- 1 | 200200bd 2 | 2003011f 3 | 00002020 4 | ac820000 5 | ac830004 6 | 20840008 7 | 10620007 8 | 0043082a 9 | 10010003 10 | 00400820 11 | 00601020 12 | 00201820 13 | 00431022 14 | 08000003 15 | 00000000 16 | 00000000 17 | 00000000 18 | 00000000 -------------------------------------------------------------------------------- /assignment-3(I)/benchtest/random write/random write.mem: -------------------------------------------------------------------------------- 1 | 20080011 2 | 20090020 3 | 200b0010 4 | 20100000 5 | 200a0000 6 | 02088020 7 | 320c007f 8 | 000c6080 9 | ad880000 10 | 214a0001 11 | 156afffa 12 | 21080001 13 | 1528fff7 14 | 00000000 15 | 00000000 16 | 00000000 17 | -------------------------------------------------------------------------------- /assignment-2/benchtest/i-type/i-type.mem: -------------------------------------------------------------------------------- 1 | 20180771 2 | 2019f81c 3 | 2b11f81c 4 | ac110000 5 | 2b3107e4 6 | ac110004 7 | 3331ffff 8 | ac110008 9 | 33317fff 10 | ac11000c 11 | 3711fff8 12 | ac110010 13 | 373107e4 14 | ac110014 15 | 00000000 16 | 00000000 17 | 00000000 18 | 00000000 -------------------------------------------------------------------------------- /assignment-3(I)/benchtest/gcd/gcd.mem: -------------------------------------------------------------------------------- 1 | 200200bd 2 | 2003011f 3 | 00002020 4 | ac820000 5 | ac830004 6 | 20840008 7 | 10620007 8 | 0043082a 9 | 10010003 10 | 00400820 11 | 00601020 12 | 00201820 13 | 00431022 14 | 08000003 15 | 00000000 16 | 00000000 17 | 00000000 18 | 00000000 -------------------------------------------------------------------------------- /assignment-1/benchtest/bisection/bisection.mem: -------------------------------------------------------------------------------- 1 | 2002002c 2 | 20040000 3 | 2005001f 4 | 20100080 5 | 00853020 6 | 00063043 7 | ae060000 8 | 22100004 9 | 00063880 10 | 8ce30000 11 | 0062882a 12 | 14110003 13 | 10620004 14 | 00c02820 15 | 08000004 16 | 00c02020 17 | 08000004 18 | 00000000 -------------------------------------------------------------------------------- /assignment-2/benchtest/quick multiply/quick multiply.mem: -------------------------------------------------------------------------------- 1 | 20080063 2 | 20090025 3 | 20100000 4 | 20040000 5 | 10090008 6 | 312a0001 7 | 100a0003 8 | 02088020 9 | ac900000 10 | 20840004 11 | 00084040 12 | 00094842 13 | 08000004 14 | 00000000 15 | 00000000 16 | 00000000 17 | 00000000 -------------------------------------------------------------------------------- /assignment-3(I)/benchtest/i-type/i-type.mem: -------------------------------------------------------------------------------- 1 | 20180771 2 | 2019f81c 3 | 2b11f81c 4 | ac110000 5 | 2b3107e4 6 | ac110004 7 | 3331ffff 8 | ac110008 9 | 33317fff 10 | ac11000c 11 | 3711fff8 12 | ac110010 13 | 373107e4 14 | ac110014 15 | 00000000 16 | 00000000 17 | 00000000 18 | 00000000 -------------------------------------------------------------------------------- /assignment-3(I)/benchtest/quick multiply/quick multiply.mem: -------------------------------------------------------------------------------- 1 | 20080063 2 | 20090025 3 | 20100000 4 | 20040000 5 | 10090008 6 | 312a0001 7 | 100a0003 8 | 02088020 9 | ac900000 10 | 20840004 11 | 00084040 12 | 00094842 13 | 08000004 14 | 00000000 15 | 00000000 16 | 00000000 17 | 00000000 -------------------------------------------------------------------------------- /assignment-1/benchtest/bubble sort/bubble sort.mem: -------------------------------------------------------------------------------- 1 | 00004020 2 | 200b0080 3 | 0008e820 4 | 8fac0000 5 | 001d6820 6 | 8fae0000 7 | 01cc782a 8 | 140f0002 9 | 000e6020 10 | 03a06820 11 | 23bd0004 12 | 157dfff9 13 | 216bfffc 14 | 8d780000 15 | ad6c0000 16 | adb80000 17 | 1560fff1 18 | 00000000 -------------------------------------------------------------------------------- /assignment-1/makefile: -------------------------------------------------------------------------------- 1 | export VIVADO_PATH=/home/sunflower/Xilinx/Vivado/2019.2/bin/vivado 2 | PROJECT_DIR:=. 3 | SIM:=sim_1 4 | PROJECT_NAME:=project_1 5 | 6 | test: 7 | SIMULATION=${SIM} ${VIVADO_PATH} -mode tcl -source benchtest/run_simulation.tcl ${PROJECT_DIR}/${PROJECT_NAME}.xpr 8 | 9 | -------------------------------------------------------------------------------- /assignment-2/makefile: -------------------------------------------------------------------------------- 1 | export VIVADO_PATH=/home/sunflower/Xilinx/Vivado/2019.2/bin/vivado 2 | PROJECT_DIR:=. 3 | SIM:=sim_1 4 | PROJECT_NAME:=Pipeline 5 | 6 | test: 7 | SIMULATION=${SIM} ${VIVADO_PATH} -mode tcl -source benchtest/run_simulation.tcl ${PROJECT_DIR}/${PROJECT_NAME}.xpr 8 | 9 | -------------------------------------------------------------------------------- /assignment-1/benchtest/ad hoc/ad hoc.mem: -------------------------------------------------------------------------------- 1 | 20020005 2 | 2003000c 3 | 2067fff7 4 | 00e22025 5 | 00642824 6 | 00a42820 7 | 10a7000a 8 | 0064202a 9 | 10800001 10 | 20050000 11 | 00e2202a 12 | 00853820 13 | 00e23822 14 | ac670044 15 | 8c020050 16 | 08000011 17 | 20020001 18 | ac020054 19 | 00000000 -------------------------------------------------------------------------------- /assignment-3(I)/makefile: -------------------------------------------------------------------------------- 1 | export VIVADO_PATH=/home/sunflower/Xilinx/Vivado/2019.2/bin/vivado 2 | PROJECT_DIR:=. 3 | SIM:=sim_1 4 | PROJECT_NAME:=mips-cache 5 | 6 | test: 7 | SIMULATION=${SIM} ${VIVADO_PATH} -mode tcl -source benchtest/run_simulation.tcl ${PROJECT_DIR}/${PROJECT_NAME}.xpr 8 | 9 | -------------------------------------------------------------------------------- /assignment-2/benchtest/en & clear/en & clear.in: -------------------------------------------------------------------------------- 1 | addi $v0, $0, 5 2 | addi $v1, $0, 12 3 | addi $a3, $v1, -9 4 | or $a0, $a3, $v0 5 | and $a1, $v1, $a0 6 | add $a1, $a1, $a0 7 | bne $a1, $0, around # should be taken 8 | add $a1, $a1, $a0 9 | around: 10 | sw $a1, 4($0) 11 | nop 12 | nop 13 | nop 14 | nop -------------------------------------------------------------------------------- /assignment-3(I)/benchtest/en & clear/en & clear.in: -------------------------------------------------------------------------------- 1 | addi $v0, $0, 5 2 | addi $v1, $0, 12 3 | addi $a3, $v1, -9 4 | or $a0, $a3, $v0 5 | and $a1, $v1, $a0 6 | add $a1, $a1, $a0 7 | bne $a1, $0, around # should be taken 8 | add $a1, $a1, $a0 9 | around: 10 | sw $a1, 4($0) 11 | nop 12 | nop 13 | nop 14 | nop -------------------------------------------------------------------------------- /assignment-2/benchtest/bisection/bisection.mem: -------------------------------------------------------------------------------- 1 | 2002002c 2 | 20040000 3 | 2005001f 4 | 20100080 5 | 00853020 6 | 00063043 7 | ae060000 8 | 22100004 9 | 00063880 10 | 8ce30000 11 | 0062882a 12 | 14110003 13 | 10620004 14 | 00c02820 15 | 08000004 16 | 00c02020 17 | 08000004 18 | 00000000 19 | 00000000 20 | 00000000 21 | 00000000 -------------------------------------------------------------------------------- /assignment-3(I)/benchtest/bisection/bisection.mem: -------------------------------------------------------------------------------- 1 | 2002002c 2 | 20040000 3 | 2005001f 4 | 20100080 5 | 00853020 6 | 00063043 7 | ae060000 8 | 22100004 9 | 00063880 10 | 8ce30000 11 | 0062882a 12 | 14110003 13 | 10620004 14 | 00c02820 15 | 08000004 16 | 00c02020 17 | 08000004 18 | 00000000 19 | 00000000 20 | 00000000 21 | 00000000 -------------------------------------------------------------------------------- /assignment-2/benchtest/ad hoc/ad hoc.mem: -------------------------------------------------------------------------------- 1 | 20020005 2 | 2003000c 3 | 2067fff7 4 | 00e22025 5 | 00642824 6 | 00a42820 7 | 10a7000a 8 | 0064202a 9 | 10800001 10 | 20050000 11 | 00e2202a 12 | 00853820 13 | 00e23822 14 | ac670044 15 | 8c020050 16 | 08000011 17 | 20020001 18 | ac020054 19 | 00000000 20 | 00000000 21 | 00000000 22 | 00000000 -------------------------------------------------------------------------------- /assignment-2/benchtest/bubble sort/bubble sort.mem: -------------------------------------------------------------------------------- 1 | 00004020 2 | 200b0080 3 | 0008e820 4 | 8fac0000 5 | 001d6820 6 | 8fae0000 7 | 01cc782a 8 | 140f0002 9 | 000e6020 10 | 03a06820 11 | 23bd0004 12 | 157dfff9 13 | 216bfffc 14 | 8d780000 15 | ad6c0000 16 | adb80000 17 | 1560fff1 18 | 00000000 19 | 00000000 20 | 00000000 21 | 00000000 -------------------------------------------------------------------------------- /assignment-3(I)/benchtest/bubble sort/bubble sort.mem: -------------------------------------------------------------------------------- 1 | 00004020 2 | 200b0080 3 | 0008e820 4 | 8fac0000 5 | 001d6820 6 | 8fae0000 7 | 01cc782a 8 | 140f0002 9 | 000e6020 10 | 03a06820 11 | 23bd0004 12 | 157dfff9 13 | 216bfffc 14 | 8d780000 15 | ad6c0000 16 | adb80000 17 | 1560fff1 18 | 00000000 19 | 00000000 20 | 00000000 21 | 00000000 -------------------------------------------------------------------------------- /assignment-3(I)/benchtest/ad hoc/ad hoc.mem: -------------------------------------------------------------------------------- 1 | 20020005 2 | 2003000c 3 | 2067fff7 4 | 00e22025 5 | 00642824 6 | 00a42820 7 | 10a7000a 8 | 0064202a 9 | 10800001 10 | 20050000 11 | 00e2202a 12 | 00853820 13 | 00e23822 14 | ac670044 15 | 8c020050 16 | 08000011 17 | 20020001 18 | ac020054 19 | 00000000 20 | 00000000 21 | 00000000 22 | 00000000 -------------------------------------------------------------------------------- /assignment-1/benchtest/gcd/gcd.in: -------------------------------------------------------------------------------- 1 | addi $v0,$0,189 2 | addi $v1,$0,287 3 | add $a0, $0, $0 4 | main: 5 | sw $v0, 0($a0) 6 | sw $v1, 4($a0) 7 | addi $a0, $a0, 8 8 | beq $v0,$v1,end 9 | slt $at,$v0,$v1 10 | beq $at,$0,run 11 | add $at,$v0,$0 12 | add $v0,$v1,$0 13 | add $v1,$at,$0 14 | run: 15 | sub $v0,$v0,$v1 16 | j main 17 | end: 18 | nop -------------------------------------------------------------------------------- /assignment-1/benchtest/ad hoc/ad hoc.ans: -------------------------------------------------------------------------------- 1 | 00000048 2 | 00000000 3 | 00000000 4 | 00000000 5 | 00000000 6 | 00000000 7 | 00000000 8 | 00000000 9 | 00000000 10 | 00000000 11 | 00000000 12 | 00000000 13 | 00000000 14 | 00000000 15 | 00000000 16 | 00000000 17 | 00000000 18 | 00000000 19 | 00000000 20 | 00000000 21 | 00000000 22 | 00000007 23 | 00000007 -------------------------------------------------------------------------------- /assignment-2/benchtest/ad hoc/ad hoc.ans: -------------------------------------------------------------------------------- 1 | 00000054 2 | 00000000 3 | 00000000 4 | 00000000 5 | 00000000 6 | 00000000 7 | 00000000 8 | 00000000 9 | 00000000 10 | 00000000 11 | 00000000 12 | 00000000 13 | 00000000 14 | 00000000 15 | 00000000 16 | 00000000 17 | 00000000 18 | 00000000 19 | 00000000 20 | 00000000 21 | 00000000 22 | 00000007 23 | 00000007 -------------------------------------------------------------------------------- /assignment-3(I)/benchtest/ad hoc/ad hoc.ans: -------------------------------------------------------------------------------- 1 | 00000054 2 | 00000000 3 | 00000000 4 | 00000000 5 | 00000000 6 | 00000000 7 | 00000000 8 | 00000000 9 | 00000000 10 | 00000000 11 | 00000000 12 | 00000000 13 | 00000000 14 | 00000000 15 | 00000000 16 | 00000000 17 | 00000000 18 | 00000000 19 | 00000000 20 | 00000000 21 | 00000000 22 | 00000007 23 | 00000007 -------------------------------------------------------------------------------- /assignment-1/benchtest/quick multiply/quick multiply.in: -------------------------------------------------------------------------------- 1 | addi $t0, $0, 99 2 | addi $t1, $0, 37 3 | addi $s0, $0, 0 4 | addi $a0, $0, 0 5 | while: 6 | beq $t1, $0, done 7 | andi $t2, $t1, 1 8 | beq $t2, $0, target 9 | add $s0, $s0, $t0 10 | sw $s0, 0($a0) 11 | addi $a0, $a0, 4 12 | target: 13 | sll $t0, $t0, 1 14 | srl $t1, $t1, 1 15 | j while 16 | done: 17 | nop -------------------------------------------------------------------------------- /assignment-1/benchtest/testzeroext/testzeroext.txt: -------------------------------------------------------------------------------- 1 | RAM[0] <= 32'h2004ffff; 2 | RAM[1] <= 32'h20050000; 3 | RAM[2] <= 32'h201d0020; 4 | RAM[3] <= 32'h3084ffff; 5 | RAM[4] <= 32'h34a5ffff; 6 | RAM[5] <= 32'hafa40000; 7 | RAM[6] <= 32'hafa50008; 8 | RAM[7] <= 32'h00000000; 9 | RAM[8] <= 32'h00000000; 10 | RAM[9] <= 32'h00000000; 11 | RAM[10] <= 32'h00000000; 12 | -------------------------------------------------------------------------------- /assignment-2/benchtest/testjr/testjr.ans: -------------------------------------------------------------------------------- 1 | 000000fc 2 | 000000dc 3 | 000000f0 4 | 0000006c 5 | 000000ec 6 | 00000090 7 | 00000000 8 | 00000000 9 | 00000000 10 | 00000000 11 | 00000000 12 | 00000064 13 | 00000000 14 | 00000064 15 | 00000000 16 | 00000064 17 | 00000000 18 | 00000064 19 | 00000000 20 | 00000000 21 | 00000000 22 | 00000000 23 | 00000000 24 | 00000000 -------------------------------------------------------------------------------- /assignment-2/benchtest/gcd/gcd.in: -------------------------------------------------------------------------------- 1 | addi $v0,$0,189 2 | addi $v1,$0,287 3 | add $a0, $0, $0 4 | main: 5 | sw $v0, 0($a0) 6 | sw $v1, 4($a0) 7 | addi $a0, $a0, 8 8 | beq $v0,$v1,end 9 | slt $at,$v0,$v1 10 | beq $at,$0,run 11 | add $at,$v0,$0 12 | add $v0,$v1,$0 13 | add $v1,$at,$0 14 | run: 15 | sub $v0,$v0,$v1 16 | j main 17 | end: 18 | nop 19 | nop 20 | nop 21 | nop -------------------------------------------------------------------------------- /assignment-3(I)/benchtest/testjr/testjr.ans: -------------------------------------------------------------------------------- 1 | 000000fc 2 | 000000dc 3 | 000000f0 4 | 0000006c 5 | 000000ec 6 | 00000090 7 | 00000000 8 | 00000000 9 | 00000000 10 | 00000000 11 | 00000000 12 | 00000064 13 | 00000000 14 | 00000064 15 | 00000000 16 | 00000064 17 | 00000000 18 | 00000064 19 | 00000000 20 | 00000000 21 | 00000000 22 | 00000000 23 | 00000000 24 | 00000000 -------------------------------------------------------------------------------- /assignment-3(I)/benchtest/gcd/gcd.in: -------------------------------------------------------------------------------- 1 | addi $v0,$0,189 2 | addi $v1,$0,287 3 | add $a0, $0, $0 4 | main: 5 | sw $v0, 0($a0) 6 | sw $v1, 4($a0) 7 | addi $a0, $a0, 8 8 | beq $v0,$v1,end 9 | slt $at,$v0,$v1 10 | beq $at,$0,run 11 | add $at,$v0,$0 12 | add $v0,$v1,$0 13 | add $v1,$at,$0 14 | run: 15 | sub $v0,$v0,$v1 16 | j main 17 | end: 18 | nop 19 | nop 20 | nop 21 | nop -------------------------------------------------------------------------------- /assignment-2/benchtest/i-type/i-type.in: -------------------------------------------------------------------------------- 1 | addi $t8, $0, 1905 2 | addi $t9, $0, -2020 3 | slti $s1, $t8, -2020 4 | sw $s1, 0($0) 5 | slti $s1, $t9, 2020 6 | sw $s1, 4($0) 7 | andi $s1, $t9, -1 8 | sw $s1, 8($0) 9 | andi $s1, $t9, 32767 10 | sw $s1, 12($0) 11 | ori $s1, $t8, -8 12 | sw $s1, 16($0) 13 | ori $s1, $t9, 2020 14 | sw $s1, 20($0) 15 | nop 16 | nop 17 | nop 18 | nop 19 | -------------------------------------------------------------------------------- /assignment-1/benchtest/factorial/factorial.mem: -------------------------------------------------------------------------------- 1 | 201d0080 2 | 20040005 3 | 20050000 4 | 0c000007 5 | aca20000 6 | 00021040 7 | 00000000 8 | 23bdfff8 9 | afa40004 10 | afbf0000 11 | 20080002 12 | 0088402a 13 | 10080003 14 | 20020001 15 | 23bd0008 16 | 03e00008 17 | 2084ffff 18 | 0c000007 19 | 8fbf0000 20 | 8fa40004 21 | 23bd0008 22 | aca20000 23 | 00821020 24 | 20a50004 25 | 03e00008 -------------------------------------------------------------------------------- /assignment-3(I)/benchtest/i-type/i-type.in: -------------------------------------------------------------------------------- 1 | addi $t8, $0, 1905 2 | addi $t9, $0, -2020 3 | slti $s1, $t8, -2020 4 | sw $s1, 0($0) 5 | slti $s1, $t9, 2020 6 | sw $s1, 4($0) 7 | andi $s1, $t9, -1 8 | sw $s1, 8($0) 9 | andi $s1, $t9, 32767 10 | sw $s1, 12($0) 11 | ori $s1, $t8, -8 12 | sw $s1, 16($0) 13 | ori $s1, $t9, 2020 14 | sw $s1, 20($0) 15 | nop 16 | nop 17 | nop 18 | nop 19 | -------------------------------------------------------------------------------- /assignment-2/benchtest/quick multiply/quick multiply.in: -------------------------------------------------------------------------------- 1 | addi $t0, $0, 99 2 | addi $t1, $0, 37 3 | addi $s0, $0, 0 4 | addi $a0, $0, 0 5 | while: 6 | beq $t1, $0, done 7 | andi $t2, $t1, 1 8 | beq $t2, $0, target 9 | add $s0, $s0, $t0 10 | sw $s0, 0($a0) 11 | addi $a0, $a0, 4 12 | target: 13 | sll $t0, $t0, 1 14 | srl $t1, $t1, 1 15 | j while 16 | done: 17 | nop 18 | nop 19 | nop 20 | nop -------------------------------------------------------------------------------- /assignment-3(I)/benchtest/random write/random write.in: -------------------------------------------------------------------------------- 1 | addi $t0, $0, 17 2 | addi $t1, $0, 32 3 | addi $t3, $0, 16 4 | addi $s0, $0, 0 5 | For: 6 | addi $t2, $0, 0 7 | for: 8 | add $s0, $s0, $t0 9 | andi $t4, $s0, 127 10 | sll $t4, $t4, 2 11 | sw $t0, 0($t4) 12 | addi $t2, $t2, 1 13 | bne $t2, $t3, for 14 | addi $t0, $t0, 1 15 | bne $t0, $t1, For 16 | nop 17 | nop 18 | nop 19 | nop 20 | -------------------------------------------------------------------------------- /assignment-2/benchtest/en & clear/en & clear.txt: -------------------------------------------------------------------------------- 1 | RAM[0] <= 32'h20020005; 2 | RAM[1] <= 32'h2003000c; 3 | RAM[2] <= 32'h2067fff7; 4 | RAM[3] <= 32'h00e22025; 5 | RAM[4] <= 32'h00642824; 6 | RAM[5] <= 32'h00a42820; 7 | RAM[6] <= 32'h14050001; 8 | RAM[7] <= 32'h00a42820; 9 | RAM[8] <= 32'hac050004; 10 | RAM[9] <= 32'h00000000; 11 | RAM[10] <= 32'h00000000; 12 | RAM[11] <= 32'h00000000; 13 | -------------------------------------------------------------------------------- /assignment-3(I)/benchtest/en & clear/en & clear.txt: -------------------------------------------------------------------------------- 1 | RAM[0] <= 32'h20020005; 2 | RAM[1] <= 32'h2003000c; 3 | RAM[2] <= 32'h2067fff7; 4 | RAM[3] <= 32'h00e22025; 5 | RAM[4] <= 32'h00642824; 6 | RAM[5] <= 32'h00a42820; 7 | RAM[6] <= 32'h14050001; 8 | RAM[7] <= 32'h00a42820; 9 | RAM[8] <= 32'hac050004; 10 | RAM[9] <= 32'h00000000; 11 | RAM[10] <= 32'h00000000; 12 | RAM[11] <= 32'h00000000; 13 | -------------------------------------------------------------------------------- /assignment-3(I)/benchtest/quick multiply/quick multiply.in: -------------------------------------------------------------------------------- 1 | addi $t0, $0, 99 2 | addi $t1, $0, 37 3 | addi $s0, $0, 0 4 | addi $a0, $0, 0 5 | while: 6 | beq $t1, $0, done 7 | andi $t2, $t1, 1 8 | beq $t2, $0, target 9 | add $s0, $s0, $t0 10 | sw $s0, 0($a0) 11 | addi $a0, $a0, 4 12 | target: 13 | sll $t0, $t0, 1 14 | srl $t1, $t1, 1 15 | j while 16 | done: 17 | nop 18 | nop 19 | nop 20 | nop -------------------------------------------------------------------------------- /assignment-2/check.sh: -------------------------------------------------------------------------------- 1 | unzip -oq $1 2 | stuId=$(grep -o "^[0-9]*" <<< $1) 3 | if [ ! -d $stuId ]; then 4 | echo 解压缩文件中需要包一层 $stuId/ 文件夹 5 | else 6 | cd $stuId 7 | if [ ! -d Pipeline ]; then 8 | echo 项目名为 Pipeline 9 | else 10 | cd Pipeline 11 | if [ ! -f makefile ]; then 12 | echo 添加 makefile 13 | elif [ ! -d benchtest ]; then 14 | echo 添加 benchtest 15 | fi 16 | fi 17 | fi 18 | -------------------------------------------------------------------------------- /assignment-2/benchtest/testjr/testjr.run: -------------------------------------------------------------------------------- 1 | [0x00000040]=0x00000064 2 | [0x00000038]=0x00000064 3 | [0x00000000]=0x00000064 4 | [0x00000008]=0x0000006c 5 | [0x00000030]=0x00000064 6 | [0x00000010]=0x00000090 7 | [0x00000028]=0x00000064 8 | [0x00000000]=0x00000006 9 | [0x00000004]=0x0000000c 10 | [0x00000000]=0x000000dc 11 | [0x00000004]=0x000000f0 12 | [0x00000018]=0x00000000 13 | [0x0000000c]=0x000000ec -------------------------------------------------------------------------------- /assignment-3(I)/benchtest/testjr/testjr.run: -------------------------------------------------------------------------------- 1 | [0x00000040]=0x00000064 2 | [0x00000038]=0x00000064 3 | [0x00000000]=0x00000064 4 | [0x00000008]=0x0000006c 5 | [0x00000030]=0x00000064 6 | [0x00000010]=0x00000090 7 | [0x00000028]=0x00000064 8 | [0x00000000]=0x00000006 9 | [0x00000004]=0x0000000c 10 | [0x00000000]=0x000000dc 11 | [0x00000004]=0x000000f0 12 | [0x00000018]=0x00000000 13 | [0x0000000c]=0x000000ec -------------------------------------------------------------------------------- /assignment-3(I)/benchtest/writeback/writeback.out: -------------------------------------------------------------------------------- 1 | 0x0 : add $a0, $0, $0 | 00002020 2 | 0x4 : addi $a2, $0, 512 | 20060200 3 | 0x8 : start: | 4 | 0x8 : lw $a1, 0($a0) | 8c850000 5 | 0xc : addi $a0, $a0, 8 | 20840008 6 | 0x10 : bne $a0, $a2, start | 14c4fffd 7 | 0x14 : nop | 00000000 8 | 0x18 : nop | 00000000 9 | 0x1c : nop | 00000000 -------------------------------------------------------------------------------- /assignment-1/benchtest/bisection/bisection.in: -------------------------------------------------------------------------------- 1 | addi $v0, $0, 44 2 | addi $a0, $0, 0 3 | addi $a1, $0, 31 4 | addi $s0, $0, 128 5 | mid: 6 | add $a2, $a0, $a1 7 | sra $a2, $a2, 1 8 | sw $a2, 0($s0) 9 | addi $s0, $s0, 4 10 | sll $a3, $a2, 2 11 | lw $v1, 0($a3) 12 | slt $s1, $v1, $v0 13 | bne $s1, $0, less 14 | beq $v0, $v1, exit 15 | add $a1, $a2, $0 16 | j mid 17 | less: 18 | add $a0, $a2, $0 19 | j mid 20 | exit: 21 | nop -------------------------------------------------------------------------------- /assignment-2/benchtest/factorial/factorial.mem: -------------------------------------------------------------------------------- 1 | 201d0080 2 | 20040005 3 | 20050000 4 | 0c00000a 5 | aca20000 6 | 00021040 7 | 00000000 8 | 00000000 9 | 00000000 10 | 00000000 11 | 23bdfff8 12 | afa40004 13 | afbf0000 14 | 20080002 15 | 0088402a 16 | 10080003 17 | 20020001 18 | 23bd0008 19 | 03e00008 20 | 2084ffff 21 | 0c00000a 22 | 8fbf0000 23 | 8fa40004 24 | 23bd0008 25 | aca20000 26 | 00821020 27 | 20a50004 28 | 03e00008 -------------------------------------------------------------------------------- /assignment-3(I)/benchtest/factorial/factorial.mem: -------------------------------------------------------------------------------- 1 | 201d0080 2 | 20040005 3 | 20050000 4 | 0c00000a 5 | aca20000 6 | 00021040 7 | 00000000 8 | 00000000 9 | 00000000 10 | 00000000 11 | 23bdfff8 12 | afa40004 13 | afbf0000 14 | 20080002 15 | 0088402a 16 | 10080003 17 | 20020001 18 | 23bd0008 19 | 03e00008 20 | 2084ffff 21 | 0c00000a 22 | 8fbf0000 23 | 8fa40004 24 | 23bd0008 25 | aca20000 26 | 00821020 27 | 20a50004 28 | 03e00008 -------------------------------------------------------------------------------- /assignment-1/benchtest/run_simulation.tcl: -------------------------------------------------------------------------------- 1 | update_compile_order -fileset sources_1 2 | 3 | set simulations [get_fileset $env(SIMULATION)] 4 | 5 | if { [llength simulations] != 0} { 6 | foreach sim $simulations { 7 | update_compile_order -fileset $sim 8 | launch_simulation -simset $sim 9 | # make simulation complete 10 | run all 11 | } 12 | } 13 | 14 | exit 15 | -------------------------------------------------------------------------------- /assignment-2/benchtest/run_simulation.tcl: -------------------------------------------------------------------------------- 1 | update_compile_order -fileset sources_1 2 | 3 | set simulations [get_fileset $env(SIMULATION)] 4 | 5 | if { [llength simulations] != 0} { 6 | foreach sim $simulations { 7 | update_compile_order -fileset $sim 8 | launch_simulation -simset $sim 9 | # make simulation complete 10 | run all 11 | } 12 | } 13 | 14 | exit 15 | -------------------------------------------------------------------------------- /assignment-3(I)/benchtest/run_simulation.tcl: -------------------------------------------------------------------------------- 1 | update_compile_order -fileset sources_1 2 | 3 | set simulations [get_fileset $env(SIMULATION)] 4 | 5 | if { [llength simulations] != 0} { 6 | foreach sim $simulations { 7 | update_compile_order -fileset $sim 8 | launch_simulation -simset $sim 9 | # make simulation complete 10 | run all 11 | } 12 | } 13 | 14 | exit 15 | -------------------------------------------------------------------------------- /assignment-1/benchtest/bubble sort/bubble sort.in: -------------------------------------------------------------------------------- 1 | add $t0, $0, $0 2 | addi $t3, $0, 128 3 | For: 4 | add $sp, $0, $t0 5 | lw $t4, 0($sp) 6 | add $t5, $0, $sp 7 | for: 8 | lw $t6, 0($sp) 9 | slt $t7, $t6, $t4 10 | bne $t7, $0, ret 11 | add $t4, $0, $t6 12 | add $t5, $sp, $0 13 | ret: 14 | addi $sp, $sp, 4 15 | bne $sp, $t3, for 16 | addi $t3, $t3, -4 17 | lw $t8, 0($t3) 18 | sw $t4, 0($t3) 19 | sw $t8, 0($t5) 20 | bne $0, $t3, For 21 | nop -------------------------------------------------------------------------------- /assignment-1/benchtest/quick multiply/quick multiply.txt: -------------------------------------------------------------------------------- 1 | RAM[0] <= 32'h20080063; 2 | RAM[1] <= 32'h20090025; 3 | RAM[2] <= 32'h20100000; 4 | RAM[3] <= 32'h20040000; 5 | RAM[4] <= 32'h10090008; 6 | RAM[5] <= 32'h312a0001; 7 | RAM[6] <= 32'h100a0003; 8 | RAM[7] <= 32'h02088020; 9 | RAM[8] <= 32'hac900000; 10 | RAM[9] <= 32'h20840004; 11 | RAM[10] <= 32'h00084040; 12 | RAM[11] <= 32'h00094842; 13 | RAM[12] <= 32'h08000004; 14 | RAM[13] <= 32'h00000000; -------------------------------------------------------------------------------- /assignment-2/benchtest/bisection/bisection.in: -------------------------------------------------------------------------------- 1 | addi $v0, $0, 44 2 | addi $a0, $0, 0 3 | addi $a1, $0, 31 4 | addi $s0, $0, 128 5 | mid: 6 | add $a2, $a0, $a1 7 | sra $a2, $a2, 1 8 | sw $a2, 0($s0) 9 | addi $s0, $s0, 4 10 | sll $a3, $a2, 2 11 | lw $v1, 0($a3) 12 | slt $s1, $v1, $v0 13 | bne $s1, $0, less 14 | beq $v0, $v1, exit 15 | add $a1, $a2, $0 16 | j mid 17 | less: 18 | add $a0, $a2, $0 19 | j mid 20 | exit: 21 | nop 22 | nop 23 | nop 24 | nop -------------------------------------------------------------------------------- /assignment-3(I)/benchtest/bisection/bisection.in: -------------------------------------------------------------------------------- 1 | addi $v0, $0, 44 2 | addi $a0, $0, 0 3 | addi $a1, $0, 31 4 | addi $s0, $0, 128 5 | mid: 6 | add $a2, $a0, $a1 7 | sra $a2, $a2, 1 8 | sw $a2, 0($s0) 9 | addi $s0, $s0, 4 10 | sll $a3, $a2, 2 11 | lw $v1, 0($a3) 12 | slt $s1, $v1, $v0 13 | bne $s1, $0, less 14 | beq $v0, $v1, exit 15 | add $a1, $a2, $0 16 | j mid 17 | less: 18 | add $a0, $a2, $0 19 | j mid 20 | exit: 21 | nop 22 | nop 23 | nop 24 | nop -------------------------------------------------------------------------------- /assignment-1/benchtest/ad hoc/ad hoc.in: -------------------------------------------------------------------------------- 1 | main: 2 | addi $v0, $0, 5 3 | addi $v1, $0, 12 4 | addi $a3, $v1, -9 5 | or $a0, $a3, $v0 6 | and $a1, $v1, $a0 7 | add $a1, $a1, $a0 8 | beq $a3, $a1, end 9 | slt $a0, $v1, $a0 10 | beq $0, $a0, around 11 | addi $a1, $0, 0 12 | around: 13 | slt $a0, $a3, $v0 14 | add $a3, $a0, $a1 15 | sub $a3, $a3, $v0 16 | sw $a3, 68($v1) 17 | lw $v0, 80($0) 18 | j end 19 | addi $v0, $0, 1 20 | end: 21 | sw $v0, 84($0) 22 | nop -------------------------------------------------------------------------------- /assignment-1/benchtest/gcd/gcd.txt: -------------------------------------------------------------------------------- 1 | RAM[0] <= 32'h200200bd; 2 | RAM[1] <= 32'h2003011f; 3 | RAM[2] <= 32'h00002020; 4 | RAM[3] <= 32'hac820000; 5 | RAM[4] <= 32'hac830004; 6 | RAM[5] <= 32'h20840008; 7 | RAM[6] <= 32'h10620007; 8 | RAM[7] <= 32'h0043082a; 9 | RAM[8] <= 32'h10010003; 10 | RAM[9] <= 32'h00400820; 11 | RAM[10] <= 32'h00601020; 12 | RAM[11] <= 32'h00201820; 13 | RAM[12] <= 32'h00431022; 14 | RAM[13] <= 32'h08000003; 15 | RAM[14] <= 32'h00000000; -------------------------------------------------------------------------------- /assignment-1/benchtest/factorial/factorial.run: -------------------------------------------------------------------------------- 1 | [0x0000007c]=0x00000005 2 | [0x00000078]=0x00000010 3 | [0x00000074]=0x00000004 4 | [0x00000070]=0x00000048 5 | [0x0000006c]=0x00000003 6 | [0x00000068]=0x00000048 7 | [0x00000064]=0x00000002 8 | [0x00000060]=0x00000048 9 | [0x0000005c]=0x00000001 10 | [0x00000058]=0x00000048 11 | [0x00000000]=0x00000001 12 | [0x00000004]=0x00000003 13 | [0x00000008]=0x00000006 14 | [0x0000000c]=0x0000000a 15 | [0x00000010]=0x0000000f -------------------------------------------------------------------------------- /assignment-2/benchtest/bubble sort/bubble sort.in: -------------------------------------------------------------------------------- 1 | add $t0, $0, $0 2 | addi $t3, $0, 128 3 | For: 4 | add $sp, $0, $t0 5 | lw $t4, 0($sp) 6 | add $t5, $0, $sp 7 | for: 8 | lw $t6, 0($sp) 9 | slt $t7, $t6, $t4 10 | bne $t7, $0, ret 11 | add $t4, $0, $t6 12 | add $t5, $sp, $0 13 | ret: 14 | addi $sp, $sp, 4 15 | bne $sp, $t3, for 16 | addi $t3, $t3, -4 17 | lw $t8, 0($t3) 18 | sw $t4, 0($t3) 19 | sw $t8, 0($t5) 20 | bne $0, $t3, For 21 | nop 22 | nop 23 | nop 24 | nop -------------------------------------------------------------------------------- /assignment-2/benchtest/factorial/factorial.run: -------------------------------------------------------------------------------- 1 | [0x0000007c]=0x00000005 2 | [0x00000078]=0x00000010 3 | [0x00000074]=0x00000004 4 | [0x00000070]=0x00000054 5 | [0x0000006c]=0x00000003 6 | [0x00000068]=0x00000054 7 | [0x00000064]=0x00000002 8 | [0x00000060]=0x00000054 9 | [0x0000005c]=0x00000001 10 | [0x00000058]=0x00000054 11 | [0x00000000]=0x00000001 12 | [0x00000004]=0x00000003 13 | [0x00000008]=0x00000006 14 | [0x0000000c]=0x0000000a 15 | [0x00000010]=0x0000000f -------------------------------------------------------------------------------- /assignment-3(I)/benchtest/bubble sort/bubble sort.in: -------------------------------------------------------------------------------- 1 | add $t0, $0, $0 2 | addi $t3, $0, 128 3 | For: 4 | add $sp, $0, $t0 5 | lw $t4, 0($sp) 6 | add $t5, $0, $sp 7 | for: 8 | lw $t6, 0($sp) 9 | slt $t7, $t6, $t4 10 | bne $t7, $0, ret 11 | add $t4, $0, $t6 12 | add $t5, $sp, $0 13 | ret: 14 | addi $sp, $sp, 4 15 | bne $sp, $t3, for 16 | addi $t3, $t3, -4 17 | lw $t8, 0($t3) 18 | sw $t4, 0($t3) 19 | sw $t8, 0($t5) 20 | bne $0, $t3, For 21 | nop 22 | nop 23 | nop 24 | nop -------------------------------------------------------------------------------- /assignment-3(I)/benchtest/factorial/factorial.run: -------------------------------------------------------------------------------- 1 | [0x0000007c]=0x00000005 2 | [0x00000078]=0x00000010 3 | [0x00000074]=0x00000004 4 | [0x00000070]=0x00000054 5 | [0x0000006c]=0x00000003 6 | [0x00000068]=0x00000054 7 | [0x00000064]=0x00000002 8 | [0x00000060]=0x00000054 9 | [0x0000005c]=0x00000001 10 | [0x00000058]=0x00000054 11 | [0x00000000]=0x00000001 12 | [0x00000004]=0x00000003 13 | [0x00000008]=0x00000006 14 | [0x0000000c]=0x0000000a 15 | [0x00000010]=0x0000000f -------------------------------------------------------------------------------- /assignment-1/benchtest/bisection/bisection.data: -------------------------------------------------------------------------------- 1 | 00000001 2 | 00000002 3 | 00000007 4 | 00000007 5 | 00000008 6 | 00000009 7 | 0000000d 8 | 00000012 9 | 00000019 10 | 0000001b 11 | 0000001c 12 | 0000001d 13 | 0000001f 14 | 00000024 15 | 00000026 16 | 00000027 17 | 00000028 18 | 0000002c 19 | 00000030 20 | 00000034 21 | 0000003e 22 | 00000042 23 | 00000044 24 | 00000046 25 | 00000049 26 | 0000004a 27 | 0000004a 28 | 0000004b 29 | 0000004b 30 | 00000051 31 | 00000052 32 | 0000005f -------------------------------------------------------------------------------- /assignment-1/benchtest/gcd/gcd.ans: -------------------------------------------------------------------------------- 1 | 00000038 2 | 000000bd 3 | 0000011f 4 | 00000062 5 | 000000bd 6 | 0000005b 7 | 00000062 8 | 00000007 9 | 0000005b 10 | 00000054 11 | 00000007 12 | 0000004d 13 | 00000007 14 | 00000046 15 | 00000007 16 | 0000003f 17 | 00000007 18 | 00000038 19 | 00000007 20 | 00000031 21 | 00000007 22 | 0000002a 23 | 00000007 24 | 00000023 25 | 00000007 26 | 0000001c 27 | 00000007 28 | 00000015 29 | 00000007 30 | 0000000e 31 | 00000007 32 | 00000007 33 | 00000007 -------------------------------------------------------------------------------- /assignment-2/benchtest/ad hoc/ad hoc.in: -------------------------------------------------------------------------------- 1 | main: 2 | addi $v0, $0, 5 3 | addi $v1, $0, 12 4 | addi $a3, $v1, -9 5 | or $a0, $a3, $v0 6 | and $a1, $v1, $a0 7 | add $a1, $a1, $a0 8 | beq $a3, $a1, end 9 | slt $a0, $v1, $a0 10 | beq $0, $a0, around 11 | addi $a1, $0, 0 12 | around: 13 | slt $a0, $a3, $v0 14 | add $a3, $a0, $a1 15 | sub $a3, $a3, $v0 16 | sw $a3, 68($v1) 17 | lw $v0, 80($0) 18 | j end 19 | addi $v0, $0, 1 20 | end: 21 | sw $v0, 84($0) 22 | nop 23 | nop 24 | nop 25 | nop -------------------------------------------------------------------------------- /assignment-2/benchtest/bisection/bisection.data: -------------------------------------------------------------------------------- 1 | 00000001 2 | 00000002 3 | 00000007 4 | 00000007 5 | 00000008 6 | 00000009 7 | 0000000d 8 | 00000012 9 | 00000019 10 | 0000001b 11 | 0000001c 12 | 0000001d 13 | 0000001f 14 | 00000024 15 | 00000026 16 | 00000027 17 | 00000028 18 | 0000002c 19 | 00000030 20 | 00000034 21 | 0000003e 22 | 00000042 23 | 00000044 24 | 00000046 25 | 00000049 26 | 0000004a 27 | 0000004a 28 | 0000004b 29 | 0000004b 30 | 00000051 31 | 00000052 32 | 0000005f -------------------------------------------------------------------------------- /assignment-2/benchtest/gcd/gcd.ans: -------------------------------------------------------------------------------- 1 | 00000044 2 | 000000bd 3 | 0000011f 4 | 00000062 5 | 000000bd 6 | 0000005b 7 | 00000062 8 | 00000007 9 | 0000005b 10 | 00000054 11 | 00000007 12 | 0000004d 13 | 00000007 14 | 00000046 15 | 00000007 16 | 0000003f 17 | 00000007 18 | 00000038 19 | 00000007 20 | 00000031 21 | 00000007 22 | 0000002a 23 | 00000007 24 | 00000023 25 | 00000007 26 | 0000001c 27 | 00000007 28 | 00000015 29 | 00000007 30 | 0000000e 31 | 00000007 32 | 00000007 33 | 00000007 -------------------------------------------------------------------------------- /assignment-2/benchtest/mutual recursion/mutual recursion.run: -------------------------------------------------------------------------------- 1 | [0x00000000]=0x00000066 2 | [0x00000004]=0x00000067 3 | [0x00000008]=0x00000066 4 | [0x0000000c]=0x00000067 5 | [0x00000010]=0x00000061 6 | [0x0000007c]=0x00000000 7 | [0x00000078]=0x00000038 8 | [0x00000074]=0x00000001 9 | [0x00000070]=0x00000084 10 | [0x0000006c]=0x00000002 11 | [0x00000068]=0x000000c4 12 | [0x00000064]=0x00000003 13 | [0x00000060]=0x00000084 14 | [0x0000005c]=0x00000004 15 | [0x00000058]=0x000000c4 -------------------------------------------------------------------------------- /assignment-3(I)/benchtest/bisection/bisection.data: -------------------------------------------------------------------------------- 1 | 00000001 2 | 00000002 3 | 00000007 4 | 00000007 5 | 00000008 6 | 00000009 7 | 0000000d 8 | 00000012 9 | 00000019 10 | 0000001b 11 | 0000001c 12 | 0000001d 13 | 0000001f 14 | 00000024 15 | 00000026 16 | 00000027 17 | 00000028 18 | 0000002c 19 | 00000030 20 | 00000034 21 | 0000003e 22 | 00000042 23 | 00000044 24 | 00000046 25 | 00000049 26 | 0000004a 27 | 0000004a 28 | 0000004b 29 | 0000004b 30 | 00000051 31 | 00000052 32 | 0000005f -------------------------------------------------------------------------------- /assignment-3(I)/benchtest/mutual recursion/mutual recursion.run: -------------------------------------------------------------------------------- 1 | [0x00000000]=0x00000066 2 | [0x00000004]=0x00000067 3 | [0x00000008]=0x00000066 4 | [0x0000000c]=0x00000067 5 | [0x00000010]=0x00000061 6 | [0x0000007c]=0x00000000 7 | [0x00000078]=0x00000038 8 | [0x00000074]=0x00000001 9 | [0x00000070]=0x00000084 10 | [0x0000006c]=0x00000002 11 | [0x00000068]=0x000000c4 12 | [0x00000064]=0x00000003 13 | [0x00000060]=0x00000084 14 | [0x0000005c]=0x00000004 15 | [0x00000058]=0x000000c4 -------------------------------------------------------------------------------- /assignment-3(I)/src/cache.vh: -------------------------------------------------------------------------------- 1 | `ifndef CACHE_VH 2 | `define CACHE_VH 3 | 4 | `timescale 1ns / 1ps 5 | 6 | `define ADDR_WIDTH 32 7 | 8 | // tag bits 9 | `define CACHE_T 26 10 | // set index bits 11 | `define CACHE_S 2 12 | // block offset bits 13 | `define CACHE_B 4 14 | // The sum of above bits should be 32 (ADDR_WIDTH) 15 | 16 | // number of lines per set 17 | `define CACHE_E 4 18 | 19 | `define SET_NUM 2**`CACHE_S 20 | `define BLOCK_SIZE 2**`CACHE_B 21 | 22 | `endif 23 | -------------------------------------------------------------------------------- /assignment-1/benchtest/bubble sort/bubble sort.data: -------------------------------------------------------------------------------- 1 | 00000007 2 | 00000034 3 | 0000005f 4 | 00000052 5 | 0000004a 6 | 00000042 7 | 00000001 8 | 0000001b 9 | 00000051 10 | 00000009 11 | 00000002 12 | 0000001c 13 | 0000001f 14 | 00000049 15 | 0000001d 16 | 00000027 17 | 00000046 18 | 00000044 19 | 00000019 20 | 0000002c 21 | 0000004b 22 | 00000030 23 | 0000004b 24 | 00000007 25 | 00000028 26 | 0000003e 27 | 00000012 28 | 0000000d 29 | 00000008 30 | 00000024 31 | 00000026 32 | 0000004a -------------------------------------------------------------------------------- /assignment-2/benchtest/bubble sort/bubble sort.data: -------------------------------------------------------------------------------- 1 | 00000007 2 | 00000034 3 | 0000005f 4 | 00000052 5 | 0000004a 6 | 00000042 7 | 00000001 8 | 0000001b 9 | 00000051 10 | 00000009 11 | 00000002 12 | 0000001c 13 | 0000001f 14 | 00000049 15 | 0000001d 16 | 00000027 17 | 00000046 18 | 00000044 19 | 00000019 20 | 0000002c 21 | 0000004b 22 | 00000030 23 | 0000004b 24 | 00000007 25 | 00000028 26 | 0000003e 27 | 00000012 28 | 0000000d 29 | 00000008 30 | 00000024 31 | 00000026 32 | 0000004a -------------------------------------------------------------------------------- /assignment-3(I)/benchtest/ad hoc/ad hoc.in: -------------------------------------------------------------------------------- 1 | main: 2 | addi $v0, $0, 5 3 | addi $v1, $0, 12 4 | addi $a3, $v1, -9 5 | or $a0, $a3, $v0 6 | and $a1, $v1, $a0 7 | add $a1, $a1, $a0 8 | beq $a3, $a1, end 9 | slt $a0, $v1, $a0 10 | beq $0, $a0, around 11 | addi $a1, $0, 0 12 | around: 13 | slt $a0, $a3, $v0 14 | add $a3, $a0, $a1 15 | sub $a3, $a3, $v0 16 | sw $a3, 68($v1) 17 | lw $v0, 80($0) 18 | j end 19 | addi $v0, $0, 1 20 | end: 21 | sw $v0, 84($0) 22 | nop 23 | nop 24 | nop 25 | nop -------------------------------------------------------------------------------- /assignment-3(I)/benchtest/bubble sort/bubble sort.data: -------------------------------------------------------------------------------- 1 | 00000007 2 | 00000034 3 | 0000005f 4 | 00000052 5 | 0000004a 6 | 00000042 7 | 00000001 8 | 0000001b 9 | 00000051 10 | 00000009 11 | 00000002 12 | 0000001c 13 | 0000001f 14 | 00000049 15 | 0000001d 16 | 00000027 17 | 00000046 18 | 00000044 19 | 00000019 20 | 0000002c 21 | 0000004b 22 | 00000030 23 | 0000004b 24 | 00000007 25 | 00000028 26 | 0000003e 27 | 00000012 28 | 0000000d 29 | 00000008 30 | 00000024 31 | 00000026 32 | 0000004a -------------------------------------------------------------------------------- /assignment-3(I)/benchtest/gcd/gcd.ans: -------------------------------------------------------------------------------- 1 | 00000044 2 | 000000bd 3 | 0000011f 4 | 00000062 5 | 000000bd 6 | 0000005b 7 | 00000062 8 | 00000007 9 | 0000005b 10 | 00000054 11 | 00000007 12 | 0000004d 13 | 00000007 14 | 00000046 15 | 00000007 16 | 0000003f 17 | 00000007 18 | 00000038 19 | 00000007 20 | 00000031 21 | 00000007 22 | 0000002a 23 | 00000007 24 | 00000023 25 | 00000007 26 | 0000001c 27 | 00000007 28 | 00000015 29 | 00000007 30 | 0000000e 31 | 00000007 32 | 00000007 33 | 00000007 -------------------------------------------------------------------------------- /assignment-1/benchtest/bubble sort/bubble sort.ans: -------------------------------------------------------------------------------- 1 | 00000044 2 | 00000001 3 | 00000002 4 | 00000007 5 | 00000007 6 | 00000008 7 | 00000009 8 | 0000000d 9 | 00000012 10 | 00000019 11 | 0000001b 12 | 0000001c 13 | 0000001d 14 | 0000001f 15 | 00000024 16 | 00000026 17 | 00000027 18 | 00000028 19 | 0000002c 20 | 00000030 21 | 00000034 22 | 0000003e 23 | 00000042 24 | 00000044 25 | 00000046 26 | 00000049 27 | 0000004a 28 | 0000004a 29 | 0000004b 30 | 0000004b 31 | 00000051 32 | 00000052 33 | 0000005f -------------------------------------------------------------------------------- /assignment-2/benchtest/bubble sort/bubble sort.ans: -------------------------------------------------------------------------------- 1 | 00000050 2 | 00000001 3 | 00000002 4 | 00000007 5 | 00000007 6 | 00000008 7 | 00000009 8 | 0000000d 9 | 00000012 10 | 00000019 11 | 0000001b 12 | 0000001c 13 | 0000001d 14 | 0000001f 15 | 00000024 16 | 00000026 17 | 00000027 18 | 00000028 19 | 0000002c 20 | 00000030 21 | 00000034 22 | 0000003e 23 | 00000042 24 | 00000044 25 | 00000046 26 | 00000049 27 | 0000004a 28 | 0000004a 29 | 0000004b 30 | 0000004b 31 | 00000051 32 | 00000052 33 | 0000005f -------------------------------------------------------------------------------- /assignment-1/benchtest/factorial/factorial.ans: -------------------------------------------------------------------------------- 1 | 00000018 2 | 00000001 3 | 00000003 4 | 00000006 5 | 0000000a 6 | 0000000f 7 | 00000000 8 | 00000000 9 | 00000000 10 | 00000000 11 | 00000000 12 | 00000000 13 | 00000000 14 | 00000000 15 | 00000000 16 | 00000000 17 | 00000000 18 | 00000000 19 | 00000000 20 | 00000000 21 | 00000000 22 | 00000000 23 | 00000000 24 | 00000048 25 | 00000001 26 | 00000048 27 | 00000002 28 | 00000048 29 | 00000003 30 | 00000048 31 | 00000004 32 | 00000010 33 | 00000005 34 | -------------------------------------------------------------------------------- /assignment-2/benchtest/factorial/factorial.ans: -------------------------------------------------------------------------------- 1 | 00000024 2 | 00000001 3 | 00000003 4 | 00000006 5 | 0000000a 6 | 0000000f 7 | 00000000 8 | 00000000 9 | 00000000 10 | 00000000 11 | 00000000 12 | 00000000 13 | 00000000 14 | 00000000 15 | 00000000 16 | 00000000 17 | 00000000 18 | 00000000 19 | 00000000 20 | 00000000 21 | 00000000 22 | 00000000 23 | 00000000 24 | 00000054 25 | 00000001 26 | 00000054 27 | 00000002 28 | 00000054 29 | 00000003 30 | 00000054 31 | 00000004 32 | 00000010 33 | 00000005 34 | -------------------------------------------------------------------------------- /assignment-3(I)/benchtest/bubble sort/bubble sort.ans: -------------------------------------------------------------------------------- 1 | 00000050 2 | 00000001 3 | 00000002 4 | 00000007 5 | 00000007 6 | 00000008 7 | 00000009 8 | 0000000d 9 | 00000012 10 | 00000019 11 | 0000001b 12 | 0000001c 13 | 0000001d 14 | 0000001f 15 | 00000024 16 | 00000026 17 | 00000027 18 | 00000028 19 | 0000002c 20 | 00000030 21 | 00000034 22 | 0000003e 23 | 00000042 24 | 00000044 25 | 00000046 26 | 00000049 27 | 0000004a 28 | 0000004a 29 | 0000004b 30 | 0000004b 31 | 00000051 32 | 00000052 33 | 0000005f -------------------------------------------------------------------------------- /assignment-3(I)/benchtest/factorial/factorial.ans: -------------------------------------------------------------------------------- 1 | 00000024 2 | 00000001 3 | 00000003 4 | 00000006 5 | 0000000a 6 | 0000000f 7 | 00000000 8 | 00000000 9 | 00000000 10 | 00000000 11 | 00000000 12 | 00000000 13 | 00000000 14 | 00000000 15 | 00000000 16 | 00000000 17 | 00000000 18 | 00000000 19 | 00000000 20 | 00000000 21 | 00000000 22 | 00000000 23 | 00000000 24 | 00000054 25 | 00000001 26 | 00000054 27 | 00000002 28 | 00000054 29 | 00000003 30 | 00000054 31 | 00000004 32 | 00000010 33 | 00000005 34 | -------------------------------------------------------------------------------- /assignment-2/benchtest/mutual recursion/mutual recursion.ans: -------------------------------------------------------------------------------- 1 | 00000048 2 | 00000066 3 | 00000067 4 | 00000066 5 | 00000067 6 | 00000061 7 | 00000000 8 | 00000000 9 | 00000000 10 | 00000000 11 | 00000000 12 | 00000000 13 | 00000000 14 | 00000000 15 | 00000000 16 | 00000000 17 | 00000000 18 | 00000000 19 | 00000000 20 | 00000000 21 | 00000000 22 | 00000000 23 | 00000000 24 | 000000c4 25 | 00000004 26 | 00000084 27 | 00000003 28 | 000000c4 29 | 00000002 30 | 00000084 31 | 00000001 32 | 00000038 33 | 00000000 34 | 00000000 -------------------------------------------------------------------------------- /assignment-3(I)/benchtest/mutual recursion/mutual recursion.ans: -------------------------------------------------------------------------------- 1 | 00000048 2 | 00000066 3 | 00000067 4 | 00000066 5 | 00000067 6 | 00000061 7 | 00000000 8 | 00000000 9 | 00000000 10 | 00000000 11 | 00000000 12 | 00000000 13 | 00000000 14 | 00000000 15 | 00000000 16 | 00000000 17 | 00000000 18 | 00000000 19 | 00000000 20 | 00000000 21 | 00000000 22 | 00000000 23 | 00000000 24 | 000000c4 25 | 00000004 26 | 00000084 27 | 00000003 28 | 000000c4 29 | 00000002 30 | 00000084 31 | 00000001 32 | 00000038 33 | 00000000 34 | 00000000 -------------------------------------------------------------------------------- /assignment-3(I)/benchtest/random write/random write.txt: -------------------------------------------------------------------------------- 1 | RAM[0] <= 32'h20080011; 2 | RAM[1] <= 32'h20090020; 3 | RAM[2] <= 32'h200b0010; 4 | RAM[3] <= 32'h20100000; 5 | RAM[4] <= 32'h200a0000; 6 | RAM[5] <= 32'h02088020; 7 | RAM[6] <= 32'h320c007f; 8 | RAM[7] <= 32'h000c6080; 9 | RAM[8] <= 32'had880000; 10 | RAM[9] <= 32'h214a0001; 11 | RAM[10] <= 32'h156afffa; 12 | RAM[11] <= 32'h21080001; 13 | RAM[12] <= 32'h1528fff7; 14 | RAM[13] <= 32'h00000000; 15 | RAM[14] <= 32'h00000000; 16 | RAM[15] <= 32'h00000000; 17 | -------------------------------------------------------------------------------- /assignment-2/benchtest/quick multiply/quick multiply.txt: -------------------------------------------------------------------------------- 1 | RAM[0] <= 32'h20080063; 2 | RAM[1] <= 32'h20090025; 3 | RAM[2] <= 32'h20100000; 4 | RAM[3] <= 32'h20040000; 5 | RAM[4] <= 32'h10090008; 6 | RAM[5] <= 32'h312a0001; 7 | RAM[6] <= 32'h100a0003; 8 | RAM[7] <= 32'h02088020; 9 | RAM[8] <= 32'hac900000; 10 | RAM[9] <= 32'h20840004; 11 | RAM[10] <= 32'h00084040; 12 | RAM[11] <= 32'h00094842; 13 | RAM[12] <= 32'h08000004; 14 | RAM[13] <= 32'h00000000; 15 | RAM[14] <= 32'h00000000; 16 | RAM[15] <= 32'h00000000; 17 | RAM[16] <= 32'h00000000; -------------------------------------------------------------------------------- /assignment-3(I)/benchtest/quick multiply/quick multiply.txt: -------------------------------------------------------------------------------- 1 | RAM[0] <= 32'h20080063; 2 | RAM[1] <= 32'h20090025; 3 | RAM[2] <= 32'h20100000; 4 | RAM[3] <= 32'h20040000; 5 | RAM[4] <= 32'h10090008; 6 | RAM[5] <= 32'h312a0001; 7 | RAM[6] <= 32'h100a0003; 8 | RAM[7] <= 32'h02088020; 9 | RAM[8] <= 32'hac900000; 10 | RAM[9] <= 32'h20840004; 11 | RAM[10] <= 32'h00084040; 12 | RAM[11] <= 32'h00094842; 13 | RAM[12] <= 32'h08000004; 14 | RAM[13] <= 32'h00000000; 15 | RAM[14] <= 32'h00000000; 16 | RAM[15] <= 32'h00000000; 17 | RAM[16] <= 32'h00000000; -------------------------------------------------------------------------------- /assignment-1/benchtest/bisection/bisection.ans: -------------------------------------------------------------------------------- 1 | 00000044 2 | 00000001 3 | 00000002 4 | 00000007 5 | 00000007 6 | 00000008 7 | 00000009 8 | 0000000d 9 | 00000012 10 | 00000019 11 | 0000001b 12 | 0000001c 13 | 0000001d 14 | 0000001f 15 | 00000024 16 | 00000026 17 | 00000027 18 | 00000028 19 | 0000002c 20 | 00000030 21 | 00000034 22 | 0000003e 23 | 00000042 24 | 00000044 25 | 00000046 26 | 00000049 27 | 0000004a 28 | 0000004a 29 | 0000004b 30 | 0000004b 31 | 00000051 32 | 00000052 33 | 0000005f 34 | 0000000f 35 | 00000017 36 | 00000013 37 | 00000011 -------------------------------------------------------------------------------- /assignment-2/benchtest/bisection/bisection.ans: -------------------------------------------------------------------------------- 1 | 00000050 2 | 00000001 3 | 00000002 4 | 00000007 5 | 00000007 6 | 00000008 7 | 00000009 8 | 0000000d 9 | 00000012 10 | 00000019 11 | 0000001b 12 | 0000001c 13 | 0000001d 14 | 0000001f 15 | 00000024 16 | 00000026 17 | 00000027 18 | 00000028 19 | 0000002c 20 | 00000030 21 | 00000034 22 | 0000003e 23 | 00000042 24 | 00000044 25 | 00000046 26 | 00000049 27 | 0000004a 28 | 0000004a 29 | 0000004b 30 | 0000004b 31 | 00000051 32 | 00000052 33 | 0000005f 34 | 0000000f 35 | 00000017 36 | 00000013 37 | 00000011 -------------------------------------------------------------------------------- /assignment-2/benchtest/gcd/gcd.txt: -------------------------------------------------------------------------------- 1 | RAM[0] <= 32'h200200bd; 2 | RAM[1] <= 32'h2003011f; 3 | RAM[2] <= 32'h00002020; 4 | RAM[3] <= 32'hac820000; 5 | RAM[4] <= 32'hac830004; 6 | RAM[5] <= 32'h20840008; 7 | RAM[6] <= 32'h10620007; 8 | RAM[7] <= 32'h0043082a; 9 | RAM[8] <= 32'h10010003; 10 | RAM[9] <= 32'h00400820; 11 | RAM[10] <= 32'h00601020; 12 | RAM[11] <= 32'h00201820; 13 | RAM[12] <= 32'h00431022; 14 | RAM[13] <= 32'h08000003; 15 | RAM[14] <= 32'h00000000; 16 | RAM[15] <= 32'h00000000; 17 | RAM[16] <= 32'h00000000; 18 | RAM[17] <= 32'h00000000; -------------------------------------------------------------------------------- /assignment-3(I)/benchtest/bisection/bisection.ans: -------------------------------------------------------------------------------- 1 | 00000050 2 | 00000001 3 | 00000002 4 | 00000007 5 | 00000007 6 | 00000008 7 | 00000009 8 | 0000000d 9 | 00000012 10 | 00000019 11 | 0000001b 12 | 0000001c 13 | 0000001d 14 | 0000001f 15 | 00000024 16 | 00000026 17 | 00000027 18 | 00000028 19 | 0000002c 20 | 00000030 21 | 00000034 22 | 0000003e 23 | 00000042 24 | 00000044 25 | 00000046 26 | 00000049 27 | 0000004a 28 | 0000004a 29 | 0000004b 30 | 0000004b 31 | 00000051 32 | 00000052 33 | 0000005f 34 | 0000000f 35 | 00000017 36 | 00000013 37 | 00000011 -------------------------------------------------------------------------------- /assignment-3(I)/benchtest/gcd/gcd.txt: -------------------------------------------------------------------------------- 1 | RAM[0] <= 32'h200200bd; 2 | RAM[1] <= 32'h2003011f; 3 | RAM[2] <= 32'h00002020; 4 | RAM[3] <= 32'hac820000; 5 | RAM[4] <= 32'hac830004; 6 | RAM[5] <= 32'h20840008; 7 | RAM[6] <= 32'h10620007; 8 | RAM[7] <= 32'h0043082a; 9 | RAM[8] <= 32'h10010003; 10 | RAM[9] <= 32'h00400820; 11 | RAM[10] <= 32'h00601020; 12 | RAM[11] <= 32'h00201820; 13 | RAM[12] <= 32'h00431022; 14 | RAM[13] <= 32'h08000003; 15 | RAM[14] <= 32'h00000000; 16 | RAM[15] <= 32'h00000000; 17 | RAM[16] <= 32'h00000000; 18 | RAM[17] <= 32'h00000000; -------------------------------------------------------------------------------- /assignment-2/benchtest/i-type/i-type.txt: -------------------------------------------------------------------------------- 1 | RAM[0] <= 32'h20180771; 2 | RAM[1] <= 32'h2019f81c; 3 | RAM[2] <= 32'h2b11f81c; 4 | RAM[3] <= 32'hac110000; 5 | RAM[4] <= 32'h2b3107e4; 6 | RAM[5] <= 32'hac110004; 7 | RAM[6] <= 32'h3331ffff; 8 | RAM[7] <= 32'hac110008; 9 | RAM[8] <= 32'h33317fff; 10 | RAM[9] <= 32'hac11000c; 11 | RAM[10] <= 32'h3711fff8; 12 | RAM[11] <= 32'hac110010; 13 | RAM[12] <= 32'h373107e4; 14 | RAM[13] <= 32'hac110014; 15 | RAM[14] <= 32'h00000000; 16 | RAM[15] <= 32'h00000000; 17 | RAM[16] <= 32'h00000000; 18 | RAM[17] <= 32'h00000000; -------------------------------------------------------------------------------- /assignment-3(I)/benchtest/i-type/i-type.txt: -------------------------------------------------------------------------------- 1 | RAM[0] <= 32'h20180771; 2 | RAM[1] <= 32'h2019f81c; 3 | RAM[2] <= 32'h2b11f81c; 4 | RAM[3] <= 32'hac110000; 5 | RAM[4] <= 32'h2b3107e4; 6 | RAM[5] <= 32'hac110004; 7 | RAM[6] <= 32'h3331ffff; 8 | RAM[7] <= 32'hac110008; 9 | RAM[8] <= 32'h33317fff; 10 | RAM[9] <= 32'hac11000c; 11 | RAM[10] <= 32'h3711fff8; 12 | RAM[11] <= 32'hac110010; 13 | RAM[12] <= 32'h373107e4; 14 | RAM[13] <= 32'hac110014; 15 | RAM[14] <= 32'h00000000; 16 | RAM[15] <= 32'h00000000; 17 | RAM[16] <= 32'h00000000; 18 | RAM[17] <= 32'h00000000; -------------------------------------------------------------------------------- /assignment-1/benchtest/bisection/bisection.txt: -------------------------------------------------------------------------------- 1 | RAM[0] <= 32'h2002002c; 2 | RAM[1] <= 32'h20040000; 3 | RAM[2] <= 32'h2005001f; 4 | RAM[3] <= 32'h20100080; 5 | RAM[4] <= 32'h00853020; 6 | RAM[5] <= 32'h00063043; 7 | RAM[6] <= 32'hae060000; 8 | RAM[7] <= 32'h22100004; 9 | RAM[8] <= 32'h00063880; 10 | RAM[9] <= 32'h8ce30000; 11 | RAM[10] <= 32'h0062882a; 12 | RAM[11] <= 32'h14110003; 13 | RAM[12] <= 32'h10620004; 14 | RAM[13] <= 32'h00c02820; 15 | RAM[14] <= 32'h08000004; 16 | RAM[15] <= 32'h00c02020; 17 | RAM[16] <= 32'h08000004; 18 | RAM[17] <= 32'h00000000; -------------------------------------------------------------------------------- /assignment-1/benchtest/testzeroext/testzeroext.out: -------------------------------------------------------------------------------- 1 | 0x0 : addi $a0, $0, -1 | 2004ffff 2 | 0x4 : addi $a1, $0, 0 | 20050000 3 | 0x8 : addi $sp, $0, 32 | 201d0020 4 | 0xc : andi $a0, $a0, -1 | 3084ffff 5 | 0x10 : ori $a1, $a1, -1 | 34a5ffff 6 | 0x14 : sw $a0, 0($sp) | afa40000 7 | 0x18 : sw $a1, 8($sp) | afa50008 8 | 0x1c : nop | 00000000 9 | 0x20 : nop | 00000000 10 | 0x24 : nop | 00000000 11 | 0x28 : nop | 00000000 12 | 0x2c : nop | 13 | -------------------------------------------------------------------------------- /assignment-1/benchtest/bubble sort/bubble sort.txt: -------------------------------------------------------------------------------- 1 | RAM[0] <= 32'h00004020; 2 | RAM[1] <= 32'h200b0080; 3 | RAM[2] <= 32'h0008e820; 4 | RAM[3] <= 32'h8fac0000; 5 | RAM[4] <= 32'h001d6820; 6 | RAM[5] <= 32'h8fae0000; 7 | RAM[6] <= 32'h01cc782a; 8 | RAM[7] <= 32'h140f0002; 9 | RAM[8] <= 32'h000e6020; 10 | RAM[9] <= 32'h03a06820; 11 | RAM[10] <= 32'h23bd0004; 12 | RAM[11] <= 32'h157dfff9; 13 | RAM[12] <= 32'h216bfffc; 14 | RAM[13] <= 32'h8d780000; 15 | RAM[14] <= 32'had6c0000; 16 | RAM[15] <= 32'hadb80000; 17 | RAM[16] <= 32'h1560fff1; 18 | RAM[17] <= 32'h00000000; -------------------------------------------------------------------------------- /assignment-1/benchtest/factorial/factorial.in: -------------------------------------------------------------------------------- 1 | addi $sp, $0, 128 2 | addi $a0, $0, 5 3 | addi $a1, $0, 0 4 | jal factorial 5 | sw $v0, 0($a1) 6 | sll $v0, $v0, 1 7 | nop 8 | 9 | factorial: 10 | addi $sp, $sp, -8 11 | sw $a0, 4($sp) 12 | sw $ra, 0($sp) 13 | addi $t0, $0, 2 14 | slt $t0, $a0, $t0 15 | beq $t0, $0 ,else 16 | addi $v0, $0, 1 17 | addi $sp, $sp, 8 18 | jr $ra 19 | else: 20 | addi $a0, $a0, -1 21 | jal factorial 22 | lw $ra, 0($sp) 23 | lw $a0, 4($sp) 24 | addi $sp, $sp, 8 25 | sw $v0, 0($a1) 26 | add $v0, $a0, $v0 27 | addi $a1, $a1, 4 28 | jr $ra -------------------------------------------------------------------------------- /assignment-1/benchtest/ad hoc/ad hoc.txt: -------------------------------------------------------------------------------- 1 | RAM[0] <= 32'h20020005; 2 | RAM[1] <= 32'h2003000c; 3 | RAM[2] <= 32'h2067fff7; 4 | RAM[3] <= 32'h00e22025; 5 | RAM[4] <= 32'h00642824; 6 | RAM[5] <= 32'h00a42820; 7 | RAM[6] <= 32'h10a7000a; 8 | RAM[7] <= 32'h0064202a; 9 | RAM[8] <= 32'h10800001; 10 | RAM[9] <= 32'h20050000; 11 | RAM[10] <= 32'h00e2202a; 12 | RAM[11] <= 32'h00853820; 13 | RAM[12] <= 32'h00e23822; 14 | RAM[13] <= 32'hac670044; 15 | RAM[14] <= 32'h8c020050; 16 | RAM[15] <= 32'h08000011; 17 | RAM[16] <= 32'h20020001; 18 | RAM[17] <= 32'hac020054; 19 | RAM[18] <= 32'h00000000; -------------------------------------------------------------------------------- /assignment-2/benchtest/factorial/factorial.in: -------------------------------------------------------------------------------- 1 | addi $sp, $0, 128 2 | addi $a0, $0, 5 3 | addi $a1, $0, 0 4 | jal factorial 5 | sw $v0, 0($a1) 6 | sll $v0, $v0, 1 7 | nop 8 | nop 9 | nop 10 | nop 11 | 12 | factorial: 13 | addi $sp, $sp, -8 14 | sw $a0, 4($sp) 15 | sw $ra, 0($sp) 16 | addi $t0, $0, 2 17 | slt $t0, $a0, $t0 18 | beq $t0, $0 ,else 19 | addi $v0, $0, 1 20 | addi $sp, $sp, 8 21 | jr $ra 22 | else: 23 | addi $a0, $a0, -1 24 | jal factorial 25 | lw $ra, 0($sp) 26 | lw $a0, 4($sp) 27 | addi $sp, $sp, 8 28 | sw $v0, 0($a1) 29 | add $v0, $a0, $v0 30 | addi $a1, $a1, 4 31 | jr $ra -------------------------------------------------------------------------------- /assignment-3(I)/benchtest/factorial/factorial.in: -------------------------------------------------------------------------------- 1 | addi $sp, $0, 128 2 | addi $a0, $0, 5 3 | addi $a1, $0, 0 4 | jal factorial 5 | sw $v0, 0($a1) 6 | sll $v0, $v0, 1 7 | nop 8 | nop 9 | nop 10 | nop 11 | 12 | factorial: 13 | addi $sp, $sp, -8 14 | sw $a0, 4($sp) 15 | sw $ra, 0($sp) 16 | addi $t0, $0, 2 17 | slt $t0, $a0, $t0 18 | beq $t0, $0 ,else 19 | addi $v0, $0, 1 20 | addi $sp, $sp, 8 21 | jr $ra 22 | else: 23 | addi $a0, $a0, -1 24 | jal factorial 25 | lw $ra, 0($sp) 26 | lw $a0, 4($sp) 27 | addi $sp, $sp, 8 28 | sw $v0, 0($a1) 29 | add $v0, $a0, $v0 30 | addi $a1, $a1, 4 31 | jr $ra -------------------------------------------------------------------------------- /assignment-2/benchtest/en & clear/en & clear.out: -------------------------------------------------------------------------------- 1 | 0x0 : addi $v0, $0, 5 | 20020005 2 | 0x4 : addi $v1, $0, 12 | 2003000c 3 | 0x8 : addi $a3, $v1, -9 | 2067fff7 4 | 0xc : or $a0, $a3, $v0 | 00e22025 5 | 0x10 : and $a1, $v1, $a0 | 00642824 6 | 0x14 : add $a1, $a1, $a0 | 00a42820 7 | 0x18 : bne $a1, $0, around | 14050001 8 | 0x1c : add $a1, $a1, $a0 | 00a42820 9 | 0x20 : around: | 10 | 0x20 : sw $a1, 4($0) | ac050004 11 | 0x24 : nop | 00000000 12 | 0x28 : nop | 00000000 13 | 0x2c : nop | 00000000 14 | 0x30 : nop | 15 | -------------------------------------------------------------------------------- /assignment-3(I)/benchtest/en & clear/en & clear.out: -------------------------------------------------------------------------------- 1 | 0x0 : addi $v0, $0, 5 | 20020005 2 | 0x4 : addi $v1, $0, 12 | 2003000c 3 | 0x8 : addi $a3, $v1, -9 | 2067fff7 4 | 0xc : or $a0, $a3, $v0 | 00e22025 5 | 0x10 : and $a1, $v1, $a0 | 00642824 6 | 0x14 : add $a1, $a1, $a0 | 00a42820 7 | 0x18 : bne $a1, $0, around | 14050001 8 | 0x1c : add $a1, $a1, $a0 | 00a42820 9 | 0x20 : around: | 10 | 0x20 : sw $a1, 4($0) | ac050004 11 | 0x24 : nop | 00000000 12 | 0x28 : nop | 00000000 13 | 0x2c : nop | 00000000 14 | 0x30 : nop | 15 | -------------------------------------------------------------------------------- /assignment-2/benchtest/bisection/bisection.txt: -------------------------------------------------------------------------------- 1 | RAM[0] <= 32'h2002002c; 2 | RAM[1] <= 32'h20040000; 3 | RAM[2] <= 32'h2005001f; 4 | RAM[3] <= 32'h20100080; 5 | RAM[4] <= 32'h00853020; 6 | RAM[5] <= 32'h00063043; 7 | RAM[6] <= 32'hae060000; 8 | RAM[7] <= 32'h22100004; 9 | RAM[8] <= 32'h00063880; 10 | RAM[9] <= 32'h8ce30000; 11 | RAM[10] <= 32'h0062882a; 12 | RAM[11] <= 32'h14110003; 13 | RAM[12] <= 32'h10620004; 14 | RAM[13] <= 32'h00c02820; 15 | RAM[14] <= 32'h08000004; 16 | RAM[15] <= 32'h00c02020; 17 | RAM[16] <= 32'h08000004; 18 | RAM[17] <= 32'h00000000; 19 | RAM[18] <= 32'h00000000; 20 | RAM[19] <= 32'h00000000; 21 | RAM[20] <= 32'h00000000; -------------------------------------------------------------------------------- /assignment-2/benchtest/bubble sort/bubble sort.txt: -------------------------------------------------------------------------------- 1 | RAM[0] <= 32'h00004020; 2 | RAM[1] <= 32'h200b0080; 3 | RAM[2] <= 32'h0008e820; 4 | RAM[3] <= 32'h8fac0000; 5 | RAM[4] <= 32'h001d6820; 6 | RAM[5] <= 32'h8fae0000; 7 | RAM[6] <= 32'h01cc782a; 8 | RAM[7] <= 32'h140f0002; 9 | RAM[8] <= 32'h000e6020; 10 | RAM[9] <= 32'h03a06820; 11 | RAM[10] <= 32'h23bd0004; 12 | RAM[11] <= 32'h157dfff9; 13 | RAM[12] <= 32'h216bfffc; 14 | RAM[13] <= 32'h8d780000; 15 | RAM[14] <= 32'had6c0000; 16 | RAM[15] <= 32'hadb80000; 17 | RAM[16] <= 32'h1560fff1; 18 | RAM[17] <= 32'h00000000; 19 | RAM[18] <= 32'h00000000; 20 | RAM[19] <= 32'h00000000; 21 | RAM[20] <= 32'h00000000; -------------------------------------------------------------------------------- /assignment-3(I)/benchtest/bisection/bisection.txt: -------------------------------------------------------------------------------- 1 | RAM[0] <= 32'h2002002c; 2 | RAM[1] <= 32'h20040000; 3 | RAM[2] <= 32'h2005001f; 4 | RAM[3] <= 32'h20100080; 5 | RAM[4] <= 32'h00853020; 6 | RAM[5] <= 32'h00063043; 7 | RAM[6] <= 32'hae060000; 8 | RAM[7] <= 32'h22100004; 9 | RAM[8] <= 32'h00063880; 10 | RAM[9] <= 32'h8ce30000; 11 | RAM[10] <= 32'h0062882a; 12 | RAM[11] <= 32'h14110003; 13 | RAM[12] <= 32'h10620004; 14 | RAM[13] <= 32'h00c02820; 15 | RAM[14] <= 32'h08000004; 16 | RAM[15] <= 32'h00c02020; 17 | RAM[16] <= 32'h08000004; 18 | RAM[17] <= 32'h00000000; 19 | RAM[18] <= 32'h00000000; 20 | RAM[19] <= 32'h00000000; 21 | RAM[20] <= 32'h00000000; -------------------------------------------------------------------------------- /assignment-3(I)/benchtest/bubble sort/bubble sort.txt: -------------------------------------------------------------------------------- 1 | RAM[0] <= 32'h00004020; 2 | RAM[1] <= 32'h200b0080; 3 | RAM[2] <= 32'h0008e820; 4 | RAM[3] <= 32'h8fac0000; 5 | RAM[4] <= 32'h001d6820; 6 | RAM[5] <= 32'h8fae0000; 7 | RAM[6] <= 32'h01cc782a; 8 | RAM[7] <= 32'h140f0002; 9 | RAM[8] <= 32'h000e6020; 10 | RAM[9] <= 32'h03a06820; 11 | RAM[10] <= 32'h23bd0004; 12 | RAM[11] <= 32'h157dfff9; 13 | RAM[12] <= 32'h216bfffc; 14 | RAM[13] <= 32'h8d780000; 15 | RAM[14] <= 32'had6c0000; 16 | RAM[15] <= 32'hadb80000; 17 | RAM[16] <= 32'h1560fff1; 18 | RAM[17] <= 32'h00000000; 19 | RAM[18] <= 32'h00000000; 20 | RAM[19] <= 32'h00000000; 21 | RAM[20] <= 32'h00000000; -------------------------------------------------------------------------------- /assignment-2/benchtest/ad hoc/ad hoc.txt: -------------------------------------------------------------------------------- 1 | RAM[0] <= 32'h20020005; 2 | RAM[1] <= 32'h2003000c; 3 | RAM[2] <= 32'h2067fff7; 4 | RAM[3] <= 32'h00e22025; 5 | RAM[4] <= 32'h00642824; 6 | RAM[5] <= 32'h00a42820; 7 | RAM[6] <= 32'h10a7000a; 8 | RAM[7] <= 32'h0064202a; 9 | RAM[8] <= 32'h10800001; 10 | RAM[9] <= 32'h20050000; 11 | RAM[10] <= 32'h00e2202a; 12 | RAM[11] <= 32'h00853820; 13 | RAM[12] <= 32'h00e23822; 14 | RAM[13] <= 32'hac670044; 15 | RAM[14] <= 32'h8c020050; 16 | RAM[15] <= 32'h08000011; 17 | RAM[16] <= 32'h20020001; 18 | RAM[17] <= 32'hac020054; 19 | RAM[18] <= 32'h00000000; 20 | RAM[19] <= 32'h00000000; 21 | RAM[20] <= 32'h00000000; 22 | RAM[21] <= 32'h00000000; -------------------------------------------------------------------------------- /assignment-3(I)/benchtest/ad hoc/ad hoc.txt: -------------------------------------------------------------------------------- 1 | RAM[0] <= 32'h20020005; 2 | RAM[1] <= 32'h2003000c; 3 | RAM[2] <= 32'h2067fff7; 4 | RAM[3] <= 32'h00e22025; 5 | RAM[4] <= 32'h00642824; 6 | RAM[5] <= 32'h00a42820; 7 | RAM[6] <= 32'h10a7000a; 8 | RAM[7] <= 32'h0064202a; 9 | RAM[8] <= 32'h10800001; 10 | RAM[9] <= 32'h20050000; 11 | RAM[10] <= 32'h00e2202a; 12 | RAM[11] <= 32'h00853820; 13 | RAM[12] <= 32'h00e23822; 14 | RAM[13] <= 32'hac670044; 15 | RAM[14] <= 32'h8c020050; 16 | RAM[15] <= 32'h08000011; 17 | RAM[16] <= 32'h20020001; 18 | RAM[17] <= 32'hac020054; 19 | RAM[18] <= 32'h00000000; 20 | RAM[19] <= 32'h00000000; 21 | RAM[20] <= 32'h00000000; 22 | RAM[21] <= 32'h00000000; -------------------------------------------------------------------------------- /assignment-3(I)/src/line.v: -------------------------------------------------------------------------------- 1 | `include "cache.vh" 2 | /** 3 | * w_en: write enable 4 | */ 5 | module line #( 6 | parameter TAG_WIDTH = `CACHE_T, 7 | OFFSET_WIDTH = `CACHE_B 8 | )( 9 | input clk, reset, 10 | input [OFFSET_WIDTH - 3:0] offset, 11 | input w_en, set_valid, set_dirty, 12 | input [TAG_WIDTH - 1:0] set_tag, 13 | input [31:0] write_data, 14 | output reg valid, 15 | output dirty, 16 | output reg [TAG_WIDTH - 1:0] tag, 17 | output [31:0] read_data 18 | ); 19 | 20 | /** 21 | * TODO: Your code here 22 | */ 23 | 24 | endmodule 25 | -------------------------------------------------------------------------------- /assignment-1/benchtest/quick multiply/quick multiply.out: -------------------------------------------------------------------------------- 1 | 0x0 : addi $t0, $0, 99 | 20080063 2 | 0x4 : addi $t1, $0, 37 | 20090025 3 | 0x8 : addi $s0, $0, 0 | 20100000 4 | 0xc : addi $a0, $0, 0 | 20040000 5 | 0x10 : while: | 6 | 0x10 : beq $t1, $0, done | 10090008 7 | 0x14 : andi $t2, $t1, 1 | 312a0001 8 | 0x18 : beq $t2, $0, target | 100a0003 9 | 0x1c : add $s0, $s0, $t0 | 02088020 10 | 0x20 : sw $s0, 0($a0) | ac900000 11 | 0x24 : addi $a0, $a0, 4 | 20840004 12 | 0x28 : target: | 13 | 0x28 : sll $t0, $t0, 1 | 00084040 14 | 0x2c : srl $t1, $t1, 1 | 00094842 15 | 0x30 : j while | 08000004 16 | 0x34 : done: | 17 | 0x34 : nop | 00000000 -------------------------------------------------------------------------------- /assignment-1/benchtest/factorial/factorial.txt: -------------------------------------------------------------------------------- 1 | RAM[0] <= 32'h201d0080; 2 | RAM[1] <= 32'h20040005; 3 | RAM[2] <= 32'h20050000; 4 | RAM[3] <= 32'h0c000007; 5 | RAM[4] <= 32'haca20000; 6 | RAM[5] <= 32'h00021040; 7 | RAM[6] <= 32'h00000000; 8 | RAM[7] <= 32'h23bdfff8; 9 | RAM[8] <= 32'hafa40004; 10 | RAM[9] <= 32'hafbf0000; 11 | RAM[10] <= 32'h20080002; 12 | RAM[11] <= 32'h0088402a; 13 | RAM[12] <= 32'h10080003; 14 | RAM[13] <= 32'h20020001; 15 | RAM[14] <= 32'h23bd0008; 16 | RAM[15] <= 32'h03e00008; 17 | RAM[16] <= 32'h2084ffff; 18 | RAM[17] <= 32'h0c000007; 19 | RAM[18] <= 32'h8fbf0000; 20 | RAM[19] <= 32'h8fa40004; 21 | RAM[20] <= 32'h23bd0008; 22 | RAM[21] <= 32'haca20000; 23 | RAM[22] <= 32'h00821020; 24 | RAM[23] <= 32'h20a50004; 25 | RAM[24] <= 32'h03e00008; -------------------------------------------------------------------------------- /assignment-1/benchtest/gcd/gcd.out: -------------------------------------------------------------------------------- 1 | 0x0 : addi $v0,$0,189 | 200200bd 2 | 0x4 : addi $v1,$0,287 | 2003011f 3 | 0x8 : add $a0, $0, $0 | 00002020 4 | 0xc : main: | 5 | 0xc : sw $v0, 0($a0) | ac820000 6 | 0x10 : sw $v1, 4($a0) | ac830004 7 | 0x14 : addi $a0, $a0, 8 | 20840008 8 | 0x18 : beq $v0,$v1,end | 10620007 9 | 0x1c : slt $at,$v0,$v1 | 0043082a 10 | 0x20 : beq $at,$0,run | 10010003 11 | 0x24 : add $at,$v0,$0 | 00400820 12 | 0x28 : add $v0,$v1,$0 | 00601020 13 | 0x2c : add $v1,$at,$0 | 00201820 14 | 0x30 : run: | 15 | 0x30 : sub $v0,$v0,$v1 | 00431022 16 | 0x34 : j main | 08000003 17 | 0x38 : end: | 18 | 0x38 : nop | 00000000 19 | -------------------------------------------------------------------------------- /assignment-2/benchtest/i-type/i-type.out: -------------------------------------------------------------------------------- 1 | 0x0 : addi $t8, $0, 1905 | 20180771 2 | 0x4 : addi $t9, $0, -2020 | 2019f81c 3 | 0x8 : slti $s1, $t8, -2020 | 2b11f81c 4 | 0xc : sw $s1, 0($0) | ac110000 5 | 0x10 : slti $s1, $t9, 2020 | 2b3107e4 6 | 0x14 : sw $s1, 4($0) | ac110004 7 | 0x18 : andi $s1, $t9, -1 | 3331ffff 8 | 0x1c : sw $s1, 8($0) | ac110008 9 | 0x20 : andi $s1, $t9, 32767 | 33317fff 10 | 0x24 : sw $s1, 12($0) | ac11000c 11 | 0x28 : ori $s1, $t8, -8 | 3711fff8 12 | 0x2c : sw $s1, 16($0) | ac110010 13 | 0x30 : ori $s1, $t9, 2020 | 373107e4 14 | 0x34 : sw $s1, 20($0) | ac110014 15 | 0x38 : nop | 00000000 16 | 0x3c : nop | 00000000 17 | 0x40 : nop | 00000000 18 | 0x44 : nop | 00000000 -------------------------------------------------------------------------------- /assignment-2/benchtest/mutual recursion/mutual recursion.mem: -------------------------------------------------------------------------------- 1 | 20100000 2 | 20080066 3 | ae080000 4 | 20080067 5 | ae080004 6 | 20080066 7 | ae080008 8 | 20080067 9 | ae08000c 10 | 20080061 11 | ae080010 12 | 201d0080 13 | 20040000 14 | 0c000013 15 | 20510000 16 | 00000000 17 | 00000000 18 | 00000000 19 | 00000000 20 | 23bdfff8 21 | afa40004 22 | afbf0000 23 | 0004c880 24 | 0219c820 25 | 8f280000 26 | 20090061 27 | 15280002 28 | 20820001 29 | 08000023 30 | 20090066 31 | 15280003 32 | 20840001 33 | 0c000027 34 | 08000023 35 | 2002ffff 36 | 8fbf0000 37 | 8fa40004 38 | 23bd0008 39 | 03e00008 40 | 23bdfff8 41 | afa40004 42 | afbf0000 43 | 0004c880 44 | 0219c820 45 | 8f280000 46 | 20090067 47 | 15280003 48 | 20840001 49 | 0c000013 50 | 08000033 51 | 2002ffff 52 | 8fbf0000 53 | 8fa40004 54 | 23bd0008 55 | 03e00008 -------------------------------------------------------------------------------- /assignment-3(I)/benchtest/mutual recursion/mutual recursion.mem: -------------------------------------------------------------------------------- 1 | 20100000 2 | 20080066 3 | ae080000 4 | 20080067 5 | ae080004 6 | 20080066 7 | ae080008 8 | 20080067 9 | ae08000c 10 | 20080061 11 | ae080010 12 | 201d0080 13 | 20040000 14 | 0c000013 15 | 20510000 16 | 00000000 17 | 00000000 18 | 00000000 19 | 00000000 20 | 23bdfff8 21 | afa40004 22 | afbf0000 23 | 0004c880 24 | 0219c820 25 | 8f280000 26 | 20090061 27 | 15280002 28 | 20820001 29 | 08000023 30 | 20090066 31 | 15280003 32 | 20840001 33 | 0c000027 34 | 08000023 35 | 2002ffff 36 | 8fbf0000 37 | 8fa40004 38 | 23bd0008 39 | 03e00008 40 | 23bdfff8 41 | afa40004 42 | afbf0000 43 | 0004c880 44 | 0219c820 45 | 8f280000 46 | 20090067 47 | 15280003 48 | 20840001 49 | 0c000013 50 | 08000033 51 | 2002ffff 52 | 8fbf0000 53 | 8fa40004 54 | 23bd0008 55 | 03e00008 -------------------------------------------------------------------------------- /assignment-3(I)/benchtest/i-type/i-type.out: -------------------------------------------------------------------------------- 1 | 0x0 : addi $t8, $0, 1905 | 20180771 2 | 0x4 : addi $t9, $0, -2020 | 2019f81c 3 | 0x8 : slti $s1, $t8, -2020 | 2b11f81c 4 | 0xc : sw $s1, 0($0) | ac110000 5 | 0x10 : slti $s1, $t9, 2020 | 2b3107e4 6 | 0x14 : sw $s1, 4($0) | ac110004 7 | 0x18 : andi $s1, $t9, -1 | 3331ffff 8 | 0x1c : sw $s1, 8($0) | ac110008 9 | 0x20 : andi $s1, $t9, 32767 | 33317fff 10 | 0x24 : sw $s1, 12($0) | ac11000c 11 | 0x28 : ori $s1, $t8, -8 | 3711fff8 12 | 0x2c : sw $s1, 16($0) | ac110010 13 | 0x30 : ori $s1, $t9, 2020 | 373107e4 14 | 0x34 : sw $s1, 20($0) | ac110014 15 | 0x38 : nop | 00000000 16 | 0x3c : nop | 00000000 17 | 0x40 : nop | 00000000 18 | 0x44 : nop | 00000000 -------------------------------------------------------------------------------- /assignment-2/benchtest/factorial/factorial.txt: -------------------------------------------------------------------------------- 1 | RAM[0] <= 32'h201d0080; 2 | RAM[1] <= 32'h20040005; 3 | RAM[2] <= 32'h20050000; 4 | RAM[3] <= 32'h0c00000a; 5 | RAM[4] <= 32'haca20000; 6 | RAM[5] <= 32'h00021040; 7 | RAM[6] <= 32'h00000000; 8 | RAM[7] <= 32'h00000000; 9 | RAM[8] <= 32'h00000000; 10 | RAM[9] <= 32'h00000000; 11 | RAM[10] <= 32'h23bdfff8; 12 | RAM[11] <= 32'hafa40004; 13 | RAM[12] <= 32'hafbf0000; 14 | RAM[13] <= 32'h20080002; 15 | RAM[14] <= 32'h0088402a; 16 | RAM[15] <= 32'h10080003; 17 | RAM[16] <= 32'h20020001; 18 | RAM[17] <= 32'h23bd0008; 19 | RAM[18] <= 32'h03e00008; 20 | RAM[19] <= 32'h2084ffff; 21 | RAM[20] <= 32'h0c00000a; 22 | RAM[21] <= 32'h8fbf0000; 23 | RAM[22] <= 32'h8fa40004; 24 | RAM[23] <= 32'h23bd0008; 25 | RAM[24] <= 32'haca20000; 26 | RAM[25] <= 32'h00821020; 27 | RAM[26] <= 32'h20a50004; 28 | RAM[27] <= 32'h03e00008; -------------------------------------------------------------------------------- /assignment-3(I)/benchtest/factorial/factorial.txt: -------------------------------------------------------------------------------- 1 | RAM[0] <= 32'h201d0080; 2 | RAM[1] <= 32'h20040005; 3 | RAM[2] <= 32'h20050000; 4 | RAM[3] <= 32'h0c00000a; 5 | RAM[4] <= 32'haca20000; 6 | RAM[5] <= 32'h00021040; 7 | RAM[6] <= 32'h00000000; 8 | RAM[7] <= 32'h00000000; 9 | RAM[8] <= 32'h00000000; 10 | RAM[9] <= 32'h00000000; 11 | RAM[10] <= 32'h23bdfff8; 12 | RAM[11] <= 32'hafa40004; 13 | RAM[12] <= 32'hafbf0000; 14 | RAM[13] <= 32'h20080002; 15 | RAM[14] <= 32'h0088402a; 16 | RAM[15] <= 32'h10080003; 17 | RAM[16] <= 32'h20020001; 18 | RAM[17] <= 32'h23bd0008; 19 | RAM[18] <= 32'h03e00008; 20 | RAM[19] <= 32'h2084ffff; 21 | RAM[20] <= 32'h0c00000a; 22 | RAM[21] <= 32'h8fbf0000; 23 | RAM[22] <= 32'h8fa40004; 24 | RAM[23] <= 32'h23bd0008; 25 | RAM[24] <= 32'haca20000; 26 | RAM[25] <= 32'h00821020; 27 | RAM[26] <= 32'h20a50004; 28 | RAM[27] <= 32'h03e00008; -------------------------------------------------------------------------------- /assignment-3(I)/benchtest/random write/random write.out: -------------------------------------------------------------------------------- 1 | 0x0 : addi $t0, $0, 17 | 20080011 2 | 0x4 : addi $t1, $0, 32 | 20090020 3 | 0x8 : addi $t3, $0, 16 | 200b0010 4 | 0xc : addi $s0, $0, 0 | 20100000 5 | 0x10 : For: | 6 | 0x10 : addi $t2, $0, 0 | 200a0000 7 | 0x14 : for: | 8 | 0x14 : add $s0, $s0, $t0 | 02088020 9 | 0x18 : andi $t4, $s0, 127 | 320c007f 10 | 0x1c : sll $t4, $t4, 2 | 000c6080 11 | 0x20 : sw $t0, 0($t4) | ad880000 12 | 0x24 : addi $t2, $t2, 1 | 214a0001 13 | 0x28 : bne $t2, $t3, for | 156afffa 14 | 0x2c : addi $t0, $t0, 1 | 21080001 15 | 0x30 : bne $t0, $t1, For | 1528fff7 16 | 0x34 : nop | 00000000 17 | 0x38 : nop | 00000000 18 | 0x3c : nop | 00000000 19 | 0x40 : nop | 20 | -------------------------------------------------------------------------------- /assignment-2/benchtest/quick multiply/quick multiply.out: -------------------------------------------------------------------------------- 1 | 0x0 : addi $t0, $0, 99 | 20080063 2 | 0x4 : addi $t1, $0, 37 | 20090025 3 | 0x8 : addi $s0, $0, 0 | 20100000 4 | 0xc : addi $a0, $0, 0 | 20040000 5 | 0x10 : while: | 6 | 0x10 : beq $t1, $0, done | 10090008 7 | 0x14 : andi $t2, $t1, 1 | 312a0001 8 | 0x18 : beq $t2, $0, target | 100a0003 9 | 0x1c : add $s0, $s0, $t0 | 02088020 10 | 0x20 : sw $s0, 0($a0) | ac900000 11 | 0x24 : addi $a0, $a0, 4 | 20840004 12 | 0x28 : target: | 13 | 0x28 : sll $t0, $t0, 1 | 00084040 14 | 0x2c : srl $t1, $t1, 1 | 00094842 15 | 0x30 : j while | 08000004 16 | 0x34 : done: | 17 | 0x34 : nop | 00000000 18 | 0x38 : nop | 00000000 19 | 0x3c : nop | 00000000 20 | 0x40 : nop | 00000000 -------------------------------------------------------------------------------- /assignment-3(I)/benchtest/quick multiply/quick multiply.out: -------------------------------------------------------------------------------- 1 | 0x0 : addi $t0, $0, 99 | 20080063 2 | 0x4 : addi $t1, $0, 37 | 20090025 3 | 0x8 : addi $s0, $0, 0 | 20100000 4 | 0xc : addi $a0, $0, 0 | 20040000 5 | 0x10 : while: | 6 | 0x10 : beq $t1, $0, done | 10090008 7 | 0x14 : andi $t2, $t1, 1 | 312a0001 8 | 0x18 : beq $t2, $0, target | 100a0003 9 | 0x1c : add $s0, $s0, $t0 | 02088020 10 | 0x20 : sw $s0, 0($a0) | ac900000 11 | 0x24 : addi $a0, $a0, 4 | 20840004 12 | 0x28 : target: | 13 | 0x28 : sll $t0, $t0, 1 | 00084040 14 | 0x2c : srl $t1, $t1, 1 | 00094842 15 | 0x30 : j while | 08000004 16 | 0x34 : done: | 17 | 0x34 : nop | 00000000 18 | 0x38 : nop | 00000000 19 | 0x3c : nop | 00000000 20 | 0x40 : nop | 00000000 -------------------------------------------------------------------------------- /assignment-3(I)/src/cache_controller.v: -------------------------------------------------------------------------------- 1 | /** 2 | * en : en in cache module 3 | * cw_en : cache writing enable signal, from w_en in cache module 4 | * hit, dirty : from set module 5 | * 6 | * w_en : writing enable signal to cache line 7 | * mw_en : writing enable signal to memory , controls whether to write to memory 8 | * set_valid : control signal for cache line 9 | * set_dirty : control signal for cache line 10 | * offset_sel : control signal for cache line and this may be used in other places 11 | */ 12 | module cache_controller #( 13 | parameter OFFSET_WIDTH = `CACHE_B 14 | )( 15 | input clk, reset, en, cw_en, hit, dirty, // mready, 16 | output w_en, set_valid, set_dirty, mw_en, 17 | output [OFFSET_WIDTH - 3:0] block_offset, 18 | output strategy_en, 19 | output reg offset_sel 20 | ); 21 | 22 | /** 23 | * TODO: Your code here 24 | */ 25 | 26 | endmodule 27 | -------------------------------------------------------------------------------- /assignment-2/benchtest/gcd/gcd.out: -------------------------------------------------------------------------------- 1 | 0x0 : addi $v0,$0,189 | 200200bd 2 | 0x4 : addi $v1,$0,287 | 2003011f 3 | 0x8 : add $a0, $0, $0 | 00002020 4 | 0xc : main: | 5 | 0xc : sw $v0, 0($a0) | ac820000 6 | 0x10 : sw $v1, 4($a0) | ac830004 7 | 0x14 : addi $a0, $a0, 8 | 20840008 8 | 0x18 : beq $v0,$v1,end | 10620007 9 | 0x1c : slt $at,$v0,$v1 | 0043082a 10 | 0x20 : beq $at,$0,run | 10010003 11 | 0x24 : add $at,$v0,$0 | 00400820 12 | 0x28 : add $v0,$v1,$0 | 00601020 13 | 0x2c : add $v1,$at,$0 | 00201820 14 | 0x30 : run: | 15 | 0x30 : sub $v0,$v0,$v1 | 00431022 16 | 0x34 : j main | 08000003 17 | 0x38 : end: | 18 | 0x38 : nop | 00000000 19 | 0x3c : nop | 00000000 20 | 0x40 : nop | 00000000 21 | 0x44 : nop | 00000000 -------------------------------------------------------------------------------- /assignment-2/benchtest/testjr/testjr.mem: -------------------------------------------------------------------------------- 1 | 201d0040 2 | 2008000a 3 | 20090064 4 | 2004001c 5 | 20040024 6 | 00000000 7 | 00800008 8 | afa80000 9 | 0800000a 10 | afa90000 11 | 23bdfff8 12 | 20040038 13 | 20040040 14 | 00800008 15 | afa80000 16 | 08000011 17 | afa90000 18 | 23bdfff8 19 | 20040064 20 | ac040000 21 | 2004006c 22 | ac040008 23 | 8c040000 24 | 8c040008 25 | 00800008 26 | afa80000 27 | 0800001c 28 | afa90000 29 | 23bdfff8 30 | 20040090 31 | ac040010 32 | 20040088 33 | 8c040010 34 | 00800008 35 | afa80000 36 | 08000025 37 | afa90000 38 | 20080006 39 | ac080000 40 | 0000e820 41 | 01204824 42 | 21290006 43 | 8fa80000 44 | 1128fffd 45 | ac090004 46 | 200800dc 47 | ac080000 48 | 200800f0 49 | ac080004 50 | 03a0e824 51 | 01004024 52 | ac000018 53 | 8fa80000 54 | 01000008 55 | afa80050 56 | 8fa80004 57 | 2108fffc 58 | 01000008 59 | afa80054 60 | ac08000c 61 | 00000000 62 | 00000000 63 | 00000000 64 | 00000000 -------------------------------------------------------------------------------- /assignment-3(I)/benchtest/gcd/gcd.out: -------------------------------------------------------------------------------- 1 | 0x0 : addi $v0,$0,189 | 200200bd 2 | 0x4 : addi $v1,$0,287 | 2003011f 3 | 0x8 : add $a0, $0, $0 | 00002020 4 | 0xc : main: | 5 | 0xc : sw $v0, 0($a0) | ac820000 6 | 0x10 : sw $v1, 4($a0) | ac830004 7 | 0x14 : addi $a0, $a0, 8 | 20840008 8 | 0x18 : beq $v0,$v1,end | 10620007 9 | 0x1c : slt $at,$v0,$v1 | 0043082a 10 | 0x20 : beq $at,$0,run | 10010003 11 | 0x24 : add $at,$v0,$0 | 00400820 12 | 0x28 : add $v0,$v1,$0 | 00601020 13 | 0x2c : add $v1,$at,$0 | 00201820 14 | 0x30 : run: | 15 | 0x30 : sub $v0,$v0,$v1 | 00431022 16 | 0x34 : j main | 08000003 17 | 0x38 : end: | 18 | 0x38 : nop | 00000000 19 | 0x3c : nop | 00000000 20 | 0x40 : nop | 00000000 21 | 0x44 : nop | 00000000 -------------------------------------------------------------------------------- /assignment-3(I)/benchtest/testjr/testjr.mem: -------------------------------------------------------------------------------- 1 | 201d0040 2 | 2008000a 3 | 20090064 4 | 2004001c 5 | 20040024 6 | 00000000 7 | 00800008 8 | afa80000 9 | 0800000a 10 | afa90000 11 | 23bdfff8 12 | 20040038 13 | 20040040 14 | 00800008 15 | afa80000 16 | 08000011 17 | afa90000 18 | 23bdfff8 19 | 20040064 20 | ac040000 21 | 2004006c 22 | ac040008 23 | 8c040000 24 | 8c040008 25 | 00800008 26 | afa80000 27 | 0800001c 28 | afa90000 29 | 23bdfff8 30 | 20040090 31 | ac040010 32 | 20040088 33 | 8c040010 34 | 00800008 35 | afa80000 36 | 08000025 37 | afa90000 38 | 20080006 39 | ac080000 40 | 0000e820 41 | 01204824 42 | 21290006 43 | 8fa80000 44 | 1128fffd 45 | ac090004 46 | 200800dc 47 | ac080000 48 | 200800f0 49 | ac080004 50 | 03a0e824 51 | 01004024 52 | ac000018 53 | 8fa80000 54 | 01000008 55 | afa80050 56 | 8fa80004 57 | 2108fffc 58 | 01000008 59 | afa80054 60 | ac08000c 61 | 00000000 62 | 00000000 63 | 00000000 64 | 00000000 -------------------------------------------------------------------------------- /assignment-1/benchtest/bisection/bisection.out: -------------------------------------------------------------------------------- 1 | 0x0 : addi $v0, $0, 44 | 2002002c 2 | 0x4 : addi $a0, $0, 0 | 20040000 3 | 0x8 : addi $a1, $0, 31 | 2005001f 4 | 0xc : addi $s0, $0, 128 | 20100080 5 | 0x10 : mid: | 6 | 0x10 : add $a2, $a0, $a1 | 00853020 7 | 0x14 : sra $a2, $a2, 1 | 00063043 8 | 0x18 : sw $a2, 0($s0) | ae060000 9 | 0x1c : addi $s0, $s0, 4 | 22100004 10 | 0x20 : sll $a3, $a2, 2 | 00063880 11 | 0x24 : lw $v1, 0($a3) | 8ce30000 12 | 0x28 : slt $s1, $v1, $v0 | 0062882a 13 | 0x2c : bne $s1, $0, less | 14110003 14 | 0x30 : beq $v0, $v1, exit | 10620004 15 | 0x34 : add $a1, $a2, $0 | 00c02820 16 | 0x38 : j mid | 08000004 17 | 0x3c : less: | 18 | 0x3c : add $a0, $a2, $0 | 00c02020 19 | 0x40 : j mid | 08000004 20 | 0x44 : exit: | 21 | 0x44 : nop | 00000000 -------------------------------------------------------------------------------- /assignment-1/benchtest/bubble sort/bubble sort.out: -------------------------------------------------------------------------------- 1 | 0x0 : add $t0, $0, $0 | 00004020 2 | 0x4 : addi $t3, $0, 128 | 200b0080 3 | 0x8 : For: | 4 | 0x8 : add $sp, $0, $t0 | 0008e820 5 | 0xc : lw $t4, 0($sp) | 8fac0000 6 | 0x10 : add $t5, $0, $sp | 001d6820 7 | 0x14 : for: | 8 | 0x14 : lw $t6, 0($sp) | 8fae0000 9 | 0x18 : slt $t7, $t6, $t4 | 01cc782a 10 | 0x1c : bne $t7, $0, ret | 140f0002 11 | 0x20 : add $t4, $0, $t6 | 000e6020 12 | 0x24 : add $t5, $sp, $0 | 03a06820 13 | 0x28 : ret: | 14 | 0x28 : addi $sp, $sp, 4 | 23bd0004 15 | 0x2c : bne $sp, $t3, for | 157dfff9 16 | 0x30 : addi $t3, $t3, -4 | 216bfffc 17 | 0x34 : lw $t8, 0($t3) | 8d780000 18 | 0x38 : sw $t4, 0($t3) | ad6c0000 19 | 0x3c : sw $t8, 0($t5) | adb80000 20 | 0x40 : bne $0, $t3, For | 1560fff1 21 | 0x44 : nop | 00000000 -------------------------------------------------------------------------------- /assignment-1/benchtest/gcd/gcd.run: -------------------------------------------------------------------------------- 1 | [0x00000000]=0x000000bd 2 | [0x00000004]=0x0000011f 3 | [0x00000008]=0x00000062 4 | [0x0000000c]=0x000000bd 5 | [0x00000010]=0x0000005b 6 | [0x00000014]=0x00000062 7 | [0x00000018]=0x00000007 8 | [0x0000001c]=0x0000005b 9 | [0x00000020]=0x00000054 10 | [0x00000024]=0x00000007 11 | [0x00000028]=0x0000004d 12 | [0x0000002c]=0x00000007 13 | [0x00000030]=0x00000046 14 | [0x00000034]=0x00000007 15 | [0x00000038]=0x0000003f 16 | [0x0000003c]=0x00000007 17 | [0x00000040]=0x00000038 18 | [0x00000044]=0x00000007 19 | [0x00000048]=0x00000031 20 | [0x0000004c]=0x00000007 21 | [0x00000050]=0x0000002a 22 | [0x00000054]=0x00000007 23 | [0x00000058]=0x00000023 24 | [0x0000005c]=0x00000007 25 | [0x00000060]=0x0000001c 26 | [0x00000064]=0x00000007 27 | [0x00000068]=0x00000015 28 | [0x0000006c]=0x00000007 29 | [0x00000070]=0x0000000e 30 | [0x00000074]=0x00000007 31 | [0x00000078]=0x00000007 32 | [0x0000007c]=0x00000007 -------------------------------------------------------------------------------- /assignment-2/benchtest/gcd/gcd.run: -------------------------------------------------------------------------------- 1 | [0x00000000]=0x000000bd 2 | [0x00000004]=0x0000011f 3 | [0x00000008]=0x00000062 4 | [0x0000000c]=0x000000bd 5 | [0x00000010]=0x0000005b 6 | [0x00000014]=0x00000062 7 | [0x00000018]=0x00000007 8 | [0x0000001c]=0x0000005b 9 | [0x00000020]=0x00000054 10 | [0x00000024]=0x00000007 11 | [0x00000028]=0x0000004d 12 | [0x0000002c]=0x00000007 13 | [0x00000030]=0x00000046 14 | [0x00000034]=0x00000007 15 | [0x00000038]=0x0000003f 16 | [0x0000003c]=0x00000007 17 | [0x00000040]=0x00000038 18 | [0x00000044]=0x00000007 19 | [0x00000048]=0x00000031 20 | [0x0000004c]=0x00000007 21 | [0x00000050]=0x0000002a 22 | [0x00000054]=0x00000007 23 | [0x00000058]=0x00000023 24 | [0x0000005c]=0x00000007 25 | [0x00000060]=0x0000001c 26 | [0x00000064]=0x00000007 27 | [0x00000068]=0x00000015 28 | [0x0000006c]=0x00000007 29 | [0x00000070]=0x0000000e 30 | [0x00000074]=0x00000007 31 | [0x00000078]=0x00000007 32 | [0x0000007c]=0x00000007 -------------------------------------------------------------------------------- /assignment-3(I)/benchtest/gcd/gcd.run: -------------------------------------------------------------------------------- 1 | [0x00000000]=0x000000bd 2 | [0x00000004]=0x0000011f 3 | [0x00000008]=0x00000062 4 | [0x0000000c]=0x000000bd 5 | [0x00000010]=0x0000005b 6 | [0x00000014]=0x00000062 7 | [0x00000018]=0x00000007 8 | [0x0000001c]=0x0000005b 9 | [0x00000020]=0x00000054 10 | [0x00000024]=0x00000007 11 | [0x00000028]=0x0000004d 12 | [0x0000002c]=0x00000007 13 | [0x00000030]=0x00000046 14 | [0x00000034]=0x00000007 15 | [0x00000038]=0x0000003f 16 | [0x0000003c]=0x00000007 17 | [0x00000040]=0x00000038 18 | [0x00000044]=0x00000007 19 | [0x00000048]=0x00000031 20 | [0x0000004c]=0x00000007 21 | [0x00000050]=0x0000002a 22 | [0x00000054]=0x00000007 23 | [0x00000058]=0x00000023 24 | [0x0000005c]=0x00000007 25 | [0x00000060]=0x0000001c 26 | [0x00000064]=0x00000007 27 | [0x00000068]=0x00000015 28 | [0x0000006c]=0x00000007 29 | [0x00000070]=0x0000000e 30 | [0x00000074]=0x00000007 31 | [0x00000078]=0x00000007 32 | [0x0000007c]=0x00000007 -------------------------------------------------------------------------------- /assignment-1/benchtest/ad hoc/ad hoc.out: -------------------------------------------------------------------------------- 1 | 0x0 : main: | 2 | 0x0 : addi $v0, $0, 5 | 20020005 3 | 0x4 : addi $v1, $0, 12 | 2003000c 4 | 0x8 : addi $a3, $v1, -9 | 2067fff7 5 | 0xc : or $a0, $a3, $v0 | 00e22025 6 | 0x10 : and $a1, $v1, $a0 | 00642824 7 | 0x14 : add $a1, $a1, $a0 | 00a42820 8 | 0x18 : beq $a3, $a1, end | 10a7000a 9 | 0x1c : slt $a0, $v1, $a0 | 0064202a 10 | 0x20 : beq $0, $a0, around | 10800001 11 | 0x24 : addi $a1, $0, 0 | 20050000 12 | 0x28 : around: | 13 | 0x28 : slt $a0, $a3, $v0 | 00e2202a 14 | 0x2c : add $a3, $a0, $a1 | 00853820 15 | 0x30 : sub $a3, $a3, $v0 | 00e23822 16 | 0x34 : sw $a3, 68($v1) | ac670044 17 | 0x38 : lw $v0, 80($0) | 8c020050 18 | 0x3c : j end | 08000011 19 | 0x40 : addi $v0, $0, 1 | 20020001 20 | 0x44 : end: | 21 | 0x44 : sw $v0, 84($0) | ac020054 22 | 0x48 : nop | 00000000 -------------------------------------------------------------------------------- /assignment-2/benchtest/bisection/bisection.out: -------------------------------------------------------------------------------- 1 | 0x0 : addi $v0, $0, 44 | 2002002c 2 | 0x4 : addi $a0, $0, 0 | 20040000 3 | 0x8 : addi $a1, $0, 31 | 2005001f 4 | 0xc : addi $s0, $0, 128 | 20100080 5 | 0x10 : mid: | 6 | 0x10 : add $a2, $a0, $a1 | 00853020 7 | 0x14 : sra $a2, $a2, 1 | 00063043 8 | 0x18 : sw $a2, 0($s0) | ae060000 9 | 0x1c : addi $s0, $s0, 4 | 22100004 10 | 0x20 : sll $a3, $a2, 2 | 00063880 11 | 0x24 : lw $v1, 0($a3) | 8ce30000 12 | 0x28 : slt $s1, $v1, $v0 | 0062882a 13 | 0x2c : bne $s1, $0, less | 14110003 14 | 0x30 : beq $v0, $v1, exit | 10620004 15 | 0x34 : add $a1, $a2, $0 | 00c02820 16 | 0x38 : j mid | 08000004 17 | 0x3c : less: | 18 | 0x3c : add $a0, $a2, $0 | 00c02020 19 | 0x40 : j mid | 08000004 20 | 0x44 : exit: | 21 | 0x44 : nop | 00000000 22 | 0x48 : nop | 00000000 23 | 0x4c : nop | 00000000 24 | 0x50 : nop | 00000000 -------------------------------------------------------------------------------- /assignment-2/benchtest/bubble sort/bubble sort.out: -------------------------------------------------------------------------------- 1 | 0x0 : add $t0, $0, $0 | 00004020 2 | 0x4 : addi $t3, $0, 128 | 200b0080 3 | 0x8 : For: | 4 | 0x8 : add $sp, $0, $t0 | 0008e820 5 | 0xc : lw $t4, 0($sp) | 8fac0000 6 | 0x10 : add $t5, $0, $sp | 001d6820 7 | 0x14 : for: | 8 | 0x14 : lw $t6, 0($sp) | 8fae0000 9 | 0x18 : slt $t7, $t6, $t4 | 01cc782a 10 | 0x1c : bne $t7, $0, ret | 140f0002 11 | 0x20 : add $t4, $0, $t6 | 000e6020 12 | 0x24 : add $t5, $sp, $0 | 03a06820 13 | 0x28 : ret: | 14 | 0x28 : addi $sp, $sp, 4 | 23bd0004 15 | 0x2c : bne $sp, $t3, for | 157dfff9 16 | 0x30 : addi $t3, $t3, -4 | 216bfffc 17 | 0x34 : lw $t8, 0($t3) | 8d780000 18 | 0x38 : sw $t4, 0($t3) | ad6c0000 19 | 0x3c : sw $t8, 0($t5) | adb80000 20 | 0x40 : bne $0, $t3, For | 1560fff1 21 | 0x44 : nop | 00000000 22 | 0x48 : nop | 00000000 23 | 0x4c : nop | 00000000 24 | 0x50 : nop | 00000000 -------------------------------------------------------------------------------- /assignment-3(I)/benchtest/bisection/bisection.out: -------------------------------------------------------------------------------- 1 | 0x0 : addi $v0, $0, 44 | 2002002c 2 | 0x4 : addi $a0, $0, 0 | 20040000 3 | 0x8 : addi $a1, $0, 31 | 2005001f 4 | 0xc : addi $s0, $0, 128 | 20100080 5 | 0x10 : mid: | 6 | 0x10 : add $a2, $a0, $a1 | 00853020 7 | 0x14 : sra $a2, $a2, 1 | 00063043 8 | 0x18 : sw $a2, 0($s0) | ae060000 9 | 0x1c : addi $s0, $s0, 4 | 22100004 10 | 0x20 : sll $a3, $a2, 2 | 00063880 11 | 0x24 : lw $v1, 0($a3) | 8ce30000 12 | 0x28 : slt $s1, $v1, $v0 | 0062882a 13 | 0x2c : bne $s1, $0, less | 14110003 14 | 0x30 : beq $v0, $v1, exit | 10620004 15 | 0x34 : add $a1, $a2, $0 | 00c02820 16 | 0x38 : j mid | 08000004 17 | 0x3c : less: | 18 | 0x3c : add $a0, $a2, $0 | 00c02020 19 | 0x40 : j mid | 08000004 20 | 0x44 : exit: | 21 | 0x44 : nop | 00000000 22 | 0x48 : nop | 00000000 23 | 0x4c : nop | 00000000 24 | 0x50 : nop | 00000000 -------------------------------------------------------------------------------- /assignment-3(I)/benchtest/bubble sort/bubble sort.out: -------------------------------------------------------------------------------- 1 | 0x0 : add $t0, $0, $0 | 00004020 2 | 0x4 : addi $t3, $0, 128 | 200b0080 3 | 0x8 : For: | 4 | 0x8 : add $sp, $0, $t0 | 0008e820 5 | 0xc : lw $t4, 0($sp) | 8fac0000 6 | 0x10 : add $t5, $0, $sp | 001d6820 7 | 0x14 : for: | 8 | 0x14 : lw $t6, 0($sp) | 8fae0000 9 | 0x18 : slt $t7, $t6, $t4 | 01cc782a 10 | 0x1c : bne $t7, $0, ret | 140f0002 11 | 0x20 : add $t4, $0, $t6 | 000e6020 12 | 0x24 : add $t5, $sp, $0 | 03a06820 13 | 0x28 : ret: | 14 | 0x28 : addi $sp, $sp, 4 | 23bd0004 15 | 0x2c : bne $sp, $t3, for | 157dfff9 16 | 0x30 : addi $t3, $t3, -4 | 216bfffc 17 | 0x34 : lw $t8, 0($t3) | 8d780000 18 | 0x38 : sw $t4, 0($t3) | ad6c0000 19 | 0x3c : sw $t8, 0($t5) | adb80000 20 | 0x40 : bne $0, $t3, For | 1560fff1 21 | 0x44 : nop | 00000000 22 | 0x48 : nop | 00000000 23 | 0x4c : nop | 00000000 24 | 0x50 : nop | 00000000 -------------------------------------------------------------------------------- /assignment-2/benchtest/ad hoc/ad hoc.out: -------------------------------------------------------------------------------- 1 | 0x0 : main: | 2 | 0x0 : addi $v0, $0, 5 | 20020005 3 | 0x4 : addi $v1, $0, 12 | 2003000c 4 | 0x8 : addi $a3, $v1, -9 | 2067fff7 5 | 0xc : or $a0, $a3, $v0 | 00e22025 6 | 0x10 : and $a1, $v1, $a0 | 00642824 7 | 0x14 : add $a1, $a1, $a0 | 00a42820 8 | 0x18 : beq $a3, $a1, end | 10a7000a 9 | 0x1c : slt $a0, $v1, $a0 | 0064202a 10 | 0x20 : beq $0, $a0, around | 10800001 11 | 0x24 : addi $a1, $0, 0 | 20050000 12 | 0x28 : around: | 13 | 0x28 : slt $a0, $a3, $v0 | 00e2202a 14 | 0x2c : add $a3, $a0, $a1 | 00853820 15 | 0x30 : sub $a3, $a3, $v0 | 00e23822 16 | 0x34 : sw $a3, 68($v1) | ac670044 17 | 0x38 : lw $v0, 80($0) | 8c020050 18 | 0x3c : j end | 08000011 19 | 0x40 : addi $v0, $0, 1 | 20020001 20 | 0x44 : end: | 21 | 0x44 : sw $v0, 84($0) | ac020054 22 | 0x48 : nop | 00000000 23 | 0x4c : nop | 00000000 24 | 0x50 : nop | 00000000 25 | 0x54 : nop | 00000000 -------------------------------------------------------------------------------- /assignment-3(I)/benchtest/ad hoc/ad hoc.out: -------------------------------------------------------------------------------- 1 | 0x0 : main: | 2 | 0x0 : addi $v0, $0, 5 | 20020005 3 | 0x4 : addi $v1, $0, 12 | 2003000c 4 | 0x8 : addi $a3, $v1, -9 | 2067fff7 5 | 0xc : or $a0, $a3, $v0 | 00e22025 6 | 0x10 : and $a1, $v1, $a0 | 00642824 7 | 0x14 : add $a1, $a1, $a0 | 00a42820 8 | 0x18 : beq $a3, $a1, end | 10a7000a 9 | 0x1c : slt $a0, $v1, $a0 | 0064202a 10 | 0x20 : beq $0, $a0, around | 10800001 11 | 0x24 : addi $a1, $0, 0 | 20050000 12 | 0x28 : around: | 13 | 0x28 : slt $a0, $a3, $v0 | 00e2202a 14 | 0x2c : add $a3, $a0, $a1 | 00853820 15 | 0x30 : sub $a3, $a3, $v0 | 00e23822 16 | 0x34 : sw $a3, 68($v1) | ac670044 17 | 0x38 : lw $v0, 80($0) | 8c020050 18 | 0x3c : j end | 08000011 19 | 0x40 : addi $v0, $0, 1 | 20020001 20 | 0x44 : end: | 21 | 0x44 : sw $v0, 84($0) | ac020054 22 | 0x48 : nop | 00000000 23 | 0x4c : nop | 00000000 24 | 0x50 : nop | 00000000 25 | 0x54 : nop | 00000000 -------------------------------------------------------------------------------- /assignment-3(I)/src/set.v: -------------------------------------------------------------------------------- 1 | `include "cache.vh" 2 | /** 3 | * ctls : control signals from cache_controller 4 | * addr : cache read/write address from processor 5 | * write_data : cache write data from processor 6 | * mread_data : data read from memory 7 | * 8 | * hit : whether cache set hits 9 | * dirty : from the cache line selected by addr (cache line's tag is equal to addr's tag) 10 | */ 11 | module set #( 12 | parameter TAG_WIDTH = `CACHE_T, 13 | OFFSET_WIDTH = `CACHE_B, 14 | LINES = `CACHE_E 15 | )( 16 | input clk, reset, 17 | input [4 + OFFSET_WIDTH-2:0] ctls, 18 | input [31:0] addr, write_data, mread_data, 19 | output hit, dirty, 20 | output [31:0] read_data 21 | ); 22 | 23 | wire w_en, set_valid, set_dirty, init, offsetSW; 24 | wire [OFFSET_WIDTH - 3:0] offset; 25 | 26 | // control signals will be assigned to the target line instance. 27 | assign {w_en, set_valid, set_dirty, offset, strategy_en, offset_sel} = ctls; 28 | 29 | /** 30 | * TODO: Your code here 31 | */ 32 | 33 | endmodule 34 | -------------------------------------------------------------------------------- /assignment-2/check.py: -------------------------------------------------------------------------------- 1 | import zipfile, sys, re, os 2 | 3 | pattern = re.compile(r'(^[0-9]*)') 4 | 5 | def check(zfile): 6 | zFile = zipfile.ZipFile(zfile, "r") 7 | stuId = pattern.match(zfile).group(0) 8 | print(stuId) 9 | cwd = os.getcwd() 10 | for zfile in zFile.namelist(): 11 | zFile.extract(zfile, cwd) 12 | zFile.close() 13 | 14 | if os.path.isdir(stuId): 15 | cwd = os.path.join(cwd, stuId) 16 | cwd = os.path.join(cwd, "Pipeline") 17 | if os.path.isdir(cwd): 18 | makefile = os.path.join(cwd, "makefile") 19 | benchtest = os.path.join(cwd, "benchtest") 20 | if os.path.isfile(makefile) == False: 21 | print("添加 makefile") 22 | elif os.path.isdir(benchtest) == False: 23 | print("添加 benchtest/") 24 | else: 25 | print("应该没啥问题了") 26 | else: 27 | print("项目名为 Pipeline") 28 | else: 29 | print("解压缩文件中需要包一层 %s/ 文件夹" %(stuId)) 30 | 31 | if __name__ == '__main__': 32 | for zfile in os.listdir(os.getcwd()): 33 | if zfile.find('.zip') != -1: 34 | check(zfile) 35 | -------------------------------------------------------------------------------- /assignment-1/benchtest/factorial/factorial.out: -------------------------------------------------------------------------------- 1 | 0x0 : addi $sp, $0, 128 | 201d0080 2 | 0x4 : addi $a0, $0, 5 | 20040005 3 | 0x8 : addi $a1, $0, 0 | 20050000 4 | 0xc : jal factorial | 0c000007 5 | 0x10 : sw $v0, 0($a1) | aca20000 6 | 0x14 : sll $v0, $v0, 1 | 00021040 7 | 0x18 : nop | 00000000 8 | 0x1c : | 9 | 0x1c : factorial: | 10 | 0x1c : addi $sp, $sp, -8 | 23bdfff8 11 | 0x20 : sw $a0, 4($sp) | afa40004 12 | 0x24 : sw $ra, 0($sp) | afbf0000 13 | 0x28 : addi $t0, $0, 2 | 20080002 14 | 0x2c : slt $t0, $a0, $t0 | 0088402a 15 | 0x30 : beq $t0, $0 ,else | 10080003 16 | 0x34 : addi $v0, $0, 1 | 20020001 17 | 0x38 : addi $sp, $sp, 8 | 23bd0008 18 | 0x3c : jr $ra | 03e00008 19 | 0x40 : else: | 20 | 0x40 : addi $a0, $a0, -1 | 2084ffff 21 | 0x44 : jal factorial | 0c000007 22 | 0x48 : lw $ra, 0($sp) | 8fbf0000 23 | 0x4c : lw $a0, 4($sp) | 8fa40004 24 | 0x50 : addi $sp, $sp, 8 | 23bd0008 25 | 0x54 : sw $v0, 0($a1) | aca20000 26 | 0x58 : add $v0, $a0, $v0 | 00821020 27 | 0x5c : addi $a1, $a1, 4 | 20a50004 28 | 0x60 : jr $ra | 03e00008 -------------------------------------------------------------------------------- /assignment-3(I)/benchtest/README.md: -------------------------------------------------------------------------------- 1 | This file is the same as the one in Pipeline. 2 | 3 | # MIPS Test Bench 4 | 5 | This is a testbench for MIPS CPU. You need to create a vivado project in this directory, thus there will be a `*.xpr` file in this directory. After creating the vivado project, please add `benchtest/cpu_tb.sv` as a simulation source file. 6 | 7 | Please change the value of `PATH_PREFIX` (default is empty `""`) in the 1st line of `cpu_tb.sv` to the absolute path to this project. 8 | 9 | Here are test files (`*.dat`) in `data` filled with machine code and corresponding answer files (`*.ans`) which are used in the simulation test. 10 | 11 | If you want to run the simulation test in command line on linux, you can configure the `makefile`: 12 | 13 | * `VIVADO_PATH` is the absolute path to your vivado executable file, eg. `/usr/local/Xilinx/Vivado/20xx.x/bin/vivado`. 14 | * `PROJECT_DIR` default is `.`, you can leave it alone. 15 | * `PROJECT_NAME` is the name of your vivado project which is equal to the name of `*.xpr` file without `.xpr` suffix. 16 | * `SIM` is the name of the simulation set you want to run. 17 | 18 | After proper configuration, you can use `make test` or simple `make` to run the simulation test. 19 | -------------------------------------------------------------------------------- /assignment-3(II)/src/bpb.v: -------------------------------------------------------------------------------- 1 | `include "bpb.vh" 2 | 3 | /** 4 | * ENTRIES : number of entries in the branch predictor buffer 5 | * TAG_WIDTH : index bits 6 | * instr_adr : if this address has been recorded, then CPU can go as the BPB directs 7 | * isbranch : in order to register the branch when first meeted 8 | * real_taken : whether this branch should be taken according to the semantics of the instructions 9 | * real_adr : where should this branch jumps to 10 | * predict_taken : whether this branch should be taken according to the prediction of our BPB 11 | * predict_adr : where should this branch jumps to if it's taken 12 | */ 13 | module bpb #( 14 | parameter ENTRIES = `BPB_E, 15 | parameter TAG_WIDTH = `BPB_T 16 | ) ( 17 | input clk, reset, stall, flush, 18 | input [TAG_WIDTH-1:0] instr_adr, 19 | 20 | input isbranch, 21 | // reality 22 | input real_taken, 23 | input [31:0] real_adr, 24 | // prediction 25 | output reg predict_taken, 26 | output reg [31:0] predict_adr 27 | ); 28 | 29 | /** 30 | * TODO: Your code here 31 | */ 32 | 33 | endmodule -------------------------------------------------------------------------------- /assignment-2/benchtest/testjr/testjr.in: -------------------------------------------------------------------------------- 1 | addi $sp, $0, 64 2 | addi $t0, $0, 10 3 | addi $t1, $0, 100 4 | 5 | test1: 6 | addi $a0, $0, 28 7 | addi $a0, $0, 36 8 | nop 9 | jr $a0 10 | sw $t0, 0($sp) 11 | j test2 12 | sw $t1, 0($sp) 13 | 14 | test2: 15 | addi $sp, $sp, -8 16 | addi $a0, $0, 56 17 | addi $a0, $0, 64 18 | jr $a0 19 | sw $t0, 0($sp) 20 | j test3 21 | sw $t1, 0($sp) 22 | 23 | test3: 24 | addi $sp, $sp, -8 25 | addi $a0, $0, 100 26 | sw $a0, 0($0) 27 | addi $a0, $0, 108 28 | sw $a0, 8($0) 29 | lw $a0, 0($0) 30 | lw $a0, 8($0) 31 | jr $a0 32 | sw $t0, 0($sp) 33 | j test4 34 | sw $t1, 0($sp) 35 | 36 | test4: 37 | addi $sp, $sp, -8 38 | addi $a0, $0, 144 39 | sw $a0, 16($0) 40 | addi $a0, $0, 136 41 | lw $a0, 16($0) 42 | jr $a0 43 | sw $t0, 0($sp) 44 | j test5 45 | sw $t1, 0($sp) 46 | 47 | test5: 48 | addi $t0, $0, 6 49 | sw $t0, 0($0) 50 | add $sp, $0, $0 51 | and $t1, $t1, $0 52 | Again: 53 | addi $t1, $t1, 6 54 | lw $t0, 0($sp) 55 | beq $t0, $t1, Again 56 | sw $t1, 4($0) 57 | 58 | test6: 59 | addi $t0, $0, 220 60 | sw $t0, 0($0) 61 | addi $t0, $0, 240 62 | sw $t0, 4($0) 63 | and $sp, $sp, $0 64 | and $t0, $t0, $0 65 | sw $0, 24($0) 66 | lw $t0, 0($sp) 67 | jr $t0 68 | sw $t0, 80($sp) 69 | lw $t0, 4($sp) 70 | addi $t0, $t0, -4 71 | jr $t0 72 | sw $t0, 84($sp) 73 | sw $t0, 12($0) 74 | nop 75 | nop 76 | nop 77 | nop 78 | -------------------------------------------------------------------------------- /assignment-3(I)/benchtest/testjr/testjr.in: -------------------------------------------------------------------------------- 1 | addi $sp, $0, 64 2 | addi $t0, $0, 10 3 | addi $t1, $0, 100 4 | 5 | test1: 6 | addi $a0, $0, 28 7 | addi $a0, $0, 36 8 | nop 9 | jr $a0 10 | sw $t0, 0($sp) 11 | j test2 12 | sw $t1, 0($sp) 13 | 14 | test2: 15 | addi $sp, $sp, -8 16 | addi $a0, $0, 56 17 | addi $a0, $0, 64 18 | jr $a0 19 | sw $t0, 0($sp) 20 | j test3 21 | sw $t1, 0($sp) 22 | 23 | test3: 24 | addi $sp, $sp, -8 25 | addi $a0, $0, 100 26 | sw $a0, 0($0) 27 | addi $a0, $0, 108 28 | sw $a0, 8($0) 29 | lw $a0, 0($0) 30 | lw $a0, 8($0) 31 | jr $a0 32 | sw $t0, 0($sp) 33 | j test4 34 | sw $t1, 0($sp) 35 | 36 | test4: 37 | addi $sp, $sp, -8 38 | addi $a0, $0, 144 39 | sw $a0, 16($0) 40 | addi $a0, $0, 136 41 | lw $a0, 16($0) 42 | jr $a0 43 | sw $t0, 0($sp) 44 | j test5 45 | sw $t1, 0($sp) 46 | 47 | test5: 48 | addi $t0, $0, 6 49 | sw $t0, 0($0) 50 | add $sp, $0, $0 51 | and $t1, $t1, $0 52 | Again: 53 | addi $t1, $t1, 6 54 | lw $t0, 0($sp) 55 | beq $t0, $t1, Again 56 | sw $t1, 4($0) 57 | 58 | test6: 59 | addi $t0, $0, 220 60 | sw $t0, 0($0) 61 | addi $t0, $0, 240 62 | sw $t0, 4($0) 63 | and $sp, $sp, $0 64 | and $t0, $t0, $0 65 | sw $0, 24($0) 66 | lw $t0, 0($sp) 67 | jr $t0 68 | sw $t0, 80($sp) 69 | lw $t0, 4($sp) 70 | addi $t0, $t0, -4 71 | jr $t0 72 | sw $t0, 84($sp) 73 | sw $t0, 12($0) 74 | nop 75 | nop 76 | nop 77 | nop 78 | -------------------------------------------------------------------------------- /assignment-2/benchtest/factorial/factorial.out: -------------------------------------------------------------------------------- 1 | 0x0 : addi $sp, $0, 128 | 201d0080 2 | 0x4 : addi $a0, $0, 5 | 20040005 3 | 0x8 : addi $a1, $0, 0 | 20050000 4 | 0xc : jal factorial | 0c00000a 5 | 0x10 : sw $v0, 0($a1) | aca20000 6 | 0x14 : sll $v0, $v0, 1 | 00021040 7 | 0x18 : nop | 00000000 8 | 0x1c : nop | 00000000 9 | 0x20 : nop | 00000000 10 | 0x24 : nop | 00000000 11 | 0x28 : | 12 | 0x28 : factorial: | 13 | 0x28 : addi $sp, $sp, -8 | 23bdfff8 14 | 0x2c : sw $a0, 4($sp) | afa40004 15 | 0x30 : sw $ra, 0($sp) | afbf0000 16 | 0x34 : addi $t0, $0, 2 | 20080002 17 | 0x38 : slt $t0, $a0, $t0 | 0088402a 18 | 0x3c : beq $t0, $0 ,else | 10080003 19 | 0x40 : addi $v0, $0, 1 | 20020001 20 | 0x44 : addi $sp, $sp, 8 | 23bd0008 21 | 0x48 : jr $ra | 03e00008 22 | 0x4c : else: | 23 | 0x4c : addi $a0, $a0, -1 | 2084ffff 24 | 0x50 : jal factorial | 0c00000a 25 | 0x54 : lw $ra, 0($sp) | 8fbf0000 26 | 0x58 : lw $a0, 4($sp) | 8fa40004 27 | 0x5c : addi $sp, $sp, 8 | 23bd0008 28 | 0x60 : sw $v0, 0($a1) | aca20000 29 | 0x64 : add $v0, $a0, $v0 | 00821020 30 | 0x68 : addi $a1, $a1, 4 | 20a50004 31 | 0x6c : jr $ra | 03e00008 -------------------------------------------------------------------------------- /assignment-3(I)/benchtest/factorial/factorial.out: -------------------------------------------------------------------------------- 1 | 0x0 : addi $sp, $0, 128 | 201d0080 2 | 0x4 : addi $a0, $0, 5 | 20040005 3 | 0x8 : addi $a1, $0, 0 | 20050000 4 | 0xc : jal factorial | 0c00000a 5 | 0x10 : sw $v0, 0($a1) | aca20000 6 | 0x14 : sll $v0, $v0, 1 | 00021040 7 | 0x18 : nop | 00000000 8 | 0x1c : nop | 00000000 9 | 0x20 : nop | 00000000 10 | 0x24 : nop | 00000000 11 | 0x28 : | 12 | 0x28 : factorial: | 13 | 0x28 : addi $sp, $sp, -8 | 23bdfff8 14 | 0x2c : sw $a0, 4($sp) | afa40004 15 | 0x30 : sw $ra, 0($sp) | afbf0000 16 | 0x34 : addi $t0, $0, 2 | 20080002 17 | 0x38 : slt $t0, $a0, $t0 | 0088402a 18 | 0x3c : beq $t0, $0 ,else | 10080003 19 | 0x40 : addi $v0, $0, 1 | 20020001 20 | 0x44 : addi $sp, $sp, 8 | 23bd0008 21 | 0x48 : jr $ra | 03e00008 22 | 0x4c : else: | 23 | 0x4c : addi $a0, $a0, -1 | 2084ffff 24 | 0x50 : jal factorial | 0c00000a 25 | 0x54 : lw $ra, 0($sp) | 8fbf0000 26 | 0x58 : lw $a0, 4($sp) | 8fa40004 27 | 0x5c : addi $sp, $sp, 8 | 23bd0008 28 | 0x60 : sw $v0, 0($a1) | aca20000 29 | 0x64 : add $v0, $a0, $v0 | 00821020 30 | 0x68 : addi $a1, $a1, 4 | 20a50004 31 | 0x6c : jr $ra | 03e00008 -------------------------------------------------------------------------------- /assignment-2/benchtest/mutual recursion/mutual recursion.txt: -------------------------------------------------------------------------------- 1 | RAM[0] <= 32'h20100000; 2 | RAM[1] <= 32'h20080066; 3 | RAM[2] <= 32'hae080000; 4 | RAM[3] <= 32'h20080067; 5 | RAM[4] <= 32'hae080004; 6 | RAM[5] <= 32'h20080066; 7 | RAM[6] <= 32'hae080008; 8 | RAM[7] <= 32'h20080067; 9 | RAM[8] <= 32'hae08000c; 10 | RAM[9] <= 32'h20080061; 11 | RAM[10] <= 32'hae080010; 12 | RAM[11] <= 32'h201d0080; 13 | RAM[12] <= 32'h20040000; 14 | RAM[13] <= 32'h0c000013; 15 | RAM[14] <= 32'h20510000; 16 | RAM[15] <= 32'h00000000; 17 | RAM[16] <= 32'h00000000; 18 | RAM[17] <= 32'h00000000; 19 | RAM[18] <= 32'h00000000; 20 | RAM[19] <= 32'h23bdfff8; 21 | RAM[20] <= 32'hafa40004; 22 | RAM[21] <= 32'hafbf0000; 23 | RAM[22] <= 32'h0004c880; 24 | RAM[23] <= 32'h0219c820; 25 | RAM[24] <= 32'h8f280000; 26 | RAM[25] <= 32'h20090061; 27 | RAM[26] <= 32'h15280002; 28 | RAM[27] <= 32'h20820001; 29 | RAM[28] <= 32'h08000023; 30 | RAM[29] <= 32'h20090066; 31 | RAM[30] <= 32'h15280003; 32 | RAM[31] <= 32'h20840001; 33 | RAM[32] <= 32'h0c000027; 34 | RAM[33] <= 32'h08000023; 35 | RAM[34] <= 32'h2002ffff; 36 | RAM[35] <= 32'h8fbf0000; 37 | RAM[36] <= 32'h8fa40004; 38 | RAM[37] <= 32'h23bd0008; 39 | RAM[38] <= 32'h03e00008; 40 | RAM[39] <= 32'h23bdfff8; 41 | RAM[40] <= 32'hafa40004; 42 | RAM[41] <= 32'hafbf0000; 43 | RAM[42] <= 32'h0004c880; 44 | RAM[43] <= 32'h0219c820; 45 | RAM[44] <= 32'h8f280000; 46 | RAM[45] <= 32'h20090067; 47 | RAM[46] <= 32'h15280003; 48 | RAM[47] <= 32'h20840001; 49 | RAM[48] <= 32'h0c000013; 50 | RAM[49] <= 32'h08000033; 51 | RAM[50] <= 32'h2002ffff; 52 | RAM[51] <= 32'h8fbf0000; 53 | RAM[52] <= 32'h8fa40004; 54 | RAM[53] <= 32'h23bd0008; 55 | RAM[54] <= 32'h03e00008; -------------------------------------------------------------------------------- /assignment-3(I)/benchtest/mutual recursion/mutual recursion.txt: -------------------------------------------------------------------------------- 1 | RAM[0] <= 32'h20100000; 2 | RAM[1] <= 32'h20080066; 3 | RAM[2] <= 32'hae080000; 4 | RAM[3] <= 32'h20080067; 5 | RAM[4] <= 32'hae080004; 6 | RAM[5] <= 32'h20080066; 7 | RAM[6] <= 32'hae080008; 8 | RAM[7] <= 32'h20080067; 9 | RAM[8] <= 32'hae08000c; 10 | RAM[9] <= 32'h20080061; 11 | RAM[10] <= 32'hae080010; 12 | RAM[11] <= 32'h201d0080; 13 | RAM[12] <= 32'h20040000; 14 | RAM[13] <= 32'h0c000013; 15 | RAM[14] <= 32'h20510000; 16 | RAM[15] <= 32'h00000000; 17 | RAM[16] <= 32'h00000000; 18 | RAM[17] <= 32'h00000000; 19 | RAM[18] <= 32'h00000000; 20 | RAM[19] <= 32'h23bdfff8; 21 | RAM[20] <= 32'hafa40004; 22 | RAM[21] <= 32'hafbf0000; 23 | RAM[22] <= 32'h0004c880; 24 | RAM[23] <= 32'h0219c820; 25 | RAM[24] <= 32'h8f280000; 26 | RAM[25] <= 32'h20090061; 27 | RAM[26] <= 32'h15280002; 28 | RAM[27] <= 32'h20820001; 29 | RAM[28] <= 32'h08000023; 30 | RAM[29] <= 32'h20090066; 31 | RAM[30] <= 32'h15280003; 32 | RAM[31] <= 32'h20840001; 33 | RAM[32] <= 32'h0c000027; 34 | RAM[33] <= 32'h08000023; 35 | RAM[34] <= 32'h2002ffff; 36 | RAM[35] <= 32'h8fbf0000; 37 | RAM[36] <= 32'h8fa40004; 38 | RAM[37] <= 32'h23bd0008; 39 | RAM[38] <= 32'h03e00008; 40 | RAM[39] <= 32'h23bdfff8; 41 | RAM[40] <= 32'hafa40004; 42 | RAM[41] <= 32'hafbf0000; 43 | RAM[42] <= 32'h0004c880; 44 | RAM[43] <= 32'h0219c820; 45 | RAM[44] <= 32'h8f280000; 46 | RAM[45] <= 32'h20090067; 47 | RAM[46] <= 32'h15280003; 48 | RAM[47] <= 32'h20840001; 49 | RAM[48] <= 32'h0c000013; 50 | RAM[49] <= 32'h08000033; 51 | RAM[50] <= 32'h2002ffff; 52 | RAM[51] <= 32'h8fbf0000; 53 | RAM[52] <= 32'h8fa40004; 54 | RAM[53] <= 32'h23bd0008; 55 | RAM[54] <= 32'h03e00008; -------------------------------------------------------------------------------- /assignment-3(I)/src/cache.v: -------------------------------------------------------------------------------- 1 | `include "cache.vh" 2 | 3 | /** 4 | * NOTE: The sum of TAG_WIDTH, SET_WIDTH and OFFSET_WIDTH should be 32 5 | * 6 | * TAG_WIDTH : (t) tag bits 7 | * SET_WIDTH : (s) set index bits, the number of sets is 2**SET_WIDTH 8 | * OFFSET_WIDTH : (b) block offset bits 9 | * LINES : number of lines per set 10 | * 11 | * stall : inorder to synchronize instruction memroy cache and data memroy cache, you may need this so that two caches will write data at most once per instruction respectively. 12 | * 13 | * input_ready : whether input data from processor are ready 14 | * addr : cache read/write address from processor 15 | * write_data : cache write data from processor 16 | * w_en : cache write enable 17 | * hit : whether cache hits 18 | * read_data : data read from cache 19 | * 20 | * maddr : memory address 21 | * mwrite_data : data written to memory 22 | * m_wen : memory write enable 23 | * mread_data : data read from memory 24 | */ 25 | module cache #( 26 | parameter TAG_WIDTH = `CACHE_T, 27 | SET_WIDTH = `CACHE_S, 28 | OFFSET_WIDTH = `CACHE_B, 29 | LINES = `CACHE_E 30 | )( 31 | input clk, reset, stall, 32 | 33 | // interface with CPU 34 | input input_ready, 35 | input [31:0] addr, write_data, 36 | input w_en, 37 | output hit, 38 | output [31:0] read_data, 39 | 40 | // interface with memory 41 | output [31:0] maddr, mwrite_data, 42 | output m_wen, 43 | input [31:0] mread_data 44 | /* input mready // memory ready ? */ 45 | ); 46 | 47 | /** 48 | * TODO: Your code here 49 | */ 50 | 51 | endmodule 52 | -------------------------------------------------------------------------------- /assignment-1/benchtest/bubble sort/bubble sort.run: -------------------------------------------------------------------------------- 1 | [0x0000007c]=0x0000005f 2 | [0x00000008]=0x0000004a 3 | [0x00000078]=0x00000052 4 | [0x0000000c]=0x00000026 5 | [0x00000074]=0x00000051 6 | [0x00000020]=0x00000024 7 | [0x00000070]=0x0000004b 8 | [0x00000058]=0x00000008 9 | [0x0000006c]=0x0000004b 10 | [0x00000050]=0x0000000d 11 | [0x00000068]=0x0000004a 12 | [0x00000010]=0x00000012 13 | [0x00000064]=0x0000004a 14 | [0x00000008]=0x0000003e 15 | [0x00000060]=0x00000049 16 | [0x00000034]=0x00000028 17 | [0x0000005c]=0x00000046 18 | [0x00000040]=0x00000007 19 | [0x00000058]=0x00000044 20 | [0x00000044]=0x00000008 21 | [0x00000054]=0x00000042 22 | [0x00000014]=0x00000030 23 | [0x00000050]=0x0000003e 24 | [0x00000008]=0x0000000d 25 | [0x0000004c]=0x00000034 26 | [0x00000004]=0x0000002c 27 | [0x00000048]=0x00000030 28 | [0x00000014]=0x00000019 29 | [0x00000044]=0x0000002c 30 | [0x00000004]=0x00000008 31 | [0x00000040]=0x00000028 32 | [0x00000034]=0x00000007 33 | [0x0000003c]=0x00000027 34 | [0x0000003c]=0x00000027 35 | [0x00000038]=0x00000026 36 | [0x0000000c]=0x0000001d 37 | [0x00000034]=0x00000024 38 | [0x00000020]=0x00000007 39 | [0x00000030]=0x0000001f 40 | [0x00000030]=0x0000001f 41 | [0x0000002c]=0x0000001d 42 | [0x0000000c]=0x0000001c 43 | [0x00000028]=0x0000001c 44 | [0x0000000c]=0x00000002 45 | [0x00000024]=0x0000001b 46 | [0x0000001c]=0x00000009 47 | [0x00000020]=0x00000019 48 | [0x00000014]=0x00000007 49 | [0x0000001c]=0x00000012 50 | [0x00000010]=0x00000009 51 | [0x00000018]=0x0000000d 52 | [0x00000008]=0x00000001 53 | [0x00000014]=0x00000009 54 | [0x00000010]=0x00000007 55 | [0x00000010]=0x00000008 56 | [0x00000004]=0x00000007 57 | [0x0000000c]=0x00000007 58 | [0x00000004]=0x00000002 59 | [0x00000008]=0x00000007 60 | [0x00000000]=0x00000001 61 | [0x00000004]=0x00000002 62 | [0x00000004]=0x00000002 63 | [0x00000000]=0x00000001 64 | [0x00000000]=0x00000001 -------------------------------------------------------------------------------- /assignment-2/benchtest/bubble sort/bubble sort.run: -------------------------------------------------------------------------------- 1 | [0x0000007c]=0x0000005f 2 | [0x00000008]=0x0000004a 3 | [0x00000078]=0x00000052 4 | [0x0000000c]=0x00000026 5 | [0x00000074]=0x00000051 6 | [0x00000020]=0x00000024 7 | [0x00000070]=0x0000004b 8 | [0x00000058]=0x00000008 9 | [0x0000006c]=0x0000004b 10 | [0x00000050]=0x0000000d 11 | [0x00000068]=0x0000004a 12 | [0x00000010]=0x00000012 13 | [0x00000064]=0x0000004a 14 | [0x00000008]=0x0000003e 15 | [0x00000060]=0x00000049 16 | [0x00000034]=0x00000028 17 | [0x0000005c]=0x00000046 18 | [0x00000040]=0x00000007 19 | [0x00000058]=0x00000044 20 | [0x00000044]=0x00000008 21 | [0x00000054]=0x00000042 22 | [0x00000014]=0x00000030 23 | [0x00000050]=0x0000003e 24 | [0x00000008]=0x0000000d 25 | [0x0000004c]=0x00000034 26 | [0x00000004]=0x0000002c 27 | [0x00000048]=0x00000030 28 | [0x00000014]=0x00000019 29 | [0x00000044]=0x0000002c 30 | [0x00000004]=0x00000008 31 | [0x00000040]=0x00000028 32 | [0x00000034]=0x00000007 33 | [0x0000003c]=0x00000027 34 | [0x0000003c]=0x00000027 35 | [0x00000038]=0x00000026 36 | [0x0000000c]=0x0000001d 37 | [0x00000034]=0x00000024 38 | [0x00000020]=0x00000007 39 | [0x00000030]=0x0000001f 40 | [0x00000030]=0x0000001f 41 | [0x0000002c]=0x0000001d 42 | [0x0000000c]=0x0000001c 43 | [0x00000028]=0x0000001c 44 | [0x0000000c]=0x00000002 45 | [0x00000024]=0x0000001b 46 | [0x0000001c]=0x00000009 47 | [0x00000020]=0x00000019 48 | [0x00000014]=0x00000007 49 | [0x0000001c]=0x00000012 50 | [0x00000010]=0x00000009 51 | [0x00000018]=0x0000000d 52 | [0x00000008]=0x00000001 53 | [0x00000014]=0x00000009 54 | [0x00000010]=0x00000007 55 | [0x00000010]=0x00000008 56 | [0x00000004]=0x00000007 57 | [0x0000000c]=0x00000007 58 | [0x00000004]=0x00000002 59 | [0x00000008]=0x00000007 60 | [0x00000000]=0x00000001 61 | [0x00000004]=0x00000002 62 | [0x00000004]=0x00000002 63 | [0x00000000]=0x00000001 64 | [0x00000000]=0x00000001 -------------------------------------------------------------------------------- /assignment-3(I)/benchtest/bubble sort/bubble sort.run: -------------------------------------------------------------------------------- 1 | [0x0000007c]=0x0000005f 2 | [0x00000008]=0x0000004a 3 | [0x00000078]=0x00000052 4 | [0x0000000c]=0x00000026 5 | [0x00000074]=0x00000051 6 | [0x00000020]=0x00000024 7 | [0x00000070]=0x0000004b 8 | [0x00000058]=0x00000008 9 | [0x0000006c]=0x0000004b 10 | [0x00000050]=0x0000000d 11 | [0x00000068]=0x0000004a 12 | [0x00000010]=0x00000012 13 | [0x00000064]=0x0000004a 14 | [0x00000008]=0x0000003e 15 | [0x00000060]=0x00000049 16 | [0x00000034]=0x00000028 17 | [0x0000005c]=0x00000046 18 | [0x00000040]=0x00000007 19 | [0x00000058]=0x00000044 20 | [0x00000044]=0x00000008 21 | [0x00000054]=0x00000042 22 | [0x00000014]=0x00000030 23 | [0x00000050]=0x0000003e 24 | [0x00000008]=0x0000000d 25 | [0x0000004c]=0x00000034 26 | [0x00000004]=0x0000002c 27 | [0x00000048]=0x00000030 28 | [0x00000014]=0x00000019 29 | [0x00000044]=0x0000002c 30 | [0x00000004]=0x00000008 31 | [0x00000040]=0x00000028 32 | [0x00000034]=0x00000007 33 | [0x0000003c]=0x00000027 34 | [0x0000003c]=0x00000027 35 | [0x00000038]=0x00000026 36 | [0x0000000c]=0x0000001d 37 | [0x00000034]=0x00000024 38 | [0x00000020]=0x00000007 39 | [0x00000030]=0x0000001f 40 | [0x00000030]=0x0000001f 41 | [0x0000002c]=0x0000001d 42 | [0x0000000c]=0x0000001c 43 | [0x00000028]=0x0000001c 44 | [0x0000000c]=0x00000002 45 | [0x00000024]=0x0000001b 46 | [0x0000001c]=0x00000009 47 | [0x00000020]=0x00000019 48 | [0x00000014]=0x00000007 49 | [0x0000001c]=0x00000012 50 | [0x00000010]=0x00000009 51 | [0x00000018]=0x0000000d 52 | [0x00000008]=0x00000001 53 | [0x00000014]=0x00000009 54 | [0x00000010]=0x00000007 55 | [0x00000010]=0x00000008 56 | [0x00000004]=0x00000007 57 | [0x0000000c]=0x00000007 58 | [0x00000004]=0x00000002 59 | [0x00000008]=0x00000007 60 | [0x00000000]=0x00000001 61 | [0x00000004]=0x00000002 62 | [0x00000004]=0x00000002 63 | [0x00000000]=0x00000001 64 | [0x00000000]=0x00000001 -------------------------------------------------------------------------------- /assignment-2/benchtest/testjr/testjr.txt: -------------------------------------------------------------------------------- 1 | RAM[0] <= 32'h201d0040; 2 | RAM[1] <= 32'h2008000a; 3 | RAM[2] <= 32'h20090064; 4 | RAM[3] <= 32'h2004001c; 5 | RAM[4] <= 32'h20040024; 6 | RAM[5] <= 32'h00000000; 7 | RAM[6] <= 32'h00800008; 8 | RAM[7] <= 32'hafa80000; 9 | RAM[8] <= 32'h0800000a; 10 | RAM[9] <= 32'hafa90000; 11 | RAM[10] <= 32'h23bdfff8; 12 | RAM[11] <= 32'h20040038; 13 | RAM[12] <= 32'h20040040; 14 | RAM[13] <= 32'h00800008; 15 | RAM[14] <= 32'hafa80000; 16 | RAM[15] <= 32'h08000011; 17 | RAM[16] <= 32'hafa90000; 18 | RAM[17] <= 32'h23bdfff8; 19 | RAM[18] <= 32'h20040064; 20 | RAM[19] <= 32'hac040000; 21 | RAM[20] <= 32'h2004006c; 22 | RAM[21] <= 32'hac040008; 23 | RAM[22] <= 32'h8c040000; 24 | RAM[23] <= 32'h8c040008; 25 | RAM[24] <= 32'h00800008; 26 | RAM[25] <= 32'hafa80000; 27 | RAM[26] <= 32'h0800001c; 28 | RAM[27] <= 32'hafa90000; 29 | RAM[28] <= 32'h23bdfff8; 30 | RAM[29] <= 32'h20040090; 31 | RAM[30] <= 32'hac040010; 32 | RAM[31] <= 32'h20040088; 33 | RAM[32] <= 32'h8c040010; 34 | RAM[33] <= 32'h00800008; 35 | RAM[34] <= 32'hafa80000; 36 | RAM[35] <= 32'h08000025; 37 | RAM[36] <= 32'hafa90000; 38 | RAM[37] <= 32'h20080006; 39 | RAM[38] <= 32'hac080000; 40 | RAM[39] <= 32'h0000e820; 41 | RAM[40] <= 32'h01204824; 42 | RAM[41] <= 32'h21290006; 43 | RAM[42] <= 32'h8fa80000; 44 | RAM[43] <= 32'h1128fffd; 45 | RAM[44] <= 32'hac090004; 46 | RAM[45] <= 32'h200800dc; 47 | RAM[46] <= 32'hac080000; 48 | RAM[47] <= 32'h200800f0; 49 | RAM[48] <= 32'hac080004; 50 | RAM[49] <= 32'h03a0e824; 51 | RAM[50] <= 32'h01004024; 52 | RAM[51] <= 32'hac000018; 53 | RAM[52] <= 32'h8fa80000; 54 | RAM[53] <= 32'h01000008; 55 | RAM[54] <= 32'hafa80050; 56 | RAM[55] <= 32'h8fa80004; 57 | RAM[56] <= 32'h2108fffc; 58 | RAM[57] <= 32'h01000008; 59 | RAM[58] <= 32'hafa80054; 60 | RAM[59] <= 32'hac08000c; 61 | RAM[60] <= 32'h00000000; 62 | RAM[61] <= 32'h00000000; 63 | RAM[62] <= 32'h00000000; 64 | RAM[63] <= 32'h00000000; -------------------------------------------------------------------------------- /assignment-3(I)/benchtest/testjr/testjr.txt: -------------------------------------------------------------------------------- 1 | RAM[0] <= 32'h201d0040; 2 | RAM[1] <= 32'h2008000a; 3 | RAM[2] <= 32'h20090064; 4 | RAM[3] <= 32'h2004001c; 5 | RAM[4] <= 32'h20040024; 6 | RAM[5] <= 32'h00000000; 7 | RAM[6] <= 32'h00800008; 8 | RAM[7] <= 32'hafa80000; 9 | RAM[8] <= 32'h0800000a; 10 | RAM[9] <= 32'hafa90000; 11 | RAM[10] <= 32'h23bdfff8; 12 | RAM[11] <= 32'h20040038; 13 | RAM[12] <= 32'h20040040; 14 | RAM[13] <= 32'h00800008; 15 | RAM[14] <= 32'hafa80000; 16 | RAM[15] <= 32'h08000011; 17 | RAM[16] <= 32'hafa90000; 18 | RAM[17] <= 32'h23bdfff8; 19 | RAM[18] <= 32'h20040064; 20 | RAM[19] <= 32'hac040000; 21 | RAM[20] <= 32'h2004006c; 22 | RAM[21] <= 32'hac040008; 23 | RAM[22] <= 32'h8c040000; 24 | RAM[23] <= 32'h8c040008; 25 | RAM[24] <= 32'h00800008; 26 | RAM[25] <= 32'hafa80000; 27 | RAM[26] <= 32'h0800001c; 28 | RAM[27] <= 32'hafa90000; 29 | RAM[28] <= 32'h23bdfff8; 30 | RAM[29] <= 32'h20040090; 31 | RAM[30] <= 32'hac040010; 32 | RAM[31] <= 32'h20040088; 33 | RAM[32] <= 32'h8c040010; 34 | RAM[33] <= 32'h00800008; 35 | RAM[34] <= 32'hafa80000; 36 | RAM[35] <= 32'h08000025; 37 | RAM[36] <= 32'hafa90000; 38 | RAM[37] <= 32'h20080006; 39 | RAM[38] <= 32'hac080000; 40 | RAM[39] <= 32'h0000e820; 41 | RAM[40] <= 32'h01204824; 42 | RAM[41] <= 32'h21290006; 43 | RAM[42] <= 32'h8fa80000; 44 | RAM[43] <= 32'h1128fffd; 45 | RAM[44] <= 32'hac090004; 46 | RAM[45] <= 32'h200800dc; 47 | RAM[46] <= 32'hac080000; 48 | RAM[47] <= 32'h200800f0; 49 | RAM[48] <= 32'hac080004; 50 | RAM[49] <= 32'h03a0e824; 51 | RAM[50] <= 32'h01004024; 52 | RAM[51] <= 32'hac000018; 53 | RAM[52] <= 32'h8fa80000; 54 | RAM[53] <= 32'h01000008; 55 | RAM[54] <= 32'hafa80050; 56 | RAM[55] <= 32'h8fa80004; 57 | RAM[56] <= 32'h2108fffc; 58 | RAM[57] <= 32'h01000008; 59 | RAM[58] <= 32'hafa80054; 60 | RAM[59] <= 32'hac08000c; 61 | RAM[60] <= 32'h00000000; 62 | RAM[61] <= 32'h00000000; 63 | RAM[62] <= 32'h00000000; 64 | RAM[63] <= 32'h00000000; -------------------------------------------------------------------------------- /assignment-3(I)/benchtest/random write/random write.ans: -------------------------------------------------------------------------------- 1 | 00000040 2 | 0000001f 3 | 00000013 4 | 0000001e 5 | 00000000 6 | 0000001f 7 | 0000001b 8 | 0000001a 9 | 00000015 10 | 0000001f 11 | 00000015 12 | 0000001e 13 | 0000001b 14 | 0000001f 15 | 00000000 16 | 0000001d 17 | 00000013 18 | 0000001e 19 | 00000011 20 | 0000001b 21 | 0000001d 22 | 00000014 23 | 00000017 24 | 00000000 25 | 00000000 26 | 0000001e 27 | 0000001b 28 | 0000001d 29 | 00000000 30 | 0000001c 31 | 00000000 32 | 0000001a 33 | 0000001d 34 | 0000001e 35 | 00000019 36 | 0000001a 37 | 0000001f 38 | 00000019 39 | 00000000 40 | 0000001b 41 | 0000001f 42 | 0000001e 43 | 00000017 44 | 00000011 45 | 0000001f 46 | 0000001c 47 | 0000001b 48 | 00000000 49 | 0000001f 50 | 0000001d 51 | 00000015 52 | 00000016 53 | 00000015 54 | 0000001b 55 | 00000015 56 | 0000001e 57 | 0000001d 58 | 0000001c 59 | 00000000 60 | 0000001a 61 | 00000011 62 | 0000001d 63 | 00000019 64 | 0000001e 65 | 00000000 66 | 00000018 67 | 0000001b 68 | 0000001f 69 | 00000017 70 | 0000001c 71 | 00000000 72 | 0000001f 73 | 00000000 74 | 0000001d 75 | 00000000 76 | 0000001f 77 | 00000000 78 | 00000016 79 | 00000017 80 | 0000001f 81 | 0000001b 82 | 00000019 83 | 00000000 84 | 0000001a 85 | 00000019 86 | 0000001e 87 | 00000011 88 | 0000001a 89 | 00000000 90 | 0000001c 91 | 0000001d 92 | 00000017 93 | 00000015 94 | 0000001e 95 | 00000015 96 | 00000016 97 | 00000015 98 | 0000001c 99 | 0000001f 100 | 00000016 101 | 0000001b 102 | 0000001e 103 | 0000001f 104 | 00000011 105 | 00000017 106 | 00000018 107 | 0000001f 108 | 0000001b 109 | 00000000 110 | 0000001e 111 | 0000001f 112 | 0000001a 113 | 00000019 114 | 0000001c 115 | 0000001d 116 | 0000001e 117 | 00000000 118 | 0000001c 119 | 00000000 120 | 0000001d 121 | 0000001b 122 | 00000018 123 | 00000000 124 | 0000001e 125 | 00000017 126 | 00000013 127 | 0000001d 128 | 0000001b 129 | 00000011 130 | -------------------------------------------------------------------------------- /assignment-2/benchtest/mutual recursion/mutual recursion.in: -------------------------------------------------------------------------------- 1 | # 在编译原理的语法分析中，很多文法都是递归形式给出的。 2 | # 假设有如下文法： 3 | # G[F]: 4 | # F → fG | a 5 | # G → gF 6 | # 判断字符串 a 是否满足的程序如下： 7 | # 8 | # int F(int pos) 9 | # { 10 | # if(a[pos] == 'a') return pos+1; 11 | # if(a[pos] == 'f') return G(pos+1); 12 | # return -1; 13 | # } 14 | # 15 | # int G(int pos) 16 | # { 17 | # if(a[pos] == 'g') return F(pos+1); 18 | # return -1; 19 | # } 20 | # b = F(0); 21 | 22 | # 将字符串"fgfga"置入从0x00000000($s0)开始的空间 23 | # 因为不支持sb指令，所以用sw代替 24 | addi $s0, $0, 0 25 | addi $t0, $0, 102 26 | sw $t0, 0($s0) 27 | addi $t0, $0, 103 28 | sw $t0, 4($s0) 29 | addi $t0, $0, 102 30 | sw $t0, 8($s0) 31 | addi $t0, $0, 103 32 | sw $t0, 12($s0) 33 | addi $t0, $0, 97 34 | sw $t0, 16($s0) 35 | # 初始化栈指针 36 | addi $sp, $0, 128 37 | 38 | # 调用F(0)。调用返回后，将返回值($v0)存入变量b($s1)。 39 | addi $a0, $0, 0 40 | jal F 41 | addi $s1, $v0, 0 42 | nop 43 | nop 44 | nop 45 | nop 46 | 47 | F: 48 | # 申请栈帧空间，存储保留寄存器 49 | addi $sp, $sp, -8 50 | sw $a0, 4($sp) 51 | sw $ra, 0($sp) 52 | 53 | # 读取a[pos] 54 | sll $t9, $a0, 2 55 | add $t9, $s0, $t9 56 | lw $t0, 0($t9) 57 | 58 | # 第一个if语句 59 | addi $t1, $0, 97 60 | bne $t0, $t1, F1 61 | # 设定返回值 62 | addi $v0, $a0, 1 63 | j F_ret 64 | 65 | F1: 66 | # 第二个if语句 67 | addi $t1, $0, 102 68 | bne $t0, $t1, F2 69 | addi $a0, $a0, 1 70 | jal G 71 | j F_ret 72 | 73 | F2: 74 | addi $v0, $0, -1 75 | F_ret: 76 | # 释放栈帧空间，恢复保留寄存器 77 | lw $ra, 0($sp) 78 | lw $a0, 4($sp) 79 | addi $sp, $sp, 8 80 | jr $ra 81 | 82 | G: 83 | addi $sp, $sp, -8 84 | sw $a0, 4($sp) 85 | sw $ra, 0($sp) 86 | 87 | sll $t9, $a0, 2 88 | add $t9, $s0, $t9 89 | lw $t0, 0($t9) 90 | 91 | addi $t1, $0, 103 92 | bne $t0, $t1, G1 93 | addi $a0, $a0, 1 94 | jal F 95 | j G_ret 96 | 97 | G1: 98 | addi $v0, $0, -1 99 | G_ret: 100 | lw $ra, 0($sp) 101 | lw $a0, 4($sp) 102 | addi $sp, $sp, 8 103 | jr $ra 104 | -------------------------------------------------------------------------------- /assignment-3(I)/benchtest/mutual recursion/mutual recursion.in: -------------------------------------------------------------------------------- 1 | # 在编译原理的语法分析中，很多文法都是递归形式给出的。 2 | # 假设有如下文法： 3 | # G[F]: 4 | # F → fG | a 5 | # G → gF 6 | # 判断字符串 a 是否满足的程序如下： 7 | # 8 | # int F(int pos) 9 | # { 10 | # if(a[pos] == 'a') return pos+1; 11 | # if(a[pos] == 'f') return G(pos+1); 12 | # return -1; 13 | # } 14 | # 15 | # int G(int pos) 16 | # { 17 | # if(a[pos] == 'g') return F(pos+1); 18 | # return -1; 19 | # } 20 | # b = F(0); 21 | 22 | # 将字符串"fgfga"置入从0x00000000($s0)开始的空间 23 | # 因为不支持sb指令，所以用sw代替 24 | addi $s0, $0, 0 25 | addi $t0, $0, 102 26 | sw $t0, 0($s0) 27 | addi $t0, $0, 103 28 | sw $t0, 4($s0) 29 | addi $t0, $0, 102 30 | sw $t0, 8($s0) 31 | addi $t0, $0, 103 32 | sw $t0, 12($s0) 33 | addi $t0, $0, 97 34 | sw $t0, 16($s0) 35 | # 初始化栈指针 36 | addi $sp, $0, 128 37 | 38 | # 调用F(0)。调用返回后，将返回值($v0)存入变量b($s1)。 39 | addi $a0, $0, 0 40 | jal F 41 | addi $s1, $v0, 0 42 | nop 43 | nop 44 | nop 45 | nop 46 | 47 | F: 48 | # 申请栈帧空间，存储保留寄存器 49 | addi $sp, $sp, -8 50 | sw $a0, 4($sp) 51 | sw $ra, 0($sp) 52 | 53 | # 读取a[pos] 54 | sll $t9, $a0, 2 55 | add $t9, $s0, $t9 56 | lw $t0, 0($t9) 57 | 58 | # 第一个if语句 59 | addi $t1, $0, 97 60 | bne $t0, $t1, F1 61 | # 设定返回值 62 | addi $v0, $a0, 1 63 | j F_ret 64 | 65 | F1: 66 | # 第二个if语句 67 | addi $t1, $0, 102 68 | bne $t0, $t1, F2 69 | addi $a0, $a0, 1 70 | jal G 71 | j F_ret 72 | 73 | F2: 74 | addi $v0, $0, -1 75 | F_ret: 76 | # 释放栈帧空间，恢复保留寄存器 77 | lw $ra, 0($sp) 78 | lw $a0, 4($sp) 79 | addi $sp, $sp, 8 80 | jr $ra 81 | 82 | G: 83 | addi $sp, $sp, -8 84 | sw $a0, 4($sp) 85 | sw $ra, 0($sp) 86 | 87 | sll $t9, $a0, 2 88 | add $t9, $s0, $t9 89 | lw $t0, 0($t9) 90 | 91 | addi $t1, $0, 103 92 | bne $t0, $t1, G1 93 | addi $a0, $a0, 1 94 | jal F 95 | j G_ret 96 | 97 | G1: 98 | addi $v0, $0, -1 99 | G_ret: 100 | lw $ra, 0($sp) 101 | lw $a0, 4($sp) 102 | addi $sp, $sp, 8 103 | jr $ra 104 | -------------------------------------------------------------------------------- /assignment-1/index.md: -------------------------------------------------------------------------------- 1 | ##
ICS (Architecture)
2 | 3 | ###
Fudan University / 2020 Spring
4 | 5 |
Assignment 1
6 | Note: This is the first assignment for this course, you should read the [guidelines](https://github.com/SunflowerAries/ICS-Spring20-Fudan/blob/master/README.md) first. This assignment will make up 20% of the final score. 7 | 8 | This assignment will **due on Apr 6** before the course start, and you must pass all the tests before submitting your work, for detailed information about checker configuration, also refer to the [guidelines](https://github.com/SunflowerAries/ICS-Spring20-Fudan/blob/master/README.md#checker-configuration). 9 | 10 | #### Description 11 | 12 | In this assignment, you are going to implement Single-Cycle MIPS CPU according to slides and textbook. Your CPU need support instructions including: add，sub，and，or，slt，addi，andi，ori，slti，sw，lw，j，nop，beq，bne, jal, jr, sra, sll, srl. For unfamiliar instructions, please refer to our textbook *Digital Design and Computer Architecture*'s Appendix B. 13 | 14 | You have to follow our variable naming rules and framework as shown in `cpu_tb.sv`, which mainly refer to our textbook, since our graders are based on them. 15 | 16 | ```verilog 17 | module cpu_tb(); 18 | /* 19 | * grader 20 | */ 21 | 22 | mips mips(.clk(cpu_clk), .reset(reset), .pc(pc), .instr(instr), .memwrite(cpu_mem_write), .aluout(cpu_data_addr), .writedata(write_data), .readdata(read_data)); 23 | imem imem(.a(pc[7:2]), .rd(instr)); 24 | dmem dmem(.clk(clk), .we(mem_write), .a(cpu_data_addr), .wd(write_data), .rd(read_data)); 25 | endmodule 26 | ``` 27 | 28 | After finishing CPU, you must run simulation to check if your CPU works well. This assignment's tests are all listed in `assignment/benchtest` 29 | 30 | #### Report Requirements 31 | 32 | - There's no need to include simulation results (e.g. wave plots) in your report, since you have passed all the benchtests. 33 | - You should list all the references you find useful during your implementation, especially for the pictures you include in your report (We recommend you draw pictures on your own). 34 | - You are encouraged to offer some interesting and useful benchtests (not included in ours) in your report (no more than 5% **bonus**). 35 | -------------------------------------------------------------------------------- /assignment-2/index.md: -------------------------------------------------------------------------------- 1 | ##
ICS (Architecture)
2 | 3 | ###
Fudan University / 2020 Spring
4 | 5 |
Assignment 2
6 | This assignment will make up 20% of the final score. It will **due on Apr 27**, and you must pass all the tests before submitting your work. Recently we've made some **changes** to grade your work automatically, please refer to [checker guidelines](https://github.com/SunflowerAries/ICS-Spring20-Fudan/blob/master/README.md#checker-configuration) for details. 7 | 8 | #### Background 9 | 10 | $$ 11 | CPU time = \frac{Seconds}{Program} = \frac{Instructions}{Program}\times\frac{Cycles}{Instruction}\times\frac{Seconds}{Cycle} 12 | $$ 13 | 14 | Pipelining is a technique where multiple instructions are overlapped during execution. It reduces CPI so that total CPU time consumption is dramatically reduced compared to non-pipelining. All modern high-performance microprocessors are pipelined. 15 | 16 | From now on, we'll measure CPI of your CPU, and you may alter 76th-79th lines of `cpu_tb.sv` to fit into yours. 17 | 18 | ```systemverilog 19 | cycle = cycle + 1; 20 | 21 | if (~mips.dp.flushD & ~mips.dp.haz.stallD) 22 | instr_count = instr_count + 1; 23 | ``` 24 | 25 | However, because multiple instructions are handled concurrently in a pipelined system, there exists possibility of *hazards*, which need special solution. 26 | 27 | #### Description 28 | 29 | In this assignment, you are going to implement Pipeline MIPS CPU according to slides and textbook. 30 | 31 | Your CPU needs to support instructions: add，sub，and，or，slt，addi，andi，ori，slti，sw，lw，j，nop，beq，bne, jal, jr, sra, sll, srl. For unfamiliar instructions, please refer to our textbook *Digital Design and Computer Architecture*'s Appendix B. 32 | 33 | You have to follow our I/O port naming as shown in `cpu_tb.sv`, on which our graders are based. (Same as in textbook) 34 | 35 | ```verilog 36 | module cpu_tb(); 37 | /* 38 | * grader 39 | */ 40 | 41 | mips mips(.clk(cpu_clk), .reset(reset), .pc(pc), .instr(instr), .memwrite(cpu_mem_write), .aluout(cpu_data_addr), .writedata(write_data), .readdata(read_data)); 42 | imem imem(.a(pc[7:2]), .rd(instr)); 43 | dmem dmem(.clk(clk), .we(mem_write), .a(cpu_data_addr), .wd(write_data), .rd(read_data)); 44 | endmodule 45 | ``` 46 | 47 | Before submission, you must run simulation to check if your CPU works well. This assignment's tests are all listed in `assignment-2/benchtest` 48 | 49 | #### Report Requirements 50 | 51 | - There's no need to include simulation results (e.g. wave plots) in your report, since you have passed all the benchtests. 52 | - For the sake of intellectual property, you should list all the references, especially the pictures you include in the report (It's recommended to draw pictures on your own). 53 | - You are encouraged to offer some interesting and useful benchtests (not included in ours) in your report (no more than 5% bonus). 54 | -------------------------------------------------------------------------------- /assignment-2/benchtest/testjr/testjr.out: -------------------------------------------------------------------------------- 1 | 0x0 : addi $sp, $0, 64 | 201d0040 2 | 0x4 : addi $t0, $0, 10 | 2008000a 3 | 0x8 : addi $t1, $0, 100 | 20090064 4 | 0xc : | 5 | 0xc : test1: | 6 | 0xc : addi $a0, $0, 28 | 2004001c 7 | 0x10 : addi $a0, $0, 36 | 20040024 8 | 0x14 : nop | 00000000 9 | 0x18 : jr $a0 | 00800008 10 | 0x1c : sw $t0, 0($sp) | afa80000 11 | 0x20 : j test2 | 0800000a 12 | 0x24 : sw $t1, 0($sp) | afa90000 13 | 0x28 : | 14 | 0x28 : test2: | 15 | 0x28 : addi $sp, $sp, -8 | 23bdfff8 16 | 0x2c : addi $a0, $0, 56 | 20040038 17 | 0x30 : addi $a0, $0, 64 | 20040040 18 | 0x34 : jr $a0 | 00800008 19 | 0x38 : sw $t0, 0($sp) | afa80000 20 | 0x3c : j test3 | 08000011 21 | 0x40 : sw $t1, 0($sp) | afa90000 22 | 0x44 : | 23 | 0x44 : test3: | 24 | 0x44 : addi $sp, $sp, -8 | 23bdfff8 25 | 0x48 : addi $a0, $0, 100 | 20040064 26 | 0x4c : sw $a0, 0($0) | ac040000 27 | 0x50 : addi $a0, $0, 108 | 2004006c 28 | 0x54 : sw $a0, 8($0) | ac040008 29 | 0x58 : lw $a0, 0($0) | 8c040000 30 | 0x5c : lw $a0, 8($0) | 8c040008 31 | 0x60 : jr $a0 | 00800008 32 | 0x64 : sw $t0, 0($sp) | afa80000 33 | 0x68 : j test4 | 0800001c 34 | 0x6c : sw $t1, 0($sp) | afa90000 35 | 0x70 : | 36 | 0x70 : test4: | 37 | 0x70 : addi $sp, $sp, -8 | 23bdfff8 38 | 0x74 : addi $a0, $0, 144 | 20040090 39 | 0x78 : sw $a0, 16($0) | ac040010 40 | 0x7c : addi $a0, $0, 136 | 20040088 41 | 0x80 : lw $a0, 16($0) | 8c040010 42 | 0x84 : jr $a0 | 00800008 43 | 0x88 : sw $t0, 0($sp) | afa80000 44 | 0x8c : j test5 | 08000025 45 | 0x90 : sw $t1, 0($sp) | afa90000 46 | 0x94 : | 47 | 0x94 : test5: | 48 | 0x94 : addi $t0, $0, 6 | 20080006 49 | 0x98 : sw $t0, 0($0) | ac080000 50 | 0x9c : add $sp, $0, $0 | 0000e820 51 | 0xa0 : and $t1, $t1, $0 | 01204824 52 | 0xa4 : Again: | 53 | 0xa4 : addi $t1, $t1, 6 | 21290006 54 | 0xa8 : lw $t0, 0($sp) | 8fa80000 55 | 0xac : beq $t0, $t1, Again | 1128fffd 56 | 0xb0 : sw $t1, 4($0) | ac090004 57 | 0xb4 : | 58 | 0xb4 : test6: | 59 | 0xb4 : addi $t0, $0, 220 | 200800dc 60 | 0xb8 : sw $t0, 0($0) | ac080000 61 | 0xbc : addi $t0, $0, 240 | 200800f0 62 | 0xc0 : sw $t0, 4($0) | ac080004 63 | 0xc4 : and $sp, $sp, $0 | 03a0e824 64 | 0xc8 : and $t0, $t0, $0 | 01004024 65 | 0xcc : sw $0, 24($0) | ac000018 66 | 0xd0 : lw $t0, 0($sp) | 8fa80000 67 | 0xd4 : jr $t0 | 01000008 68 | 0xd8 : sw $t0, 80($sp) | afa80050 69 | 0xdc : lw $t0, 4($sp) | 8fa80004 70 | 0xe0 : addi $t0, $t0, -4 | 2108fffc 71 | 0xe4 : jr $t0 | 01000008 72 | 0xe8 : sw $t0, 84($sp) | afa80054 73 | 0xec : sw $t0, 12($0) | ac08000c 74 | 0xf0 : nop | 00000000 75 | 0xf4 : nop | 00000000 76 | 0xf8 : nop | 00000000 77 | 0xfc : nop | 00000000 -------------------------------------------------------------------------------- /assignment-3(I)/benchtest/testjr/testjr.out: -------------------------------------------------------------------------------- 1 | 0x0 : addi $sp, $0, 64 | 201d0040 2 | 0x4 : addi $t0, $0, 10 | 2008000a 3 | 0x8 : addi $t1, $0, 100 | 20090064 4 | 0xc : | 5 | 0xc : test1: | 6 | 0xc : addi $a0, $0, 28 | 2004001c 7 | 0x10 : addi $a0, $0, 36 | 20040024 8 | 0x14 : nop | 00000000 9 | 0x18 : jr $a0 | 00800008 10 | 0x1c : sw $t0, 0($sp) | afa80000 11 | 0x20 : j test2 | 0800000a 12 | 0x24 : sw $t1, 0($sp) | afa90000 13 | 0x28 : | 14 | 0x28 : test2: | 15 | 0x28 : addi $sp, $sp, -8 | 23bdfff8 16 | 0x2c : addi $a0, $0, 56 | 20040038 17 | 0x30 : addi $a0, $0, 64 | 20040040 18 | 0x34 : jr $a0 | 00800008 19 | 0x38 : sw $t0, 0($sp) | afa80000 20 | 0x3c : j test3 | 08000011 21 | 0x40 : sw $t1, 0($sp) | afa90000 22 | 0x44 : | 23 | 0x44 : test3: | 24 | 0x44 : addi $sp, $sp, -8 | 23bdfff8 25 | 0x48 : addi $a0, $0, 100 | 20040064 26 | 0x4c : sw $a0, 0($0) | ac040000 27 | 0x50 : addi $a0, $0, 108 | 2004006c 28 | 0x54 : sw $a0, 8($0) | ac040008 29 | 0x58 : lw $a0, 0($0) | 8c040000 30 | 0x5c : lw $a0, 8($0) | 8c040008 31 | 0x60 : jr $a0 | 00800008 32 | 0x64 : sw $t0, 0($sp) | afa80000 33 | 0x68 : j test4 | 0800001c 34 | 0x6c : sw $t1, 0($sp) | afa90000 35 | 0x70 : | 36 | 0x70 : test4: | 37 | 0x70 : addi $sp, $sp, -8 | 23bdfff8 38 | 0x74 : addi $a0, $0, 144 | 20040090 39 | 0x78 : sw $a0, 16($0) | ac040010 40 | 0x7c : addi $a0, $0, 136 | 20040088 41 | 0x80 : lw $a0, 16($0) | 8c040010 42 | 0x84 : jr $a0 | 00800008 43 | 0x88 : sw $t0, 0($sp) | afa80000 44 | 0x8c : j test5 | 08000025 45 | 0x90 : sw $t1, 0($sp) | afa90000 46 | 0x94 : | 47 | 0x94 : test5: | 48 | 0x94 : addi $t0, $0, 6 | 20080006 49 | 0x98 : sw $t0, 0($0) | ac080000 50 | 0x9c : add $sp, $0, $0 | 0000e820 51 | 0xa0 : and $t1, $t1, $0 | 01204824 52 | 0xa4 : Again: | 53 | 0xa4 : addi $t1, $t1, 6 | 21290006 54 | 0xa8 : lw $t0, 0($sp) | 8fa80000 55 | 0xac : beq $t0, $t1, Again | 1128fffd 56 | 0xb0 : sw $t1, 4($0) | ac090004 57 | 0xb4 : | 58 | 0xb4 : test6: | 59 | 0xb4 : addi $t0, $0, 220 | 200800dc 60 | 0xb8 : sw $t0, 0($0) | ac080000 61 | 0xbc : addi $t0, $0, 240 | 200800f0 62 | 0xc0 : sw $t0, 4($0) | ac080004 63 | 0xc4 : and $sp, $sp, $0 | 03a0e824 64 | 0xc8 : and $t0, $t0, $0 | 01004024 65 | 0xcc : sw $0, 24($0) | ac000018 66 | 0xd0 : lw $t0, 0($sp) | 8fa80000 67 | 0xd4 : jr $t0 | 01000008 68 | 0xd8 : sw $t0, 80($sp) | afa80050 69 | 0xdc : lw $t0, 4($sp) | 8fa80004 70 | 0xe0 : addi $t0, $t0, -4 | 2108fffc 71 | 0xe4 : jr $t0 | 01000008 72 | 0xe8 : sw $t0, 84($sp) | afa80054 73 | 0xec : sw $t0, 12($0) | ac08000c 74 | 0xf0 : nop | 00000000 75 | 0xf4 : nop | 00000000 76 | 0xf8 : nop | 00000000 77 | 0xfc : nop | 00000000 -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # MIPS-Spring20-Fudan 2 | 3 | Course Website for MIPS Spring 2020 at Fudan University 4 | [[course website]](https://sunfloweraries.github.io/ICS-Spring20-Fudan/) 5 | 6 | ## Coursework Guidelines 7 | 8 | - Both **verilog** and **system verilog** are recommended, and if you have any problems about them, please search in proper websites (e.g. [stack overflow](https://stackoverflow.com/)) first. 9 | - The first three assignments must be checked as scheduled in our syllabus, and each report can be delayed **no more than a week**. For the fourth assignment, you will not be required to finish it, but we will grade on your accomplishments. 10 | - You'd better form a team as soon as possible, since `assignment-3` and `assignment-4` are designed as team project (to be discussed). 11 | - Both English and Chinese are acceptable, and there will be no difference in terms of scores as long as you can make yourself clear with your report. 12 | - Write clearly and succinctly. Highlight your answer and key result that is asked in the coursework requirements by **Bold** font. You should take your own risk if you intentionally or unintentionally make the marking un-straightforward. 13 | - Bonus mark (no more than 20%) will be considered if you make more in-depth exploration or further development that could in turn inspire the coursework to be a better one and show your understanding of the course material, this should only be the case given that you have already met the requirements. 14 | - Please use the [issue system](https://github.com/SunflowerAries/ICS-Spring20-Fudan/issues) to ask questions about the coursework and course or discuss about the course content, use proper tags whenever possible, (e.g. `Arch/assignment-1`). In this case any questions answered by the instructor, TAs or others, and discussions will also be visible to other students. 15 | - If you find any mistakes in the coursework or the course website itself (e.g. typos) you are encouraged to correct it with a pull request, however, don't mix this kind of changes with your coursework submission pull request as stated in the following section. 16 | - For any feedback, please consider emailing the TAs first. 17 | 18 | ## Checker Configuration 19 | 20 | For the first three assignments, you need pass all the tests before submitting, and we will again check if you've passed them. 21 | 22 | Take `assignment-1` as an example, its benchtests are all included in `assignment-1/benchtest`, which is structured like this 23 | 24 | ``` 25 | . 26 | ├── benchtest/ 27 | | ├── run_simulation.tcl 28 | │ ├── cpu_tb.sv 29 | │ ├── .... (other benchtests) 30 | │ └── factorial 31 | | | ├── factorial.ans 32 | | | ├── factorial.in 33 | | | ├── factorial.mem 34 | | | ├── factorial.out 35 | | | ├── factorial.run 36 | | | └── factorial.txt 37 | ``` 38 | 39 | You need to create a vivado project first, and suppose its name is `project_1`, then include the `benchtest/` directory and `makefile` in `project_1/`, and add `benchtest/cpu_tb.sv` as a simulation source file without copying sources into project (and then set it as top). ~~Please change the value of `PATH_PREFIX` in the 1st line of `cpu_tb.sv` to the absolute path to this project, for example `/home/sunflower/Downloads/project_1/`~~. To grade your work automatically, we've made some changes to your cpu_tb.sv and began to take relative path, so there's no need to change the value of `PATH_PREFIX` in the 1st line of `cpu_tb.sv` any more. 40 | 41 | Each directory (e.g. `factorial/`) represents a test, which includes 6 files, and you can look into \*.out which includes mips instructions and its corresponding machine code. **If you want to commit some tests to us, you need comment out additional tests before committing in `cpu_tb.sv`**. 42 | 43 | If you successfully passed a test, you can get outputs like 44 | 45 | ```shell 46 | [OK] factorial 47 | [OK] ... 48 | [Done] 49 | ``` 50 | 51 | Otherwise you may get outputs like `FAILURE: Testbench Failed to finish before ddl!` or `[Error] PC: 0x0000001e Cycle: 5 Expected: balabala, Got: labalaba`, when you encounters the second situation in GUI, CPU is now stopped, and you can look into the wave plot to find what's wrong. 52 | 53 | On linux, if you want to run the simulation test in command line, you can configure the `makefile`: 54 | 55 | * `VIVADO_PATH` is the absolute path to your vivado executable file, eg. `/usr/local/Xilinx/Vivado/20xx.x/bin/vivado`. 56 | * `PROJECT_DIR` default is `.`, you can leave it alone. 57 | * `PROJECT_NAME` is the name of your vivado project which should correspond to `*.xpr`. 58 | * `SIM` is the name of the simulation set you want to run (default is sim_1). 59 | * **You need to restore the configuration before committing, since we'll just use `makefile` in your directory to run vivado automatically**. 60 | 61 | After proper configuration, you can use `make test` or simple `make` to run the simulation test. 62 | 63 | ## Scores 64 | 65 | For each assignment, the score is made up of 66 | 67 | - Passing all the benchtests (40%). 68 | - Report and interview (40%). 69 | - On-board test (20%). 70 | 71 | ## Hint 72 | 73 | This course website mainly refers to [PRML-Spring19-Fudan](https://github.com/ichn-hu/PRML-Spring19-Fudan). 74 | 75 | For textbook, you can refer to 76 | 77 | - *Digital Design and Computer Architecture* (2nd) -------------------------------------------------------------------------------- /assignment-1/benchtest/cpu_tb.sv: -------------------------------------------------------------------------------- 1 | `define PATH_PREFIX "/home/sunflower/Downloads/project_1/" 2 | `define NAME "benchtest/" 3 | 4 | module cpu_tb(); 5 | 6 | wire mem_write, cpu_clk, finish, cpu_mem_write; 7 | wire [31:0] pc, instr, read_data, write_data, cpu_data_addr; 8 | 9 | reg clk, reset; 10 | reg [31:0] tb_data_addr, tb_dmem_data, pc_finished; 11 | 12 | string summary; 13 | // test variables 14 | integer fans, frun, fimem, fdmem, error_count, imem_counter, dmem_counter; 15 | integer cycle = 0, instr_count = 0; 16 | 17 | // module instances 18 | mips mips(.clk(cpu_clk), .reset(reset), .pc(pc), .instr(instr), .memwrite(cpu_mem_write), .aluout(cpu_data_addr), .writedata(write_data), .readdata(read_data)); 19 | imem imem(.a(pc[7:2]), .rd(instr)); 20 | dmem dmem(.clk(clk), .we(mem_write), .a(cpu_data_addr), .wd(write_data), .rd(read_data)); 21 | 22 | // clock and reset 23 | always #20 clk = ~clk; 24 | 25 | assign finish = ~|(pc ^ pc_finished); 26 | assign cpu_clk = clk & ~finish; 27 | assign mem_write = cpu_mem_write & ~finish; 28 | 29 | task judge( 30 | input integer frun, 31 | input integer cycle, 32 | input string out 33 | ); 34 | string ans; 35 | ans = ""; 36 | $fscanf(frun, "%s\n", ans); 37 | if (ans != out) 38 | begin 39 | $display("[Error] PC: 0x%x Cycle: %d\tExpected: %0s, Got: %0s", pc, cycle, ans, out); 40 | $stop; 41 | end 42 | endtask 43 | 44 | // judge memory 45 | task judge_memory( 46 | input integer fans 47 | ); 48 | $display("========== In memory judge =========="); 49 | begin 50 | wait(finish == 1'b1); 51 | while(!$feof(fans)) 52 | begin 53 | tb_dmem_data = 32'h0000_0000; 54 | $fscanf(fans, "%h", tb_dmem_data); 55 | if (tb_dmem_data != dmem.RAM[tb_data_addr/4]) 56 | begin 57 | $display("FAILUER: dmem 0x%0h expect 0x%0h but get 0x%0h", 58 | tb_data_addr, tb_dmem_data, dmem.RAM[tb_data_addr/4]); 59 | error_count = error_count + 1; 60 | end 61 | tb_data_addr = tb_data_addr + 4; 62 | end 63 | $display("successfully pass memory judge"); 64 | end 65 | endtask 66 | 67 | // check runtime 68 | task runtime_checker( 69 | input integer frun 70 | ); 71 | string out; 72 | $display("========== In runtime checker =========="); 73 | while(!$feof(frun)) 74 | begin@(negedge clk) 75 | cycle = cycle + 1; 76 | 77 | if (mem_write) 78 | begin 79 | $sformat(out, "[0x%x]=0x%x", cpu_data_addr, write_data); 80 | // $display("out: %0s", out); 81 | judge(frun, cycle, out); 82 | end 83 | end 84 | $display("successfully pass runtime checker"); 85 | endtask 86 | 87 | initial 88 | begin 89 | // ddl to finish simulation 90 | #10000000 $display("FAILURE: Testbench Failed to finish before ddl!"); 91 | error_count = error_count + 1; 92 | $finish; 93 | end 94 | 95 | // init memory 96 | task init(input string name); 97 | imem.RAM = '{ default: '0 }; 98 | dmem.RAM = '{ default: '0 }; 99 | fimem = $fopen({ `PATH_PREFIX, `NAME, name, "/", name, ".mem"}, "r"); 100 | fdmem = $fopen({ `PATH_PREFIX, `NAME, name, "/", name, ".data"}, "r"); 101 | if (fdmem != 0) 102 | begin 103 | dmem_counter = 0; 104 | while(!$feof(fdmem)) 105 | begin 106 | dmem.RAM[dmem_counter] = 32'h0000_0000; 107 | $fscanf(fdmem, "%x", dmem.RAM[dmem_counter]); 108 | dmem_counter = dmem_counter + 1; 109 | end 110 | $fclose(fdmem); 111 | end 112 | imem_counter = 0; 113 | $display("========== In init =========="); 114 | while(!$feof(fimem)) 115 | begin 116 | imem.RAM[imem_counter] = 32'h0000_0000; 117 | $fscanf(fimem, "%x", imem.RAM[imem_counter]); 118 | imem_counter = imem_counter + 1; 119 | end 120 | $display("%d instructions in total", imem_counter); 121 | $fclose(fimem); 122 | endtask 123 | 124 | task grader(input string name); 125 | $display("========== Test: %0s ==========", name); 126 | begin 127 | reset = 1'b1; 128 | tb_dmem_data = 32'h0000_0000; 129 | tb_data_addr = 32'h0000_0000; 130 | pc_finished = 32'hffff_ffff; 131 | #50 reset = 1'b0; 132 | end 133 | init(name); 134 | fans = $fopen({ `PATH_PREFIX, `NAME, name, "/", name, ".ans"}, "r"); 135 | $fscanf(fans, "%h", pc_finished); 136 | frun = $fopen({ `PATH_PREFIX, `NAME, name, "/", name, ".run"}, "r"); 137 | runtime_checker(frun); 138 | error_count = 0; 139 | $fclose(frun); 140 | judge_memory(fans); 141 | $fclose(fans); 142 | if (error_count != 0) 143 | $display("Find %d error(s)", error_count); 144 | else 145 | $display("[OK] %0s\n", name); 146 | endtask 147 | 148 | // start test 149 | initial 150 | begin 151 | clk = 1'b0; 152 | grader("ad hoc"); 153 | grader("factorial"); 154 | grader("bubble sort"); 155 | grader("gcd"); 156 | grader("quick multiply"); 157 | grader("bisection"); 158 | $display("[Done]\n"); 159 | $finish; 160 | end 161 | 162 | endmodule 163 | -------------------------------------------------------------------------------- /assignment-1/benchtest/assembler.py: -------------------------------------------------------------------------------- 1 | # -*- coding: UTF-8 -*- 2 | 3 | import re 4 | import os 5 | import sys 6 | import platform 7 | 8 | reg = ['0', 'at', 'v0', 'v1', 'a0', 'a1', 'a2', 'a3', 't0', 't1', 't2', 't3', 't4', 't5', 't6', 't7', 's0', 's1', 's2', 's3', 's4', 's5', 's6', 's7', 't8', 't9', 'k0', 'k1', 'gp', 'sp', 'fp', 'ra'] 9 | RType = ['sll', 0, 'srl', 'sra', 'sllv', 0, 'srlv', 'srav', 'jr', 'jalr', 0, 0, 'syscall', 'break', 0, 0, 'mfhi', 'mthi', 'mflo', 'mtlo', 0, 0, 0, 0, 'mult', 'multu', 'div', 'divu', 0, 0, 0, 0, 'add', 'addu', 'sub', 'subu', 'and', 'or', 'xor', 'nor', 0, 0, 'slt', 'sltu'] 10 | Shift = ['sll', 'srl', 'sra'] 11 | IType = {'beq':4, 'bne':5, 'blez':6, 'bgtz':7, 'addi':8, 'addiu':9, 'slti':10, 'sltiu':11, 'andi':12, 'ori':13, 'xori':14, 'lui':15, 'mul':28, 'lb':32, 'lh':33, 'lw':35, 'lbu':36, 'lhu':37, 'sb':40, 'sh':41, 'sw':43, 'lwcl':49, 'swcl':56} 12 | JType = {'j':2, 'jal':3} 13 | 14 | sysstr = platform.system() 15 | # print(sysstr) 16 | if sysstr == "Windows": 17 | os.chdir(os.getcwd() + '\\' + sys.argv[1]) 18 | else: 19 | os.chdir(os.getcwd() + '/' + sys.argv[1]) 20 | FileList = os.listdir(os.getcwd()) 21 | 22 | global finPC 23 | finPC = 0 24 | 25 | def HEX(number, length): 26 | if number < 0: 27 | number += 1 << length 28 | ans = hex(number) 29 | return ans[2:].rjust(length, '0') 30 | 31 | def BIN(number, length): 32 | if number < 0: 33 | number += 1 << length 34 | ans = bin(number) 35 | return ans[2:].rjust(length, '0') 36 | 37 | def Disassembler(InputFile, OutputFile, type="out"): 38 | labels = {} 39 | PC = 0 40 | lines = InputFile.readlines(100000) 41 | for line in lines: 42 | line = line.strip() 43 | sep = line.find(':') 44 | if sep != -1: 45 | labels[line[0:sep].strip()] = PC 46 | sep = line.find(' ') 47 | if sep != -1: 48 | cmd = line[0:sep].strip() 49 | else: 50 | cmd = line.strip() 51 | if (cmd in RType) or (cmd in IType) or (cmd in JType) or (cmd == 'nop'): 52 | PC += 4 53 | print("PC: ", PC) 54 | finPC = PC 55 | #print(labels) 56 | 57 | PC = 0 58 | for line in lines: 59 | result = '' 60 | now = line.strip() 61 | sep = line.find(' ') 62 | cmd = line[0:sep].strip() 63 | if cmd in RType: 64 | line = line[sep+1:].strip() 65 | sep = line.find(',') 66 | reg1 = line[1:sep].strip() 67 | if cmd == 'jr': 68 | reg1 = line[1:].strip() 69 | result = '000000' + BIN(reg.index(reg1), 5) + '000000000000000' + '001000' 70 | else: 71 | line = line[sep+1:].strip() 72 | sep = line.find(',') 73 | reg2 = line[1:sep].strip() 74 | line = line[sep+1:].strip() 75 | if cmd not in Shift: 76 | reg3 = line[1:].strip() 77 | result = '000000' + BIN(reg.index(reg2), 5) + BIN(reg.index(reg3), 5) + BIN(reg.index(reg1), 5) + '00000' + BIN(RType.index(cmd), 6) 78 | else: 79 | result = '000000' + '00000' + BIN(reg.index(reg2), 5) + BIN(reg.index(reg1), 5) + BIN(int(line.strip()), 5) + BIN(RType.index(cmd), 6) 80 | 81 | elif cmd in IType: 82 | line = line[sep+1:].strip() 83 | sep = line.find(',') 84 | reg1 = line[1:sep].strip() 85 | line = line[sep+1:].strip() 86 | sep = line.find(',') 87 | if cmd in ['sw', 'lw']: 88 | leftbracket = line.find('(') 89 | rightbracket = line.find(')') 90 | reg2 = line[leftbracket+2:rightbracket].strip() 91 | imm = int(line[0:leftbracket].strip(), base = 0) 92 | else: 93 | reg2 = line[1:sep].strip() 94 | line = line[sep+1:].strip() 95 | if cmd in ['mul']: 96 | reg3 = line[1:].strip() 97 | result = BIN(IType[cmd], 6) + BIN(reg.index(reg2), 5) + BIN(reg.index(reg3), 5) + BIN(reg.index(reg1),5) + '00000' + '000010' 98 | else: 99 | if line in labels: 100 | imm = labels[line] 101 | else: 102 | imm = int(line, base = 0) 103 | if cmd in ['beq', 'bne']: 104 | imm = (imm - PC - 4) >> 2; 105 | if cmd not in ['mul']: result = BIN(IType[cmd], 6) + BIN(reg.index(reg2), 5) + BIN(reg.index(reg1), 5) + BIN(imm, 16) 106 | 107 | elif cmd in JType: 108 | result = BIN(JType[cmd], 6) 109 | line = line[sep+1:].strip() 110 | if line in labels: 111 | result += BIN(labels[line] >> 2, 26) 112 | else: 113 | result += BIN(int(line, base = 0), 26) 114 | 115 | elif cmd == 'nop': 116 | result = BIN(0, 32) 117 | 118 | if result == '' and type == 'txt': continue 119 | if result != '': 120 | result = HEX(int(result, base = 2), 8) 121 | if type == 'out': 122 | result = hex(PC).rjust(4) + ' : ' + now.strip().ljust(20) + ' | ' + result 123 | elif type == 'txt': 124 | result = 'RAM[%d] <= 32\'h'%(PC/4) + result + ';' 125 | elif result == '': 126 | continue 127 | print(result) 128 | if (cmd in RType) or (cmd in IType) or (cmd in JType) or (cmd == 'nop'): 129 | PC += 4 130 | if PC != finPC: 131 | OutputFile.write(result+'\n') 132 | else: 133 | OutputFile.write(result) 134 | 135 | for File in filter(lambda s: True if s.find('.in') != -1 else False, FileList): 136 | print(File) 137 | InputFile = open(File, 'r') 138 | OutputFile = open(File[0:len(File)-3] + '.out', 'w') 139 | Disassembler(InputFile, OutputFile, type="out") 140 | InputFile.close() 141 | OutputFile.close() 142 | InputFile = open(File, 'r') 143 | OutputFile = open(File[0:len(File)-3] + '.txt', 'w') 144 | Disassembler(InputFile, OutputFile, type="txt") 145 | InputFile = open(File, 'r') 146 | OutputFile = open(File[0:len(File)-3] + '.mem', 'w') 147 | Disassembler(InputFile, OutputFile, type="mem") 148 | InputFile.close() 149 | OutputFile.close() 150 | 151 | -------------------------------------------------------------------------------- /assignment-2/benchtest/assembler.py: -------------------------------------------------------------------------------- 1 | # -*- coding: UTF-8 -*- 2 | 3 | import re 4 | import os 5 | import sys 6 | import platform 7 | 8 | reg = ['0', 'at', 'v0', 'v1', 'a0', 'a1', 'a2', 'a3', 't0', 't1', 't2', 't3', 't4', 't5', 't6', 't7', 's0', 's1', 's2', 's3', 's4', 's5', 's6', 's7', 't8', 't9', 'k0', 'k1', 'gp', 'sp', 'fp', 'ra'] 9 | RType = ['sll', 0, 'srl', 'sra', 'sllv', 0, 'srlv', 'srav', 'jr', 'jalr', 0, 0, 'syscall', 'break', 0, 0, 'mfhi', 'mthi', 'mflo', 'mtlo', 0, 0, 0, 0, 'mult', 'multu', 'div', 'divu', 0, 0, 0, 0, 'add', 'addu', 'sub', 'subu', 'and', 'or', 'xor', 'nor', 0, 0, 'slt', 'sltu'] 10 | Shift = ['sll', 'srl', 'sra'] 11 | IType = {'beq':4, 'bne':5, 'blez':6, 'bgtz':7, 'addi':8, 'addiu':9, 'slti':10, 'sltiu':11, 'andi':12, 'ori':13, 'xori':14, 'lui':15, 'mul':28, 'lb':32, 'lh':33, 'lw':35, 'lbu':36, 'lhu':37, 'sb':40, 'sh':41, 'sw':43, 'lwcl':49, 'swcl':56} 12 | JType = {'j':2, 'jal':3} 13 | 14 | sysstr = platform.system() 15 | # print(sysstr) 16 | if sysstr == "Windows": 17 | os.chdir(os.getcwd() + '\\' + sys.argv[1]) 18 | else: 19 | os.chdir(os.getcwd() + '/' + sys.argv[1]) 20 | FileList = os.listdir(os.getcwd()) 21 | 22 | global finPC 23 | finPC = 0 24 | 25 | def HEX(number, length): 26 | if number < 0: 27 | number += 1 << length 28 | ans = hex(number) 29 | return ans[2:].rjust(length, '0') 30 | 31 | def BIN(number, length): 32 | if number < 0: 33 | number += 1 << length 34 | ans = bin(number) 35 | return ans[2:].rjust(length, '0') 36 | 37 | def Disassembler(InputFile, OutputFile, type="out"): 38 | labels = {} 39 | PC = 0 40 | lines = InputFile.readlines(100000) 41 | for line in lines: 42 | line = line.strip() 43 | sep = line.find(':') 44 | if sep != -1: 45 | labels[line[0:sep].strip()] = PC 46 | sep = line.find(' ') 47 | if sep != -1: 48 | cmd = line[0:sep].strip() 49 | else: 50 | cmd = line.strip() 51 | if (cmd in RType) or (cmd in IType) or (cmd in JType) or (cmd == 'nop'): 52 | PC += 4 53 | print("PC: ", PC) 54 | finPC = PC 55 | #print(labels) 56 | 57 | PC = 0 58 | for line in lines: 59 | result = '' 60 | now = line.strip() 61 | sep = line.find(' ') 62 | cmd = line[0:sep].strip() 63 | if cmd in RType: 64 | line = line[sep+1:].strip() 65 | sep = line.find(',') 66 | reg1 = line[1:sep].strip() 67 | if cmd == 'jr': 68 | reg1 = line[1:].strip() 69 | result = '000000' + BIN(reg.index(reg1), 5) + '000000000000000' + '001000' 70 | else: 71 | line = line[sep+1:].strip() 72 | sep = line.find(',') 73 | reg2 = line[1:sep].strip() 74 | line = line[sep+1:].strip() 75 | if cmd not in Shift: 76 | reg3 = line[1:].strip() 77 | result = '000000' + BIN(reg.index(reg2), 5) + BIN(reg.index(reg3), 5) + BIN(reg.index(reg1), 5) + '00000' + BIN(RType.index(cmd), 6) 78 | else: 79 | result = '000000' + '00000' + BIN(reg.index(reg2), 5) + BIN(reg.index(reg1), 5) + BIN(int(line.strip()), 5) + BIN(RType.index(cmd), 6) 80 | 81 | elif cmd in IType: 82 | line = line[sep+1:].strip() 83 | sep = line.find(',') 84 | reg1 = line[1:sep].strip() 85 | line = line[sep+1:].strip() 86 | sep = line.find(',') 87 | if cmd in ['sw', 'lw']: 88 | leftbracket = line.find('(') 89 | rightbracket = line.find(')') 90 | reg2 = line[leftbracket+2:rightbracket].strip() 91 | imm = int(line[0:leftbracket].strip(), base = 0) 92 | else: 93 | reg2 = line[1:sep].strip() 94 | line = line[sep+1:].strip() 95 | if cmd in ['mul']: 96 | reg3 = line[1:].strip() 97 | result = BIN(IType[cmd], 6) + BIN(reg.index(reg2), 5) + BIN(reg.index(reg3), 5) + BIN(reg.index(reg1),5) + '00000' + '000010' 98 | else: 99 | if line in labels: 100 | imm = labels[line] 101 | else: 102 | imm = int(line, base = 0) 103 | if cmd in ['beq', 'bne']: 104 | imm = (imm - PC - 4) >> 2 105 | if cmd not in ['mul']: result = BIN(IType[cmd], 6) + BIN(reg.index(reg2), 5) + BIN(reg.index(reg1), 5) + BIN(imm, 16) 106 | 107 | elif cmd in JType: 108 | result = BIN(JType[cmd], 6) 109 | line = line[sep+1:].strip() 110 | if line in labels: 111 | result += BIN(labels[line] >> 2, 26) 112 | else: 113 | result += BIN(int(line, base = 0), 26) 114 | 115 | elif cmd == 'nop': 116 | result = BIN(0, 32) 117 | 118 | if result == '' and type == 'txt': continue 119 | if result != '': 120 | result = HEX(int(result, base = 2), 8) 121 | if type == 'out': 122 | result = hex(PC).rjust(4) + ' : ' + now.strip().ljust(20) + ' | ' + result 123 | elif type == 'txt': 124 | result = 'RAM[%d] <= 32\'h'%(PC/4) + result + ';' 125 | elif result == '': 126 | continue 127 | print(result) 128 | if (cmd in RType) or (cmd in IType) or (cmd in JType) or (cmd == 'nop'): 129 | PC += 4 130 | if PC != finPC: 131 | OutputFile.write(result+'\n') 132 | else: 133 | OutputFile.write(result) 134 | 135 | for File in filter(lambda s: True if s.find('.in') != -1 else False, FileList): 136 | print(File) 137 | InputFile = open(File, 'r') 138 | OutputFile = open(File[0:len(File)-3] + '.out', 'w') 139 | Disassembler(InputFile, OutputFile, type="out") 140 | InputFile.close() 141 | OutputFile.close() 142 | InputFile = open(File, 'r') 143 | OutputFile = open(File[0:len(File)-3] + '.txt', 'w') 144 | Disassembler(InputFile, OutputFile, type="txt") 145 | InputFile = open(File, 'r') 146 | OutputFile = open(File[0:len(File)-3] + '.mem', 'w') 147 | Disassembler(InputFile, OutputFile, type="mem") 148 | InputFile.close() 149 | OutputFile.close() 150 | 151 | -------------------------------------------------------------------------------- /assignment-3(I)/benchtest/assembler.py: -------------------------------------------------------------------------------- 1 | # -*- coding: UTF-8 -*- 2 | 3 | import re 4 | import os 5 | import sys 6 | import platform 7 | 8 | reg = ['0', 'at', 'v0', 'v1', 'a0', 'a1', 'a2', 'a3', 't0', 't1', 't2', 't3', 't4', 't5', 't6', 't7', 's0', 's1', 's2', 's3', 's4', 's5', 's6', 's7', 't8', 't9', 'k0', 'k1', 'gp', 'sp', 'fp', 'ra'] 9 | RType = ['sll', 0, 'srl', 'sra', 'sllv', 0, 'srlv', 'srav', 'jr', 'jalr', 0, 0, 'syscall', 'break', 0, 0, 'mfhi', 'mthi', 'mflo', 'mtlo', 0, 0, 0, 0, 'mult', 'multu', 'div', 'divu', 0, 0, 0, 0, 'add', 'addu', 'sub', 'subu', 'and', 'or', 'xor', 'nor', 0, 0, 'slt', 'sltu'] 10 | Shift = ['sll', 'srl', 'sra'] 11 | IType = {'beq':4, 'bne':5, 'blez':6, 'bgtz':7, 'addi':8, 'addiu':9, 'slti':10, 'sltiu':11, 'andi':12, 'ori':13, 'xori':14, 'lui':15, 'mul':28, 'lb':32, 'lh':33, 'lw':35, 'lbu':36, 'lhu':37, 'sb':40, 'sh':41, 'sw':43, 'lwcl':49, 'swcl':56} 12 | JType = {'j':2, 'jal':3} 13 | 14 | sysstr = platform.system() 15 | # print(sysstr) 16 | if sysstr == "Windows": 17 | os.chdir(os.getcwd() + '\\' + sys.argv[1]) 18 | else: 19 | os.chdir(os.getcwd() + '/' + sys.argv[1]) 20 | FileList = os.listdir(os.getcwd()) 21 | 22 | global finPC 23 | finPC = 0 24 | 25 | def HEX(number, length): 26 | if number < 0: 27 | number += 1 << length 28 | ans = hex(number) 29 | return ans[2:].rjust(length, '0') 30 | 31 | def BIN(number, length): 32 | if number < 0: 33 | number += 1 << length 34 | ans = bin(number) 35 | return ans[2:].rjust(length, '0') 36 | 37 | def Disassembler(InputFile, OutputFile, type="out"): 38 | labels = {} 39 | PC = 0 40 | lines = InputFile.readlines(100000) 41 | for line in lines: 42 | line = line.strip() 43 | sep = line.find(':') 44 | if sep != -1: 45 | labels[line[0:sep].strip()] = PC 46 | sep = line.find(' ') 47 | if sep != -1: 48 | cmd = line[0:sep].strip() 49 | else: 50 | cmd = line.strip() 51 | if (cmd in RType) or (cmd in IType) or (cmd in JType) or (cmd == 'nop'): 52 | PC += 4 53 | print("PC: ", PC) 54 | finPC = PC 55 | #print(labels) 56 | 57 | PC = 0 58 | for line in lines: 59 | result = '' 60 | now = line.strip() 61 | sep = line.find(' ') 62 | cmd = line[0:sep].strip() 63 | if cmd in RType: 64 | line = line[sep+1:].strip() 65 | sep = line.find(',') 66 | reg1 = line[1:sep].strip() 67 | if cmd == 'jr': 68 | reg1 = line[1:].strip() 69 | result = '000000' + BIN(reg.index(reg1), 5) + '000000000000000' + '001000' 70 | else: 71 | line = line[sep+1:].strip() 72 | sep = line.find(',') 73 | reg2 = line[1:sep].strip() 74 | line = line[sep+1:].strip() 75 | if cmd not in Shift: 76 | reg3 = line[1:].strip() 77 | result = '000000' + BIN(reg.index(reg2), 5) + BIN(reg.index(reg3), 5) + BIN(reg.index(reg1), 5) + '00000' + BIN(RType.index(cmd), 6) 78 | else: 79 | result = '000000' + '00000' + BIN(reg.index(reg2), 5) + BIN(reg.index(reg1), 5) + BIN(int(line.strip()), 5) + BIN(RType.index(cmd), 6) 80 | 81 | elif cmd in IType: 82 | line = line[sep+1:].strip() 83 | sep = line.find(',') 84 | reg1 = line[1:sep].strip() 85 | line = line[sep+1:].strip() 86 | sep = line.find(',') 87 | if cmd in ['sw', 'lw']: 88 | leftbracket = line.find('(') 89 | rightbracket = line.find(')') 90 | reg2 = line[leftbracket+2:rightbracket].strip() 91 | imm = int(line[0:leftbracket].strip(), base = 0) 92 | else: 93 | reg2 = line[1:sep].strip() 94 | line = line[sep+1:].strip() 95 | if cmd in ['mul']: 96 | reg3 = line[1:].strip() 97 | result = BIN(IType[cmd], 6) + BIN(reg.index(reg2), 5) + BIN(reg.index(reg3), 5) + BIN(reg.index(reg1),5) + '00000' + '000010' 98 | else: 99 | if line in labels: 100 | imm = labels[line] 101 | else: 102 | imm = int(line, base = 0) 103 | if cmd in ['beq', 'bne']: 104 | imm = (imm - PC - 4) >> 2 105 | if cmd not in ['mul']: result = BIN(IType[cmd], 6) + BIN(reg.index(reg2), 5) + BIN(reg.index(reg1), 5) + BIN(imm, 16) 106 | 107 | elif cmd in JType: 108 | result = BIN(JType[cmd], 6) 109 | line = line[sep+1:].strip() 110 | if line in labels: 111 | result += BIN(labels[line] >> 2, 26) 112 | else: 113 | result += BIN(int(line, base = 0), 26) 114 | 115 | elif cmd == 'nop': 116 | result = BIN(0, 32) 117 | 118 | if result == '' and type == 'txt': continue 119 | if result != '': 120 | result = HEX(int(result, base = 2), 8) 121 | if type == 'out': 122 | result = hex(PC).rjust(4) + ' : ' + now.strip().ljust(20) + ' | ' + result 123 | elif type == 'txt': 124 | result = 'RAM[%d] <= 32\'h'%(PC/4) + result + ';' 125 | elif result == '': 126 | continue 127 | print(result) 128 | if (cmd in RType) or (cmd in IType) or (cmd in JType) or (cmd == 'nop'): 129 | PC += 4 130 | if PC != finPC: 131 | OutputFile.write(result+'\n') 132 | else: 133 | OutputFile.write(result) 134 | 135 | for File in filter(lambda s: True if s.find('.in') != -1 else False, FileList): 136 | print(File) 137 | InputFile = open(File, 'r') 138 | OutputFile = open(File[0:len(File)-3] + '.out', 'w') 139 | Disassembler(InputFile, OutputFile, type="out") 140 | InputFile.close() 141 | OutputFile.close() 142 | InputFile = open(File, 'r') 143 | OutputFile = open(File[0:len(File)-3] + '.txt', 'w') 144 | Disassembler(InputFile, OutputFile, type="txt") 145 | InputFile = open(File, 'r') 146 | OutputFile = open(File[0:len(File)-3] + '.mem', 'w') 147 | Disassembler(InputFile, OutputFile, type="mem") 148 | InputFile.close() 149 | OutputFile.close() 150 | 151 | -------------------------------------------------------------------------------- /assignment-2/benchtest/cpu_tb.sv: -------------------------------------------------------------------------------- 1 | `define PATH_PREFIX "../../../../" 2 | `define NAME "benchtest/" 3 | 4 | module cpu_tb(); 5 | 6 | wire mem_write, cpu_clk, finish, cpu_mem_write; 7 | wire [31:0] pc, instr, read_data, write_data, cpu_data_addr; 8 | 9 | reg clk, reset; 10 | reg [31:0] tb_data_addr, tb_dmem_data, pc_finished; 11 | 12 | //parameter ISIZE = 32, DSIZE = 32; 13 | string summary; 14 | // test variables 15 | integer fans, frun, fimem, fdmem, error_count, imem_counter, dmem_counter; 16 | integer cycle = 0, instr_count = 0; 17 | 18 | `ifdef checking 19 | integer error_test = 0; 20 | `endif 21 | 22 | // module instances 23 | mips mips(.clk(cpu_clk), .reset(reset), .pc(pc), .instr(instr), .memwrite(cpu_mem_write), .aluout(cpu_data_addr), .writedata(write_data), .readdata(read_data)); 24 | imem imem(.a(pc[7:2]), .rd(instr)); 25 | dmem dmem(.clk(clk), .we(mem_write), .a(cpu_data_addr), .wd(write_data), .rd(read_data)); 26 | 27 | // clock and reset 28 | always #20 clk = ~clk; 29 | 30 | assign finish = ~|(pc ^ pc_finished); 31 | assign cpu_clk = clk & ~finish; 32 | assign mem_write = cpu_mem_write & ~finish; 33 | 34 | task judge( 35 | input integer frun, 36 | input integer cycle, 37 | input string out 38 | ); 39 | string ans; 40 | ans = ""; 41 | $fscanf(frun, "%s\n", ans); 42 | if (ans != out) 43 | begin 44 | `ifdef checking 45 | error_count = error_count + 1; 46 | `else 47 | begin 48 | $display("[Error] PC: 0x%x Cycle: %0d\tExpected: %0s, Got: %0s", pc, cycle, ans, out); 49 | $stop; 50 | end 51 | `endif 52 | end 53 | endtask 54 | 55 | // judge memory 56 | task judge_memory( 57 | input integer fans 58 | ); 59 | $display("========== In memory judge =========="); 60 | begin 61 | wait(finish == 1'b1); 62 | while(!$feof(fans)) 63 | begin 64 | tb_dmem_data = 32'h0000_0000; 65 | $fscanf(fans, "%h", tb_dmem_data); 66 | if (tb_dmem_data != dmem.RAM[tb_data_addr/4]) 67 | begin 68 | $display("FAILURE: dmem 0x%0h expect 0x%0h but get 0x%0h", 69 | tb_data_addr, tb_dmem_data, dmem.RAM[tb_data_addr/4]); 70 | error_count = error_count + 1; 71 | end 72 | tb_data_addr = tb_data_addr + 4; 73 | end 74 | `ifndef checking 75 | $display("successfully pass memory judge"); 76 | `endif 77 | end 78 | endtask 79 | 80 | // check runtime 81 | task runtime_checker( 82 | input integer frun 83 | ); 84 | string out; 85 | $display("========== In runtime checker =========="); 86 | while(!$feof(frun)) 87 | begin@(negedge clk) 88 | cycle = cycle + 1; 89 | 90 | if (~mips.dp.flushD & ~mips.dp.haz.stallD) 91 | instr_count = instr_count + 1; 92 | 93 | if (mem_write) 94 | begin 95 | $sformat(out, "[0x%x]=0x%x", cpu_data_addr, write_data); 96 | // $display("out: %0s", out); 97 | judge(frun, cycle, out); 98 | end 99 | end 100 | `ifndef checking 101 | $display("successfully pass runtime checker"); 102 | `endif 103 | endtask 104 | 105 | initial 106 | begin 107 | // ddl to finish simulation 108 | #1000000 $display("FAILURE: Testbench Failed to finish before ddl!"); 109 | error_count = error_count + 1; 110 | $finish; 111 | end 112 | 113 | // init memory 114 | task init(input string name); 115 | imem.RAM = '{ default: '0 }; 116 | dmem.RAM = '{ default: '0 }; 117 | fimem = $fopen({ `PATH_PREFIX, `NAME, name, "/", name, ".mem"}, "r"); 118 | fdmem = $fopen({ `PATH_PREFIX, `NAME, name, "/", name, ".data"}, "r"); 119 | if (fdmem != 0) 120 | begin 121 | dmem_counter = 0; 122 | while(!$feof(fdmem)) 123 | begin 124 | dmem.RAM[dmem_counter] = 32'h0000_0000; 125 | $fscanf(fdmem, "%x", dmem.RAM[dmem_counter]); 126 | dmem_counter = dmem_counter + 1; 127 | end 128 | $fclose(fdmem); 129 | end 130 | imem_counter = 0; 131 | $display("========== In init =========="); 132 | while(!$feof(fimem)) 133 | begin 134 | imem.RAM[imem_counter] = 32'h0000_0000; 135 | $fscanf(fimem, "%x", imem.RAM[imem_counter]); 136 | imem_counter = imem_counter + 1; 137 | end 138 | $display("%0d instructions in total", imem_counter); 139 | $fclose(fimem); 140 | endtask 141 | 142 | task grader(input string name); 143 | $display("========== Test: %0s ==========", name); 144 | begin 145 | reset = 1'b1; 146 | tb_dmem_data = 32'h0000_0000; 147 | tb_data_addr = 32'h0000_0000; 148 | pc_finished = 32'hffff_ffff; 149 | #50 reset = 1'b0; 150 | end 151 | init(name); 152 | fans = $fopen({ `PATH_PREFIX, `NAME, name, "/", name, ".ans"}, "r"); 153 | $fscanf(fans, "%h", pc_finished); 154 | frun = $fopen({ `PATH_PREFIX, `NAME, name, "/", name, ".run"}, "r"); 155 | error_count = 0; 156 | runtime_checker(frun); 157 | $fclose(frun); 158 | judge_memory(fans); 159 | $fclose(fans); 160 | if (error_count != 0) 161 | begin 162 | $display("Find %0d error(s)", error_count); 163 | `ifdef checking 164 | error_test = error_test + 1; 165 | $display("[ERROR] %0s\n", name); 166 | `endif 167 | end 168 | else 169 | $display("[OK] %0s\n", name); 170 | endtask 171 | 172 | // start test 173 | initial 174 | begin 175 | clk = 1'b0; 176 | grader("ad hoc"); 177 | grader("factorial"); 178 | grader("bubble sort"); 179 | grader("gcd"); 180 | grader("quick multiply"); 181 | grader("bisection"); 182 | grader("mutual recursion"); 183 | grader("testjr"); 184 | grader("en & clear"); 185 | grader("i-type"); 186 | $display("[Done]\n"); 187 | $display("CPI = %0f\n", $bitstoreal(cycle) / $bitstoreal(instr_count)); 188 | `ifdef checking 189 | $display("Error test: %0d\n", error_test); 190 | `endif 191 | $finish; 192 | end 193 | 194 | endmodule 195 | -------------------------------------------------------------------------------- /assignment-3(II)/index.md: -------------------------------------------------------------------------------- 1 | ##
ICS (Architecture)
2 | 3 | ###
Fudan University / 2020 Spring
4 | 5 |
Assignment 3 Part II (Branch Prediction)
6 | 7 | > There are only two hard things in Computer Science: cache invalidation and naming things. 8 | > 9 | > ​ -- Phil Karlton[^Skeptics] 10 | 11 | [^Skeptics]:https://skeptics.stackexchange.com/questions/19836/has-phil-karlton-ever-said-there-are-only-two-hard-things-in-computer-science 12 | 13 | After Part I of the assignment-3, I think you've got some clues about what the saying is talking about. Then in Part II, you are required to add branch predictor to your MIPS Pipeline Processor, which in some way is another kind of cache, recording the choices about branch to help predict the future, thus decreasing the waste of the CPU cycles. 14 | 15 | This part will make up 15% of the final score. It will **due on June 1**, and you must pass all the tests (cpu_tb.sv is to be delayed) before submitting your work. Recently we've made some **changes** to checker, please refer to [checker guidelines](https://github.com/SunflowerAries/ICS-Spring20-Fudan/blob/master/README.md#checker-configuration) for details (If you've seen this in assignment-2, you can just ignore). 16 | 17 | In Part II, you need have a look at the related chapters in *Computer Architecture: A Quantitative Approach*[^CAAQA] (e.g. 3.3 Reducing Branch Cost With Advanced Branch Prediction, Appendix C) about branch predictor and follow this doc to implement one. Before work, you need import codes in `src/`. 18 | 19 | [^CAAQA]:https://www.amazon.com/Computer-Architecture-Quantitative-John-Hennessy/dp/012383872X 20 | 21 | #### Background 22 | 23 | Now recall the value of the CPI (Cycles per Instruction), we'll have a deeper image: 24 | 25 | Pipeline CPI = Ideal pipeline CPI + Structural stalls + Data hazard stalls + Control stalls[^CAAQA] 26 | 27 | There are so many items contributing to the final CPI and engineers (and scientists) have explored so many techniques to improve them by the sophisticated design of CPU and the interesting interaction with Compiler and so on. 28 | 29 | 30 | 31 | In assignment-2, we've taken advantage of some techniques to improve our CPU, such as forwarding and bypassing, or even simple branch scheduling and prediction to decrease the CPI (due to the inherent features of our programs, always taken may have round a 60% success rate[^ICS]). 32 | 33 | [^ICS]:http://csappbook.blogspot.com/ 34 | 35 | However, that's still far from how the industry is doing, since for typical RISC programs, the average dynamic branch frequency is often between 15% and 25%, meaning that 3-6 instructions execute between a pair of branches[^CAAQA]. When we only consider the stalls caused by branch, we will have at least 1 + 0.4 \* 0.2 = 1.08 CPI, while state-of-the-art pipeline with BPB can have 90% accuracy (do not consider the hit rate), which means we can get 1 + 0.1 \* 0.2 = 1.02 CPI based on the classic 5-stage pipeline. With the introduction of Superscalar and IPC (Instructions per cycle), the performance differential may even grow larger. 36 | 37 | Although branch predictor is promising, it also incurs new challenge. 38 | $$ 39 | \mbox{CPU time} = \frac{\mbox{Seconds}}{\mbox{Program}} = \frac{\mbox{Instructions}}{\mbox{Program}}\times\frac{\mbox{Clock cycles}}{\mbox{Instruction}}\times\frac{\mbox{Seconds}}{\mbox{Clock cycles}} 40 | $$ 41 | Modern architecture's depth has been designed as more than 5 stages to lower the third item, thus leading to the extremely high misprediction penalty. Take the Intel Core i7 pipeline structure as an example, the total pipeline depth is 14 stages, with branch mispredictions typically costing 17 cycles[^CAAQA]. To obtain better performance, thus we need more sophisticated branch prediction mechanisms. 42 | 43 | **Hint**: In this part, you have to at least design a 2-bit predictor scheme, while other strategies are also welcomed. 44 | 45 | #### BPB Module 46 | 47 | Our BPB offers another choice for the update of PC, meanwhile, BPB should watch cautiously how CPU is going. You need to implement `bpb` module defined as below. 48 | 49 | ```verilog 50 | `include "bpb.vh" 51 | 52 | /** 53 | * ENTRIES : number of entries in the branch predictor buffer 54 | * TAG_WIDTH : index bits 55 | * instr_adr : if this address has been recorded, then CPU can go as the BPB directs 56 | * isbranch : in order to register the branch when first meeted 57 | * real_taken : whether this branch should be taken according to the semantics of the instructions 58 | * real_adr : where should this branch jumps to 59 | * predict_taken : whether this branch should be taken according to the prediction of our BPB 60 | * predict_adr : where should this branch jumps to if it's taken 61 | */ 62 | module bpb #( 63 | parameter ENTRIES = `BPB_E, 64 | parameter TAG_WIDTH = `BPB_T 65 | ) ( 66 | input clk, reset, stall, flush, 67 | input [TAG_WIDTH-1:0] instr_adr, 68 | 69 | input isbranch, 70 | // reality 71 | input real_taken, 72 | input [31:0] real_adr, 73 | // prediction 74 | output reg predict_taken, 75 | output reg [31:0] predict_adr 76 | ); 77 | 78 | /** 79 | * TODO: Your code here 80 | */ 81 | 82 | endmodule 83 | ``` 84 | 85 | I recommend you to design a structure like `cache` which can scale well when we change the parameters, and separating the controller module out can give you more flexibility to change your strategy. Due to its simplicity, we will not give further setting, and it's your time to design. 86 | 87 | #### Report Requirements 88 | 89 | - There's no need to include simulation results (e.g. wave plots) in your report, since you have passed all the benchtests. 90 | - You need state how your predictor works and draw the state diagram and state-transition table by yourself and include them in your report. 91 | - For the sake of intellectual property, you should list all the references, especially the pictures you include in the report (It's recommended to draw pictures on your own). 92 | 93 | - You are encouraged to implement a parameter-defined predictor (5% bonus) and to implement different prediction mechanisms (15%) and run benchtests to test the performance and give analysis. 94 | - You are encouraged to offer some interesting and useful benchtests used for BPB (not included in ours) in your report (no more than 5% bonus). 95 | 96 | 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[0x000000dc]=0x0000001d 196 | [0x00000150]=0x0000001d 197 | [0x000001c4]=0x0000001d 198 | [0x00000038]=0x0000001d 199 | [0x000000ac]=0x0000001d 200 | [0x00000120]=0x0000001d 201 | [0x00000194]=0x0000001d 202 | [0x00000008]=0x0000001d 203 | [0x0000007c]=0x0000001d 204 | [0x000000f0]=0x0000001d 205 | [0x00000164]=0x0000001d 206 | [0x000001d8]=0x0000001d 207 | [0x0000004c]=0x0000001d 208 | [0x000000c0]=0x0000001d 209 | [0x00000138]=0x0000001e 210 | [0x000001b0]=0x0000001e 211 | [0x00000028]=0x0000001e 212 | [0x000000a0]=0x0000001e 213 | [0x00000118]=0x0000001e 214 | [0x00000190]=0x0000001e 215 | [0x00000008]=0x0000001e 216 | [0x00000080]=0x0000001e 217 | [0x000000f8]=0x0000001e 218 | [0x00000170]=0x0000001e 219 | [0x000001e8]=0x0000001e 220 | [0x00000060]=0x0000001e 221 | [0x000000d8]=0x0000001e 222 | [0x00000150]=0x0000001e 223 | [0x000001c8]=0x0000001e 224 | [0x00000040]=0x0000001e 225 | [0x000000bc]=0x0000001f 226 | [0x00000138]=0x0000001f 227 | [0x000001b4]=0x0000001f 228 | [0x00000030]=0x0000001f 229 | [0x000000ac]=0x0000001f 230 | [0x00000128]=0x0000001f 231 | [0x000001a4]=0x0000001f 232 | [0x00000020]=0x0000001f 233 | [0x0000009c]=0x0000001f 234 | [0x00000118]=0x0000001f 235 | [0x00000194]=0x0000001f 236 | [0x00000010]=0x0000001f 237 | [0x0000008c]=0x0000001f 238 | [0x00000108]=0x0000001f 239 | [0x00000184]=0x0000001f 240 | [0x00000000]=0x0000001f 241 | -------------------------------------------------------------------------------- /index.html: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | Arch Course Description 8 | 10 | 11 | 12 | 13 | 14 | 15 |
16 |
17 | 18 |
19 |
20 | 21 |
22 |

23 |
Introduction to Computer System II
24 |

25 |

26 |
Fudan University / 2020 Spring
27 |

28 | 29 |
[homepage] [coursework]
30 | 31 |

32 | This course is the second part of a full year's course on computer system, and in this semester, the course is splited into two parts, 33 | the first part teaches you about the architecture of the computing hardware, and the second part touches the software that runs directly 34 | on top of the hardware, i.e. the operating system. 35 |

36 |

Logistics

37 |

38 | Part I: Architecture 39 |

40 | 45 |

46 | Part II: Introductory Operating System 47 |
48 | Note: this part is still in preparation, detailed information will be released in the near future, and the course will start from the 8th week. 49 |

50 | 55 |

Syllabus

56 |
57 | 64 | 65 | 66 | 67 | 68 | 69 | 70 | 71 | 72 | 73 | 74 | 75 | 76 | 77 | 78 | 79 | 80 | 81 | 82 | 83 | 84 | 85 | 86 | 87 | 88 | 89 | 90 | 91 | 92 | 93 | 94 | 95 | 96 | 97 | 98 | 99 | 100 | 101 | 102 | 103 | 104 | 105 | 106 | 107 | 108 | 109 | 110 | 111 | 112 | 113 | 114 | 115 | 116 | 117 | 118 | 119 | 120 | 121 | 122 | 123 | 124 | 125 | 126 | 127 | 128 | 129 | 130 | 131 | 132 | 133 | 134 | 135 | 136 | 137 | 138 | 139 | 140 | 141 | 142 | 143 | 144 | 145 | 146 | 147 | 148 | 149 | 150 | 151 | 152 | 153 | 154 | 155 |
DATECOURSENOTE
Mar   2Course Introduction
MIPS Single-Cycle Processor Implementation

Assignment 1 Released

Mar   9MIPS Pipeline Processor Implementation

Assignment 2 Released

Mar 16
Mar 23
Mar 30
Apr   6

Assignment 1 Due

Assignment 3 (Part I) Released

Apr 13
Apr 20
Apr 27

Assignment 2 Due

May   4

Assignment 3 (Part II) Released

May 11

Assignment 3 (Part I) Due

May 18

May 25
Jun   1

Assignment 3 (Part II) Due

156 |
157 |

 

158 |
159 | 160 | 161 | -------------------------------------------------------------------------------- /assignment-3(I)/benchtest/cpu_tb.sv: -------------------------------------------------------------------------------- 1 | `define PATH_PREFIX "../../../../" 2 | `define NAME "benchtest/" 3 | 4 | module cpu_tb(); 5 | 6 | logic mem_write, cpu_clk, finish, cpu_mem_write; 7 | logic [31:0] pc, instr, read_data, write_data, cpu_data_addr; 8 | 9 | reg clk, reset; 10 | reg [31:0] tb_data_addr, tb_dmem_data, pc_finished; 11 | 12 | //parameter ISIZE = 32, DSIZE = 32; 13 | 14 | 15 | string summary; 16 | // test variables 17 | integer fans, frun, fimem, fdmem, error_count, imem_counter, dmem_counter; 18 | integer cycle = 0, instr_count = 0; 19 | logic running; 20 | 21 | `ifdef checking 22 | integer error_test = 0; 23 | `endif 24 | logic ihit, dhit, stall, dcen; 25 | logic finish1, finish2, ireset; 26 | logic [31:0]cpu_wd, cpu_rd, m_wd, m_rd, cpu_instr, m_data_addr, i_ad; 27 | 28 | // module instances 29 | mips mips(.clk(cpu_clk), .reset(reset | ireset), .pc(pc), .instr(cpu_instr), .memwrite(cpu_mem_write), 30 | .aluout(cpu_data_addr), .writedata(cpu_wd), .readdata(cpu_rd), .ihit(ihit), .dhit(dhit), .dcen(dcen)); 31 | imem imem(.a(i_ad[7:2]), .rd(instr)); 32 | dmem dmem(.clk(clk), .we(mem_write), .a(m_data_addr), .wd(m_wd), .rd(m_rd)); 33 | cache icache(.clk(clk), .reset(reset | ireset), .stall(stall), .input_ready(1'b1), .addr(pc), 34 | .write_data(cpu_wd), .w_en(1'b0), .hit(ihit), .read_data(cpu_instr), 35 | .maddr(i_ad), .mread_data(instr)); 36 | cache dcache(.clk(clk), .reset(reset), .stall(stall), .input_ready(dcen), .addr(cpu_data_addr), 37 | .write_data(cpu_wd), .w_en(cpu_mem_write), .hit(dhit), .read_data(cpu_rd), 38 | .maddr(m_data_addr),.mwrite_data(m_wd),.m_wen(mem_write),.mread_data(m_rd)); 39 | 40 | // clock and reset 41 | always #20 clk = ~clk; 42 | 43 | always_ff @( posedge clk, negedge clk ) begin 44 | cpu_clk <= clk & ~finish & ~stall; 45 | end 46 | 47 | // assign mem_write = cpu_mem_write & ~finish; 48 | assign finish = ~|(pc ^ pc_finished); 49 | assign stall = ~(ihit & (~dcen | dhit)); 50 | 51 | task judge( 52 | input integer frun, 53 | input integer cycle, 54 | input string out 55 | ); 56 | string ans; 57 | ans = ""; 58 | $fscanf(frun, "%s\n", ans); 59 | if (ans != out) 60 | begin 61 | `ifdef checking 62 | error_count = error_count + 1; 63 | `else 64 | begin 65 | $display("[Error] PC: 0x%x Cycle: %0d\tExpected: %0s, Got: %0s", pc, cycle, ans, out); 66 | $stop; 67 | end 68 | `endif 69 | end 70 | endtask 71 | 72 | // judge memory 73 | task judge_memory( 74 | input integer fans 75 | ); 76 | $display("========== In memory judge =========="); 77 | begin 78 | wait(finish == 1'b1); 79 | while(!$feof(fans)) 80 | begin 81 | tb_dmem_data = 32'h0000_0000; 82 | $fscanf(fans, "%h", tb_dmem_data); 83 | if (tb_dmem_data != dmem.RAM[tb_data_addr/4]) 84 | begin 85 | $display("FAILURE: dmem 0x%0h expect 0x%0h but get 0x%0h", 86 | tb_data_addr, tb_dmem_data, dmem.RAM[tb_data_addr/4]); 87 | error_count = error_count + 1; 88 | end 89 | tb_data_addr = tb_data_addr + 4; 90 | end 91 | `ifndef checking 92 | $display("successfully pass memory judge"); 93 | `endif 94 | end 95 | endtask 96 | 97 | always_ff @(negedge clk) begin 98 | if (running) 99 | cycle <= cycle + 1; 100 | else 101 | cycle <= cycle; 102 | end 103 | 104 | // check runtime 105 | task runtime_checker( 106 | input integer frun 107 | ); 108 | string out; 109 | $display("========== In runtime checker =========="); 110 | running = 1'b1; 111 | if(frun) 112 | while(!$feof(frun)) 113 | begin@(negedge cpu_clk) 114 | // cycle = cycle + 1; 115 | 116 | if (~mips.dp.flushD & ~mips.dp.haz.stallD) 117 | instr_count = instr_count + 1; 118 | 119 | if (cpu_mem_write) 120 | begin 121 | $sformat(out, "[0x%x]=0x%x", cpu_data_addr, cpu_wd); 122 | // $display("out: %0s", out); 123 | judge(frun, cycle, out); 124 | end 125 | end 126 | running = 1'b0; 127 | `ifndef checking 128 | $display("successfully pass runtime checker"); 129 | `endif 130 | endtask 131 | 132 | initial 133 | begin 134 | // ddl to finish simulation 135 | #10000000 $display("FAILURE: Testbench Failed to finish before ddl!"); 136 | error_count = error_count + 1; 137 | $finish; 138 | end 139 | 140 | // init memory 141 | task init(input string name); 142 | imem.RAM = '{ default: '0 }; 143 | dmem.RAM = '{ default: '0 }; 144 | fimem = $fopen({ `PATH_PREFIX, `NAME, name, "/", name, ".mem"}, "r"); 145 | fdmem = $fopen({ `PATH_PREFIX, `NAME, name, "/", name, ".data"}, "r"); 146 | if (fdmem != 0) 147 | begin 148 | dmem_counter = 0; 149 | while(!$feof(fdmem)) 150 | begin 151 | dmem.RAM[dmem_counter] = 32'h0000_0000; 152 | $fscanf(fdmem, "%x", dmem.RAM[dmem_counter]); 153 | dmem_counter = dmem_counter + 1; 154 | end 155 | $fclose(fdmem); 156 | end 157 | imem_counter = 0; 158 | $display("========== In init =========="); 159 | while(!$feof(fimem)) 160 | begin 161 | imem.RAM[imem_counter] = 32'h0000_0000; 162 | $fscanf(fimem, "%x", imem.RAM[imem_counter]); 163 | imem_counter = imem_counter + 1; 164 | end 165 | $display("%0d instructions in total", imem_counter); 166 | $fclose(fimem); 167 | endtask 168 | 169 | task finishing(); 170 | wait(finish == 1'b1); 171 | ireset = 1; 172 | #50 ireset = 0; 173 | pc_finished = 32'h0000_001c; 174 | imem.RAM = '{ default: '0 }; 175 | fimem = $fopen({ `PATH_PREFIX, `NAME, "writeback", "/", "writeback", ".mem"}, "r"); 176 | imem_counter = 0; 177 | while(!$feof(fimem)) 178 | begin 179 | imem.RAM[imem_counter] = 32'h0000_0000; 180 | $fscanf(fimem, "%x", imem.RAM[imem_counter]); 181 | imem_counter = imem_counter + 1; 182 | end 183 | $fclose(fimem); 184 | endtask 185 | 186 | task grader(input string name); 187 | $display("========== Test: %0s ==========", name); 188 | begin 189 | reset = 1'b1; 190 | ireset = 1'b0; 191 | tb_dmem_data = 32'h0000_0000; 192 | tb_data_addr = 32'h0000_0000; 193 | pc_finished = 32'hffff_ffff; 194 | #50 reset = 1'b0; 195 | end 196 | init(name); 197 | fans = $fopen({ `PATH_PREFIX, `NAME, name, "/", name, ".ans"}, "r"); 198 | $fscanf(fans, "%h", pc_finished); 199 | frun = $fopen({ `PATH_PREFIX, `NAME, name, "/", name, ".run"}, "r"); 200 | error_count = 0; 201 | runtime_checker(frun); 202 | $fclose(frun); 203 | finishing(); 204 | judge_memory(fans); 205 | $fclose(fans); 206 | if (error_count != 0) 207 | begin 208 | $display("Find %0d error(s)", error_count); 209 | `ifdef checking 210 | error_test = error_test + 1; 211 | $display("[ERROR] %0s\n", name); 212 | `endif 213 | end 214 | else 215 | $display("[OK] %0s\n", name); 216 | endtask 217 | 218 | // start test 219 | initial 220 | begin 221 | clk = 1'b0; 222 | grader("ad hoc"); 223 | grader("factorial"); 224 | grader("bubble sort"); 225 | grader("gcd"); 226 | grader("quick multiply"); 227 | grader("bisection"); 228 | grader("mutual recursion"); 229 | grader("testjr"); 230 | grader("en & clear"); 231 | grader("i-type"); 232 | grader("random write"); 233 | $display("[Done]\n"); 234 | $display("CPI = %0f\n", $bitstoreal(cycle) / $bitstoreal(instr_count)); 235 | `ifdef checking 236 | $display("Error test: %0d\n", error_test); 237 | `endif 238 | $finish; 239 | end 240 | 241 | endmodule 242 | 243 | -------------------------------------------------------------------------------- /assignment-3(I)/index.md: -------------------------------------------------------------------------------- 1 | ##
ICS (Architecture)
2 | 3 | ###
Fudan University / 2020 Spring
4 | 5 |
Assignment 3 Part I (Cache)
6 | 7 | You are required to add Cache and Branch Predictor to your MIPS Pipeline Processor in assignment 3. Due to its work and doc, assignment 3 is divided into two parts. The first part is about Cache, and the latter one is about Branch Predictor. 8 | 9 | The first part will make up 25% of the final score. It will **due on May 11**, and you must pass all the tests (cpu_tb.sv is to be delayed) before submitting your work. And recently we've made some **changes** to checker, please refer to [checker guidelines](https://github.com/SunflowerAries/ICS-Spring20-Fudan/blob/master/README.md#checker-configuration) for details (If you've seen this in assignment-2, you can just ignore this). 10 | 11 | In Part I, you may recall what you've learned from ICS about cache and follow this doc to implement both instruction cache and data cache. Before work, you need import codes in `src/`. 12 | 13 | #### Description 14 | 15 | ![cache from csapp](img/cache.png) 16 | 17 | In the above picture, the 32-bit address is divided into three parts: *Tag*, *Set index*, *Block offset*. And we define the widths of each part as `CACHE_T`, `CACHE_S` and `CACHE_B` in `cache.vh`. We also get `CACHE_E` in `cache.vh`, which means there are `CACHE_E` lines in one Set. 18 | 19 | If `CACHE_B` is 4 and `CACHE_S` is 2, then each line stores 16 bytes or 4 words and there are 4 sets in one cache. 20 | 21 | When 32-bit address is given, the cache first finds the set index `i` of that address, then it checks in `set[i]` whether there exists a line whose tag matches the tag of the address. If so, the cache hits or else the cache misses and we need to load a block of data from the memory into the cache line. 22 | 23 | In the real world, memory can provide at most 32 bits of data in one clock cycle on a 32-bit processor. So if we want to read a block of data from memory, we need plenty of clock cycles to get all of them. 24 | 25 | Under cache miss, if the selected set is full of valid lines and we choose a dirty line to be replaced, we should first write data back to memory and load new data into this line. 26 | 27 | To do those above, you'd better use *Finite State Machines*(FSMs) in the cache. 28 | 29 | #### Cache Module 30 | 31 | Our cache module will act like a bridge between MIPS processor and the memory. You need to implement `cache` module defined below. Besides, you may need to block your processor during the cache miss. 32 | 33 | `cache.v`: 34 | 35 | ```verilog 36 | `include "cache.vh" 37 | 38 | /** 39 | * NOTE: The sum of TAG_WIDTH, SET_WIDTH and OFFSET_WIDTH should be 32 40 | * 41 | * TAG_WIDTH : (t) tag bits 42 | * SET_WIDTH : (s) set index bits, the number of sets is 2**SET_WIDTH 43 | * OFFSET_WIDTH : (b) block offset bits 44 | * LINES : number of lines per set 45 | * 46 | * stall : inorder to synchronize instruction memroy cache and data memroy cache, you may need this so that two caches will write data at most once per instruction respectively. 47 | * 48 | * input_ready : whether input data from processor are ready 49 | * addr : cache read/write address from processor 50 | * write_data : cache write data from processor 51 | * w_en : cache write enable 52 | * hit : whether cache hits 53 | * read_data : data read from cache 54 | * 55 | * maddr : memory address 56 | * mwrite_data : data written to memory 57 | * m_wen : memory write enable 58 | * mread_data : data read from memory 59 | */ 60 | module cache #( 61 | parameter TAG_WIDTH = `CACHE_T, 62 | SET_WIDTH = `CACHE_S, 63 | OFFSET_WIDTH = `CACHE_B, 64 | LINES = `CACHE_E 65 | )( 66 | input clk, reset, stall, 67 | 68 | // interface with CPU 69 | input input_ready, 70 | input [31:0] addr, write_data, 71 | input w_en, 72 | output hit, 73 | output [31:0] read_data, 74 | 75 | // interface with memory 76 | output [31:0] maddr, mwrite_data, 77 | output m_wen, 78 | input [31:0] mread_data 79 | /* input mready // memory ready ? */ 80 | ); 81 | 82 | /** 83 | * TODO: Your code here 84 | */ 85 | 86 | endmodule 87 | ``` 88 | 89 | `cache.vh`: 90 | 91 | ```verilog cache.vh 92 | `ifndef CACHE_VH 93 | `define CACHE_VH 94 | 95 | `timescale 1ns / 1ps 96 | 97 | `define ADDR_WIDTH 32 98 | 99 | // tag bits 100 | `define CACHE_T 26 101 | // set index bits 102 | `define CACHE_S 2 103 | // block offset bits 104 | `define CACHE_B 4 105 | // The sum of above bits should be 32 (ADDR_WIDTH) 106 | 107 | // number of lines per set 108 | `define CACHE_E 4 109 | 110 | `define SET_NUM 2**`CACHE_S 111 | `define BLOCK_SIZE 2**`CACHE_B 112 | 113 | `endif 114 | ``` 115 | 116 | You'd better review *6.4 Cache Memories* in CSAPP first and understand how `cache` `set` and `line` modules should be organized (*PS*: you'd better also create a module for Line Replacement Strategy). You can refer to module declarations listed below. 117 | 118 | **Hint**: declarations below are for reference only. You may modify them (e.g. exposed ports) according to your way to implement cache (and we think there should be **no changes to cache.v** because we think all the ports are musts and we should set up these ports to ease our testing). 119 | 120 | #### Reference Implementation 121 | 122 | ##### Structure 123 | 124 | Below is the structure of `cache` module. `cache_controller`, `replacement_controller`, `set`, `line` modules are instantiated directly or indirectly in `cache`. 125 | 126 | ``` 127 | cache 128 | +-- cache_controller 129 | +-- set[0] 130 | | +-- replacement_controller 131 | | +-- line[0] 132 | | +-- line[1] 133 | | +-- line[2] 134 | | +-- line[3] 135 | +-- set[1] 136 | +-- set[2] 137 | +-- set[3] 138 | ``` 139 | 140 | In `cache` module, there are several sets and a `cache_controller` which is implemented with FSMs to control the cache. 141 | 142 | `cache_controller` will provide control signals and you need to send these control signals to the corresponding cache set (decided by the set index of address from processor), and in that cache set, control signals needed by `line` should be assigned to the correct cache line (line's tag matches the tag of address). 143 | 144 | Every `set` instantiate a `replacement_controller`. If cache misses and the set is full, `replacement_controller` in the set will select one line to kick off. Besides, you should make sure the replacement strategy in `replacement_controller` updates its states correctly. 145 | 146 | ##### Line 147 | 148 | ```verilog 149 | `include "cache.vh" 150 | /** 151 | * w_en: write enable 152 | */ 153 | module line #( 154 | parameter TAG_WIDTH = `CACHE_T, 155 | OFFSET_WIDTH = `CACHE_B 156 | )( 157 | input clk, reset, 158 | input [OFFSET_WIDTH - 3:0] offset, 159 | input w_en, set_valid, set_dirty, 160 | input [TAG_WIDTH - 1:0] set_tag, 161 | input [31:0] write_data, 162 | output reg valid, 163 | output dirty, 164 | output reg [TAG_WIDTH - 1:0] tag, 165 | output [31:0] read_data 166 | ); 167 | 168 | /** 169 | * TODO: Your code here 170 | */ 171 | 172 | endmodule 173 | ``` 174 | 175 | The `line` module behaves quite like `dmem` except that there are extra properties(registers) and corresponding control signals like `valid`, `dirty`, `tag` and `set_valid`, `set_dirty`, `set_tag`. 176 | If `w_en` is 1, not only will `write_data` be written into `line`, but also `set_valid`, `set_dirty` and `set_tag` will be assigned to `valid`, `dirty` and `tag` registers in this clock cycle. If `w_en` is 0, nothing will be changed in `line`. 177 | 178 | ##### Set 179 | 180 | ```verilog 181 | `include "cache.vh" 182 | /** 183 | * ctls : control signals from cache_controller 184 | * addr : cache read/write address from processor 185 | * write_data : cache write data from processor 186 | * mread_data : data read from memory 187 | * 188 | * hit : whether cache set hits 189 | * dirty : from the cache line selected by addr (cache line's tag is equal to addr's tag) 190 | */ 191 | module set #( 192 | parameter TAG_WIDTH = `CACHE_T, 193 | OFFSET_WIDTH = `CACHE_B, 194 | LINES = `CACHE_E 195 | )( 196 | input clk, reset, 197 | input [4 + OFFSET_WIDTH-2:0] ctls, 198 | input [31:0] addr, write_data, mread_data, 199 | output hit, dirty, 200 | output [31:0] read_data 201 | ); 202 | 203 | wire w_en, set_valid, set_dirty, init, offsetSW; 204 | wire [OFFSET_WIDTH - 3:0] offset; 205 | 206 | // control signals will be assigned to the target line instance. 207 | assign {w_en, set_valid, set_dirty, offset, strategy_en, offset_sel} = ctls; 208 | 209 | /** 210 | * TODO: Your code here 211 | */ 212 | 213 | endmodule 214 | ``` 215 | 216 | `set` module will instantiate several `line` modules. To conveniently instantiate an array of custom modules, follow [this link](https://stackoverflow.com/questions/1378159/can-we-have-an-array-of-custom-modules) for more details. Besides, you'd better use a *Line Replacement Strategy* module(`replacement_controller`) in `set` module. 217 | 218 | The `ctls` are control signals from `cache_controller` and part of them should be sent to cache line whose tag matches address's tag. 219 | 220 | In `ctls`, `strategy_en` is the enable signal of Line Replacement Strategy. The reason why we need it is that there may be lots of clock cycles in one cycle of cache read/write, and some replacement strategy (eg. LFU) may be affected if the strategy runs in every clock cycle. 221 | 222 | `offset_sel` is used to select from `mread_data` and `write_data`. The selected data will be written into `line` as `write_data`. 223 | 224 | ##### Cache Controller 225 | 226 | ```verilog 227 | /** 228 | * en : en in cache module 229 | * cw_en : cache writing enable signal, from w_en in cache module 230 | * hit, dirty : from set module 231 | * 232 | * w_en : writing enable signal to cache line 233 | * mw_en : writing enable signal to memory , controls whether to write to memory 234 | * set_valid : control signal for cache line 235 | * set_dirty : control signal for cache line 236 | * offset_sel : control signal for cache line and this may be used in other places 237 | */ 238 | module cache_controller #( 239 | parameter OFFSET_WIDTH = `CACHE_B 240 | )( 241 | input clk, reset, en, cw_en, hit, dirty, // mready, 242 | output w_en, set_valid, set_dirty, mw_en, 243 | output [OFFSET_WIDTH - 3:0] block_offset, 244 | output strategy_en, 245 | output reg offset_sel 246 | ); 247 | 248 | /** 249 | * TODO: Your code here 250 | */ 251 | 252 | endmodule 253 | ``` 254 | 255 | Personally, I suggest you use two FSMs. One is used to count on offset. The other records the action state of cache: `ReadMem`(read block from memory), `WriteBack`(write block to memory), `Initial`(initial state), etc. Also you should notice that there are connections between these two FSMs. For example, `WriteBack` will change to `ReadMem` only when offset is certain value. 256 | 257 | #### Report Requirements 258 | 259 | - There's no need to include simulation results (e.g. wave plots) in your report, since you have passed all the benchtests. 260 | - You need state how your cache works and draw the state diagram and state-transition table by yourself and include them in your report. 261 | - For the sake of intellectual property, you should list all the references, especially the pictures you include in the report (It's recommended to draw pictures on your own). 262 | 263 | - You are encouraged to implement a parameter-defined cache (15% bonus). Otherwise, please implement 4-way associative cache with 4 sets and each of line stores 16 bytes. 264 | - You are encouraged to offer some interesting and useful benchtests used for cache (not included in ours) in your report (no more than 5% bonus). 265 | 266 | --------------------------------------------------------------------------------