├── .gitattributes ├── .gitignore ├── LICENSE ├── QSFP-HDMI-OUT-NB7NQ621M ├── README-zh.md ├── README.md ├── board │ ├── QSFP-HDMI-OUT-NB7NQ621M.kicad_pcb │ ├── QSFP-HDMI-OUT-NB7NQ621M.kicad_pro │ ├── QSFP-HDMI-OUT-NB7NQ621M.kicad_sch │ ├── fp-lib-table │ └── sym-lib-table ├── examples │ ├── ADM-PCIE-KU3 │ │ ├── build.py │ │ ├── constraints │ │ │ └── Timing.xdc │ │ ├── scripts │ │ │ ├── Config.tcl │ │ │ ├── CreateProject.tcl │ │ │ └── IP │ │ │ │ ├── GTWizard0.tcl │ │ │ │ ├── GTWizard1.tcl │ │ │ │ └── MMCM0.tcl │ │ └── sources │ │ │ ├── GTWizardWrapper.v │ │ │ ├── Si5338.v │ │ │ └── Top.v │ ├── Alibaba-VU13P │ │ ├── build.py │ │ ├── constraints │ │ │ └── Timing.xdc │ │ ├── scripts │ │ │ ├── Config.tcl │ │ │ ├── CreateProject.tcl │ │ │ └── IP │ │ │ │ ├── GTWizard0.tcl │ │ │ │ ├── GTWizard1.tcl │ │ │ │ └── PLL0.tcl │ │ └── sources │ │ │ ├── GTWizardWrapper.v │ │ │ └── Top.v │ ├── BoChenJingXin-KU5P │ │ ├── build.py │ │ ├── constraints │ │ │ └── Timing.xdc │ │ ├── scripts │ │ │ ├── Config.tcl │ │ │ ├── CreateProject.tcl │ │ │ └── IP │ │ │ │ ├── GTWizard0.tcl │ │ │ │ └── MMCM0.tcl │ │ └── sources │ │ │ ├── GTWizardWrapper.v │ │ │ └── Top.v │ ├── Longs-Peak │ │ ├── build.py │ │ ├── constraints │ │ │ └── Timing.sdc │ │ ├── scripts │ │ │ ├── CreateIP.tcl │ │ │ ├── CreateProject.tcl │ │ │ └── IP │ │ │ │ ├── PLL0.tcl │ │ │ │ ├── XCVR0.tcl │ │ │ │ ├── XCVRFPLL0.tcl │ │ │ │ └── XCVRReset0.tcl │ │ └── sources │ │ │ ├── Arbiter.v │ │ │ ├── DS250DF810.v │ │ │ ├── Top.v │ │ │ └── XCVRWrapper.v │ ├── MLK-H8-CU06-KU5P │ │ ├── build.py │ │ ├── constraints │ │ │ └── Timing.xdc │ │ ├── scripts │ │ │ ├── Config.tcl │ │ │ ├── CreateProject.tcl │ │ │ └── IP │ │ │ │ ├── GTWizard0.tcl │ │ │ │ └── MMCM0.tcl │ │ └── sources │ │ │ ├── GTWizardWrapper.v │ │ │ └── Top.v │ ├── RK-XCKU5P-F │ │ ├── build.py │ │ ├── constraints │ │ │ └── Timing.xdc │ │ ├── scripts │ │ │ ├── Config.tcl │ │ │ ├── CreateProject.tcl │ │ │ └── IP │ │ │ │ ├── GTWizard0.tcl │ │ │ │ └── MMCM0.tcl │ │ └── sources │ │ │ ├── GTWizardWrapper.v │ │ │ └── Top.v │ └── Storey-Peak │ │ ├── build.py │ │ ├── constraints │ │ └── Timing.sdc │ │ ├── scripts │ │ ├── CreateIP.tcl │ │ ├── CreateProject.tcl │ │ └── IP │ │ │ ├── PLL0.tcl │ │ │ ├── XCVR0.tcl │ │ │ ├── XCVRReconfiguration0.tcl │ │ │ └── XCVRReset0.tcl │ │ └── sources │ │ ├── IDT8N4Q001.v │ │ ├── Top.v │ │ └── XCVRWrapper.v ├── images │ ├── Module-Photo-1.jpg │ ├── Module-Photo-2.jpg │ └── Module-Photo-3.jpg └── shell │ ├── Label.png │ ├── QSFP-HDMI-OUT-NB7NQ621M-Shell-1.stl │ └── QSFP-HDMI-OUT-NB7NQ621M-Shell-2.stl ├── README.md └── common ├── Chisel ├── .mill-version ├── build.mill ├── hdmi │ ├── package.mill │ └── src │ │ ├── common │ │ ├── HDMIDataIslandPacket.scala │ │ ├── HDMIScramblerLFSR.scala │ │ └── HDMIVideoTiming.scala │ │ ├── source │ │ └── HDMISource.scala │ │ └── tmds │ │ ├── HDMITMDSEncoder.scala │ │ └── HDMITMDSScrambler.scala └── hdmioutexample │ ├── package.mill │ └── src │ └── HDMIOutExample.scala ├── KiCad ├── footprints │ ├── Connector_SFF.pretty │ │ └── QSFP-Plug.kicad_mod │ └── Interface_HDMI_Onsemi.pretty │ │ └── Onsemi_X2QFN38_4.05x4.50mm_P0.4mm.kicad_mod └── symbols │ ├── Connector_SFF.kicad_sym │ ├── Interface_HDMI_Onsemi.kicad_sym │ └── Power_Protection_AMAZING.kicad_sym ├── OpenOCD ├── Longs-Peak │ └── Config.cfg └── Storey-Peak │ └── Config.cfg ├── Quartus └── constraints │ ├── Longs-Peak │ ├── Clock.tcl │ ├── LED.tcl │ └── QSFP.tcl │ └── Storey-Peak │ ├── Clock.tcl │ ├── IDT8N4Q001.tcl │ ├── LED.tcl │ ├── QSFP0.tcl │ └── QSFP1.tcl ├── Verilog ├── hdmi │ ├── HDMIOUTExample.v │ └── VideoGenerator.v └── i2c │ └── I2CMaster.v └── Vivado ├── constraints ├── ADM-PCIE-KU3 │ ├── Clock.xdc │ ├── Config.xdc │ ├── LED.xdc │ ├── QSFP0.xdc │ ├── QSFP1.xdc │ └── Si5338.xdc ├── Alibaba-VU13P │ ├── Clock.xdc │ ├── Config.xdc │ ├── LED.xdc │ ├── QSFP1.xdc │ └── QSFP2.xdc ├── BoChenJingXin-KU5P │ ├── Clock.xdc │ ├── Config.xdc │ ├── Key.xdc │ ├── LED.xdc │ └── QSFP.xdc ├── MLK-H8-CU06-KU5P │ ├── Clock.xdc │ ├── Config.xdc │ ├── Key.xdc │ ├── LED.xdc │ └── QSFP.xdc └── RK-XCKU5P-F │ ├── Clock.xdc │ ├── Config.xdc │ ├── Key.xdc │ ├── LED.xdc │ └── QSFP.xdc └── scripts ├── Flash.tcl ├── GenerateBitstream.tcl ├── Implementation.tcl ├── Program.tcl └── Synthesis.tcl /.gitattributes: -------------------------------------------------------------------------------- 1 | * text=auto 2 | 3 | *.jpg filter=lfs diff=lfs merge=lfs -text 4 | *.png filter=lfs diff=lfs merge=lfs -text 5 | *.stl filter=lfs diff=lfs merge=lfs -text 6 | -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | # VSCode 2 | .vscode 3 | 4 | # KiCad 5 | *.bak 6 | *.kicad_prl 7 | *.lck 8 | *.tmp 9 | *-backups 10 | fp-info-cache 11 | 12 | # KiCad Fabrication Toolkit 13 | fabrication-toolkit-options.json 14 | production 15 | 16 | # Chisel 17 | .bloop 18 | .metals 19 | .scala-build 20 | out 21 | 22 | # Vivado 23 | build 24 | -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | DO WHAT THE FUCK YOU WANT TO PUBLIC LICENSE 2 | Version 2, December 2004 3 | 4 | Copyright (C) 2004 Sam Hocevar 5 | 6 | Everyone is permitted to copy and distribute verbatim or modified 7 | copies of this license document, and changing it is allowed as long 8 | as the name is changed. 9 | 10 | DO WHAT THE FUCK YOU WANT TO PUBLIC LICENSE 11 | TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION 12 | 13 | 0. You just DO WHAT THE FUCK YOU WANT TO. 14 | -------------------------------------------------------------------------------- /QSFP-HDMI-OUT-NB7NQ621M/README-zh.md: -------------------------------------------------------------------------------- 1 | # QSFP-HDMI-OUT-NB7NQ621M 2 | 3 | ![Module Photo 1](./images/Module-Photo-1.jpg) 4 | 5 |

6 | English | 7 | 中文 8 |

9 | 10 | --- 11 | 12 | [![GitHub Stars](https://img.shields.io/github/stars/SuperSodaSea/Plugcat.svg?style=social)](https://github.com/SuperSodaSea/Plugcat/stargazers) 13 | [![GitHub License](https://img.shields.io/github/license/SuperSodaSea/Plugcat)](https://github.com/SuperSodaSea/Plugcat/blob/main/LICENSE) 14 | 15 | 还在为 FPGA 板卡缺少视频输出接口而发愁吗？这款小巧精致的创新模块可以帮您！QSFP-HDMI-OUT-NB7NQ621M 是一款具有 HDMI 输出接口的 QSFP 模块：只需将其插入 FPGA 板卡上的 QSFP 插槽中，即可立即使板卡获得 HDMI 输出功能。这将极大提高您 FPGA 板卡的可扩展性。 16 | 17 | ## 特性 18 | 19 | - 使用 [NB7NQ621M](https://www.onsemi.com/products/signal-conditioning-control/redrivers/NB7NQ621M) 重驱动器芯片，支持HDMI 2.1 视频信号输出，带宽高达 48Gbps 20 | - 提供 HDMI 2.0 TMDS 示例代码，支持 1920x1080@240Hz、2560x1440@144Hz、3840x2160@60Hz 等显示模式 21 | - HDMI 2.1 FRL 待后续提供，您可以使用任意 HDMI 2.1 IP 核 22 | 23 | ## 引脚描述 24 | 25 | | 名称 | 描述 | 26 | |---------|-----------------------------------| 27 | | TX1p | HDMI CK+ | 28 | | TX1n | HDMI CK- | 29 | | TX2p | HDMI D0+ | 30 | | TX2n | HDMI D0- | 31 | | TX3p | HDMI D1+ | 32 | | TX3n | HDMI D1- | 33 | | TX4p | HDMI D2+ | 34 | | TX4n | HDMI D2- | 35 | | ModPrsL | 为低电平时，HDMI 线缆为插入状态 | 36 | | ResetL | 为低电平时，重置 NB7NQ621M | 37 | | SCL | NB7NQ621M 和 HDMI DDC 的 I2C 时钟 | 38 | | SDA | NB7NQ621M 和 HDMI DDC 的 I2C 数据 | 39 | 40 | ## PCB 信息 41 | 42 | - 厚度: 1.00mm 43 | - 叠层结构: JLC04101H-3313 44 | 45 | ## 已验证的 FPGA 板卡 46 | 47 | 48 | 49 | 50 | 51 | 52 | 53 | 54 | 55 | 56 | 57 | 58 | 59 | 60 | 61 | 62 | 63 | 64 | 65 | 66 | 67 | 68 | 69 | 70 | 71 | 72 | 73 | 74 | 75 | 76 | 77 | 78 | 79 | 80 | 81 | 82 | 83 | 84 | 85 | 86 | 87 | 88 | 89 | 90 | 91 | 92 | 93 | 94 | 95 | 96 | 97 | 98 | 99 | 100 | 101 | 102 | 103 | 104 | 105 | 106 | 107 | 108 | 109 | 110 | 111 | 112 | 113 | 114 | 115 | 116 | 117 | 118 | 119 | 120 | 121 | 122 | 123 |
FPGA板卡示例代码
Xilinx Zynq 7000 SoC
XC7Z100公子哥 玄武 ZYNQ7100 + FMC 转 QSFP 子板
Xilinx Kintex Ultrascale
XCKU060Alpha Data ADM-PCIE-KU3🔗
Xilinx Kintex UltraScale+
XCKU5P博宸精芯 KU5P🔗
XCKU5PRIGUKE RK-XCKU5P-F🔗
XCKU5P米联客 MLK-H8-CU06-KU5P🔗
Xilinx Virtex UltraScale+
XCVU13P阿里巴巴 VU13P🔗
Altera Stratix V GS
5SGSKF40I3LNAC微软 Catapult v2 Storey Peak / X930613-001🔗
Altera Arria 10 GX
10AXF40AA微软 Catapult v3 Longs Peak / Model: 1768🔗
紫光同创 Titan-2
PG2T390H小眼睛泰坦 390H + FMC 转 QSFP 子板
124 | 125 | ## 示例代码 126 | 127 | 示例代码在 Windows 与 Linux 下均可构建。 128 | 129 | ### 依赖工具 130 | 131 | - [Python 3](https://www.python.org/)（用于构建脚本） 132 | - [Java](https://www.java.com/)（用于 Chisel） 133 | - [Mill](https://mill-build.org/mill/index.html)（用于 Chisel） 134 | - [Vivado](https://www.amd.com/en/products/software/adaptive-socs-and-fpgas/vivado.html)（用于构建 Xilinx FPGA 工程） 135 | - [Quartus Prime](https://www.intel.com/content/www/us/en/products/details/fpga/development-tools/quartus-prime.html)（用于构建 Altera FPGA 工程） 136 | 137 | ### 构建示例代码 138 | 139 | 在对应示例代码目录下运行以下命令即可构建示例代码： 140 | 141 | ```bash 142 | python build.py build 143 | ``` 144 | 145 | 示例代码的默认视频模式为 `1920x1080@60Hz`。若需要更改分辨率和刷新率，可通过命令行参数指定： 146 | 147 | ```bash 148 | python build.py build --resolution 2560x1440 --refresh-rate 144 149 | ``` 150 | 151 | 支持的视频模式： 152 | - `1920x1080@30/60/120/144/240Hz` 153 | - `2560x1440@30/60/120/144Hz` 154 | - `3840x2160@30/60Hz` 155 | 156 | 其他分辨率可自行修改代码实现。 157 | 158 | ### 下载位流 159 | 160 | ```shell 161 | python build.py program 162 | ``` 163 | 164 | ### 固化位流 165 | 166 | ```shell 167 | python build.py flash 168 | ``` 169 | 170 | ## 画廊 171 | 172 | ![Module Photo 2](./images/Module-Photo-2.jpg) 173 | ![Module Photo 3](./images/Module-Photo-3.jpg) 174 | -------------------------------------------------------------------------------- /QSFP-HDMI-OUT-NB7NQ621M/README.md: -------------------------------------------------------------------------------- 1 | # QSFP-HDMI-OUT-NB7NQ621M 2 | 3 | ![Module Photo 1](./images/Module-Photo-1.jpg) 4 | 5 |

6 | English | 7 | 中文 8 |

9 | 10 | --- 11 | 12 | [![GitHub Stars](https://img.shields.io/github/stars/SuperSodaSea/Plugcat.svg?style=social)](https://github.com/SuperSodaSea/Plugcat/stargazers) 13 | [![GitHub License](https://img.shields.io/github/license/SuperSodaSea/Plugcat)](https://github.com/SuperSodaSea/Plugcat/blob/main/LICENSE) 14 | 15 | Bothered by the lack of video output interface on your FPGA boards? This tiny innovative module can help you! QSFP-HDMI-OUT-NB7NQ621M is a QSFP module with HDMI output connector: simply plug it into the QSFP socket on your FPGA boards and get HDMI output capability instantly. This greatly enhances the extensibility of your FPGA boards. 16 | 17 | ## Features 18 | 19 | - Uses [NB7NQ621M](https://www.onsemi.com/products/signal-conditioning-control/redrivers/NB7NQ621M) redriver chip, supports HDMI 2.1 video signal output, bandwidth up to 48Gbps 20 | - HDMI 2.0 TMDS example code provided, supports display modes such as 1920x1080@240Hz, 2560x1440@144Hz, 3840x2160@60Hz, etc. 21 | - HDMI 2.1 FRL example code TBA, you can use arbitrary HDMI 2.1 IP core 22 | 23 | ## Pin Description 24 | 25 | | Name | Description | 26 | |---------|-----------------------------------------------| 27 | | TX1p | HDMI CK+ | 28 | | TX1n | HDMI CK- | 29 | | TX2p | HDMI D0+ | 30 | | TX2n | HDMI D0- | 31 | | TX3p | HDMI D1+ | 32 | | TX3n | HDMI D1- | 33 | | TX4p | HDMI D2+ | 34 | | TX4n | HDMI D2- | 35 | | ModPrsL | HDMI cable is plugged in when low | 36 | | ResetL | Reset NB7NQ621M when low | 37 | | SCL | I2C clock for both the NB7NQ621M and HDMI DDC | 38 | | SDA | I2C data for both the NB7NQ621M and HDMI DDC | 39 | 40 | ## PCB Information 41 | 42 | - Thickness: 1.00mm 43 | - Layer Stackup: JLC04101H-3313 44 | 45 | ## Verified FPGA Boards 46 | 47 | 48 | 49 | 50 | 51 | 52 | 53 | 54 | 55 | 56 | 57 | 58 | 59 | 60 | 61 | 62 | 63 | 64 | 65 | 66 | 67 | 68 | 69 | 70 | 71 | 72 | 73 | 74 | 75 | 76 | 77 | 78 | 79 | 80 | 81 | 82 | 83 | 84 | 85 | 86 | 87 | 88 | 89 | 90 | 91 | 92 | 93 | 94 | 95 | 96 | 97 | 98 | 99 | 100 | 101 | 102 | 103 | 104 | 105 | 106 | 107 | 108 | 109 | 110 | 111 | 112 | 113 | 114 | 115 | 116 | 117 | 118 | 119 | 120 | 121 | 122 | 123 |
FPGABoardExample
Xilinx Zynq 7000 SoC
XC7Z100GongZiGe XuanWu ZYNQ7100 + FMC to QSFP daughter board
Xilinx Kintex Ultrascale
XCKU060Alpha Data ADM-PCIE-KU3🔗
Xilinx Kintex UltraScale+
XCKU5PBoChenJingXin KU5P🔗
XCKU5PRIGUKE RK-XCKU5P-F🔗
XCKU5PMilianke MLK-H8-CU06-KU5P🔗
Xilinx Virtex UltraScale+
XCVU13PAlibaba VU13P🔗
Altera Stratix V GS
5SGSKF40I3LNACMicrosoft Catapult v2 Storey Peak / X930613-001🔗
Altera Arria 10 GX
10AXF40AAMicrosoft Catapult v3 Longs Peak / Model: 1768🔗
Pango Titan-2
PG2T390HXiaoYanJing Titan 390H + FMC to QSFP daughter board
124 | 125 | ## Example Code 126 | 127 | The example code can be built on both Windows and Linux. 128 | 129 | ### Dependencies 130 | 131 | - [Python 3](https://www.python.org/) (for build scripts) 132 | - [Java](https://www.java.com/) (for Chisel) 133 | - [Mill](https://mill-build.org/mill/index.html) (for Chisel) 134 | - [Vivado](https://www.amd.com/en/products/software/adaptive-socs-and-fpgas/vivado.html) (for building Xilinx FPGA projects) 135 | - [Quartus Prime](https://www.intel.com/content/www/us/en/products/details/fpga/development-tools/quartus-prime.html) (for building Altera FPGA projects) 136 | 137 | ### Build Example Code 138 | 139 | Execute the following commands in the corresponding directory to build the example code: 140 | 141 | ```bash 142 | python build.py build 143 | ``` 144 | 145 | The default video mode is 1920x1080@60Hz. To change the video mode, add the following parameters to the build command: 146 | 147 | ```bash 148 | python build.py build --resolution 2560x1440 --refresh-rate 144 149 | ``` 150 | 151 | Supported video modes: 152 | 153 | - `1920x1080@30/60/120/144/240Hz` 154 | - `2560x1440@30/60/120/144Hz` 155 | - `3840x2160@30/60Hz` 156 | 157 | Other resolutions can be implemented by modifying the code. 158 | 159 | ### Programming Bitstream 160 | 161 | ```bash 162 | python build.py program 163 | ``` 164 | 165 | ### Flashing Bitstream 166 | 167 | ```bash 168 | python build.py flash 169 | ``` 170 | 171 | ## Gallery 172 | 173 | ![Module Photo 2](./images/Module-Photo-2.jpg) 174 | ![Module Photo 3](./images/Module-Photo-3.jpg) 175 | -------------------------------------------------------------------------------- /QSFP-HDMI-OUT-NB7NQ621M/board/fp-lib-table: -------------------------------------------------------------------------------- 1 | (fp_lib_table 2 | (version 7) 3 | (lib (name "Connector_SFF")(type "KiCad")(uri "${KIPRJMOD}/../../common/KiCad/footprints/Connector_SFF.pretty")(options "")(descr "")) 4 | (lib (name "Interface_HDMI_Onsemi")(type "KiCad")(uri "${KIPRJMOD}/../../common/KiCad/footprints/Interface_HDMI_Onsemi.pretty")(options "")(descr "")) 5 | ) 6 | -------------------------------------------------------------------------------- /QSFP-HDMI-OUT-NB7NQ621M/board/sym-lib-table: -------------------------------------------------------------------------------- 1 | (sym_lib_table 2 | (version 7) 3 | (lib (name "Connector_SFF")(type "KiCad")(uri "${KIPRJMOD}/../../common/KiCad/symbols/Connector_SFF.kicad_sym")(options "")(descr "")) 4 | (lib (name "Interface_HDMI_Onsemi")(type "KiCad")(uri "${KIPRJMOD}/../../common/KiCad/symbols/Interface_HDMI_Onsemi.kicad_sym")(options "")(descr "")) 5 | (lib (name "Power_Protection_AMAZING")(type "KiCad")(uri "${KIPRJMOD}/../../common/KiCad/symbols/Power_Protection_AMAZING.kicad_sym")(options "")(descr "")) 6 | ) 7 | -------------------------------------------------------------------------------- /QSFP-HDMI-OUT-NB7NQ621M/examples/ADM-PCIE-KU3/build.py: -------------------------------------------------------------------------------- 1 | import argparse 2 | import os 3 | import shutil 4 | import subprocess 5 | 6 | VIVADO = os.getenv('VIVADO', shutil.which('vivado')) 7 | MILL = os.getenv('MILL', shutil.which('mill')) 8 | 9 | RESOLUTION_LIST = [ 10 | '1920x1080', 11 | '2560x1440', 12 | '3840x2160', 13 | ] 14 | REFRESH_RATE_LIST = [ 15 | '30', 16 | '60', 17 | '120', 18 | '144', 19 | '240', 20 | ] 21 | 22 | PROJECT_PATH = os.path.dirname(os.path.realpath(__file__)) 23 | COMMON_PATH = os.path.join(PROJECT_PATH, '..', '..', '..', 'common') 24 | COMMON_CHISEL_PATH = os.path.join(COMMON_PATH, 'Chisel') 25 | COMMON_SCRIPTS_PATH = os.path.join(COMMON_PATH, 'Vivado', 'scripts') 26 | SCRIPTS_PATH = os.path.join(PROJECT_PATH, 'scripts') 27 | CONFIG_PATH = os.path.join(SCRIPTS_PATH, 'Config.tcl') 28 | BUILD_PATH = os.path.join(PROJECT_PATH, 'build') 29 | GENERATED_PATH = os.path.join(BUILD_PATH, 'generated') 30 | BITSTREAM_PATH = os.path.join(BUILD_PATH, 'bitstream') 31 | 32 | def runCommand(command, **kwargs): 33 | print(command) 34 | subprocess.run(command, check = True, **kwargs) 35 | 36 | def runVivadoScript(script, *args): 37 | runCommand([VIVADO, '-nojournal', '-nolog', '-mode', 'batch', '-source', script, '-tclargs', *args], cwd = BUILD_PATH) 38 | 39 | if __name__ == "__main__": 40 | parser = argparse.ArgumentParser() 41 | parser.add_argument('command', choices = ['build', 'program', 'flash']) 42 | parser.add_argument('--resolution', choices = RESOLUTION_LIST, default = '1920x1080') 43 | parser.add_argument('--refresh-rate', choices = REFRESH_RATE_LIST, default = '60') 44 | parser.add_argument('-j', '--jobs', default = '8') 45 | args = parser.parse_args() 46 | 47 | RESOLUTION = args.resolution 48 | REFRESH_RATE = args.refresh_rate 49 | JOBS = args.jobs 50 | 51 | if args.command == 'build': 52 | os.makedirs(GENERATED_PATH, exist_ok = True) 53 | runCommand([MILL, 'hdmioutexample.run', '-o', os.path.join(GENERATED_PATH, 'HDMIOutExample.sv')], cwd = COMMON_CHISEL_PATH) 54 | 55 | runVivadoScript(os.path.join(SCRIPTS_PATH, 'CreateProject.tcl'), RESOLUTION, REFRESH_RATE) 56 | runVivadoScript(os.path.join(COMMON_SCRIPTS_PATH, 'Synthesis.tcl'), CONFIG_PATH, JOBS) 57 | runVivadoScript(os.path.join(COMMON_SCRIPTS_PATH, 'Implementation.tcl'), CONFIG_PATH, JOBS) 58 | runVivadoScript(os.path.join(COMMON_SCRIPTS_PATH, 'GenerateBitstream.tcl'), CONFIG_PATH, BITSTREAM_PATH) 59 | elif args.command == 'program': 60 | runVivadoScript(os.path.join(COMMON_SCRIPTS_PATH, 'Program.tcl'), CONFIG_PATH, BITSTREAM_PATH) 61 | elif args.command == 'flash': 62 | runVivadoScript(os.path.join(COMMON_SCRIPTS_PATH, 'Flash.tcl'), CONFIG_PATH, BITSTREAM_PATH) 63 | else: 64 | assert False 65 | -------------------------------------------------------------------------------- /QSFP-HDMI-OUT-NB7NQ621M/examples/ADM-PCIE-KU3/constraints/Timing.xdc: -------------------------------------------------------------------------------- 1 | # System clock frequency = 200MHz 2 | create_clock -name system_clock -period 5 -quiet [get_nets system_clock] 3 | 4 | # Maximum TX clock frequency = 6GHz / 40 bits per clock = 150MHz 5 | create_clock -name tx_clock_0 -period 6.666 -quiet [get_nets tx_clock_0] 6 | create_clock -name tx_clock_1 -period 6.666 -quiet [get_nets tx_clock_1] 7 | 8 | set_clock_groups -asynchronous \ 9 | -group system_clock \ 10 | -group tx_clock_0 \ 11 | -group tx_clock_1 12 | -------------------------------------------------------------------------------- /QSFP-HDMI-OUT-NB7NQ621M/examples/ADM-PCIE-KU3/scripts/Config.tcl: -------------------------------------------------------------------------------- 1 | set PROJECT_NAME ADM-PCIE-KU3-Example 2 | 3 | set TOP_NAME Top 4 | 5 | set PART_NAME xcku060-ffva1156-2-e 6 | 7 | set HW_DEVICE_NAME xcku060_0 8 | set CFGMEM_PART_NAME pc28f00ag18-bpi-x16 9 | -------------------------------------------------------------------------------- /QSFP-HDMI-OUT-NB7NQ621M/examples/ADM-PCIE-KU3/scripts/CreateProject.tcl: -------------------------------------------------------------------------------- 1 | set RESOLUTION [lindex $argv 0] 2 | set REFRESH_RATE [lindex $argv 1] 3 | 4 | set PROJECT_PATH [file normalize [file dirname [info script]]/..] 5 | 6 | source $PROJECT_PATH/scripts/Config.tcl 7 | 8 | create_project -force -part $PART_NAME $PROJECT_NAME 9 | 10 | source $PROJECT_PATH/scripts/IP/GTWizard0.tcl 11 | source $PROJECT_PATH/scripts/IP/GTWizard1.tcl 12 | source $PROJECT_PATH/scripts/IP/MMCM0.tcl 13 | 14 | set_property VERILOG_DEFINE [list \ 15 | RESOLUTION="$RESOLUTION" \ 16 | REFRESH_RATE=$REFRESH_RATE \ 17 | ] [get_filesets sources_1] 18 | 19 | set_property top $TOP_NAME [current_fileset] 20 | 21 | add_files -fileset sources_1 \ 22 | [glob $PROJECT_PATH/../../../common/Verilog/*/*.v] \ 23 | [glob $PROJECT_PATH/build/generated/*.sv] \ 24 | [glob $PROJECT_PATH/sources/*.v] 25 | 26 | add_files -fileset constrs_1 \ 27 | [glob $PROJECT_PATH/../../../common/Vivado/constraints/ADM-PCIE-KU3/*.xdc] \ 28 | [glob $PROJECT_PATH/constraints/*.xdc] 29 | -------------------------------------------------------------------------------- /QSFP-HDMI-OUT-NB7NQ621M/examples/ADM-PCIE-KU3/scripts/IP/GTWizard0.tcl: -------------------------------------------------------------------------------- 1 | create_ip -module_name GTWizard0 -vendor xilinx.com -library ip -name gtwizard_ultrascale -version 1.7 2 | 3 | set GTWIZARD0_PROPERTIES {} 4 | 5 | set GTWIZARD0_PROPERTIES [concat $GTWIZARD0_PROPERTIES { 6 | CONFIG.preset GTH-HDMI 7 | 8 | CONFIG.TX_USER_DATA_WIDTH 40 9 | CONFIG.TX_INT_DATA_WIDTH 40 10 | 11 | CONFIG.RX_USER_DATA_WIDTH 40 12 | CONFIG.RX_INT_DATA_WIDTH 40 13 | 14 | CONFIG.FREERUN_FREQUENCY 10.0 15 | 16 | CONFIG.CHANNEL_ENABLE { X0Y19 X0Y18 X0Y17 X0Y16 } 17 | CONFIG.TX_MASTER_CHANNEL X0Y17 18 | CONFIG.RX_MASTER_CHANNEL X0Y17 19 | 20 | CONFIG.TX_REFCLK_SOURCE { X0Y19 clk0 X0Y18 clk0 X0Y17 clk0 X0Y16 clk0 } 21 | CONFIG.RX_REFCLK_SOURCE { X0Y19 clk0 X0Y18 clk0 X0Y17 clk0 X0Y16 clk0 } 22 | 23 | CONFIG.LOCATE_TX_USER_CLOCKING CORE 24 | CONFIG.LOCATE_RX_USER_CLOCKING CORE 25 | 26 | CONFIG.ENABLE_OPTIONAL_PORTS { 27 | gtrefclk00_in 28 | gtrefclk01_in 29 | 30 | qpll0outclk_out 31 | qpll0outrefclk_out 32 | qpll1outclk_out 33 | qpll1outrefclk_out 34 | } 35 | }] 36 | 37 | switch "$RESOLUTION@$REFRESH_RATE" { 38 | "1920x1080@30" { 39 | set GTWIZARD0_PROPERTIES [concat $GTWIZARD0_PROPERTIES { 40 | CONFIG.TX_LINE_RATE 0.7425 41 | CONFIG.TX_PLL_TYPE QPLL0 42 | CONFIG.TX_REFCLK_FREQUENCY 148.5 43 | 44 | CONFIG.RX_LINE_RATE 0.7425 45 | CONFIG.RX_PLL_TYPE QPLL0 46 | CONFIG.RX_REFCLK_FREQUENCY 148.5 47 | }] 48 | } 49 | "2560x1440@30" { 50 | set GTWIZARD0_PROPERTIES [concat $GTWIZARD0_PROPERTIES { 51 | CONFIG.TX_LINE_RATE 1.21584 52 | CONFIG.TX_PLL_TYPE QPLL1 53 | CONFIG.TX_REFCLK_FREQUENCY 121.584 54 | 55 | CONFIG.RX_LINE_RATE 1.21584 56 | CONFIG.RX_PLL_TYPE QPLL1 57 | CONFIG.RX_REFCLK_FREQUENCY 121.584 58 | }] 59 | } 60 | "1920x1080@60" { 61 | set GTWIZARD0_PROPERTIES [concat $GTWIZARD0_PROPERTIES { 62 | CONFIG.TX_LINE_RATE 1.485 63 | CONFIG.TX_PLL_TYPE QPLL0 64 | CONFIG.TX_REFCLK_FREQUENCY 148.5 65 | 66 | CONFIG.RX_LINE_RATE 1.485 67 | CONFIG.RX_PLL_TYPE QPLL0 68 | CONFIG.RX_REFCLK_FREQUENCY 148.5 69 | }] 70 | } 71 | "2560x1440@60" { 72 | set GTWIZARD0_PROPERTIES [concat $GTWIZARD0_PROPERTIES { 73 | CONFIG.TX_LINE_RATE 2.43168 74 | CONFIG.TX_PLL_TYPE QPLL1 75 | CONFIG.TX_REFCLK_FREQUENCY 121.584 76 | 77 | CONFIG.RX_LINE_RATE 2.43168 78 | CONFIG.RX_PLL_TYPE QPLL1 79 | CONFIG.RX_REFCLK_FREQUENCY 121.584 80 | }] 81 | } 82 | "1920x1080@120" - 83 | "3840x2160@30" { 84 | set GTWIZARD0_PROPERTIES [concat $GTWIZARD0_PROPERTIES { 85 | CONFIG.TX_LINE_RATE 2.97 86 | CONFIG.TX_PLL_TYPE QPLL0 87 | CONFIG.TX_REFCLK_FREQUENCY 148.5 88 | 89 | CONFIG.RX_LINE_RATE 2.97 90 | CONFIG.RX_PLL_TYPE QPLL0 91 | CONFIG.RX_REFCLK_FREQUENCY 148.5 92 | }] 93 | } 94 | "1920x1080@144" { 95 | set GTWIZARD0_PROPERTIES [concat $GTWIZARD0_PROPERTIES { 96 | CONFIG.TX_LINE_RATE 3.564 97 | CONFIG.TX_PLL_TYPE QPLL0 98 | CONFIG.TX_REFCLK_FREQUENCY 148.5 99 | 100 | CONFIG.RX_LINE_RATE 3.564 101 | CONFIG.RX_PLL_TYPE QPLL0 102 | CONFIG.RX_REFCLK_FREQUENCY 148.5 103 | }] 104 | } 105 | "2560x1440@120" { 106 | set GTWIZARD0_PROPERTIES [concat $GTWIZARD0_PROPERTIES { 107 | CONFIG.TX_LINE_RATE 4.86336 108 | CONFIG.TX_PLL_TYPE QPLL1 109 | CONFIG.TX_REFCLK_FREQUENCY 121.584 110 | 111 | CONFIG.RX_LINE_RATE 4.86336 112 | CONFIG.RX_PLL_TYPE QPLL1 113 | CONFIG.RX_REFCLK_FREQUENCY 121.584 114 | }] 115 | } 116 | "2560x1440@144" { 117 | set GTWIZARD0_PROPERTIES [concat $GTWIZARD0_PROPERTIES { 118 | CONFIG.TX_LINE_RATE 5.836032 119 | CONFIG.TX_PLL_TYPE QPLL0 120 | CONFIG.TX_REFCLK_FREQUENCY 121.584 121 | 122 | CONFIG.RX_LINE_RATE 5.836032 123 | CONFIG.RX_PLL_TYPE QPLL0 124 | CONFIG.RX_REFCLK_FREQUENCY 121.584 125 | }] 126 | } 127 | "1920x1080@240" - 128 | "3840x2160@60" { 129 | set GTWIZARD0_PROPERTIES [concat $GTWIZARD0_PROPERTIES { 130 | CONFIG.TX_LINE_RATE 5.94 131 | CONFIG.TX_PLL_TYPE QPLL0 132 | CONFIG.TX_REFCLK_FREQUENCY 148.5 133 | 134 | CONFIG.RX_LINE_RATE 5.94 135 | CONFIG.RX_PLL_TYPE QPLL0 136 | CONFIG.RX_REFCLK_FREQUENCY 148.5 137 | }] 138 | } 139 | default { 140 | error "Invalid video mode $RESOLUTION@$REFRESH_RATE" 141 | } 142 | } 143 | 144 | set_property -dict $GTWIZARD0_PROPERTIES [get_ips GTWizard0] 145 | -------------------------------------------------------------------------------- /QSFP-HDMI-OUT-NB7NQ621M/examples/ADM-PCIE-KU3/scripts/IP/GTWizard1.tcl: -------------------------------------------------------------------------------- 1 | create_ip -module_name GTWizard1 -vendor xilinx.com -library ip -name gtwizard_ultrascale -version 1.7 2 | 3 | set GTWIZARD1_PROPERTIES {} 4 | 5 | set GTWIZARD1_PROPERTIES [concat $GTWIZARD1_PROPERTIES { 6 | CONFIG.preset GTH-HDMI 7 | 8 | CONFIG.TX_USER_DATA_WIDTH 40 9 | CONFIG.TX_INT_DATA_WIDTH 40 10 | 11 | CONFIG.RX_USER_DATA_WIDTH 40 12 | CONFIG.RX_INT_DATA_WIDTH 40 13 | 14 | CONFIG.FREERUN_FREQUENCY 10.0 15 | 16 | CONFIG.CHANNEL_ENABLE { X1Y19 X1Y18 X1Y17 X1Y16 } 17 | CONFIG.TX_MASTER_CHANNEL X1Y17 18 | CONFIG.RX_MASTER_CHANNEL X1Y17 19 | 20 | CONFIG.TX_REFCLK_SOURCE { X1Y19 clk0 X1Y18 clk0 X1Y17 clk0 X1Y16 clk0 } 21 | CONFIG.RX_REFCLK_SOURCE { X1Y19 clk0 X1Y18 clk0 X1Y17 clk0 X1Y16 clk0 } 22 | 23 | CONFIG.LOCATE_TX_USER_CLOCKING CORE 24 | CONFIG.LOCATE_RX_USER_CLOCKING CORE 25 | 26 | CONFIG.ENABLE_OPTIONAL_PORTS { 27 | gtrefclk00_in 28 | gtrefclk01_in 29 | 30 | qpll0outclk_out 31 | qpll0outrefclk_out 32 | qpll1outclk_out 33 | qpll1outrefclk_out 34 | } 35 | }] 36 | 37 | switch "$RESOLUTION@$REFRESH_RATE" { 38 | "1920x1080@30" { 39 | set GTWIZARD1_PROPERTIES [concat $GTWIZARD1_PROPERTIES { 40 | CONFIG.TX_LINE_RATE 0.7425 41 | CONFIG.TX_PLL_TYPE QPLL0 42 | CONFIG.TX_REFCLK_FREQUENCY 148.5 43 | 44 | CONFIG.RX_LINE_RATE 0.7425 45 | CONFIG.RX_PLL_TYPE QPLL0 46 | CONFIG.RX_REFCLK_FREQUENCY 148.5 47 | }] 48 | } 49 | "2560x1440@30" { 50 | set GTWIZARD1_PROPERTIES [concat $GTWIZARD1_PROPERTIES { 51 | CONFIG.TX_LINE_RATE 1.21584 52 | CONFIG.TX_PLL_TYPE QPLL1 53 | CONFIG.TX_REFCLK_FREQUENCY 121.584 54 | 55 | CONFIG.RX_LINE_RATE 1.21584 56 | CONFIG.RX_PLL_TYPE QPLL1 57 | CONFIG.RX_REFCLK_FREQUENCY 121.584 58 | }] 59 | } 60 | "1920x1080@60" { 61 | set GTWIZARD1_PROPERTIES [concat $GTWIZARD1_PROPERTIES { 62 | CONFIG.TX_LINE_RATE 1.485 63 | CONFIG.TX_PLL_TYPE QPLL0 64 | CONFIG.TX_REFCLK_FREQUENCY 148.5 65 | 66 | CONFIG.RX_LINE_RATE 1.485 67 | CONFIG.RX_PLL_TYPE QPLL0 68 | CONFIG.RX_REFCLK_FREQUENCY 148.5 69 | }] 70 | } 71 | "2560x1440@60" { 72 | set GTWIZARD1_PROPERTIES [concat $GTWIZARD1_PROPERTIES { 73 | CONFIG.TX_LINE_RATE 2.43168 74 | CONFIG.TX_PLL_TYPE QPLL1 75 | CONFIG.TX_REFCLK_FREQUENCY 121.584 76 | 77 | CONFIG.RX_LINE_RATE 2.43168 78 | CONFIG.RX_PLL_TYPE QPLL1 79 | CONFIG.RX_REFCLK_FREQUENCY 121.584 80 | }] 81 | } 82 | "1920x1080@120" - 83 | "3840x2160@30" { 84 | set GTWIZARD1_PROPERTIES [concat $GTWIZARD1_PROPERTIES { 85 | CONFIG.TX_LINE_RATE 2.97 86 | CONFIG.TX_PLL_TYPE QPLL0 87 | CONFIG.TX_REFCLK_FREQUENCY 148.5 88 | 89 | CONFIG.RX_LINE_RATE 2.97 90 | CONFIG.RX_PLL_TYPE QPLL0 91 | CONFIG.RX_REFCLK_FREQUENCY 148.5 92 | }] 93 | } 94 | "1920x1080@144" { 95 | set GTWIZARD1_PROPERTIES [concat $GTWIZARD1_PROPERTIES { 96 | CONFIG.TX_LINE_RATE 3.564 97 | CONFIG.TX_PLL_TYPE QPLL0 98 | CONFIG.TX_REFCLK_FREQUENCY 148.5 99 | 100 | CONFIG.RX_LINE_RATE 3.564 101 | CONFIG.RX_PLL_TYPE QPLL0 102 | CONFIG.RX_REFCLK_FREQUENCY 148.5 103 | }] 104 | } 105 | "2560x1440@120" { 106 | set GTWIZARD1_PROPERTIES [concat $GTWIZARD1_PROPERTIES { 107 | CONFIG.TX_LINE_RATE 4.86336 108 | CONFIG.TX_PLL_TYPE QPLL1 109 | CONFIG.TX_REFCLK_FREQUENCY 121.584 110 | 111 | CONFIG.RX_LINE_RATE 4.86336 112 | CONFIG.RX_PLL_TYPE QPLL1 113 | CONFIG.RX_REFCLK_FREQUENCY 121.584 114 | }] 115 | } 116 | "2560x1440@144" { 117 | set GTWIZARD1_PROPERTIES [concat $GTWIZARD1_PROPERTIES { 118 | CONFIG.TX_LINE_RATE 5.836032 119 | CONFIG.TX_PLL_TYPE QPLL0 120 | CONFIG.TX_REFCLK_FREQUENCY 121.584 121 | 122 | CONFIG.RX_LINE_RATE 5.836032 123 | CONFIG.RX_PLL_TYPE QPLL0 124 | CONFIG.RX_REFCLK_FREQUENCY 121.584 125 | }] 126 | } 127 | "1920x1080@240" - 128 | "3840x2160@60" { 129 | set GTWIZARD1_PROPERTIES [concat $GTWIZARD1_PROPERTIES { 130 | CONFIG.TX_LINE_RATE 5.94 131 | CONFIG.TX_PLL_TYPE QPLL0 132 | CONFIG.TX_REFCLK_FREQUENCY 148.5 133 | 134 | CONFIG.RX_LINE_RATE 5.94 135 | CONFIG.RX_PLL_TYPE QPLL0 136 | CONFIG.RX_REFCLK_FREQUENCY 148.5 137 | }] 138 | } 139 | default { 140 | error "Invalid video mode $RESOLUTION@$REFRESH_RATE" 141 | } 142 | } 143 | 144 | set_property -dict $GTWIZARD1_PROPERTIES [get_ips GTWizard1] 145 | -------------------------------------------------------------------------------- /QSFP-HDMI-OUT-NB7NQ621M/examples/ADM-PCIE-KU3/scripts/IP/MMCM0.tcl: -------------------------------------------------------------------------------- 1 | create_ip -module_name MMCM0 -vendor xilinx.com -library ip -name clk_wiz -version 6.0 2 | 3 | set_property -dict { 4 | CONFIG.PRIMITIVE MMCM 5 | CONFIG.PRIMARY_PORT clk_in1 6 | CONFIG.PRIM_IN_FREQ 200.000 7 | CONFIG.PRIM_SOURCE Differential_clock_capable_pin 8 | 9 | CONFIG.NUM_OUT_CLKS 2 10 | 11 | CONFIG.CLKOUT1_USED true 12 | CONFIG.CLK_OUT1_PORT clk_out1 13 | CONFIG.CLKOUT1_REQUESTED_OUT_FREQ 200.000 14 | CONFIG.CLKOUT1_DRIVES BUFG 15 | 16 | CONFIG.CLKOUT2_USED true 17 | CONFIG.CLK_OUT2_PORT clk_out2 18 | CONFIG.CLKOUT2_REQUESTED_OUT_FREQ 10.000 19 | CONFIG.CLKOUT2_DRIVES BUFG 20 | } [get_ips MMCM0] 21 | -------------------------------------------------------------------------------- /QSFP-HDMI-OUT-NB7NQ621M/examples/ADM-PCIE-KU3/sources/GTWizardWrapper.v: -------------------------------------------------------------------------------- 1 | module GTWizardWrapper0( 2 | input clock, 3 | input reset, 4 | 5 | input refclk_p, 6 | input refclk_n, 7 | input [3:0] rxp, 8 | input [3:0] rxn, 9 | output [3:0] txp, 10 | output [3:0] txn, 11 | 12 | output tx_clock, 13 | output tx_reset, 14 | input [159:0] tx_data 15 | ); 16 | 17 | wire refclk; 18 | 19 | IBUFDS_GTE3 ibufds_gte3 ( 20 | .O (refclk), 21 | .ODIV2 (), 22 | .CEB (0), 23 | .I (refclk_p), 24 | .IB (refclk_n) 25 | ); 26 | 27 | wire userclk_tx_reset; 28 | wire userclk_tx_usrclk2; 29 | wire userclk_tx_active; 30 | wire buffbypass_tx_reset; 31 | wire buffbypass_tx_done; 32 | wire buffbypass_tx_error; 33 | wire reset_tx_done; 34 | wire [3:0] txpmaresetdone; 35 | wire [3:0] txprgdivresetdone; 36 | 37 | GTWizard0 gt_wizard( 38 | .gtwiz_userclk_tx_reset_in (userclk_tx_reset), 39 | .gtwiz_userclk_tx_srcclk_out (), 40 | .gtwiz_userclk_tx_usrclk_out (), 41 | .gtwiz_userclk_tx_usrclk2_out (userclk_tx_usrclk2), 42 | .gtwiz_userclk_tx_active_out (userclk_tx_active), 43 | .gtwiz_userclk_rx_reset_in (1), 44 | .gtwiz_userclk_rx_srcclk_out (), 45 | .gtwiz_userclk_rx_usrclk_out (), 46 | .gtwiz_userclk_rx_usrclk2_out (), 47 | .gtwiz_userclk_rx_active_out (), 48 | .gtwiz_buffbypass_tx_reset_in (buffbypass_tx_reset), 49 | .gtwiz_buffbypass_tx_start_user_in (0), 50 | .gtwiz_buffbypass_tx_done_out (buffbypass_tx_done), 51 | .gtwiz_buffbypass_tx_error_out (buffbypass_tx_error), 52 | .gtwiz_reset_clk_freerun_in (clock), 53 | .gtwiz_reset_all_in (reset), 54 | .gtwiz_reset_tx_pll_and_datapath_in (0), 55 | .gtwiz_reset_tx_datapath_in (0), 56 | .gtwiz_reset_rx_pll_and_datapath_in (0), 57 | .gtwiz_reset_rx_datapath_in (0), 58 | .gtwiz_reset_rx_cdr_stable_out (), 59 | .gtwiz_reset_tx_done_out (reset_tx_done), 60 | .gtwiz_reset_rx_done_out (), 61 | .gtwiz_userdata_tx_in (tx_data), 62 | .gtwiz_userdata_rx_out (), 63 | .gtrefclk00_in (refclk), 64 | .gtrefclk01_in (refclk), 65 | .qpll0outclk_out (), 66 | .qpll0outrefclk_out (), 67 | .qpll1outclk_out (), 68 | .qpll1outrefclk_out (), 69 | .gthrxn_in (rxn), 70 | .gthrxp_in (rxp), 71 | .gtpowergood_out (), 72 | .gthtxn_out (txn), 73 | .gthtxp_out (txp), 74 | .rxpmaresetdone_out (), 75 | .txpmaresetdone_out (txpmaresetdone), 76 | .txprgdivresetdone_out (txprgdivresetdone) 77 | ); 78 | 79 | assign userclk_tx_reset = ~(&txpmaresetdone & &txprgdivresetdone); 80 | 81 | reg [2:0] buffbypass_tx_reset_reg; 82 | always @(posedge userclk_tx_usrclk2) begin 83 | if (~userclk_tx_active) begin 84 | buffbypass_tx_reset_reg <= 5; 85 | end else begin 86 | if (buffbypass_tx_reset_reg != 0) 87 | buffbypass_tx_reset_reg <= buffbypass_tx_reset_reg - 1; 88 | end 89 | end 90 | assign buffbypass_tx_reset = buffbypass_tx_reset_reg != 0; 91 | 92 | assign tx_clock = userclk_tx_usrclk2; 93 | assign tx_reset = reset | ~reset_tx_done | ~buffbypass_tx_done; 94 | 95 | endmodule 96 | 97 | 98 | module GTWizardWrapper1( 99 | input clock, 100 | input reset, 101 | 102 | input refclk_p, 103 | input refclk_n, 104 | input [3:0] rxp, 105 | input [3:0] rxn, 106 | output [3:0] txp, 107 | output [3:0] txn, 108 | 109 | output tx_clock, 110 | output tx_reset, 111 | input [159:0] tx_data 112 | ); 113 | 114 | wire refclk; 115 | 116 | IBUFDS_GTE3 ibufds_gte3 ( 117 | .O (refclk), 118 | .ODIV2 (), 119 | .CEB (0), 120 | .I (refclk_p), 121 | .IB (refclk_n) 122 | ); 123 | 124 | wire userclk_tx_reset; 125 | wire userclk_tx_usrclk2; 126 | wire userclk_tx_active; 127 | wire buffbypass_tx_reset; 128 | wire buffbypass_tx_done; 129 | wire buffbypass_tx_error; 130 | wire reset_tx_done; 131 | wire [3:0] txpmaresetdone; 132 | wire [3:0] txprgdivresetdone; 133 | 134 | GTWizard1 gt_wizard( 135 | .gtwiz_userclk_tx_reset_in (userclk_tx_reset), 136 | .gtwiz_userclk_tx_srcclk_out (), 137 | .gtwiz_userclk_tx_usrclk_out (), 138 | .gtwiz_userclk_tx_usrclk2_out (userclk_tx_usrclk2), 139 | .gtwiz_userclk_tx_active_out (userclk_tx_active), 140 | .gtwiz_userclk_rx_reset_in (1), 141 | .gtwiz_userclk_rx_srcclk_out (), 142 | .gtwiz_userclk_rx_usrclk_out (), 143 | .gtwiz_userclk_rx_usrclk2_out (), 144 | .gtwiz_userclk_rx_active_out (), 145 | .gtwiz_buffbypass_tx_reset_in (buffbypass_tx_reset), 146 | .gtwiz_buffbypass_tx_start_user_in (0), 147 | .gtwiz_buffbypass_tx_done_out (buffbypass_tx_done), 148 | .gtwiz_buffbypass_tx_error_out (buffbypass_tx_error), 149 | .gtwiz_reset_clk_freerun_in (clock), 150 | .gtwiz_reset_all_in (reset), 151 | .gtwiz_reset_tx_pll_and_datapath_in (0), 152 | .gtwiz_reset_tx_datapath_in (0), 153 | .gtwiz_reset_rx_pll_and_datapath_in (0), 154 | .gtwiz_reset_rx_datapath_in (0), 155 | .gtwiz_reset_rx_cdr_stable_out (), 156 | .gtwiz_reset_tx_done_out (reset_tx_done), 157 | .gtwiz_reset_rx_done_out (), 158 | .gtwiz_userdata_tx_in (tx_data), 159 | .gtwiz_userdata_rx_out (), 160 | .gtrefclk00_in (refclk), 161 | .gtrefclk01_in (refclk), 162 | .qpll0outclk_out (), 163 | .qpll0outrefclk_out (), 164 | .qpll1outclk_out (), 165 | .qpll1outrefclk_out (), 166 | .gthrxn_in (rxn), 167 | .gthrxp_in (rxp), 168 | .gtpowergood_out (), 169 | .gthtxn_out (txn), 170 | .gthtxp_out (txp), 171 | .rxpmaresetdone_out (), 172 | .txpmaresetdone_out (txpmaresetdone), 173 | .txprgdivresetdone_out (txprgdivresetdone) 174 | ); 175 | 176 | assign userclk_tx_reset = ~(&txpmaresetdone & &txprgdivresetdone); 177 | 178 | reg [2:0] buffbypass_tx_reset_reg; 179 | always @(posedge userclk_tx_usrclk2) begin 180 | if (~userclk_tx_active) begin 181 | buffbypass_tx_reset_reg <= 5; 182 | end else begin 183 | if (buffbypass_tx_reset_reg != 0) 184 | buffbypass_tx_reset_reg <= buffbypass_tx_reset_reg - 1; 185 | end 186 | end 187 | assign buffbypass_tx_reset = buffbypass_tx_reset_reg != 0; 188 | 189 | assign tx_clock = userclk_tx_usrclk2; 190 | assign tx_reset = reset | ~reset_tx_done | ~buffbypass_tx_done; 191 | 192 | endmodule 193 | -------------------------------------------------------------------------------- /QSFP-HDMI-OUT-NB7NQ621M/examples/ADM-PCIE-KU3/sources/Top.v: -------------------------------------------------------------------------------- 1 | `ifndef RESOLUTION 2 | `define RESOLUTION "1920x1080" 3 | `endif 4 | `ifndef REFRESH_RATE 5 | `define REFRESH_RATE 60 6 | `endif 7 | 8 | 9 | module Top( 10 | input clock_200_p, 11 | input clock_200_n, 12 | 13 | output [2:0] led, 14 | 15 | inout si5338_scl, 16 | inout si5338_sda, 17 | 18 | input qsfp0_refclk_p, 19 | input qsfp0_refclk_n, 20 | input [3:0] qsfp0_rxp, 21 | input [3:0] qsfp0_rxn, 22 | output [3:0] qsfp0_txp, 23 | output [3:0] qsfp0_txn, 24 | input qsfp0_modprsl, 25 | output qsfp0_resetl, 26 | inout qsfp0_scl, 27 | inout qsfp0_sda, 28 | 29 | input qsfp1_refclk_p, 30 | input qsfp1_refclk_n, 31 | input [3:0] qsfp1_rxp, 32 | input [3:0] qsfp1_rxn, 33 | output [3:0] qsfp1_txp, 34 | output [3:0] qsfp1_txn, 35 | input qsfp1_modprsl, 36 | output qsfp1_resetl, 37 | inout qsfp1_scl, 38 | inout qsfp1_sda 39 | ); 40 | 41 | localparam CLOCK_FREQUENCY = 200_000_000; 42 | 43 | localparam REFERENCE_CLOCK_FREQUENCY = 44 | `RESOLUTION == "1920x1080" ? 148_500_000 : 45 | `RESOLUTION == "2560x1440" ? 121_584_000 : 46 | `RESOLUTION == "3840x2160" ? 148_500_000 : 47 | 0; 48 | 49 | 50 | wire system_reset_input = 0; 51 | 52 | wire system_clock; 53 | wire gt_config_clock; 54 | wire mmcm0_locked; 55 | 56 | MMCM0 mmcm0( 57 | .clk_in1_p (clock_200_p), 58 | .clk_in1_n (clock_200_n), 59 | .reset (system_reset_input), 60 | .clk_out1 (system_clock), 61 | .clk_out2 (gt_config_clock), 62 | .locked (mmcm0_locked) 63 | ); 64 | 65 | reg [2:0] system_reset_reg; 66 | 67 | always @(posedge system_clock) begin 68 | if (~mmcm0_locked) begin 69 | system_reset_reg <= 3'b111; 70 | end else begin 71 | system_reset_reg <= system_reset_reg >> 1; 72 | end 73 | end 74 | 75 | wire system_reset = system_reset_reg[0]; 76 | 77 | 78 | wire si5338_scl_input; 79 | wire si5338_scl_output; 80 | wire si5338_sda_input; 81 | wire si5338_sda_output; 82 | 83 | IOBUF si5338_scl_iobuf( 84 | .O (si5338_scl_input), 85 | .I (si5338_scl_output), 86 | .IO (si5338_scl), 87 | .T (si5338_scl_output) 88 | ); 89 | IOBUF si5338_sda_iobuf( 90 | .O (si5338_sda_input), 91 | .I (si5338_sda_output), 92 | .IO (si5338_sda), 93 | .T (si5338_sda_output) 94 | ); 95 | 96 | wire si5338_ready; 97 | 98 | Si5338 #( 99 | .CLOCK_FREQUENCY (CLOCK_FREQUENCY), 100 | .REFERENCE_CLOCK_FREQUENCY (REFERENCE_CLOCK_FREQUENCY) 101 | ) si5338( 102 | .clock (system_clock), 103 | .reset (system_reset), 104 | 105 | .scl_input (si5338_scl_input), 106 | .scl_output (si5338_scl_output), 107 | .sda_input (si5338_sda_input), 108 | .sda_output (si5338_sda_output), 109 | 110 | .ready (si5338_ready) 111 | ); 112 | 113 | 114 | wire [1:0] tx_clock; 115 | wire [1:0] tx_reset; 116 | wire [159:0] tx_data[1:0]; 117 | 118 | GTWizardWrapper0 gt_wizard_wrapper_0( 119 | .clock (gt_config_clock), 120 | .reset (~si5338_ready), 121 | 122 | .refclk_p (qsfp0_refclk_p), 123 | .refclk_n (qsfp0_refclk_n), 124 | .rxp (qsfp0_rxp), 125 | .rxn (qsfp0_rxn), 126 | .txp (qsfp0_txp), 127 | .txn (qsfp0_txn), 128 | 129 | .tx_clock (tx_clock[0]), 130 | .tx_reset (tx_reset[0]), 131 | .tx_data (tx_data[0]) 132 | ); 133 | 134 | GTWizardWrapper1 gt_wizard_wrapper_1( 135 | .clock (gt_config_clock), 136 | .reset (~si5338_ready), 137 | 138 | .refclk_p (qsfp1_refclk_p), 139 | .refclk_n (qsfp1_refclk_n), 140 | .rxp (qsfp1_rxp), 141 | .rxn (qsfp1_rxn), 142 | .txp (qsfp1_txp), 143 | .txn (qsfp1_txn), 144 | 145 | .tx_clock (tx_clock[1]), 146 | .tx_reset (tx_reset[1]), 147 | .tx_data (tx_data[1]) 148 | ); 149 | 150 | 151 | wire [1:0] qsfp_scl_input; 152 | wire [1:0] qsfp_scl_output; 153 | wire [1:0] qsfp_sda_input; 154 | wire [1:0] qsfp_sda_output; 155 | 156 | IOBUF qsfp0_scl_iobuf( 157 | .O (qsfp_scl_input[0]), 158 | .I (qsfp_scl_output[0]), 159 | .IO (qsfp0_scl), 160 | .T (qsfp_scl_output[0]) 161 | ); 162 | IOBUF qsfp0_sda_iobuf( 163 | .O (qsfp_sda_input[0]), 164 | .I (qsfp_sda_output[0]), 165 | .IO (qsfp0_sda), 166 | .T (qsfp_sda_output[0]) 167 | ); 168 | 169 | IOBUF qsfp1_scl_iobuf( 170 | .O (qsfp_scl_input[1]), 171 | .I (qsfp_scl_output[1]), 172 | .IO (qsfp1_scl), 173 | .T (qsfp_scl_output[1]) 174 | ); 175 | IOBUF qsfp1_sda_iobuf( 176 | .O (qsfp_sda_input[1]), 177 | .I (qsfp_sda_output[1]), 178 | .IO (qsfp1_sda), 179 | .T (qsfp_sda_output[1]) 180 | ); 181 | 182 | wire [1:0] hpd = { ~qsfp1_modprsl, ~qsfp0_modprsl }; 183 | wire [1:0] run; 184 | 185 | genvar i; 186 | 187 | generate 188 | for (i = 0; i < 2; i = i + 1) begin: hdmi_out_examples 189 | HDMIOUTExample #( 190 | .CLOCK_FREQUENCY (CLOCK_FREQUENCY), 191 | .RESOLUTION (`RESOLUTION), 192 | .REFRESH_RATE (`REFRESH_RATE) 193 | ) hdmi_out_example( 194 | .system_clock (system_clock), 195 | .system_reset (system_reset), 196 | .tx_clock (tx_clock[i]), 197 | .tx_reset (tx_reset[i]), 198 | .tx_data (tx_data[i]), 199 | .hpd (hpd[i]), 200 | .scl_input (qsfp_scl_input[i]), 201 | .scl_output (qsfp_scl_output[i]), 202 | .sda_input (qsfp_sda_input[i]), 203 | .sda_output (qsfp_sda_output[i]), 204 | .i2c_request (), 205 | .i2c_grant (1'b1), 206 | .run (run[i]) 207 | ); 208 | end 209 | endgenerate 210 | 211 | reg led_reg; 212 | reg [31:0] led_count; 213 | 214 | always @(posedge system_clock) begin 215 | if (system_reset) begin 216 | led_reg <= 0; 217 | led_count <= 0; 218 | end else begin 219 | if (led_count != CLOCK_FREQUENCY / 2 - 1) begin 220 | led_count <= led_count + 1; 221 | end else begin 222 | led_count <= 0; 223 | led_reg <= ~led_reg; 224 | end 225 | end 226 | end 227 | 228 | assign led = { 229 | ~system_reset, 230 | ~(~system_reset & ((led_reg & hpd[1]) | run[1])), 231 | ~(~system_reset & ((led_reg & hpd[0]) | run[0])) 232 | }; 233 | 234 | assign qsfp0_resetl = ~system_reset; 235 | 236 | assign qsfp1_resetl = ~system_reset; 237 | 238 | endmodule 239 | -------------------------------------------------------------------------------- /QSFP-HDMI-OUT-NB7NQ621M/examples/Alibaba-VU13P/build.py: -------------------------------------------------------------------------------- 1 | import argparse 2 | import os 3 | import shutil 4 | import subprocess 5 | 6 | VIVADO = os.getenv('VIVADO', shutil.which('vivado')) 7 | MILL = os.getenv('MILL', shutil.which('mill')) 8 | 9 | RESOLUTION_LIST = [ 10 | '1920x1080', 11 | '2560x1440', 12 | '3840x2160', 13 | ] 14 | REFRESH_RATE_LIST = [ 15 | '30', 16 | '60', 17 | '120', 18 | '144', 19 | '240', 20 | ] 21 | 22 | PROJECT_PATH = os.path.dirname(os.path.realpath(__file__)) 23 | COMMON_PATH = os.path.join(PROJECT_PATH, '..', '..', '..', 'common') 24 | COMMON_CHISEL_PATH = os.path.join(COMMON_PATH, 'Chisel') 25 | COMMON_SCRIPTS_PATH = os.path.join(COMMON_PATH, 'Vivado', 'scripts') 26 | SCRIPTS_PATH = os.path.join(PROJECT_PATH, 'scripts') 27 | CONFIG_PATH = os.path.join(SCRIPTS_PATH, 'Config.tcl') 28 | BUILD_PATH = os.path.join(PROJECT_PATH, 'build') 29 | GENERATED_PATH = os.path.join(BUILD_PATH, 'generated') 30 | BITSTREAM_PATH = os.path.join(BUILD_PATH, 'bitstream') 31 | 32 | def runCommand(command, **kwargs): 33 | print(command) 34 | subprocess.run(command, check = True, **kwargs) 35 | 36 | def runVivadoScript(script, *args): 37 | runCommand([VIVADO, '-nojournal', '-nolog', '-mode', 'batch', '-source', script, '-tclargs', *args], cwd = BUILD_PATH) 38 | 39 | if __name__ == "__main__": 40 | parser = argparse.ArgumentParser() 41 | parser.add_argument('command', choices = ['build', 'program', 'flash']) 42 | parser.add_argument('--resolution', choices = RESOLUTION_LIST, default = '1920x1080') 43 | parser.add_argument('--refresh-rate', choices = REFRESH_RATE_LIST, default = '60') 44 | parser.add_argument('-j', '--jobs', default = '8') 45 | args = parser.parse_args() 46 | 47 | RESOLUTION = args.resolution 48 | REFRESH_RATE = args.refresh_rate 49 | JOBS = args.jobs 50 | 51 | if args.command == 'build': 52 | os.makedirs(GENERATED_PATH, exist_ok = True) 53 | runCommand([MILL, 'hdmioutexample.run', '-o', os.path.join(GENERATED_PATH, 'HDMIOutExample.sv')], cwd = COMMON_CHISEL_PATH) 54 | 55 | runVivadoScript(os.path.join(SCRIPTS_PATH, 'CreateProject.tcl'), RESOLUTION, REFRESH_RATE) 56 | runVivadoScript(os.path.join(COMMON_SCRIPTS_PATH, 'Synthesis.tcl'), CONFIG_PATH, JOBS) 57 | runVivadoScript(os.path.join(COMMON_SCRIPTS_PATH, 'Implementation.tcl'), CONFIG_PATH, JOBS) 58 | runVivadoScript(os.path.join(COMMON_SCRIPTS_PATH, 'GenerateBitstream.tcl'), CONFIG_PATH, BITSTREAM_PATH) 59 | elif args.command == 'program': 60 | runVivadoScript(os.path.join(COMMON_SCRIPTS_PATH, 'Program.tcl'), CONFIG_PATH, BITSTREAM_PATH) 61 | elif args.command == 'flash': 62 | runVivadoScript(os.path.join(COMMON_SCRIPTS_PATH, 'Flash.tcl'), CONFIG_PATH, BITSTREAM_PATH) 63 | else: 64 | assert False 65 | -------------------------------------------------------------------------------- /QSFP-HDMI-OUT-NB7NQ621M/examples/Alibaba-VU13P/constraints/Timing.xdc: -------------------------------------------------------------------------------- 1 | # System clock frequency = 200MHz 2 | create_clock -name system_clock -period 5 -quiet [get_nets system_clock] 3 | 4 | # Maximum TX clock frequency = 6GHz / 40 bits per clock = 150MHz 5 | create_clock -name tx_clock_0 -period 6.666 -quiet [get_nets tx_clock_0] 6 | create_clock -name tx_clock_1 -period 6.666 -quiet [get_nets tx_clock_1] 7 | 8 | set_clock_groups -asynchronous \ 9 | -group system_clock \ 10 | -group tx_clock_0 \ 11 | -group tx_clock_1 12 | -------------------------------------------------------------------------------- /QSFP-HDMI-OUT-NB7NQ621M/examples/Alibaba-VU13P/scripts/Config.tcl: -------------------------------------------------------------------------------- 1 | set PROJECT_NAME Alibaba-VU13P-Example 2 | 3 | set TOP_NAME Top 4 | 5 | set PART_NAME xcvu13p-fhgb2104-2L-e 6 | 7 | set HW_DEVICE_NAME xcvu13p_0 8 | set CFGMEM_PART_NAME mt25qu02g-spi-x1_x2_x4 9 | -------------------------------------------------------------------------------- /QSFP-HDMI-OUT-NB7NQ621M/examples/Alibaba-VU13P/scripts/CreateProject.tcl: -------------------------------------------------------------------------------- 1 | set RESOLUTION [lindex $argv 0] 2 | set REFRESH_RATE [lindex $argv 1] 3 | 4 | set PROJECT_PATH [file normalize [file dirname [info script]]/..] 5 | 6 | source $PROJECT_PATH/scripts/Config.tcl 7 | 8 | create_project -force -part $PART_NAME $PROJECT_NAME 9 | 10 | source $PROJECT_PATH/scripts/IP/GTWizard0.tcl 11 | source $PROJECT_PATH/scripts/IP/GTWizard1.tcl 12 | source $PROJECT_PATH/scripts/IP/PLL0.tcl 13 | 14 | set_property VERILOG_DEFINE [list \ 15 | RESOLUTION="$RESOLUTION" \ 16 | REFRESH_RATE=$REFRESH_RATE \ 17 | ] [get_filesets sources_1] 18 | 19 | set_property top $TOP_NAME [current_fileset] 20 | 21 | add_files -fileset sources_1 \ 22 | [glob $PROJECT_PATH/../../../common/Verilog/*/*.v] \ 23 | [glob $PROJECT_PATH/build/generated/*.sv] \ 24 | [glob $PROJECT_PATH/sources/*.v] 25 | 26 | add_files -fileset constrs_1 \ 27 | [glob $PROJECT_PATH/../../../common/Vivado/constraints/Alibaba-VU13P/*.xdc] \ 28 | [glob $PROJECT_PATH/constraints/*.xdc] 29 | -------------------------------------------------------------------------------- /QSFP-HDMI-OUT-NB7NQ621M/examples/Alibaba-VU13P/scripts/IP/GTWizard0.tcl: -------------------------------------------------------------------------------- 1 | create_ip -module_name GTWizard0 -vendor xilinx.com -library ip -name gtwizard_ultrascale -version 1.7 2 | 3 | set GTWIZARD0_PROPERTIES {} 4 | 5 | set GTWIZARD0_PROPERTIES [concat $GTWIZARD0_PROPERTIES { 6 | CONFIG.preset GTY-HDMI 7 | 8 | CONFIG.TX_USER_DATA_WIDTH 40 9 | CONFIG.TX_INT_DATA_WIDTH 40 10 | 11 | CONFIG.RX_USER_DATA_WIDTH 40 12 | CONFIG.RX_INT_DATA_WIDTH 40 13 | 14 | CONFIG.FREERUN_FREQUENCY 10.0 15 | 16 | CONFIG.CHANNEL_ENABLE { X1Y55 X1Y54 X1Y53 X1Y52 } 17 | CONFIG.TX_MASTER_CHANNEL X1Y53 18 | CONFIG.RX_MASTER_CHANNEL X1Y53 19 | 20 | CONFIG.LOCATE_TX_USER_CLOCKING CORE 21 | CONFIG.LOCATE_RX_USER_CLOCKING CORE 22 | 23 | CONFIG.ENABLE_OPTIONAL_PORTS { 24 | gtrefclk00_in 25 | gtrefclk01_in 26 | 27 | qpll0outclk_out 28 | qpll0outrefclk_out 29 | qpll1outclk_out 30 | qpll1outrefclk_out 31 | } 32 | }] 33 | 34 | switch "$RESOLUTION@$REFRESH_RATE" { 35 | "1920x1080@30" { 36 | set GTWIZARD0_PROPERTIES [concat $GTWIZARD0_PROPERTIES { 37 | CONFIG.TX_LINE_RATE 0.7425 38 | CONFIG.TX_PLL_TYPE QPLL0 39 | CONFIG.TX_QPLL_FRACN_NUMERATOR 12220050 40 | CONFIG.TX_REFCLK_FREQUENCY 161.1320001 41 | 42 | CONFIG.RX_LINE_RATE 0.7425 43 | CONFIG.RX_PLL_TYPE QPLL0 44 | CONFIG.RX_QPLL_FRACN_NUMERATOR 12220050 45 | CONFIG.RX_REFCLK_FREQUENCY 161.1320001 46 | }] 47 | } 48 | "2560x1440@30" { 49 | set GTWIZARD0_PROPERTIES [concat $GTWIZARD0_PROPERTIES { 50 | CONFIG.TX_LINE_RATE 1.21584 51 | CONFIG.TX_PLL_TYPE QPLL1 52 | CONFIG.TX_QPLL_FRACN_NUMERATOR 6122311 53 | CONFIG.TX_REFCLK_FREQUENCY 161.1320001 54 | 55 | CONFIG.RX_LINE_RATE 1.21584 56 | CONFIG.RX_PLL_TYPE QPLL1 57 | CONFIG.RX_QPLL_FRACN_NUMERATOR 6122311 58 | CONFIG.RX_REFCLK_FREQUENCY 161.1320001 59 | }] 60 | } 61 | "1920x1080@60" { 62 | set GTWIZARD0_PROPERTIES [concat $GTWIZARD0_PROPERTIES { 63 | CONFIG.TX_LINE_RATE 1.485 64 | CONFIG.TX_PLL_TYPE QPLL0 65 | CONFIG.TX_QPLL_FRACN_NUMERATOR 12220050 66 | CONFIG.TX_REFCLK_FREQUENCY 161.1320001 67 | 68 | CONFIG.RX_LINE_RATE 1.485 69 | CONFIG.RX_PLL_TYPE QPLL0 70 | CONFIG.RX_QPLL_FRACN_NUMERATOR 12220050 71 | CONFIG.RX_REFCLK_FREQUENCY 161.1320001 72 | }] 73 | } 74 | "2560x1440@60" { 75 | set GTWIZARD0_PROPERTIES [concat $GTWIZARD0_PROPERTIES { 76 | CONFIG.TX_LINE_RATE 2.43168 77 | CONFIG.TX_PLL_TYPE QPLL1 78 | CONFIG.TX_QPLL_FRACN_NUMERATOR 6122311 79 | CONFIG.TX_REFCLK_FREQUENCY 161.1320001 80 | 81 | CONFIG.RX_LINE_RATE 2.43168 82 | CONFIG.RX_PLL_TYPE QPLL1 83 | CONFIG.RX_QPLL_FRACN_NUMERATOR 6122311 84 | CONFIG.RX_REFCLK_FREQUENCY 161.1320001 85 | }] 86 | } 87 | "1920x1080@120" - 88 | "3840x2160@30" { 89 | set GTWIZARD0_PROPERTIES [concat $GTWIZARD0_PROPERTIES { 90 | CONFIG.TX_LINE_RATE 2.97 91 | CONFIG.TX_PLL_TYPE QPLL0 92 | CONFIG.TX_QPLL_FRACN_NUMERATOR 12220050 93 | CONFIG.TX_REFCLK_FREQUENCY 161.1320001 94 | 95 | CONFIG.RX_LINE_RATE 2.97 96 | CONFIG.RX_PLL_TYPE QPLL0 97 | CONFIG.RX_QPLL_FRACN_NUMERATOR 12220050 98 | CONFIG.RX_REFCLK_FREQUENCY 161.1320001 99 | }] 100 | } 101 | "1920x1080@144" { 102 | set GTWIZARD0_PROPERTIES [concat $GTWIZARD0_PROPERTIES { 103 | CONFIG.TX_LINE_RATE 3.564 104 | CONFIG.TX_PLL_TYPE QPLL0 105 | CONFIG.TX_QPLL_FRACN_NUMERATOR 7953174 106 | CONFIG.TX_REFCLK_FREQUENCY 161.132 107 | 108 | CONFIG.RX_LINE_RATE 3.564 109 | CONFIG.RX_PLL_TYPE QPLL0 110 | CONFIG.RX_QPLL_FRACN_NUMERATOR 7953174 111 | CONFIG.RX_REFCLK_FREQUENCY 161.132 112 | }] 113 | } 114 | "2560x1440@120" { 115 | set GTWIZARD0_PROPERTIES [concat $GTWIZARD0_PROPERTIES { 116 | CONFIG.TX_LINE_RATE 4.86336 117 | CONFIG.TX_PLL_TYPE QPLL1 118 | CONFIG.TX_QPLL_FRACN_NUMERATOR 6122311 119 | CONFIG.TX_REFCLK_FREQUENCY 161.1320001 120 | 121 | CONFIG.RX_LINE_RATE 4.86336 122 | CONFIG.RX_PLL_TYPE QPLL1 123 | CONFIG.RX_QPLL_FRACN_NUMERATOR 6122311 124 | CONFIG.RX_REFCLK_FREQUENCY 161.1320001 125 | }] 126 | } 127 | "2560x1440@144" { 128 | set GTWIZARD0_PROPERTIES [concat $GTWIZARD0_PROPERTIES { 129 | CONFIG.TX_LINE_RATE 5.836032 130 | CONFIG.TX_PLL_TYPE QPLL0 131 | CONFIG.TX_QPLL_FRACN_NUMERATOR 7346773 132 | CONFIG.TX_REFCLK_FREQUENCY 161.1320001 133 | 134 | CONFIG.RX_LINE_RATE 5.836032 135 | CONFIG.RX_PLL_TYPE QPLL0 136 | CONFIG.RX_QPLL_FRACN_NUMERATOR 7346773 137 | CONFIG.RX_REFCLK_FREQUENCY 161.1320001 138 | }] 139 | } 140 | "1920x1080@240" - 141 | "3840x2160@60" { 142 | set GTWIZARD0_PROPERTIES [concat $GTWIZARD0_PROPERTIES { 143 | CONFIG.TX_LINE_RATE 5.94 144 | CONFIG.TX_PLL_TYPE QPLL0 145 | CONFIG.TX_QPLL_FRACN_NUMERATOR 12220050 146 | CONFIG.TX_REFCLK_FREQUENCY 161.1320001 147 | 148 | CONFIG.RX_LINE_RATE 5.94 149 | CONFIG.RX_PLL_TYPE QPLL0 150 | CONFIG.RX_QPLL_FRACN_NUMERATOR 12220050 151 | CONFIG.RX_REFCLK_FREQUENCY 161.1320001 152 | }] 153 | } 154 | default { 155 | error "Invalid video mode $RESOLUTION@$REFRESH_RATE" 156 | } 157 | } 158 | 159 | set_property -dict $GTWIZARD0_PROPERTIES [get_ips GTWizard0] 160 | -------------------------------------------------------------------------------- /QSFP-HDMI-OUT-NB7NQ621M/examples/Alibaba-VU13P/scripts/IP/GTWizard1.tcl: -------------------------------------------------------------------------------- 1 | create_ip -module_name GTWizard1 -vendor xilinx.com -library ip -name gtwizard_ultrascale -version 1.7 2 | 3 | set GTWIZARD1_PROPERTIES {} 4 | 5 | set GTWIZARD1_PROPERTIES [concat $GTWIZARD1_PROPERTIES { 6 | CONFIG.preset GTY-HDMI 7 | 8 | CONFIG.TX_USER_DATA_WIDTH 40 9 | CONFIG.TX_INT_DATA_WIDTH 40 10 | 11 | CONFIG.RX_USER_DATA_WIDTH 40 12 | CONFIG.RX_INT_DATA_WIDTH 40 13 | 14 | CONFIG.FREERUN_FREQUENCY 10.0 15 | 16 | CONFIG.CHANNEL_ENABLE { X1Y39 X1Y38 X1Y37 X1Y36 } 17 | CONFIG.TX_MASTER_CHANNEL X1Y37 18 | CONFIG.RX_MASTER_CHANNEL X1Y37 19 | 20 | CONFIG.LOCATE_TX_USER_CLOCKING CORE 21 | CONFIG.LOCATE_RX_USER_CLOCKING CORE 22 | 23 | CONFIG.ENABLE_OPTIONAL_PORTS { 24 | gtrefclk00_in 25 | gtrefclk01_in 26 | 27 | qpll0outclk_out 28 | qpll0outrefclk_out 29 | qpll1outclk_out 30 | qpll1outrefclk_out 31 | } 32 | }] 33 | 34 | switch "$RESOLUTION@$REFRESH_RATE" { 35 | "1920x1080@30" { 36 | set GTWIZARD1_PROPERTIES [concat $GTWIZARD1_PROPERTIES { 37 | CONFIG.TX_LINE_RATE 0.7425 38 | CONFIG.TX_PLL_TYPE QPLL0 39 | CONFIG.TX_QPLL_FRACN_NUMERATOR 12220050 40 | CONFIG.TX_REFCLK_FREQUENCY 161.1320001 41 | 42 | CONFIG.RX_LINE_RATE 0.7425 43 | CONFIG.RX_PLL_TYPE QPLL0 44 | CONFIG.RX_QPLL_FRACN_NUMERATOR 12220050 45 | CONFIG.RX_REFCLK_FREQUENCY 161.1320001 46 | }] 47 | } 48 | "2560x1440@30" { 49 | set GTWIZARD1_PROPERTIES [concat $GTWIZARD1_PROPERTIES { 50 | CONFIG.TX_LINE_RATE 1.21584 51 | CONFIG.TX_PLL_TYPE QPLL1 52 | CONFIG.TX_QPLL_FRACN_NUMERATOR 6122311 53 | CONFIG.TX_REFCLK_FREQUENCY 161.1320001 54 | 55 | CONFIG.RX_LINE_RATE 1.21584 56 | CONFIG.RX_PLL_TYPE QPLL1 57 | CONFIG.RX_QPLL_FRACN_NUMERATOR 6122311 58 | CONFIG.RX_REFCLK_FREQUENCY 161.1320001 59 | }] 60 | } 61 | "1920x1080@60" { 62 | set GTWIZARD1_PROPERTIES [concat $GTWIZARD1_PROPERTIES { 63 | CONFIG.TX_LINE_RATE 1.485 64 | CONFIG.TX_PLL_TYPE QPLL0 65 | CONFIG.TX_QPLL_FRACN_NUMERATOR 12220050 66 | CONFIG.TX_REFCLK_FREQUENCY 161.1320001 67 | 68 | CONFIG.RX_LINE_RATE 1.485 69 | CONFIG.RX_PLL_TYPE QPLL0 70 | CONFIG.RX_QPLL_FRACN_NUMERATOR 12220050 71 | CONFIG.RX_REFCLK_FREQUENCY 161.1320001 72 | }] 73 | } 74 | "2560x1440@60" { 75 | set GTWIZARD1_PROPERTIES [concat $GTWIZARD1_PROPERTIES { 76 | CONFIG.TX_LINE_RATE 2.43168 77 | CONFIG.TX_PLL_TYPE QPLL1 78 | CONFIG.TX_QPLL_FRACN_NUMERATOR 6122311 79 | CONFIG.TX_REFCLK_FREQUENCY 161.1320001 80 | 81 | CONFIG.RX_LINE_RATE 2.43168 82 | CONFIG.RX_PLL_TYPE QPLL1 83 | CONFIG.RX_QPLL_FRACN_NUMERATOR 6122311 84 | CONFIG.RX_REFCLK_FREQUENCY 161.1320001 85 | }] 86 | } 87 | "1920x1080@120" - 88 | "3840x2160@30" { 89 | set GTWIZARD1_PROPERTIES [concat $GTWIZARD1_PROPERTIES { 90 | CONFIG.TX_LINE_RATE 2.97 91 | CONFIG.TX_PLL_TYPE QPLL0 92 | CONFIG.TX_QPLL_FRACN_NUMERATOR 12220050 93 | CONFIG.TX_REFCLK_FREQUENCY 161.1320001 94 | 95 | CONFIG.RX_LINE_RATE 2.97 96 | CONFIG.RX_PLL_TYPE QPLL0 97 | CONFIG.RX_QPLL_FRACN_NUMERATOR 12220050 98 | CONFIG.RX_REFCLK_FREQUENCY 161.1320001 99 | }] 100 | } 101 | "1920x1080@144" { 102 | set GTWIZARD1_PROPERTIES [concat $GTWIZARD1_PROPERTIES { 103 | CONFIG.TX_LINE_RATE 3.564 104 | CONFIG.TX_PLL_TYPE QPLL0 105 | CONFIG.TX_QPLL_FRACN_NUMERATOR 7953174 106 | CONFIG.TX_REFCLK_FREQUENCY 161.132 107 | 108 | CONFIG.RX_LINE_RATE 3.564 109 | CONFIG.RX_PLL_TYPE QPLL0 110 | CONFIG.RX_QPLL_FRACN_NUMERATOR 7953174 111 | CONFIG.RX_REFCLK_FREQUENCY 161.132 112 | }] 113 | } 114 | "2560x1440@120" { 115 | set GTWIZARD1_PROPERTIES [concat $GTWIZARD1_PROPERTIES { 116 | CONFIG.TX_LINE_RATE 4.86336 117 | CONFIG.TX_PLL_TYPE QPLL1 118 | CONFIG.TX_QPLL_FRACN_NUMERATOR 6122311 119 | CONFIG.TX_REFCLK_FREQUENCY 161.1320001 120 | 121 | CONFIG.RX_LINE_RATE 4.86336 122 | CONFIG.RX_PLL_TYPE QPLL1 123 | CONFIG.RX_QPLL_FRACN_NUMERATOR 6122311 124 | CONFIG.RX_REFCLK_FREQUENCY 161.1320001 125 | }] 126 | } 127 | "2560x1440@144" { 128 | set GTWIZARD1_PROPERTIES [concat $GTWIZARD1_PROPERTIES { 129 | CONFIG.TX_LINE_RATE 5.836032 130 | CONFIG.TX_PLL_TYPE QPLL0 131 | CONFIG.TX_QPLL_FRACN_NUMERATOR 7346773 132 | CONFIG.TX_REFCLK_FREQUENCY 161.1320001 133 | 134 | CONFIG.RX_LINE_RATE 5.836032 135 | CONFIG.RX_PLL_TYPE QPLL0 136 | CONFIG.RX_QPLL_FRACN_NUMERATOR 7346773 137 | CONFIG.RX_REFCLK_FREQUENCY 161.1320001 138 | }] 139 | } 140 | "1920x1080@240" - 141 | "3840x2160@60" { 142 | set GTWIZARD1_PROPERTIES [concat $GTWIZARD1_PROPERTIES { 143 | CONFIG.TX_LINE_RATE 5.94 144 | CONFIG.TX_PLL_TYPE QPLL0 145 | CONFIG.TX_QPLL_FRACN_NUMERATOR 12220050 146 | CONFIG.TX_REFCLK_FREQUENCY 161.1320001 147 | 148 | CONFIG.RX_LINE_RATE 5.94 149 | CONFIG.RX_PLL_TYPE QPLL0 150 | CONFIG.RX_QPLL_FRACN_NUMERATOR 12220050 151 | CONFIG.RX_REFCLK_FREQUENCY 161.1320001 152 | }] 153 | } 154 | default { 155 | error "Invalid video mode $RESOLUTION@$REFRESH_RATE" 156 | } 157 | } 158 | 159 | set_property -dict $GTWIZARD1_PROPERTIES [get_ips GTWizard1] 160 | -------------------------------------------------------------------------------- /QSFP-HDMI-OUT-NB7NQ621M/examples/Alibaba-VU13P/scripts/IP/PLL0.tcl: -------------------------------------------------------------------------------- 1 | create_ip -module_name PLL0 -vendor xilinx.com -library ip -name clk_wiz -version 6.0 2 | 3 | set_property -dict { 4 | CONFIG.PRIMITIVE PLL 5 | CONFIG.PRIMARY_PORT clk_in1 6 | CONFIG.PRIM_IN_FREQ 100.000 7 | CONFIG.PRIM_SOURCE Differential_clock_capable_pin 8 | 9 | CONFIG.NUM_OUT_CLKS 2 10 | 11 | CONFIG.CLKOUT1_USED true 12 | CONFIG.CLK_OUT1_PORT clk_out1 13 | CONFIG.CLKOUT1_REQUESTED_OUT_FREQ 200.000 14 | CONFIG.CLKOUT1_DRIVES BUFG 15 | 16 | CONFIG.CLKOUT2_USED true 17 | CONFIG.CLK_OUT2_PORT clk_out2 18 | CONFIG.CLKOUT2_REQUESTED_OUT_FREQ 10.000 19 | CONFIG.CLKOUT2_DRIVES BUFG 20 | } [get_ips PLL0] 21 | -------------------------------------------------------------------------------- /QSFP-HDMI-OUT-NB7NQ621M/examples/Alibaba-VU13P/sources/GTWizardWrapper.v: -------------------------------------------------------------------------------- 1 | module GTWizardWrapper0( 2 | input clock, 3 | input reset, 4 | 5 | input refclk_p, 6 | input refclk_n, 7 | input [3:0] rxp, 8 | input [3:0] rxn, 9 | output [3:0] txp, 10 | output [3:0] txn, 11 | 12 | output tx_clock, 13 | output tx_reset, 14 | input [159:0] tx_data 15 | ); 16 | 17 | wire refclk; 18 | 19 | IBUFDS_GTE4 ibufds_gte4 ( 20 | .O (refclk), 21 | .ODIV2 (), 22 | .CEB (0), 23 | .I (refclk_p), 24 | .IB (refclk_n) 25 | ); 26 | 27 | wire userclk_tx_reset; 28 | wire userclk_tx_usrclk2; 29 | wire userclk_tx_active; 30 | wire buffbypass_tx_reset; 31 | wire buffbypass_tx_done; 32 | wire buffbypass_tx_error; 33 | wire reset_tx_done; 34 | wire [3:0] txpmaresetdone; 35 | wire [3:0] txprgdivresetdone; 36 | 37 | GTWizard0 gt_wizard( 38 | .gtwiz_userclk_tx_reset_in (userclk_tx_reset), 39 | .gtwiz_userclk_tx_srcclk_out (), 40 | .gtwiz_userclk_tx_usrclk_out (), 41 | .gtwiz_userclk_tx_usrclk2_out (userclk_tx_usrclk2), 42 | .gtwiz_userclk_tx_active_out (userclk_tx_active), 43 | .gtwiz_userclk_rx_reset_in (1), 44 | .gtwiz_userclk_rx_srcclk_out (), 45 | .gtwiz_userclk_rx_usrclk_out (), 46 | .gtwiz_userclk_rx_usrclk2_out (), 47 | .gtwiz_userclk_rx_active_out (), 48 | .gtwiz_buffbypass_tx_reset_in (buffbypass_tx_reset), 49 | .gtwiz_buffbypass_tx_start_user_in (0), 50 | .gtwiz_buffbypass_tx_done_out (buffbypass_tx_done), 51 | .gtwiz_buffbypass_tx_error_out (buffbypass_tx_error), 52 | .gtwiz_reset_clk_freerun_in (clock), 53 | .gtwiz_reset_all_in (reset), 54 | .gtwiz_reset_tx_pll_and_datapath_in (0), 55 | .gtwiz_reset_tx_datapath_in (0), 56 | .gtwiz_reset_rx_pll_and_datapath_in (0), 57 | .gtwiz_reset_rx_datapath_in (0), 58 | .gtwiz_reset_rx_cdr_stable_out (), 59 | .gtwiz_reset_tx_done_out (reset_tx_done), 60 | .gtwiz_reset_rx_done_out (), 61 | .gtwiz_userdata_tx_in (tx_data), 62 | .gtwiz_userdata_rx_out (), 63 | .gtrefclk00_in (refclk), 64 | .gtrefclk01_in (refclk), 65 | .qpll0outclk_out (), 66 | .qpll0outrefclk_out (), 67 | .qpll1outclk_out (), 68 | .qpll1outrefclk_out (), 69 | .gtyrxn_in (rxn), 70 | .gtyrxp_in (rxp), 71 | .gtpowergood_out (), 72 | .gtytxn_out (txn), 73 | .gtytxp_out (txp), 74 | .rxpmaresetdone_out (), 75 | .txpmaresetdone_out (txpmaresetdone), 76 | .txprgdivresetdone_out (txprgdivresetdone) 77 | ); 78 | 79 | assign userclk_tx_reset = ~(&txpmaresetdone & &txprgdivresetdone); 80 | 81 | reg [2:0] buffbypass_tx_reset_reg; 82 | always @(posedge userclk_tx_usrclk2) begin 83 | if (~userclk_tx_active) begin 84 | buffbypass_tx_reset_reg <= 5; 85 | end else begin 86 | if (buffbypass_tx_reset_reg != 0) 87 | buffbypass_tx_reset_reg <= buffbypass_tx_reset_reg - 1; 88 | end 89 | end 90 | assign buffbypass_tx_reset = buffbypass_tx_reset_reg != 0; 91 | 92 | assign tx_clock = userclk_tx_usrclk2; 93 | assign tx_reset = reset | ~reset_tx_done | ~buffbypass_tx_done; 94 | 95 | endmodule 96 | 97 | 98 | module GTWizardWrapper1( 99 | input clock, 100 | input reset, 101 | 102 | input refclk_p, 103 | input refclk_n, 104 | input [3:0] rxp, 105 | input [3:0] rxn, 106 | output [3:0] txp, 107 | output [3:0] txn, 108 | 109 | output tx_clock, 110 | output tx_reset, 111 | input [159:0] tx_data 112 | ); 113 | 114 | wire refclk; 115 | 116 | IBUFDS_GTE4 ibufds_gte4 ( 117 | .O (refclk), 118 | .ODIV2 (), 119 | .CEB (0), 120 | .I (refclk_p), 121 | .IB (refclk_n) 122 | ); 123 | 124 | wire userclk_tx_reset; 125 | wire userclk_tx_usrclk2; 126 | wire userclk_tx_active; 127 | wire buffbypass_tx_reset; 128 | wire buffbypass_tx_done; 129 | wire buffbypass_tx_error; 130 | wire reset_tx_done; 131 | wire [3:0] txpmaresetdone; 132 | wire [3:0] txprgdivresetdone; 133 | 134 | GTWizard1 gt_wizard( 135 | .gtwiz_userclk_tx_reset_in (userclk_tx_reset), 136 | .gtwiz_userclk_tx_srcclk_out (), 137 | .gtwiz_userclk_tx_usrclk_out (), 138 | .gtwiz_userclk_tx_usrclk2_out (userclk_tx_usrclk2), 139 | .gtwiz_userclk_tx_active_out (userclk_tx_active), 140 | .gtwiz_userclk_rx_reset_in (1), 141 | .gtwiz_userclk_rx_srcclk_out (), 142 | .gtwiz_userclk_rx_usrclk_out (), 143 | .gtwiz_userclk_rx_usrclk2_out (), 144 | .gtwiz_userclk_rx_active_out (), 145 | .gtwiz_buffbypass_tx_reset_in (buffbypass_tx_reset), 146 | .gtwiz_buffbypass_tx_start_user_in (0), 147 | .gtwiz_buffbypass_tx_done_out (buffbypass_tx_done), 148 | .gtwiz_buffbypass_tx_error_out (buffbypass_tx_error), 149 | .gtwiz_reset_clk_freerun_in (clock), 150 | .gtwiz_reset_all_in (reset), 151 | .gtwiz_reset_tx_pll_and_datapath_in (0), 152 | .gtwiz_reset_tx_datapath_in (0), 153 | .gtwiz_reset_rx_pll_and_datapath_in (0), 154 | .gtwiz_reset_rx_datapath_in (0), 155 | .gtwiz_reset_rx_cdr_stable_out (), 156 | .gtwiz_reset_tx_done_out (reset_tx_done), 157 | .gtwiz_reset_rx_done_out (), 158 | .gtwiz_userdata_tx_in (tx_data), 159 | .gtwiz_userdata_rx_out (), 160 | .gtrefclk00_in (refclk), 161 | .gtrefclk01_in (refclk), 162 | .qpll0outclk_out (), 163 | .qpll0outrefclk_out (), 164 | .qpll1outclk_out (), 165 | .qpll1outrefclk_out (), 166 | .gtyrxn_in (rxn), 167 | .gtyrxp_in (rxp), 168 | .gtpowergood_out (), 169 | .gtytxn_out (txn), 170 | .gtytxp_out (txp), 171 | .rxpmaresetdone_out (), 172 | .txpmaresetdone_out (txpmaresetdone), 173 | .txprgdivresetdone_out (txprgdivresetdone) 174 | ); 175 | 176 | assign userclk_tx_reset = ~(&txpmaresetdone & &txprgdivresetdone); 177 | 178 | reg [2:0] buffbypass_tx_reset_reg; 179 | always @(posedge userclk_tx_usrclk2) begin 180 | if (~userclk_tx_active) begin 181 | buffbypass_tx_reset_reg <= 5; 182 | end else begin 183 | if (buffbypass_tx_reset_reg != 0) 184 | buffbypass_tx_reset_reg <= buffbypass_tx_reset_reg - 1; 185 | end 186 | end 187 | assign buffbypass_tx_reset = buffbypass_tx_reset_reg != 0; 188 | 189 | assign tx_clock = userclk_tx_usrclk2; 190 | assign tx_reset = reset | ~reset_tx_done | ~buffbypass_tx_done; 191 | 192 | endmodule 193 | -------------------------------------------------------------------------------- /QSFP-HDMI-OUT-NB7NQ621M/examples/Alibaba-VU13P/sources/Top.v: -------------------------------------------------------------------------------- 1 | `ifndef RESOLUTION 2 | `define RESOLUTION "1920x1080" 3 | `endif 4 | `ifndef REFRESH_RATE 5 | `define REFRESH_RATE 60 6 | `endif 7 | 8 | 9 | module Top( 10 | input clock_100_p, 11 | input clock_100_n, 12 | 13 | output led_run, 14 | output [7:0] led, 15 | 16 | input qsfp1_refclk_p, 17 | input qsfp1_refclk_n, 18 | input [3:0] qsfp1_rxp, 19 | input [3:0] qsfp1_rxn, 20 | output [3:0] qsfp1_txp, 21 | output [3:0] qsfp1_txn, 22 | input qsfp1_modprsl, 23 | output qsfp1_resetl, 24 | inout qsfp1_scl, 25 | inout qsfp1_sda, 26 | output qsfp1_led_y, 27 | output qsfp1_led_g, 28 | 29 | input qsfp2_refclk_p, 30 | input qsfp2_refclk_n, 31 | input [3:0] qsfp2_rxp, 32 | input [3:0] qsfp2_rxn, 33 | output [3:0] qsfp2_txp, 34 | output [3:0] qsfp2_txn, 35 | input qsfp2_modprsl, 36 | output qsfp2_resetl, 37 | inout qsfp2_scl, 38 | inout qsfp2_sda, 39 | output qsfp2_led_y, 40 | output qsfp2_led_g 41 | ); 42 | 43 | localparam CLOCK_FREQUENCY = 200_000_000; 44 | 45 | 46 | wire system_reset_input = 0; 47 | 48 | wire system_clock; 49 | wire gt_config_clock; 50 | wire pll0_locked; 51 | 52 | PLL0 pll0( 53 | .clk_in1_p (clock_100_p), 54 | .clk_in1_n (clock_100_n), 55 | .reset (system_reset_input), 56 | .clk_out1 (system_clock), 57 | .clk_out2 (gt_config_clock), 58 | .locked (pll0_locked) 59 | ); 60 | 61 | 62 | wire system_reset = ~pll0_locked; 63 | 64 | wire [1:0] tx_clock; 65 | wire [1:0] tx_reset; 66 | wire [159:0] tx_data[1:0]; 67 | 68 | GTWizardWrapper0 gt_wizard_wrapper_0( 69 | .clock (gt_config_clock), 70 | .reset (system_reset), 71 | 72 | .refclk_p (qsfp1_refclk_p), 73 | .refclk_n (qsfp1_refclk_n), 74 | .rxp (qsfp1_rxp), 75 | .rxn (qsfp1_rxn), 76 | .txp (qsfp1_txp), 77 | .txn (qsfp1_txn), 78 | 79 | .tx_clock (tx_clock[0]), 80 | .tx_reset (tx_reset[0]), 81 | .tx_data (tx_data[0]) 82 | ); 83 | 84 | GTWizardWrapper1 gt_wizard_wrapper_1( 85 | .clock (gt_config_clock), 86 | .reset (system_reset), 87 | 88 | .refclk_p (qsfp2_refclk_p), 89 | .refclk_n (qsfp2_refclk_n), 90 | .rxp (qsfp2_rxp), 91 | .rxn (qsfp2_rxn), 92 | .txp (qsfp2_txp), 93 | .txn (qsfp2_txn), 94 | 95 | .tx_clock (tx_clock[1]), 96 | .tx_reset (tx_reset[1]), 97 | .tx_data (tx_data[1]) 98 | ); 99 | 100 | 101 | wire [1:0] qsfp_scl_input; 102 | wire [1:0] qsfp_scl_output; 103 | wire [1:0] qsfp_sda_input; 104 | wire [1:0] qsfp_sda_output; 105 | 106 | IOBUF qsfp1_scl_iobuf( 107 | .O (qsfp_scl_input[0]), 108 | .I (qsfp_scl_output[0]), 109 | .IO (qsfp1_scl), 110 | .T (qsfp_scl_output[0]) 111 | ); 112 | IOBUF qsfp1_sda_iobuf( 113 | .O (qsfp_sda_input[0]), 114 | .I (qsfp_sda_output[0]), 115 | .IO (qsfp1_sda), 116 | .T (qsfp_sda_output[0]) 117 | ); 118 | 119 | IOBUF qsfp2_scl_iobuf( 120 | .O (qsfp_scl_input[1]), 121 | .I (qsfp_scl_output[1]), 122 | .IO (qsfp2_scl), 123 | .T (qsfp_scl_output[1]) 124 | ); 125 | IOBUF qsfp2_sda_iobuf( 126 | .O (qsfp_sda_input[1]), 127 | .I (qsfp_sda_output[1]), 128 | .IO (qsfp2_sda), 129 | .T (qsfp_sda_output[1]) 130 | ); 131 | 132 | wire [1:0] hpd = { ~qsfp2_modprsl, ~qsfp1_modprsl }; 133 | wire [1:0] run; 134 | 135 | genvar i; 136 | 137 | generate 138 | for (i = 0; i < 2; i = i + 1) begin: hdmi_out_examples 139 | HDMIOUTExample #( 140 | .CLOCK_FREQUENCY (CLOCK_FREQUENCY), 141 | .RESOLUTION (`RESOLUTION), 142 | .REFRESH_RATE (`REFRESH_RATE) 143 | ) hdmi_out_example( 144 | .system_clock (system_clock), 145 | .system_reset (system_reset), 146 | .tx_clock (tx_clock[i]), 147 | .tx_reset (tx_reset[i]), 148 | .tx_data (tx_data[i]), 149 | .hpd (hpd[i]), 150 | .scl_input (qsfp_scl_input[i]), 151 | .scl_output (qsfp_scl_output[i]), 152 | .sda_input (qsfp_sda_input[i]), 153 | .sda_output (qsfp_sda_output[i]), 154 | .i2c_request (), 155 | .i2c_grant (1'b1), 156 | .run (run[i]) 157 | ); 158 | end 159 | endgenerate 160 | 161 | assign led_run = ~system_reset; 162 | assign led = 8'b0; 163 | 164 | assign qsfp1_resetl = ~system_reset; 165 | assign qsfp1_led_y = ~system_reset & hpd[0] & ~run[0]; 166 | assign qsfp1_led_g = ~system_reset & run[0]; 167 | 168 | assign qsfp2_resetl = ~system_reset; 169 | assign qsfp2_led_y = ~system_reset & hpd[1] & ~run[1]; 170 | assign qsfp2_led_g = ~system_reset & run[1]; 171 | 172 | endmodule 173 | -------------------------------------------------------------------------------- /QSFP-HDMI-OUT-NB7NQ621M/examples/BoChenJingXin-KU5P/build.py: -------------------------------------------------------------------------------- 1 | import argparse 2 | import os 3 | import shutil 4 | import subprocess 5 | 6 | VIVADO = os.getenv('VIVADO', shutil.which('vivado')) 7 | MILL = os.getenv('MILL', shutil.which('mill')) 8 | 9 | RESOLUTION_LIST = [ 10 | '1920x1080', 11 | '2560x1440', 12 | '3840x2160', 13 | ] 14 | REFRESH_RATE_LIST = [ 15 | '30', 16 | '60', 17 | '120', 18 | '144', 19 | '240', 20 | ] 21 | 22 | PROJECT_PATH = os.path.dirname(os.path.realpath(__file__)) 23 | COMMON_PATH = os.path.join(PROJECT_PATH, '..', '..', '..', 'common') 24 | COMMON_CHISEL_PATH = os.path.join(COMMON_PATH, 'Chisel') 25 | COMMON_SCRIPTS_PATH = os.path.join(COMMON_PATH, 'Vivado', 'scripts') 26 | SCRIPTS_PATH = os.path.join(PROJECT_PATH, 'scripts') 27 | CONFIG_PATH = os.path.join(SCRIPTS_PATH, 'Config.tcl') 28 | BUILD_PATH = os.path.join(PROJECT_PATH, 'build') 29 | GENERATED_PATH = os.path.join(BUILD_PATH, 'generated') 30 | BITSTREAM_PATH = os.path.join(BUILD_PATH, 'bitstream') 31 | 32 | def runCommand(command, **kwargs): 33 | print(command) 34 | subprocess.run(command, check = True, **kwargs) 35 | 36 | def runVivadoScript(script, *args): 37 | runCommand([VIVADO, '-nojournal', '-nolog', '-mode', 'batch', '-source', script, '-tclargs', *args], cwd = BUILD_PATH) 38 | 39 | if __name__ == "__main__": 40 | parser = argparse.ArgumentParser() 41 | parser.add_argument('command', choices = ['build', 'program', 'flash']) 42 | parser.add_argument('--resolution', choices = RESOLUTION_LIST, default = '1920x1080') 43 | parser.add_argument('--refresh-rate', choices = REFRESH_RATE_LIST, default = '60') 44 | parser.add_argument('-j', '--jobs', default = '8') 45 | args = parser.parse_args() 46 | 47 | RESOLUTION = args.resolution 48 | REFRESH_RATE = args.refresh_rate 49 | JOBS = args.jobs 50 | 51 | if args.command == 'build': 52 | os.makedirs(GENERATED_PATH, exist_ok = True) 53 | runCommand([MILL, 'hdmioutexample.run', '-o', os.path.join(GENERATED_PATH, 'HDMIOutExample.sv')], cwd = COMMON_CHISEL_PATH) 54 | 55 | runVivadoScript(os.path.join(SCRIPTS_PATH, 'CreateProject.tcl'), RESOLUTION, REFRESH_RATE) 56 | runVivadoScript(os.path.join(COMMON_SCRIPTS_PATH, 'Synthesis.tcl'), CONFIG_PATH, JOBS) 57 | runVivadoScript(os.path.join(COMMON_SCRIPTS_PATH, 'Implementation.tcl'), CONFIG_PATH, JOBS) 58 | runVivadoScript(os.path.join(COMMON_SCRIPTS_PATH, 'GenerateBitstream.tcl'), CONFIG_PATH, BITSTREAM_PATH) 59 | elif args.command == 'program': 60 | runVivadoScript(os.path.join(COMMON_SCRIPTS_PATH, 'Program.tcl'), CONFIG_PATH, BITSTREAM_PATH) 61 | elif args.command == 'flash': 62 | runVivadoScript(os.path.join(COMMON_SCRIPTS_PATH, 'Flash.tcl'), CONFIG_PATH, BITSTREAM_PATH) 63 | else: 64 | assert False 65 | -------------------------------------------------------------------------------- /QSFP-HDMI-OUT-NB7NQ621M/examples/BoChenJingXin-KU5P/constraints/Timing.xdc: -------------------------------------------------------------------------------- 1 | # System clock frequency = 200MHz 2 | create_clock -name system_clock -period 5 -quiet [get_nets system_clock] 3 | 4 | # Maximum TX clock frequency = 6GHz / 40 bits per clock = 150MHz 5 | create_clock -name tx_clock -period 6.666 -quiet [get_nets tx_clock] 6 | 7 | set_clock_groups -asynchronous \ 8 | -group system_clock \ 9 | -group tx_clock 10 | -------------------------------------------------------------------------------- /QSFP-HDMI-OUT-NB7NQ621M/examples/BoChenJingXin-KU5P/scripts/Config.tcl: -------------------------------------------------------------------------------- 1 | set PROJECT_NAME BoChenJingXin-KU5P-Example 2 | 3 | set TOP_NAME Top 4 | 5 | set PART_NAME xcku5p-ffvb676-2-i 6 | 7 | set HW_DEVICE_NAME xcku5p_0 8 | set CFGMEM_PART_NAME mt25qu256-spi-x1_x2_x4 9 | -------------------------------------------------------------------------------- /QSFP-HDMI-OUT-NB7NQ621M/examples/BoChenJingXin-KU5P/scripts/CreateProject.tcl: -------------------------------------------------------------------------------- 1 | set RESOLUTION [lindex $argv 0] 2 | set REFRESH_RATE [lindex $argv 1] 3 | 4 | set PROJECT_PATH [file normalize [file dirname [info script]]/..] 5 | 6 | source $PROJECT_PATH/scripts/Config.tcl 7 | 8 | create_project -force -part $PART_NAME $PROJECT_NAME 9 | 10 | source $PROJECT_PATH/scripts/IP/GTWizard0.tcl 11 | source $PROJECT_PATH/scripts/IP/MMCM0.tcl 12 | 13 | set_property VERILOG_DEFINE [list \ 14 | RESOLUTION="$RESOLUTION" \ 15 | REFRESH_RATE=$REFRESH_RATE \ 16 | ] [get_filesets sources_1] 17 | 18 | set_property top $TOP_NAME [current_fileset] 19 | 20 | add_files -fileset sources_1 \ 21 | [glob $PROJECT_PATH/../../../common/Verilog/*/*.v] \ 22 | [glob $PROJECT_PATH/build/generated/*.sv] \ 23 | [glob $PROJECT_PATH/sources/*.v] 24 | 25 | add_files -fileset constrs_1 \ 26 | [glob $PROJECT_PATH/../../../common/Vivado/constraints/BoChenJingXin-KU5P/*.xdc] \ 27 | [glob $PROJECT_PATH/constraints/*.xdc] 28 | -------------------------------------------------------------------------------- /QSFP-HDMI-OUT-NB7NQ621M/examples/BoChenJingXin-KU5P/scripts/IP/GTWizard0.tcl: -------------------------------------------------------------------------------- 1 | create_ip -module_name GTWizard0 -vendor xilinx.com -library ip -name gtwizard_ultrascale -version 1.7 2 | 3 | set GTWIZARD0_PROPERTIES {} 4 | 5 | set GTWIZARD0_PROPERTIES [concat $GTWIZARD0_PROPERTIES { 6 | CONFIG.preset GTY-HDMI 7 | 8 | CONFIG.TX_USER_DATA_WIDTH 40 9 | CONFIG.TX_INT_DATA_WIDTH 40 10 | 11 | CONFIG.RX_USER_DATA_WIDTH 40 12 | CONFIG.RX_INT_DATA_WIDTH 40 13 | 14 | CONFIG.FREERUN_FREQUENCY 10.0 15 | 16 | CONFIG.CHANNEL_ENABLE { X0Y7 X0Y6 X0Y5 X0Y4 } 17 | CONFIG.TX_MASTER_CHANNEL X0Y5 18 | CONFIG.RX_MASTER_CHANNEL X0Y5 19 | 20 | CONFIG.LOCATE_TX_USER_CLOCKING CORE 21 | CONFIG.LOCATE_RX_USER_CLOCKING CORE 22 | 23 | CONFIG.ENABLE_OPTIONAL_PORTS { 24 | gtrefclk00_in 25 | gtrefclk01_in 26 | 27 | qpll0outclk_out 28 | qpll0outrefclk_out 29 | qpll1outclk_out 30 | qpll1outrefclk_out 31 | } 32 | }] 33 | 34 | switch "$RESOLUTION@$REFRESH_RATE" { 35 | "1920x1080@30" { 36 | set GTWIZARD0_PROPERTIES [concat $GTWIZARD0_PROPERTIES { 37 | CONFIG.TX_LINE_RATE 0.7425 38 | CONFIG.TX_PLL_TYPE QPLL0 39 | CONFIG.TX_QPLL_FRACN_NUMERATOR 536870 40 | CONFIG.TX_REFCLK_FREQUENCY 156.2500001 41 | 42 | CONFIG.RX_LINE_RATE 0.7425 43 | CONFIG.RX_PLL_TYPE QPLL0 44 | CONFIG.RX_QPLL_FRACN_NUMERATOR 536870 45 | CONFIG.RX_REFCLK_FREQUENCY 156.2500001 46 | }] 47 | } 48 | "2560x1440@30" { 49 | set GTWIZARD0_PROPERTIES [concat $GTWIZARD0_PROPERTIES { 50 | CONFIG.TX_LINE_RATE 1.21584 51 | CONFIG.TX_PLL_TYPE QPLL1 52 | CONFIG.TX_QPLL_FRACN_NUMERATOR 4211215 53 | CONFIG.TX_REFCLK_FREQUENCY 156.2500001 54 | 55 | CONFIG.RX_LINE_RATE 1.21584 56 | CONFIG.RX_PLL_TYPE QPLL1 57 | CONFIG.RX_QPLL_FRACN_NUMERATOR 4211215 58 | CONFIG.RX_REFCLK_FREQUENCY 156.2500001 59 | }] 60 | } 61 | "1920x1080@60" { 62 | set GTWIZARD0_PROPERTIES [concat $GTWIZARD0_PROPERTIES { 63 | CONFIG.TX_LINE_RATE 1.485 64 | CONFIG.TX_PLL_TYPE QPLL0 65 | CONFIG.TX_QPLL_FRACN_NUMERATOR 536870 66 | CONFIG.TX_REFCLK_FREQUENCY 156.2500001 67 | 68 | CONFIG.RX_LINE_RATE 1.485 69 | CONFIG.RX_PLL_TYPE QPLL0 70 | CONFIG.RX_QPLL_FRACN_NUMERATOR 536870 71 | CONFIG.RX_REFCLK_FREQUENCY 156.2500001 72 | }] 73 | } 74 | "2560x1440@60" { 75 | set GTWIZARD0_PROPERTIES [concat $GTWIZARD0_PROPERTIES { 76 | CONFIG.TX_LINE_RATE 2.43168 77 | CONFIG.TX_PLL_TYPE QPLL1 78 | CONFIG.TX_QPLL_FRACN_NUMERATOR 4211215 79 | CONFIG.TX_REFCLK_FREQUENCY 156.2500001 80 | 81 | CONFIG.RX_LINE_RATE 2.43168 82 | CONFIG.RX_PLL_TYPE QPLL1 83 | CONFIG.RX_QPLL_FRACN_NUMERATOR 4211215 84 | CONFIG.RX_REFCLK_FREQUENCY 156.2500001 85 | }] 86 | } 87 | "1920x1080@120" - 88 | "3840x2160@30" { 89 | set GTWIZARD0_PROPERTIES [concat $GTWIZARD0_PROPERTIES { 90 | CONFIG.TX_LINE_RATE 2.97 91 | CONFIG.TX_PLL_TYPE QPLL0 92 | CONFIG.TX_QPLL_FRACN_NUMERATOR 536870 93 | CONFIG.TX_REFCLK_FREQUENCY 156.2500001 94 | 95 | CONFIG.RX_LINE_RATE 2.97 96 | CONFIG.RX_PLL_TYPE QPLL0 97 | CONFIG.RX_QPLL_FRACN_NUMERATOR 536870 98 | CONFIG.RX_REFCLK_FREQUENCY 156.2500001 99 | }] 100 | } 101 | "1920x1080@144" { 102 | set GTWIZARD0_PROPERTIES [concat $GTWIZARD0_PROPERTIES { 103 | CONFIG.TX_LINE_RATE 3.564 104 | CONFIG.TX_PLL_TYPE QPLL0 105 | CONFIG.TX_QPLL_FRACN_NUMERATOR 3999688 106 | CONFIG.TX_REFCLK_FREQUENCY 156.25 107 | 108 | CONFIG.RX_LINE_RATE 3.564 109 | CONFIG.RX_PLL_TYPE QPLL0 110 | CONFIG.RX_QPLL_FRACN_NUMERATOR 3999688 111 | CONFIG.RX_REFCLK_FREQUENCY 156.25 112 | }] 113 | } 114 | "2560x1440@120" { 115 | set GTWIZARD0_PROPERTIES [concat $GTWIZARD0_PROPERTIES { 116 | CONFIG.TX_LINE_RATE 4.86336 117 | CONFIG.TX_PLL_TYPE QPLL1 118 | CONFIG.TX_QPLL_FRACN_NUMERATOR 4211215 119 | CONFIG.TX_REFCLK_FREQUENCY 156.2500001 120 | 121 | CONFIG.RX_LINE_RATE 4.86336 122 | CONFIG.RX_PLL_TYPE QPLL1 123 | CONFIG.RX_QPLL_FRACN_NUMERATOR 4211215 124 | CONFIG.RX_REFCLK_FREQUENCY 156.2500001 125 | }] 126 | } 127 | "2560x1440@144" { 128 | set GTWIZARD0_PROPERTIES [concat $GTWIZARD0_PROPERTIES { 129 | CONFIG.TX_LINE_RATE 5.836032 130 | CONFIG.TX_PLL_TYPE QPLL0 131 | CONFIG.TX_QPLL_FRACN_NUMERATOR 11764344 132 | CONFIG.TX_REFCLK_FREQUENCY 156.2500001 133 | 134 | CONFIG.RX_LINE_RATE 5.836032 135 | CONFIG.RX_PLL_TYPE QPLL0 136 | CONFIG.RX_QPLL_FRACN_NUMERATOR 11764344 137 | CONFIG.RX_REFCLK_FREQUENCY 156.2500001 138 | }] 139 | } 140 | "1920x1080@240" - 141 | "3840x2160@60" { 142 | set GTWIZARD0_PROPERTIES [concat $GTWIZARD0_PROPERTIES { 143 | CONFIG.TX_LINE_RATE 5.94 144 | CONFIG.TX_PLL_TYPE QPLL0 145 | CONFIG.TX_QPLL_FRACN_NUMERATOR 536870 146 | CONFIG.TX_REFCLK_FREQUENCY 156.2500001 147 | 148 | CONFIG.RX_LINE_RATE 5.94 149 | CONFIG.RX_PLL_TYPE QPLL0 150 | CONFIG.RX_QPLL_FRACN_NUMERATOR 536870 151 | CONFIG.RX_REFCLK_FREQUENCY 156.2500001 152 | }] 153 | } 154 | default { 155 | error "Invalid video mode $RESOLUTION@$REFRESH_RATE" 156 | } 157 | } 158 | 159 | set_property -dict $GTWIZARD0_PROPERTIES [get_ips GTWizard0] 160 | -------------------------------------------------------------------------------- /QSFP-HDMI-OUT-NB7NQ621M/examples/BoChenJingXin-KU5P/scripts/IP/MMCM0.tcl: -------------------------------------------------------------------------------- 1 | create_ip -module_name MMCM0 -vendor xilinx.com -library ip -name clk_wiz -version 6.0 2 | 3 | set_property -dict { 4 | CONFIG.PRIMITIVE MMCM 5 | CONFIG.PRIMARY_PORT clk_in1 6 | CONFIG.PRIM_IN_FREQ 50.000 7 | CONFIG.PRIM_SOURCE Single_ended_clock_capable_pin 8 | 9 | CONFIG.NUM_OUT_CLKS 2 10 | 11 | CONFIG.CLKOUT1_USED true 12 | CONFIG.CLK_OUT1_PORT clk_out1 13 | CONFIG.CLKOUT1_REQUESTED_OUT_FREQ 200.000 14 | CONFIG.CLKOUT1_DRIVES BUFG 15 | 16 | CONFIG.CLKOUT2_USED true 17 | CONFIG.CLK_OUT2_PORT clk_out2 18 | CONFIG.CLKOUT2_REQUESTED_OUT_FREQ 10.000 19 | CONFIG.CLKOUT2_DRIVES BUFG 20 | } [get_ips MMCM0] 21 | -------------------------------------------------------------------------------- /QSFP-HDMI-OUT-NB7NQ621M/examples/BoChenJingXin-KU5P/sources/GTWizardWrapper.v: -------------------------------------------------------------------------------- 1 | module GTWizardWrapper0( 2 | input clock, 3 | input reset, 4 | 5 | input refclk_p, 6 | input refclk_n, 7 | input [3:0] rxp, 8 | input [3:0] rxn, 9 | output [3:0] txp, 10 | output [3:0] txn, 11 | 12 | output tx_clock, 13 | output tx_reset, 14 | input [159:0] tx_data 15 | ); 16 | 17 | wire refclk; 18 | 19 | IBUFDS_GTE4 ibufds_gte4 ( 20 | .O (refclk), 21 | .ODIV2 (), 22 | .CEB (0), 23 | .I (refclk_p), 24 | .IB (refclk_n) 25 | ); 26 | 27 | wire userclk_tx_reset; 28 | wire userclk_tx_usrclk2; 29 | wire userclk_tx_active; 30 | wire buffbypass_tx_reset; 31 | wire buffbypass_tx_done; 32 | wire buffbypass_tx_error; 33 | wire reset_tx_done; 34 | wire [3:0] txpmaresetdone; 35 | wire [3:0] txprgdivresetdone; 36 | 37 | GTWizard0 gt_wizard( 38 | .gtwiz_userclk_tx_reset_in (userclk_tx_reset), 39 | .gtwiz_userclk_tx_srcclk_out (), 40 | .gtwiz_userclk_tx_usrclk_out (), 41 | .gtwiz_userclk_tx_usrclk2_out (userclk_tx_usrclk2), 42 | .gtwiz_userclk_tx_active_out (userclk_tx_active), 43 | .gtwiz_userclk_rx_reset_in (1), 44 | .gtwiz_userclk_rx_srcclk_out (), 45 | .gtwiz_userclk_rx_usrclk_out (), 46 | .gtwiz_userclk_rx_usrclk2_out (), 47 | .gtwiz_userclk_rx_active_out (), 48 | .gtwiz_buffbypass_tx_reset_in (buffbypass_tx_reset), 49 | .gtwiz_buffbypass_tx_start_user_in (0), 50 | .gtwiz_buffbypass_tx_done_out (buffbypass_tx_done), 51 | .gtwiz_buffbypass_tx_error_out (buffbypass_tx_error), 52 | .gtwiz_reset_clk_freerun_in (clock), 53 | .gtwiz_reset_all_in (reset), 54 | .gtwiz_reset_tx_pll_and_datapath_in (0), 55 | .gtwiz_reset_tx_datapath_in (0), 56 | .gtwiz_reset_rx_pll_and_datapath_in (0), 57 | .gtwiz_reset_rx_datapath_in (0), 58 | .gtwiz_reset_rx_cdr_stable_out (), 59 | .gtwiz_reset_tx_done_out (reset_tx_done), 60 | .gtwiz_reset_rx_done_out (), 61 | .gtwiz_userdata_tx_in (tx_data), 62 | .gtwiz_userdata_rx_out (), 63 | .gtrefclk00_in (refclk), 64 | .gtrefclk01_in (refclk), 65 | .qpll0outclk_out (), 66 | .qpll0outrefclk_out (), 67 | .qpll1outclk_out (), 68 | .qpll1outrefclk_out (), 69 | .gtyrxn_in (rxn), 70 | .gtyrxp_in (rxp), 71 | .gtpowergood_out (), 72 | .gtytxn_out (txn), 73 | .gtytxp_out (txp), 74 | .rxpmaresetdone_out (), 75 | .txpmaresetdone_out (txpmaresetdone), 76 | .txprgdivresetdone_out (txprgdivresetdone) 77 | ); 78 | 79 | assign userclk_tx_reset = ~(&txpmaresetdone & &txprgdivresetdone); 80 | 81 | reg [2:0] buffbypass_tx_reset_reg; 82 | always @(posedge userclk_tx_usrclk2) begin 83 | if (~userclk_tx_active) begin 84 | buffbypass_tx_reset_reg <= 5; 85 | end else begin 86 | if (buffbypass_tx_reset_reg != 0) 87 | buffbypass_tx_reset_reg <= buffbypass_tx_reset_reg - 1; 88 | end 89 | end 90 | assign buffbypass_tx_reset = buffbypass_tx_reset_reg != 0; 91 | 92 | assign tx_clock = userclk_tx_usrclk2; 93 | assign tx_reset = reset | ~reset_tx_done | ~buffbypass_tx_done; 94 | 95 | endmodule 96 | -------------------------------------------------------------------------------- /QSFP-HDMI-OUT-NB7NQ621M/examples/BoChenJingXin-KU5P/sources/Top.v: -------------------------------------------------------------------------------- 1 | `ifndef RESOLUTION 2 | `define RESOLUTION "1920x1080" 3 | `endif 4 | `ifndef REFRESH_RATE 5 | `define REFRESH_RATE 60 6 | `endif 7 | 8 | 9 | module Top( 10 | input clock_50, 11 | 12 | input [1:0] key, 13 | output [5:0] led, 14 | 15 | input qsfp_refclk_p, 16 | input qsfp_refclk_n, 17 | input [3:0] qsfp_rxp, 18 | input [3:0] qsfp_rxn, 19 | output [3:0] qsfp_txp, 20 | output [3:0] qsfp_txn, 21 | input qsfp_modprsl, 22 | output qsfp_resetl, 23 | inout qsfp_scl, 24 | inout qsfp_sda 25 | ); 26 | 27 | localparam CLOCK_FREQUENCY = 200_000_000; 28 | 29 | 30 | wire system_reset_input = ~key[0]; 31 | 32 | wire system_clock; 33 | wire gt_config_clock; 34 | wire mmcm0_locked; 35 | 36 | MMCM0 mmcm0( 37 | .clk_in1 (clock_50), 38 | .reset (system_reset_input), 39 | .clk_out1 (system_clock), 40 | .clk_out2 (gt_config_clock), 41 | .locked (mmcm0_locked) 42 | ); 43 | 44 | 45 | wire system_reset = ~mmcm0_locked; 46 | 47 | wire tx_clock; 48 | wire tx_reset; 49 | wire [159:0] tx_data; 50 | 51 | GTWizardWrapper0 gt_wizard_wrapper_0( 52 | .clock (gt_config_clock), 53 | .reset (system_reset), 54 | 55 | .refclk_p (qsfp_refclk_p), 56 | .refclk_n (qsfp_refclk_n), 57 | .rxp (qsfp_rxp), 58 | .rxn (qsfp_rxn), 59 | .txp (qsfp_txp), 60 | .txn (qsfp_txn), 61 | 62 | .tx_clock (tx_clock), 63 | .tx_reset (tx_reset), 64 | .tx_data (tx_data) 65 | ); 66 | 67 | 68 | wire qsfp_scl_input; 69 | wire qsfp_scl_output; 70 | wire qsfp_sda_input; 71 | wire qsfp_sda_output; 72 | 73 | IOBUF qsfp_scl_iobuf( 74 | .O (qsfp_scl_input), 75 | .I (qsfp_scl_output), 76 | .IO (qsfp_scl), 77 | .T (qsfp_scl_output) 78 | ); 79 | IOBUF qsfp_sda_iobuf( 80 | .O (qsfp_sda_input), 81 | .I (qsfp_sda_output), 82 | .IO (qsfp_sda), 83 | .T (qsfp_sda_output) 84 | ); 85 | 86 | wire hpd = ~qsfp_modprsl; 87 | wire run; 88 | 89 | HDMIOUTExample #( 90 | .CLOCK_FREQUENCY (CLOCK_FREQUENCY), 91 | .RESOLUTION (`RESOLUTION), 92 | .REFRESH_RATE (`REFRESH_RATE) 93 | ) hdmi_out_example( 94 | .system_clock (system_clock), 95 | .system_reset (system_reset), 96 | .tx_clock (tx_clock), 97 | .tx_reset (tx_reset), 98 | .tx_data (tx_data), 99 | .hpd (hpd), 100 | .scl_input (qsfp_scl_input), 101 | .scl_output (qsfp_scl_output), 102 | .sda_input (qsfp_sda_input), 103 | .sda_output (qsfp_sda_output), 104 | .i2c_request (), 105 | .i2c_grant (1'b1), 106 | .run (run) 107 | ); 108 | 109 | assign qsfp_resetl = ~system_reset; 110 | 111 | assign led = { 112 | ~system_reset & run, 113 | ~system_reset & hpd & ~run, 114 | ~system_reset 115 | }; 116 | 117 | endmodule 118 | -------------------------------------------------------------------------------- /QSFP-HDMI-OUT-NB7NQ621M/examples/Longs-Peak/build.py: -------------------------------------------------------------------------------- 1 | import argparse 2 | import os 3 | import shutil 4 | import subprocess 5 | 6 | MILL = os.getenv('MILL', shutil.which('mill')) 7 | OPENOCD = shutil.which('openocd') 8 | QUARTUS_SH = shutil.which('quartus_sh') 9 | QUARTUS_CPF = shutil.which('quartus_cpf') 10 | QSYS_SCRIPT = shutil.which('qsys-script') 11 | 12 | RESOLUTION_LIST = [ 13 | '1920x1080', 14 | '2560x1440', 15 | '3840x2160', 16 | ] 17 | REFRESH_RATE_LIST = [ 18 | '30', 19 | '60', 20 | '120', 21 | '144', 22 | '240', 23 | ] 24 | 25 | PROJECT_PATH = os.path.dirname(os.path.realpath(__file__)) 26 | COMMON_PATH = os.path.join(PROJECT_PATH, '..', '..', '..', 'common') 27 | COMMON_CHISEL_PATH = os.path.join(COMMON_PATH, 'Chisel') 28 | SCRIPTS_PATH = os.path.join(PROJECT_PATH, 'scripts') 29 | CONFIG_PATH = os.path.join(SCRIPTS_PATH, 'Config.tcl') 30 | BUILD_PATH = os.path.join(PROJECT_PATH, 'build') 31 | IP_PATH = os.path.join(BUILD_PATH, 'ip') 32 | GENERATED_PATH = os.path.join(BUILD_PATH, 'generated') 33 | BITSTREAM_PATH = os.path.join(BUILD_PATH, 'bitstream') 34 | 35 | def runCommand(command, **kwargs): 36 | print(command) 37 | subprocess.run(command, check = True, **kwargs) 38 | 39 | if __name__ == "__main__": 40 | parser = argparse.ArgumentParser() 41 | parser.add_argument('command', choices = ['build', 'program']) 42 | parser.add_argument('--resolution', choices = RESOLUTION_LIST, default = '1920x1080') 43 | parser.add_argument('--refresh-rate', choices = REFRESH_RATE_LIST, default = '60') 44 | parser.add_argument('-j', '--jobs', default = '8') 45 | args = parser.parse_args() 46 | 47 | RESOLUTION = args.resolution 48 | REFRESH_RATE = args.refresh_rate 49 | JOBS = args.jobs 50 | 51 | PROJECT_NAME = 'Longs-Peak-Example' 52 | 53 | if args.command == 'build': 54 | os.makedirs(GENERATED_PATH, exist_ok = True) 55 | runCommand([ MILL, 'hdmioutexample.run', '-o', os.path.join(GENERATED_PATH, 'HDMIOutExample.sv') ], cwd = COMMON_CHISEL_PATH) 56 | 57 | runCommand([ QSYS_SCRIPT, f'''--script={ os.path.join(SCRIPTS_PATH, 'CreateIP.tcl') }''', IP_PATH, RESOLUTION, REFRESH_RATE ], cwd = BUILD_PATH) 58 | 59 | runCommand([ QUARTUS_SH, '-t', os.path.join(SCRIPTS_PATH, 'CreateProject.tcl'), JOBS, RESOLUTION, REFRESH_RATE ], cwd = BUILD_PATH) 60 | 61 | runCommand([ QUARTUS_SH, '--flow', 'compile', PROJECT_NAME ], cwd = BUILD_PATH) 62 | 63 | os.makedirs(BITSTREAM_PATH, exist_ok = True) 64 | shutil.copy(os.path.join(BUILD_PATH, 'output', f'{ PROJECT_NAME }.sof'), os.path.join(BITSTREAM_PATH, f'{ PROJECT_NAME }.sof')) 65 | 66 | runCommand([ QUARTUS_CPF, '--convert', '--frequency=30MHz', '--voltage=2.5', '--operation=p', os.path.join(BITSTREAM_PATH, f'{ PROJECT_NAME }.sof'), os.path.join(BITSTREAM_PATH, f'{ PROJECT_NAME }.svf') ], cwd = PROJECT_PATH) 67 | elif args.command == 'program': 68 | svfPath = os.path.join(BITSTREAM_PATH, f'{ PROJECT_NAME }.svf') 69 | svfPathEscaped = svfPath.replace('\\', '\\\\') 70 | runCommand([ OPENOCD, '--file', '../../../common/OpenOCD/Longs-Peak/Config.cfg', '--command', f'svf -tap 10AXF40AA.tap "{ svfPathEscaped }"; exit' ], cwd = PROJECT_PATH) 71 | else: 72 | assert False 73 | -------------------------------------------------------------------------------- /QSFP-HDMI-OUT-NB7NQ621M/examples/Longs-Peak/constraints/Timing.sdc: -------------------------------------------------------------------------------- 1 | create_clock -name clock_100 -period 5 [get_ports clock_100] 2 | 3 | create_clock -name qsfp_refclk -period 1.551 [get_ports qsfp_refclk] 4 | 5 | # System clock frequency = 200MHz 6 | create_clock -name system_clock -period 5 [get_pins pll0|inst|altera_iopll_i|twentynm_pll|iopll_inst|outclk[0]] 7 | 8 | # Maximum TX clock frequency = 6GHz / 40 bits per clock = 150MHz 9 | create_clock -name tx_clock -period 6.666 [get_pins xcvr_wrapper_0|xcvr|inst|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs|sta_tx_clk2_by2_1_out] 10 | 11 | set_clock_groups -asynchronous \ 12 | -group system_clock \ 13 | -group tx_clock 14 | 15 | derive_pll_clocks 16 | derive_clock_uncertainty 17 | -------------------------------------------------------------------------------- /QSFP-HDMI-OUT-NB7NQ621M/examples/Longs-Peak/scripts/CreateIP.tcl: -------------------------------------------------------------------------------- 1 | package require -exact qsys 14.0 2 | 3 | set SYSTEM_PATH [lindex $argv 0] 4 | set RESOLUTION [lindex $argv 1] 5 | set REFRESH_RATE [lindex $argv 2] 6 | 7 | set_project_property DEVICE_FAMILY "Arria 10" 8 | set_project_property DEVICE 10AXF40AA 9 | 10 | # TODO: Support data rate below 1.0Gbps 11 | # "1920x1080@30" { 12 | # set XCVR0_DATA_RATE 742.5 13 | # set XCVRFPLL0_OUTPUT_CLOCK_FREQUENCY 371.25 14 | # } 15 | 16 | switch "$RESOLUTION@$REFRESH_RATE" { 17 | "2560x1440@30" { 18 | set XCVR0_DATA_RATE 1215.84 19 | set XCVRFPLL0_OUTPUT_CLOCK_FREQUENCY 607.92 20 | } 21 | "1920x1080@60" { 22 | set XCVR0_DATA_RATE 1485 23 | set XCVRFPLL0_OUTPUT_CLOCK_FREQUENCY 742.5 24 | } 25 | "2560x1440@60" { 26 | set XCVR0_DATA_RATE 2431.68 27 | set XCVRFPLL0_OUTPUT_CLOCK_FREQUENCY 1215.84 28 | } 29 | "1920x1080@120" - 30 | "3840x2160@30" { 31 | set XCVR0_DATA_RATE 2970 32 | set XCVRFPLL0_OUTPUT_CLOCK_FREQUENCY 1485 33 | } 34 | "1920x1080@144" { 35 | set XCVR0_DATA_RATE 3564 36 | set XCVRFPLL0_OUTPUT_CLOCK_FREQUENCY 1782 37 | } 38 | "2560x1440@120" { 39 | set XCVR0_DATA_RATE 4863.36 40 | set XCVRFPLL0_OUTPUT_CLOCK_FREQUENCY 2431.68 41 | } 42 | "2560x1440@144" { 43 | set XCVR0_DATA_RATE 5836.032 44 | set XCVRFPLL0_OUTPUT_CLOCK_FREQUENCY 2918.016 45 | } 46 | "1920x1080@240" - 47 | "3840x2160@60" { 48 | set XCVR0_DATA_RATE 5940 49 | set XCVRFPLL0_OUTPUT_CLOCK_FREQUENCY 2970 50 | } 51 | default { 52 | error "Invalid video mode $RESOLUTION@$REFRESH_RATE" 53 | } 54 | } 55 | 56 | foreach ip [glob ../scripts/IP/*.tcl] { 57 | source $ip 58 | } 59 | -------------------------------------------------------------------------------- /QSFP-HDMI-OUT-NB7NQ621M/examples/Longs-Peak/scripts/CreateProject.tcl: -------------------------------------------------------------------------------- 1 | set JOBS [lindex $argv 0] 2 | set RESOLUTION [lindex $argv 1] 3 | set REFRESH_RATE [lindex $argv 2] 4 | 5 | project_new Longs-Peak-Example -overwrite 6 | 7 | set_global_assignment -name FAMILY "Arria 10" 8 | set_global_assignment -name DEVICE 10AXF40AA 9 | 10 | set_global_assignment -name NUM_PARALLEL_PROCESSORS $JOBS 11 | 12 | set_global_assignment -name VERILOG_MACRO RESOLUTION="$RESOLUTION" 13 | set_global_assignment -name VERILOG_MACRO REFRESH_RATE=$REFRESH_RATE 14 | 15 | set_global_assignment -name TOP_LEVEL_ENTITY Top 16 | 17 | set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output 18 | 19 | set_global_assignment -name PROJECT_IP_REGENERATION_POLICY ALWAYS_REGENERATE_IP 20 | 21 | set_global_assignment -name AUTO_RESERVE_CLKUSR_FOR_CALIBRATION OFF 22 | set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO" 23 | 24 | foreach ip [glob ip/*.qsys] { 25 | set_global_assignment -name QSYS_FILE $ip 26 | } 27 | 28 | foreach v [glob ../../../../common/Verilog/*/*.v] { 29 | set_global_assignment -name VERILOG_FILE $v 30 | } 31 | 32 | foreach sv [glob generated/*.sv] { 33 | set_global_assignment -name SYSTEMVERILOG_FILE $sv 34 | } 35 | 36 | foreach v [glob ../sources/*.v] { 37 | set_global_assignment -name VERILOG_FILE $v 38 | } 39 | 40 | foreach tcl [glob ../../../../common/Quartus/constraints/Longs-Peak/*.tcl] { 41 | source $tcl 42 | } 43 | 44 | foreach sdc [glob ../constraints/*.sdc] { 45 | set_global_assignment -name SDC_FILE $sdc 46 | } 47 | -------------------------------------------------------------------------------- /QSFP-HDMI-OUT-NB7NQ621M/examples/Longs-Peak/scripts/IP/PLL0.tcl: -------------------------------------------------------------------------------- 1 | create_system PLL0 2 | 3 | add_instance inst altera_iopll 4 | set_instance_property inst AUTO_EXPORT true 5 | 6 | set_instance_parameter_value inst gui_reference_clock_frequency 100.0 7 | set_instance_parameter_value inst gui_output_clock_frequency0 200.0 8 | 9 | set_instance_parameter_value inst gui_pll_auto_reset true 10 | 11 | save_system $SYSTEM_PATH/PLL0.qsys 12 | -------------------------------------------------------------------------------- /QSFP-HDMI-OUT-NB7NQ621M/examples/Longs-Peak/scripts/IP/XCVR0.tcl: -------------------------------------------------------------------------------- 1 | create_system XCVR0 2 | 3 | add_instance inst altera_xcvr_native_a10 4 | set_instance_property inst AUTO_EXPORT true 5 | 6 | set_instance_parameter_value inst design_environment NATIVE 7 | 8 | # Datapath Options 9 | set_instance_parameter_value inst duplex_mode tx 10 | set_instance_parameter_value inst channels 4 11 | set_instance_parameter_value inst set_data_rate $XCVR0_DATA_RATE 12 | set_instance_parameter_value inst enable_simple_interface 1 13 | 14 | # Standard PCS 15 | set_instance_parameter_value inst std_pcs_pma_width 20 16 | set_instance_parameter_value inst std_tx_byte_ser_mode "Serialize x2" 17 | 18 | save_system $SYSTEM_PATH/XCVR0.qsys 19 | -------------------------------------------------------------------------------- /QSFP-HDMI-OUT-NB7NQ621M/examples/Longs-Peak/scripts/IP/XCVRFPLL0.tcl: -------------------------------------------------------------------------------- 1 | create_system XCVRFPLL0 2 | 3 | add_instance inst altera_xcvr_fpll_a10 4 | set_instance_property inst AUTO_EXPORT true 5 | 6 | # General 7 | set_instance_parameter_value inst gui_enable_fractional 1 8 | 9 | # Reference Clock 10 | set_instance_parameter_value inst gui_desired_refclk_frequency 644.53125 11 | 12 | # Settings 13 | set_instance_parameter_value inst gui_bw_sel low 14 | 15 | # Output Frequency 16 | set_instance_parameter_value inst gui_hssi_output_clock_frequency $XCVRFPLL0_OUTPUT_CLOCK_FREQUENCY 17 | 18 | save_system $SYSTEM_PATH/XCVRFPLL0.qsys 19 | -------------------------------------------------------------------------------- /QSFP-HDMI-OUT-NB7NQ621M/examples/Longs-Peak/scripts/IP/XCVRReset0.tcl: -------------------------------------------------------------------------------- 1 | create_system XCVRReset0 2 | 3 | add_instance inst altera_xcvr_reset_control 4 | set_instance_property inst AUTO_EXPORT true 5 | 6 | # General Options 7 | set_instance_parameter_value inst CHANNELS 4 8 | set_instance_parameter_value inst PLLS 1 9 | set_instance_parameter_value inst SYS_CLK_IN_MHZ 200 10 | 11 | # TX PLL 12 | set_instance_parameter_value inst TX_PLL_ENABLE 1 13 | 14 | # TX Channel 15 | set_instance_parameter_value inst TX_ENABLE 1 16 | set_instance_parameter_value inst T_TX_ANALOGRESET 70000 17 | set_instance_parameter_value inst T_TX_DIGITALRESET 70000 18 | 19 | # RX Channel 20 | set_instance_parameter_value inst RX_ENABLE 0 21 | 22 | save_system $SYSTEM_PATH/XCVRReset0.qsys 23 | -------------------------------------------------------------------------------- /QSFP-HDMI-OUT-NB7NQ621M/examples/Longs-Peak/sources/Arbiter.v: -------------------------------------------------------------------------------- 1 | module Arbiter #( 2 | parameter REQUEST_COUNT = 0 3 | ) ( 4 | input clock, 5 | input reset, 6 | 7 | input [REQUEST_COUNT - 1:0] request, 8 | output [REQUEST_COUNT - 1:0] grant 9 | ); 10 | 11 | reg [REQUEST_COUNT - 1:0] grant_reg; 12 | 13 | always @(posedge clock) begin 14 | if (reset) 15 | grant_reg <= 0; 16 | else begin 17 | if ((request & grant_reg) == 0) 18 | grant_reg <= request & -request; 19 | end 20 | end 21 | 22 | assign grant = grant_reg; 23 | 24 | endmodule 25 | -------------------------------------------------------------------------------- /QSFP-HDMI-OUT-NB7NQ621M/examples/Longs-Peak/sources/DS250DF810.v: -------------------------------------------------------------------------------- 1 | module DS250DF810 #( 2 | parameter CLOCK_FREQUENCY = 0 3 | ) ( 4 | input clock, 5 | input reset, 6 | 7 | input scl_input, 8 | output scl_output, 9 | input sda_input, 10 | output sda_output, 11 | 12 | output i2c_request, 13 | input i2c_grant, 14 | 15 | output ready 16 | ); 17 | 18 | localparam 19 | STATE_RESET = 0, 20 | STATE_WRITE_START = 1, 21 | STATE_WRITE_WAIT = 2, 22 | STATE_READY = 3; 23 | 24 | localparam DS250DF810_ADDRESS = 7'h22; 25 | 26 | localparam DATA_COUNT = 4; 27 | 28 | function [15:0] DATA( 29 | input [2:0] index 30 | ); 31 | case (index) 32 | 0: DATA = { 8'hFC, 8'h0F }; // EN_CH = 0b00001111 33 | 1: DATA = { 8'hFF, 8'h01 }; // EN_SHARE_Q1 = 0, EN_SHARE_Q0 = 0, WRITE_ALL_CH = 0, EN_CH_SMB = 1 34 | 2: DATA = { 8'h00, 8'h04 }; // RST_REGS = 1 35 | 3: DATA = { 8'h1E, 8'h09 }; // PFD_SEL_DATA_MUX = 0b000 36 | default: DATA = 16'h0; 37 | endcase 38 | endfunction 39 | 40 | 41 | wire i2c_valid; 42 | reg i2c_ready; 43 | reg [7:0] i2c_register; 44 | reg [7:0] i2c_data_write; 45 | wire i2c_nack; 46 | 47 | I2CMaster #(.CLOCK_FREQUENCY (CLOCK_FREQUENCY), .FREQUENCY(100_000)) i2c_master( 48 | .clock (clock), 49 | .reset (reset), 50 | 51 | .scl_input (scl_input), 52 | .scl_output (scl_output), 53 | .sda_input (sda_input), 54 | .sda_output (sda_output), 55 | 56 | .request (i2c_request), 57 | .grant (i2c_grant), 58 | 59 | .valid (i2c_valid), 60 | .ready (i2c_ready), 61 | .address (DS250DF810_ADDRESS), 62 | .rw (1'b0), 63 | .register (i2c_register), 64 | .data_write (i2c_data_write), 65 | .nack (i2c_nack), 66 | .data_read () 67 | ); 68 | 69 | 70 | reg [2:0] data_index; 71 | wire [15:0] data = DATA(data_index); 72 | 73 | reg [1:0] state; 74 | 75 | always @(posedge clock) begin 76 | if (reset) begin 77 | i2c_ready <= 0; 78 | state <= STATE_RESET; 79 | end else begin 80 | case (state) 81 | STATE_RESET: begin 82 | data_index <= 0; 83 | state <= STATE_WRITE_START; 84 | end 85 | STATE_WRITE_START: begin 86 | i2c_ready <= 1; 87 | i2c_register <= data[15:8]; 88 | i2c_data_write <= data[7:0]; 89 | state <= STATE_WRITE_WAIT; 90 | end 91 | STATE_WRITE_WAIT: begin 92 | if (i2c_valid) begin 93 | i2c_ready <= 0; 94 | if (i2c_nack) begin 95 | state <= STATE_RESET; 96 | end else begin 97 | if (data_index != DATA_COUNT - 1) begin 98 | data_index <= data_index + 1; 99 | state <= STATE_WRITE_START; 100 | end else begin 101 | state <= STATE_READY; 102 | end 103 | end 104 | end 105 | end 106 | endcase 107 | end 108 | end 109 | 110 | assign ready = state == STATE_READY; 111 | 112 | endmodule 113 | -------------------------------------------------------------------------------- /QSFP-HDMI-OUT-NB7NQ621M/examples/Longs-Peak/sources/Top.v: -------------------------------------------------------------------------------- 1 | `ifndef RESOLUTION 2 | `define RESOLUTION "1920x1080" 3 | `endif 4 | `ifndef REFRESH_RATE 5 | `define REFRESH_RATE 60 6 | `endif 7 | 8 | 9 | module Top( 10 | input clock_100, 11 | 12 | output [8:0] led, 13 | 14 | input qsfp_refclk, 15 | 16 | output [3:0] qsfp_tx, 17 | inout qsfp_scl, 18 | inout qsfp_sda, 19 | input qsfp_modprsl 20 | ); 21 | 22 | localparam CLOCK_FREQUENCY = 200_000_000; 23 | 24 | 25 | reg [2:0] system_reset_input_reg = 3'b111; 26 | wire system_reset_input = system_reset_input_reg[0]; 27 | 28 | always @(posedge clock_100) begin 29 | system_reset_input_reg <= system_reset_input_reg >> 1; 30 | end 31 | 32 | wire system_clock; 33 | wire pll0_locked; 34 | 35 | PLL0 pll0 ( 36 | .refclk (clock_100), 37 | .rst (system_reset_input), 38 | .outclk_0 (system_clock), 39 | .locked (pll0_locked) 40 | ); 41 | 42 | reg [2:0] system_reset_reg; 43 | 44 | always @(posedge system_clock) begin 45 | if (~pll0_locked) begin 46 | system_reset_reg <= 3'b111; 47 | end else begin 48 | system_reset_reg <= system_reset_reg >> 1; 49 | end 50 | end 51 | 52 | wire system_reset = system_reset_reg[0]; 53 | 54 | 55 | wire tx_clock; 56 | wire tx_reset; 57 | wire [159:0] tx_data; 58 | 59 | XCVRWrapper0 xcvr_wrapper_0( 60 | .clock (system_clock), 61 | .reset (system_reset), 62 | 63 | .refclk (qsfp_refclk), 64 | .tx (qsfp_tx), 65 | 66 | .tx_clock (tx_clock), 67 | .tx_reset (tx_reset), 68 | .tx_data (tx_data) 69 | ); 70 | 71 | 72 | wire qsfp_scl_input; 73 | wire [1:0] qsfp_scl_output; 74 | wire qsfp_sda_input; 75 | wire [1:0] qsfp_sda_output; 76 | 77 | alt_iobuf qsfp_scl_iobuf( 78 | .I (&qsfp_scl_output), 79 | .OE (~&qsfp_scl_output), 80 | .O (qsfp_scl_input), 81 | .IO (qsfp_scl) 82 | ); 83 | alt_iobuf qsfp_sda_iobuf( 84 | .I (&qsfp_sda_output), 85 | .OE (~&qsfp_sda_output), 86 | .O (qsfp_sda_input), 87 | .IO (qsfp_sda) 88 | ); 89 | 90 | wire [1:0] qsfp_i2c_request; 91 | wire [1:0] qsfp_i2c_grant; 92 | 93 | Arbiter #( 94 | .REQUEST_COUNT (2) 95 | ) arbiter ( 96 | .clock (system_clock), 97 | .reset (system_reset), 98 | 99 | .request (qsfp_i2c_request), 100 | .grant (qsfp_i2c_grant) 101 | ); 102 | 103 | wire ds250df810_ready; 104 | 105 | DS250DF810 #( 106 | .CLOCK_FREQUENCY (CLOCK_FREQUENCY) 107 | ) ds250df810 ( 108 | .clock (system_clock), 109 | .reset (system_reset), 110 | 111 | .scl_input (qsfp_scl_input), 112 | .scl_output (qsfp_scl_output[0]), 113 | .sda_input (qsfp_sda_input), 114 | .sda_output (qsfp_sda_output[0]), 115 | 116 | .i2c_request (qsfp_i2c_request[0]), 117 | .i2c_grant (qsfp_i2c_grant[0]), 118 | 119 | .ready (ds250df810_ready) 120 | ); 121 | 122 | wire hpd = ~qsfp_modprsl; 123 | wire run; 124 | 125 | HDMIOUTExample #( 126 | .CLOCK_FREQUENCY (CLOCK_FREQUENCY), 127 | .RESOLUTION (`RESOLUTION), 128 | .REFRESH_RATE (`REFRESH_RATE) 129 | ) hdmi_out_example( 130 | .system_clock (system_clock), 131 | .system_reset (system_reset), 132 | .tx_clock (tx_clock), 133 | .tx_reset (tx_reset), 134 | .tx_data (tx_data), 135 | .hpd (hpd), 136 | .scl_input (qsfp_scl_input), 137 | .scl_output (qsfp_scl_output[1]), 138 | .sda_input (qsfp_sda_input), 139 | .sda_output (qsfp_sda_output[1]), 140 | .i2c_request (qsfp_i2c_request[1]), 141 | .i2c_grant (qsfp_i2c_grant[1]), 142 | .run (run) 143 | ); 144 | 145 | assign led = { 146 | ~system_reset & run, 147 | ~system_reset & hpd & ~run, 148 | ~system_reset 149 | }; 150 | 151 | endmodule 152 | -------------------------------------------------------------------------------- /QSFP-HDMI-OUT-NB7NQ621M/examples/Longs-Peak/sources/XCVRWrapper.v: -------------------------------------------------------------------------------- 1 | module XCVRWrapper0( 2 | input clock, 3 | input reset, 4 | 5 | input refclk, 6 | output [3:0] tx, 7 | 8 | output tx_clock, 9 | output tx_reset, 10 | input [159:0] tx_data 11 | ); 12 | 13 | wire pll_powerdown; 14 | wire [3:0] tx_analogreset; 15 | wire [3:0] tx_digitalreset; 16 | wire [3:0] tx_ready; 17 | wire pll_locked; 18 | wire [3:0] tx_cal_busy; 19 | 20 | wire tx_serial_clk; 21 | wire [3:0] tx_clocks; 22 | 23 | XCVRReset0 xcvr_reset( 24 | .clock (clock), 25 | .reset (reset), 26 | .pll_powerdown (pll_powerdown), 27 | .tx_analogreset (tx_analogreset), 28 | .tx_digitalreset (tx_digitalreset), 29 | .tx_ready (tx_ready), 30 | .pll_locked (pll_locked), 31 | .pll_select (1'b0), 32 | .tx_cal_busy (tx_cal_busy) 33 | ); 34 | 35 | XCVRFPLL0 xcvr_fpll( 36 | .pll_refclk0 (refclk), 37 | .pll_powerdown (pll_powerdown), 38 | .pll_locked (pll_locked), 39 | .tx_serial_clk (tx_serial_clk), 40 | .pll_cal_busy () 41 | ); 42 | 43 | XCVR0 xcvr( 44 | .tx_analogreset (tx_analogreset), 45 | .tx_digitalreset (tx_digitalreset), 46 | .tx_cal_busy (tx_cal_busy), 47 | .tx_serial_clk0 ({ 4 { tx_serial_clk } }), 48 | .tx_serial_data (tx), 49 | .tx_coreclkin ({ 4 { tx_clock } }), 50 | .tx_clkout (tx_clocks), 51 | .tx_parallel_data (tx_data), 52 | .unused_tx_parallel_data (352'b0) 53 | ); 54 | 55 | assign tx_clock = tx_clocks[1]; 56 | assign tx_reset = ~&tx_ready; 57 | 58 | endmodule 59 | -------------------------------------------------------------------------------- /QSFP-HDMI-OUT-NB7NQ621M/examples/MLK-H8-CU06-KU5P/build.py: -------------------------------------------------------------------------------- 1 | import argparse 2 | import os 3 | import shutil 4 | import subprocess 5 | 6 | VIVADO = os.getenv('VIVADO', shutil.which('vivado')) 7 | MILL = os.getenv('MILL', shutil.which('mill')) 8 | 9 | RESOLUTION_LIST = [ 10 | '1920x1080', 11 | '2560x1440', 12 | '3840x2160', 13 | ] 14 | REFRESH_RATE_LIST = [ 15 | '30', 16 | '60', 17 | '120', 18 | '144', 19 | '240', 20 | ] 21 | 22 | PROJECT_PATH = os.path.dirname(os.path.realpath(__file__)) 23 | COMMON_PATH = os.path.join(PROJECT_PATH, '..', '..', '..', 'common') 24 | COMMON_CHISEL_PATH = os.path.join(COMMON_PATH, 'Chisel') 25 | COMMON_SCRIPTS_PATH = os.path.join(COMMON_PATH, 'Vivado', 'scripts') 26 | SCRIPTS_PATH = os.path.join(PROJECT_PATH, 'scripts') 27 | CONFIG_PATH = os.path.join(SCRIPTS_PATH, 'Config.tcl') 28 | BUILD_PATH = os.path.join(PROJECT_PATH, 'build') 29 | GENERATED_PATH = os.path.join(BUILD_PATH, 'generated') 30 | BITSTREAM_PATH = os.path.join(BUILD_PATH, 'bitstream') 31 | 32 | def runCommand(command, **kwargs): 33 | print(command) 34 | subprocess.run(command, check = True, **kwargs) 35 | 36 | def runVivadoScript(script, *args): 37 | runCommand([VIVADO, '-nojournal', '-nolog', '-mode', 'batch', '-source', script, '-tclargs', *args], cwd = BUILD_PATH) 38 | 39 | if __name__ == "__main__": 40 | parser = argparse.ArgumentParser() 41 | parser.add_argument('command', choices = ['build', 'program', 'flash']) 42 | parser.add_argument('--resolution', choices = RESOLUTION_LIST, default = '1920x1080') 43 | parser.add_argument('--refresh-rate', choices = REFRESH_RATE_LIST, default = '60') 44 | parser.add_argument('-j', '--jobs', default = '8') 45 | args = parser.parse_args() 46 | 47 | RESOLUTION = args.resolution 48 | REFRESH_RATE = args.refresh_rate 49 | JOBS = args.jobs 50 | 51 | if args.command == 'build': 52 | os.makedirs(GENERATED_PATH, exist_ok = True) 53 | runCommand([MILL, 'hdmioutexample.run', '-o', os.path.join(GENERATED_PATH, 'HDMIOutExample.sv')], cwd = COMMON_CHISEL_PATH) 54 | 55 | runVivadoScript(os.path.join(SCRIPTS_PATH, 'CreateProject.tcl'), RESOLUTION, REFRESH_RATE) 56 | runVivadoScript(os.path.join(COMMON_SCRIPTS_PATH, 'Synthesis.tcl'), CONFIG_PATH, JOBS) 57 | runVivadoScript(os.path.join(COMMON_SCRIPTS_PATH, 'Implementation.tcl'), CONFIG_PATH, JOBS) 58 | runVivadoScript(os.path.join(COMMON_SCRIPTS_PATH, 'GenerateBitstream.tcl'), CONFIG_PATH, BITSTREAM_PATH) 59 | elif args.command == 'program': 60 | runVivadoScript(os.path.join(COMMON_SCRIPTS_PATH, 'Program.tcl'), CONFIG_PATH, BITSTREAM_PATH) 61 | elif args.command == 'flash': 62 | runVivadoScript(os.path.join(COMMON_SCRIPTS_PATH, 'Flash.tcl'), CONFIG_PATH, BITSTREAM_PATH) 63 | else: 64 | assert False 65 | -------------------------------------------------------------------------------- /QSFP-HDMI-OUT-NB7NQ621M/examples/MLK-H8-CU06-KU5P/constraints/Timing.xdc: -------------------------------------------------------------------------------- 1 | # System clock frequency = 200MHz 2 | create_clock -name system_clock -period 5 -quiet [get_nets system_clock] 3 | 4 | # Maximum TX clock frequency = 6GHz / 40 bits per clock = 150MHz 5 | create_clock -name tx_clock -period 6.666 -quiet [get_nets tx_clock] 6 | 7 | set_clock_groups -asynchronous \ 8 | -group system_clock \ 9 | -group tx_clock 10 | -------------------------------------------------------------------------------- /QSFP-HDMI-OUT-NB7NQ621M/examples/MLK-H8-CU06-KU5P/scripts/Config.tcl: -------------------------------------------------------------------------------- 1 | set PROJECT_NAME MLK-H8-CU06-KU5P-Example 2 | 3 | set TOP_NAME Top 4 | 5 | set PART_NAME xcku5p-ffvb676-2-i 6 | 7 | set HW_DEVICE_NAME xcku5p_0 8 | set CFGMEM_PART_NAME mt25qu256-spi-x1_x2_x4 9 | -------------------------------------------------------------------------------- /QSFP-HDMI-OUT-NB7NQ621M/examples/MLK-H8-CU06-KU5P/scripts/CreateProject.tcl: -------------------------------------------------------------------------------- 1 | set RESOLUTION [lindex $argv 0] 2 | set REFRESH_RATE [lindex $argv 1] 3 | 4 | set PROJECT_PATH [file normalize [file dirname [info script]]/..] 5 | 6 | source $PROJECT_PATH/scripts/Config.tcl 7 | 8 | create_project -force -part $PART_NAME $PROJECT_NAME 9 | 10 | source $PROJECT_PATH/scripts/IP/GTWizard0.tcl 11 | source $PROJECT_PATH/scripts/IP/MMCM0.tcl 12 | 13 | set_property VERILOG_DEFINE [list \ 14 | RESOLUTION="$RESOLUTION" \ 15 | REFRESH_RATE=$REFRESH_RATE \ 16 | ] [get_filesets sources_1] 17 | 18 | set_property top $TOP_NAME [current_fileset] 19 | 20 | add_files -fileset sources_1 \ 21 | [glob $PROJECT_PATH/../../../common/Verilog/*/*.v] \ 22 | [glob $PROJECT_PATH/build/generated/*.sv] \ 23 | [glob $PROJECT_PATH/sources/*.v] 24 | 25 | add_files -fileset constrs_1 \ 26 | [glob $PROJECT_PATH/../../../common/Vivado/constraints/MLK-H8-CU06-KU5P/*.xdc] \ 27 | [glob $PROJECT_PATH/constraints/*.xdc] 28 | -------------------------------------------------------------------------------- /QSFP-HDMI-OUT-NB7NQ621M/examples/MLK-H8-CU06-KU5P/scripts/IP/GTWizard0.tcl: -------------------------------------------------------------------------------- 1 | create_ip -module_name GTWizard0 -vendor xilinx.com -library ip -name gtwizard_ultrascale -version 1.7 2 | 3 | set GTWIZARD0_PROPERTIES {} 4 | 5 | set GTWIZARD0_PROPERTIES [concat $GTWIZARD0_PROPERTIES { 6 | CONFIG.preset GTY-HDMI 7 | 8 | CONFIG.TX_USER_DATA_WIDTH 40 9 | CONFIG.TX_INT_DATA_WIDTH 40 10 | 11 | CONFIG.RX_USER_DATA_WIDTH 40 12 | CONFIG.RX_INT_DATA_WIDTH 40 13 | 14 | CONFIG.FREERUN_FREQUENCY 10.0 15 | 16 | CONFIG.CHANNEL_ENABLE { X0Y7 X0Y6 X0Y5 X0Y4 } 17 | CONFIG.TX_MASTER_CHANNEL X0Y5 18 | CONFIG.RX_MASTER_CHANNEL X0Y5 19 | 20 | CONFIG.TX_REFCLK_SOURCE { X0Y7 clk1 X0Y6 clk1 X0Y5 clk1 X0Y4 clk1 } 21 | CONFIG.RX_REFCLK_SOURCE { X0Y7 clk1 X0Y6 clk1 X0Y5 clk1 X0Y4 clk1 } 22 | 23 | CONFIG.LOCATE_TX_USER_CLOCKING CORE 24 | CONFIG.LOCATE_RX_USER_CLOCKING CORE 25 | 26 | CONFIG.ENABLE_OPTIONAL_PORTS { 27 | gtrefclk00_in 28 | gtrefclk01_in 29 | 30 | qpll0outclk_out 31 | qpll0outrefclk_out 32 | qpll1outclk_out 33 | qpll1outrefclk_out 34 | } 35 | }] 36 | 37 | switch "$RESOLUTION@$REFRESH_RATE" { 38 | "1920x1080@30" { 39 | set GTWIZARD0_PROPERTIES [concat $GTWIZARD0_PROPERTIES { 40 | CONFIG.TX_LINE_RATE 0.7425 41 | CONFIG.TX_PLL_TYPE QPLL0 42 | CONFIG.TX_QPLL_FRACN_NUMERATOR 536870 43 | CONFIG.TX_REFCLK_FREQUENCY 156.2500001 44 | 45 | CONFIG.RX_LINE_RATE 0.7425 46 | CONFIG.RX_PLL_TYPE QPLL0 47 | CONFIG.RX_QPLL_FRACN_NUMERATOR 536870 48 | CONFIG.RX_REFCLK_FREQUENCY 156.2500001 49 | }] 50 | } 51 | "2560x1440@30" { 52 | set GTWIZARD0_PROPERTIES [concat $GTWIZARD0_PROPERTIES { 53 | CONFIG.TX_LINE_RATE 1.21584 54 | CONFIG.TX_PLL_TYPE QPLL1 55 | CONFIG.TX_QPLL_FRACN_NUMERATOR 4211215 56 | CONFIG.TX_REFCLK_FREQUENCY 156.2500001 57 | 58 | CONFIG.RX_LINE_RATE 1.21584 59 | CONFIG.RX_PLL_TYPE QPLL1 60 | CONFIG.RX_QPLL_FRACN_NUMERATOR 4211215 61 | CONFIG.RX_REFCLK_FREQUENCY 156.2500001 62 | }] 63 | } 64 | "1920x1080@60" { 65 | set GTWIZARD0_PROPERTIES [concat $GTWIZARD0_PROPERTIES { 66 | CONFIG.TX_LINE_RATE 1.485 67 | CONFIG.TX_PLL_TYPE QPLL0 68 | CONFIG.TX_QPLL_FRACN_NUMERATOR 536870 69 | CONFIG.TX_REFCLK_FREQUENCY 156.2500001 70 | 71 | CONFIG.RX_LINE_RATE 1.485 72 | CONFIG.RX_PLL_TYPE QPLL0 73 | CONFIG.RX_QPLL_FRACN_NUMERATOR 536870 74 | CONFIG.RX_REFCLK_FREQUENCY 156.2500001 75 | }] 76 | } 77 | "2560x1440@60" { 78 | set GTWIZARD0_PROPERTIES [concat $GTWIZARD0_PROPERTIES { 79 | CONFIG.TX_LINE_RATE 2.43168 80 | CONFIG.TX_PLL_TYPE QPLL1 81 | CONFIG.TX_QPLL_FRACN_NUMERATOR 4211215 82 | CONFIG.TX_REFCLK_FREQUENCY 156.2500001 83 | 84 | CONFIG.RX_LINE_RATE 2.43168 85 | CONFIG.RX_PLL_TYPE QPLL1 86 | CONFIG.RX_QPLL_FRACN_NUMERATOR 4211215 87 | CONFIG.RX_REFCLK_FREQUENCY 156.2500001 88 | }] 89 | } 90 | "1920x1080@120" - 91 | "3840x2160@30" { 92 | set GTWIZARD0_PROPERTIES [concat $GTWIZARD0_PROPERTIES { 93 | CONFIG.TX_LINE_RATE 2.97 94 | CONFIG.TX_PLL_TYPE QPLL0 95 | CONFIG.TX_QPLL_FRACN_NUMERATOR 536870 96 | CONFIG.TX_REFCLK_FREQUENCY 156.2500001 97 | 98 | CONFIG.RX_LINE_RATE 2.97 99 | CONFIG.RX_PLL_TYPE QPLL0 100 | CONFIG.RX_QPLL_FRACN_NUMERATOR 536870 101 | CONFIG.RX_REFCLK_FREQUENCY 156.2500001 102 | }] 103 | } 104 | "1920x1080@144" { 105 | set GTWIZARD0_PROPERTIES [concat $GTWIZARD0_PROPERTIES { 106 | CONFIG.TX_LINE_RATE 3.564 107 | CONFIG.TX_PLL_TYPE QPLL0 108 | CONFIG.TX_QPLL_FRACN_NUMERATOR 3999688 109 | CONFIG.TX_REFCLK_FREQUENCY 156.25 110 | 111 | CONFIG.RX_LINE_RATE 3.564 112 | CONFIG.RX_PLL_TYPE QPLL0 113 | CONFIG.RX_QPLL_FRACN_NUMERATOR 3999688 114 | CONFIG.RX_REFCLK_FREQUENCY 156.25 115 | }] 116 | } 117 | "2560x1440@120" { 118 | set GTWIZARD0_PROPERTIES [concat $GTWIZARD0_PROPERTIES { 119 | CONFIG.TX_LINE_RATE 4.86336 120 | CONFIG.TX_PLL_TYPE QPLL1 121 | CONFIG.TX_QPLL_FRACN_NUMERATOR 4211215 122 | CONFIG.TX_REFCLK_FREQUENCY 156.2500001 123 | 124 | CONFIG.RX_LINE_RATE 4.86336 125 | CONFIG.RX_PLL_TYPE QPLL1 126 | CONFIG.RX_QPLL_FRACN_NUMERATOR 4211215 127 | CONFIG.RX_REFCLK_FREQUENCY 156.2500001 128 | }] 129 | } 130 | "2560x1440@144" { 131 | set GTWIZARD0_PROPERTIES [concat $GTWIZARD0_PROPERTIES { 132 | CONFIG.TX_LINE_RATE 5.836032 133 | CONFIG.TX_PLL_TYPE QPLL0 134 | CONFIG.TX_QPLL_FRACN_NUMERATOR 11764344 135 | CONFIG.TX_REFCLK_FREQUENCY 156.2500001 136 | 137 | CONFIG.RX_LINE_RATE 5.836032 138 | CONFIG.RX_PLL_TYPE QPLL0 139 | CONFIG.RX_QPLL_FRACN_NUMERATOR 11764344 140 | CONFIG.RX_REFCLK_FREQUENCY 156.2500001 141 | }] 142 | } 143 | "1920x1080@240" - 144 | "3840x2160@60" { 145 | set GTWIZARD0_PROPERTIES [concat $GTWIZARD0_PROPERTIES { 146 | CONFIG.TX_LINE_RATE 5.94 147 | CONFIG.TX_PLL_TYPE QPLL0 148 | CONFIG.TX_QPLL_FRACN_NUMERATOR 536870 149 | CONFIG.TX_REFCLK_FREQUENCY 156.2500001 150 | 151 | CONFIG.RX_LINE_RATE 5.94 152 | CONFIG.RX_PLL_TYPE QPLL0 153 | CONFIG.RX_QPLL_FRACN_NUMERATOR 536870 154 | CONFIG.RX_REFCLK_FREQUENCY 156.2500001 155 | }] 156 | } 157 | default { 158 | error "Invalid video mode $RESOLUTION@$REFRESH_RATE" 159 | } 160 | } 161 | 162 | set_property -dict $GTWIZARD0_PROPERTIES [get_ips GTWizard0] 163 | -------------------------------------------------------------------------------- /QSFP-HDMI-OUT-NB7NQ621M/examples/MLK-H8-CU06-KU5P/scripts/IP/MMCM0.tcl: -------------------------------------------------------------------------------- 1 | create_ip -module_name MMCM0 -vendor xilinx.com -library ip -name clk_wiz -version 6.0 2 | 3 | set_property -dict { 4 | CONFIG.PRIMITIVE MMCM 5 | CONFIG.PRIMARY_PORT clk_in1 6 | CONFIG.PRIM_IN_FREQ 100.000 7 | CONFIG.PRIM_SOURCE Differential_clock_capable_pin 8 | 9 | CONFIG.NUM_OUT_CLKS 2 10 | 11 | CONFIG.CLKOUT1_USED true 12 | CONFIG.CLK_OUT1_PORT clk_out1 13 | CONFIG.CLKOUT1_REQUESTED_OUT_FREQ 200.000 14 | CONFIG.CLKOUT1_DRIVES BUFG 15 | 16 | CONFIG.CLKOUT2_USED true 17 | CONFIG.CLK_OUT2_PORT clk_out2 18 | CONFIG.CLKOUT2_REQUESTED_OUT_FREQ 10.000 19 | CONFIG.CLKOUT2_DRIVES BUFG 20 | } [get_ips MMCM0] 21 | -------------------------------------------------------------------------------- /QSFP-HDMI-OUT-NB7NQ621M/examples/MLK-H8-CU06-KU5P/sources/GTWizardWrapper.v: -------------------------------------------------------------------------------- 1 | module GTWizardWrapper0( 2 | input clock, 3 | input reset, 4 | 5 | input refclk_p, 6 | input refclk_n, 7 | input [3:0] rxp, 8 | input [3:0] rxn, 9 | output [3:0] txp, 10 | output [3:0] txn, 11 | 12 | output tx_clock, 13 | output tx_reset, 14 | input [159:0] tx_data 15 | ); 16 | 17 | wire refclk; 18 | 19 | IBUFDS_GTE4 ibufds_gte4 ( 20 | .O (refclk), 21 | .ODIV2 (), 22 | .CEB (0), 23 | .I (refclk_p), 24 | .IB (refclk_n) 25 | ); 26 | 27 | wire userclk_tx_reset; 28 | wire userclk_tx_usrclk2; 29 | wire userclk_tx_active; 30 | wire buffbypass_tx_reset; 31 | wire buffbypass_tx_done; 32 | wire buffbypass_tx_error; 33 | wire reset_tx_done; 34 | wire [3:0] txpmaresetdone; 35 | wire [3:0] txprgdivresetdone; 36 | 37 | GTWizard0 gt_wizard( 38 | .gtwiz_userclk_tx_reset_in (userclk_tx_reset), 39 | .gtwiz_userclk_tx_srcclk_out (), 40 | .gtwiz_userclk_tx_usrclk_out (), 41 | .gtwiz_userclk_tx_usrclk2_out (userclk_tx_usrclk2), 42 | .gtwiz_userclk_tx_active_out (userclk_tx_active), 43 | .gtwiz_userclk_rx_reset_in (1), 44 | .gtwiz_userclk_rx_srcclk_out (), 45 | .gtwiz_userclk_rx_usrclk_out (), 46 | .gtwiz_userclk_rx_usrclk2_out (), 47 | .gtwiz_userclk_rx_active_out (), 48 | .gtwiz_buffbypass_tx_reset_in (buffbypass_tx_reset), 49 | .gtwiz_buffbypass_tx_start_user_in (0), 50 | .gtwiz_buffbypass_tx_done_out (buffbypass_tx_done), 51 | .gtwiz_buffbypass_tx_error_out (buffbypass_tx_error), 52 | .gtwiz_reset_clk_freerun_in (clock), 53 | .gtwiz_reset_all_in (reset), 54 | .gtwiz_reset_tx_pll_and_datapath_in (0), 55 | .gtwiz_reset_tx_datapath_in (0), 56 | .gtwiz_reset_rx_pll_and_datapath_in (0), 57 | .gtwiz_reset_rx_datapath_in (0), 58 | .gtwiz_reset_rx_cdr_stable_out (), 59 | .gtwiz_reset_tx_done_out (reset_tx_done), 60 | .gtwiz_reset_rx_done_out (), 61 | .gtwiz_userdata_tx_in (tx_data), 62 | .gtwiz_userdata_rx_out (), 63 | .gtrefclk00_in (refclk), 64 | .gtrefclk01_in (refclk), 65 | .qpll0outclk_out (), 66 | .qpll0outrefclk_out (), 67 | .qpll1outclk_out (), 68 | .qpll1outrefclk_out (), 69 | .gtyrxn_in (rxn), 70 | .gtyrxp_in (rxp), 71 | .gtpowergood_out (), 72 | .gtytxn_out (txn), 73 | .gtytxp_out (txp), 74 | .rxpmaresetdone_out (), 75 | .txpmaresetdone_out (txpmaresetdone), 76 | .txprgdivresetdone_out (txprgdivresetdone) 77 | ); 78 | 79 | assign userclk_tx_reset = ~(&txpmaresetdone & &txprgdivresetdone); 80 | 81 | reg [2:0] buffbypass_tx_reset_reg; 82 | always @(posedge userclk_tx_usrclk2) begin 83 | if (~userclk_tx_active) begin 84 | buffbypass_tx_reset_reg <= 5; 85 | end else begin 86 | if (buffbypass_tx_reset_reg != 0) 87 | buffbypass_tx_reset_reg <= buffbypass_tx_reset_reg - 1; 88 | end 89 | end 90 | assign buffbypass_tx_reset = buffbypass_tx_reset_reg != 0; 91 | 92 | assign tx_clock = userclk_tx_usrclk2; 93 | assign tx_reset = reset | ~reset_tx_done | ~buffbypass_tx_done; 94 | 95 | endmodule 96 | -------------------------------------------------------------------------------- /QSFP-HDMI-OUT-NB7NQ621M/examples/MLK-H8-CU06-KU5P/sources/Top.v: -------------------------------------------------------------------------------- 1 | `ifndef RESOLUTION 2 | `define RESOLUTION "1920x1080" 3 | `endif 4 | `ifndef REFRESH_RATE 5 | `define REFRESH_RATE 60 6 | `endif 7 | 8 | 9 | module Top( 10 | input clock_100_p, 11 | input clock_100_n, 12 | 13 | input [1:0] key, 14 | output [1:0] led, 15 | 16 | input qsfp_refclk_p, 17 | input qsfp_refclk_n, 18 | input [3:0] qsfp_rxp, 19 | input [3:0] qsfp_rxn, 20 | output [3:0] qsfp_txp, 21 | output [3:0] qsfp_txn, 22 | input qsfp_modprsl, 23 | output qsfp_resetl, 24 | inout qsfp_scl, 25 | inout qsfp_sda 26 | ); 27 | 28 | localparam CLOCK_FREQUENCY = 200_000_000; 29 | 30 | 31 | wire system_reset_input = ~key[0]; 32 | 33 | wire system_clock; 34 | wire gt_config_clock; 35 | wire mmcm0_locked; 36 | 37 | MMCM0 mmcm0( 38 | .clk_in1_p (clock_100_p), 39 | .clk_in1_n (clock_100_n), 40 | .reset (system_reset_input), 41 | .clk_out1 (system_clock), 42 | .clk_out2 (gt_config_clock), 43 | .locked (mmcm0_locked) 44 | ); 45 | 46 | 47 | wire system_reset = ~mmcm0_locked; 48 | 49 | wire tx_clock; 50 | wire tx_reset; 51 | wire [159:0] tx_data; 52 | 53 | GTWizardWrapper0 gt_wizard_wrapper_0( 54 | .clock (gt_config_clock), 55 | .reset (system_reset), 56 | 57 | .refclk_p (qsfp_refclk_p), 58 | .refclk_n (qsfp_refclk_n), 59 | .rxp (qsfp_rxp), 60 | .rxn (qsfp_rxn), 61 | .txp (qsfp_txp), 62 | .txn (qsfp_txn), 63 | 64 | .tx_clock (tx_clock), 65 | .tx_reset (tx_reset), 66 | .tx_data (tx_data) 67 | ); 68 | 69 | 70 | wire qsfp_scl_input; 71 | wire qsfp_scl_output; 72 | wire qsfp_sda_input; 73 | wire qsfp_sda_output; 74 | 75 | IOBUF qsfp_scl_iobuf( 76 | .O (qsfp_scl_input), 77 | .I (qsfp_scl_output), 78 | .IO (qsfp_scl), 79 | .T (qsfp_scl_output) 80 | ); 81 | IOBUF qsfp_sda_iobuf( 82 | .O (qsfp_sda_input), 83 | .I (qsfp_sda_output), 84 | .IO (qsfp_sda), 85 | .T (qsfp_sda_output) 86 | ); 87 | 88 | wire hpd = ~qsfp_modprsl; 89 | wire run; 90 | 91 | HDMIOUTExample #( 92 | .CLOCK_FREQUENCY (CLOCK_FREQUENCY), 93 | .RESOLUTION (`RESOLUTION), 94 | .REFRESH_RATE (`REFRESH_RATE) 95 | ) hdmi_out_example( 96 | .system_clock (system_clock), 97 | .system_reset (system_reset), 98 | .tx_clock (tx_clock), 99 | .tx_reset (tx_reset), 100 | .tx_data (tx_data), 101 | .hpd (hpd), 102 | .scl_input (qsfp_scl_input), 103 | .scl_output (qsfp_scl_output), 104 | .sda_input (qsfp_sda_input), 105 | .sda_output (qsfp_sda_output), 106 | .i2c_request (), 107 | .i2c_grant (1'b1), 108 | .run (run) 109 | ); 110 | 111 | assign qsfp_resetl = ~system_reset; 112 | 113 | assign led = { 114 | ~system_reset & run, 115 | ~system_reset & hpd & ~run 116 | }; 117 | 118 | endmodule 119 | -------------------------------------------------------------------------------- /QSFP-HDMI-OUT-NB7NQ621M/examples/RK-XCKU5P-F/build.py: -------------------------------------------------------------------------------- 1 | import argparse 2 | import os 3 | import shutil 4 | import subprocess 5 | 6 | VIVADO = os.getenv('VIVADO', shutil.which('vivado')) 7 | MILL = os.getenv('MILL', shutil.which('mill')) 8 | 9 | RESOLUTION_LIST = [ 10 | '1920x1080', 11 | '2560x1440', 12 | '3840x2160', 13 | ] 14 | REFRESH_RATE_LIST = [ 15 | '30', 16 | '60', 17 | '120', 18 | '144', 19 | '240', 20 | ] 21 | 22 | PROJECT_PATH = os.path.dirname(os.path.realpath(__file__)) 23 | COMMON_PATH = os.path.join(PROJECT_PATH, '..', '..', '..', 'common') 24 | COMMON_CHISEL_PATH = os.path.join(COMMON_PATH, 'Chisel') 25 | COMMON_SCRIPTS_PATH = os.path.join(COMMON_PATH, 'Vivado', 'scripts') 26 | SCRIPTS_PATH = os.path.join(PROJECT_PATH, 'scripts') 27 | CONFIG_PATH = os.path.join(SCRIPTS_PATH, 'Config.tcl') 28 | BUILD_PATH = os.path.join(PROJECT_PATH, 'build') 29 | GENERATED_PATH = os.path.join(BUILD_PATH, 'generated') 30 | BITSTREAM_PATH = os.path.join(BUILD_PATH, 'bitstream') 31 | 32 | def runCommand(command, **kwargs): 33 | print(command) 34 | subprocess.run(command, check = True, **kwargs) 35 | 36 | def runVivadoScript(script, *args): 37 | runCommand([VIVADO, '-nojournal', '-nolog', '-mode', 'batch', '-source', script, '-tclargs', *args], cwd = BUILD_PATH) 38 | 39 | if __name__ == "__main__": 40 | parser = argparse.ArgumentParser() 41 | parser.add_argument('command', choices = ['build', 'program', 'flash']) 42 | parser.add_argument('--resolution', choices = RESOLUTION_LIST, default = '1920x1080') 43 | parser.add_argument('--refresh-rate', choices = REFRESH_RATE_LIST, default = '60') 44 | parser.add_argument('-j', '--jobs', default = '8') 45 | args = parser.parse_args() 46 | 47 | RESOLUTION = args.resolution 48 | REFRESH_RATE = args.refresh_rate 49 | JOBS = args.jobs 50 | 51 | if args.command == 'build': 52 | os.makedirs(GENERATED_PATH, exist_ok = True) 53 | runCommand([MILL, 'hdmioutexample.run', '-o', os.path.join(GENERATED_PATH, 'HDMIOutExample.sv')], cwd = COMMON_CHISEL_PATH) 54 | 55 | runVivadoScript(os.path.join(SCRIPTS_PATH, 'CreateProject.tcl'), RESOLUTION, REFRESH_RATE) 56 | runVivadoScript(os.path.join(COMMON_SCRIPTS_PATH, 'Synthesis.tcl'), CONFIG_PATH, JOBS) 57 | runVivadoScript(os.path.join(COMMON_SCRIPTS_PATH, 'Implementation.tcl'), CONFIG_PATH, JOBS) 58 | runVivadoScript(os.path.join(COMMON_SCRIPTS_PATH, 'GenerateBitstream.tcl'), CONFIG_PATH, BITSTREAM_PATH) 59 | elif args.command == 'program': 60 | runVivadoScript(os.path.join(COMMON_SCRIPTS_PATH, 'Program.tcl'), CONFIG_PATH, BITSTREAM_PATH) 61 | elif args.command == 'flash': 62 | runVivadoScript(os.path.join(COMMON_SCRIPTS_PATH, 'Flash.tcl'), CONFIG_PATH, BITSTREAM_PATH) 63 | else: 64 | assert False 65 | -------------------------------------------------------------------------------- /QSFP-HDMI-OUT-NB7NQ621M/examples/RK-XCKU5P-F/constraints/Timing.xdc: -------------------------------------------------------------------------------- 1 | set_property CLOCK_DEDICATED_ROUTE ANY_CMT_COLUMN [get_nets clock_50_bufg_wire] 2 | 3 | # System clock frequency = 200MHz 4 | create_clock -name system_clock -period 5 -quiet [get_nets system_clock] 5 | 6 | # Maximum TX clock frequency = 6GHz / 40 bits per clock = 150MHz 7 | create_clock -name tx_clock -period 6.666 -quiet [get_nets tx_clock] 8 | 9 | set_clock_groups -asynchronous \ 10 | -group system_clock \ 11 | -group tx_clock 12 | -------------------------------------------------------------------------------- /QSFP-HDMI-OUT-NB7NQ621M/examples/RK-XCKU5P-F/scripts/Config.tcl: -------------------------------------------------------------------------------- 1 | set PROJECT_NAME RK-XCKU5P-F-Example 2 | 3 | set TOP_NAME Top 4 | 5 | set PART_NAME xcku5p-ffvb676-2-i 6 | 7 | set HW_DEVICE_NAME xcku5p_0 8 | set CFGMEM_PART_NAME mx25u51245g-spi-x1_x2_x4 9 | -------------------------------------------------------------------------------- /QSFP-HDMI-OUT-NB7NQ621M/examples/RK-XCKU5P-F/scripts/CreateProject.tcl: -------------------------------------------------------------------------------- 1 | set RESOLUTION [lindex $argv 0] 2 | set REFRESH_RATE [lindex $argv 1] 3 | 4 | set PROJECT_PATH [file normalize [file dirname [info script]]/..] 5 | 6 | source $PROJECT_PATH/scripts/Config.tcl 7 | 8 | create_project -force -part $PART_NAME $PROJECT_NAME 9 | 10 | source $PROJECT_PATH/scripts/IP/GTWizard0.tcl 11 | source $PROJECT_PATH/scripts/IP/MMCM0.tcl 12 | 13 | set_property VERILOG_DEFINE [list \ 14 | RESOLUTION="$RESOLUTION" \ 15 | REFRESH_RATE=$REFRESH_RATE \ 16 | ] [get_filesets sources_1] 17 | 18 | set_property top $TOP_NAME [current_fileset] 19 | 20 | add_files -fileset sources_1 \ 21 | [glob $PROJECT_PATH/../../../common/Verilog/*/*.v] \ 22 | [glob $PROJECT_PATH/build/generated/*.sv] \ 23 | [glob $PROJECT_PATH/sources/*.v] 24 | 25 | add_files -fileset constrs_1 \ 26 | [glob $PROJECT_PATH/../../../common/Vivado/constraints/RK-XCKU5P-F/*.xdc] \ 27 | [glob $PROJECT_PATH/constraints/*.xdc] 28 | -------------------------------------------------------------------------------- /QSFP-HDMI-OUT-NB7NQ621M/examples/RK-XCKU5P-F/scripts/IP/GTWizard0.tcl: -------------------------------------------------------------------------------- 1 | create_ip -module_name GTWizard0 -vendor xilinx.com -library ip -name gtwizard_ultrascale -version 1.7 2 | 3 | set GTWIZARD0_PROPERTIES {} 4 | 5 | set GTWIZARD0_PROPERTIES [concat $GTWIZARD0_PROPERTIES { 6 | CONFIG.preset GTY-HDMI 7 | 8 | CONFIG.TX_USER_DATA_WIDTH 40 9 | CONFIG.TX_INT_DATA_WIDTH 40 10 | 11 | CONFIG.RX_USER_DATA_WIDTH 40 12 | CONFIG.RX_INT_DATA_WIDTH 40 13 | 14 | CONFIG.FREERUN_FREQUENCY 10.0 15 | 16 | CONFIG.CHANNEL_ENABLE { X0Y7 X0Y6 X0Y5 X0Y4 } 17 | CONFIG.TX_MASTER_CHANNEL X0Y5 18 | CONFIG.RX_MASTER_CHANNEL X0Y5 19 | 20 | CONFIG.LOCATE_TX_USER_CLOCKING CORE 21 | CONFIG.LOCATE_RX_USER_CLOCKING CORE 22 | 23 | CONFIG.ENABLE_OPTIONAL_PORTS { 24 | gtrefclk00_in 25 | gtrefclk01_in 26 | 27 | qpll0outclk_out 28 | qpll0outrefclk_out 29 | qpll1outclk_out 30 | qpll1outrefclk_out 31 | } 32 | }] 33 | 34 | switch "$RESOLUTION@$REFRESH_RATE" { 35 | "1920x1080@30" { 36 | set GTWIZARD0_PROPERTIES [concat $GTWIZARD0_PROPERTIES { 37 | CONFIG.TX_LINE_RATE 0.7425 38 | CONFIG.TX_PLL_TYPE QPLL0 39 | CONFIG.TX_QPLL_FRACN_NUMERATOR 536870 40 | CONFIG.TX_REFCLK_FREQUENCY 156.2500001 41 | 42 | CONFIG.RX_LINE_RATE 0.7425 43 | CONFIG.RX_PLL_TYPE QPLL0 44 | CONFIG.RX_QPLL_FRACN_NUMERATOR 536870 45 | CONFIG.RX_REFCLK_FREQUENCY 156.2500001 46 | }] 47 | } 48 | "2560x1440@30" { 49 | set GTWIZARD0_PROPERTIES [concat $GTWIZARD0_PROPERTIES { 50 | CONFIG.TX_LINE_RATE 1.21584 51 | CONFIG.TX_PLL_TYPE QPLL1 52 | CONFIG.TX_QPLL_FRACN_NUMERATOR 4211215 53 | CONFIG.TX_REFCLK_FREQUENCY 156.2500001 54 | 55 | CONFIG.RX_LINE_RATE 1.21584 56 | CONFIG.RX_PLL_TYPE QPLL1 57 | CONFIG.RX_QPLL_FRACN_NUMERATOR 4211215 58 | CONFIG.RX_REFCLK_FREQUENCY 156.2500001 59 | }] 60 | } 61 | "1920x1080@60" { 62 | set GTWIZARD0_PROPERTIES [concat $GTWIZARD0_PROPERTIES { 63 | CONFIG.TX_LINE_RATE 1.485 64 | CONFIG.TX_PLL_TYPE QPLL0 65 | CONFIG.TX_QPLL_FRACN_NUMERATOR 536870 66 | CONFIG.TX_REFCLK_FREQUENCY 156.2500001 67 | 68 | CONFIG.RX_LINE_RATE 1.485 69 | CONFIG.RX_PLL_TYPE QPLL0 70 | CONFIG.RX_QPLL_FRACN_NUMERATOR 536870 71 | CONFIG.RX_REFCLK_FREQUENCY 156.2500001 72 | }] 73 | } 74 | "2560x1440@60" { 75 | set GTWIZARD0_PROPERTIES [concat $GTWIZARD0_PROPERTIES { 76 | CONFIG.TX_LINE_RATE 2.43168 77 | CONFIG.TX_PLL_TYPE QPLL1 78 | CONFIG.TX_QPLL_FRACN_NUMERATOR 4211215 79 | CONFIG.TX_REFCLK_FREQUENCY 156.2500001 80 | 81 | CONFIG.RX_LINE_RATE 2.43168 82 | CONFIG.RX_PLL_TYPE QPLL1 83 | CONFIG.RX_QPLL_FRACN_NUMERATOR 4211215 84 | CONFIG.RX_REFCLK_FREQUENCY 156.2500001 85 | }] 86 | } 87 | "1920x1080@120" - 88 | "3840x2160@30" { 89 | set GTWIZARD0_PROPERTIES [concat $GTWIZARD0_PROPERTIES { 90 | CONFIG.TX_LINE_RATE 2.97 91 | CONFIG.TX_PLL_TYPE QPLL0 92 | CONFIG.TX_QPLL_FRACN_NUMERATOR 536870 93 | CONFIG.TX_REFCLK_FREQUENCY 156.2500001 94 | 95 | CONFIG.RX_LINE_RATE 2.97 96 | CONFIG.RX_PLL_TYPE QPLL0 97 | CONFIG.RX_QPLL_FRACN_NUMERATOR 536870 98 | CONFIG.RX_REFCLK_FREQUENCY 156.2500001 99 | }] 100 | } 101 | "1920x1080@144" { 102 | set GTWIZARD0_PROPERTIES [concat $GTWIZARD0_PROPERTIES { 103 | CONFIG.TX_LINE_RATE 3.564 104 | CONFIG.TX_PLL_TYPE QPLL0 105 | CONFIG.TX_QPLL_FRACN_NUMERATOR 3999688 106 | CONFIG.TX_REFCLK_FREQUENCY 156.25 107 | 108 | CONFIG.RX_LINE_RATE 3.564 109 | CONFIG.RX_PLL_TYPE QPLL0 110 | CONFIG.RX_QPLL_FRACN_NUMERATOR 3999688 111 | CONFIG.RX_REFCLK_FREQUENCY 156.25 112 | }] 113 | } 114 | "2560x1440@120" { 115 | set GTWIZARD0_PROPERTIES [concat $GTWIZARD0_PROPERTIES { 116 | CONFIG.TX_LINE_RATE 4.86336 117 | CONFIG.TX_PLL_TYPE QPLL1 118 | CONFIG.TX_QPLL_FRACN_NUMERATOR 4211215 119 | CONFIG.TX_REFCLK_FREQUENCY 156.2500001 120 | 121 | CONFIG.RX_LINE_RATE 4.86336 122 | CONFIG.RX_PLL_TYPE QPLL1 123 | CONFIG.RX_QPLL_FRACN_NUMERATOR 4211215 124 | CONFIG.RX_REFCLK_FREQUENCY 156.2500001 125 | }] 126 | } 127 | "2560x1440@144" { 128 | set GTWIZARD0_PROPERTIES [concat $GTWIZARD0_PROPERTIES { 129 | CONFIG.TX_LINE_RATE 5.836032 130 | CONFIG.TX_PLL_TYPE QPLL0 131 | CONFIG.TX_QPLL_FRACN_NUMERATOR 11764344 132 | CONFIG.TX_REFCLK_FREQUENCY 156.2500001 133 | 134 | CONFIG.RX_LINE_RATE 5.836032 135 | CONFIG.RX_PLL_TYPE QPLL0 136 | CONFIG.RX_QPLL_FRACN_NUMERATOR 11764344 137 | CONFIG.RX_REFCLK_FREQUENCY 156.2500001 138 | }] 139 | } 140 | "1920x1080@240" - 141 | "3840x2160@60" { 142 | set GTWIZARD0_PROPERTIES [concat $GTWIZARD0_PROPERTIES { 143 | CONFIG.TX_LINE_RATE 5.94 144 | CONFIG.TX_PLL_TYPE QPLL0 145 | CONFIG.TX_QPLL_FRACN_NUMERATOR 536870 146 | CONFIG.TX_REFCLK_FREQUENCY 156.2500001 147 | 148 | CONFIG.RX_LINE_RATE 5.94 149 | CONFIG.RX_PLL_TYPE QPLL0 150 | CONFIG.RX_QPLL_FRACN_NUMERATOR 536870 151 | CONFIG.RX_REFCLK_FREQUENCY 156.2500001 152 | }] 153 | } 154 | default { 155 | error "Invalid video mode $RESOLUTION@$REFRESH_RATE" 156 | } 157 | } 158 | 159 | set_property -dict $GTWIZARD0_PROPERTIES [get_ips GTWizard0] 160 | -------------------------------------------------------------------------------- /QSFP-HDMI-OUT-NB7NQ621M/examples/RK-XCKU5P-F/scripts/IP/MMCM0.tcl: -------------------------------------------------------------------------------- 1 | create_ip -module_name MMCM0 -vendor xilinx.com -library ip -name clk_wiz -version 6.0 2 | 3 | set_property -dict { 4 | CONFIG.PRIMITIVE MMCM 5 | CONFIG.PRIMARY_PORT clk_in1 6 | CONFIG.PRIM_IN_FREQ 50.000 7 | CONFIG.PRIM_SOURCE No_buffer 8 | 9 | CONFIG.NUM_OUT_CLKS 2 10 | 11 | CONFIG.CLKOUT1_USED true 12 | CONFIG.CLK_OUT1_PORT clk_out1 13 | CONFIG.CLKOUT1_REQUESTED_OUT_FREQ 200.000 14 | CONFIG.CLKOUT1_DRIVES BUFG 15 | 16 | CONFIG.CLKOUT2_USED true 17 | CONFIG.CLK_OUT2_PORT clk_out2 18 | CONFIG.CLKOUT2_REQUESTED_OUT_FREQ 10.000 19 | CONFIG.CLKOUT2_DRIVES BUFG 20 | } [get_ips MMCM0] 21 | -------------------------------------------------------------------------------- /QSFP-HDMI-OUT-NB7NQ621M/examples/RK-XCKU5P-F/sources/GTWizardWrapper.v: -------------------------------------------------------------------------------- 1 | module GTWizardWrapper0( 2 | input clock, 3 | input reset, 4 | 5 | input refclk_p, 6 | input refclk_n, 7 | input [3:0] rxp, 8 | input [3:0] rxn, 9 | output [3:0] txp, 10 | output [3:0] txn, 11 | 12 | output tx_clock, 13 | output tx_reset, 14 | input [159:0] tx_data 15 | ); 16 | 17 | wire refclk; 18 | 19 | IBUFDS_GTE4 ibufds_gte4 ( 20 | .O (refclk), 21 | .ODIV2 (), 22 | .CEB (0), 23 | .I (refclk_p), 24 | .IB (refclk_n) 25 | ); 26 | 27 | wire userclk_tx_reset; 28 | wire userclk_tx_usrclk2; 29 | wire userclk_tx_active; 30 | wire buffbypass_tx_reset; 31 | wire buffbypass_tx_done; 32 | wire buffbypass_tx_error; 33 | wire reset_tx_done; 34 | wire [3:0] txpmaresetdone; 35 | wire [3:0] txprgdivresetdone; 36 | 37 | GTWizard0 gt_wizard( 38 | .gtwiz_userclk_tx_reset_in (userclk_tx_reset), 39 | .gtwiz_userclk_tx_srcclk_out (), 40 | .gtwiz_userclk_tx_usrclk_out (), 41 | .gtwiz_userclk_tx_usrclk2_out (userclk_tx_usrclk2), 42 | .gtwiz_userclk_tx_active_out (userclk_tx_active), 43 | .gtwiz_userclk_rx_reset_in (1), 44 | .gtwiz_userclk_rx_srcclk_out (), 45 | .gtwiz_userclk_rx_usrclk_out (), 46 | .gtwiz_userclk_rx_usrclk2_out (), 47 | .gtwiz_userclk_rx_active_out (), 48 | .gtwiz_buffbypass_tx_reset_in (buffbypass_tx_reset), 49 | .gtwiz_buffbypass_tx_start_user_in (0), 50 | .gtwiz_buffbypass_tx_done_out (buffbypass_tx_done), 51 | .gtwiz_buffbypass_tx_error_out (buffbypass_tx_error), 52 | .gtwiz_reset_clk_freerun_in (clock), 53 | .gtwiz_reset_all_in (reset), 54 | .gtwiz_reset_tx_pll_and_datapath_in (0), 55 | .gtwiz_reset_tx_datapath_in (0), 56 | .gtwiz_reset_rx_pll_and_datapath_in (0), 57 | .gtwiz_reset_rx_datapath_in (0), 58 | .gtwiz_reset_rx_cdr_stable_out (), 59 | .gtwiz_reset_tx_done_out (reset_tx_done), 60 | .gtwiz_reset_rx_done_out (), 61 | .gtwiz_userdata_tx_in (tx_data), 62 | .gtwiz_userdata_rx_out (), 63 | .gtrefclk00_in (refclk), 64 | .gtrefclk01_in (refclk), 65 | .qpll0outclk_out (), 66 | .qpll0outrefclk_out (), 67 | .qpll1outclk_out (), 68 | .qpll1outrefclk_out (), 69 | .gtyrxn_in (rxn), 70 | .gtyrxp_in (rxp), 71 | .gtpowergood_out (), 72 | .gtytxn_out (txn), 73 | .gtytxp_out (txp), 74 | .rxpmaresetdone_out (), 75 | .txpmaresetdone_out (txpmaresetdone), 76 | .txprgdivresetdone_out (txprgdivresetdone) 77 | ); 78 | 79 | assign userclk_tx_reset = ~(&txpmaresetdone & &txprgdivresetdone); 80 | 81 | reg [2:0] buffbypass_tx_reset_reg; 82 | always @(posedge userclk_tx_usrclk2) begin 83 | if (~userclk_tx_active) begin 84 | buffbypass_tx_reset_reg <= 5; 85 | end else begin 86 | if (buffbypass_tx_reset_reg != 0) 87 | buffbypass_tx_reset_reg <= buffbypass_tx_reset_reg - 1; 88 | end 89 | end 90 | assign buffbypass_tx_reset = buffbypass_tx_reset_reg != 0; 91 | 92 | assign tx_clock = userclk_tx_usrclk2; 93 | assign tx_reset = reset | ~reset_tx_done | ~buffbypass_tx_done; 94 | 95 | endmodule 96 | -------------------------------------------------------------------------------- /QSFP-HDMI-OUT-NB7NQ621M/examples/RK-XCKU5P-F/sources/Top.v: -------------------------------------------------------------------------------- 1 | `ifndef RESOLUTION 2 | `define RESOLUTION "1920x1080" 3 | `endif 4 | `ifndef REFRESH_RATE 5 | `define REFRESH_RATE 60 6 | `endif 7 | 8 | 9 | module Top( 10 | input clock_50, 11 | 12 | input [3:0] key, 13 | output [3:0] led, 14 | 15 | input qsfp_refclk_p, 16 | input qsfp_refclk_n, 17 | input [3:0] qsfp_rxp, 18 | input [3:0] qsfp_rxn, 19 | output [3:0] qsfp_txp, 20 | output [3:0] qsfp_txn, 21 | input qsfp_modprsl, 22 | output qsfp_resetl, 23 | inout qsfp_scl, 24 | inout qsfp_sda 25 | ); 26 | 27 | localparam CLOCK_FREQUENCY = 200_000_000; 28 | 29 | 30 | wire system_reset_input = ~key[0]; 31 | 32 | wire clock_50_bufg_wire; 33 | 34 | BUFG clock_50_bufg( 35 | .O (clock_50_bufg_wire), 36 | .I (clock_50) 37 | ); 38 | 39 | wire system_clock; 40 | wire gt_config_clock; 41 | wire mmcm0_locked; 42 | 43 | MMCM0 mmcm0( 44 | .clk_in1 (clock_50_bufg_wire), 45 | .reset (system_reset_input), 46 | .clk_out1 (system_clock), 47 | .clk_out2 (gt_config_clock), 48 | .locked (mmcm0_locked) 49 | ); 50 | 51 | 52 | wire system_reset = ~mmcm0_locked; 53 | 54 | wire tx_clock; 55 | wire tx_reset; 56 | wire [159:0] tx_data; 57 | 58 | GTWizardWrapper0 gt_wizard_wrapper_0( 59 | .clock (gt_config_clock), 60 | .reset (system_reset), 61 | 62 | .refclk_p (qsfp_refclk_p), 63 | .refclk_n (qsfp_refclk_n), 64 | .rxp (qsfp_rxp), 65 | .rxn (qsfp_rxn), 66 | .txp (qsfp_txp), 67 | .txn (qsfp_txn), 68 | 69 | .tx_clock (tx_clock), 70 | .tx_reset (tx_reset), 71 | .tx_data (tx_data) 72 | ); 73 | 74 | 75 | wire qsfp_scl_input; 76 | wire qsfp_scl_output; 77 | wire qsfp_sda_input; 78 | wire qsfp_sda_output; 79 | 80 | IOBUF qsfp_scl_iobuf( 81 | .O (qsfp_scl_input), 82 | .I (qsfp_scl_output), 83 | .IO (qsfp_scl), 84 | .T (qsfp_scl_output) 85 | ); 86 | IOBUF qsfp_sda_iobuf( 87 | .O (qsfp_sda_input), 88 | .I (qsfp_sda_output), 89 | .IO (qsfp_sda), 90 | .T (qsfp_sda_output) 91 | ); 92 | 93 | wire hpd = ~qsfp_modprsl; 94 | wire run; 95 | 96 | HDMIOUTExample #( 97 | .CLOCK_FREQUENCY (CLOCK_FREQUENCY), 98 | .RESOLUTION (`RESOLUTION), 99 | .REFRESH_RATE (`REFRESH_RATE) 100 | ) hdmi_out_example( 101 | .system_clock (system_clock), 102 | .system_reset (system_reset), 103 | .tx_clock (tx_clock), 104 | .tx_reset (tx_reset), 105 | .tx_data (tx_data), 106 | .hpd (hpd), 107 | .scl_input (qsfp_scl_input), 108 | .scl_output (qsfp_scl_output), 109 | .sda_input (qsfp_sda_input), 110 | .sda_output (qsfp_sda_output), 111 | .i2c_request (), 112 | .i2c_grant (1'b1), 113 | .run (run) 114 | ); 115 | 116 | assign qsfp_resetl = ~system_reset; 117 | 118 | assign led = { 119 | ~system_reset & run, 120 | ~system_reset & hpd & ~run, 121 | ~system_reset 122 | }; 123 | 124 | endmodule 125 | -------------------------------------------------------------------------------- /QSFP-HDMI-OUT-NB7NQ621M/examples/Storey-Peak/build.py: -------------------------------------------------------------------------------- 1 | import argparse 2 | import os 3 | import shutil 4 | import subprocess 5 | 6 | MILL = os.getenv('MILL', shutil.which('mill')) 7 | OPENOCD = shutil.which('openocd') 8 | QUARTUS_SH = shutil.which('quartus_sh') 9 | QUARTUS_CPF = shutil.which('quartus_cpf') 10 | QSYS_SCRIPT = shutil.which('qsys-script') 11 | 12 | RESOLUTION_LIST = [ 13 | '1920x1080', 14 | '2560x1440', 15 | '3840x2160', 16 | ] 17 | REFRESH_RATE_LIST = [ 18 | '30', 19 | '60', 20 | '120', 21 | '144', 22 | '240', 23 | ] 24 | 25 | PROJECT_PATH = os.path.dirname(os.path.realpath(__file__)) 26 | COMMON_PATH = os.path.join(PROJECT_PATH, '..', '..', '..', 'common') 27 | COMMON_CHISEL_PATH = os.path.join(COMMON_PATH, 'Chisel') 28 | SCRIPTS_PATH = os.path.join(PROJECT_PATH, 'scripts') 29 | CONFIG_PATH = os.path.join(SCRIPTS_PATH, 'Config.tcl') 30 | BUILD_PATH = os.path.join(PROJECT_PATH, 'build') 31 | IP_PATH = os.path.join(BUILD_PATH, 'ip') 32 | GENERATED_PATH = os.path.join(BUILD_PATH, 'generated') 33 | BITSTREAM_PATH = os.path.join(BUILD_PATH, 'bitstream') 34 | 35 | def runCommand(command, **kwargs): 36 | print(command) 37 | subprocess.run(command, check = True, **kwargs) 38 | 39 | if __name__ == "__main__": 40 | parser = argparse.ArgumentParser() 41 | parser.add_argument('command', choices = ['build', 'program']) 42 | parser.add_argument('--resolution', choices = RESOLUTION_LIST, default = '1920x1080') 43 | parser.add_argument('--refresh-rate', choices = REFRESH_RATE_LIST, default = '60') 44 | parser.add_argument('-j', '--jobs', default = '8') 45 | args = parser.parse_args() 46 | 47 | RESOLUTION = args.resolution 48 | REFRESH_RATE = args.refresh_rate 49 | JOBS = args.jobs 50 | 51 | PROJECT_NAME = 'Storey-Peak-Example' 52 | 53 | if args.command == 'build': 54 | os.makedirs(GENERATED_PATH, exist_ok = True) 55 | runCommand([MILL, 'hdmioutexample.run', '-o', os.path.join(GENERATED_PATH, 'HDMIOutExample.sv')], cwd = COMMON_CHISEL_PATH) 56 | 57 | runCommand([ QSYS_SCRIPT, f'''--script={ os.path.join(SCRIPTS_PATH, 'CreateIP.tcl') }''', IP_PATH, RESOLUTION, REFRESH_RATE ], cwd = BUILD_PATH) 58 | 59 | runCommand([ QUARTUS_SH, '-t', os.path.join(SCRIPTS_PATH, 'CreateProject.tcl'), JOBS, RESOLUTION, REFRESH_RATE ], cwd = BUILD_PATH) 60 | 61 | runCommand([ QUARTUS_SH, '--flow', 'compile', PROJECT_NAME ], cwd = BUILD_PATH) 62 | 63 | os.makedirs(BITSTREAM_PATH, exist_ok = True) 64 | shutil.copy(os.path.join(BUILD_PATH, 'output', f'{ PROJECT_NAME }.sof'), os.path.join(BITSTREAM_PATH, f'{ PROJECT_NAME }.sof')) 65 | 66 | runCommand([ QUARTUS_CPF, '--convert', '--frequency=30MHz', '--voltage=2.5', '--operation=p', os.path.join(BITSTREAM_PATH, f'{ PROJECT_NAME }.sof'), os.path.join(BITSTREAM_PATH, f'{ PROJECT_NAME }.svf') ], cwd = PROJECT_PATH) 67 | elif args.command == 'program': 68 | svfPath = os.path.join(BITSTREAM_PATH, f'{ PROJECT_NAME }.svf') 69 | svfPathEscaped = svfPath.replace('\\', '\\\\') 70 | runCommand([ OPENOCD, '--file', '../../../common/OpenOCD/Storey-Peak/Config.cfg', '--command', f'"svf -tap 5SGSKF40I3LNAC.tap { svfPathEscaped }; exit"' ], cwd = PROJECT_PATH) 71 | else: 72 | assert False 73 | -------------------------------------------------------------------------------- /QSFP-HDMI-OUT-NB7NQ621M/examples/Storey-Peak/constraints/Timing.sdc: -------------------------------------------------------------------------------- 1 | create_clock -name clock_125 -period 8 [get_ports clock_125] 2 | 3 | # System clock frequency = 200MHz 4 | create_clock -name system_clock -period 5 [get_pins pll0|inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk] 5 | 6 | # Maximum TX clock frequency = 6GHz / 40 bits per clock = 150MHz 7 | create_clock -name tx_clock_0 -period 6.666 [get_pins xcvr_wrapper_0|xcvrs[0].xcvr|inst|gen_native_inst.xcvr_native_insts[0].gen_bonded_group_native.xcvr_native_inst|inst_sv_pcs|ch[1].inst_sv_pcs_ch|inst_sv_hssi_8g_tx_pcs|wys|clkout] 8 | create_clock -name tx_clock_1 -period 6.666 [get_pins xcvr_wrapper_0|xcvrs[1].xcvr|inst|gen_native_inst.xcvr_native_insts[0].gen_bonded_group_native.xcvr_native_inst|inst_sv_pcs|ch[1].inst_sv_pcs_ch|inst_sv_hssi_8g_tx_pcs|wys|clkout] 9 | 10 | set_clock_groups -asynchronous \ 11 | -group system_clock \ 12 | -group tx_clock_0 \ 13 | -group tx_clock_1 14 | 15 | derive_pll_clocks 16 | derive_clock_uncertainty 17 | -------------------------------------------------------------------------------- /QSFP-HDMI-OUT-NB7NQ621M/examples/Storey-Peak/scripts/CreateIP.tcl: -------------------------------------------------------------------------------- 1 | package require -exact qsys 14.0 2 | 3 | set SYSTEM_PATH [lindex $argv 0] 4 | set RESOLUTION [lindex $argv 1] 5 | set REFRESH_RATE [lindex $argv 2] 6 | 7 | set_project_property DEVICE_FAMILY "Stratix V" 8 | set_project_property DEVICE 5SGSMD5K2F40I3L 9 | 10 | switch "$RESOLUTION@$REFRESH_RATE" { 11 | "1920x1080@30" { 12 | set XCVR0_DATA_RATE 742.5 13 | set XCVR0_REFERENCE_CLOCK_FREQUENCY "148.5 MHz" 14 | } 15 | "2560x1440@30" { 16 | set XCVR0_DATA_RATE 1215.84 17 | set XCVR0_REFERENCE_CLOCK_FREQUENCY "121.584 MHz" 18 | } 19 | "1920x1080@60" { 20 | set XCVR0_DATA_RATE 1485 21 | set XCVR0_REFERENCE_CLOCK_FREQUENCY "148.5 MHz" 22 | } 23 | "2560x1440@60" { 24 | set XCVR0_DATA_RATE 2431.68 25 | set XCVR0_REFERENCE_CLOCK_FREQUENCY "121.584 MHz" 26 | } 27 | "1920x1080@120" - 28 | "3840x2160@30" { 29 | set XCVR0_DATA_RATE 2970 30 | set XCVR0_REFERENCE_CLOCK_FREQUENCY "148.5 MHz" 31 | } 32 | "1920x1080@144" { 33 | set XCVR0_DATA_RATE 3564 34 | set XCVR0_REFERENCE_CLOCK_FREQUENCY "148.5 MHz" 35 | } 36 | "2560x1440@120" { 37 | set XCVR0_DATA_RATE 4863.36 38 | set XCVR0_REFERENCE_CLOCK_FREQUENCY "121.584 MHz" 39 | } 40 | "2560x1440@144" { 41 | set XCVR0_DATA_RATE 5836.032 42 | set XCVR0_REFERENCE_CLOCK_FREQUENCY "145.9008 MHz" 43 | } 44 | "1920x1080@240" - 45 | "3840x2160@60" { 46 | set XCVR0_DATA_RATE 5940 47 | set XCVR0_REFERENCE_CLOCK_FREQUENCY "148.5 MHz" 48 | } 49 | default { 50 | error "Invalid video mode $RESOLUTION@$REFRESH_RATE" 51 | } 52 | } 53 | 54 | foreach ip [glob ../scripts/IP/*.tcl] { 55 | source $ip 56 | } 57 | -------------------------------------------------------------------------------- /QSFP-HDMI-OUT-NB7NQ621M/examples/Storey-Peak/scripts/CreateProject.tcl: -------------------------------------------------------------------------------- 1 | set JOBS [lindex $argv 0] 2 | set RESOLUTION [lindex $argv 1] 3 | set REFRESH_RATE [lindex $argv 2] 4 | 5 | project_new Storey-Peak-Example -overwrite 6 | 7 | set_global_assignment -name FAMILY "Stratix V" 8 | set_global_assignment -name DEVICE 5SGSKF40I3LNAC 9 | 10 | set_global_assignment -name NUM_PARALLEL_PROCESSORS $JOBS 11 | 12 | set_global_assignment -name VERILOG_MACRO RESOLUTION="$RESOLUTION" 13 | set_global_assignment -name VERILOG_MACRO REFRESH_RATE=$REFRESH_RATE 14 | 15 | set_global_assignment -name TOP_LEVEL_ENTITY Top 16 | 17 | set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output 18 | 19 | foreach ip [glob ip/*.qsys] { 20 | set_global_assignment -name QSYS_FILE $ip 21 | } 22 | 23 | foreach v [glob ../../../../common/Verilog/*/*.v] { 24 | set_global_assignment -name VERILOG_FILE $v 25 | } 26 | 27 | foreach sv [glob generated/*.sv] { 28 | set_global_assignment -name SYSTEMVERILOG_FILE $sv 29 | } 30 | 31 | foreach v [glob ../sources/*.v] { 32 | set_global_assignment -name VERILOG_FILE $v 33 | } 34 | 35 | foreach tcl [glob ../../../../common/Quartus/constraints/Storey-Peak/*.tcl] { 36 | source $tcl 37 | } 38 | 39 | foreach sdc [glob ../constraints/*.sdc] { 40 | set_global_assignment -name SDC_FILE $sdc 41 | } 42 | -------------------------------------------------------------------------------- /QSFP-HDMI-OUT-NB7NQ621M/examples/Storey-Peak/scripts/IP/PLL0.tcl: -------------------------------------------------------------------------------- 1 | create_system PLL0 2 | 3 | add_instance inst altera_pll 4 | set_instance_property inst AUTO_EXPORT true 5 | 6 | set_instance_parameter_value inst gui_reference_clock_frequency 125.0 7 | set_instance_parameter_value inst gui_output_clock_frequency0 200.0 8 | 9 | set_instance_parameter_value inst gui_pll_auto_reset On 10 | 11 | save_system $SYSTEM_PATH/PLL0.qsys 12 | -------------------------------------------------------------------------------- /QSFP-HDMI-OUT-NB7NQ621M/examples/Storey-Peak/scripts/IP/XCVR0.tcl: -------------------------------------------------------------------------------- 1 | create_system XCVR0 2 | 3 | add_instance inst altera_xcvr_native_sv 4 | set_instance_property inst AUTO_EXPORT true 5 | 6 | # Datapath Options 7 | set_instance_parameter_value inst tx_enable 1 8 | set_instance_parameter_value inst rx_enable 0 9 | set_instance_parameter_value inst enable_std 1 10 | set_instance_parameter_value inst enable_teng 0 11 | set_instance_parameter_value inst channels 4 12 | set_instance_parameter_value inst bonded_mode xN 13 | set_instance_parameter_value inst enable_simple_interface 1 14 | 15 | # PMA 16 | set_instance_parameter_value inst set_data_rate $XCVR0_DATA_RATE 17 | set_instance_parameter_value inst tx_pma_clk_div 1 18 | set_instance_parameter_value inst gui_pll_reconfig_pll0_refclk_freq $XCVR0_REFERENCE_CLOCK_FREQUENCY 19 | 20 | # Standard PCS 21 | set_instance_parameter_value inst std_protocol_hint basic 22 | set_instance_parameter_value inst std_pcs_pma_width 20 23 | set_instance_parameter_value inst std_tx_byte_ser_enable 1 24 | 25 | save_system $SYSTEM_PATH/XCVR0.qsys 26 | -------------------------------------------------------------------------------- /QSFP-HDMI-OUT-NB7NQ621M/examples/Storey-Peak/scripts/IP/XCVRReconfiguration0.tcl: -------------------------------------------------------------------------------- 1 | create_system XCVRReconfiguration0 2 | 3 | add_instance inst alt_xcvr_reconfig 4 | set_instance_property inst AUTO_EXPORT true 5 | 6 | set_instance_parameter_value inst number_of_reconfig_interfaces 10 7 | 8 | save_system $SYSTEM_PATH/XCVRReconfiguration0.qsys 9 | -------------------------------------------------------------------------------- /QSFP-HDMI-OUT-NB7NQ621M/examples/Storey-Peak/scripts/IP/XCVRReset0.tcl: -------------------------------------------------------------------------------- 1 | create_system XCVRReset0 2 | 3 | add_instance inst altera_xcvr_reset_control 4 | set_instance_property inst AUTO_EXPORT true 5 | 6 | # General Options 7 | set_instance_parameter_value inst CHANNELS 4 8 | set_instance_parameter_value inst PLLS 1 9 | set_instance_parameter_value inst SYS_CLK_IN_MHZ 200 10 | 11 | # TX PLL 12 | set_instance_parameter_value inst TX_PLL_ENABLE 1 13 | 14 | # TX Channel 15 | set_instance_parameter_value inst TX_ENABLE 1 16 | 17 | # RX Channel 18 | set_instance_parameter_value inst RX_ENABLE 0 19 | 20 | save_system $SYSTEM_PATH/XCVRReset0.qsys 21 | -------------------------------------------------------------------------------- /QSFP-HDMI-OUT-NB7NQ621M/examples/Storey-Peak/sources/IDT8N4Q001.v: -------------------------------------------------------------------------------- 1 | module IDT8N4Q001 #( 2 | parameter CLOCK_FREQUENCY = 0, 3 | parameter REFERENCE_CLOCK_FREQUENCY = 0 4 | ) ( 5 | input clock, 6 | input reset, 7 | 8 | input scl_input, 9 | output scl_output, 10 | input sda_input, 11 | output sda_output, 12 | 13 | output ready 14 | ); 15 | 16 | localparam IDT8N4Q001_ADDRESS = 7'h6E; 17 | 18 | localparam 19 | STATE_RESET = 0, 20 | STATE_WRITE_START = 1, 21 | STATE_WRITE_WAIT = 2, 22 | STATE_RECALIBRATE_START = 3, 23 | STATE_RECALIBRATE_WAIT = 4, 24 | STATE_WAIT = 5, 25 | STATE_READY = 6; 26 | 27 | 28 | wire [5:0] MINT; 29 | wire [17:0] MFRAC; 30 | wire [6:0] N; 31 | wire [1:0] P = 2'b00; 32 | wire DG = 1'b1; 33 | wire [1:0] DSM = 2'b11; 34 | wire DSM_ENA = 1'b1; 35 | wire LF = 1'b1; 36 | wire [1:0] CP = 2'b00; 37 | wire [1:0] FSEL = 2'b00; 38 | wire NPLL_BYP = 1'b1; 39 | wire ADC_ENA = 1'b1; 40 | 41 | generate 42 | if (REFERENCE_CLOCK_FREQUENCY == 121_584_000) begin 43 | // M = 21.88512, N = 18 44 | assign MINT = 6'd21; 45 | assign MFRAC = 18'd232028; 46 | assign N = 7'd18; 47 | end else if (REFERENCE_CLOCK_FREQUENCY == 145_900_800) begin 48 | // M = 20.426112, N = 14 49 | assign MINT = 6'd20; 50 | assign MFRAC = 18'd111702; 51 | assign N = 7'd14; 52 | end else if (REFERENCE_CLOCK_FREQUENCY == 148_500_000) begin 53 | // M = 20.79, N = 14 54 | assign MINT = 6'd20; 55 | assign MFRAC = 18'd207093; 56 | assign N = 7'd14; 57 | end 58 | endgenerate 59 | 60 | 61 | localparam DATA_COUNT = 24; 62 | 63 | function [7:0] DATA( 64 | input [4:0] index 65 | ); 66 | case (index) 67 | 0, 1, 2, 3: DATA = { CP, MINT[4:0], MFRAC[17] }; 68 | 4, 5, 6, 7: DATA = MFRAC[16:9]; 69 | 8, 9, 10, 11: DATA = MFRAC[8:1]; 70 | 12, 13, 14, 15: DATA = { MFRAC[0], N }; 71 | 18: DATA = { ADC_ENA, 1'b0, NPLL_BYP, ~FSEL, 3'b0 }; 72 | 20, 21, 22, 23: DATA = { P, MINT[5], DSM, DG, DSM_ENA, LF }; 73 | default: DATA = 8'h0; 74 | endcase 75 | endfunction 76 | 77 | 78 | wire i2c_valid; 79 | reg i2c_ready; 80 | reg [7:0] i2c_register; 81 | reg [7:0] i2c_data_write; 82 | wire i2c_nack; 83 | 84 | I2CMaster #(.CLOCK_FREQUENCY (CLOCK_FREQUENCY), .FREQUENCY(100_000)) i2c_master( 85 | .clock (clock), 86 | .reset (reset), 87 | 88 | .scl_input (scl_input), 89 | .scl_output (scl_output), 90 | .sda_input (sda_input), 91 | .sda_output (sda_output), 92 | 93 | .request (), 94 | .grant (1'b1), 95 | 96 | .valid (i2c_valid), 97 | .ready (i2c_ready), 98 | .address (IDT8N4Q001_ADDRESS), 99 | .rw (1'b0), 100 | .register (i2c_register), 101 | .data_write (i2c_data_write), 102 | .nack (i2c_nack), 103 | .data_read () 104 | ); 105 | 106 | 107 | reg [4:0] register_index; 108 | wire [7:0] data = DATA(register_index); 109 | 110 | reg [31:0] wait_count; 111 | 112 | reg [2:0] state; 113 | 114 | always @(posedge clock) begin 115 | if (reset) begin 116 | i2c_ready <= 0; 117 | state <= STATE_RESET; 118 | end else begin 119 | case (state) 120 | STATE_RESET: begin 121 | register_index <= 0; 122 | state <= STATE_WRITE_START; 123 | end 124 | STATE_WRITE_START: begin 125 | i2c_ready <= 1; 126 | i2c_register <= register_index; 127 | i2c_data_write <= data; 128 | state <= STATE_WRITE_WAIT; 129 | end 130 | STATE_WRITE_WAIT: begin 131 | if (i2c_valid) begin 132 | i2c_ready <= 0; 133 | if (i2c_nack) begin 134 | state <= STATE_RESET; 135 | end else begin 136 | if (register_index != DATA_COUNT - 1) begin 137 | register_index <= register_index + 1; 138 | state <= STATE_WRITE_START; 139 | end else begin 140 | state <= STATE_RECALIBRATE_START; 141 | end 142 | end 143 | end 144 | end 145 | STATE_RECALIBRATE_START: begin 146 | i2c_ready <= 1; 147 | i2c_register <= 18; 148 | i2c_data_write <= { ADC_ENA, 1'b0, NPLL_BYP, FSEL, 3'b0 }; // Toggle FSEL to recalibrate PLL 149 | state <= STATE_RECALIBRATE_WAIT; 150 | end 151 | STATE_RECALIBRATE_WAIT: begin 152 | if (i2c_valid) begin 153 | i2c_ready <= 0; 154 | if (i2c_nack) begin 155 | state <= STATE_RESET; 156 | end else begin 157 | wait_count <= CLOCK_FREQUENCY / 1000 - 1; // Wait 1ms 158 | state <= STATE_WAIT; 159 | end 160 | end 161 | end 162 | STATE_WAIT: begin 163 | if (wait_count != 0) begin 164 | wait_count <= wait_count - 1; 165 | end else begin 166 | state <= STATE_READY; 167 | end 168 | end 169 | endcase 170 | end 171 | end 172 | 173 | assign ready = state == STATE_READY; 174 | 175 | endmodule 176 | -------------------------------------------------------------------------------- /QSFP-HDMI-OUT-NB7NQ621M/examples/Storey-Peak/sources/Top.v: -------------------------------------------------------------------------------- 1 | `ifndef RESOLUTION 2 | `define RESOLUTION "1920x1080" 3 | `endif 4 | `ifndef REFRESH_RATE 5 | `define REFRESH_RATE 60 6 | `endif 7 | 8 | 9 | module Top( 10 | input clock_125, 11 | 12 | output [7:0] led, 13 | 14 | inout idt8n4q001_scl, 15 | inout idt8n4q001_sda, 16 | 17 | input qsfp_refclk, 18 | 19 | output [3:0] qsfp0_tx, 20 | inout qsfp0_scl, 21 | inout qsfp0_sda, 22 | 23 | output [3:0] qsfp1_tx, 24 | inout qsfp1_scl, 25 | inout qsfp1_sda 26 | ); 27 | 28 | localparam CLOCK_FREQUENCY = 200_000_000; 29 | 30 | localparam REFERENCE_CLOCK_FREQUENCY = 31 | `RESOLUTION == "1920x1080" ? 148_500_000 : 32 | `RESOLUTION == "2560x1440" ? (`REFRESH_RATE == 144 ? 145_900_800 : 121_584_000) : 33 | `RESOLUTION == "3840x2160" ? 148_500_000 : 34 | 0; 35 | 36 | 37 | reg [2:0] system_reset_input_reg = 3'b111; 38 | wire system_reset_input = system_reset_input_reg[0]; 39 | 40 | always @(posedge clock_125) begin 41 | system_reset_input_reg <= system_reset_input_reg >> 1; 42 | end 43 | 44 | wire system_clock; 45 | wire pll0_locked; 46 | 47 | PLL0 pll0 ( 48 | .refclk (clock_125), 49 | .rst (system_reset_input), 50 | .outclk_0 (system_clock), 51 | .locked (pll0_locked) 52 | ); 53 | 54 | reg [2:0] system_reset_reg; 55 | 56 | always @(posedge system_clock) begin 57 | if (~pll0_locked) begin 58 | system_reset_reg <= 3'b111; 59 | end else begin 60 | system_reset_reg <= system_reset_reg >> 1; 61 | end 62 | end 63 | 64 | wire system_reset = system_reset_reg[0]; 65 | 66 | 67 | wire idt8n4q001_scl_input; 68 | wire idt8n4q001_scl_output; 69 | wire idt8n4q001_sda_input; 70 | wire idt8n4q001_sda_output; 71 | 72 | alt_iobuf idt8n4q001_scl_iobuf( 73 | .I (idt8n4q001_scl_output), 74 | .OE (~idt8n4q001_scl_output), 75 | .O (idt8n4q001_scl_input), 76 | .IO (idt8n4q001_scl) 77 | ); 78 | alt_iobuf idt8n4q0010_sda_iobuf( 79 | .I (idt8n4q001_sda_output), 80 | .OE (~idt8n4q001_sda_output), 81 | .O (idt8n4q001_sda_input), 82 | .IO (idt8n4q001_sda) 83 | ); 84 | 85 | wire idt8n4q001_ready; 86 | 87 | IDT8N4Q001 #( 88 | .CLOCK_FREQUENCY (CLOCK_FREQUENCY), 89 | .REFERENCE_CLOCK_FREQUENCY (REFERENCE_CLOCK_FREQUENCY) 90 | ) idt8n4q001( 91 | .clock (system_clock), 92 | .reset (system_reset), 93 | 94 | .scl_input (idt8n4q001_scl_input), 95 | .scl_output (idt8n4q001_scl_output), 96 | .sda_input (idt8n4q001_sda_input), 97 | .sda_output (idt8n4q001_sda_output), 98 | 99 | .ready (idt8n4q001_ready) 100 | ); 101 | 102 | 103 | 104 | wire [1:0] tx_clock; 105 | wire [1:0] tx_reset; 106 | wire [159:0] tx_data[1:0]; 107 | 108 | XCVRWrapper0 xcvr_wrapper_0( 109 | .clock (system_clock), 110 | .reset (~idt8n4q001_ready), 111 | 112 | .refclk_0 (qsfp_refclk), 113 | .tx_0 (qsfp0_tx), 114 | 115 | .tx_clock_0 (tx_clock[0]), 116 | .tx_reset_0 (tx_reset[0]), 117 | .tx_data_0 (tx_data[0]), 118 | 119 | .refclk_1 (qsfp_refclk), 120 | .tx_1 (qsfp1_tx), 121 | 122 | .tx_clock_1 (tx_clock[1]), 123 | .tx_reset_1 (tx_reset[1]), 124 | .tx_data_1 (tx_data[1]) 125 | ); 126 | 127 | 128 | wire [1:0] qsfp_scl_input; 129 | wire [1:0] qsfp_scl_output; 130 | wire [1:0] qsfp_sda_input; 131 | wire [1:0] qsfp_sda_output; 132 | 133 | alt_iobuf qsfp0_scl_iobuf( 134 | .I (qsfp_scl_output[0]), 135 | .OE (~qsfp_scl_output[0]), 136 | .O (qsfp_scl_input[0]), 137 | .IO (qsfp0_scl) 138 | ); 139 | alt_iobuf qsfp0_sda_iobuf( 140 | .I (qsfp_sda_output[0]), 141 | .OE (~qsfp_sda_output[0]), 142 | .O (qsfp_sda_input[0]), 143 | .IO (qsfp0_sda) 144 | ); 145 | 146 | alt_iobuf qsfp1_scl_iobuf( 147 | .I (qsfp_scl_output[1]), 148 | .OE (~qsfp_scl_output[1]), 149 | .O (qsfp_scl_input[1]), 150 | .IO (qsfp1_scl) 151 | ); 152 | alt_iobuf qsfp1_sda_iobuf( 153 | .I (qsfp_sda_output[1]), 154 | .OE (~qsfp_sda_output[1]), 155 | .O (qsfp_sda_input[1]), 156 | .IO (qsfp1_sda) 157 | ); 158 | 159 | wire [1:0] run; 160 | 161 | genvar i; 162 | 163 | generate 164 | for (i = 0; i < 2; i = i + 1) begin: hdmi_out_examples 165 | HDMIOUTExample #( 166 | .CLOCK_FREQUENCY (CLOCK_FREQUENCY), 167 | .RESOLUTION (`RESOLUTION), 168 | .REFRESH_RATE (`REFRESH_RATE) 169 | ) hdmi_out_example( 170 | .system_clock (system_clock), 171 | .system_reset (system_reset), 172 | .tx_clock (tx_clock[i]), 173 | .tx_reset (tx_reset[i]), 174 | .tx_data (tx_data[i]), 175 | .hpd (1'b1), 176 | .scl_input (qsfp_scl_input[i]), 177 | .scl_output (qsfp_scl_output[i]), 178 | .sda_input (qsfp_sda_input[i]), 179 | .sda_output (qsfp_sda_output[i]), 180 | .i2c_request (), 181 | .i2c_grant (1'b1), 182 | .run (run[i]) 183 | ); 184 | end 185 | endgenerate 186 | 187 | assign led = { 188 | ~system_reset & run[1], 189 | ~system_reset & run[0], 190 | ~system_reset 191 | }; 192 | 193 | endmodule 194 | -------------------------------------------------------------------------------- /QSFP-HDMI-OUT-NB7NQ621M/examples/Storey-Peak/sources/XCVRWrapper.v: -------------------------------------------------------------------------------- 1 | module XCVRWrapper0( 2 | input clock, 3 | input reset, 4 | 5 | input refclk_0, 6 | output [3:0] tx_0, 7 | 8 | output tx_clock_0, 9 | output tx_reset_0, 10 | input [159:0] tx_data_0, 11 | 12 | input refclk_1, 13 | output [3:0] tx_1, 14 | 15 | output tx_clock_1, 16 | output tx_reset_1, 17 | input [159:0] tx_data_1 18 | ); 19 | 20 | wire [349:0] reconfig_to_xcvr[1:0]; 21 | wire [229:0] reconfig_from_xcvr[1:0]; 22 | 23 | XCVRReconfiguration0 xcvr_reconfiguration( 24 | .reconfig_busy (), 25 | .mgmt_clk_clk (clock), 26 | .mgmt_rst_reset (reset), 27 | .reconfig_mgmt_address (7'b0), 28 | .reconfig_mgmt_read (1'b0), 29 | .reconfig_mgmt_readdata (), 30 | .reconfig_mgmt_waitrequest (), 31 | .reconfig_mgmt_write (1'b0), 32 | .reconfig_mgmt_writedata (32'b0), 33 | .reconfig_to_xcvr ({ reconfig_to_xcvr[1], reconfig_to_xcvr[0] }), 34 | .reconfig_from_xcvr ({ reconfig_from_xcvr[1], reconfig_from_xcvr[0] }) 35 | ); 36 | 37 | wire [1:0] pll_powerdown; 38 | wire [3:0] tx_analogreset[1:0]; 39 | wire [3:0] tx_digitalreset[1:0]; 40 | wire [3:0] tx_ready[1:0]; 41 | wire [1:0] pll_locked; 42 | wire [3:0] tx_cal_busy[1:0]; 43 | 44 | wire [3:0] tx_std_clock[1:0]; 45 | 46 | wire [1:0] refclk = { refclk_1, refclk_0 }; 47 | wire [3:0] tx[1:0]; 48 | assign tx_0 = tx[0]; 49 | assign tx_1 = tx[1]; 50 | wire [1:0] tx_clock; 51 | assign tx_clock_0 = tx_clock[0]; 52 | assign tx_clock_1 = tx_clock[1]; 53 | wire [1:0] tx_reset; 54 | assign tx_reset_0 = tx_reset[0]; 55 | assign tx_reset_1 = tx_reset[1]; 56 | wire [159:0] tx_data[1:0]; 57 | assign tx_data[0] = tx_data_0; 58 | assign tx_data[1] = tx_data_1; 59 | 60 | genvar i; 61 | 62 | generate 63 | for (i = 0; i < 2; i = i + 1) begin: xcvrs 64 | XCVRReset0 xcvr_reset( 65 | .clock (clock), 66 | .reset (reset), 67 | .pll_powerdown (pll_powerdown[i]), 68 | .tx_analogreset (tx_analogreset[i]), 69 | .tx_digitalreset (tx_digitalreset[i]), 70 | .tx_ready (tx_ready[i]), 71 | .pll_locked (pll_locked[i]), 72 | .pll_select (1'b0), 73 | .tx_cal_busy (tx_cal_busy[i]) 74 | ); 75 | 76 | XCVR0 xcvr( 77 | .pll_powerdown (pll_powerdown[i]), 78 | .tx_analogreset (tx_analogreset[i]), 79 | .tx_digitalreset (tx_digitalreset[i]), 80 | .tx_pll_refclk (refclk[i]), 81 | .tx_serial_data (tx[i]), 82 | .pll_locked (pll_locked[i]), 83 | .tx_std_coreclkin ({ 4 { tx_clock[i] } }), 84 | .tx_std_clkout (tx_std_clock[i]), 85 | .tx_cal_busy (tx_cal_busy[i]), 86 | .reconfig_to_xcvr (reconfig_to_xcvr[i]), 87 | .reconfig_from_xcvr (reconfig_from_xcvr[i]), 88 | .tx_parallel_data (tx_data[i]), 89 | .unused_tx_parallel_data (96'b0) 90 | ); 91 | 92 | assign tx_clock[i] = tx_std_clock[i][1]; 93 | assign tx_reset[i] = ~&tx_ready[i]; 94 | end 95 | endgenerate 96 | 97 | endmodule 98 | -------------------------------------------------------------------------------- /QSFP-HDMI-OUT-NB7NQ621M/images/Module-Photo-1.jpg: -------------------------------------------------------------------------------- 1 | version https://git-lfs.github.com/spec/v1 2 | oid sha256:239944b3bc3a72a4f4d0a04c2f5221b8a6484771087fb61e2aeee6b8109a3586 3 | size 972673 4 | -------------------------------------------------------------------------------- /QSFP-HDMI-OUT-NB7NQ621M/images/Module-Photo-2.jpg: -------------------------------------------------------------------------------- 1 | version https://git-lfs.github.com/spec/v1 2 | oid sha256:fedc25af84f37ae484ac1e6e97fd92b4593378a5ad78d49ec0ec8b836c7469c9 3 | size 1927198 4 | -------------------------------------------------------------------------------- /QSFP-HDMI-OUT-NB7NQ621M/images/Module-Photo-3.jpg: -------------------------------------------------------------------------------- 1 | version https://git-lfs.github.com/spec/v1 2 | oid sha256:2254ec80bdebb7a139751cf2c89a5969ebe192080d2f6212232906838a8efae8 3 | size 1624273 4 | -------------------------------------------------------------------------------- /QSFP-HDMI-OUT-NB7NQ621M/shell/Label.png: -------------------------------------------------------------------------------- 1 | version https://git-lfs.github.com/spec/v1 2 | oid sha256:dabea964bf98fd273cca49a0d0cf9fe98441628d3220e3f4708f433c50e2be8f 3 | size 3506 4 | -------------------------------------------------------------------------------- /QSFP-HDMI-OUT-NB7NQ621M/shell/QSFP-HDMI-OUT-NB7NQ621M-Shell-1.stl: -------------------------------------------------------------------------------- 1 | version https://git-lfs.github.com/spec/v1 2 | oid sha256:076cae1c75aa6ca614683ee969c5135148a3e69b9c2939a611b5fb0107469137 3 | size 1139784 4 | -------------------------------------------------------------------------------- /QSFP-HDMI-OUT-NB7NQ621M/shell/QSFP-HDMI-OUT-NB7NQ621M-Shell-2.stl: -------------------------------------------------------------------------------- 1 | version https://git-lfs.github.com/spec/v1 2 | oid sha256:738b1383a334079592c5abc0ec04192cd81bd148dbde68bdb175fc80c93e0aff 3 | size 2163884 4 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # 🔌Plugcat 2 | 3 | [![GitHub Stars](https://img.shields.io/github/stars/SuperSodaSea/Plugcat.svg?style=social)](https://github.com/SuperSodaSea/Plugcat/stargazers) 4 | [![GitHub License](https://img.shields.io/github/license/SuperSodaSea/Plugcat)](https://github.com/SuperSodaSea/Plugcat/blob/main/LICENSE) 5 | 6 | - [QSFP-HDMI-OUT-NB7NQ621M v1.0](./QSFP-HDMI-OUT-NB7NQ621M/README.md) 7 | -------------------------------------------------------------------------------- /common/Chisel/.mill-version: -------------------------------------------------------------------------------- 1 | 0.12.8 2 | -------------------------------------------------------------------------------- /common/Chisel/build.mill: -------------------------------------------------------------------------------- 1 | package build 2 | 3 | import mill._ 4 | import scalalib._ 5 | 6 | import $packages._ 7 | 8 | trait Module extends ScalaModule { 9 | def scalaVersion = "2.13.15" 10 | def scalacOptions = super.scalacOptions() ++ Seq( 11 | "-unchecked", 12 | "-deprecation", 13 | "-language:reflectiveCalls", 14 | "-feature", 15 | "-Xcheckinit", 16 | "-Xfatal-warnings", 17 | "-Ywarn-dead-code", 18 | "-Ywarn-unused", 19 | "-Ymacro-annotations", 20 | ) 21 | } 22 | -------------------------------------------------------------------------------- /common/Chisel/hdmi/package.mill: -------------------------------------------------------------------------------- 1 | package build.hdmi 2 | 3 | import mill._ 4 | import scalalib._ 5 | 6 | object `package` extends RootModule with build.Module { 7 | def ivyDeps = Agg( 8 | ivy"org.chipsalliance::chisel:6.6.0", 9 | ) 10 | def scalacPluginIvyDeps = Agg( 11 | ivy"org.chipsalliance:::chisel-plugin:6.6.0", 12 | ) 13 | } 14 | -------------------------------------------------------------------------------- /common/Chisel/hdmi/src/common/HDMIDataIslandPacket.scala: -------------------------------------------------------------------------------- 1 | package hdmi.common 2 | 3 | import chisel3._ 4 | 5 | class HDMIDataIslandPacket extends Bundle { 6 | val header = Vec(3, UInt(8.W)) 7 | val body = Vec(28, UInt(8.W)) 8 | } 9 | 10 | object HDMIDataIslandPacketECC { 11 | // G(x) = 1 + x^6 + x^7 + x^8 12 | def advance(ecc: UInt, input: Bool): UInt = { 13 | (ecc >> 1) ^ Mux(ecc(0) ^ input, "b10000011".U, 0.U) 14 | } 15 | def advance(ecc: UInt, input: UInt): UInt = { 16 | (0 until 8).foldLeft(ecc)((ecc, i) => advance(ecc, input(i))) 17 | } 18 | } 19 | 20 | 21 | object HDMIAVIInfoFrame { 22 | def apply(): HDMIDataIslandPacket = { 23 | val packet = Wire(new HDMIDataIslandPacket) 24 | packet.header(0) := 0x82.U // AVI InfoFrame 25 | packet.header(1) := 0x02.U // Version 26 | packet.header(2) := 0x0D.U // Length 27 | packet.body := VecInit.fill(28)(0.U) 28 | 29 | // RGB 4:4:4 30 | packet.body(1) := "b00000000".U // Y = 00, A = 0, B = 00, S = 00 31 | packet.body(2) := "b00000000".U // C = 00, M = 00, R = 0000 32 | packet.body(3) := "b00000000".U // ITC = 0, EC = 000, Q = 00, SC = 00 33 | packet.body(4) := "b00000000".U // VIC = 0 34 | packet.body(5) := "b00000000".U // YQ = 00, CN = 00, PR = 0000 35 | 36 | // YCbCr 4:4:4 37 | // packet.body(1) := "b01000000".U // Y = 10, A = 0, B = 00, S = 00 38 | // packet.body(2) := "b00000000".U // C = 00, M = 00, R = 0000 39 | // packet.body(3) := "b00000000".U // ITC = 0, EC = 000, Q = 00, SC = 00 40 | // packet.body(4) := "b00000000".U // VIC = 0 41 | // packet.body(5) := "b00000000".U // YQ = 00, CN = 00, PR = 0000 42 | 43 | var checksum = 0.U(8.W) 44 | for (i <- 0 until 3) checksum = checksum - packet.header(i) 45 | for (i <- 1 to 13) checksum = checksum - packet.body(i) 46 | packet.body(0) := checksum 47 | 48 | packet 49 | } 50 | } 51 | -------------------------------------------------------------------------------- /common/Chisel/hdmi/src/common/HDMIScramblerLFSR.scala: -------------------------------------------------------------------------------- 1 | package hdmi.common 2 | 3 | import chisel3._ 4 | 5 | object HDMIScramblerLFSR { 6 | // G(x) = 1 + x^11 + x^12 + x^13 + x^16 7 | def advance(value: UInt): UInt = { 8 | (value(14, 0) << 1) ^ Mux(value(15), "b0011100000000001".U, 0.U) 9 | } 10 | def advance(value: UInt, steps: Int): UInt = { 11 | (0 until steps).foldLeft(value)((v, _) => advance(v)) 12 | } 13 | } 14 | -------------------------------------------------------------------------------- /common/Chisel/hdmi/src/common/HDMIVideoTiming.scala: -------------------------------------------------------------------------------- 1 | package hdmi.common 2 | 3 | import chisel3._ 4 | 5 | class HDMIVideoTiming extends Bundle { 6 | var h_active = UInt(16.W) 7 | var h_front_porch = UInt(16.W) 8 | var h_sync = UInt(16.W) 9 | var h_back_porch = UInt(16.W) 10 | var v_active = UInt(16.W) 11 | var v_front_porch = UInt(16.W) 12 | var v_sync = UInt(16.W) 13 | var v_back_porch = UInt(16.W) 14 | var h_sync_polarity = Bool() 15 | var v_sync_polarity = Bool() 16 | } 17 | -------------------------------------------------------------------------------- /common/Chisel/hdmi/src/tmds/HDMITMDSEncoder.scala: -------------------------------------------------------------------------------- 1 | package hdmi.tmds 2 | 3 | import chisel3._ 4 | import chisel3.experimental.BundleLiterals._ 5 | import chisel3.util._ 6 | 7 | object HDMITMDSEncoderInputType extends ChiselEnum { 8 | val TMDS, TERC4, BYPASS = Value 9 | } 10 | 11 | class HDMITMDSEncoderInput extends Bundle { 12 | val input_type = HDMITMDSEncoderInputType() 13 | val counter_reset = Bool() 14 | val tmds = UInt(8.W) 15 | val terc4 = UInt(4.W) 16 | val bypass = UInt(10.W) 17 | } 18 | 19 | class HDMITMDSEncoderState extends Bundle { 20 | // TMDS dispairty counter 21 | val count = SInt(5.W) 22 | } 23 | 24 | class HDMITMDSEncoderUnit extends Module { 25 | val io = FlatIO(new Bundle { 26 | val input_state = Input(new HDMITMDSEncoderState) 27 | val input = Input(new HDMITMDSEncoderInput) 28 | val output_state = Output(new HDMITMDSEncoderState) 29 | val output = Output(UInt(10.W)) 30 | }) 31 | 32 | val q_m = Reg(UInt(9.W)) 33 | 34 | when (io.input.input_type === HDMITMDSEncoderInputType.TMDS) { 35 | val d = io.input.tmds 36 | val n1_d = PopCount(d) 37 | 38 | val b0 = n1_d > 4.U | (n1_d === 4.U & d(0) === 0.U) 39 | val q_m_b = Wire(Vec(9, Bool())) 40 | q_m_b(0) := d(0) 41 | for (j <- 1 to 7) 42 | q_m_b(j) := q_m_b(j - 1) ^ d(j) ^ b0 43 | q_m_b(8) := ~b0 44 | q_m := q_m_b.asUInt 45 | } 46 | 47 | val input_reg = RegNext(io.input) 48 | 49 | io.output_state.count := Mux(input_reg.counter_reset, 0.S, io.input_state.count) 50 | 51 | val output = Reg(UInt(10.W)) 52 | io.output := output 53 | 54 | switch (input_reg.input_type) { 55 | is (HDMITMDSEncoderInputType.TMDS) { 56 | val n1_q_m = PopCount(q_m(7, 0)) 57 | 58 | val delta = 2.S * n1_q_m - 8.S 59 | val count = io.input_state.count 60 | when (count === 0.S | n1_q_m === 4.U) { 61 | output := Cat(~q_m(8), q_m(8), Mux(q_m(8), q_m(7, 0), ~q_m(7, 0))) 62 | when (q_m(8)) { 63 | io.output_state.count := count + delta 64 | } .otherwise { 65 | io.output_state.count := count - delta 66 | } 67 | } .elsewhen ((count > 0.S & n1_q_m > 4.U) | (count < 0.S & n1_q_m < 4.U)) { 68 | output := Cat(1.B, q_m(8), ~q_m(7, 0)) 69 | io.output_state.count := count + 2.S * q_m(8) - delta 70 | } .otherwise { 71 | output := Cat(0.B, q_m(8), q_m(7, 0)) 72 | io.output_state.count := count - 2.S * ~q_m(8) + delta 73 | } 74 | } 75 | is (HDMITMDSEncoderInputType.TERC4) { 76 | val TERC4_ENCODING = VecInit( 77 | "b1010011100".U, 78 | "b1001100011".U, 79 | "b1011100100".U, 80 | "b1011100010".U, 81 | "b0101110001".U, 82 | "b0100011110".U, 83 | "b0110001110".U, 84 | "b0100111100".U, 85 | "b1011001100".U, 86 | "b0100111001".U, 87 | "b0110011100".U, 88 | "b1011000110".U, 89 | "b1010001110".U, 90 | "b1001110001".U, 91 | "b0101100011".U, 92 | "b1011000011".U, 93 | ) 94 | 95 | output := TERC4_ENCODING(input_reg.terc4) 96 | } 97 | is (HDMITMDSEncoderInputType.BYPASS) { 98 | output := input_reg.bypass 99 | } 100 | } 101 | } 102 | 103 | class HDMITMDSEncoder(characters: Int) extends Module { 104 | val io = FlatIO(new Bundle { 105 | val input = Input(Vec(characters, new HDMITMDSEncoderInput)) 106 | val output = Output(Vec(characters, UInt(10.W))) 107 | }) 108 | 109 | val units = (0 until characters).map(_ => Module(new HDMITMDSEncoderUnit)) 110 | 111 | val state = RegInit((new HDMITMDSEncoderState).Lit( 112 | _.count -> 0.S, 113 | )) 114 | val states = Wire(Vec(characters + 1, new HDMITMDSEncoderState)) 115 | states(0) := state 116 | state := states(characters) 117 | 118 | for (i <- 0 until characters) { 119 | units(i).io.input := io.input(i) 120 | units(i).io.input_state := states(i) 121 | io.output(i) := units(i).io.output 122 | states(i + 1) := units(i).io.output_state 123 | } 124 | } 125 | -------------------------------------------------------------------------------- /common/Chisel/hdmioutexample/package.mill: -------------------------------------------------------------------------------- 1 | package build.hdmioutexample 2 | 3 | import mill._ 4 | import scalalib._ 5 | 6 | object `package` extends RootModule with build.Module { 7 | def moduleDeps = Seq(build.hdmi) 8 | 9 | def ivyDeps = Agg( 10 | ivy"org.chipsalliance::chisel:6.6.0", 11 | ) 12 | def scalacPluginIvyDeps = Agg( 13 | ivy"org.chipsalliance:::chisel-plugin:6.6.0", 14 | ) 15 | } 16 | -------------------------------------------------------------------------------- /common/Chisel/hdmioutexample/src/HDMIOutExample.scala: -------------------------------------------------------------------------------- 1 | package hdmioutexample 2 | 3 | import circt.stage._ 4 | import hdmi.source._ 5 | 6 | object HDMIGenerator extends App { 7 | ChiselStage.emitSystemVerilog(new HDMISource(4), Array.empty, args) 8 | } 9 | -------------------------------------------------------------------------------- /common/KiCad/symbols/Power_Protection_AMAZING.kicad_sym: -------------------------------------------------------------------------------- 1 | (kicad_symbol_lib 2 | (version 20241209) 3 | (generator "kicad_symbol_editor") 4 | (generator_version "9.0") 5 | (symbol "AZ1023-04F.R7G" 6 | (exclude_from_sim no) 7 | (in_bom yes) 8 | (on_board yes) 9 | (property "Reference" "U" 10 | (at 0 10.922 0) 11 | (effects 12 | (font 13 | (size 1.27 1.27) 14 | ) 15 | ) 16 | ) 17 | (property "Value" "AZ1023-04F.R7G" 18 | (at 0 8.89 0) 19 | (effects 20 | (font 21 | (size 1.27 1.27) 22 | ) 23 | ) 24 | ) 25 | (property "Footprint" "Package_DFN_QFN:Diodes_UDFN-10_1.0x2.5mm_P0.5mm" 26 | (at 0 -8.89 0) 27 | (effects 28 | (font 29 | (size 1.27 1.27) 30 | ) 31 | (hide yes) 32 | ) 33 | ) 34 | (property "Datasheet" "https://www.amazingic.com/uploads/images/products/PDF/AZ1/AZ1023-04F.pdf" 35 | (at 0 -13.97 0) 36 | (effects 37 | (font 38 | (size 1.27 1.27) 39 | ) 40 | (hide yes) 41 | ) 42 | ) 43 | (property "Description" "Ultra Low Capacitance ESD Protection Array For High Speed I/O Port" 44 | (at 0 -11.43 0) 45 | (effects 46 | (font 47 | (size 1.27 1.27) 48 | ) 49 | (hide yes) 50 | ) 51 | ) 52 | (property "ki_keywords" "ESD" 53 | (at 0 0 0) 54 | (effects 55 | (font 56 | (size 1.27 1.27) 57 | ) 58 | (hide yes) 59 | ) 60 | ) 61 | (symbol "AZ1023-04F.R7G_0_0" 62 | (pin passive line 63 | (at -10.16 5.08 0) 64 | (length 5.08) 65 | (name "L1" 66 | (effects 67 | (font 68 | (size 1.27 1.27) 69 | ) 70 | ) 71 | ) 72 | (number "1" 73 | (effects 74 | (font 75 | (size 1.27 1.27) 76 | ) 77 | ) 78 | ) 79 | ) 80 | (pin passive line 81 | (at -10.16 2.54 0) 82 | (length 5.08) 83 | (name "L2" 84 | (effects 85 | (font 86 | (size 1.27 1.27) 87 | ) 88 | ) 89 | ) 90 | (number "2" 91 | (effects 92 | (font 93 | (size 1.27 1.27) 94 | ) 95 | ) 96 | ) 97 | ) 98 | (pin power_in line 99 | (at -10.16 0 0) 100 | (length 5.08) 101 | (name "GND" 102 | (effects 103 | (font 104 | (size 1.27 1.27) 105 | ) 106 | ) 107 | ) 108 | (number "3" 109 | (effects 110 | (font 111 | (size 1.27 1.27) 112 | ) 113 | ) 114 | ) 115 | ) 116 | (pin passive line 117 | (at -10.16 -2.54 0) 118 | (length 5.08) 119 | (name "L3" 120 | (effects 121 | (font 122 | (size 1.27 1.27) 123 | ) 124 | ) 125 | ) 126 | (number "4" 127 | (effects 128 | (font 129 | (size 1.27 1.27) 130 | ) 131 | ) 132 | ) 133 | ) 134 | (pin passive line 135 | (at -10.16 -5.08 0) 136 | (length 5.08) 137 | (name "L4" 138 | (effects 139 | (font 140 | (size 1.27 1.27) 141 | ) 142 | ) 143 | ) 144 | (number "5" 145 | (effects 146 | (font 147 | (size 1.27 1.27) 148 | ) 149 | ) 150 | ) 151 | ) 152 | (pin power_in line 153 | (at 10.16 0 180) 154 | (length 5.08) 155 | (name "GND" 156 | (effects 157 | (font 158 | (size 1.27 1.27) 159 | ) 160 | ) 161 | ) 162 | (number "8" 163 | (effects 164 | (font 165 | (size 1.27 1.27) 166 | ) 167 | ) 168 | ) 169 | ) 170 | (pin passive line 171 | (at 10.16 -2.54 180) 172 | (length 5.08) 173 | (name "NC" 174 | (effects 175 | (font 176 | (size 1.27 1.27) 177 | ) 178 | ) 179 | ) 180 | (number "7" 181 | (effects 182 | (font 183 | (size 1.27 1.27) 184 | ) 185 | ) 186 | ) 187 | ) 188 | (pin passive line 189 | (at 10.16 -5.08 180) 190 | (length 5.08) 191 | (name "NC" 192 | (effects 193 | (font 194 | (size 1.27 1.27) 195 | ) 196 | ) 197 | ) 198 | (number "6" 199 | (effects 200 | (font 201 | (size 1.27 1.27) 202 | ) 203 | ) 204 | ) 205 | ) 206 | ) 207 | (symbol "AZ1023-04F.R7G_1_0" 208 | (pin passive line 209 | (at 10.16 5.08 180) 210 | (length 5.08) 211 | (name "NC" 212 | (effects 213 | (font 214 | (size 1.27 1.27) 215 | ) 216 | ) 217 | ) 218 | (number "10" 219 | (effects 220 | (font 221 | (size 1.27 1.27) 222 | ) 223 | ) 224 | ) 225 | ) 226 | (pin passive line 227 | (at 10.16 2.54 180) 228 | (length 5.08) 229 | (name "NC" 230 | (effects 231 | (font 232 | (size 1.27 1.27) 233 | ) 234 | ) 235 | ) 236 | (number "9" 237 | (effects 238 | (font 239 | (size 1.27 1.27) 240 | ) 241 | ) 242 | ) 243 | ) 244 | ) 245 | (symbol "AZ1023-04F.R7G_1_1" 246 | (rectangle 247 | (start -5.08 7.62) 248 | (end 5.08 -7.62) 249 | (stroke 250 | (width 0) 251 | (type default) 252 | ) 253 | (fill 254 | (type background) 255 | ) 256 | ) 257 | ) 258 | (embedded_fonts no) 259 | ) 260 | ) 261 | -------------------------------------------------------------------------------- /common/OpenOCD/Longs-Peak/Config.cfg: -------------------------------------------------------------------------------- 1 | source [find interface/ftdi/um232h.cfg] 2 | 3 | adapter speed 30000 4 | transport select jtag 5 | jtag newtap 10AXF40AA tap -irlen 1 -expected-id 0x04c0c0bb 6 | init 7 | -------------------------------------------------------------------------------- /common/OpenOCD/Storey-Peak/Config.cfg: -------------------------------------------------------------------------------- 1 | source [find interface/ftdi/um232h.cfg] 2 | 3 | adapter speed 30000 4 | transport select jtag 5 | jtag newtap 5SGSKF40I3LNAC tap -irlen 10 -expected-id 0x029070dd 6 | init 7 | -------------------------------------------------------------------------------- /common/Quartus/constraints/Longs-Peak/Clock.tcl: -------------------------------------------------------------------------------- 1 | set_location_assignment PIN_AP20 -to clock_100 2 | set_instance_assignment -name IO_STANDARD "1.8 V" -to clock_100 3 | set_instance_assignment -name GLOBAL_SIGNAL GLOBAL_CLOCK -to clock_100 4 | 5 | set_location_assignment PIN_U29 -to qsfp_refclk 6 | set_location_assignment PIN_U28 -to qsfp_refclk(n) 7 | set_instance_assignment -name IO_STANDARD LVDS -to qsfp_refclk 8 | -------------------------------------------------------------------------------- /common/Quartus/constraints/Longs-Peak/LED.tcl: -------------------------------------------------------------------------------- 1 | set_location_assignment PIN_AM17 -to led[0] 2 | set_instance_assignment -name IO_STANDARD "1.8 V" -to led[0] 3 | set_location_assignment PIN_AH18 -to led[1] 4 | set_instance_assignment -name IO_STANDARD "1.8 V" -to led[1] 5 | set_location_assignment PIN_AJ18 -to led[2] 6 | set_instance_assignment -name IO_STANDARD "1.8 V" -to led[2] 7 | set_location_assignment PIN_AH17 -to led[3] 8 | set_instance_assignment -name IO_STANDARD "1.8 V" -to led[3] 9 | set_location_assignment PIN_AJ16 -to led[4] 10 | set_instance_assignment -name IO_STANDARD "1.8 V" -to led[4] 11 | set_location_assignment PIN_AK17 -to led[5] 12 | set_instance_assignment -name IO_STANDARD "1.8 V" -to led[5] 13 | set_location_assignment PIN_AK16 -to led[6] 14 | set_instance_assignment -name IO_STANDARD "1.8 V" -to led[6] 15 | set_location_assignment PIN_AK18 -to led[7] 16 | set_instance_assignment -name IO_STANDARD "1.8 V" -to led[7] 17 | set_location_assignment PIN_AL18 -to led[8] 18 | set_instance_assignment -name IO_STANDARD "1.8 V" -to led[8] 19 | -------------------------------------------------------------------------------- /common/Quartus/constraints/Longs-Peak/QSFP.tcl: -------------------------------------------------------------------------------- 1 | set QSFP_TX_P_PINS { R37 T39 U37 V39 } 2 | set QSFP_TX_N_PINS { R36 T38 U36 V38 } 3 | for { set i 0 } { $i < 4 } { incr i } { 4 | set_location_assignment PIN_[lindex $QSFP_TX_P_PINS $i] -to qsfp_tx[$i] 5 | set_location_assignment PIN_[lindex $QSFP_TX_N_PINS $i] -to qsfp_tx[$i](n) 6 | set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to qsfp_tx[$i] 7 | } 8 | set QSFP_RX_P_PINS { U33 V31 V35 W33 } 9 | set QSFP_RX_N_PINS { U32 V30 V34 W32 } 10 | for { set i 0 } { $i < 4 } { incr i } { 11 | set_location_assignment PIN_[lindex $QSFP_RX_P_PINS $i] -to qsfp_rx[$i] 12 | set_location_assignment PIN_[lindex $QSFP_RX_N_PINS $i] -to qsfp_rx[$i](n) 13 | set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to qsfp_rx[$i] 14 | } 15 | 16 | set_location_assignment PIN_K20 -to qsfp_scl 17 | set_instance_assignment -name IO_STANDARD "1.8 V" -to qsfp_scl 18 | set_location_assignment PIN_L20 -to qsfp_sda 19 | set_instance_assignment -name IO_STANDARD "1.8 V" -to qsfp_sda 20 | set_location_assignment PIN_AG15 -to qsfp_modprsl 21 | set_instance_assignment -name IO_STANDARD "1.8 V" -to qsfp_modprsl 22 | -------------------------------------------------------------------------------- /common/Quartus/constraints/Storey-Peak/Clock.tcl: -------------------------------------------------------------------------------- 1 | set_location_assignment PIN_M23 -to clock_125 2 | set_instance_assignment -name IO_STANDARD SSTL-135 -to clock_125 3 | 4 | set_location_assignment PIN_T7 -to qsfp_refclk 5 | set_location_assignment PIN_T6 -to qsfp_refclk(n) 6 | set_instance_assignment -name IO_STANDARD LVDS -to qsfp_refclk 7 | -------------------------------------------------------------------------------- /common/Quartus/constraints/Storey-Peak/IDT8N4Q001.tcl: -------------------------------------------------------------------------------- 1 | set_location_assignment PIN_N7 -to idt8n4q001_scl 2 | set_instance_assignment -name IO_STANDARD "2.5 V" -to idt8n4q001_scl 3 | set_location_assignment PIN_P7 -to idt8n4q001_sda 4 | set_instance_assignment -name IO_STANDARD "2.5 V" -to idt8n4q001_sda 5 | -------------------------------------------------------------------------------- /common/Quartus/constraints/Storey-Peak/LED.tcl: -------------------------------------------------------------------------------- 1 | set_location_assignment PIN_A11 -to led[0] 2 | set_instance_assignment -name IO_STANDARD "2.5 V" -to led[0] 3 | set_location_assignment PIN_A10 -to led[1] 4 | set_instance_assignment -name IO_STANDARD "2.5 V" -to led[1] 5 | set_location_assignment PIN_B10 -to led[2] 6 | set_instance_assignment -name IO_STANDARD "2.5 V" -to led[2] 7 | set_location_assignment PIN_C10 -to led[3] 8 | set_instance_assignment -name IO_STANDARD "2.5 V" -to led[3] 9 | set_location_assignment PIN_C9 -to led[4] 10 | set_instance_assignment -name IO_STANDARD "2.5 V" -to led[4] 11 | set_location_assignment PIN_C8 -to led[5] 12 | set_instance_assignment -name IO_STANDARD "2.5 V" -to led[5] 13 | set_location_assignment PIN_B8 -to led[6] 14 | set_instance_assignment -name IO_STANDARD "2.5 V" -to led[6] 15 | set_location_assignment PIN_A8 -to led[7] 16 | set_instance_assignment -name IO_STANDARD "2.5 V" -to led[7] 17 | -------------------------------------------------------------------------------- /common/Quartus/constraints/Storey-Peak/QSFP0.tcl: -------------------------------------------------------------------------------- 1 | set QSFP0_TX_P_PINS { U4 R4 N4 L4 } 2 | set QSFP0_TX_N_PINS { U3 R3 N3 L3 } 3 | for { set i 0 } { $i < 4 } { incr i } { 4 | set_location_assignment PIN_[lindex $QSFP0_TX_P_PINS $i] -to qsfp0_tx[$i] 5 | set_location_assignment PIN_[lindex $QSFP0_TX_N_PINS $i] -to qsfp0_tx[$i](n) 6 | set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to qsfp0_tx[$i] 7 | } 8 | set QSFP0_RX_P_PINS { V2 T2 P2 M2 } 9 | set QSFP0_RX_N_PINS { V1 T1 P1 M1 } 10 | for { set i 0 } { $i < 4 } { incr i } { 11 | set_location_assignment PIN_[lindex $QSFP0_RX_P_PINS $i] -to qsfp0_rx[$i] 12 | set_location_assignment PIN_[lindex $QSFP0_RX_N_PINS $i] -to qsfp0_rx[$i](n) 13 | set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to qsfp0_rx[$i] 14 | } 15 | 16 | set_location_assignment PIN_AB24 -to qsfp0_scl 17 | set_instance_assignment -name IO_STANDARD "2.5 V" -to qsfp0_scl 18 | set_location_assignment PIN_AC24 -to qsfp0_sda 19 | set_instance_assignment -name IO_STANDARD "2.5 V" -to qsfp0_sda 20 | -------------------------------------------------------------------------------- /common/Quartus/constraints/Storey-Peak/QSFP1.tcl: -------------------------------------------------------------------------------- 1 | set QSFP1_TX_P_PINS { J4 G4 E4 C4 } 2 | set QSFP1_TX_N_PINS { J3 G3 E3 C3 } 3 | for { set i 0 } { $i < 4 } { incr i } { 4 | set_location_assignment PIN_[lindex $QSFP1_TX_P_PINS $i] -to qsfp1_tx[$i] 5 | set_location_assignment PIN_[lindex $QSFP1_TX_N_PINS $i] -to qsfp1_tx[$i](n) 6 | set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to qsfp1_tx[$i] 7 | } 8 | set QSFP1_RX_P_PINS { K2 H2 F2 D2 } 9 | set QSFP1_RX_N_PINS { K1 H1 F1 D1 } 10 | for { set i 0 } { $i < 4 } { incr i } { 11 | set_location_assignment PIN_[lindex $QSFP1_RX_P_PINS $i] -to qsfp1_rx[$i] 12 | set_location_assignment PIN_[lindex $QSFP1_RX_N_PINS $i] -to qsfp1_rx[$i](n) 13 | set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to qsfp1_rx[$i] 14 | } 15 | 16 | set_location_assignment PIN_AA25 -to qsfp1_scl 17 | set_instance_assignment -name IO_STANDARD "2.5 V" -to qsfp1_scl 18 | set_location_assignment PIN_AB25 -to qsfp1_sda 19 | set_instance_assignment -name IO_STANDARD "2.5 V" -to qsfp1_sda 20 | -------------------------------------------------------------------------------- /common/Verilog/hdmi/VideoGenerator.v: -------------------------------------------------------------------------------- 1 | module VideoGenerator( 2 | input clock, 3 | input reset, 4 | 5 | input [15:0] video_width, 6 | input [15:0] video_height, 7 | 8 | input start_frame, 9 | 10 | input ready, 11 | output valid, 12 | output [63:0] bits_0, 13 | output [63:0] bits_1, 14 | output [63:0] bits_2, 15 | output [63:0] bits_3 16 | ); 17 | 18 | reg valid_reg; 19 | assign valid = valid_reg; 20 | 21 | reg [63:0] bits[0:3]; 22 | assign bits_0 = bits[0]; 23 | assign bits_1 = bits[1]; 24 | assign bits_2 = bits[2]; 25 | assign bits_3 = bits[3]; 26 | 27 | wire position_ready = ready | ~valid; 28 | reg position_valid; 29 | reg [15:0] cx; 30 | reg [15:0] cy; 31 | 32 | reg [15:0] bx; 33 | reg [15:0] by; 34 | reg dx; 35 | reg dy; 36 | 37 | localparam border = 20; 38 | localparam step = 8; 39 | 40 | always @(posedge clock) begin 41 | if (reset) begin 42 | valid_reg <= 0; 43 | position_valid <= 0; 44 | bx <= border; 45 | by <= border; 46 | dx <= 0; 47 | dy <= 0; 48 | end else begin 49 | if (~position_valid) begin 50 | if (start_frame) begin 51 | position_valid <= 1; 52 | cx <= 0; 53 | cy <= 0; 54 | end 55 | end 56 | 57 | if (position_ready & position_valid) begin 58 | if (cx + 4 < video_width) begin 59 | cx <= cx + 4; 60 | end else begin 61 | cx <= 0; 62 | if (cy + 1 < video_height) begin 63 | cy <= cy + 1; 64 | end else begin 65 | position_valid <= 0; 66 | 67 | if (~dx) begin 68 | if (bx + step < video_width - border - 200) begin 69 | bx <= bx + step; 70 | end else begin 71 | bx <= bx - step; 72 | dx <= 1; 73 | end 74 | end else begin 75 | if (bx - step >= border) begin 76 | bx <= bx - step; 77 | end else begin 78 | bx <= bx + step; 79 | dx <= 0; 80 | end 81 | end 82 | 83 | if (~dy) begin 84 | if (by + step < video_height - border - 200) begin 85 | by <= by + step; 86 | end else begin 87 | by <= by - step; 88 | dy <= 1; 89 | end 90 | end else begin 91 | if (by - step >= border) begin 92 | by <= by - step; 93 | end else begin 94 | by <= by + step; 95 | dy <= 0; 96 | end 97 | end 98 | end 99 | end 100 | end 101 | 102 | if (position_ready) begin 103 | valid_reg <= position_valid; 104 | end 105 | end 106 | end 107 | 108 | function [63:0] generate_pixel( 109 | input [15:0] px, 110 | input [15:0] py 111 | ); 112 | begin 113 | if (px == 0 || py == 0 || px == video_width - 1 || py == video_height - 1) begin 114 | generate_pixel = 64'h0000FF; 115 | end else if (px == 1 || py == 1 || px == video_width - 2 || py == video_height - 2) begin 116 | generate_pixel = 64'h00FF00; 117 | end else if (px == 2 || py == 2 || px == video_width - 3 || py == video_height - 3) begin 118 | generate_pixel = 64'hFF0000; 119 | end else if (px == 3 || py == 3 || px == video_width - 4 || py == video_height - 4) begin 120 | generate_pixel = 64'h000000; 121 | end else if (px >= bx && py >= by && px < bx + 200 && py < by + 200) begin 122 | generate_pixel = 64'hFFCC66; 123 | end else if (px >= 50 && py >= 50 && px < 250 && py <= 250) begin 124 | generate_pixel = 64'h0000FF; 125 | end else if (px >= 100 && py >= 100 && px < 300 && py <= 300) begin 126 | generate_pixel = 64'h00FFFF; 127 | end else if (px >= 150 && py >= 150 && px < 350 && py <= 350) begin 128 | generate_pixel = 64'h00FF00; 129 | end else if (px >= 200 && py >= 200 && px < 400 && py <= 400) begin 130 | generate_pixel = 64'hFFFF00; 131 | end else if (px >= 250 && py >= 250 && px < 450 && py <= 450) begin 132 | generate_pixel = 64'hFF0000; 133 | end else if (px >= 300 && py >= 300 && px < 500 && py <= 500) begin 134 | generate_pixel = 64'hFF00FF; 135 | end else if (px[5] ^ py[5]) begin 136 | generate_pixel = 64'hFFFFFF; 137 | end else begin 138 | generate_pixel = 64'hCCCCCC; 139 | end 140 | end 141 | endfunction 142 | 143 | genvar i; 144 | 145 | generate 146 | for (i = 0; i < 4; i = i + 1) begin: generate_pixels 147 | wire [15:0] px = cx + i; 148 | wire [15:0] py = cy; 149 | 150 | always @(posedge clock) begin 151 | if (~reset & position_ready & position_valid) begin 152 | bits[i] <= generate_pixel(px, py); 153 | end 154 | end 155 | end 156 | endgenerate 157 | 158 | endmodule 159 | -------------------------------------------------------------------------------- /common/Vivado/constraints/ADM-PCIE-KU3/Clock.xdc: -------------------------------------------------------------------------------- 1 | set_property -dict { PACKAGE_PIN AA24 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports clock_250_p] 2 | set_property -dict { PACKAGE_PIN AA25 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports clock_250_n] 3 | 4 | create_clock -name clock_250 -period 4 -quiet [get_ports clock_250_p] 5 | 6 | set_property -dict { PACKAGE_PIN W23 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports clock_200_p] 7 | set_property -dict { PACKAGE_PIN W24 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports clock_200_n] 8 | 9 | create_clock -name clock_200 -period 5 -quiet [get_ports clock_200_p] 10 | -------------------------------------------------------------------------------- /common/Vivado/constraints/ADM-PCIE-KU3/Config.xdc: -------------------------------------------------------------------------------- 1 | set_property CFGBVS GND [current_design] 2 | set_property CONFIG_VOLTAGE 1.8 [current_design] 3 | set_property CONFIG_MODE BPI16 [current_design] 4 | set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN DIV-1 [current_design] 5 | set_property BITSTREAM.CONFIG.BPI_SYNC_MODE TYPE1 [current_design] 6 | set_property BITSTREAM.CONFIG.UNUSEDPIN Pullnone [current_design] 7 | set_property BITSTREAM.GENERAL.COMPRESS True [current_design] 8 | -------------------------------------------------------------------------------- /common/Vivado/constraints/ADM-PCIE-KU3/LED.xdc: -------------------------------------------------------------------------------- 1 | set_property PACKAGE_PIN AE12 [get_ports led[0]] 2 | set_property PACKAGE_PIN AF12 [get_ports led[1]] 3 | set_property PACKAGE_PIN AD11 [get_ports led[2]] 4 | set_property IOSTANDARD LVCMOS33 [get_ports led[*]] 5 | -------------------------------------------------------------------------------- /common/Vivado/constraints/ADM-PCIE-KU3/QSFP0.xdc: -------------------------------------------------------------------------------- 1 | # Bank 128, X0Y16~X0Y19 2 | 3 | # 156.25MHz, Reconfigurable with Si5338 4 | set_property PACKAGE_PIN L29 [get_ports qsfp0_refclk_p] 5 | set_property PACKAGE_PIN L30 [get_ports qsfp0_refclk_n] 6 | 7 | create_clock -name qsfp0_refclk -period 6.4 [get_ports qsfp0_refclk_p] 8 | 9 | set_property PACKAGE_PIN H31 [get_ports qsfp0_txp[0]] 10 | set_property PACKAGE_PIN H32 [get_ports qsfp0_txn[0]] 11 | set_property PACKAGE_PIN G29 [get_ports qsfp0_txp[1]] 12 | set_property PACKAGE_PIN G30 [get_ports qsfp0_txn[1]] 13 | set_property PACKAGE_PIN D31 [get_ports qsfp0_txp[2]] 14 | set_property PACKAGE_PIN D32 [get_ports qsfp0_txn[2]] 15 | set_property PACKAGE_PIN B31 [get_ports qsfp0_txp[3]] 16 | set_property PACKAGE_PIN B32 [get_ports qsfp0_txn[3]] 17 | 18 | set_property PACKAGE_PIN G33 [get_ports qsfp0_rxp[0]] 19 | set_property PACKAGE_PIN G34 [get_ports qsfp0_rxn[0]] 20 | set_property PACKAGE_PIN F31 [get_ports qsfp0_rxp[1]] 21 | set_property PACKAGE_PIN F32 [get_ports qsfp0_rxn[1]] 22 | set_property PACKAGE_PIN E33 [get_ports qsfp0_rxp[2]] 23 | set_property PACKAGE_PIN E34 [get_ports qsfp0_rxn[2]] 24 | set_property PACKAGE_PIN C33 [get_ports qsfp0_rxp[3]] 25 | set_property PACKAGE_PIN C34 [get_ports qsfp0_rxn[3]] 26 | 27 | set_property -dict { PACKAGE_PIN AK13 IOSTANDARD LVCMOS33 } [get_ports qsfp0_modprsl] 28 | set_property -dict { PACKAGE_PIN AE13 IOSTANDARD LVCMOS33 } [get_ports qsfp0_intl] 29 | set_property -dict { PACKAGE_PIN AL12 IOSTANDARD LVCMOS33 } [get_ports qsfp0_resetl] 30 | set_property -dict { PACKAGE_PIN AF13 IOSTANDARD LVCMOS33 } [get_ports qsfp0_lpmode] 31 | set_property -dict { PACKAGE_PIN AK11 IOSTANDARD LVCMOS33 } [get_ports qsfp0_scl] 32 | set_property -dict { PACKAGE_PIN AL13 IOSTANDARD LVCMOS33 } [get_ports qsfp0_sda] 33 | -------------------------------------------------------------------------------- /common/Vivado/constraints/ADM-PCIE-KU3/QSFP1.xdc: -------------------------------------------------------------------------------- 1 | # Bank 228, X1Y16~X1Y19 2 | 3 | # 156.25MHz, Reconfigurable with Si5338 4 | set_property PACKAGE_PIN K6 [get_ports qsfp1_refclk_p] 5 | set_property PACKAGE_PIN K5 [get_ports qsfp1_refclk_n] 6 | 7 | create_clock -name qsfp1_refclk -period 6.4 [get_ports qsfp1_refclk_p] 8 | 9 | set_property PACKAGE_PIN F6 [get_ports qsfp1_txp[0]] 10 | set_property PACKAGE_PIN F5 [get_ports qsfp1_txn[0]] 11 | set_property PACKAGE_PIN D6 [get_ports qsfp1_txp[1]] 12 | set_property PACKAGE_PIN D5 [get_ports qsfp1_txn[1]] 13 | set_property PACKAGE_PIN C4 [get_ports qsfp1_txp[2]] 14 | set_property PACKAGE_PIN C3 [get_ports qsfp1_txn[2]] 15 | set_property PACKAGE_PIN B6 [get_ports qsfp1_txp[3]] 16 | set_property PACKAGE_PIN B5 [get_ports qsfp1_txn[3]] 17 | 18 | set_property PACKAGE_PIN E4 [get_ports qsfp1_rxp[0]] 19 | set_property PACKAGE_PIN E3 [get_ports qsfp1_rxn[0]] 20 | set_property PACKAGE_PIN D2 [get_ports qsfp1_rxp[1]] 21 | set_property PACKAGE_PIN D1 [get_ports qsfp1_rxn[1]] 22 | set_property PACKAGE_PIN B2 [get_ports qsfp1_rxp[2]] 23 | set_property PACKAGE_PIN B1 [get_ports qsfp1_rxn[2]] 24 | set_property PACKAGE_PIN A4 [get_ports qsfp1_rxp[3]] 25 | set_property PACKAGE_PIN A3 [get_ports qsfp1_rxn[3]] 26 | 27 | set_property -dict { PACKAGE_PIN AP10 IOSTANDARD LVCMOS33 } [get_ports qsfp1_modprsl] 28 | set_property -dict { PACKAGE_PIN AN11 IOSTANDARD LVCMOS33 } [get_ports qsfp1_intl] 29 | set_property -dict { PACKAGE_PIN AP11 IOSTANDARD LVCMOS33 } [get_ports qsfp1_resetl] 30 | set_property -dict { PACKAGE_PIN AN13 IOSTANDARD LVCMOS33 } [get_ports qsfp1_lpmode] 31 | set_property -dict { PACKAGE_PIN AP13 IOSTANDARD LVCMOS33 } [get_ports qsfp1_scl] 32 | set_property -dict { PACKAGE_PIN AM11 IOSTANDARD LVCMOS33 } [get_ports qsfp1_sda] 33 | -------------------------------------------------------------------------------- /common/Vivado/constraints/ADM-PCIE-KU3/Si5338.xdc: -------------------------------------------------------------------------------- 1 | set_property -dict { PACKAGE_PIN AE11 IOSTANDARD LVCMOS33 } [get_ports si5338_scl] 2 | set_property -dict { PACKAGE_PIN AG12 IOSTANDARD LVCMOS33 } [get_ports si5338_sda] 3 | -------------------------------------------------------------------------------- /common/Vivado/constraints/Alibaba-VU13P/Clock.xdc: -------------------------------------------------------------------------------- 1 | set_property -dict { PACKAGE_PIN AY23 IOSTANDARD DIFF_SSTL12 } [get_ports clock_100_p] 2 | set_property -dict { PACKAGE_PIN BA23 IOSTANDARD DIFF_SSTL12 } [get_ports clock_100_n] 3 | 4 | create_clock -name clock_100 -period 10 -quiet [get_ports clock_100_p] 5 | 6 | set_property -dict { PACKAGE_PIN AY22 IOSTANDARD DIFF_SSTL12 } [get_ports clock_400_p] 7 | set_property -dict { PACKAGE_PIN BA22 IOSTANDARD DIFF_SSTL12 } [get_ports clock_400_n] 8 | 9 | create_clock -name clock_400 -period 2.5 -quiet [get_ports clock_400_p] 10 | -------------------------------------------------------------------------------- /common/Vivado/constraints/Alibaba-VU13P/Config.xdc: -------------------------------------------------------------------------------- 1 | set_property CFGBVS GND [current_design] 2 | set_property CONFIG_VOLTAGE 1.8 [current_design] 3 | set_property CONFIG_MODE SPIx4 [current_design] 4 | set_property BITSTREAM.CONFIG.CONFIGRATE 102.0 [current_design] 5 | set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN Disable [current_design] 6 | set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR Yes [current_design] 7 | set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design] 8 | set_property BITSTREAM.CONFIG.SPI_FALL_EDGE Yes [current_design] 9 | set_property BITSTREAM.CONFIG.UNUSEDPIN Pullnone [current_design] 10 | set_property BITSTREAM.GENERAL.COMPRESS True [current_design] 11 | -------------------------------------------------------------------------------- /common/Vivado/constraints/Alibaba-VU13P/LED.xdc: -------------------------------------------------------------------------------- 1 | set_property PACKAGE_PIN BA20 [get_ports led[0]] 2 | set_property PACKAGE_PIN BB20 [get_ports led[1]] 3 | set_property PACKAGE_PIN BB21 [get_ports led[2]] 4 | set_property PACKAGE_PIN BC21 [get_ports led[3]] 5 | set_property PACKAGE_PIN BB22 [get_ports led[4]] 6 | set_property PACKAGE_PIN BC22 [get_ports led[5]] 7 | set_property PACKAGE_PIN BA24 [get_ports led[6]] 8 | set_property PACKAGE_PIN BB24 [get_ports led[7]] 9 | set_property IOSTANDARD LVCMOS12 [get_ports led[*]] 10 | 11 | set_property -dict { PACKAGE_PIN BD20 IOSTANDARD LVCMOS12 } [get_ports led_run] 12 | -------------------------------------------------------------------------------- /common/Vivado/constraints/Alibaba-VU13P/QSFP1.xdc: -------------------------------------------------------------------------------- 1 | # SLR3, Bank 233, X1Y52~X1Y55 2 | 3 | # 161.132MHz 4 | set_property PACKAGE_PIN D11 [get_ports qsfp1_refclk_p] 5 | set_property PACKAGE_PIN D10 [get_ports qsfp1_refclk_n] 6 | 7 | create_clock -name qsfp1_refclk -period 6.206 [get_ports qsfp1_refclk_p] 8 | 9 | set_property PACKAGE_PIN E4 [get_ports qsfp1_rxp[0]] 10 | set_property PACKAGE_PIN E3 [get_ports qsfp1_rxn[0]] 11 | set_property PACKAGE_PIN D2 [get_ports qsfp1_rxp[1]] 12 | set_property PACKAGE_PIN D1 [get_ports qsfp1_rxn[1]] 13 | set_property PACKAGE_PIN C4 [get_ports qsfp1_rxp[2]] 14 | set_property PACKAGE_PIN C3 [get_ports qsfp1_rxn[2]] 15 | set_property PACKAGE_PIN A5 [get_ports qsfp1_rxp[3]] 16 | set_property PACKAGE_PIN A4 [get_ports qsfp1_rxn[3]] 17 | 18 | set_property PACKAGE_PIN E9 [get_ports qsfp1_txp[0]] 19 | set_property PACKAGE_PIN E8 [get_ports qsfp1_txn[0]] 20 | set_property PACKAGE_PIN D7 [get_ports qsfp1_txp[1]] 21 | set_property PACKAGE_PIN D6 [get_ports qsfp1_txn[1]] 22 | set_property PACKAGE_PIN C9 [get_ports qsfp1_txp[2]] 23 | set_property PACKAGE_PIN C8 [get_ports qsfp1_txn[2]] 24 | set_property PACKAGE_PIN A9 [get_ports qsfp1_txp[3]] 25 | set_property PACKAGE_PIN A8 [get_ports qsfp1_txn[3]] 26 | 27 | set_property -dict { PACKAGE_PIN BC7 IOSTANDARD LVCMOS12 } [get_ports qsfp1_modprsl] 28 | set_property -dict { PACKAGE_PIN BC8 IOSTANDARD LVCMOS12 } [get_ports qsfp1_intl] 29 | set_property -dict { PACKAGE_PIN BB9 IOSTANDARD LVCMOS12 DRIVE 8 PULLTYPE PULLUP } [get_ports qsfp1_lpmode] 30 | set_property -dict { PACKAGE_PIN BA7 IOSTANDARD LVCMOS12 DRIVE 8 PULLTYPE PULLUP } [get_ports qsfp1_resetl] 31 | set_property -dict { PACKAGE_PIN BD8 IOSTANDARD LVCMOS12 DRIVE 8 PULLTYPE PULLUP } [get_ports qsfp1_scl] 32 | set_property -dict { PACKAGE_PIN BC12 IOSTANDARD LVCMOS12 DRIVE 8 PULLTYPE PULLUP } [get_ports qsfp1_sda] 33 | 34 | set_property -dict { PACKAGE_PIN BE21 IOSTANDARD LVCMOS12 DRIVE 8 } [get_ports qsfp1_led_y] 35 | set_property -dict { PACKAGE_PIN BF22 IOSTANDARD LVCMOS12 DRIVE 8 } [get_ports qsfp1_led_g] 36 | -------------------------------------------------------------------------------- /common/Vivado/constraints/Alibaba-VU13P/QSFP2.xdc: -------------------------------------------------------------------------------- 1 | # SLR2, Bank 229, X1Y36~X1Y39 2 | 3 | # 161.132MHz 4 | set_property PACKAGE_PIN Y11 [get_ports qsfp2_refclk_p] 5 | set_property PACKAGE_PIN Y10 [get_ports qsfp2_refclk_n] 6 | 7 | create_clock -name qsfp2_refclk -period 6.206 [get_ports qsfp2_refclk_p] 8 | 9 | set_property PACKAGE_PIN AA4 [get_ports qsfp2_rxp[0]] 10 | set_property PACKAGE_PIN AA3 [get_ports qsfp2_rxn[0]] 11 | set_property PACKAGE_PIN Y2 [get_ports qsfp2_rxp[1]] 12 | set_property PACKAGE_PIN Y1 [get_ports qsfp2_rxn[1]] 13 | set_property PACKAGE_PIN W4 [get_ports qsfp2_rxp[2]] 14 | set_property PACKAGE_PIN W3 [get_ports qsfp2_rxn[2]] 15 | set_property PACKAGE_PIN V2 [get_ports qsfp2_rxp[3]] 16 | set_property PACKAGE_PIN V1 [get_ports qsfp2_rxn[3]] 17 | 18 | set_property PACKAGE_PIN AA9 [get_ports qsfp2_txp[0]] 19 | set_property PACKAGE_PIN AA8 [get_ports qsfp2_txn[0]] 20 | set_property PACKAGE_PIN Y7 [get_ports qsfp2_txp[1]] 21 | set_property PACKAGE_PIN Y6 [get_ports qsfp2_txn[1]] 22 | set_property PACKAGE_PIN W9 [get_ports qsfp2_txp[2]] 23 | set_property PACKAGE_PIN W8 [get_ports qsfp2_txn[2]] 24 | set_property PACKAGE_PIN V7 [get_ports qsfp2_txp[3]] 25 | set_property PACKAGE_PIN V6 [get_ports qsfp2_txn[3]] 26 | 27 | set_property -dict { PACKAGE_PIN BB11 IOSTANDARD LVCMOS12 } [get_ports qsfp2_modprsl] 28 | set_property -dict { PACKAGE_PIN BC11 IOSTANDARD LVCMOS12 } [get_ports qsfp2_intl] 29 | set_property -dict { PACKAGE_PIN BB10 IOSTANDARD LVCMOS12 DRIVE 8 PULLTYPE PULLUP } [get_ports qsfp2_resetl] 30 | set_property -dict { PACKAGE_PIN BB7 IOSTANDARD LVCMOS12 DRIVE 8 PULLTYPE PULLUP } [get_ports qsfp2_lpmode] 31 | set_property -dict { PACKAGE_PIN BF12 IOSTANDARD LVCMOS12 DRIVE 8 PULLTYPE PULLUP } [get_ports qsfp2_scl] 32 | set_property -dict { PACKAGE_PIN BD9 IOSTANDARD LVCMOS12 DRIVE 8 PULLTYPE PULLUP } [get_ports qsfp2_sda] 33 | 34 | set_property -dict { PACKAGE_PIN BD21 IOSTANDARD LVCMOS12 DRIVE 8 } [get_ports qsfp2_led_y] 35 | set_property -dict { PACKAGE_PIN BE22 IOSTANDARD LVCMOS12 DRIVE 8 } [get_ports qsfp2_led_g] 36 | -------------------------------------------------------------------------------- /common/Vivado/constraints/BoChenJingXin-KU5P/Clock.xdc: -------------------------------------------------------------------------------- 1 | set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS18 } [get_ports clock_50] 2 | 3 | create_clock -name clock_50 -period 20 -quiet [get_ports clock_50] 4 | -------------------------------------------------------------------------------- /common/Vivado/constraints/BoChenJingXin-KU5P/Config.xdc: -------------------------------------------------------------------------------- 1 | set_property CFGBVS GND [current_design] 2 | set_property CONFIG_VOLTAGE 1.8 [current_design] 3 | set_property CONFIG_MODE SPIx4 [current_design] 4 | set_property BITSTREAM.CONFIG.CONFIGRATE 85.0 [current_design] 5 | set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN Disable [current_design] 6 | set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design] 7 | set_property BITSTREAM.CONFIG.UNUSEDPIN Pullnone [current_design] 8 | set_property BITSTREAM.GENERAL.COMPRESS True [current_design] 9 | -------------------------------------------------------------------------------- /common/Vivado/constraints/BoChenJingXin-KU5P/Key.xdc: -------------------------------------------------------------------------------- 1 | set_property PACKAGE_PIN AF14 [get_ports key[0]] 2 | set_property PACKAGE_PIN AF15 [get_ports key[1]] 3 | set_property IOSTANDARD LVCMOS33 [get_ports key[*]] 4 | -------------------------------------------------------------------------------- /common/Vivado/constraints/BoChenJingXin-KU5P/LED.xdc: -------------------------------------------------------------------------------- 1 | set_property PACKAGE_PIN K10 [get_ports led[0]] 2 | set_property PACKAGE_PIN K9 [get_ports led[1]] 3 | set_property PACKAGE_PIN J11 [get_ports led[2]] 4 | set_property PACKAGE_PIN J10 [get_ports led[3]] 5 | set_property PACKAGE_PIN J9 [get_ports led[4]] 6 | set_property PACKAGE_PIN H9 [get_ports led[5]] 7 | set_property IOSTANDARD LVCMOS33 [get_ports led[*]] 8 | -------------------------------------------------------------------------------- /common/Vivado/constraints/BoChenJingXin-KU5P/QSFP.xdc: -------------------------------------------------------------------------------- 1 | # Bank 225, X0Y4~X0Y7 2 | 3 | # 156.25MHz 4 | set_property PACKAGE_PIN V7 [get_ports qsfp_refclk_p] 5 | set_property PACKAGE_PIN V6 [get_ports qsfp_refclk_n] 6 | 7 | create_clock -name qsfp_refclk -period 6.4 [get_ports qsfp_refclk_p] 8 | 9 | set_property PACKAGE_PIN Y2 [get_ports qsfp_rxp[0]] 10 | set_property PACKAGE_PIN Y1 [get_ports qsfp_rxn[0]] 11 | set_property PACKAGE_PIN V2 [get_ports qsfp_rxp[1]] 12 | set_property PACKAGE_PIN V1 [get_ports qsfp_rxn[1]] 13 | set_property PACKAGE_PIN T2 [get_ports qsfp_rxp[2]] 14 | set_property PACKAGE_PIN T1 [get_ports qsfp_rxn[2]] 15 | set_property PACKAGE_PIN P2 [get_ports qsfp_rxp[3]] 16 | set_property PACKAGE_PIN P1 [get_ports qsfp_rxn[3]] 17 | 18 | set_property PACKAGE_PIN AA5 [get_ports qsfp_txp[0]] 19 | set_property PACKAGE_PIN AA4 [get_ports qsfp_txn[0]] 20 | set_property PACKAGE_PIN W5 [get_ports qsfp_txp[1]] 21 | set_property PACKAGE_PIN W4 [get_ports qsfp_txn[1]] 22 | set_property PACKAGE_PIN U5 [get_ports qsfp_txp[2]] 23 | set_property PACKAGE_PIN U4 [get_ports qsfp_txn[2]] 24 | set_property PACKAGE_PIN R5 [get_ports qsfp_txp[3]] 25 | set_property PACKAGE_PIN R4 [get_ports qsfp_txn[3]] 26 | 27 | set_property -dict { PACKAGE_PIN AD15 IOSTANDARD LVCMOS33 } [get_ports qsfp_modprsl] 28 | set_property -dict { PACKAGE_PIN AD13 IOSTANDARD LVCMOS33 } [get_ports qsfp_intl] 29 | set_property -dict { PACKAGE_PIN Y15 IOSTANDARD LVCMOS33 } [get_ports qsfp_modsell] 30 | set_property -dict { PACKAGE_PIN AE13 IOSTANDARD LVCMOS33 } [get_ports qsfp_resetl] 31 | set_property -dict { PACKAGE_PIN W14 IOSTANDARD LVCMOS33 } [get_ports qsfp_lpmode] 32 | set_property -dict { PACKAGE_PIN AF13 IOSTANDARD LVCMOS33 } [get_ports qsfp_scl] 33 | set_property -dict { PACKAGE_PIN AE15 IOSTANDARD LVCMOS33 } [get_ports qsfp_sda] 34 | -------------------------------------------------------------------------------- /common/Vivado/constraints/MLK-H8-CU06-KU5P/Clock.xdc: -------------------------------------------------------------------------------- 1 | set_property -dict { PACKAGE_PIN V24 IOSTANDARD DIFF_SSTL12 } [get_ports clock_100_p] 2 | set_property -dict { PACKAGE_PIN W24 IOSTANDARD DIFF_SSTL12 } [get_ports clock_100_n] 3 | 4 | create_clock -name clock_100 -period 10 -quiet [get_ports clock_100_p] 5 | -------------------------------------------------------------------------------- /common/Vivado/constraints/MLK-H8-CU06-KU5P/Config.xdc: -------------------------------------------------------------------------------- 1 | set_property CFGBVS VCCO [current_design] 2 | set_property CONFIG_VOLTAGE 1.8 [current_design] 3 | set_property CONFIG_MODE SPIx4 [current_design] 4 | set_property BITSTREAM.CONFIG.CONFIGRATE 85.0 [current_design] 5 | set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design] 6 | set_property BITSTREAM.CONFIG.SPI_FALL_EDGE Yes [current_design] 7 | set_property BITSTREAM.CONFIG.UNUSEDPIN Pullnone [current_design] 8 | set_property BITSTREAM.GENERAL.COMPRESS True [current_design] 9 | -------------------------------------------------------------------------------- /common/Vivado/constraints/MLK-H8-CU06-KU5P/Key.xdc: -------------------------------------------------------------------------------- 1 | set_property PACKAGE_PIN W19 [get_ports key[0]] 2 | set_property PACKAGE_PIN W20 [get_ports key[1]] 3 | set_property IOSTANDARD LVCMOS12 [get_ports key[*]] -------------------------------------------------------------------------------- /common/Vivado/constraints/MLK-H8-CU06-KU5P/LED.xdc: -------------------------------------------------------------------------------- 1 | set_property PACKAGE_PIN AC16 [get_ports led[0]] 2 | set_property PACKAGE_PIN AE18 [get_ports led[1]] 3 | set_property IOSTANDARD LVCMOS12 [get_ports led[*]] -------------------------------------------------------------------------------- /common/Vivado/constraints/MLK-H8-CU06-KU5P/QSFP.xdc: -------------------------------------------------------------------------------- 1 | # Bank 225, X0Y4~X0Y7 2 | 3 | # 156.25MHz 4 | set_property PACKAGE_PIN T7 [get_ports qsfp_refclk_p] 5 | set_property PACKAGE_PIN T6 [get_ports qsfp_refclk_n] 6 | 7 | create_clock -name qsfp_refclk -period 6.4 [get_ports qsfp_refclk_p] 8 | 9 | set_property PACKAGE_PIN Y2 [get_ports qsfp_rxp[0]] 10 | set_property PACKAGE_PIN Y1 [get_ports qsfp_rxn[0]] 11 | set_property PACKAGE_PIN V2 [get_ports qsfp_rxp[1]] 12 | set_property PACKAGE_PIN V1 [get_ports qsfp_rxn[1]] 13 | set_property PACKAGE_PIN T2 [get_ports qsfp_rxp[2]] 14 | set_property PACKAGE_PIN T1 [get_ports qsfp_rxn[2]] 15 | set_property PACKAGE_PIN P2 [get_ports qsfp_rxp[3]] 16 | set_property PACKAGE_PIN P1 [get_ports qsfp_rxn[3]] 17 | 18 | set_property PACKAGE_PIN AA5 [get_ports qsfp_txp[0]] 19 | set_property PACKAGE_PIN AA4 [get_ports qsfp_txn[0]] 20 | set_property PACKAGE_PIN W5 [get_ports qsfp_txp[1]] 21 | set_property PACKAGE_PIN W4 [get_ports qsfp_txn[1]] 22 | set_property PACKAGE_PIN U5 [get_ports qsfp_txp[2]] 23 | set_property PACKAGE_PIN U4 [get_ports qsfp_txn[2]] 24 | set_property PACKAGE_PIN R5 [get_ports qsfp_txp[3]] 25 | set_property PACKAGE_PIN R4 [get_ports qsfp_txn[3]] 26 | 27 | set_property -dict { PACKAGE_PIN G12 IOSTANDARD LVCMOS33 } [get_ports qsfp_modprsl] 28 | set_property -dict { PACKAGE_PIN F13 IOSTANDARD LVCMOS33 } [get_ports qsfp_resetl] 29 | set_property -dict { PACKAGE_PIN F9 IOSTANDARD LVCMOS33 } [get_ports qsfp_scl] 30 | set_property -dict { PACKAGE_PIN F10 IOSTANDARD LVCMOS33 } [get_ports qsfp_sda] 31 | -------------------------------------------------------------------------------- /common/Vivado/constraints/RK-XCKU5P-F/Clock.xdc: -------------------------------------------------------------------------------- 1 | set_property -dict { PACKAGE_PIN AC13 IOSTANDARD LVCMOS33 } [get_ports clock_50] 2 | 3 | create_clock -name clock_50 -period 20 -quiet [get_ports clock_50] 4 | -------------------------------------------------------------------------------- /common/Vivado/constraints/RK-XCKU5P-F/Config.xdc: -------------------------------------------------------------------------------- 1 | set_property CFGBVS GND [current_design] 2 | set_property CONFIG_VOLTAGE 1.8 [current_design] 3 | set_property CONFIG_MODE SPIx4 [current_design] 4 | set_property BITSTREAM.CONFIG.CONFIGRATE 85.0 [current_design] 5 | set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN Disable [current_design] 6 | set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design] 7 | set_property BITSTREAM.CONFIG.UNUSEDPIN Pullnone [current_design] 8 | set_property BITSTREAM.GENERAL.COMPRESS True [current_design] 9 | -------------------------------------------------------------------------------- /common/Vivado/constraints/RK-XCKU5P-F/Key.xdc: -------------------------------------------------------------------------------- 1 | set_property PACKAGE_PIN K9 [get_ports key[0]] 2 | set_property PACKAGE_PIN K10 [get_ports key[1]] 3 | set_property PACKAGE_PIN J10 [get_ports key[1]] 4 | set_property PACKAGE_PIN J11 [get_ports key[1]] 5 | set_property IOSTANDARD LVCMOS33 [get_ports key[*]] 6 | -------------------------------------------------------------------------------- /common/Vivado/constraints/RK-XCKU5P-F/LED.xdc: -------------------------------------------------------------------------------- 1 | set_property PACKAGE_PIN H9 [get_ports led[0]] 2 | set_property PACKAGE_PIN J9 [get_ports led[1]] 3 | set_property PACKAGE_PIN G11 [get_ports led[2]] 4 | set_property PACKAGE_PIN H11 [get_ports led[3]] 5 | set_property IOSTANDARD LVCMOS33 [get_ports led[*]] 6 | -------------------------------------------------------------------------------- /common/Vivado/constraints/RK-XCKU5P-F/QSFP.xdc: -------------------------------------------------------------------------------- 1 | # Bank 225, X0Y4~X0Y7 2 | 3 | # 156.25MHz 4 | set_property PACKAGE_PIN V7 [get_ports qsfp_refclk_p] 5 | set_property PACKAGE_PIN V6 [get_ports qsfp_refclk_n] 6 | 7 | create_clock -name qsfp_refclk -period 6.4 [get_ports qsfp_refclk_p] 8 | 9 | set_property PACKAGE_PIN Y2 [get_ports qsfp_rxp[0]] 10 | set_property PACKAGE_PIN Y1 [get_ports qsfp_rxn[0]] 11 | set_property PACKAGE_PIN V2 [get_ports qsfp_rxp[1]] 12 | set_property PACKAGE_PIN V1 [get_ports qsfp_rxn[1]] 13 | set_property PACKAGE_PIN T2 [get_ports qsfp_rxp[2]] 14 | set_property PACKAGE_PIN T1 [get_ports qsfp_rxn[2]] 15 | set_property PACKAGE_PIN P2 [get_ports qsfp_rxp[3]] 16 | set_property PACKAGE_PIN P1 [get_ports qsfp_rxn[3]] 17 | 18 | set_property PACKAGE_PIN AA5 [get_ports qsfp_txp[0]] 19 | set_property PACKAGE_PIN AA4 [get_ports qsfp_txn[0]] 20 | set_property PACKAGE_PIN W5 [get_ports qsfp_txp[1]] 21 | set_property PACKAGE_PIN W4 [get_ports qsfp_txn[1]] 22 | set_property PACKAGE_PIN U5 [get_ports qsfp_txp[2]] 23 | set_property PACKAGE_PIN U4 [get_ports qsfp_txn[2]] 24 | set_property PACKAGE_PIN R5 [get_ports qsfp_txp[3]] 25 | set_property PACKAGE_PIN R4 [get_ports qsfp_txn[3]] 26 | 27 | set_property -dict { PACKAGE_PIN AA13 IOSTANDARD LVCMOS33 } [get_ports qsfp_modprsl] 28 | set_property -dict { PACKAGE_PIN Y13 IOSTANDARD LVCMOS33 } [get_ports qsfp_intl] 29 | set_property -dict { PACKAGE_PIN W13 IOSTANDARD LVCMOS33 } [get_ports qsfp_modsell] 30 | set_property -dict { PACKAGE_PIN W12 IOSTANDARD LVCMOS33 } [get_ports qsfp_resetl] 31 | set_property -dict { PACKAGE_PIN W14 IOSTANDARD LVCMOS33 } [get_ports qsfp_lpmode] 32 | set_property -dict { PACKAGE_PIN AE15 IOSTANDARD LVCMOS33 } [get_ports qsfp_scl] 33 | set_property -dict { PACKAGE_PIN AE13 IOSTANDARD LVCMOS33 } [get_ports qsfp_sda] 34 | -------------------------------------------------------------------------------- /common/Vivado/scripts/Flash.tcl: -------------------------------------------------------------------------------- 1 | set CONFIG_PATH [lindex $argv 0] 2 | set BITSTREAM_PATH [lindex $argv 1] 3 | 4 | source $CONFIG_PATH 5 | 6 | open_hw_manager 7 | connect_hw_server -allow_non_jtag 8 | open_hw_target 9 | 10 | set HW_DEVICE [lindex [get_hw_devices $HW_DEVICE_NAME] 0] 11 | current_hw_device $HW_DEVICE 12 | 13 | set CFGMEM_PART [lindex [get_cfgmem_parts $CFGMEM_PART_NAME] 0] 14 | 15 | set HW_CFGMEM [create_hw_cfgmem -hw_device $HW_DEVICE -mem_dev $CFGMEM_PART] 16 | 17 | set_property PROGRAM.FILES $BITSTREAM_PATH/$TOP_NAME.bin $HW_CFGMEM 18 | set_property PROGRAM.ADDRESS_RANGE use_file $HW_CFGMEM 19 | set_property PROGRAM.BLANK_CHECK 0 $HW_CFGMEM 20 | set_property PROGRAM.ERASE 1 $HW_CFGMEM 21 | set_property PROGRAM.CFG_PROGRAM 1 $HW_CFGMEM 22 | set_property PROGRAM.VERIFY 1 $HW_CFGMEM 23 | set_property PROGRAM.UNUSED_PIN_TERMINATION pull-none $HW_CFGMEM 24 | 25 | program_hw_devices $HW_DEVICE 26 | 27 | program_hw_cfgmem -hw_cfgmem $HW_CFGMEM 28 | 29 | refresh_hw_device $HW_DEVICE 30 | 31 | boot_hw_device $HW_DEVICE 32 | -------------------------------------------------------------------------------- /common/Vivado/scripts/GenerateBitstream.tcl: -------------------------------------------------------------------------------- 1 | set CONFIG_PATH [lindex $argv 0] 2 | set BITSTREAM_PATH [lindex $argv 1] 3 | 4 | source $CONFIG_PATH 5 | 6 | open_project $PROJECT_NAME.xpr 7 | open_run impl_1 8 | 9 | file mkdir $BITSTREAM_PATH 10 | write_bitstream -force -bin_file $BITSTREAM_PATH/$TOP_NAME.bit 11 | -------------------------------------------------------------------------------- /common/Vivado/scripts/Implementation.tcl: -------------------------------------------------------------------------------- 1 | set CONFIG_PATH [lindex $argv 0] 2 | set JOBS [lindex $argv 1] 3 | 4 | source $CONFIG_PATH 5 | 6 | open_project $PROJECT_NAME.xpr 7 | reset_run impl_1 8 | launch_runs -jobs $JOBS impl_1 9 | wait_on_run impl_1 10 | -------------------------------------------------------------------------------- /common/Vivado/scripts/Program.tcl: -------------------------------------------------------------------------------- 1 | set CONFIG_PATH [lindex $argv 0] 2 | set BITSTREAM_PATH [lindex $argv 1] 3 | 4 | source $CONFIG_PATH 5 | 6 | open_hw_manager 7 | connect_hw_server -allow_non_jtag 8 | open_hw_target 9 | 10 | set HW_DEVICE [lindex [get_hw_devices $HW_DEVICE_NAME] 0] 11 | current_hw_device $HW_DEVICE 12 | 13 | set_property PROGRAM.FILE $BITSTREAM_PATH/$TOP_NAME.bit $HW_DEVICE 14 | 15 | program_hw_devices $HW_DEVICE 16 | 17 | refresh_hw_device $HW_DEVICE 18 | -------------------------------------------------------------------------------- /common/Vivado/scripts/Synthesis.tcl: -------------------------------------------------------------------------------- 1 | set CONFIG_PATH [lindex $argv 0] 2 | set JOBS [lindex $argv 1] 3 | 4 | source $CONFIG_PATH 5 | 6 | open_project $PROJECT_NAME.xpr 7 | reset_run synth_1 8 | launch_runs -jobs $JOBS synth_1 9 | wait_on_run synth_1 10 | --------------------------------------------------------------------------------