├── cl_chronos ├── validation │ ├── inputs │ │ └── .keep │ ├── runs │ │ └── .gitignore │ ├── synth │ │ └── .gitignore │ ├── scripts │ │ ├── build_scripts │ │ │ ├── checkpoints │ │ │ │ └── to_aws │ │ │ │ │ └── .keep │ │ │ ├── constraints │ │ │ │ ├── cl_synth_user.xdc │ │ │ │ └── cl_pnr_user.xdc │ │ │ ├── src_post_encryption │ │ │ │ └── .gitignore │ │ │ ├── scripts │ │ │ │ ├── local_synth.sh │ │ │ │ ├── set_app.py │ │ │ │ └── encrypt.tcl │ │ │ └── run_synth.py │ │ ├── README.txt │ │ ├── apps.txt │ │ ├── sample_chronos_runtimes.txt │ │ ├── launch_synth.py │ │ ├── experiments.txt │ │ ├── gen_synth.py │ │ ├── run_validation.py │ │ └── run.py │ └── baselines │ │ ├── fetch_baselines.py │ │ ├── runtime_ref.txt │ │ └── README.txt ├── build │ ├── constraints │ │ ├── cl_synth_user.xdc │ │ └── cl_pnr_user.xdc │ ├── src_post_encryption │ │ └── .gitignore │ └── scripts │ │ ├── local_synth.sh │ │ ├── set_app.py │ │ ├── delete_afis.sh │ │ └── encrypt.tcl ├── riscv_code │ ├── color-nonspec │ │ ├── pipe.c │ │ └── Makefile │ ├── color │ │ └── Makefile │ ├── des │ │ └── Makefile │ ├── maxflow │ │ └── Makefile │ ├── color-pull │ │ └── Makefile │ ├── silo │ │ └── Makefile │ ├── sssp │ │ ├── Makefile │ │ └── main.c │ └── include │ │ └── simulator.h ├── software │ ├── runtime │ │ ├── load_driver.sh │ │ ├── agfi_list.txt │ │ ├── Makefile │ │ └── serialize_enq.py │ └── verif_rtl │ │ ├── Makefile │ │ ├── src │ │ ├── test_null.c │ │ └── test_swarm.c │ │ └── include │ │ └── sh_dpi_tasks.h ├── tools │ ├── silo_gen │ │ ├── generate_files.sh │ │ └── Makefile │ └── graph_gen │ │ └── Makefile ├── hls │ ├── astar │ │ ├── sssp_prj │ │ │ └── vivado_hls.app │ │ ├── astar_prj │ │ │ └── vivado_hls.app │ │ ├── run_sim.tcl │ │ ├── run_hls.tcl │ │ └── astar.h │ └── sssp │ │ ├── sssp_prj │ │ └── vivado_hls.app │ │ ├── run_hls.tcl │ │ └── sssp.h ├── design │ ├── apps │ │ ├── astar │ │ │ ├── astar_dist_mul_mukbM.v │ │ │ ├── astar.f │ │ │ ├── config_pipe.vh │ │ │ ├── astar_dist_mul_22g8j.v │ │ │ ├── astar_dist_mul_31pcA.v │ │ │ ├── astar_dist_mul_36eOg.v │ │ │ ├── config.vh │ │ │ ├── astar_dist_mul_31lbW.v │ │ │ ├── astar_dist_mul_31ocq.v │ │ │ ├── astar_dist_mul_23hbi.v │ │ │ ├── astar_dist_mul_36ibs.v │ │ │ ├── astar_dist_mul_31mb6.v │ │ │ ├── sinf_or_cosf_32_3cud.v │ │ │ ├── sinf_or_cosf_32_3dEe.v │ │ │ ├── astar_dist_mul_31ncg.v │ │ │ ├── sinf_or_cosf_32_3bkb.v │ │ │ ├── astar_dist_mux_83fYi.v │ │ │ ├── sinf_or_cosf_32_3dEe_rom.dat │ │ │ ├── sinf_or_cosf_32_3cud_rom.dat │ │ │ ├── astar_dist_mux_16jbC.v │ │ │ ├── sinf_or_cosf_32_3bkb_rom.dat │ │ │ └── terminate_core.sv │ │ ├── sssp_hls │ │ │ └── config.vh │ │ ├── sssp │ │ │ ├── config.vh │ │ │ └── config_pipe.vh │ │ ├── des │ │ │ ├── config.vh │ │ │ ├── config_pipe.vh │ │ │ └── des_common.sv │ │ ├── color │ │ │ ├── config.vh │ │ │ └── config_pipe.vh │ │ ├── silo │ │ │ ├── config.vh │ │ │ └── config_pipe.vh │ │ ├── maxflow │ │ │ ├── config.vh │ │ │ └── config_pipe.vh │ │ └── riscv │ │ │ ├── config.vh │ │ │ └── GenSwarm.scala │ ├── cl_chronos_defines.vh │ ├── prefetcher.sv │ ├── cl_id_defines.vh │ ├── gvt_arbiter.sv │ ├── derived.vh │ ├── spill_config.vh │ ├── types.vh │ ├── task_type_fifo.sv │ ├── mem_arbiter.sv │ └── task_xbar.sv ├── misc │ ├── licence_header.h │ └── inject_license.py └── verif │ ├── scripts │ ├── waves.tcl │ ├── Makefile │ ├── Makefile.vcs │ ├── Makefile.vivado │ ├── Makefile.questa │ ├── Makefile.ies │ ├── top.questa.f │ └── top.vcs.f │ └── tests │ ├── test_null.sv │ └── module_task_unit.sv ├── talk.pptx ├── asplos20_chronos.pdf ├── aws_setup.sh ├── install.sh └── .gitignore /cl_chronos/validation/inputs/.keep: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /cl_chronos/validation/runs/.gitignore: -------------------------------------------------------------------------------- 1 | * 2 | !.gitignore 3 | -------------------------------------------------------------------------------- /cl_chronos/validation/synth/.gitignore: -------------------------------------------------------------------------------- 1 | * 2 | !.gitignore 3 | -------------------------------------------------------------------------------- /cl_chronos/validation/scripts/build_scripts/checkpoints/to_aws/.keep: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /talk.pptx: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/SwarmArch/chronos/HEAD/talk.pptx -------------------------------------------------------------------------------- /asplos20_chronos.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/SwarmArch/chronos/HEAD/asplos20_chronos.pdf -------------------------------------------------------------------------------- /aws_setup.sh: -------------------------------------------------------------------------------- 1 | export CL_DIR=$(pwd)/cl_chronos 2 | source aws-fpga/hdk_setup.sh 3 | source aws-fpga/sdk_setup.sh 4 | -------------------------------------------------------------------------------- /cl_chronos/build/constraints/cl_synth_user.xdc: -------------------------------------------------------------------------------- 1 | # This contains the CL specific constraints for synthesis at the CL level 2 | 3 | 4 | -------------------------------------------------------------------------------- /cl_chronos/build/src_post_encryption/.gitignore: -------------------------------------------------------------------------------- 1 | # Ignore everything in this directory 2 | * 3 | # Except this file 4 | !.gitignore 5 | -------------------------------------------------------------------------------- /cl_chronos/riscv_code/color-nonspec/pipe.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/SwarmArch/chronos/HEAD/cl_chronos/riscv_code/color-nonspec/pipe.c -------------------------------------------------------------------------------- /cl_chronos/software/runtime/load_driver.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | rmmod edma-drv 3 | insmod /home/centos/aws-fpga/sdk/linux_kernel_drivers/edma/edma-drv.ko 4 | -------------------------------------------------------------------------------- /cl_chronos/validation/scripts/build_scripts/constraints/cl_synth_user.xdc: -------------------------------------------------------------------------------- 1 | # This contains the CL specific constraints for synthesis at the CL level 2 | 3 | 4 | -------------------------------------------------------------------------------- /cl_chronos/validation/scripts/build_scripts/src_post_encryption/.gitignore: -------------------------------------------------------------------------------- 1 | # Ignore everything in this directory 2 | * 3 | # Except this file 4 | !.gitignore 5 | -------------------------------------------------------------------------------- /cl_chronos/validation/scripts/README.txt: -------------------------------------------------------------------------------- 1 | This directory contains the scripts necessary to validate the results in the 2 | paper. Please see the master script 'run_validation.py' for more details. 3 | -------------------------------------------------------------------------------- /cl_chronos/validation/baselines/fetch_baselines.py: -------------------------------------------------------------------------------- 1 | import os 2 | 3 | AWS_PATH = "aws" 4 | os.system(AWS_PATH+" s3 sync s3://chronos-baselines/ .") 5 | os.system("chmod +x binaries/*") 6 | 7 | #Also available at ://doi.org/10.5281/zenodo.3563190 8 | -------------------------------------------------------------------------------- /cl_chronos/build/scripts/local_synth.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | if [ "$#" -ne 1 ]; then 3 | echo "Usage: local_synth.sh module" >&2 4 | exit 1 5 | fi 6 | ./aws_build_dcp_from_cl.sh -ignore_memory_requirement -foreground -script local_synth.tcl -module $1 7 | 8 | -------------------------------------------------------------------------------- /cl_chronos/validation/scripts/build_scripts/scripts/local_synth.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | if [ "$#" -ne 1 ]; then 3 | echo "Usage: local_synth.sh module" >&2 4 | exit 1 5 | fi 6 | ./aws_build_dcp_from_cl.sh -ignore_memory_requirement -foreground -script local_synth.tcl -module $1 7 | 8 | -------------------------------------------------------------------------------- /cl_chronos/tools/silo_gen/generate_files.sh: -------------------------------------------------------------------------------- 1 | 2 | make 3 | ./silo_gen 4 | cp silo_tx ../../verif/sim/test_chronos 5 | cp silo_tx ../../riscv_code/silo/silo_small_ref 6 | (cd ../../riscv_code/silo/; ./silo_sim silo_small_ref silo_small_out > log;) 7 | (cd ../../riscv_code/silo/; cp silo_small_out ../../verif/sim/test_chronos/silo_ref;) 8 | 9 | -------------------------------------------------------------------------------- /cl_chronos/build/scripts/set_app.py: -------------------------------------------------------------------------------- 1 | import sys, os 2 | if len(sys.argv) < 2: 3 | print("Usage set_app.py app") 4 | exit(0) 5 | app = sys.argv[1] 6 | 7 | cmd1 = "cp ../../design/apps/%s/config.vh ../../design/app_config.vh" % app 8 | cmd2 = "cp %s_config.sv ../../design/config.sv" % app 9 | 10 | print(cmd1) 11 | print(cmd2) 12 | 13 | os.system(cmd1) 14 | os.system(cmd2) 15 | -------------------------------------------------------------------------------- /cl_chronos/validation/scripts/build_scripts/scripts/set_app.py: -------------------------------------------------------------------------------- 1 | import sys, os 2 | if len(sys.argv) < 2: 3 | print("Usage set_app.py app") 4 | exit(0) 5 | app = sys.argv[1] 6 | 7 | cmd1 = "cp ../../design/apps/%s/config.vh ../../design/app_config.vh" % app 8 | cmd2 = "cp %s_config.sv ../../design/config.sv" % app 9 | 10 | print(cmd1) 11 | print(cmd2) 12 | 13 | os.system(cmd1) 14 | os.system(cmd2) 15 | -------------------------------------------------------------------------------- /cl_chronos/build/scripts/delete_afis.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | # extract command 4 | ~/.local/bin/aws ec2 describe-fpga-images --owners self --filters \ 5 | "Name=update-time,Values=2019-11-25*" | grep "afi-" | sed 's/\"FpgaImageId\": \"//' | sed 's/\",//g' | sed -e 's/^\s*//' | sed 's/[ \t]*$//' > 2018_afis 6 | 7 | input="2018_afis" 8 | while IFS= read -r var 9 | do 10 | echo "$var" 11 | ~/.local/bin/aws ec2 delete-fpga-image --fpga-image-id "$var" 12 | 13 | done < "$input" 14 | -------------------------------------------------------------------------------- /cl_chronos/validation/scripts/apps.txt: -------------------------------------------------------------------------------- 1 | # Some apps have two configs. 2 | # The larger system is optimized for increased chance of 3 | # routing closure. 4 | 5 | sssp pipe sssp_nr_16t 6 | sssp pipe sssp_nr_6t 7 | astar pipe astar_nr_6t 8 | astar pipe astar_nr_10t 9 | des pipe des_r_8t 10 | des pipe des_r_2t 11 | maxflow pipe maxflow_r_8t 12 | maxflow pipe maxflow_r_2t 13 | 14 | # color pipe color_nr_5t 15 | 16 | # Needed for sensitivity studies 17 | # sssp pipe sssp_r_8t 18 | # astar pipe astar_r_6t 19 | # riscv riscv_nr_4t 20 | # riscv riscv_r_4t 21 | -------------------------------------------------------------------------------- /cl_chronos/validation/scripts/sample_chronos_runtimes.txt: -------------------------------------------------------------------------------- 1 | astar 1 1 525.5444432 2 | astar 1 16 52.3446032 3 | astar 2 16 27.169296 4 | astar 4 16 16.1719344 5 | des 1 1 168.8539136 6 | des 1 16 23.0501488 7 | des 2 16 14.6696016 8 | des 4 16 8.8055504 9 | des 6 16 7.2125312 10 | des 8 16 5.092136 11 | maxflow 1 1 590.112472 12 | maxflow 1 16 113.114616 13 | maxflow 2 16 63.029072 14 | maxflow 4 16 33.4070704 15 | maxflow 6 16 27.6601168 16 | maxflow 8 16 20.6091984 17 | sssp 1 1 8602.8738816 18 | sssp 1 16 1001.6200448 19 | sssp 2 16 481.3461264 20 | sssp 4 16 249.8231056 21 | sssp 8 16 146.9389552 22 | sssp 12 16 111.2121696 23 | sssp 14 16 101.8367616 24 | -------------------------------------------------------------------------------- /cl_chronos/hls/astar/sssp_prj/vivado_hls.app: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | -------------------------------------------------------------------------------- /cl_chronos/hls/sssp/sssp_prj/vivado_hls.app: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | -------------------------------------------------------------------------------- /install.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | if [ -e aws-fpga ] 3 | then 4 | echo "aws-fpga already exists. Not cloning.." 5 | else 6 | git clone https://github.com/aws/aws-fpga.git 7 | fi 8 | 9 | if [ -e aws-fpga/hdk/cl/developer_designs/cl_chronos ] 10 | then 11 | echo "cl_chronos symling already exists. Not creating.." 12 | else 13 | ln -s cl_chronos aws-fpga/hdk/cl/developer_designs/cl_chronos 14 | echo "Creating symlink aws_fpga/hdk/cl/developer_designs/cl_chronos" 15 | fi 16 | 17 | source aws_setup.sh 18 | ## install DMA drivers 19 | # (https://github.com/aws/aws-fpga/blob/master/sdk/linux_kernel_drivers/xdma/xdma_install.md) 20 | sudo rmmod xocl 21 | sudo yum install kernel kernel-devel 22 | (cd aws-fpga/sdk/linux_kernel_drivers/xdma/; make; sudo make install) 23 | sudo modprobe xdma 24 | 25 | ## Needed for plotting 26 | sudo yum install python-matplotlib 27 | -------------------------------------------------------------------------------- /cl_chronos/design/apps/astar/astar_dist_mul_mukbM.v: -------------------------------------------------------------------------------- 1 | 2 | `timescale 1 ns / 1 ps 3 | 4 | module astar_dist_mul_mukbM_DSP48_0(a, b, p); 5 | input signed [15 - 1 : 0] a; // synthesis attribute keep a "true" 6 | input [22 - 1 : 0] b; // synthesis attribute keep b "true" 7 | output signed [37 - 1 : 0] p; // synthesis attribute keep p "true" 8 | 9 | assign p = $signed (a) * $signed ({1'b0, b}); 10 | 11 | endmodule 12 | 13 | `timescale 1 ns / 1 ps 14 | module astar_dist_mul_mukbM( 15 | din0, 16 | din1, 17 | dout); 18 | 19 | parameter ID = 32'd1; 20 | parameter NUM_STAGE = 32'd1; 21 | parameter din0_WIDTH = 32'd1; 22 | parameter din1_WIDTH = 32'd1; 23 | parameter dout_WIDTH = 32'd1; 24 | input[din0_WIDTH - 1:0] din0; 25 | input[din1_WIDTH - 1:0] din1; 26 | output[dout_WIDTH - 1:0] dout; 27 | 28 | 29 | 30 | astar_dist_mul_mukbM_DSP48_0 astar_dist_mul_mukbM_DSP48_0_U( 31 | .a( din0 ), 32 | .b( din1 ), 33 | .p( dout )); 34 | 35 | endmodule 36 | 37 | -------------------------------------------------------------------------------- /cl_chronos/tools/graph_gen/Makefile: -------------------------------------------------------------------------------- 1 | # Amazon FPGA Hardware Development Kit 2 | # 3 | # Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. 4 | # 5 | # Licensed under the Amazon Software License (the "License"). You may not use 6 | # this file except in compliance with the License. A copy of the License is 7 | # located at 8 | # 9 | # http://aws.amazon.com/asl/ 10 | # 11 | # or in the "license" file accompanying this file. This file is distributed on 12 | # an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or 13 | # implied. See the License for the specific language governing permissions and 14 | # limitations under the License. 15 | 16 | #VPATH = src:include:$(HDK_DIR)/common/software/src:$(HDK_DIR)/common/software/include 17 | 18 | CC = g++ 19 | CFLAGS = -std=c++11 -O3 -Wall 20 | 21 | LDLIBS = -lrt -lpthread 22 | 23 | SRC = graph_gen.cpp 24 | OBJ = $(SRC:.c=.o) 25 | BIN = graph_gen 26 | 27 | all: $(BIN) 28 | 29 | $(BIN): $(OBJ) 30 | $(CC) $(CFLAGS) -o $@ $^ $(LDFLAGS) $(LDLIBS) 31 | 32 | clean: 33 | rm -f *.o $(BIN) 34 | 35 | -------------------------------------------------------------------------------- /cl_chronos/validation/baselines/runtime_ref.txt: -------------------------------------------------------------------------------- 1 | des 1 632 2 | des 2 332 3 | des 4 177 4 | des 6 129 5 | des 8 108 6 | des 10 96 7 | des 15 88 8 | des 20 89 9 | des 25 90 10 | des 30 99 11 | des 35 111 12 | des 40 123 13 | astar 1 891 14 | astar 2 394 15 | astar 4 201 16 | astar 6 161 17 | astar 8 98 18 | astar 10 97 19 | astar 15 61 20 | astar 20 49 21 | astar 25 46 22 | astar 30 44 23 | astar 35 42 24 | astar 40 42 25 | maxflow 1 80 26 | maxflow 2 110 27 | maxflow 4 83 28 | maxflow 6 78 29 | maxflow 8 81 30 | maxflow 10 87 31 | maxflow 15 117 32 | maxflow 20 139 33 | maxflow 25 177 34 | maxflow 30 217 35 | maxflow 35 249 36 | maxflow 40 287 37 | color 1 213.086 38 | color 2 124.9 39 | color 4 65.776 40 | color 6 48.614 41 | color 8 39.142 42 | color 10 34.312 43 | color 15 26.476 44 | color 20 23.58 45 | color 25 23.196 46 | color 30 24.45 47 | color 35 25.74 48 | color 40 26.676 49 | sssp 1 3831 50 | sssp 2 2171 51 | sssp 4 1123 52 | sssp 6 759 53 | sssp 8 578 54 | sssp 10 470 55 | sssp 15 381 56 | sssp 20 310 57 | sssp 25 301 58 | sssp 30 289 59 | sssp 35 288 60 | sssp 40 291 61 | -------------------------------------------------------------------------------- /cl_chronos/tools/silo_gen/Makefile: -------------------------------------------------------------------------------- 1 | # Amazon FPGA Hardware Development Kit 2 | # 3 | # Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. 4 | # 5 | # Licensed under the Amazon Software License (the "License"). You may not use 6 | # this file except in compliance with the License. A copy of the License is 7 | # located at 8 | # 9 | # http://aws.amazon.com/asl/ 10 | # 11 | # or in the "license" file accompanying this file. This file is distributed on 12 | # an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or 13 | # implied. See the License for the specific language governing permissions and 14 | # limitations under the License. 15 | 16 | #VPATH = src:include:$(HDK_DIR)/common/software/src:$(HDK_DIR)/common/software/include 17 | 18 | CC = g++ 19 | CFLAGS = -std=c++11 -O3 -Wall 20 | 21 | LDLIBS = -lrt -lpthread 22 | 23 | SRC = silo_gen.cpp silo_gen.h 24 | OBJ = $(SRC:.c=.o) 25 | BIN = silo_gen 26 | 27 | all: $(BIN) 28 | 29 | $(BIN): $(OBJ) 30 | $(CC) $(CFLAGS) -o $@ $^ $(LDFLAGS) $(LDLIBS) 31 | 32 | clean: 33 | rm -f *.o $(BIN) 34 | 35 | -------------------------------------------------------------------------------- /cl_chronos/misc/licence_header.h: -------------------------------------------------------------------------------- 1 | /** $lic$ 2 | * Copyright (C) 2014-2019 by Massachusetts Institute of Technology 3 | * 4 | * This file is part of the Chronos FPGA Acceleration Framework. 5 | * 6 | * Chronos is free software; you can redistribute it and/or modify it under the 7 | * terms of the GNU General Public License as published by the Free Software 8 | * Foundation, version 2. 9 | * 10 | * If you use this framework in your research, we request that you reference 11 | * the Chronos paper ("Chronos: Efficient Speculative Parallelism for 12 | * Accelerators", Abeydeera and Sanchez, ASPLOS-25, March 2020), and that 13 | * you send us a citation of your work. 14 | * 15 | * Chronos is distributed in the hope that it will be useful, but WITHOUT ANY 16 | * WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS 17 | * FOR A PARTICULAR PURPOSE. See the GNU General Public License for more 18 | * details. 19 | * 20 | * You should have received a copy of the GNU General Public License along with 21 | * this program. If not, see . 22 | */ 23 | 24 | -------------------------------------------------------------------------------- /cl_chronos/software/verif_rtl/Makefile: -------------------------------------------------------------------------------- 1 | # Amazon FPGA Hardware Development Kit 2 | # 3 | # Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. 4 | # 5 | # Licensed under the Amazon Software License (the "License"). You may not use 6 | # this file except in compliance with the License. A copy of the License is 7 | # located at 8 | # 9 | # http://aws.amazon.com/asl/ 10 | # 11 | # or in the "license" file accompanying this file. This file is distributed on 12 | # an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or 13 | # implied. See the License for the specific language governing permissions and 14 | # limitations under the License. 15 | 16 | 17 | VPATH = src:include:$(HDK_DIR)/common/software/src:$(HDK_DIR)/common/software/include 18 | 19 | C_SRCS := test_hello_world.c pcie_utils.c cl_utils.c main.c 20 | C_OBJS := $(C_SRCS:.c=.o) 21 | 22 | CC = gcc 23 | CFLAGS = -I ./include 24 | CFLAGS += -I $(HDK_DIR)/common/software/include 25 | all: test_hello_world 26 | 27 | test_hello_world: $(C_SRCS) 28 | $(CC) $(CFLAGS) -o $@ $^ 29 | 30 | clean: 31 | rm test_hello_world 32 | -------------------------------------------------------------------------------- /cl_chronos/hls/astar/astar_prj/vivado_hls.app: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | -------------------------------------------------------------------------------- /cl_chronos/design/apps/astar/astar.f: -------------------------------------------------------------------------------- 1 | ${CL_ROOT}/design/apps/astar/astar_dist.v 2 | ${CL_ROOT}/design/apps/astar/astar_dist_mul_22g8j.v 3 | ${CL_ROOT}/design/apps/astar/astar_dist_mul_23hbi.v 4 | ${CL_ROOT}/design/apps/astar/astar_dist_mul_31pcA.v 5 | ${CL_ROOT}/design/apps/astar/astar_dist_mul_31lbW.v 6 | ${CL_ROOT}/design/apps/astar/astar_dist_mul_31mb6.v 7 | ${CL_ROOT}/design/apps/astar/astar_dist_mul_31ncg.v 8 | ${CL_ROOT}/design/apps/astar/astar_dist_mul_31ocq.v 9 | ${CL_ROOT}/design/apps/astar/astar_dist_mul_36eOg.v 10 | ${CL_ROOT}/design/apps/astar/astar_dist_mul_36ibs.v 11 | ${CL_ROOT}/design/apps/astar/astar_dist_mul_mukbM.v 12 | ${CL_ROOT}/design/apps/astar/astar_dist_mux_16jbC.v 13 | ${CL_ROOT}/design/apps/astar/astar_dist_mux_83fYi.v 14 | ${CL_ROOT}/design/apps/astar/cordic_base.v 15 | ${CL_ROOT}/design/apps/astar/fxp_sqrt.v 16 | ${CL_ROOT}/design/apps/astar/fxp_sqrt_1.v 17 | ${CL_ROOT}/design/apps/astar/sinf_or_cosf_32_3_s.v 18 | ${CL_ROOT}/design/apps/astar/sinf_or_cosf_32_3dEe.v 19 | ${CL_ROOT}/design/apps/astar/sinf_or_cosf_32_3cud.v 20 | ${CL_ROOT}/design/apps/astar/sinf_or_cosf_32_3bkb.v 21 | ${CL_ROOT}/design/apps/astar/terminate_core.sv 22 | -------------------------------------------------------------------------------- /cl_chronos/design/apps/sssp_hls/config.vh: -------------------------------------------------------------------------------- 1 | /** $lic$ 2 | * Copyright (C) 2014-2019 by Massachusetts Institute of Technology 3 | * 4 | * This file is part of the Chronos FPGA Acceleration Framework. 5 | * 6 | * Chronos is free software; you can redistribute it and/or modify it under the 7 | * terms of the GNU General Public License as published by the Free Software 8 | * Foundation, version 2. 9 | * 10 | * If you use this framework in your research, we request that you reference 11 | * the Chronos paper ("Chronos: Efficient Speculative Parallelism for 12 | * Accelerators", Abeydeera and Sanchez, ASPLOS-25, March 2020), and that 13 | * you send us a citation of your work. 14 | * 15 | * Chronos is distributed in the hope that it will be useful, but WITHOUT ANY 16 | * WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS 17 | * FOR A PARTICULAR PURPOSE. See the GNU General Public License for more 18 | * details. 19 | * 20 | * You should have received a copy of the GNU General Public License along with 21 | * this program. If not, see . 22 | */ 23 | 24 | ARG_WIDTH 1 25 | 26 | core sssp_hls 8 27 | -------------------------------------------------------------------------------- /cl_chronos/design/apps/sssp/config.vh: -------------------------------------------------------------------------------- 1 | /** $lic$ 2 | * Copyright (C) 2014-2019 by Massachusetts Institute of Technology 3 | * 4 | * This file is part of the Chronos FPGA Acceleration Framework. 5 | * 6 | * Chronos is free software; you can redistribute it and/or modify it under the 7 | * terms of the GNU General Public License as published by the Free Software 8 | * Foundation, version 2. 9 | * 10 | * If you use this framework in your research, we request that you reference 11 | * the Chronos paper ("Chronos: Efficient Speculative Parallelism for 12 | * Accelerators", Abeydeera and Sanchez, ASPLOS-25, March 2020), and that 13 | * you send us a citation of your work. 14 | * 15 | * Chronos is distributed in the hope that it will be useful, but WITHOUT ANY 16 | * WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS 17 | * FOR A PARTICULAR PURPOSE. See the GNU General Public License for more 18 | * details. 19 | * 20 | * You should have received a copy of the GNU General Public License along with 21 | * this program. If not, see . 22 | */ 23 | 24 | ARG_WIDTH 1 25 | APP_ID 0 26 | 27 | core sssp_core 8 28 | -------------------------------------------------------------------------------- /cl_chronos/verif/scripts/waves.tcl: -------------------------------------------------------------------------------- 1 | # Amazon FPGA Hardware Development Kit 2 | # 3 | # Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. 4 | # 5 | # Licensed under the Amazon Software License (the "License"). You may not use 6 | # this file except in compliance with the License. A copy of the License is 7 | # located at 8 | # 9 | # http://aws.amazon.com/asl/ 10 | # 11 | # or in the "license" file accompanying this file. This file is distributed on 12 | # an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or 13 | # implied. See the License for the specific language governing permissions and 14 | # limitations under the License. 15 | 16 | set curr_wave [current_wave_config] 17 | if { [string length $curr_wave] == 0 } { 18 | if { [llength [get_objects]] > 0} { 19 | add_wave / 20 | set_property needs_save false [current_wave_config] 21 | } else { 22 | send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." 23 | } 24 | } 25 | 26 | run 200 us 27 | quit 28 | -------------------------------------------------------------------------------- /cl_chronos/design/apps/des/config.vh: -------------------------------------------------------------------------------- 1 | /** $lic$ 2 | * Copyright (C) 2014-2019 by Massachusetts Institute of Technology 3 | * 4 | * This file is part of the Chronos FPGA Acceleration Framework. 5 | * 6 | * Chronos is free software; you can redistribute it and/or modify it under the 7 | * terms of the GNU General Public License as published by the Free Software 8 | * Foundation, version 2. 9 | * 10 | * If you use this framework in your research, we request that you reference 11 | * the Chronos paper ("Chronos: Efficient Speculative Parallelism for 12 | * Accelerators", Abeydeera and Sanchez, ASPLOS-25, March 2020), and that 13 | * you send us a citation of your work. 14 | * 15 | * Chronos is distributed in the hope that it will be useful, but WITHOUT ANY 16 | * WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS 17 | * FOR A PARTICULAR PURPOSE. See the GNU General Public License for more 18 | * details. 19 | * 20 | * You should have received a copy of the GNU General Public License along with 21 | * this program. If not, see . 22 | */ 23 | 24 | ARG_WIDTH 16 25 | APP_ID 1 26 | 27 | core des_core 7 28 | core des_enqueuer 1 29 | -------------------------------------------------------------------------------- /cl_chronos/design/apps/color/config.vh: -------------------------------------------------------------------------------- 1 | /** $lic$ 2 | * Copyright (C) 2014-2019 by Massachusetts Institute of Technology 3 | * 4 | * This file is part of the Chronos FPGA Acceleration Framework. 5 | * 6 | * Chronos is free software; you can redistribute it and/or modify it under the 7 | * terms of the GNU General Public License as published by the Free Software 8 | * Foundation, version 2. 9 | * 10 | * If you use this framework in your research, we request that you reference 11 | * the Chronos paper ("Chronos: Efficient Speculative Parallelism for 12 | * Accelerators", Abeydeera and Sanchez, ASPLOS-25, March 2020), and that 13 | * you send us a citation of your work. 14 | * 15 | * Chronos is distributed in the hope that it will be useful, but WITHOUT ANY 16 | * WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS 17 | * FOR A PARTICULAR PURPOSE. See the GNU General Public License for more 18 | * details. 19 | * 20 | * You should have received a copy of the GNU General Public License along with 21 | * this program. If not, see . 22 | */ 23 | 24 | ARG_WIDTH 32 25 | APP_ID 4 26 | # core module_name num_cores 27 | core color 8 all_tasks 28 | -------------------------------------------------------------------------------- /cl_chronos/design/apps/silo/config.vh: -------------------------------------------------------------------------------- 1 | /** $lic$ 2 | * Copyright (C) 2014-2019 by Massachusetts Institute of Technology 3 | * 4 | * This file is part of the Chronos FPGA Acceleration Framework. 5 | * 6 | * Chronos is free software; you can redistribute it and/or modify it under the 7 | * terms of the GNU General Public License as published by the Free Software 8 | * Foundation, version 2. 9 | * 10 | * If you use this framework in your research, we request that you reference 11 | * the Chronos paper ("Chronos: Efficient Speculative Parallelism for 12 | * Accelerators", Abeydeera and Sanchez, ASPLOS-25, March 2020), and that 13 | * you send us a citation of your work. 14 | * 15 | * Chronos is distributed in the hope that it will be useful, but WITHOUT ANY 16 | * WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS 17 | * FOR A PARTICULAR PURPOSE. See the GNU General Public License for more 18 | * details. 19 | * 20 | * You should have received a copy of the GNU General Public License along with 21 | * this program. If not, see . 22 | */ 23 | 24 | ARG_WIDTH 32 25 | APP_ID 4 26 | # core module_name num_cores 27 | core color 8 all_tasks 28 | -------------------------------------------------------------------------------- /cl_chronos/software/runtime/agfi_list.txt: -------------------------------------------------------------------------------- 1 | des_r_2t agfi-09510cc6682c69739 afi-0d6d6ddc1af843a46 2 | sssp_nr_6t agfi-0d3750b6360762108 afi-09d716062d889a9a4 3 | astar_nr_4t agfi-09225490f0ceb7866 afi-04a8021c2ccb68383 4 | maxflow_r_2t agfi-0f6b7bda3d78c727e afi-0f5001e6426b4d534 5 | des_r_2t agfi-02067efe7302cbca5 afi-0d15c9d1d271ccc55 6 | des_r_2t agfi-079ccf0a578de9ad6 afi-02544a72d4d476833 7 | maxflow_r_8t agfi-08c3caa26a9278e52 afi-007793f2f9856139c 8 | maxflow_r_2t agfi-00636be467d984d7f afi-0fb6e4bd4cb5c0125 9 | astar_nr_4t agfi-07535bd12d1158adf afi-0768bdecfec757810 10 | des_r_8t agfi-035f6cc857859d8f8 afi-080cf0ab6192d5f66 11 | sssp_nr_14t agfi-0aee744f3dec319eb afi-099f9521a1865eafc 12 | sssp_nr_16t agfi-058ecc8cdda0fed3f afi-01b8f2d2982d3aa9c 13 | astar_nr_6t agfi-0238f9ced170a0d61 afi-05248d0e6887ffaff 14 | color_nr_6t agfi-0558c89be59b1f676 abcd-fg 15 | riscv_r_4t agfi-02159d0614fb731a9 abcd-fg 16 | riscv_nr_4t agfi-075b2c09a8bc477bc abcd-fg 17 | astar_r_6t agfi-0bac3f3d6fdb338bf abcd-fg 18 | sssp_r_6t agfi-0d0018020b9eed768 abcd-fg 19 | sssp_r_8t agfi-01ed0f2fdee90a514 abcd-fg 20 | riscv_rate_ctrl_nr_4t agfi-00bc8e8fd0139a989 na 21 | astar_nr_1t agfi-0dc1ac81aac25f995 na 22 | sssp_nr_1t agfi-057571a7b52f9a0cd na 23 | -------------------------------------------------------------------------------- /cl_chronos/design/apps/maxflow/config.vh: -------------------------------------------------------------------------------- 1 | /** $lic$ 2 | * Copyright (C) 2014-2019 by Massachusetts Institute of Technology 3 | * 4 | * This file is part of the Chronos FPGA Acceleration Framework. 5 | * 6 | * Chronos is free software; you can redistribute it and/or modify it under the 7 | * terms of the GNU General Public License as published by the Free Software 8 | * Foundation, version 2. 9 | * 10 | * If you use this framework in your research, we request that you reference 11 | * the Chronos paper ("Chronos: Efficient Speculative Parallelism for 12 | * Accelerators", Abeydeera and Sanchez, ASPLOS-25, March 2020), and that 13 | * you send us a citation of your work. 14 | * 15 | * Chronos is distributed in the hope that it will be useful, but WITHOUT ANY 16 | * WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS 17 | * FOR A PARTICULAR PURPOSE. See the GNU General Public License for more 18 | * details. 19 | * 20 | * You should have received a copy of the GNU General Public License along with 21 | * this program. If not, see . 22 | */ 23 | 24 | ARG_WIDTH 64 25 | DATA_WIDTH 64 26 | APP_ID 3 27 | 28 | # core module_name num_cores 29 | core maxflow 8 all_tasks 30 | -------------------------------------------------------------------------------- /cl_chronos/riscv_code/color/Makefile: -------------------------------------------------------------------------------- 1 | # Amazon FPGA Hardware Development Kit 2 | # 3 | # Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. 4 | # 5 | # Licensed under the Amazon Software License (the "License"). You may not use 6 | # this file except in compliance with the License. A copy of the License is 7 | # located at 8 | # 9 | # http://aws.amazon.com/asl/ 10 | # 11 | # or in the "license" file accompanying this file. This file is distributed on 12 | # an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or 13 | # implied. See the License for the specific language governing permissions and 14 | # limitations under the License. 15 | 16 | #VPATH = src:include:$(HDK_DIR)/common/software/src:$(HDK_DIR)/common/software/include 17 | 18 | INCLUDES = -I$(SDK_DIR)/userspace/include 19 | 20 | CC = riscv-none-embed-gcc 21 | CFLAGS = -march=rv32i -mabi=ilp32 -T linker_script 22 | 23 | 24 | SRC = main.c 25 | OBJ = $(SRC:.c=.o) 26 | BIN = main 27 | 28 | all: $(BIN) 29 | 30 | $(BIN): $(OBJ) 31 | $(CC) $(CFLAGS) -O3 -o $^ $(SRC) 32 | riscv-none-embed-objdump -d main.o > main.dump 33 | riscv-none-embed-objcopy --output-target=ihex main.o main.hex 34 | 35 | clean: 36 | rm -f *.o $(BIN) 37 | 38 | -------------------------------------------------------------------------------- /cl_chronos/riscv_code/des/Makefile: -------------------------------------------------------------------------------- 1 | # Amazon FPGA Hardware Development Kit 2 | # 3 | # Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. 4 | # 5 | # Licensed under the Amazon Software License (the "License"). You may not use 6 | # this file except in compliance with the License. A copy of the License is 7 | # located at 8 | # 9 | # http://aws.amazon.com/asl/ 10 | # 11 | # or in the "license" file accompanying this file. This file is distributed on 12 | # an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or 13 | # implied. See the License for the specific language governing permissions and 14 | # limitations under the License. 15 | 16 | #VPATH = src:include:$(HDK_DIR)/common/software/src:$(HDK_DIR)/common/software/include 17 | 18 | INCLUDES = -I$(SDK_DIR)/userspace/include 19 | 20 | CC = riscv-none-embed-gcc 21 | CFLAGS = -march=rv32i -mabi=ilp32 -T linker_script 22 | 23 | 24 | SRC = main.c 25 | OBJ = $(SRC:.c=.o) 26 | BIN = main 27 | 28 | all: $(BIN) 29 | 30 | $(BIN): $(OBJ) 31 | $(CC) $(CFLAGS) -O3 -o $^ $(SRC) 32 | riscv-none-embed-objdump -d main.o > main.dump 33 | riscv-none-embed-objcopy --output-target=ihex main.o main.hex 34 | 35 | clean: 36 | rm -f *.o $(BIN) 37 | 38 | -------------------------------------------------------------------------------- /cl_chronos/riscv_code/maxflow/Makefile: -------------------------------------------------------------------------------- 1 | # Amazon FPGA Hardware Development Kit 2 | # 3 | # Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. 4 | # 5 | # Licensed under the Amazon Software License (the "License"). You may not use 6 | # this file except in compliance with the License. A copy of the License is 7 | # located at 8 | # 9 | # http://aws.amazon.com/asl/ 10 | # 11 | # or in the "license" file accompanying this file. This file is distributed on 12 | # an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or 13 | # implied. See the License for the specific language governing permissions and 14 | # limitations under the License. 15 | 16 | #VPATH = src:include:$(HDK_DIR)/common/software/src:$(HDK_DIR)/common/software/include 17 | 18 | INCLUDES = -I$(SDK_DIR)/userspace/include 19 | 20 | CC = riscv-none-embed-gcc 21 | CFLAGS = -march=rv32i -mabi=ilp32 -T linker_script 22 | 23 | 24 | SRC = main.c 25 | OBJ = $(SRC:.c=.o) 26 | BIN = main 27 | 28 | all: $(BIN) 29 | 30 | $(BIN): $(OBJ) 31 | $(CC) $(CFLAGS) -O3 -o $^ $(SRC) 32 | riscv-none-embed-objdump -d main.o > main.dump 33 | riscv-none-embed-objcopy --output-target=ihex main.o main.hex 34 | 35 | clean: 36 | rm -f *.o $(BIN) 37 | 38 | -------------------------------------------------------------------------------- /cl_chronos/riscv_code/color-pull/Makefile: -------------------------------------------------------------------------------- 1 | # Amazon FPGA Hardware Development Kit 2 | # 3 | # Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. 4 | # 5 | # Licensed under the Amazon Software License (the "License"). You may not use 6 | # this file except in compliance with the License. A copy of the License is 7 | # located at 8 | # 9 | # http://aws.amazon.com/asl/ 10 | # 11 | # or in the "license" file accompanying this file. This file is distributed on 12 | # an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or 13 | # implied. See the License for the specific language governing permissions and 14 | # limitations under the License. 15 | 16 | #VPATH = src:include:$(HDK_DIR)/common/software/src:$(HDK_DIR)/common/software/include 17 | 18 | INCLUDES = -I$(SDK_DIR)/userspace/include 19 | 20 | CC = riscv-none-embed-gcc 21 | CFLAGS = -march=rv32i -mabi=ilp32 -T linker_script 22 | 23 | 24 | SRC = main.c 25 | OBJ = $(SRC:.c=.o) 26 | BIN = main 27 | 28 | all: $(BIN) 29 | 30 | $(BIN): $(OBJ) 31 | $(CC) $(CFLAGS) -O3 -o $^ $(SRC) 32 | riscv-none-embed-objdump -d main.o > main.dump 33 | riscv-none-embed-objcopy --output-target=ihex main.o main.hex 34 | 35 | clean: 36 | rm -f *.o $(BIN) 37 | 38 | -------------------------------------------------------------------------------- /cl_chronos/validation/baselines/README.txt: -------------------------------------------------------------------------------- 1 | Note: All baseline experiments were run on the AWS m4.10xlarge instance, with 2 | the Amazon Linux AMI 2018.03.0. 3 | The authors are happy to provide the reviewers with an access to this instance 4 | if desired. Please contact (maleen@mit.edu) 5 | 6 | All code for baselines are hosted on the shared s3 bucket, "chronos_baselines" 7 | Run fetch_baselines.py to download these. 8 | 9 | Once downloaded, the S3 bucket contains several folders 10 | Galois-2.4/: Contains the source code for sssp, astar and maxflow applications 11 | in Galois-2.4/lonestar/ respectively 12 | Galois-2.1/: Contains source code for des in Galois-2.1/apps/des. 13 | (DES is from an older version of Galois beacuse DES is deprecated in 2.4) 14 | color : Contains source code for baseline graph coloring. 15 | binaries/: Precompiled binaries for the four applications. 16 | inputs/ : Inputs for four applications 17 | run_experiments.py : Runs the binaries with the inputs for all applications at 18 | at various thread counts and writes the runtime to baseline_runtime.txt 19 | baseline_runtime.txt : The result of our experiments. This file is used as an 20 | input to the scripts/plot.py to generate Figure 10 in the paper 21 | 22 | 23 | 24 | -------------------------------------------------------------------------------- /cl_chronos/validation/scripts/launch_synth.py: -------------------------------------------------------------------------------- 1 | 2 | ## Input month-day-index 3 | ## Launches the synth scripts (in ../synth// all in parallel 4 | ## Once a synthesis job is complete, each app would append an entry to the file 5 | ## ../synth//agfi_list.txt 6 | 7 | import sys 8 | import os 9 | if (len(sys.argv) == 1): 10 | print ("Usage: python launch_synth.py ") 11 | exit(0); 12 | 13 | folder = sys.argv[1] 14 | os.chdir("../synth") 15 | dirs = os.listdir(os.getcwd()) 16 | print(dirs) 17 | if folder not in dirs: 18 | print(folder + " not found in ../synth/. Exiting..") 19 | exit(0) 20 | 21 | os.chdir(folder) 22 | print(os.getcwd()) 23 | 24 | apps = os.listdir(os.getcwd()) 25 | print(apps) 26 | cwd = os.getcwd(); 27 | 28 | ## Be very careful in turning this on. Can require astronomical amount of memory 29 | parallel_synth = False 30 | 31 | for app in apps: 32 | print(app) 33 | os.chdir(os.path.join(cwd, app)) 34 | print(os.getcwd()) 35 | if not parallel_synth: 36 | cmd = "python run_synth.py | tee synth_out" 37 | os.system(cmd) 38 | else: 39 | pid = os.fork() 40 | if (pid==0): 41 | cmd = "python run_synth.py > synth_out" 42 | os.system(cmd) 43 | 44 | 45 | 46 | -------------------------------------------------------------------------------- /cl_chronos/riscv_code/silo/Makefile: -------------------------------------------------------------------------------- 1 | # Amazon FPGA Hardware Development Kit 2 | # 3 | # Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. 4 | # 5 | # Licensed under the Amazon Software License (the "License"). You may not use 6 | # this file except in compliance with the License. A copy of the License is 7 | # located at 8 | # 9 | # http://aws.amazon.com/asl/ 10 | # 11 | # or in the "license" file accompanying this file. This file is distributed on 12 | # an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or 13 | # implied. See the License for the specific language governing permissions and 14 | # limitations under the License. 15 | 16 | #VPATH = src:include:$(HDK_DIR)/common/software/src:$(HDK_DIR)/common/software/include 17 | 18 | INCLUDES = -I$(SDK_DIR)/userspace/include 19 | 20 | #CC = g++ 21 | CC = riscv-none-embed-g++ 22 | CFLAGS = -march=rv32i -mabi=ilp32 -T linker_script -DRISCV -specs=nosys.specs 23 | 24 | 25 | SRC = main.c silo.h 26 | OBJ = $(SRC:.c=.o) 27 | BIN = riscv 28 | 29 | all: $(BIN) 30 | 31 | riscv: $(OBJ) 32 | $(CC) $(CFLAGS) -O3 -o $^ $(SRC) 33 | riscv-none-embed-objdump -D main.o > main.dump 34 | riscv-none-embed-objcopy --output-target=ihex main.o main.hex 35 | sim: $(OBJ) 36 | g++ -O3 -o silo_sim $(SRC) 37 | 38 | clean: 39 | rm -f *.o $(BIN) 40 | 41 | -------------------------------------------------------------------------------- /cl_chronos/riscv_code/sssp/Makefile: -------------------------------------------------------------------------------- 1 | # Amazon FPGA Hardware Development Kit 2 | # 3 | # Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. 4 | # 5 | # Licensed under the Amazon Software License (the "License"). You may not use 6 | # this file except in compliance with the License. A copy of the License is 7 | # located at 8 | # 9 | # http://aws.amazon.com/asl/ 10 | # 11 | # or in the "license" file accompanying this file. This file is distributed on 12 | # an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or 13 | # implied. See the License for the specific language governing permissions and 14 | # limitations under the License. 15 | 16 | #VPATH = src:include:$(HDK_DIR)/common/software/src:$(HDK_DIR)/common/software/include 17 | 18 | INCLUDES = -I$(SDK_DIR)/userspace/include 19 | 20 | #CC = riscv-none-embed-gcc 21 | #CFLAGS = -march=rv32i -mabi=ilp32 -T linker_script 22 | CC = riscv-none-embed-g++ 23 | CFLAGS = -march=rv32i -mabi=ilp32 -T linker_script -DRISCV -specs=nosys.specs 24 | 25 | 26 | SRC = main.c 27 | OBJ = $(SRC:.c=.o) 28 | BIN = main 29 | 30 | all: $(BIN) 31 | 32 | $(BIN): $(OBJ) 33 | $(CC) $(CFLAGS) -O3 -o $^ $(SRC) 34 | riscv-none-embed-objdump -D main.o > main.dump 35 | riscv-none-embed-objcopy --output-target=ihex main.o main.hex 36 | 37 | clean: 38 | rm -f *.o $(BIN) 39 | 40 | -------------------------------------------------------------------------------- /cl_chronos/software/runtime/Makefile: -------------------------------------------------------------------------------- 1 | # Amazon FPGA Hardware Development Kit 2 | # 3 | # Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. 4 | # 5 | # Licensed under the Amazon Software License (the "License"). You may not use 6 | # this file except in compliance with the License. A copy of the License is 7 | # located at 8 | # 9 | # http://aws.amazon.com/asl/ 10 | # 11 | # or in the "license" file accompanying this file. This file is distributed on 12 | # an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or 13 | # implied. See the License for the specific language governing permissions and 14 | # limitations under the License. 15 | 16 | #VPATH = src:include:$(HDK_DIR)/common/software/src:$(HDK_DIR)/common/software/include 17 | 18 | INCLUDES = -I$(SDK_DIR)/userspace/include 19 | 20 | CC = gcc 21 | CFLAGS = -DCONFIG_LOGLEVEL=4 -std=gnu99 -g -Wall $(INCLUDES) 22 | 23 | LDLIBS = -lfpga_mgmt -lrt -lpthread -lm 24 | 25 | SRC = test_chronos.c util_log.c header.h test_task_unit.c 26 | OBJ = $(SRC:.c=.o) 27 | BIN = test_chronos 28 | 29 | all: $(BIN) check_env 30 | 31 | $(BIN): $(OBJ) 32 | $(CC) $(CFLAGS) -o $@ $^ $(LDFLAGS) $(LDLIBS) 33 | 34 | clean: 35 | rm -f *.o $(BIN) 36 | 37 | check_env: 38 | ifndef SDK_DIR 39 | $(error SDK_DIR is undefined. Try "source sdk_setup.sh" to set the software environment) 40 | endif 41 | -------------------------------------------------------------------------------- /cl_chronos/riscv_code/color-nonspec/Makefile: -------------------------------------------------------------------------------- 1 | # Amazon FPGA Hardware Development Kit 2 | # 3 | # Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. 4 | # 5 | # Licensed under the Amazon Software License (the "License"). You may not use 6 | # this file except in compliance with the License. A copy of the License is 7 | # located at 8 | # 9 | # http://aws.amazon.com/asl/ 10 | # 11 | # or in the "license" file accompanying this file. This file is distributed on 12 | # an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or 13 | # implied. See the License for the specific language governing permissions and 14 | # limitations under the License. 15 | 16 | #VPATH = src:include:$(HDK_DIR)/common/software/src:$(HDK_DIR)/common/software/include 17 | 18 | INCLUDES = -I$(SDK_DIR)/userspace/include 19 | 20 | #CC = g++ 21 | CC = riscv-none-embed-g++ 22 | CFLAGS = -march=rv32i -mabi=ilp32 -T linker_script -DRISCV -specs=nosys.specs 23 | 24 | 25 | SRC = main.c 26 | OBJ = $(SRC:.c=.o) 27 | BIN = riscv 28 | 29 | all: $(BIN) 30 | 31 | riscv: $(OBJ) 32 | $(CC) $(CFLAGS) -O3 -o $^ $(SRC) 33 | riscv-none-embed-objdump -D main.o > main.dump 34 | riscv-none-embed-objcopy --output-target=ihex main.o main.hex 35 | pipe: pipe.c 36 | $(CC) $(CFLAGS) -O3 -o $^ $(SRC) 37 | riscv-none-embed-objdump -D main.o > main.dump 38 | riscv-none-embed-objcopy --output-target=ihex main.o main.hex 39 | sim: $(OBJ) 40 | g++ -O3 -o color_sim $(SRC) 41 | 42 | clean: 43 | rm -f *.o $(BIN) 44 | 45 | -------------------------------------------------------------------------------- /cl_chronos/design/cl_chronos_defines.vh: -------------------------------------------------------------------------------- 1 | /** $lic$ 2 | * Copyright (C) 2014-2019 by Massachusetts Institute of Technology 3 | * 4 | * This file is part of the Chronos FPGA Acceleration Framework. 5 | * 6 | * Chronos is free software; you can redistribute it and/or modify it under the 7 | * terms of the GNU General Public License as published by the Free Software 8 | * Foundation, version 2. 9 | * 10 | * If you use this framework in your research, we request that you reference 11 | * the Chronos paper ("Chronos: Efficient Speculative Parallelism for 12 | * Accelerators", Abeydeera and Sanchez, ASPLOS-25, March 2020), and that 13 | * you send us a citation of your work. 14 | * 15 | * Chronos is distributed in the hope that it will be useful, but WITHOUT ANY 16 | * WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS 17 | * FOR A PARTICULAR PURPOSE. See the GNU General Public License for more 18 | * details. 19 | * 20 | * You should have received a copy of the GNU General Public License along with 21 | * this program. If not, see . 22 | */ 23 | 24 | 25 | `ifndef CL_CHRONOS_DEFINES 26 | `define CL_CHRONOS_DEFINES 27 | 28 | //Put module name of the CL design here. This is used to instantiate in top.sv 29 | `define CL_NAME cl_chronos 30 | 31 | //Highly recommeneded. For lib FIFO block, uses less async reset (take advantage of 32 | // FPGA flop init capability). This will help with routing resources. 33 | `define FPGA_LESS_RST 34 | 35 | // Uncomment to disable Virtual JTAG 36 | //`define DISABLE_VJTAG_DEBUG 37 | 38 | `endif 39 | -------------------------------------------------------------------------------- /cl_chronos/design/prefetcher.sv: -------------------------------------------------------------------------------- 1 | 2 | module prefetcher 3 | ( 4 | input clk, 5 | input rstn, 6 | 7 | input task_in_valid, 8 | task_t task_in, 9 | 10 | output logic prefetch_valid, 11 | output axi_addr_t prefetch_addr, 12 | 13 | input reg_bus_wvalid, 14 | input [31:0] reg_bus_waddr, 15 | input [31:0] reg_bus_wdata 16 | ); 17 | 18 | `ifdef USE_PIPELINED_TEMPLATE 19 | 20 | reg_bus_t reg_bus(); 21 | assign reg_bus.wvalid = reg_bus_wvalid; 22 | assign reg_bus.waddr = reg_bus_waddr; 23 | assign reg_bus.wdata = reg_bus_wdata; 24 | assign reg_bus.arvalid = 1'b0; 25 | 26 | `RW_READER RW_READER ( 27 | .clk(clk), 28 | .rstn(rstn), 29 | .task_in(task_in), 30 | 31 | .araddr(prefetch_addr[31:0]), 32 | .reg_bus(reg_bus) 33 | ); 34 | assign prefetch_addr[63:32] = 0; 35 | assign prefetch_valid = task_in_valid; 36 | 37 | `else 38 | assign prefetch_valid = task_in_valid; 39 | logic [31:0] base_rw_addr; 40 | logic [3:0] log_rw_width; 41 | assign prefetch_addr = base_rw_addr + (task_in.object << (log_rw_width) ); 42 | 43 | always_ff @(posedge clk) begin 44 | if (!rstn) begin 45 | base_rw_addr <= 0; 46 | log_rw_width <= 2; 47 | end else begin 48 | if (reg_bus_wvalid) begin 49 | case (reg_bus_waddr) 50 | PREFETCHER_BASE_ADDR : base_rw_addr <= {reg_bus_wdata[29:0], 2'b00}; 51 | PREFETCHER_OBJECT_SIZE : log_rw_width <= reg_bus_wdata[3:0]; 52 | endcase 53 | end 54 | end 55 | end 56 | `endif 57 | 58 | endmodule 59 | -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | cscope.files 2 | cscope.out 3 | tags 4 | simv 5 | simv.daidir 6 | csrc 7 | ucli.key 8 | vc_hdrs.h 9 | INCA_libs 10 | irun.log 11 | irun.key 12 | 13 | fpga-local-cmd* 14 | static-fpga-local-cmd 15 | 16 | *_compile.log 17 | *_run.log 18 | *.vpd 19 | .simvision 20 | *.vcd 21 | *.vcdplus* 22 | waves.shm 23 | *.mod.c 24 | *.order 25 | *.symvers 26 | 27 | .* 28 | *~ 29 | .\#* 30 | \#* 31 | 32 | *.swp 33 | *.o 34 | .nfs* 35 | *.so 36 | *.a 37 | *.ko 38 | *.csr 39 | *.swo 40 | *.swn 41 | *.swm 42 | 43 | nohup.out 44 | *.nohup.out 45 | 46 | # Shell DCP files are stored in S3 and downloaded by hdk_setup.sh 47 | hdk/common/shell_*/build/checkpoints/from_aws/SH_CL_BB_routed.dcp* 48 | 49 | # Generated checkpoints 50 | checkpoints 51 | 52 | # Created when building DDR4 models 53 | build.lock 54 | hdk/common/verif/models/.vivado_version 55 | 56 | # These get created when you run vivado interactively or batch 57 | vivado_pid*.str 58 | vivado*.jou 59 | vivado*.log 60 | 61 | # Pycharm projects 62 | .idea/ 63 | 64 | # Python compiled code 65 | *.pyc 66 | 67 | # all files from vivado simulations except tb.wcfg 68 | **sim/ 69 | !tb.wcfg 70 | 71 | 72 | # graph inputs 73 | *.net 74 | *.gr 75 | 76 | # auto generated files 77 | **/cl_clocks_aws.xdc 78 | obj_dir 79 | debug_probes 80 | *.log 81 | test_chronos 82 | #graph_gen 83 | sdk/userspace/lib 84 | *.hex 85 | *.dump 86 | *.out 87 | a 88 | *.color 89 | *.sssp 90 | *.edges 91 | *.bin 92 | *.flow 93 | cl_chronos/design/config_app.vh 94 | cl_chronos/design/gen_core_spec.vh 95 | cl_chronos/design/gen_core_spec_tile.vh 96 | cl_chronos/design/app_config.vh 97 | aws-fpga/ 98 | 99 | -------------------------------------------------------------------------------- /cl_chronos/design/apps/riscv/config.vh: -------------------------------------------------------------------------------- 1 | /** $lic$ 2 | * Copyright (C) 2014-2019 by Massachusetts Institute of Technology 3 | * 4 | * This file is part of the Chronos FPGA Acceleration Framework. 5 | * 6 | * Chronos is free software; you can redistribute it and/or modify it under the 7 | * terms of the GNU General Public License as published by the Free Software 8 | * Foundation, version 2. 9 | * 10 | * If you use this framework in your research, we request that you reference 11 | * the Chronos paper ("Chronos: Efficient Speculative Parallelism for 12 | * Accelerators", Abeydeera and Sanchez, ASPLOS-25, March 2020), and that 13 | * you send us a citation of your work. 14 | * 15 | * Chronos is distributed in the hope that it will be useful, but WITHOUT ANY 16 | * WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS 17 | * FOR A PARTICULAR PURPOSE. See the GNU General Public License for more 18 | * details. 19 | * 20 | * You should have received a copy of the GNU General Public License along with 21 | * this program. If not, see . 22 | */ 23 | 24 | # ARG_WIDTH has to be a multiple of 32 25 | ARG_WIDTH 128 26 | 27 | APP_ID 256 28 | RISCV_APP sssp 29 | 30 | mt_core riscv_core 1 31 | mt_core riscv_core 1 32 | mt_core riscv_core 1 33 | mt_core riscv_core 1 34 | mt_core riscv_core 1 35 | mt_core riscv_core 1 36 | mt_core riscv_core 1 37 | mt_core riscv_core 1 38 | mt_core riscv_core 1 39 | mt_core riscv_core 1 40 | mt_core riscv_core 1 41 | mt_core riscv_core 1 42 | mt_core riscv_core 1 43 | mt_core riscv_core 1 44 | mt_core riscv_core 1 45 | mt_core riscv_core 1 46 | -------------------------------------------------------------------------------- /cl_chronos/design/apps/silo/config_pipe.vh: -------------------------------------------------------------------------------- 1 | /** $lic$ 2 | * Copyright (C) 2014-2019 by Massachusetts Institute of Technology 3 | * 4 | * This file is part of the Chronos FPGA Acceleration Framework. 5 | * 6 | * Chronos is free software; you can redistribute it and/or modify it under the 7 | * terms of the GNU General Public License as published by the Free Software 8 | * Foundation, version 2. 9 | * 10 | * If you use this framework in your research, we request that you reference 11 | * the Chronos paper ("Chronos: Efficient Speculative Parallelism for 12 | * Accelerators", Abeydeera and Sanchez, ASPLOS-25, March 2020), and that 13 | * you send us a citation of your work. 14 | * 15 | * Chronos is distributed in the hope that it will be useful, but WITHOUT ANY 16 | * WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS 17 | * FOR A PARTICULAR PURPOSE. See the GNU General Public License for more 18 | * details. 19 | * 20 | * You should have received a copy of the GNU General Public License along with 21 | * this program. If not, see . 22 | */ 23 | 24 | `define USE_PIPELINED_TEMPLATE 25 | 26 | parameter APP_NAME = "silo"; 27 | parameter APP_ID = 4; 28 | parameter RISCV = 0; 29 | 30 | parameter ARG_WIDTH = 96; 31 | 32 | parameter RW_WIDTH = 256; 33 | parameter DATA_WIDTH = 32; 34 | 35 | parameter RW_BASE_ADDR = 20; 36 | parameter OFFSET_BASE_ADDR = 12; 37 | parameter NEIGHBOR_BASE_ADDR = 16; 38 | 39 | 40 | parameter LOG_N_SUB_TYPES = 3; 41 | 42 | 43 | `define RO_WORKER silo_ro 44 | `define RW_READER silo_read 45 | `define RW_WORKER silo_write 46 | 47 | parameter N_CORES = 0; 48 | -------------------------------------------------------------------------------- /cl_chronos/design/apps/sssp/config_pipe.vh: -------------------------------------------------------------------------------- 1 | /** $lic$ 2 | * Copyright (C) 2014-2019 by Massachusetts Institute of Technology 3 | * 4 | * This file is part of the Chronos FPGA Acceleration Framework. 5 | * 6 | * Chronos is free software; you can redistribute it and/or modify it under the 7 | * terms of the GNU General Public License as published by the Free Software 8 | * Foundation, version 2. 9 | * 10 | * If you use this framework in your research, we request that you reference 11 | * the Chronos paper ("Chronos: Efficient Speculative Parallelism for 12 | * Accelerators", Abeydeera and Sanchez, ASPLOS-25, March 2020), and that 13 | * you send us a citation of your work. 14 | * 15 | * Chronos is distributed in the hope that it will be useful, but WITHOUT ANY 16 | * WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS 17 | * FOR A PARTICULAR PURPOSE. See the GNU General Public License for more 18 | * details. 19 | * 20 | * You should have received a copy of the GNU General Public License along with 21 | * this program. If not, see . 22 | */ 23 | 24 | `define USE_PIPELINED_TEMPLATE 25 | `define SINGLE_UNDO_LOG_RESTORE 26 | 27 | parameter APP_NAME = "sssp"; 28 | parameter APP_ID = 0; 29 | parameter RISCV = 0; 30 | 31 | parameter ARG_WIDTH = 1; 32 | 33 | parameter RW_WIDTH = 32; 34 | parameter DATA_WIDTH = 64; 35 | 36 | parameter RW_BASE_ADDR = 20; 37 | parameter OFFSET_BASE_ADDR = 12; 38 | parameter NEIGHBOR_BASE_ADDR = 16; 39 | 40 | 41 | parameter LOG_N_SUB_TYPES = 2; 42 | 43 | 44 | `define RO_WORKER sssp_ro 45 | `define RW_READER default_rw_reader 46 | `define RW_WORKER sssp_rw 47 | 48 | 49 | -------------------------------------------------------------------------------- /cl_chronos/design/apps/des/config_pipe.vh: -------------------------------------------------------------------------------- 1 | /** $lic$ 2 | * Copyright (C) 2014-2019 by Massachusetts Institute of Technology 3 | * 4 | * This file is part of the Chronos FPGA Acceleration Framework. 5 | * 6 | * Chronos is free software; you can redistribute it and/or modify it under the 7 | * terms of the GNU General Public License as published by the Free Software 8 | * Foundation, version 2. 9 | * 10 | * If you use this framework in your research, we request that you reference 11 | * the Chronos paper ("Chronos: Efficient Speculative Parallelism for 12 | * Accelerators", Abeydeera and Sanchez, ASPLOS-25, March 2020), and that 13 | * you send us a citation of your work. 14 | * 15 | * Chronos is distributed in the hope that it will be useful, but WITHOUT ANY 16 | * WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS 17 | * FOR A PARTICULAR PURPOSE. See the GNU General Public License for more 18 | * details. 19 | * 20 | * You should have received a copy of the GNU General Public License along with 21 | * this program. If not, see . 22 | */ 23 | 24 | `define USE_PIPELINED_TEMPLATE 25 | `define SINGLE_UNDO_LOG_RESTORE 26 | 27 | parameter APP_NAME = "des"; 28 | parameter APP_ID = 1; 29 | parameter RISCV = 0; 30 | 31 | parameter ARG_WIDTH = 32; 32 | 33 | parameter RW_WIDTH = 32; 34 | parameter DATA_WIDTH = 64; 35 | 36 | 37 | parameter LOG_N_SUB_TYPES = 2; 38 | 39 | parameter RW_BASE_ADDR = 20; 40 | parameter OFFSET_BASE_ADDR = 12; 41 | parameter NEIGHBOR_BASE_ADDR = 16; 42 | 43 | `define RO_WORKER des_ro 44 | `define RW_READER default_rw_reader 45 | `define RW_WORKER des_rw 46 | 47 | parameter N_CORES = 0; 48 | -------------------------------------------------------------------------------- /cl_chronos/verif/scripts/Makefile: -------------------------------------------------------------------------------- 1 | # Amazon FPGA Hardware Development Kit 2 | # 3 | # Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. 4 | # 5 | # Licensed under the Amazon Software License (the "License"). You may not use 6 | # this file except in compliance with the License. A copy of the License is 7 | # located at 8 | # 9 | # http://aws.amazon.com/asl/ 10 | # 11 | # or in the "license" file accompanying this file. This file is distributed on 12 | # an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or 13 | # implied. See the License for the specific language governing permissions and 14 | # limitations under the License. 15 | 16 | 17 | export TEST ?= test_null 18 | export C_TEST ?= test_null 19 | 20 | export CL_ROOT = $(PWD)/../.. 21 | 22 | export C_INC_DIR = $(CL_ROOT)/software/verif_rtl/include 23 | export C_SRC_DIR = $(CL_ROOT)/software/verif_rtl/src 24 | 25 | export TEST_NAME = $(CL_ROOT)/verif/tests/$(TEST).sv 26 | export C_TEST_NAME = $(C_SRC_DIR)/$(C_TEST).c 27 | 28 | export SIM_ROOT = $(CL_ROOT)/verif/sim 29 | 30 | ifeq ($(C_TEST),test_null) 31 | export SIM_DIR = $(SIM_ROOT)/$(TEST) 32 | else 33 | export SIM_DIR = $(SIM_ROOT)/$(C_TEST) 34 | endif 35 | 36 | 37 | export SCRIPTS_DIR = $(PWD) 38 | export XILINX_IP = $(HDK_SHELL_DESIGN_DIR)/ip 39 | export SH_LIB_DIR = $(HDK_SHELL_DESIGN_DIR)/lib 40 | export SH_INF_DIR = $(HDK_SHELL_DESIGN_DIR)/interfaces 41 | export SH_SH_DIR = $(HDK_SHELL_DESIGN_DIR)/sh_ddr/sim 42 | 43 | SV_TEST_LIST = test_task_unit 44 | C_TEST_LIST = test_task_unit.c 45 | 46 | all: make_sim_dir compile run 47 | 48 | include $(HDK_COMMON_DIR)/verif/tb/scripts/Makefile.common.inc 49 | 50 | -------------------------------------------------------------------------------- /cl_chronos/design/apps/astar/config_pipe.vh: -------------------------------------------------------------------------------- 1 | /** $lic$ 2 | * Copyright (C) 2014-2019 by Massachusetts Institute of Technology 3 | * 4 | * This file is part of the Chronos FPGA Acceleration Framework. 5 | * 6 | * Chronos is free software; you can redistribute it and/or modify it under the 7 | * terms of the GNU General Public License as published by the Free Software 8 | * Foundation, version 2. 9 | * 10 | * If you use this framework in your research, we request that you reference 11 | * the Chronos paper ("Chronos: Efficient Speculative Parallelism for 12 | * Accelerators", Abeydeera and Sanchez, ASPLOS-25, March 2020), and that 13 | * you send us a citation of your work. 14 | * 15 | * Chronos is distributed in the hope that it will be useful, but WITHOUT ANY 16 | * WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS 17 | * FOR A PARTICULAR PURPOSE. See the GNU General Public License for more 18 | * details. 19 | * 20 | * You should have received a copy of the GNU General Public License along with 21 | * this program. If not, see . 22 | */ 23 | 24 | `define USE_PIPELINED_TEMPLATE 25 | `define SINGLE_UNDO_LOG_RESTORE 26 | 27 | parameter APP_NAME = "astar"; 28 | parameter APP_ID = 2; 29 | parameter RISCV = 0; 30 | 31 | parameter ARG_WIDTH = 64; 32 | 33 | parameter RW_WIDTH = 32; 34 | parameter DATA_WIDTH = 64; 35 | 36 | 37 | parameter LOG_N_SUB_TYPES = 2; 38 | 39 | parameter RW_BASE_ADDR = 20; 40 | parameter OFFSET_BASE_ADDR = 12; 41 | parameter NEIGHBOR_BASE_ADDR = 16; 42 | 43 | `define RO_WORKER astar_ro 44 | `define RW_READER default_rw_reader 45 | `define RW_WORKER astar_rw 46 | 47 | parameter N_CORES = 0; 48 | 49 | 50 | -------------------------------------------------------------------------------- /cl_chronos/design/apps/color/config_pipe.vh: -------------------------------------------------------------------------------- 1 | /** $lic$ 2 | * Copyright (C) 2014-2019 by Massachusetts Institute of Technology 3 | * 4 | * This file is part of the Chronos FPGA Acceleration Framework. 5 | * 6 | * Chronos is free software; you can redistribute it and/or modify it under the 7 | * terms of the GNU General Public License as published by the Free Software 8 | * Foundation, version 2. 9 | * 10 | * If you use this framework in your research, we request that you reference 11 | * the Chronos paper ("Chronos: Efficient Speculative Parallelism for 12 | * Accelerators", Abeydeera and Sanchez, ASPLOS-25, March 2020), and that 13 | * you send us a citation of your work. 14 | * 15 | * Chronos is distributed in the hope that it will be useful, but WITHOUT ANY 16 | * WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS 17 | * FOR A PARTICULAR PURPOSE. See the GNU General Public License for more 18 | * details. 19 | * 20 | * You should have received a copy of the GNU General Public License along with 21 | * this program. If not, see . 22 | */ 23 | 24 | `define USE_PIPELINED_TEMPLATE 25 | `define SINGLE_UNDO_LOG_RESTORE 26 | 27 | parameter APP_NAME = "color"; 28 | parameter APP_ID = 4; 29 | parameter RISCV = 0; 30 | 31 | parameter ARG_WIDTH = 80; 32 | 33 | parameter RW_WIDTH = 128; 34 | parameter DATA_WIDTH = 32; 35 | 36 | parameter RW_BASE_ADDR = 20; 37 | parameter OFFSET_BASE_ADDR = 12; 38 | parameter NEIGHBOR_BASE_ADDR = 16; 39 | 40 | 41 | parameter LOG_N_SUB_TYPES = 1; 42 | 43 | 44 | `define RO_WORKER color_worker 45 | `define RW_READER default_rw_reader 46 | `define RW_WORKER color_rw 47 | 48 | parameter N_CORES = 0; 49 | -------------------------------------------------------------------------------- /cl_chronos/design/apps/maxflow/config_pipe.vh: -------------------------------------------------------------------------------- 1 | /** $lic$ 2 | * Copyright (C) 2014-2019 by Massachusetts Institute of Technology 3 | * 4 | * This file is part of the Chronos FPGA Acceleration Framework. 5 | * 6 | * Chronos is free software; you can redistribute it and/or modify it under the 7 | * terms of the GNU General Public License as published by the Free Software 8 | * Foundation, version 2. 9 | * 10 | * If you use this framework in your research, we request that you reference 11 | * the Chronos paper ("Chronos: Efficient Speculative Parallelism for 12 | * Accelerators", Abeydeera and Sanchez, ASPLOS-25, March 2020), and that 13 | * you send us a citation of your work. 14 | * 15 | * Chronos is distributed in the hope that it will be useful, but WITHOUT ANY 16 | * WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS 17 | * FOR A PARTICULAR PURPOSE. See the GNU General Public License for more 18 | * details. 19 | * 20 | * You should have received a copy of the GNU General Public License along with 21 | * this program. If not, see . 22 | */ 23 | 24 | `define USE_PIPELINED_TEMPLATE 25 | `define SINGLE_UNDO_LOG_RESTORE 26 | 27 | parameter APP_NAME = "maxflow"; 28 | parameter APP_ID = 3; 29 | parameter RISCV = 0; 30 | 31 | parameter ARG_WIDTH = 96; 32 | 33 | parameter RW_WIDTH = 512; 34 | parameter DATA_WIDTH = 64; 35 | 36 | parameter RW_BASE_ADDR = 20; 37 | parameter OFFSET_BASE_ADDR = 12; 38 | parameter NEIGHBOR_BASE_ADDR = 16; 39 | 40 | 41 | parameter LOG_N_SUB_TYPES = 2; 42 | 43 | 44 | `define RO_WORKER maxflow_ro 45 | `define RW_READER default_rw_reader 46 | `define RW_WORKER maxflow_rw 47 | 48 | parameter N_CORES = 0; 49 | -------------------------------------------------------------------------------- /cl_chronos/design/apps/astar/astar_dist_mul_22g8j.v: -------------------------------------------------------------------------------- 1 | // ============================================================== 2 | // File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC 3 | // Version: 2017.1 4 | // Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved. 5 | // 6 | // ============================================================== 7 | 8 | 9 | `timescale 1 ns / 1 ps 10 | 11 | module astar_dist_mul_22g8j_Mul3S_1(clk, ce, a, b, p); 12 | input clk; 13 | input ce; 14 | input[22 - 1 : 0] a; // synthesis attribute keep a "true" 15 | input[22 - 1 : 0] b; // synthesis attribute keep b "true" 16 | output[44 - 1 : 0] p; 17 | 18 | reg [22 - 1 : 0] a_reg0; 19 | reg [22 - 1 : 0] b_reg0; 20 | wire [44 - 1 : 0] tmp_product; 21 | reg [44 - 1 : 0] buff0; 22 | 23 | assign p = buff0; 24 | assign tmp_product = a_reg0 * b_reg0; 25 | always @ (posedge clk) begin 26 | if (ce) begin 27 | a_reg0 <= a; 28 | b_reg0 <= b; 29 | buff0 <= tmp_product; 30 | end 31 | end 32 | endmodule 33 | 34 | `timescale 1 ns / 1 ps 35 | module astar_dist_mul_22g8j( 36 | clk, 37 | reset, 38 | ce, 39 | din0, 40 | din1, 41 | dout); 42 | 43 | parameter ID = 32'd1; 44 | parameter NUM_STAGE = 32'd1; 45 | parameter din0_WIDTH = 32'd1; 46 | parameter din1_WIDTH = 32'd1; 47 | parameter dout_WIDTH = 32'd1; 48 | input clk; 49 | input reset; 50 | input ce; 51 | input[din0_WIDTH - 1:0] din0; 52 | input[din1_WIDTH - 1:0] din1; 53 | output[dout_WIDTH - 1:0] dout; 54 | 55 | 56 | 57 | astar_dist_mul_22g8j_Mul3S_1 astar_dist_mul_22g8j_Mul3S_1_U( 58 | .clk( clk ), 59 | .ce( ce ), 60 | .a( din0 ), 61 | .b( din1 ), 62 | .p( dout )); 63 | 64 | endmodule 65 | 66 | -------------------------------------------------------------------------------- /cl_chronos/design/apps/astar/astar_dist_mul_31pcA.v: -------------------------------------------------------------------------------- 1 | // ============================================================== 2 | // File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC 3 | // Version: 2017.1 4 | // Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved. 5 | // 6 | // ============================================================== 7 | 8 | 9 | `timescale 1 ns / 1 ps 10 | 11 | module astar_dist_mul_31pcA_Mul3S_6(clk, ce, a, b, p); 12 | input clk; 13 | input ce; 14 | input[31 - 1 : 0] a; // synthesis attribute keep a "true" 15 | input[24 - 1 : 0] b; // synthesis attribute keep b "true" 16 | output[54 - 1 : 0] p; 17 | 18 | reg [31 - 1 : 0] a_reg0; 19 | reg [24 - 1 : 0] b_reg0; 20 | wire [54 - 1 : 0] tmp_product; 21 | reg [54 - 1 : 0] buff0; 22 | 23 | assign p = buff0; 24 | assign tmp_product = a_reg0 * b_reg0; 25 | always @ (posedge clk) begin 26 | if (ce) begin 27 | a_reg0 <= a; 28 | b_reg0 <= b; 29 | buff0 <= tmp_product; 30 | end 31 | end 32 | endmodule 33 | 34 | `timescale 1 ns / 1 ps 35 | module astar_dist_mul_31pcA( 36 | clk, 37 | reset, 38 | ce, 39 | din0, 40 | din1, 41 | dout); 42 | 43 | parameter ID = 32'd1; 44 | parameter NUM_STAGE = 32'd1; 45 | parameter din0_WIDTH = 32'd1; 46 | parameter din1_WIDTH = 32'd1; 47 | parameter dout_WIDTH = 32'd1; 48 | input clk; 49 | input reset; 50 | input ce; 51 | input[din0_WIDTH - 1:0] din0; 52 | input[din1_WIDTH - 1:0] din1; 53 | output[dout_WIDTH - 1:0] dout; 54 | 55 | 56 | 57 | astar_dist_mul_31pcA_Mul3S_6 astar_dist_mul_31pcA_Mul3S_6_U( 58 | .clk( clk ), 59 | .ce( ce ), 60 | .a( din0 ), 61 | .b( din1 ), 62 | .p( dout )); 63 | 64 | endmodule 65 | 66 | -------------------------------------------------------------------------------- /cl_chronos/design/apps/astar/astar_dist_mul_36eOg.v: -------------------------------------------------------------------------------- 1 | // ============================================================== 2 | // File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC 3 | // Version: 2017.1 4 | // Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved. 5 | // 6 | // ============================================================== 7 | 8 | 9 | `timescale 1 ns / 1 ps 10 | 11 | module astar_dist_mul_36eOg_Mul3S_0(clk, ce, a, b, p); 12 | input clk; 13 | input ce; 14 | input[36 - 1 : 0] a; // synthesis attribute keep a "true" 15 | input[32 - 1 : 0] b; // synthesis attribute keep b "true" 16 | output[67 - 1 : 0] p; 17 | 18 | reg [36 - 1 : 0] a_reg0; 19 | reg [32 - 1 : 0] b_reg0; 20 | wire [67 - 1 : 0] tmp_product; 21 | reg [67 - 1 : 0] buff0; 22 | 23 | assign p = buff0; 24 | assign tmp_product = a_reg0 * b_reg0; 25 | always @ (posedge clk) begin 26 | if (ce) begin 27 | a_reg0 <= a; 28 | b_reg0 <= b; 29 | buff0 <= tmp_product; 30 | end 31 | end 32 | endmodule 33 | 34 | `timescale 1 ns / 1 ps 35 | module astar_dist_mul_36eOg( 36 | clk, 37 | reset, 38 | ce, 39 | din0, 40 | din1, 41 | dout); 42 | 43 | parameter ID = 32'd1; 44 | parameter NUM_STAGE = 32'd1; 45 | parameter din0_WIDTH = 32'd1; 46 | parameter din1_WIDTH = 32'd1; 47 | parameter dout_WIDTH = 32'd1; 48 | input clk; 49 | input reset; 50 | input ce; 51 | input[din0_WIDTH - 1:0] din0; 52 | input[din1_WIDTH - 1:0] din1; 53 | output[dout_WIDTH - 1:0] dout; 54 | 55 | 56 | 57 | astar_dist_mul_36eOg_Mul3S_0 astar_dist_mul_36eOg_Mul3S_0_U( 58 | .clk( clk ), 59 | .ce( ce ), 60 | .a( din0 ), 61 | .b( din1 ), 62 | .p( dout )); 63 | 64 | endmodule 65 | 66 | -------------------------------------------------------------------------------- /cl_chronos/software/runtime/serialize_enq.py: -------------------------------------------------------------------------------- 1 | import sys 2 | # Reads tq log, filters enqs that was not child-aborted 3 | # and sorts in ts order 4 | f = open(sys.argv[1]) 5 | i = 0 6 | slot_lines = [None]*4096 7 | slot_ts = [None]*4096 8 | slot_seq= [None]*4096 9 | enqs = [] 10 | #fw = open("a", "w") 11 | n_tied_enq = 0 12 | n_cut_tie = 0 13 | n_commit = 0 14 | n_abort = 0 15 | last_cut_tie_cycle = 0 16 | last_cut_tie_slot = 0 17 | seq =0 18 | 19 | log_count = 0 20 | 21 | for line in f: 22 | i=i+1 23 | slot = 0 24 | ts = 0 25 | if (line.find('log') >= 0): 26 | continue 27 | if (line.find('mismatch') >= 0): 28 | print(line) 29 | continue 30 | if (line.find('going') >=0): 31 | # print(line) 32 | continue 33 | #seq = int(line[1:7]) 34 | seq = i 35 | slot_loc = line.find('slot:') 36 | ts_loc = line.find('ts:') 37 | object_loc = line.find('object') 38 | if (slot_loc >0): 39 | slot = int(line[slot_loc+5:slot_loc+9]) 40 | 41 | if (line.find('task_enqueue')>0): 42 | slot_lines[slot] = line 43 | ts = int(line[ts_loc+3:object_loc], 16) 44 | slot_ts[slot] = ts 45 | slot_seq[slot] = seq 46 | 47 | if (line.find('commit')>0): 48 | if (slot_ts[slot] is not None): 49 | enqs.append([ slot_ts[slot], slot_seq[slot], slot_lines[slot]]) 50 | if (line.find('overflow')>0): 51 | enqs.append([ slot_ts[slot], slot_seq[slot], slot_lines[slot]]) 52 | 53 | enqs.sort(key=lambda tup: tup[0]*1000000000 + tup[1]) 54 | for (ts, seq, line) in enqs: 55 | #if (line[99+1] == ' '): 56 | # line = line[0:99] + " " + line[100:] 57 | print("%s" % line[:-1]) 58 | 59 | -------------------------------------------------------------------------------- /cl_chronos/design/apps/astar/config.vh: -------------------------------------------------------------------------------- 1 | /** $lic$ 2 | * Copyright (C) 2014-2019 by Massachusetts Institute of Technology 3 | * 4 | * This file is part of the Chronos FPGA Acceleration Framework. 5 | * 6 | * Chronos is free software; you can redistribute it and/or modify it under the 7 | * terms of the GNU General Public License as published by the Free Software 8 | * Foundation, version 2. 9 | * 10 | * If you use this framework in your research, we request that you reference 11 | * the Chronos paper ("Chronos: Efficient Speculative Parallelism for 12 | * Accelerators", Abeydeera and Sanchez, ASPLOS-25, March 2020), and that 13 | * you send us a citation of your work. 14 | * 15 | * Chronos is distributed in the hope that it will be useful, but WITHOUT ANY 16 | * WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS 17 | * FOR A PARTICULAR PURPOSE. See the GNU General Public License for more 18 | * details. 19 | * 20 | * You should have received a copy of the GNU General Public License along with 21 | * this program. If not, see . 22 | */ 23 | 24 | WARNING ASTAR NON-PIPELINED VERSION IS NOT SUPPORTED 25 | WARNING HENCE, DEFAULTING TO PIPELINED VERSION 26 | 27 | `define USE_PIPELINED_TEMPLATE 28 | 29 | parameter APP_NAME = "astar"; 30 | parameter APP_ID = 2; 31 | parameter RISCV = 0; 32 | 33 | parameter ARG_WIDTH = 64; 34 | 35 | parameter RW_WIDTH = 32; 36 | parameter DATA_WIDTH = 64; 37 | 38 | 39 | parameter LOG_N_SUB_TYPES = 2; 40 | 41 | parameter RW_BASE_ADDR = 20; 42 | parameter OFFSET_BASE_ADDR = 12; 43 | parameter NEIGHBOR_BASE_ADDR = 16; 44 | 45 | `define RO_WORKER astar_ro 46 | `define RW_WORKER astar_rw 47 | 48 | parameter N_CORES = 0; 49 | 50 | 51 | -------------------------------------------------------------------------------- /cl_chronos/design/apps/astar/astar_dist_mul_31lbW.v: -------------------------------------------------------------------------------- 1 | // ============================================================== 2 | // File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC 3 | // Version: 2017.1 4 | // Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved. 5 | // 6 | // ============================================================== 7 | 8 | 9 | `timescale 1 ns / 1 ps 10 | 11 | module astar_dist_mul_31lbW_Mul3S_4(clk, ce, a, b, p); 12 | input clk; 13 | input ce; 14 | input[31 - 1 : 0] a; // synthesis attribute keep a "true" 15 | input[31 - 1 : 0] b; // synthesis attribute keep b "true" 16 | output[62 - 1 : 0] p; 17 | 18 | reg signed [31 - 1 : 0] a_reg0; 19 | reg signed [31 - 1 : 0] b_reg0; 20 | wire signed [62 - 1 : 0] tmp_product; 21 | reg signed [62 - 1 : 0] buff0; 22 | 23 | assign p = buff0; 24 | assign tmp_product = a_reg0 * b_reg0; 25 | always @ (posedge clk) begin 26 | if (ce) begin 27 | a_reg0 <= a; 28 | b_reg0 <= b; 29 | buff0 <= tmp_product; 30 | end 31 | end 32 | endmodule 33 | 34 | `timescale 1 ns / 1 ps 35 | module astar_dist_mul_31lbW( 36 | clk, 37 | reset, 38 | ce, 39 | din0, 40 | din1, 41 | dout); 42 | 43 | parameter ID = 32'd1; 44 | parameter NUM_STAGE = 32'd1; 45 | parameter din0_WIDTH = 32'd1; 46 | parameter din1_WIDTH = 32'd1; 47 | parameter dout_WIDTH = 32'd1; 48 | input clk; 49 | input reset; 50 | input ce; 51 | input[din0_WIDTH - 1:0] din0; 52 | input[din1_WIDTH - 1:0] din1; 53 | output[dout_WIDTH - 1:0] dout; 54 | 55 | 56 | 57 | astar_dist_mul_31lbW_Mul3S_4 astar_dist_mul_31lbW_Mul3S_4_U( 58 | .clk( clk ), 59 | .ce( ce ), 60 | .a( din0 ), 61 | .b( din1 ), 62 | .p( dout )); 63 | 64 | endmodule 65 | 66 | -------------------------------------------------------------------------------- /cl_chronos/design/apps/astar/astar_dist_mul_31ocq.v: -------------------------------------------------------------------------------- 1 | // ============================================================== 2 | // File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC 3 | // Version: 2017.1 4 | // Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved. 5 | // 6 | // ============================================================== 7 | 8 | 9 | `timescale 1 ns / 1 ps 10 | 11 | module astar_dist_mul_31ocq_Mul3S_5(clk, ce, a, b, p); 12 | input clk; 13 | input ce; 14 | input[31 - 1 : 0] a; // synthesis attribute keep a "true" 15 | input[31 - 1 : 0] b; // synthesis attribute keep b "true" 16 | output[50 - 1 : 0] p; 17 | 18 | reg signed [31 - 1 : 0] a_reg0; 19 | reg signed [31 - 1 : 0] b_reg0; 20 | wire signed [50 - 1 : 0] tmp_product; 21 | reg signed [50 - 1 : 0] buff0; 22 | 23 | assign p = buff0; 24 | assign tmp_product = a_reg0 * b_reg0; 25 | always @ (posedge clk) begin 26 | if (ce) begin 27 | a_reg0 <= a; 28 | b_reg0 <= b; 29 | buff0 <= tmp_product; 30 | end 31 | end 32 | endmodule 33 | 34 | `timescale 1 ns / 1 ps 35 | module astar_dist_mul_31ocq( 36 | clk, 37 | reset, 38 | ce, 39 | din0, 40 | din1, 41 | dout); 42 | 43 | parameter ID = 32'd1; 44 | parameter NUM_STAGE = 32'd1; 45 | parameter din0_WIDTH = 32'd1; 46 | parameter din1_WIDTH = 32'd1; 47 | parameter dout_WIDTH = 32'd1; 48 | input clk; 49 | input reset; 50 | input ce; 51 | input[din0_WIDTH - 1:0] din0; 52 | input[din1_WIDTH - 1:0] din1; 53 | output[dout_WIDTH - 1:0] dout; 54 | 55 | 56 | 57 | astar_dist_mul_31ocq_Mul3S_5 astar_dist_mul_31ocq_Mul3S_5_U( 58 | .clk( clk ), 59 | .ce( ce ), 60 | .a( din0 ), 61 | .b( din1 ), 62 | .p( dout )); 63 | 64 | endmodule 65 | 66 | -------------------------------------------------------------------------------- /cl_chronos/design/apps/astar/astar_dist_mul_23hbi.v: -------------------------------------------------------------------------------- 1 | // ============================================================== 2 | // File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC 3 | // Version: 2017.1 4 | // Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved. 5 | // 6 | // ============================================================== 7 | 8 | 9 | `timescale 1 ns / 1 ps 10 | 11 | module astar_dist_mul_23hbi_Mul3S_2(clk, ce, a, b, p); 12 | input clk; 13 | input ce; 14 | input[23 - 1 : 0] a; // synthesis attribute keep a "true" 15 | input[29 - 1 : 0] b; // synthesis attribute keep b "true" 16 | output[52 - 1 : 0] p; 17 | 18 | reg signed [23 - 1 : 0] a_reg0; 19 | reg [29 - 1 : 0] b_reg0; 20 | wire signed [52 - 1 : 0] tmp_product; 21 | reg signed [52 - 1 : 0] buff0; 22 | 23 | assign p = buff0; 24 | assign tmp_product = a_reg0 * $signed({1'b0, b_reg0}); 25 | always @ (posedge clk) begin 26 | if (ce) begin 27 | a_reg0 <= a; 28 | b_reg0 <= b; 29 | buff0 <= tmp_product; 30 | end 31 | end 32 | endmodule 33 | 34 | `timescale 1 ns / 1 ps 35 | module astar_dist_mul_23hbi( 36 | clk, 37 | reset, 38 | ce, 39 | din0, 40 | din1, 41 | dout); 42 | 43 | parameter ID = 32'd1; 44 | parameter NUM_STAGE = 32'd1; 45 | parameter din0_WIDTH = 32'd1; 46 | parameter din1_WIDTH = 32'd1; 47 | parameter dout_WIDTH = 32'd1; 48 | input clk; 49 | input reset; 50 | input ce; 51 | input[din0_WIDTH - 1:0] din0; 52 | input[din1_WIDTH - 1:0] din1; 53 | output[dout_WIDTH - 1:0] dout; 54 | 55 | 56 | 57 | astar_dist_mul_23hbi_Mul3S_2 astar_dist_mul_23hbi_Mul3S_2_U( 58 | .clk( clk ), 59 | .ce( ce ), 60 | .a( din0 ), 61 | .b( din1 ), 62 | .p( dout )); 63 | 64 | endmodule 65 | 66 | -------------------------------------------------------------------------------- /cl_chronos/design/apps/astar/astar_dist_mul_36ibs.v: -------------------------------------------------------------------------------- 1 | // ============================================================== 2 | // File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC 3 | // Version: 2017.1 4 | // Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved. 5 | // 6 | // ============================================================== 7 | 8 | 9 | `timescale 1 ns / 1 ps 10 | 11 | module astar_dist_mul_36ibs_Mul3S_3(clk, ce, a, b, p); 12 | input clk; 13 | input ce; 14 | input[36 - 1 : 0] a; // synthesis attribute keep a "true" 15 | input[37 - 1 : 0] b; // synthesis attribute keep b "true" 16 | output[73 - 1 : 0] p; 17 | 18 | reg [36 - 1 : 0] a_reg0; 19 | reg signed [37 - 1 : 0] b_reg0; 20 | wire signed [73 - 1 : 0] tmp_product; 21 | reg signed [73 - 1 : 0] buff0; 22 | 23 | assign p = buff0; 24 | assign tmp_product = $signed({1'b0, a_reg0}) * b_reg0; 25 | always @ (posedge clk) begin 26 | if (ce) begin 27 | a_reg0 <= a; 28 | b_reg0 <= b; 29 | buff0 <= tmp_product; 30 | end 31 | end 32 | endmodule 33 | 34 | `timescale 1 ns / 1 ps 35 | module astar_dist_mul_36ibs( 36 | clk, 37 | reset, 38 | ce, 39 | din0, 40 | din1, 41 | dout); 42 | 43 | parameter ID = 32'd1; 44 | parameter NUM_STAGE = 32'd1; 45 | parameter din0_WIDTH = 32'd1; 46 | parameter din1_WIDTH = 32'd1; 47 | parameter dout_WIDTH = 32'd1; 48 | input clk; 49 | input reset; 50 | input ce; 51 | input[din0_WIDTH - 1:0] din0; 52 | input[din1_WIDTH - 1:0] din1; 53 | output[dout_WIDTH - 1:0] dout; 54 | 55 | 56 | 57 | astar_dist_mul_36ibs_Mul3S_3 astar_dist_mul_36ibs_Mul3S_3_U( 58 | .clk( clk ), 59 | .ce( ce ), 60 | .a( din0 ), 61 | .b( din1 ), 62 | .p( dout )); 63 | 64 | endmodule 65 | 66 | -------------------------------------------------------------------------------- /cl_chronos/design/cl_id_defines.vh: -------------------------------------------------------------------------------- 1 | /** $lic$ 2 | * Copyright (C) 2014-2019 by Massachusetts Institute of Technology 3 | * 4 | * This file is part of the Chronos FPGA Acceleration Framework. 5 | * 6 | * Chronos is free software; you can redistribute it and/or modify it under the 7 | * terms of the GNU General Public License as published by the Free Software 8 | * Foundation, version 2. 9 | * 10 | * If you use this framework in your research, we request that you reference 11 | * the Chronos paper ("Chronos: Efficient Speculative Parallelism for 12 | * Accelerators", Abeydeera and Sanchez, ASPLOS-25, March 2020), and that 13 | * you send us a citation of your work. 14 | * 15 | * Chronos is distributed in the hope that it will be useful, but WITHOUT ANY 16 | * WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS 17 | * FOR A PARTICULAR PURPOSE. See the GNU General Public License for more 18 | * details. 19 | * 20 | * You should have received a copy of the GNU General Public License along with 21 | * this program. If not, see . 22 | */ 23 | 24 | 25 | // CL_SH_ID0 26 | // - PCIe Vendor/Device ID Values 27 | // 31:16: PCIe Device ID 28 | // 15: 0: PCIe Vendor ID 29 | // - A Vendor ID value of 0x8086 is not valid. 30 | // - If using a Vendor ID value of 0x1D0F (Amazon) then valid 31 | // values for Device ID's are in the range of 0xF000 - 0xF0FF. 32 | // - A Vendor/Device ID of 0 (zero) is not valid. 33 | `define CL_SH_ID0 32'hF000_1D0F 34 | 35 | // CL_SH_ID1 36 | // - PCIe Subsystem/Subsystem Vendor ID Values 37 | // 31:16: PCIe Subsystem ID 38 | // 15: 0: PCIe Subsystem Vendor ID 39 | // - A PCIe Subsystem/Subsystem Vendor ID of 0 (zero) is not valid 40 | `define CL_SH_ID1 32'h1D51_FEDD 41 | 42 | 43 | -------------------------------------------------------------------------------- /cl_chronos/validation/scripts/experiments.txt: -------------------------------------------------------------------------------- 1 | zenodo https://zenodo.org/record/3563178/files/chronos-inputs.zip 2 | input sssp inputs/sssp/USA-road-d.USA.gr.sssp 3 | input astar inputs/astar/germany_1227737_11049637.csr 4 | input maxflow inputs/maxflow/genrmf_wide_37_6_1_10000_0.in.flow 5 | input des inputs/des/csaArray32.net.csr 6 | input color inputs/color/com-youtube.edges.color 7 | 8 | test riscv_sssp riscv_nr_4t 4 12 9 | test riscv_color riscv_nr_4t 4 12 10 | test riscv_maxflow riscv_r_4t 4 12 11 | test riscv_des riscv_r_4t 4 12 12 | test throttle_sssp riscv_rate_ctrl_nr_4t 4 12 13 | test throttle_color riscv_rate_ctrl_nr_4t 4 12 14 | 15 | test color color_nr_6t 1 1 16 | test color color_nr_6t 1 32 17 | test color color_nr_6t 2 32 18 | test color color_nr_6t 3 32 19 | test color color_nr_6t 4 32 20 | test color color_nr_6t 5 32 21 | test color color_nr_6t 6 32 22 | 23 | test sssp sssp_nr_1t 1 1 24 | test sssp sssp_nr_6t 1 16 25 | test sssp sssp_nr_6t 2 16 26 | test sssp sssp_nr_6t 4 16 27 | test sssp sssp_nr_14t 8 16 28 | test sssp sssp_nr_14t 12 16 29 | test sssp sssp_nr_16t 14 16 30 | test sssp sssp_nr_16t 16 16 31 | 32 | test sssp sssp_r_8t 8 16 33 | 34 | test astar astar_nr_1t 1 1 35 | test astar astar_nr_4t 1 16 36 | test astar astar_nr_4t 2 16 37 | test astar astar_nr_4t 4 16 38 | test astar astar_nr_6t 6 16 39 | test astar astar_nr_10t 8 16 40 | test astar astar_nr_10t 10 16 41 | 42 | test astar astar_r_6t 6 16 43 | 44 | test des des_r_8t 1 1 45 | test des des_r_8t 1 16 46 | test des des_r_8t 2 16 47 | test des des_r_8t 4 16 48 | test des des_r_8t 6 16 49 | test des des_r_8t 8 16 50 | 51 | test maxflow maxflow_r_2t 1 1 52 | test maxflow maxflow_r_2t 1 16 53 | test maxflow maxflow_r_2t 2 16 54 | test maxflow maxflow_r_8t 4 16 55 | test maxflow maxflow_r_8t 6 16 56 | test maxflow maxflow_r_8t 8 16 57 | 58 | -------------------------------------------------------------------------------- /cl_chronos/design/apps/astar/astar_dist_mul_31mb6.v: -------------------------------------------------------------------------------- 1 | // ============================================================== 2 | // File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC 3 | // Version: 2017.1 4 | // Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved. 5 | // 6 | // ============================================================== 7 | 8 | 9 | `timescale 1 ns / 1 ps 10 | 11 | module astar_dist_mul_31mb6_MulnS_0(clk, ce, a, b, p); 12 | input clk; 13 | input ce; 14 | input[31 - 1 : 0] a; // synthesis attribute keep a "true" 15 | input[62 - 1 : 0] b; // synthesis attribute keep b "true" 16 | output[91 - 1 : 0] p; 17 | 18 | reg signed [31 - 1 : 0] a_reg0; 19 | reg signed [62 - 1 : 0] b_reg0; 20 | wire signed [91 - 1 : 0] tmp_product; 21 | reg signed [91 - 1 : 0] buff0; 22 | reg signed [91 - 1 : 0] buff1; 23 | reg signed [91 - 1 : 0] buff2; 24 | 25 | assign p = buff2; 26 | assign tmp_product = a_reg0 * b_reg0; 27 | always @ (posedge clk) begin 28 | if (ce) begin 29 | a_reg0 <= a; 30 | b_reg0 <= b; 31 | buff0 <= tmp_product; 32 | buff1 <= buff0; 33 | buff2 <= buff1; 34 | end 35 | end 36 | endmodule 37 | 38 | `timescale 1 ns / 1 ps 39 | module astar_dist_mul_31mb6( 40 | clk, 41 | reset, 42 | ce, 43 | din0, 44 | din1, 45 | dout); 46 | 47 | parameter ID = 32'd1; 48 | parameter NUM_STAGE = 32'd1; 49 | parameter din0_WIDTH = 32'd1; 50 | parameter din1_WIDTH = 32'd1; 51 | parameter dout_WIDTH = 32'd1; 52 | input clk; 53 | input reset; 54 | input ce; 55 | input[din0_WIDTH - 1:0] din0; 56 | input[din1_WIDTH - 1:0] din1; 57 | output[dout_WIDTH - 1:0] dout; 58 | 59 | 60 | 61 | astar_dist_mul_31mb6_MulnS_0 astar_dist_mul_31mb6_MulnS_0_U( 62 | .clk( clk ), 63 | .ce( ce ), 64 | .a( din0 ), 65 | .b( din1 ), 66 | .p( dout )); 67 | 68 | endmodule 69 | 70 | -------------------------------------------------------------------------------- /cl_chronos/design/apps/astar/sinf_or_cosf_32_3cud.v: -------------------------------------------------------------------------------- 1 | // ============================================================== 2 | // File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC 3 | // Version: 2017.1 4 | // Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved. 5 | // 6 | // ============================================================== 7 | 8 | `timescale 1 ns / 1 ps 9 | (* rom_style = "distributed" *) module sinf_or_cosf_32_3cud_rom ( 10 | addr0, ce0, q0, clk); 11 | 12 | parameter DWIDTH = 23; 13 | parameter AWIDTH = 8; 14 | parameter MEM_SIZE = 256; 15 | 16 | input[AWIDTH-1:0] addr0; 17 | input ce0; 18 | output reg[DWIDTH-1:0] q0; 19 | input clk; 20 | 21 | // https://stackoverflow.com/questions/23554080/passing-string-values-to-systemverilog-parameter 22 | `define STRINGIFY(x) `"x`" 23 | `ifdef ROM_INIT_PATH 24 | localparam FNAME = `STRINGIFY(`ROM_INIT_PATH); 25 | `else 26 | localparam FNAME = "."; 27 | `endif 28 | (* ram_style = "distributed" *)reg [DWIDTH-1:0] ram[0:MEM_SIZE-1]; 29 | 30 | initial begin 31 | $readmemh({FNAME, "/sinf_or_cosf_32_3cud_rom.dat"}, ram); 32 | end 33 | 34 | 35 | 36 | always @(posedge clk) 37 | begin 38 | if (ce0) 39 | begin 40 | q0 <= ram[addr0]; 41 | end 42 | end 43 | 44 | 45 | 46 | endmodule 47 | 48 | 49 | `timescale 1 ns / 1 ps 50 | module sinf_or_cosf_32_3cud( 51 | reset, 52 | clk, 53 | address0, 54 | ce0, 55 | q0); 56 | 57 | parameter DataWidth = 32'd23; 58 | parameter AddressRange = 32'd256; 59 | parameter AddressWidth = 32'd8; 60 | input reset; 61 | input clk; 62 | input[AddressWidth - 1:0] address0; 63 | input ce0; 64 | output[DataWidth - 1:0] q0; 65 | 66 | 67 | 68 | sinf_or_cosf_32_3cud_rom sinf_or_cosf_32_3cud_rom_U( 69 | .clk( clk ), 70 | .addr0( address0 ), 71 | .ce0( ce0 ), 72 | .q0( q0 )); 73 | 74 | endmodule 75 | 76 | -------------------------------------------------------------------------------- /cl_chronos/design/apps/astar/sinf_or_cosf_32_3dEe.v: -------------------------------------------------------------------------------- 1 | // ============================================================== 2 | // File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC 3 | // Version: 2017.1 4 | // Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved. 5 | // 6 | // ============================================================== 7 | 8 | `timescale 1 ns / 1 ps 9 | (* rom_style = "distributed" *) module sinf_or_cosf_32_3dEe_rom ( 10 | addr0, ce0, q0, clk); 11 | 12 | parameter DWIDTH = 15; 13 | parameter AWIDTH = 8; 14 | parameter MEM_SIZE = 256; 15 | 16 | input[AWIDTH-1:0] addr0; 17 | input ce0; 18 | output reg[DWIDTH-1:0] q0; 19 | input clk; 20 | 21 | // https://stackoverflow.com/questions/23554080/passing-string-values-to-systemverilog-parameter 22 | `define STRINGIFY(x) `"x`" 23 | `ifdef ROM_INIT_PATH 24 | localparam FNAME = `STRINGIFY(`ROM_INIT_PATH); 25 | `else 26 | localparam FNAME = "."; 27 | `endif 28 | (* ram_style = "distributed" *)reg [DWIDTH-1:0] ram[0:MEM_SIZE-1]; 29 | 30 | initial begin 31 | $readmemh({FNAME, "/sinf_or_cosf_32_3dEe_rom.dat"}, ram); 32 | end 33 | 34 | 35 | 36 | always @(posedge clk) 37 | begin 38 | if (ce0) 39 | begin 40 | q0 <= ram[addr0]; 41 | end 42 | end 43 | 44 | 45 | 46 | endmodule 47 | 48 | 49 | `timescale 1 ns / 1 ps 50 | module sinf_or_cosf_32_3dEe( 51 | reset, 52 | clk, 53 | address0, 54 | ce0, 55 | q0); 56 | 57 | parameter DataWidth = 32'd15; 58 | parameter AddressRange = 32'd256; 59 | parameter AddressWidth = 32'd8; 60 | input reset; 61 | input clk; 62 | input[AddressWidth - 1:0] address0; 63 | input ce0; 64 | output[DataWidth - 1:0] q0; 65 | 66 | 67 | 68 | sinf_or_cosf_32_3dEe_rom sinf_or_cosf_32_3dEe_rom_U( 69 | .clk( clk ), 70 | .addr0( address0 ), 71 | .ce0( ce0 ), 72 | .q0( q0 )); 73 | 74 | endmodule 75 | 76 | -------------------------------------------------------------------------------- /cl_chronos/design/apps/astar/astar_dist_mul_31ncg.v: -------------------------------------------------------------------------------- 1 | // ============================================================== 2 | // File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC 3 | // Version: 2017.1 4 | // Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved. 5 | // 6 | // ============================================================== 7 | 8 | 9 | `timescale 1 ns / 1 ps 10 | 11 | module astar_dist_mul_31ncg_MulnS_1(clk, ce, a, b, p); 12 | input clk; 13 | input ce; 14 | input[31 - 1 : 0] a; // synthesis attribute keep a "true" 15 | input[91 - 1 : 0] b; // synthesis attribute keep b "true" 16 | output[108 - 1 : 0] p; 17 | 18 | reg signed [31 - 1 : 0] a_reg0; 19 | reg signed [91 - 1 : 0] b_reg0; 20 | wire signed [108 - 1 : 0] tmp_product; 21 | reg signed [108 - 1 : 0] buff0; 22 | reg signed [108 - 1 : 0] buff1; 23 | reg signed [108 - 1 : 0] buff2; 24 | 25 | assign p = buff2; 26 | assign tmp_product = a_reg0 * b_reg0; 27 | always @ (posedge clk) begin 28 | if (ce) begin 29 | a_reg0 <= a; 30 | b_reg0 <= b; 31 | buff0 <= tmp_product; 32 | buff1 <= buff0; 33 | buff2 <= buff1; 34 | end 35 | end 36 | endmodule 37 | 38 | `timescale 1 ns / 1 ps 39 | module astar_dist_mul_31ncg( 40 | clk, 41 | reset, 42 | ce, 43 | din0, 44 | din1, 45 | dout); 46 | 47 | parameter ID = 32'd1; 48 | parameter NUM_STAGE = 32'd1; 49 | parameter din0_WIDTH = 32'd1; 50 | parameter din1_WIDTH = 32'd1; 51 | parameter dout_WIDTH = 32'd1; 52 | input clk; 53 | input reset; 54 | input ce; 55 | input[din0_WIDTH - 1:0] din0; 56 | input[din1_WIDTH - 1:0] din1; 57 | output[dout_WIDTH - 1:0] dout; 58 | 59 | 60 | 61 | astar_dist_mul_31ncg_MulnS_1 astar_dist_mul_31ncg_MulnS_1_U( 62 | .clk( clk ), 63 | .ce( ce ), 64 | .a( din0 ), 65 | .b( din1 ), 66 | .p( dout )); 67 | 68 | endmodule 69 | 70 | -------------------------------------------------------------------------------- /cl_chronos/design/apps/astar/sinf_or_cosf_32_3bkb.v: -------------------------------------------------------------------------------- 1 | // ============================================================== 2 | // File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC 3 | // Version: 2017.1 4 | // Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved. 5 | // 6 | // ============================================================== 7 | 8 | `timescale 1 ns / 1 ps 9 | (* rom_style = "distributed" *) module sinf_or_cosf_32_3bkb_rom ( 10 | addr0, ce0, q0, clk); 11 | 12 | parameter DWIDTH = 30; 13 | parameter AWIDTH = 8; 14 | parameter MEM_SIZE = 256; 15 | 16 | input[AWIDTH-1:0] addr0; 17 | input ce0; 18 | output reg[DWIDTH-1:0] q0; 19 | input clk; 20 | 21 | // https://stackoverflow.com/questions/23554080/passing-string-values-to-systemverilog-parameter 22 | `define STRINGIFY(x) `"x`" 23 | `ifdef ROM_INIT_PATH 24 | localparam FNAME = `STRINGIFY(`ROM_INIT_PATH); 25 | `else 26 | localparam FNAME = "."; 27 | `endif 28 | 29 | (* ram_style = "distributed" *)reg [DWIDTH-1:0] ram[0:MEM_SIZE-1]; 30 | 31 | initial begin 32 | $readmemh({FNAME, "/sinf_or_cosf_32_3bkb_rom.dat"}, ram); 33 | end 34 | 35 | 36 | 37 | always @(posedge clk) 38 | begin 39 | if (ce0) 40 | begin 41 | q0 <= ram[addr0]; 42 | end 43 | end 44 | 45 | 46 | 47 | endmodule 48 | 49 | 50 | `timescale 1 ns / 1 ps 51 | module sinf_or_cosf_32_3bkb( 52 | reset, 53 | clk, 54 | address0, 55 | ce0, 56 | q0); 57 | 58 | parameter DataWidth = 32'd30; 59 | parameter AddressRange = 32'd256; 60 | parameter AddressWidth = 32'd8; 61 | input reset; 62 | input clk; 63 | input[AddressWidth - 1:0] address0; 64 | input ce0; 65 | output[DataWidth - 1:0] q0; 66 | 67 | 68 | 69 | sinf_or_cosf_32_3bkb_rom sinf_or_cosf_32_3bkb_rom_U( 70 | .clk( clk ), 71 | .addr0( address0 ), 72 | .ce0( ce0 ), 73 | .q0( q0 )); 74 | 75 | endmodule 76 | 77 | -------------------------------------------------------------------------------- /cl_chronos/validation/scripts/gen_synth.py: -------------------------------------------------------------------------------- 1 | 2 | # This script reads apps.txt and generates the synthesis scripts for each 3 | # application 4 | 5 | import os 6 | from os import listdir 7 | import datetime 8 | 9 | runs = listdir("../synth") 10 | print(runs) 11 | 12 | fapps = open("apps.txt", "r") 13 | 14 | d = datetime.datetime.today() 15 | index = 0 16 | scripts_dir = os.getcwd() 17 | while(True): 18 | dirname = str(d.year) + "-" + format(d.month, '02') + "-" + format(d.day, '02') + "_" + str(index) 19 | if dirname not in runs: 20 | print("creating directory "+dirname) 21 | os.mkdir("../synth/" + dirname) 22 | os.chdir("../synth/" + dirname) 23 | print(os.getcwd()) 24 | synth_dir = os.getcwd() 25 | break 26 | index = index+1 27 | 28 | for line in fapps: 29 | if line.strip() == "": 30 | continue 31 | if line.strip().startswith("#"): 32 | continue 33 | print(line) 34 | os.chdir(synth_dir) 35 | words = line.split() 36 | config = words[-1]; 37 | app = words[0]; 38 | pipe = "" 39 | if (words[1] == "pipe"): 40 | pipe = "pipe" 41 | print("making directory "+config) 42 | os.mkdir(config) 43 | print("copying all RTL") 44 | cmd = "cp -r ../../../design " + config 45 | os.system(cmd) 46 | cmd = "cp ../../scripts/configs/" + config +".sv " + config+"/design/config.sv" 47 | os.system(cmd) 48 | print(cmd) 49 | 50 | print("copying build scripts") 51 | os.mkdir(config +"/build") 52 | cmd = os.path.join(scripts_dir, "build_scripts") 53 | cmd = "cp -r " + cmd +"/* " +config+ "/build/" 54 | print(cmd) 55 | os.system(cmd) 56 | 57 | cmd = "mv " + config + "/build/run_synth.py " + config + "/" 58 | print(cmd) 59 | os.system(cmd) 60 | 61 | print("configuring app") 62 | os.chdir(config + "/design") 63 | cmd = "python ./scripts/gen_cores.py "+app +" " + pipe 64 | print(cmd) 65 | os.system(cmd) 66 | 67 | os.chdir(scripts_dir) 68 | 69 | -------------------------------------------------------------------------------- /cl_chronos/verif/scripts/Makefile.vcs: -------------------------------------------------------------------------------- 1 | # Amazon FPGA Hardware Development Kit 2 | # 3 | # Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. 4 | # 5 | # Licensed under the Amazon Software License (the "License"). You may not use 6 | # this file except in compliance with the License. A copy of the License is 7 | # located at 8 | # 9 | # http://aws.amazon.com/asl/ 10 | # 11 | # or in the "license" file accompanying this file. This file is distributed on 12 | # an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or 13 | # implied. See the License for the specific language governing permissions and 14 | # limitations under the License. 15 | 16 | 17 | ################################################################## 18 | ## Makefile For VCS compiles and simulations 19 | ## Step to run : 20 | ## 1. make create_libs VCS=1 -> To generate xilinx compile 21 | ## libraries. This is a one time step 22 | ## 2. make all VCS=1 -> Runs the test 23 | ################################################################## 24 | 25 | compile: $(COMPLIB_DIR) 26 | mkdir -p $(SIM_DIR) 27 | cd ${SIM_DIR} && ln -s -f ../vcs_complib/synopsys_sim.setup 28 | cd $(SIM_DIR) && vlogan -ntb_opts tb_timescale=1ps/1ps -timescale=1ps/1ps -sverilog +systemverilogext+.sv +libext+.sv +libext+.v -full64 -lca -v2005 +v2k -l compile.vlogan.log -f $(SCRIPTS_DIR)/top.$(SIMULATOR).f +define+VCS $(DEFINES) +lint=TFIPC-L 29 | cd $(SIM_DIR) && vcs tb $(TEST) $(C_TEST_NAME) -CFLAGS "-I$(C_INC_DIR)" -debug_all -M -I +lint=TFIPC-L -debug_pp glbl -ntb_opts tb_timescale=1ps/1ps -timescale=1ps/1ps -sverilog -full64 +memcbk -licqueue -lca -v2005 -l compile.vcs.log 30 | 31 | run: 32 | cd $(SIM_DIR) && ./simv -l $(TEST).log $(PLUSARGS) +ntb_random_seed_automatic +vpdfile+$(TEST).vpd 33 | 34 | $(COMPLIB_DIR): 35 | cd $(SIM_ROOT)/.. && echo "compile_simlib -language all -dir $(COMPLIB_DIR) -simulator $(SIMULATOR) -library all -family all" > create_libs.tcl 36 | cd $(SIM_ROOT)/.. && vivado -mode batch -source create_libs.tcl 37 | cd $(SIM_ROOT)/.. && rm -rf create_libs.tcl 38 | -------------------------------------------------------------------------------- /cl_chronos/verif/tests/test_null.sv: -------------------------------------------------------------------------------- 1 | /** $lic$ 2 | * Copyright (C) 2014-2019 by Massachusetts Institute of Technology 3 | * 4 | * This file is part of the Chronos FPGA Acceleration Framework. 5 | * 6 | * Chronos is free software; you can redistribute it and/or modify it under the 7 | * terms of the GNU General Public License as published by the Free Software 8 | * Foundation, version 2. 9 | * 10 | * If you use this framework in your research, we request that you reference 11 | * the Chronos paper ("Chronos: Efficient Speculative Parallelism for 12 | * Accelerators", Abeydeera and Sanchez, ASPLOS-25, March 2020), and that 13 | * you send us a citation of your work. 14 | * 15 | * Chronos is distributed in the hope that it will be useful, but WITHOUT ANY 16 | * WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS 17 | * FOR A PARTICULAR PURPOSE. See the GNU General Public License for more 18 | * details. 19 | * 20 | * You should have received a copy of the GNU General Public License along with 21 | * this program. If not, see . 22 | */ 23 | 24 | // Amazon FPGA Hardware Development Kit 25 | // 26 | // Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. 27 | // 28 | // Licensed under the Amazon Software License (the "License"). You may not use 29 | // this file except in compliance with the License. A copy of the License is 30 | // located at 31 | // 32 | // http://aws.amazon.com/asl/ 33 | // 34 | // or in the "license" file accompanying this file. This file is distributed on 35 | // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or 36 | // implied. See the License for the specific language governing permissions and 37 | // limitations under the License. 38 | 39 | module test_null(); 40 | 41 | initial begin 42 | int exit_code; 43 | 44 | tb.power_up(); 45 | 46 | 47 | tb.test_main(exit_code); 48 | 49 | #50ns; 50 | 51 | tb.power_down(); 52 | 53 | $finish; 54 | end 55 | 56 | endmodule // test_null 57 | -------------------------------------------------------------------------------- /cl_chronos/design/gvt_arbiter.sv: -------------------------------------------------------------------------------- 1 | /** $lic$ 2 | * Copyright (C) 2014-2019 by Massachusetts Institute of Technology 3 | * 4 | * This file is part of the Chronos FPGA Acceleration Framework. 5 | * 6 | * Chronos is free software; you can redistribute it and/or modify it under the 7 | * terms of the GNU General Public License as published by the Free Software 8 | * Foundation, version 2. 9 | * 10 | * If you use this framework in your research, we request that you reference 11 | * the Chronos paper ("Chronos: Efficient Speculative Parallelism for 12 | * Accelerators", Abeydeera and Sanchez, ASPLOS-25, March 2020), and that 13 | * you send us a citation of your work. 14 | * 15 | * Chronos is distributed in the hope that it will be useful, but WITHOUT ANY 16 | * WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS 17 | * FOR A PARTICULAR PURPOSE. See the GNU General Public License for more 18 | * details. 19 | * 20 | * You should have received a copy of the GNU General Public License along with 21 | * this program. If not, see . 22 | */ 23 | 24 | import chronos::*; 25 | 26 | module gvt_arbiter ( 27 | input clk, 28 | input rstn, 29 | 30 | input vt_t [C_N_TILES-1:0] lvt, 31 | output vt_t gvt 32 | ); 33 | // Tree of comparators 34 | vt_t tree [$clog2(C_N_TILES):0][C_N_TILES-1:0]; 35 | 36 | genvar i,j; 37 | 38 | generate 39 | for (i=0;i=0;i--) begin 46 | for (j=0;j< 2**i; j++) begin 47 | always_ff @(posedge clk) begin 48 | tree[i][j] <= (tree[i+1][j*2] < tree[i+1][j*2+1]) ? 49 | tree[i+1][j*2] : tree[i+1][j*2+1]; 50 | end 51 | end 52 | end 53 | endgenerate 54 | 55 | 56 | lib_pipe #( 57 | .WIDTH(TS_WIDTH + TB_WIDTH), 58 | .STAGES(2) 59 | ) GVT_PIPE ( 60 | .clk(clk), 61 | .rst_n(1'b1), 62 | 63 | .in_bus ( tree[0][0] ), 64 | .out_bus( gvt ) 65 | ); 66 | 67 | 68 | endmodule 69 | -------------------------------------------------------------------------------- /cl_chronos/design/apps/astar/astar_dist_mux_83fYi.v: -------------------------------------------------------------------------------- 1 | // ============================================================== 2 | // File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC 3 | // Version: 2017.1 4 | // Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved. 5 | // 6 | // ============================================================== 7 | 8 | 9 | `timescale 1ns/1ps 10 | 11 | module astar_dist_mux_83fYi #( 12 | parameter 13 | ID = 0, 14 | NUM_STAGE = 1, 15 | din1_WIDTH = 32, 16 | din2_WIDTH = 32, 17 | din3_WIDTH = 32, 18 | din4_WIDTH = 32, 19 | din5_WIDTH = 32, 20 | din6_WIDTH = 32, 21 | din7_WIDTH = 32, 22 | din8_WIDTH = 32, 23 | din9_WIDTH = 32, 24 | dout_WIDTH = 32 25 | )( 26 | input [0 : 0] din1, 27 | input [0 : 0] din2, 28 | input [0 : 0] din3, 29 | input [0 : 0] din4, 30 | input [0 : 0] din5, 31 | input [0 : 0] din6, 32 | input [0 : 0] din7, 33 | input [0 : 0] din8, 34 | input [2 : 0] din9, 35 | output [0 : 0] dout); 36 | 37 | // puts internal signals 38 | wire [2 : 0] sel; 39 | // level 1 signals 40 | wire [0 : 0] mux_1_0; 41 | wire [0 : 0] mux_1_1; 42 | wire [0 : 0] mux_1_2; 43 | wire [0 : 0] mux_1_3; 44 | // level 2 signals 45 | wire [0 : 0] mux_2_0; 46 | wire [0 : 0] mux_2_1; 47 | // level 3 signals 48 | wire [0 : 0] mux_3_0; 49 | 50 | assign sel = din9; 51 | 52 | // Generate level 1 logic 53 | assign mux_1_0 = (sel[0] == 0)? din1 : din2; 54 | assign mux_1_1 = (sel[0] == 0)? din3 : din4; 55 | assign mux_1_2 = (sel[0] == 0)? din5 : din6; 56 | assign mux_1_3 = (sel[0] == 0)? din7 : din8; 57 | 58 | // Generate level 2 logic 59 | assign mux_2_0 = (sel[1] == 0)? mux_1_0 : mux_1_1; 60 | assign mux_2_1 = (sel[1] == 0)? mux_1_2 : mux_1_3; 61 | 62 | // Generate level 3 logic 63 | assign mux_3_0 = (sel[2] == 0)? mux_2_0 : mux_2_1; 64 | 65 | // output logic 66 | assign dout = mux_3_0; 67 | 68 | endmodule 69 | -------------------------------------------------------------------------------- /cl_chronos/software/verif_rtl/src/test_null.c: -------------------------------------------------------------------------------- 1 | /** $lic$ 2 | * Copyright (C) 2014-2019 by Massachusetts Institute of Technology 3 | * 4 | * This file is part of the Chronos FPGA Acceleration Framework. 5 | * 6 | * Chronos is free software; you can redistribute it and/or modify it under the 7 | * terms of the GNU General Public License as published by the Free Software 8 | * Foundation, version 2. 9 | * 10 | * If you use this framework in your research, we request that you reference 11 | * the Chronos paper ("Chronos: Efficient Speculative Parallelism for 12 | * Accelerators", Abeydeera and Sanchez, ASPLOS-25, March 2020), and that 13 | * you send us a citation of your work. 14 | * 15 | * Chronos is distributed in the hope that it will be useful, but WITHOUT ANY 16 | * WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS 17 | * FOR A PARTICULAR PURPOSE. See the GNU General Public License for more 18 | * details. 19 | * 20 | * You should have received a copy of the GNU General Public License along with 21 | * this program. If not, see . 22 | */ 23 | 24 | // Amazon FPGA Hardware Development Kit 25 | // 26 | // Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. 27 | // 28 | // Licensed under the Amazon Software License (the "License"). You may not use 29 | // this file except in compliance with the License. A copy of the License is 30 | // located at 31 | // 32 | // http://aws.amazon.com/asl/ 33 | // 34 | // or in the "license" file accompanying this file. This file is distributed on 35 | // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or 36 | // implied. See the License for the specific language governing permissions and 37 | // limitations under the License. 38 | 39 | 40 | #include 41 | #include 42 | #include 43 | 44 | // Vivado does not support svGetScopeFromName 45 | #ifdef INCLUDE_DPI_CALLS 46 | #ifndef VIVADO_SIM 47 | #include "svdpi.h" 48 | #endif 49 | #endif 50 | 51 | #include "sh_dpi_tasks.h" 52 | 53 | void test_main(uint32_t *exit_code) { 54 | 55 | // NULL Test 56 | 57 | *exit_code = 0; 58 | } 59 | -------------------------------------------------------------------------------- /cl_chronos/build/constraints/cl_pnr_user.xdc: -------------------------------------------------------------------------------- 1 | # This contains the CL specific constraints for Top level PNR 2 | 3 | #create_pblock pblock_CL_top 4 | #add_cells_to_pblock [get_pblocks pblock_CL_top] [get_cells [list {CL/tile[0].TILE}]] 5 | #add_cells_to_pblock [get_pblocks pblock_CL_top] [get_cells [list {CL/tile[1].TILE}]] 6 | #add_cells_to_pblock [get_pblocks pblock_CL_top] [get_cells [list {CL/tile[2].TILE}]] 7 | #add_cells_to_pblock [get_pblocks pblock_CL_top] [get_cells [list {CL/tile[3].TILE}]] 8 | #resize_pblock [get_pblocks pblock_CL_top] -add {CLOCKREGION_X0Y10:CLOCKREGION_X5Y14} 9 | #set_property PARENT pblock_CL [get_pblocks pblock_CL_top] 10 | 11 | #create_pblock pblock_CL_mid 12 | #add_cells_to_pblock [get_pblocks pblock_CL_mid] [get_cells [list {CL/tile[4].TILE}]] 13 | #add_cells_to_pblock [get_pblocks pblock_CL_mid] [get_cells [list {CL/tile[5].TILE}]] 14 | #resize_pblock [get_pblocks pblock_CL_mid] -add {CLOCKREGION_X0Y5:CLOCKREGION_X3Y9} 15 | #set_property PARENT pblock_CL [get_pblocks pblock_CL_mid] 16 | 17 | #create_pblock pblock_CL_bot 18 | #add_cells_to_pblock [get_pblocks pblock_CL_bot] [get_cells [list {CL/tile[6].TILE}]] 19 | #add_cells_to_pblock [get_pblocks pblock_CL_bot] [get_cells [list {CL/tile[7].TILE}]] 20 | #resize_pblock [get_pblocks pblock_CL_bot] -add {CLOCKREGION_X0Y0:CLOCKREGION_X3Y4} 21 | #set_property PARENT pblock_CL [get_pblocks pblock_CL_bot] 22 | 23 | #set_clock_groups -name TIG_SRAI_1 -asynchronous -group [get_clocks -of_objects [get_pins static_sh/SH_DEBUG_BRIDGE/inst/bsip/inst/USE_SOFTBSCAN.U_TAP_TCKBUFG/O]] -group [get_clocks -of_objects [get_pins SH/kernel_clks_i/clkwiz_sys_clk/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst/CLKOUT0]] 24 | #set_clock_groups -name TIG_SRAI_2 -asynchronous -group [get_clocks -of_objects [get_pins static_sh/SH_DEBUG_BRIDGE/inst/bsip/inst/USE_SOFTBSCAN.U_TAP_TCKBUFG/O]] -group [get_clocks drck] 25 | #set_clock_groups -name TIG_SRAI_3 -asynchronous -group [get_clocks -of_objects [get_pins static_sh/SH_DEBUG_BRIDGE/inst/bsip/inst/USE_SOFTBSCAN.U_TAP_TCKBUFG/O]] -group [get_clocks -of_objects [get_pins static_sh/pcie_inst/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_userclk/O]] 26 | 27 | 28 | -------------------------------------------------------------------------------- /cl_chronos/validation/scripts/build_scripts/constraints/cl_pnr_user.xdc: -------------------------------------------------------------------------------- 1 | # This contains the CL specific constraints for Top level PNR 2 | 3 | #create_pblock pblock_CL_top 4 | #add_cells_to_pblock [get_pblocks pblock_CL_top] [get_cells [list {CL/tile[0].TILE}]] 5 | #add_cells_to_pblock [get_pblocks pblock_CL_top] [get_cells [list {CL/tile[1].TILE}]] 6 | #add_cells_to_pblock [get_pblocks pblock_CL_top] [get_cells [list {CL/tile[2].TILE}]] 7 | #add_cells_to_pblock [get_pblocks pblock_CL_top] [get_cells [list {CL/tile[3].TILE}]] 8 | #resize_pblock [get_pblocks pblock_CL_top] -add {CLOCKREGION_X0Y10:CLOCKREGION_X5Y14} 9 | #set_property PARENT pblock_CL [get_pblocks pblock_CL_top] 10 | 11 | #create_pblock pblock_CL_mid 12 | #add_cells_to_pblock [get_pblocks pblock_CL_mid] [get_cells [list {CL/tile[4].TILE}]] 13 | #add_cells_to_pblock [get_pblocks pblock_CL_mid] [get_cells [list {CL/tile[5].TILE}]] 14 | #resize_pblock [get_pblocks pblock_CL_mid] -add {CLOCKREGION_X0Y5:CLOCKREGION_X3Y9} 15 | #set_property PARENT pblock_CL [get_pblocks pblock_CL_mid] 16 | 17 | #create_pblock pblock_CL_bot 18 | #add_cells_to_pblock [get_pblocks pblock_CL_bot] [get_cells [list {CL/tile[6].TILE}]] 19 | #add_cells_to_pblock [get_pblocks pblock_CL_bot] [get_cells [list {CL/tile[7].TILE}]] 20 | #resize_pblock [get_pblocks pblock_CL_bot] -add {CLOCKREGION_X0Y0:CLOCKREGION_X3Y4} 21 | #set_property PARENT pblock_CL [get_pblocks pblock_CL_bot] 22 | 23 | #set_clock_groups -name TIG_SRAI_1 -asynchronous -group [get_clocks -of_objects [get_pins static_sh/SH_DEBUG_BRIDGE/inst/bsip/inst/USE_SOFTBSCAN.U_TAP_TCKBUFG/O]] -group [get_clocks -of_objects [get_pins SH/kernel_clks_i/clkwiz_sys_clk/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst/CLKOUT0]] 24 | #set_clock_groups -name TIG_SRAI_2 -asynchronous -group [get_clocks -of_objects [get_pins static_sh/SH_DEBUG_BRIDGE/inst/bsip/inst/USE_SOFTBSCAN.U_TAP_TCKBUFG/O]] -group [get_clocks drck] 25 | #set_clock_groups -name TIG_SRAI_3 -asynchronous -group [get_clocks -of_objects [get_pins static_sh/SH_DEBUG_BRIDGE/inst/bsip/inst/USE_SOFTBSCAN.U_TAP_TCKBUFG/O]] -group [get_clocks -of_objects [get_pins static_sh/pcie_inst/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_userclk/O]] 26 | 27 | 28 | -------------------------------------------------------------------------------- /cl_chronos/validation/scripts/build_scripts/run_synth.py: -------------------------------------------------------------------------------- 1 | # export CL_DIR=$(pwd) 2 | # run build/script/aws_build_dcp_from_cl.sh in foreground 3 | # run aws s3 cp 4 | # run create fpga-image and write output to agfi.txt 5 | # read agfi.txt and append to ../agfi_list.txt 6 | 7 | 8 | ## Need to be run from validation/synth/// 9 | 10 | #Set the location of aws executable, if running on AWS instances it is just "aws" 11 | AWS_PATH = "aws" 12 | 13 | S3_BUCKET = "chronos-runs" 14 | S3_KEY = "dcp/" 15 | S3_PATH = "s3://" + S3_BUCKET + "/" + S3_KEY 16 | 17 | 18 | 19 | import os 20 | def run_cmd(cmd): 21 | print(cmd) 22 | os.system(cmd) 23 | 24 | cwd = os.getcwd() 25 | app = cwd.split("/")[-1] 26 | 27 | ## Run synthesis 28 | os.chdir("build/scripts") 29 | cmd = "CL_DIR=" + cwd + " ./aws_build_dcp_from_cl.sh" 30 | run_cmd(cmd) 31 | 32 | ## copy tar to aws s3 33 | os.chdir(os.path.join(cwd, "build", "checkpoints", "to_aws")) 34 | print(os.getcwd()) 35 | file_list = os.listdir(os.getcwd()) 36 | file_list = [f for f in file_list if f.find(".tar") >0] #filter tar files 37 | print(file_list) 38 | if len(file_list) == 0: 39 | print("tar file not found. Exiting...") 40 | exit(0) 41 | ## TODO: IF multiple tar files select the most recent one 42 | tar_file = file_list[0] 43 | cmd = AWS_PATH + " s3 cp " + tar_file +" " + S3_PATH + tar_file 44 | run_cmd(cmd) 45 | 46 | ## Run create-fpga-image 47 | cmd = AWS_PATH + " ec2 create-fpga-image --name " + app 48 | cmd += " --input-storage-location Bucket=" + S3_BUCKET 49 | cmd += ",Key=" + S3_KEY+tar_file 50 | cmd += " --logs-storage-location Bucket="+S3_BUCKET 51 | cmd += ",Key=logs/"+tar_file 52 | cmd += " | tee agfi.txt" 53 | run_cmd(cmd) 54 | 55 | ## Read agfi.txt and append to ../agfi_list.txt 56 | f = open("agfi.txt", "r") 57 | agfi = "" 58 | afi = "" 59 | for line in f: 60 | if (line.find("agfi-")>0): 61 | agfi = line.split(":")[1].split("\"")[1] 62 | print(agfi) 63 | if (line.find("afi-")>0): 64 | afi = line.split(":")[1].split("\"")[1] 65 | print(afi) 66 | append_line = app +" "+agfi + " "+afi +"\n" 67 | os.chdir(cwd) 68 | f = open("../agfi_list.txt", "a+") 69 | f.write(append_line) 70 | f.close() 71 | 72 | -------------------------------------------------------------------------------- /cl_chronos/verif/scripts/Makefile.vivado: -------------------------------------------------------------------------------- 1 | # Amazon FPGA Hardware Development Kit 2 | # 3 | # Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. 4 | # 5 | # Licensed under the Amazon Software License (the "License"). You may not use 6 | # this file except in compliance with the License. A copy of the License is 7 | # located at 8 | # 9 | # http://aws.amazon.com/asl/ 10 | # 11 | # or in the "license" file accompanying this file. This file is distributed on 12 | # an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or 13 | # implied. See the License for the specific language governing permissions and 14 | # limitations under the License. 15 | 16 | ################################################################## 17 | ## Makefile For Vivado compiles and simulations 18 | ################################################################## 19 | 20 | compile: 21 | mkdir -p $(SIM_DIR) 22 | cd $(SIM_DIR) && xsc $(C_TEST_NAME) --additional_option "-I$(C_INC_DIR)" --additional_option "-DVIVADO_SIM" 23 | # cd $(SIM_DIR) && xvlog --sv -m64 --initfile $(SCRIPTS_DIR)/xsim.ini --work xil_defaultlib --relax -f $(SCRIPTS_DIR)/top.vivado.f 24 | cd $(SIM_DIR) && xvlog --sv -m64 --initfile $(XILINX_VIVADO)/data/xsim/ip/xsim_ip.ini --work xil_defaultlib --relax -f $(SCRIPTS_DIR)/top.vivado.f 25 | # cd $(SIM_DIR) && xelab -m64 --initfile $(SCRIPTS_DIR)/xsim.ini --timescale 1ps/1ps --debug typical --relax --mt 8 -L axi_clock_converter_v2_1_11 -L generic_baseblocks_v2_1_0 -L axi_infrastructure_v1_1_0 -L axi_register_slice_v2_1_12 -L fifo_generator_v13_1_4 -L axi_data_fifo_v2_1_11 -L axi_crossbar_v2_1_13 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm -sv_lib dpi --snapshot tb xil_defaultlib.tb xil_defaultlib.glbl xil_defaultlib.$(TEST) 26 | cd $(SIM_DIR) && xelab -m64 --initfile $(XILINX_VIVADO)/data/xsim/ip/xsim_ip.ini --timescale 1ps/1ps --debug typical --relax --mt 8 -L axi_clock_converter_v2_1_11 -L generic_baseblocks_v2_1_0 -L axi_infrastructure_v1_1_0 -L axi_register_slice_v2_1_12 -L fifo_generator_v13_1_4 -L axi_data_fifo_v2_1_11 -L axi_crossbar_v2_1_13 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm -sv_lib dpi --snapshot tb xil_defaultlib.tb xil_defaultlib.glbl xil_defaultlib.$(TEST) 27 | 28 | 29 | run: 30 | cd $(SIM_DIR) && xsim -R -log test.log -tclbatch $(SCRIPTS_DIR)/waves.tcl tb 31 | 32 | -------------------------------------------------------------------------------- /cl_chronos/verif/scripts/Makefile.questa: -------------------------------------------------------------------------------- 1 | # Amazon FPGA Hardware Development Kit 2 | # 3 | # Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. 4 | # 5 | # Licensed under the Amazon Software License (the "License"). You may not use 6 | # this file except in compliance with the License. A copy of the License is 7 | # located at 8 | # 9 | # http://aws.amazon.com/asl/ 10 | # 11 | # or in the "license" file accompanying this file. This file is distributed on 12 | # an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or 13 | # implied. See the License for the specific language governing permissions and 14 | # limitations under the License. 15 | 16 | 17 | ################################################################## 18 | ## Makefile For Questa compiles and simulations 19 | ## Step to run : 20 | ## 1. make create_libs QUESTA=1 -> To generate xilinx compile 21 | ## libraries. This is a one time step 22 | ## 2. make all QUESTA=1 -> Runs the test 23 | ################################################################## 24 | 25 | compile: $(COMPLIB_DIR) 26 | mkdir -p $(SIM_DIR) 27 | cd ${SIM_DIR} && ln -s -f ../questa_complib/modelsim.ini 28 | cd $(SIM_DIR) && vlog $(C_TEST_NAME) -ccflags "-I$(C_INC_DIR)" 29 | cd $(SIM_DIR) && vlog -mfcu -sv -64 -timescale 1ps/1ps -93 -L $(COMPLIB_DIR)/unisims_ver -L $(COMPLIB_DIR)/unimacro_ver -L $(COMPLIB_DIR)/secureip -f $(SCRIPTS_DIR)/top.$(SIMULATOR).f 30 | 31 | run: 32 | cd $(SIM_DIR) && vsim -c -voptargs="+acc" -64 -t ps -sv_seed random -L $(COMPLIB_DIR)/unisims_ver -L $(COMPLIB_DIR)/unisim -L $(COMPLIB_DIR)/unifast_ver -L $(COMPLIB_DIR)/unifast -L $(COMPLIB_DIR)/unimacro_ver -L $(COMPLIB_DIR)/unimacro -L $(COMPLIB_DIR)/secureip -L $(COMPLIB_DIR)/axi_register_slice_v2_1_12 -L $(COMPLIB_DIR)/axi_infrastructure_v1_1_0 -L $(COMPLIB_DIR)/axi_crossbar_v2_1_13 -L $(COMPLIB_DIR)/xpm -L $(COMPLIB_DIR)/axi_clock_converter_v2_1_11 -L $(COMPLIB_DIR)/fifo_generator_v13_1_4 -L $(COMPLIB_DIR)/axi_data_fifo_v2_1_11 -L $(COMPLIB_DIR)/generic_baseblocks_v2_1_0 -do "run -all; quit -f" tb glbl $(TEST) 33 | 34 | $(COMPLIB_DIR): 35 | cd $(SIM_ROOT)/.. && echo "compile_simlib -language all -dir $(COMPLIB_DIR) -simulator $(SIMULATOR) -library all -family all" > create_libs.tcl 36 | cd $(SIM_ROOT)/.. && vivado -mode batch -source create_libs.tcl 37 | cd $(SIM_ROOT)/.. && rm -rf create_libs.tcl 38 | 39 | 40 | -------------------------------------------------------------------------------- /cl_chronos/verif/scripts/Makefile.ies: -------------------------------------------------------------------------------- 1 | # Amazon FPGA Hardware Development Kit 2 | # 3 | # Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. 4 | # 5 | # Licensed under the Amazon Software License (the "License"). You may not use 6 | # this file except in compliance with the License. A copy of the License is 7 | # located at 8 | # 9 | # http://aws.amazon.com/asl/ 10 | # 11 | # or in the "license" file accompanying this file. This file is distributed on 12 | # an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or 13 | # implied. See the License for the specific language governing permissions and 14 | # limitations under the License. 15 | 16 | 17 | ################################################################## 18 | ## Makefile For IES compiles and simulations 19 | ## Step to run : 20 | ## 1. make create_libs IES=1 -> To generate xilinx compile 21 | ## libraries. This is a one time step 22 | ## 2. make all IES=1 -> Runs the test 23 | ################################################################## 24 | 25 | compile: $(COMPLIB_DIR) 26 | mkdir -p $(SIM_DIR) 27 | cd $(SIM_DIR) && ln -s -f ../ies_complib/cds.lib 28 | cd $(SIM_DIR) && ln -s -f ../ies_complib/hdl.var 29 | cd $(SIM_DIR) && gcc -fPIC -g -shared -I$(C_SDK_USR_INC_DIR) -I$(C_SDK_USR_UTILS_DIR) -I$(C_COMMON_DIR)/include -I$(C_COMMON_DIR)/src -I$(C_INC_DIR) -DSV_TEST -DSCOPE -DIES_SIM -DINT_MAIN -o libdpi.so $(C_FILES) -I/`ncroot`/tools/include 30 | cd $(SIM_DIR) && irun -64bit -elaborate +libext+.v+.sv -disable_sem2009 -l compile.ies.log -I$(C_SDK_USR_INC_DIR) -I$(C_SDK_USR_UTILS_DIR) -I$(C_COMMON_DIR) -define SV_TEST -define DMA_TEST -define SCOPE -define IES_SIM $(DEFAULT_DEFINES) -I$(C_INC_DIR)/include -I$(C_INC_DIR)/src -f $(SCRIPTS_DIR)/top.$(SIMULATOR).f -top tb -top glbl -top $(TEST) $(DEFINES) $(TEST_NAME) -timescale 1ps/1ps 31 | 32 | run: 33 | 34 | ifeq ($(TEST),test_null) 35 | cd $(SIM_DIR) && irun -R -access +rwc -timescale 1ps/1ps -l $(C_TEST).log $(PLUSARGS) +vpdfile+$(TEST).vpd 36 | else 37 | cd $(SIM_DIR) && irun -R -access +rwc -timescale 1ps/1ps -l $(TEST).log $(PLUSARGS) +vpdfile+$(TEST).vpd 38 | endif 39 | 40 | $(COMPLIB_DIR): 41 | cd $(SIM_ROOT) && echo "compile_simlib -language all -dir $(COMPLIB_DIR) -simulator $(SIMULATOR) -library all -family all" > create_libs.tcl 42 | cd $(SIM_ROOT) && vivado -mode batch -source create_libs.tcl 43 | cd $(SIM_ROOT) && rm -rf create_libs.tcl 44 | -------------------------------------------------------------------------------- /cl_chronos/validation/scripts/run_validation.py: -------------------------------------------------------------------------------- 1 | # Validation of results in the paper is done by running five separate python 2 | # scripts one after the other. This script specifies this sequence. 3 | 4 | # However, running the entire script might take about a week (mostly to run the 5 | # FPGA build flow), hence it is recommended that the scripts are run 6 | # individually in the specified order 7 | 8 | # To facilitate quick evaluation, we also provide precompiled images. 9 | # To use them, run this script with the --precompiled option. 10 | 11 | import os 12 | import sys 13 | def run_cmd(cmd): 14 | print(cmd) 15 | os.system(cmd) 16 | 17 | def get_latest_dir(dir_name): 18 | ## Returns the name of the latest subdirectory in dir_name 19 | dirs = os.listdir(dir_name) 20 | dirs = sorted([d for d in dirs if d.startswith("20")]) 21 | return dirs[-1] 22 | 23 | Use_Precompiled_Images = False 24 | if len(sys.argv)>1: 25 | if sys.argv[1] == '--precompiled': 26 | Use_Precompiled_Images = True 27 | 28 | 29 | if not Use_Precompiled_Images: 30 | # Step 1: Create Synthesis scripts for each application (gen_synth.py) 31 | # This script reads apps.txt and generates the synthesis scripts for each 32 | # application. These synthesis scripts are placed in 33 | # validation/synth/ 34 | run_cmd("python gen_synth.py") 35 | 36 | 37 | # Step 2: Launch these synthesis scripts for each app sequentially. 38 | # The output of this is the agfi_list.txt specifying AGFI-ID for each FPGA image 39 | syn_dir = get_latest_dir("../synth/") 40 | run_cmd("python launch_synth.py " + syn_dir) 41 | 42 | # Step 3: Runs a set of experiments (experiments.txt) on the generated FPGA images and records 43 | # their output ("../runs/") 44 | run_cmd("python run.py ../synth/" + syn_dir + "/agfi_list.txt") 45 | else: 46 | run_cmd("aws s3 cp s3://chronos-images/agfi_list.txt ." ) 47 | run_cmd("python run.py agfi_list.txt") 48 | 49 | 50 | ## Following steps require matplotlib 51 | ## Please run 'sudo yum install python-matplotlib' if necessary 52 | 53 | 54 | # Step 4: Averages the result from experiments. Writes output to 55 | # chronos_runtimes.txt 56 | # Also generates the cycle breakdown and queue utilization plots. 57 | run_dir = get_latest_dir("../runs/") 58 | run_cmd("python summarize.py " + run_dir) 59 | 60 | 61 | # Step 5: Generates the speedup plot in Figure 10, 11 and 14 62 | run_cmd("python plot.py chronos_runtimes.txt ../baselines/runtime_ref.txt") 63 | -------------------------------------------------------------------------------- /cl_chronos/design/apps/riscv/GenSwarm.scala: -------------------------------------------------------------------------------- 1 | package vexriscv.demo 2 | 3 | import spinal.core._ 4 | import vexriscv.ip.{DataCacheConfig, InstructionCacheConfig} 5 | import vexriscv.plugin._ 6 | import vexriscv.{VexRiscv, VexRiscvConfig, plugin} 7 | 8 | /** 9 | * Created by spinalvm on 15.06.17. 10 | */ 11 | object GenChronos extends App{ 12 | def cpu() = new VexRiscv( 13 | config = VexRiscvConfig( 14 | plugins = List( 15 | new PcManagerSimplePlugin( 16 | resetVector = 0x80000000l, 17 | relaxedPcCalculation = false 18 | ), 19 | new IBusCachedPlugin( 20 | prediction = DYNAMIC_TARGET, 21 | historyRamSizeLog2 = 8, 22 | config = InstructionCacheConfig( 23 | cacheSize = 1024*4, 24 | bytePerLine =32, 25 | wayCount = 1, 26 | addressWidth = 32, 27 | cpuDataWidth = 32, 28 | memDataWidth = 32, 29 | catchIllegalAccess = true, 30 | catchAccessFault = true, 31 | catchMemoryTranslationMiss = false, 32 | asyncTagMemory = false, 33 | twoCycleRam = true, 34 | twoCycleCache = true 35 | ) 36 | ), 37 | new DBusSimplePlugin( 38 | catchAddressMisaligned = false, 39 | catchAccessFault = false 40 | ), 41 | new StaticMemoryTranslatorPlugin( 42 | ioRange = _(31 downto 28) === 0xF 43 | ), 44 | new DecoderSimplePlugin( 45 | catchIllegalInstruction = true 46 | ), 47 | new RegFilePlugin( 48 | regFileReadyKind = plugin.SYNC, 49 | zeroBoot = true 50 | ), 51 | new IntAluPlugin, 52 | new SrcPlugin( 53 | separatedAddSub = false, 54 | executeInsertion = true 55 | ), 56 | new FullBarrelShifterPlugin(earlyInjection = true), 57 | new HazardSimplePlugin( 58 | bypassExecute = true, 59 | bypassMemory = true, 60 | bypassWriteBack = true, 61 | bypassWriteBackBuffer = true, 62 | pessimisticUseSrc = false, 63 | pessimisticWriteRegFile = false, 64 | pessimisticAddressMatch = false 65 | ), 66 | new CsrPlugin(CsrPluginConfig.small(0x80000000l)), 67 | new BranchPlugin( 68 | earlyBranch = true, 69 | catchAddressMisaligned = true 70 | ), 71 | new YamlPlugin("cpu0.yaml") 72 | ) 73 | ) 74 | ) 75 | 76 | SpinalVerilog(cpu()) 77 | } 78 | -------------------------------------------------------------------------------- /cl_chronos/riscv_code/sssp/main.c: -------------------------------------------------------------------------------- 1 | /** $lic$ 2 | * Copyright (C) 2014-2019 by Massachusetts Institute of Technology 3 | * 4 | * This file is part of the Chronos FPGA Acceleration Framework. 5 | * 6 | * Chronos is free software; you can redistribute it and/or modify it under the 7 | * terms of the GNU General Public License as published by the Free Software 8 | * Foundation, version 2. 9 | * 10 | * If you use this framework in your research, we request that you reference 11 | * the Chronos paper ("Chronos: Efficient Speculative Parallelism for 12 | * Accelerators", Abeydeera and Sanchez, ASPLOS-25, March 2020), and that 13 | * you send us a citation of your work. 14 | * 15 | * Chronos is distributed in the hope that it will be useful, but WITHOUT ANY 16 | * WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS 17 | * FOR A PARTICULAR PURPOSE. See the GNU General Public License for more 18 | * details. 19 | * 20 | * You should have received a copy of the GNU General Public License along with 21 | * this program. If not, see . 22 | */ 23 | 24 | 25 | #include "../include/chronos.h" 26 | 27 | // The location pointing to the base of each of the arrays 28 | const int ADDR_BASE_DIST = 5 << 2; 29 | const int ADDR_BASE_EDGE_OFFSET = 3 << 2; 30 | const int ADDR_BASE_NEIGHBORS = 4 << 2; 31 | 32 | uint32_t* dist; 33 | uint32_t* edge_offset; 34 | uint32_t* edge_neighbors; 35 | 36 | #define VISIT_NODE_TASK 0 37 | 38 | void visit_node_task(uint ts, uint vid) { 39 | 40 | unsigned int cur_dist = (unsigned int) dist[vid]; 41 | if (cur_dist <= ts) { 42 | return; 43 | } 44 | 45 | undo_log_write(&(dist[vid]), cur_dist); 46 | dist[vid] = ts; 47 | for (int i = edge_offset[vid]; i < edge_offset[vid+1]; i++) { 48 | int neighbor = edge_neighbors[i*2]; 49 | int weight = edge_neighbors[i*2+1]; 50 | 51 | enq_task_arg0(VISIT_NODE_TASK, ts + weight, neighbor); 52 | } 53 | } 54 | 55 | 56 | int main() { 57 | chronos_init(); 58 | 59 | // Dereference the pointers to array base addresses. 60 | // ( The '<<2' is because graph_gen writes the word number, not the byte) 61 | dist = (uint32_t*) ((*(uint32_t *) (ADDR_BASE_DIST))<<2) ; 62 | edge_offset =(uint32_t*) ((*(int *)(ADDR_BASE_EDGE_OFFSET))<<2) ; 63 | edge_neighbors =(uint32_t*) ((*(int *)(ADDR_BASE_NEIGHBORS))<<2) ; 64 | 65 | while (1) { 66 | uint ttype, ts, object; 67 | deq_task_arg0(&ttype, &ts, &object); 68 | switch(ttype){ 69 | case VISIT_NODE_TASK: 70 | visit_node_task(ts, object); 71 | break; 72 | default: 73 | break; 74 | } 75 | 76 | finish_task(); 77 | } 78 | } 79 | 80 | -------------------------------------------------------------------------------- /cl_chronos/build/scripts/encrypt.tcl: -------------------------------------------------------------------------------- 1 | # Amazon FPGA Hardware Development Kit 2 | # 3 | # Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. 4 | # 5 | # Licensed under the Amazon Software License (the "License"). You may not use 6 | # this file except in compliance with the License. A copy of the License is 7 | # located at 8 | # 9 | # http://aws.amazon.com/asl/ 10 | # 11 | # or in the "license" file accompanying this file. This file is distributed on 12 | # an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or 13 | # implied. See the License for the specific language governing permissions and 14 | # limitations under the License. 15 | 16 | # TODO: 17 | # Add check if CL_DIR and HDK_SHELL_DIR directories exist 18 | # Add check if /build and /build/src_port_encryption directories exist 19 | # Add check if the vivado_keyfile exist 20 | 21 | set HDK_SHELL_DIR $::env(HDK_SHELL_DIR) 22 | set HDK_SHELL_DESIGN_DIR $::env(HDK_SHELL_DESIGN_DIR) 23 | set CL_DIR $::env(CL_DIR) 24 | set TARGET_DIR $CL_DIR/build/src_post_encryption 25 | set UNUSED_TEMPLATES_DIR $HDK_SHELL_DESIGN_DIR/interfaces 26 | 27 | # Remove any previously encrypted files, that may no longer be used 28 | exec rm -f $TARGET_DIR/* 29 | 30 | #---- Developr would replace this section with design files ---- 31 | 32 | ## Change file names and paths below to reflect your CL area. DO NOT include AWS RTL files. 33 | 34 | ## grab all files in design folder 35 | file copy -force {*}[glob -nocomplain -- $CL_DIR/design/*.{v,sv,vh}] $TARGET_DIR 36 | 37 | file copy -force $UNUSED_TEMPLATES_DIR/unused_apppf_irq_template.inc $TARGET_DIR 38 | file copy -force $UNUSED_TEMPLATES_DIR/unused_cl_sda_template.inc $TARGET_DIR 39 | file copy -force $UNUSED_TEMPLATES_DIR/unused_ddr_a_b_d_template.inc $TARGET_DIR 40 | file copy -force $UNUSED_TEMPLATES_DIR/unused_ddr_c_template.inc $TARGET_DIR 41 | file copy -force $UNUSED_TEMPLATES_DIR/unused_dma_pcis_template.inc $TARGET_DIR 42 | file copy -force $UNUSED_TEMPLATES_DIR/unused_pcim_template.inc $TARGET_DIR 43 | file copy -force $UNUSED_TEMPLATES_DIR/unused_sh_bar1_template.inc $TARGET_DIR 44 | file copy -force $UNUSED_TEMPLATES_DIR/unused_flr_template.inc $TARGET_DIR 45 | 46 | #---- End of section replaced by Developr --- 47 | 48 | # Make sure files have write permissions for the encryption 49 | exec chmod +w {*}[glob $TARGET_DIR/*] 50 | 51 | # encrypt .v/.sv/.vh/inc as verilog files 52 | encrypt -k $HDK_SHELL_DIR/build/scripts/vivado_keyfile.txt -lang verilog [glob -nocomplain -- $TARGET_DIR/*.{v,sv}] [glob -nocomplain -- $TARGET_DIR/*.vh] [glob -nocomplain -- $TARGET_DIR/*.inc] 53 | 54 | # encrypt *vhdl files 55 | encrypt -k $HDK_SHELL_DIR/build/scripts/vivado_vhdl_keyfile.txt -lang vhdl -quiet [ glob -nocomplain -- $TARGET_DIR/*.vhd? ] 56 | 57 | 58 | -------------------------------------------------------------------------------- /cl_chronos/design/apps/astar/sinf_or_cosf_32_3dEe_rom.dat: -------------------------------------------------------------------------------- 1 | 5887 2 | 5888 3 | 5887 4 | 5888 5 | 588B 6 | 588B 7 | 588E 8 | 588F 9 | 5896 10 | 5899 11 | 589C 12 | 589F 13 | 58A3 14 | 58A8 15 | 58AE 16 | 58B4 17 | 58B9 18 | 58BE 19 | 58C8 20 | 58CE 21 | 58D6 22 | 58DF 23 | 58E6 24 | 58EE 25 | 58F8 26 | 5902 27 | 590C 28 | 5915 29 | 5921 30 | 592C 31 | 5937 32 | 5942 33 | 594D 34 | 595C 35 | 5967 36 | 5973 37 | 5983 38 | 598F 39 | 59A0 40 | 59AB 41 | 59BD 42 | 59CC 43 | 59DB 44 | 59EC 45 | 59FE 46 | 5A0E 47 | 5A1F 48 | 5A31 49 | 5A42 50 | 5A53 51 | 5A65 52 | 5A7B 53 | 5A8B 54 | 5AA2 55 | 5AB4 56 | 5ACC 57 | 5ADE 58 | 5AF3 59 | 5B0A 60 | 5B21 61 | 5B36 62 | 5B4B 63 | 5B62 64 | 5B7C 65 | 5B90 66 | 5BAC 67 | 5BC4 68 | 5BDB 69 | 5BF7 70 | 5C0E 71 | 5C2B 72 | 5C43 73 | 5C5E 74 | 5C79 75 | 5C92 76 | 5CAF 77 | 5CCA 78 | 5CE5 79 | 5D04 80 | 5D1F 81 | 5D3D 82 | 5D5B 83 | 5D7A 84 | 5D98 85 | 5DB6 86 | 5DD5 87 | 5DF5 88 | 5E15 89 | 5E32 90 | 5E55 91 | 5E74 92 | 5E95 93 | 5EB5 94 | 5ED9 95 | 5EF9 96 | 5F1B 97 | 5F3C 98 | 5F62 99 | 5F84 100 | 5FA6 101 | 5FCB 102 | 5FEF 103 | 6016 104 | 6038 105 | 605B 106 | 6081 107 | 60A7 108 | 60CD 109 | 60F3 110 | 6118 111 | 6141 112 | 6168 113 | 618E 114 | 61B7 115 | 61DD 116 | 6207 117 | 622E 118 | 6258 119 | 6281 120 | 62AA 121 | 62D5 122 | 6300 123 | 6327 124 | 6351 125 | 637E 126 | 63AC 127 | 63D2 128 | 63FF 129 | 75A8 130 | 75A9 131 | 75AB 132 | 75AC 133 | 75AD 134 | 75AB 135 | 75AE 136 | 75AD 137 | 75AD 138 | 75AE 139 | 75AD 140 | 75AD 141 | 75AF 142 | 75B0 143 | 75B0 144 | 75B1 145 | 75B2 146 | 75B2 147 | 75B2 148 | 75B3 149 | 75B5 150 | 75B7 151 | 75BA 152 | 75BA 153 | 75BC 154 | 75BF 155 | 75C0 156 | 75C0 157 | 75C2 158 | 75C4 159 | 75C4 160 | 75C6 161 | 75C8 162 | 75CC 163 | 75CE 164 | 75CF 165 | 75D1 166 | 75D5 167 | 75D8 168 | 75DB 169 | 75DD 170 | 75DF 171 | 75E2 172 | 75E3 173 | 75E5 174 | 75E9 175 | 75EB 176 | 75ED 177 | 75EF 178 | 75F1 179 | 75F6 180 | 75F9 181 | 75FB 182 | 75FF 183 | 7604 184 | 7606 185 | 7607 186 | 760A 187 | 7612 188 | 7614 189 | 7615 190 | 761C 191 | 761E 192 | 7622 193 | 7626 194 | 7628 195 | 762C 196 | 7630 197 | 7636 198 | 7639 199 | 763D 200 | 7641 201 | 7643 202 | 764C 203 | 764E 204 | 7650 205 | 7654 206 | 765E 207 | 7662 208 | 7667 209 | 766A 210 | 766D 211 | 7671 212 | 767A 213 | 767E 214 | 7680 215 | 7685 216 | 768C 217 | 7690 218 | 7698 219 | 769A 220 | 76A0 221 | 76A4 222 | 76AB 223 | 76B1 224 | 76B7 225 | 76BB 226 | 76C1 227 | 76C6 228 | 76CA 229 | 76D2 230 | 76D6 231 | 76DE 232 | 76E3 233 | 76E8 234 | 76ED 235 | 76F6 236 | 76FC 237 | 7703 238 | 7707 239 | 770E 240 | 7713 241 | 7719 242 | 771F 243 | 7726 244 | 772C 245 | 7732 246 | 773D 247 | 7743 248 | 7749 249 | 774D 250 | 7755 251 | 775C 252 | 7762 253 | 776A 254 | 776F 255 | 7778 256 | 777E 257 | 258 | -------------------------------------------------------------------------------- /cl_chronos/software/verif_rtl/include/sh_dpi_tasks.h: -------------------------------------------------------------------------------- 1 | /** $lic$ 2 | * Copyright (C) 2014-2019 by Massachusetts Institute of Technology 3 | * 4 | * This file is part of the Chronos FPGA Acceleration Framework. 5 | * 6 | * Chronos is free software; you can redistribute it and/or modify it under the 7 | * terms of the GNU General Public License as published by the Free Software 8 | * Foundation, version 2. 9 | * 10 | * If you use this framework in your research, we request that you reference 11 | * the Chronos paper ("Chronos: Efficient Speculative Parallelism for 12 | * Accelerators", Abeydeera and Sanchez, ASPLOS-25, March 2020), and that 13 | * you send us a citation of your work. 14 | * 15 | * Chronos is distributed in the hope that it will be useful, but WITHOUT ANY 16 | * WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS 17 | * FOR A PARTICULAR PURPOSE. See the GNU General Public License for more 18 | * details. 19 | * 20 | * You should have received a copy of the GNU General Public License along with 21 | * this program. If not, see . 22 | */ 23 | 24 | // Amazon FPGA Hardware Development Kit 25 | // 26 | // Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. 27 | // 28 | // Licensed under the Amazon Software License (the "License"). You may not use 29 | // this file except in compliance with the License. A copy of the License is 30 | // located at 31 | // 32 | // http://aws.amazon.com/asl/ 33 | // 34 | // or in the "license" file accompanying this file. This file is distributed on 35 | // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or 36 | // implied. See the License for the specific language governing permissions and 37 | // limitations under the License. 38 | 39 | #ifndef SH_DPI_TASKS 40 | #define SH_DPI_TASKS 41 | 42 | #include 43 | 44 | extern void sv_printf(char *msg); 45 | extern void sv_map_host_memory(uint8_t *memory); 46 | 47 | extern void cl_peek(uint64_t addr, uint32_t *data); 48 | extern void cl_poke(uint64_t addr, uint32_t data); 49 | extern void sv_pause(uint32_t x); 50 | 51 | void test_main(uint32_t *exit_code); 52 | 53 | void host_memory_putc(uint64_t addr, uint8_t data) 54 | { 55 | *(uint8_t *)addr = data; 56 | } 57 | 58 | //void host_memory_getc(uint64_t addr, uint8_t *data) 59 | uint8_t host_memory_getc(uint64_t addr) 60 | { 61 | return *(uint8_t *)addr; 62 | } 63 | 64 | void log_printf(const char *format, ...) 65 | { 66 | static char sv_msg_buffer[256]; 67 | va_list args; 68 | 69 | va_start(args, format); 70 | vsprintf(sv_msg_buffer, format, args); 71 | sv_printf(sv_msg_buffer); 72 | 73 | va_end(args); 74 | } 75 | 76 | #define LOW_32b(a) ((uint32_t)((uint64_t)(a) & 0xffffffff)) 77 | #define HIGH_32b(a) ((uint32_t)(((uint64_t)(a)) >> 32L)) 78 | 79 | #endif 80 | -------------------------------------------------------------------------------- /cl_chronos/validation/scripts/build_scripts/scripts/encrypt.tcl: -------------------------------------------------------------------------------- 1 | # Amazon FPGA Hardware Development Kit 2 | # 3 | # Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. 4 | # 5 | # Licensed under the Amazon Software License (the "License"). You may not use 6 | # this file except in compliance with the License. A copy of the License is 7 | # located at 8 | # 9 | # http://aws.amazon.com/asl/ 10 | # 11 | # or in the "license" file accompanying this file. This file is distributed on 12 | # an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or 13 | # implied. See the License for the specific language governing permissions and 14 | # limitations under the License. 15 | 16 | # TODO: 17 | # Add check if CL_DIR and HDK_SHELL_DIR directories exist 18 | # Add check if /build and /build/src_port_encryption directories exist 19 | # Add check if the vivado_keyfile exist 20 | 21 | set HDK_SHELL_DIR $::env(HDK_SHELL_DIR) 22 | set HDK_SHELL_DESIGN_DIR $::env(HDK_SHELL_DESIGN_DIR) 23 | set CL_DIR $::env(CL_DIR) 24 | set TARGET_DIR $CL_DIR/build/src_post_encryption 25 | set UNUSED_TEMPLATES_DIR $HDK_SHELL_DESIGN_DIR/interfaces 26 | 27 | # Remove any previously encrypted files, that may no longer be used 28 | exec rm -f $TARGET_DIR/* 29 | 30 | #---- Developr would replace this section with design files ---- 31 | 32 | ## Change file names and paths below to reflect your CL area. DO NOT include AWS RTL files. 33 | 34 | ## grab all files in design folder 35 | file copy -force {*}[glob -nocomplain -- $CL_DIR/design/*.{v,sv,vh}] $TARGET_DIR 36 | 37 | file copy -force $UNUSED_TEMPLATES_DIR/unused_apppf_irq_template.inc $TARGET_DIR 38 | file copy -force $UNUSED_TEMPLATES_DIR/unused_cl_sda_template.inc $TARGET_DIR 39 | file copy -force $UNUSED_TEMPLATES_DIR/unused_ddr_a_b_d_template.inc $TARGET_DIR 40 | file copy -force $UNUSED_TEMPLATES_DIR/unused_ddr_c_template.inc $TARGET_DIR 41 | file copy -force $UNUSED_TEMPLATES_DIR/unused_dma_pcis_template.inc $TARGET_DIR 42 | file copy -force $UNUSED_TEMPLATES_DIR/unused_pcim_template.inc $TARGET_DIR 43 | file copy -force $UNUSED_TEMPLATES_DIR/unused_sh_bar1_template.inc $TARGET_DIR 44 | file copy -force $UNUSED_TEMPLATES_DIR/unused_flr_template.inc $TARGET_DIR 45 | 46 | #---- End of section replaced by Developr --- 47 | 48 | # Make sure files have write permissions for the encryption 49 | exec chmod +w {*}[glob $TARGET_DIR/*] 50 | 51 | # encrypt .v/.sv/.vh/inc as verilog files 52 | encrypt -k $HDK_SHELL_DIR/build/scripts/vivado_keyfile.txt -lang verilog [glob -nocomplain -- $TARGET_DIR/*.{v,sv}] [glob -nocomplain -- $TARGET_DIR/*.vh] [glob -nocomplain -- $TARGET_DIR/*.inc] 53 | 54 | # encrypt *vhdl files 55 | encrypt -k $HDK_SHELL_DIR/build/scripts/vivado_vhdl_keyfile.txt -lang vhdl -quiet [ glob -nocomplain -- $TARGET_DIR/*.vhd? ] 56 | 57 | 58 | -------------------------------------------------------------------------------- /cl_chronos/verif/scripts/top.questa.f: -------------------------------------------------------------------------------- 1 | # Amazon FPGA Hardware Development Kit 2 | # 3 | # Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. 4 | # 5 | # Licensed under the Amazon Software License (the "License"). You may not use 6 | # this file except in compliance with the License. A copy of the License is 7 | # located at 8 | # 9 | # http://aws.amazon.com/asl/ 10 | # 11 | # or in the "license" file accompanying this file. This file is distributed on 12 | # an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or 13 | # implied. See the License for the specific language governing permissions and 14 | # limitations under the License. 15 | 16 | +define+QUESTA_SIM 17 | +define+CARD_1=card 18 | +libext+.v 19 | +libext+.sv 20 | +libext+.svh 21 | 22 | -y ${CL_ROOT}/../common/design 23 | -y ${CL_ROOT}/design 24 | -y ${CL_ROOT}/verif/sv 25 | -y ${SH_LIB_DIR} 26 | -y ${SH_INF_DIR} 27 | -y ${SH_SH_DIR} 28 | -y ${HDK_SHELL_DESIGN_DIR}/ip/cl_debug_bridge/bd_0/hdl 29 | -y ${HDK_SHELL_DESIGN_DIR}/ip/cl_debug_bridge/sim 30 | 31 | +incdir+${CL_ROOT}/../common/design 32 | +incdir+${CL_ROOT}/design 33 | +incdir+${CL_ROOT}/verif/sv 34 | +incdir+${SH_LIB_DIR} 35 | +incdir+${SH_INF_DIR} 36 | +incdir+${SH_SH_DIR} 37 | +incdir+${HDK_COMMON_DIR}/verif/include 38 | +incdir+${HDK_SHELL_DESIGN_DIR}/ip/cl_debug_bridge/bd_0/ip/ip_0/hdl/verilog 39 | +incdir+${HDK_SHELL_DESIGN_DIR}/ip/axi_register_slice_light/hdl 40 | 41 | ${CL_ROOT}/../common/design/cl_common_defines.vh 42 | ${CL_ROOT}/design/cl_chronos_defines.vh 43 | ${HDK_SHELL_DESIGN_DIR}/ip/ila_vio_counter/sim/ila_vio_counter.v 44 | ${HDK_SHELL_DESIGN_DIR}/ip/ila_0/sim/ila_0.v 45 | ${HDK_SHELL_DESIGN_DIR}/ip/cl_debug_bridge/bd_0/hdl/bd_a493.v 46 | ${HDK_SHELL_DESIGN_DIR}/ip/cl_debug_bridge/bd_0/ip/ip_0/sim/bd_a493_xsdbm_0.v 47 | ${HDK_SHELL_DESIGN_DIR}/ip/cl_debug_bridge/bd_0/ip/ip_0/hdl/xsdbm_v3_0_vl_rfs.v 48 | ${HDK_SHELL_DESIGN_DIR}/ip/cl_debug_bridge/bd_0/ip/ip_0/hdl/ltlib_v1_0_vl_rfs.v 49 | ${HDK_SHELL_DESIGN_DIR}/ip/cl_debug_bridge/bd_0/ip/ip_1/sim/bd_a493_lut_buffer_0.v 50 | ${HDK_SHELL_DESIGN_DIR}/ip/cl_debug_bridge/bd_0/ip/ip_1/hdl/lut_buffer_v2_0_vl_rfs.v 51 | ${HDK_SHELL_DESIGN_DIR}/ip/cl_debug_bridge/bd_0/hdl/bd_a493_wrapper.v 52 | ${HDK_SHELL_DESIGN_DIR}/ip/cl_debug_bridge/sim/cl_debug_bridge.v 53 | ${HDK_SHELL_DESIGN_DIR}/ip/vio_0/sim/vio_0.v 54 | ${HDK_SHELL_DESIGN_DIR}/ip/axi_register_slice_light/sim/axi_register_slice_light.v 55 | ${HDK_SHELL_DESIGN_DIR}/ip/axi_register_slice_light/hdl/axi_register_slice_v2_1_vl_rfs.v 56 | ${HDK_SHELL_DESIGN_DIR}/ip/axi_register_slice_light/hdl/axi_infrastructure_v1_1_vl_rfs.v 57 | ${HDK_SHELL_DESIGN_DIR}/ip/axi_register_slice/sim/axi_register_slice.v 58 | ${HDK_SHELL_DESIGN_DIR}/ip/axi_clock_converter_0/sim/axi_clock_converter_0.v 59 | 60 | ${CL_ROOT}/design/cl_chronos.sv 61 | 62 | -f ${HDK_COMMON_DIR}/verif/tb/filelists/tb.${SIMULATOR}.f 63 | 64 | ${TEST_NAME} 65 | -------------------------------------------------------------------------------- /cl_chronos/verif/scripts/top.vcs.f: -------------------------------------------------------------------------------- 1 | # Amazon FPGA Hardware Development Kit 2 | # 3 | # Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. 4 | # 5 | # Licensed under the Amazon Software License (the "License"). You may not use 6 | # this file except in compliance with the License. A copy of the License is 7 | # located at 8 | # 9 | # http://aws.amazon.com/asl/ 10 | # 11 | # or in the "license" file accompanying this file. This file is distributed on 12 | # an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or 13 | # implied. See the License for the specific language governing permissions and 14 | # limitations under the License. 15 | 16 | +define+VCS_SIM 17 | +define+CARD_1=card 18 | +libext+.v 19 | +libext+.sv 20 | +libext+.svh 21 | 22 | -y ${CL_ROOT}/../common/design 23 | -y ${CL_ROOT}/design 24 | -y ${CL_ROOT}/verif/sv 25 | -y ${SH_LIB_DIR} 26 | -y ${SH_INF_DIR} 27 | -y ${SH_SH_DIR} 28 | -y ${HDK_SHELL_DESIGN_DIR}/ip/cl_debug_bridge/bd_0/hdl 29 | -y ${HDK_SHELL_DESIGN_DIR}/ip/cl_debug_bridge/sim 30 | 31 | +incdir+${CL_ROOT}/../common/design 32 | +incdir+${CL_ROOT}/design 33 | +incdir+${CL_ROOT}/verif/sv 34 | +incdir+${SH_LIB_DIR} 35 | +incdir+${SH_INF_DIR} 36 | +incdir+${SH_SH_DIR} 37 | +incdir+${HDK_COMMON_DIR}/verif/include 38 | +incdir+${HDK_SHELL_DESIGN_DIR}/ip/cl_debug_bridge/bd_0/ip/ip_0/hdl/verilog 39 | +incdir+${HDK_SHELL_DESIGN_DIR}/ip/axi_register_slice_light/hdl 40 | 41 | ${CL_ROOT}/../common/design/cl_common_defines.vh 42 | ${CL_ROOT}/design/cl_hello_world_defines.vh 43 | ${HDK_SHELL_DESIGN_DIR}/ip/ila_vio_counter/sim/ila_vio_counter.v 44 | ${HDK_SHELL_DESIGN_DIR}/ip/ila_0/sim/ila_0.v 45 | ${HDK_SHELL_DESIGN_DIR}/ip/cl_debug_bridge/bd_0/hdl/bd_a493.v 46 | ${HDK_SHELL_DESIGN_DIR}/ip/cl_debug_bridge/bd_0/ip/ip_0/sim/bd_a493_xsdbm_0.v 47 | ${HDK_SHELL_DESIGN_DIR}/ip/cl_debug_bridge/bd_0/ip/ip_0/hdl/xsdbm_v3_0_vl_rfs.v 48 | ${HDK_SHELL_DESIGN_DIR}/ip/cl_debug_bridge/bd_0/ip/ip_0/hdl/ltlib_v1_0_vl_rfs.v 49 | ${HDK_SHELL_DESIGN_DIR}/ip/cl_debug_bridge/bd_0/ip/ip_1/sim/bd_a493_lut_buffer_0.v 50 | ${HDK_SHELL_DESIGN_DIR}/ip/cl_debug_bridge/bd_0/ip/ip_1/hdl/lut_buffer_v2_0_vl_rfs.v 51 | ${HDK_SHELL_DESIGN_DIR}/ip/cl_debug_bridge/bd_0/hdl/bd_a493_wrapper.v 52 | ${HDK_SHELL_DESIGN_DIR}/ip/cl_debug_bridge/sim/cl_debug_bridge.v 53 | ${HDK_SHELL_DESIGN_DIR}/ip/vio_0/sim/vio_0.v 54 | ${HDK_SHELL_DESIGN_DIR}/ip/axi_register_slice_light/sim/axi_register_slice_light.v 55 | ${HDK_SHELL_DESIGN_DIR}/ip/axi_register_slice_light/hdl/axi_register_slice_v2_1_vl_rfs.v 56 | ${HDK_SHELL_DESIGN_DIR}/ip/axi_register_slice_light/hdl/axi_infrastructure_v1_1_vl_rfs.v 57 | ${HDK_SHELL_DESIGN_DIR}/ip/axi_register_slice/sim/axi_register_slice.v 58 | ${HDK_SHELL_DESIGN_DIR}/ip/axi_clock_converter_0/sim/axi_clock_converter_0.v 59 | 60 | ${CL_ROOT}/design/cl_hello_world.sv 61 | 62 | -f ${HDK_COMMON_DIR}/verif/tb/filelists/tb.${SIMULATOR}.f 63 | 64 | ${TEST_NAME} 65 | -------------------------------------------------------------------------------- /cl_chronos/software/verif_rtl/src/test_swarm.c: -------------------------------------------------------------------------------- 1 | /** $lic$ 2 | * Copyright (C) 2014-2019 by Massachusetts Institute of Technology 3 | * 4 | * This file is part of the Chronos FPGA Acceleration Framework. 5 | * 6 | * Chronos is free software; you can redistribute it and/or modify it under the 7 | * terms of the GNU General Public License as published by the Free Software 8 | * Foundation, version 2. 9 | * 10 | * If you use this framework in your research, we request that you reference 11 | * the Chronos paper ("Chronos: Efficient Speculative Parallelism for 12 | * Accelerators", Abeydeera and Sanchez, ASPLOS-25, March 2020), and that 13 | * you send us a citation of your work. 14 | * 15 | * Chronos is distributed in the hope that it will be useful, but WITHOUT ANY 16 | * WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS 17 | * FOR A PARTICULAR PURPOSE. See the GNU General Public License for more 18 | * details. 19 | * 20 | * You should have received a copy of the GNU General Public License along with 21 | * this program. If not, see . 22 | */ 23 | 24 | // Amazon FPGA Hardware Development Kit 25 | // 26 | // Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. 27 | // 28 | // Licensed under the Amazon Software License (the "License"). You may not use 29 | // this file except in compliance with the License. A copy of the License is 30 | // located at 31 | // 32 | // http://aws.amazon.com/asl/ 33 | // 34 | // or in the "license" file accompanying this file. This file is distributed on 35 | // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or 36 | // implied. See the License for the specific language governing permissions and 37 | // limitations under the License. 38 | 39 | #include 40 | #include 41 | #include 42 | 43 | // Vivado does not support svGetScopeFromName 44 | //#ifdef INCLUDE_DPI_CALLS 45 | #ifndef VIVADO_SIM 46 | #include "svdpi.h" 47 | #endif 48 | //#endif 49 | 50 | #include "sh_dpi_tasks.h" 51 | 52 | #define HELLO_WORLD_REG_ADDR UINT64_C(0x500) 53 | 54 | void test_main(uint32_t *exit_code) { 55 | 56 | // Vivado does not support svGetScopeFromName 57 | //#ifdef INCLUDE_DPI_CALLS 58 | #ifndef VIVADO_SIM 59 | svScope scope; 60 | #endif 61 | //#endif 62 | 63 | uint32_t rdata; 64 | 65 | // Vivado does not support svGetScopeFromName 66 | //#ifdef INCLUDE_DPI_CALLS 67 | #ifndef VIVADO_SIM 68 | scope = svGetScopeFromName("tb"); 69 | svSetScope(scope); 70 | #endif 71 | //#endif 72 | 73 | log_printf("Writing 0xDEAD_BEEF to address 0x%x", HELLO_WORLD_REG_ADDR); 74 | cl_poke(HELLO_WORLD_REG_ADDR, 0xDEADBEEF); 75 | cl_peek(HELLO_WORLD_REG_ADDR, &rdata); 76 | 77 | log_printf("Reading 0x%x from address 0x%x", rdata, HELLO_WORLD_REG_ADDR); 78 | 79 | if (rdata == 0xEFBEADDE) { 80 | log_printf("Test PASSED"); 81 | } else { 82 | log_printf("Test FAILED"); 83 | } 84 | 85 | *exit_code = 0; 86 | } 87 | -------------------------------------------------------------------------------- /cl_chronos/design/derived.vh: -------------------------------------------------------------------------------- 1 | /** $lic$ 2 | * Copyright (C) 2014-2019 by Massachusetts Institute of Technology 3 | * 4 | * This file is part of the Chronos FPGA Acceleration Framework. 5 | * 6 | * Chronos is free software; you can redistribute it and/or modify it under the 7 | * terms of the GNU General Public License as published by the Free Software 8 | * Foundation, version 2. 9 | * 10 | * If you use this framework in your research, we request that you reference 11 | * the Chronos paper ("Chronos: Efficient Speculative Parallelism for 12 | * Accelerators", Abeydeera and Sanchez, ASPLOS-25, March 2020), and that 13 | * you send us a citation of your work. 14 | * 15 | * Chronos is distributed in the hope that it will be useful, but WITHOUT ANY 16 | * WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS 17 | * FOR A PARTICULAR PURPOSE. See the GNU General Public License for more 18 | * details. 19 | * 20 | * You should have received a copy of the GNU General Public License along with 21 | * this program. If not, see . 22 | */ 23 | 24 | 25 | // Derived parameters. 26 | // ---------------------------------------------------------------------------------// 27 | parameter CACHE_TAG_WIDTH = ADDR_BITS - CACHE_BYTE_WIDTH - CACHE_INDEX_WIDTH; //18 28 | 29 | parameter LOG_CQ_TS_BANKS = LOG_CQ_SLICE_SIZE - LOG_GVT_PERIOD; 30 | 31 | parameter L2_BANKS = (1<. 22 | */ 23 | 24 | 25 | package des; 26 | typedef enum logic [2:0] { BUF, INV, NAND2, NOR2, AND2, OR2, XOR2, XNOR2 } gate_t; 27 | typedef enum logic [1:0] { LOGIC_0 =0, LOGIC_1=1, LOGIC_X=2, LOGIC_Z=3 } logic_val_t; 28 | endpackage 29 | 30 | import des::*; 31 | 32 | module logic_eval ( 33 | input logic_val_t p0, 34 | input logic_val_t p1, 35 | gate_t gate, 36 | 37 | output logic_val_t o 38 | 39 | ); 40 | 41 | always_comb begin 42 | case (gate) 43 | BUF: o = p0; 44 | INV: begin 45 | if (p0 == LOGIC_0) o = LOGIC_1; 46 | else if (p0 == LOGIC_1) o= LOGIC_0; 47 | else o = p0; 48 | end 49 | NAND2: begin 50 | if ((p0 == LOGIC_1) & (p1 == LOGIC_1)) o = LOGIC_0; 51 | else if (( p0 == LOGIC_0) | (p1 == LOGIC_0)) o = LOGIC_1; 52 | else o = LOGIC_X; 53 | end 54 | NOR2: begin 55 | if ((p0 == LOGIC_1) | (p1 == LOGIC_1)) o = LOGIC_0; 56 | else if (( p0 == LOGIC_0) & (p1 == LOGIC_0)) o = LOGIC_1; 57 | else o = LOGIC_X; 58 | end 59 | AND2: begin 60 | if ((p0 == LOGIC_1) & (p1 == LOGIC_1)) o = LOGIC_1; 61 | else if (( p0 == LOGIC_0) | (p1 == LOGIC_0)) o = LOGIC_0; 62 | else o = LOGIC_X; 63 | end 64 | OR2: begin 65 | if ((p0 == LOGIC_1) | (p1 == LOGIC_1)) o = LOGIC_1; 66 | else if (( p0 == LOGIC_0) & (p1 == LOGIC_0)) o = LOGIC_0; 67 | else o = LOGIC_X; 68 | end 69 | XOR2: begin 70 | if ((p0 == LOGIC_1) & (p1 == LOGIC_1)) o = LOGIC_0; 71 | else if (( p0 == LOGIC_1) & (p1 == LOGIC_0)) o = LOGIC_1; 72 | else if (( p0 == LOGIC_0) & (p1 == LOGIC_1)) o = LOGIC_1; 73 | else if (( p0 == LOGIC_0) & (p1 == LOGIC_0)) o = LOGIC_0; 74 | else o = LOGIC_X; 75 | end 76 | XNOR2: begin 77 | if ((p0 == LOGIC_1) & (p1 == LOGIC_1)) o = LOGIC_1; 78 | else if (( p0 == LOGIC_1) & (p1 == LOGIC_0)) o = LOGIC_0; 79 | else if (( p0 == LOGIC_0) & (p1 == LOGIC_1)) o = LOGIC_0; 80 | else if (( p0 == LOGIC_0) & (p1 == LOGIC_0)) o = LOGIC_1; 81 | else o = LOGIC_X; 82 | end 83 | 84 | endcase 85 | 86 | end 87 | 88 | endmodule 89 | -------------------------------------------------------------------------------- /cl_chronos/design/apps/astar/sinf_or_cosf_32_3cud_rom.dat: -------------------------------------------------------------------------------- 1 | 7FFFFF 2 | 7FB109 3 | 7F6216 4 | 7F1325 5 | 7EC432 6 | 7E7547 7 | 7E265D 8 | 7DD779 9 | 7D8896 10 | 7D39BD 11 | 7CEAEB 12 | 7C9C21 13 | 7C4D5F 14 | 7BFEA6 15 | 7BAFF5 16 | 7B6150 17 | 7B12B7 18 | 7AC42B 19 | 7A75A7 20 | 7A2736 21 | 79D8D1 22 | 798A7B 23 | 793C36 24 | 78EE03 25 | 789FDF 26 | 7851CD 27 | 7803CF 28 | 77B5E5 29 | 77680E 30 | 771A4E 31 | 76CCA3 32 | 767F10 33 | 763194 34 | 75E42D 35 | 7596E4 36 | 7549B3 37 | 74FC99 38 | 74AF9F 39 | 7462BC 40 | 7415FC 41 | 73C953 42 | 737CCC 43 | 733063 44 | 72E418 45 | 7297EE 46 | 724BE7 47 | 720001 48 | 71B43D 49 | 71689D 50 | 711D22 51 | 70D1CB 52 | 708695 53 | 703B8D 54 | 6FF0A4 55 | 6FA5E9 56 | 6F5B50 57 | 6F10E7 58 | 6EC6A5 59 | 6E7C8C 60 | 6E329E 61 | 6DE8DE 62 | 6D9F4C 63 | 6D55E5 64 | 6D0CA9 65 | 6CC3A3 66 | 6C7AC5 67 | 6C321B 68 | 6BE9A3 69 | 6BA158 70 | 6B5945 71 | 6B115F 72 | 6AC9B2 73 | 6A8236 74 | 6A3AF1 75 | 69F3E3 76 | 69AD08 77 | 696667 78 | 691FFD 79 | 68D9C8 80 | 6893D1 81 | 684E10 82 | 68088B 83 | 67C340 84 | 677E32 85 | 673961 86 | 66F4CD 87 | 66B075 88 | 666C5D 89 | 662887 90 | 65E4EB 91 | 65A194 92 | 655E7C 93 | 651BA7 94 | 64D910 95 | 6496C2 96 | 6454B5 97 | 6412ED 98 | 63D166 99 | 639029 100 | 634F32 101 | 630E7E 102 | 62CE15 103 | 628DF0 104 | 624E1A 105 | 620E8B 106 | 61CF44 107 | 619048 108 | 615197 109 | 611332 110 | 60D51B 111 | 60974E 112 | 6059D0 113 | 601CA1 114 | 5FDFBD 115 | 5FA32D 116 | 5F66EA 117 | 5F2AF9 118 | 5EEF57 119 | 5EB407 120 | 5E790B 121 | 5E3E5F 122 | 5E0407 123 | 5DCA07 124 | 5D9058 125 | 5D56FD 126 | 5D1DF5 127 | 5CE54C 128 | 5CACF3 129 | 000002 130 | 7FEB56 131 | 7FD6A8 132 | 7FC1FC 133 | 7FAD50 134 | 7F98A7 135 | 7F83FB 136 | 7F6F53 137 | 7F5AAC 138 | 7F4603 139 | 7F315F 140 | 7F1CBA 141 | 7F0816 142 | 7EF372 143 | 7EDED3 144 | 7ECA33 145 | 7EB596 146 | 7EA0FB 147 | 7E8C63 148 | 7E77CC 149 | 7E6336 150 | 7E4EA3 151 | 7E3A11 152 | 7E2584 153 | 7E10FA 154 | 7DFC70 155 | 7DE7EB 156 | 7DD36B 157 | 7DBEED 158 | 7DAA70 159 | 7D95FB 160 | 7D8186 161 | 7D6D16 162 | 7D58A7 163 | 7D443E 164 | 7D2FDA 165 | 7D1B7A 166 | 7D071C 167 | 7CF2C3 168 | 7CDE6F 169 | 7CCA20 170 | 7CB5D7 171 | 7CA191 172 | 7C8D52 173 | 7C7918 174 | 7C64E1 175 | 7C50B0 176 | 7C3C87 177 | 7C2861 178 | 7C1443 179 | 7C0027 180 | 7BEC12 181 | 7BD805 182 | 7BC3FD 183 | 7BAFF9 184 | 7B9BFE 185 | 7B880C 186 | 7B741E 187 | 7B6032 188 | 7B4C52 189 | 7B387B 190 | 7B24A5 191 | 7B10DB 192 | 7AFD17 193 | 7AE959 194 | 7AD5A6 195 | 7AC1F8 196 | 7AAE52 197 | 7A9AB2 198 | 7A871C 199 | 7A738F 200 | 7A6008 201 | 7A4C8D 202 | 7A3913 203 | 7A25A8 204 | 7A1247 205 | 79FEEC 206 | 79EB94 207 | 79D84B 208 | 79C50A 209 | 79B1D4 210 | 799EA8 211 | 798B84 212 | 797865 213 | 796554 214 | 79524F 215 | 793F52 216 | 792C5C 217 | 791972 218 | 790690 219 | 78F3BD 220 | 78E0F1 221 | 78CE33 222 | 78BB7B 223 | 78A8CF 224 | 78962E 225 | 788399 226 | 78710F 227 | 785E8F 228 | 784C1D 229 | 7839B2 230 | 782755 231 | 781501 232 | 7802BC 233 | 77F082 234 | 77DE54 235 | 77CC2E 236 | 77BA18 237 | 77A80C 238 | 77960F 239 | 77841C 240 | 777239 241 | 77605F 242 | 774E94 243 | 773CD3 244 | 772B21 245 | 77197B 246 | 7707DE 247 | 76F653 248 | 76E4D5 249 | 76D366 250 | 76C201 251 | 76B0AC 252 | 769F63 253 | 768E27 254 | 767CFD 255 | 766BDC 256 | 765ACB 257 | 258 | -------------------------------------------------------------------------------- /cl_chronos/misc/inject_license.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/python 2 | 3 | import os, sys 4 | 5 | # Look for all files under the following tree and inject the license code 6 | 7 | exts = [".c", ".cpp", ".h", ".vh", ".sv"] # only C/C++ files for now 8 | licTextId = "$lic$" # license headers MUST have this text somewhere, and be a multi-line comment 9 | 10 | targetDir = sys.argv[1] 11 | 12 | srcs = [os.path.join(dir, file) for (dir, x, files) in os.walk(targetDir) for file in files if os.path.splitext(file)[1] in exts] 13 | srcs.sort() 14 | 15 | print "Will operate on " + str(len(srcs)) + " source files:" 16 | for src in srcs: print " " + src 17 | 18 | def askForPermission(): 19 | resp = raw_input("Continue (y/n)? ") 20 | if not resp == "y": 21 | print "Not continuing" 22 | sys.exit(0) 23 | 24 | askForPermission() 25 | 26 | # Open license header file, read its text 27 | licHdrFile = sys.argv[2] 28 | f = open(licHdrFile, 'r') 29 | licHdr = f.read() 30 | f.close() 31 | 32 | print "Will inject license header:" 33 | print licHdr 34 | 35 | if licHdr.find(licTextId) == -1: 36 | print "ERROR: License identifier text not found in provided header" 37 | sys.exit(-1) 38 | 39 | 40 | # Open each file for r/we, read its contents and produce modifications (but don't write them yet!) 41 | addedList = [] 42 | modifiedList = [] 43 | compliantList = [] 44 | 45 | for src in srcs: 46 | f = open(src, 'r+') # we open for read/write here to fail early on read-only files 47 | txt = f.read() 48 | f.close() 49 | if txt.find(licHdr) != -1: 50 | # This already has the current license header 51 | compliantList.append(src) 52 | elif txt.find(licTextId) == -1: 53 | # No license header, insert at the beginning 54 | addedList.append((src, licHdr + txt)) 55 | else: 56 | # NOTE: This detection algorithm is pretty basic, and could raise hell in corner cases 57 | licPos = txt.find(licTextId) 58 | 59 | # Check lic text is after a comment start, and before a comment end 60 | prevCommentOpen = txt.rfind("/*", 0, licPos) 61 | prevCommentClose = txt.rfind("*/", 0, licPos) 62 | if prevCommentOpen == -1 or prevCommentOpen < prevCommentClose: 63 | print "BOGUS " + licTextId + "detected on " + src + ", unmatched start, aborting" 64 | sys.exit(-1) 65 | 66 | nextCommentOpen = txt.find("/*", licPos) 67 | nextCommentClose = txt.find("*/", licPos) 68 | if nextCommentClose == -1 or (not nextCommentOpen == -1 and nextCommentClose > nextCommentOpen): 69 | print "BOGUS " + licTextId + "detected on " + src + ", unmatched end, aborting" 70 | sys.exit(-1) 71 | 72 | #print prevCommentOpen, nextCommentClose 73 | newTxt = txt[:prevCommentOpen] + txt[nextCommentClose+2:] # kill old license comment 74 | newTxt = licHdr + newTxt.lstrip() # prepend new license (not that this works if careless developers put code or comments before the license comment) 75 | #print newTxt 76 | 77 | modifiedList.append((src, newTxt)) 78 | 79 | print "Will add license to %d files, %d will be modified, %d are already compliant" % (len(addedList), len(modifiedList), len(compliantList)) 80 | 81 | askForPermission() 82 | 83 | for (src, txt) in addedList + modifiedList: 84 | f = open(src, 'w') 85 | f.write(txt) 86 | f.close() 87 | 88 | print "Done!" 89 | 90 | -------------------------------------------------------------------------------- /cl_chronos/design/apps/astar/astar_dist_mux_16jbC.v: -------------------------------------------------------------------------------- 1 | // ============================================================== 2 | // File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC 3 | // Version: 2017.1 4 | // Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved. 5 | // 6 | // ============================================================== 7 | 8 | 9 | `timescale 1ns/1ps 10 | 11 | module astar_dist_mux_16jbC #( 12 | parameter 13 | ID = 0, 14 | NUM_STAGE = 1, 15 | din1_WIDTH = 32, 16 | din2_WIDTH = 32, 17 | din3_WIDTH = 32, 18 | din4_WIDTH = 32, 19 | din5_WIDTH = 32, 20 | din6_WIDTH = 32, 21 | din7_WIDTH = 32, 22 | din8_WIDTH = 32, 23 | din9_WIDTH = 32, 24 | din10_WIDTH = 32, 25 | din11_WIDTH = 32, 26 | din12_WIDTH = 32, 27 | din13_WIDTH = 32, 28 | din14_WIDTH = 32, 29 | din15_WIDTH = 32, 30 | din16_WIDTH = 32, 31 | din17_WIDTH = 32, 32 | dout_WIDTH = 32 33 | )( 34 | input [0 : 0] din1, 35 | input [0 : 0] din2, 36 | input [0 : 0] din3, 37 | input [0 : 0] din4, 38 | input [0 : 0] din5, 39 | input [0 : 0] din6, 40 | input [0 : 0] din7, 41 | input [0 : 0] din8, 42 | input [0 : 0] din9, 43 | input [0 : 0] din10, 44 | input [0 : 0] din11, 45 | input [0 : 0] din12, 46 | input [0 : 0] din13, 47 | input [0 : 0] din14, 48 | input [0 : 0] din15, 49 | input [0 : 0] din16, 50 | input [3 : 0] din17, 51 | output [0 : 0] dout); 52 | 53 | // puts internal signals 54 | wire [3 : 0] sel; 55 | // level 1 signals 56 | wire [0 : 0] mux_1_0; 57 | wire [0 : 0] mux_1_1; 58 | wire [0 : 0] mux_1_2; 59 | wire [0 : 0] mux_1_3; 60 | wire [0 : 0] mux_1_4; 61 | wire [0 : 0] mux_1_5; 62 | wire [0 : 0] mux_1_6; 63 | wire [0 : 0] mux_1_7; 64 | // level 2 signals 65 | wire [0 : 0] mux_2_0; 66 | wire [0 : 0] mux_2_1; 67 | wire [0 : 0] mux_2_2; 68 | wire [0 : 0] mux_2_3; 69 | // level 3 signals 70 | wire [0 : 0] mux_3_0; 71 | wire [0 : 0] mux_3_1; 72 | // level 4 signals 73 | wire [0 : 0] mux_4_0; 74 | 75 | assign sel = din17; 76 | 77 | // Generate level 1 logic 78 | assign mux_1_0 = (sel[0] == 0)? din1 : din2; 79 | assign mux_1_1 = (sel[0] == 0)? din3 : din4; 80 | assign mux_1_2 = (sel[0] == 0)? din5 : din6; 81 | assign mux_1_3 = (sel[0] == 0)? din7 : din8; 82 | assign mux_1_4 = (sel[0] == 0)? din9 : din10; 83 | assign mux_1_5 = (sel[0] == 0)? din11 : din12; 84 | assign mux_1_6 = (sel[0] == 0)? din13 : din14; 85 | assign mux_1_7 = (sel[0] == 0)? din15 : din16; 86 | 87 | // Generate level 2 logic 88 | assign mux_2_0 = (sel[1] == 0)? mux_1_0 : mux_1_1; 89 | assign mux_2_1 = (sel[1] == 0)? mux_1_2 : mux_1_3; 90 | assign mux_2_2 = (sel[1] == 0)? mux_1_4 : mux_1_5; 91 | assign mux_2_3 = (sel[1] == 0)? mux_1_6 : mux_1_7; 92 | 93 | // Generate level 3 logic 94 | assign mux_3_0 = (sel[2] == 0)? mux_2_0 : mux_2_1; 95 | assign mux_3_1 = (sel[2] == 0)? mux_2_2 : mux_2_3; 96 | 97 | // Generate level 4 logic 98 | assign mux_4_0 = (sel[3] == 0)? mux_3_0 : mux_3_1; 99 | 100 | // output logic 101 | assign dout = mux_4_0; 102 | 103 | endmodule 104 | -------------------------------------------------------------------------------- /cl_chronos/riscv_code/include/simulator.h: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | #include 4 | #include 5 | #include 6 | 7 | typedef unsigned char uint8_t; 8 | typedef unsigned short uint16_t; 9 | typedef unsigned int uint32_t; 10 | typedef unsigned long uint64_t; 11 | 12 | typedef unsigned int uint; 13 | 14 | void finish_task() { 15 | } 16 | 17 | struct task { 18 | uint32_t ts; 19 | uint32_t ttype; 20 | uint32_t locale; 21 | uint32_t args[4]; 22 | }; 23 | struct compare_task { 24 | bool operator() (const task &a, const task &b) const { 25 | return a.ts > b.ts; 26 | } 27 | }; 28 | 29 | std::priority_queue, compare_task > pq; 30 | 31 | static inline void chronos_init() { 32 | 33 | 34 | } 35 | 36 | void undo_log_write(uint* addr, uint data) { 37 | } 38 | 39 | void enq_task_arg4(uint ttype, uint ts, uint locale, uint arg0, uint arg1, uint arg2, uint arg3){ 40 | task t = {ts, ttype, locale, arg0, arg1, arg2, arg3}; 41 | printf("\tEnq Task ts:%4x ttype:%2d locale:%6x args:(%4x %4x %4x %4x)\n", 42 | t.ts, t.ttype, locale, t.args[0], t.args[1], t.args[2], t.args[3]); 43 | pq.push(t); 44 | } 45 | 46 | void enq_task_arg0(uint ttype, uint ts, uint locale){ 47 | enq_task_arg4(ttype, ts, locale, 0, 0, 0, 0); 48 | } 49 | void enq_task_arg1(uint ttype, uint ts, uint locale, uint arg0){ 50 | enq_task_arg4(ttype, ts, locale, arg0, 0, 0, 0); 51 | } 52 | void enq_task_arg2(uint ttype, uint ts, uint locale, uint arg0, uint arg1){ 53 | enq_task_arg4(ttype, ts, locale, arg0, arg1, 0, 0); 54 | } 55 | void enq_task_arg3(uint ttype, uint ts, uint locale, uint arg0, uint arg1, uint arg2){ 56 | enq_task_arg4(ttype, ts, locale, arg0, arg1, arg2, 0); 57 | } 58 | 59 | 60 | void deq_task() { 61 | task t = pq.top(); 62 | printf("Deq Task ts:%4x ttype:%2d locale:%6x args:(%8x %8x %4x %4x) \n", 63 | t.ts, t.ttype, t.locale, t.args[0], t.args[1], t.args[2], t.args[3]); 64 | pq.pop(); 65 | } 66 | void deq_task_arg0(uint* ttype, uint* ts, uint* locale) { 67 | if (pq.empty()) {*ttype = -1; return;} 68 | task t = pq.top(); 69 | *ttype = t.ttype; *ts = t.ts; *locale = t.locale; 70 | deq_task(); 71 | } 72 | void deq_task_arg1(uint* ttype, uint* ts, uint* locale, uint* arg0) { 73 | if (pq.empty()) {*ttype = -1; return;} 74 | task t = pq.top(); 75 | *ttype = t.ttype; *ts = t.ts; *locale = t.locale; *arg0 = t.args[0]; 76 | deq_task(); 77 | } 78 | void deq_task_arg2(uint* ttype, uint* ts, uint* locale, uint* arg0, uint* arg1) { 79 | if (pq.empty()) {*ttype = -1; return;} 80 | task t = pq.top(); 81 | *ttype = t.ttype; *ts = t.ts; *locale = t.locale; 82 | *arg0 = t.args[0]; *arg1 = t.args[1]; 83 | deq_task(); 84 | } 85 | void deq_task_arg3(uint* ttype, uint* ts, uint* locale, uint* arg0, uint* arg1, uint* arg2) { 86 | if (pq.empty()) {*ttype = -1; return;} 87 | task t = pq.top(); 88 | *ttype = t.ttype; *ts = t.ts; *locale = t.locale; 89 | *arg0 = t.args[0]; *arg1 = t.args[1]; *arg2 = t.args[2]; 90 | deq_task(); 91 | } 92 | void deq_task_arg4(uint* ttype, uint* ts, uint* locale, uint* arg0, uint* arg1, uint* arg2, uint* arg3) { 93 | if (pq.empty()) {*ttype = -1; return;} 94 | task t = pq.top(); 95 | *ttype = t.ttype; *ts = t.ts; *locale = t.locale; 96 | *arg0 = t.args[0]; *arg1 = t.args[1]; *arg2 = t.args[2]; *arg3 = t.args[3]; 97 | deq_task(); 98 | } 99 | 100 | 101 | -------------------------------------------------------------------------------- /cl_chronos/hls/sssp/run_hls.tcl: -------------------------------------------------------------------------------- 1 | # ******************************************************************************* 2 | # Vendor: Xilinx 3 | # Associated Filename: run_hls.tcl 4 | # Purpose: Tcl commands to setup a Vivado HLS project 5 | # Device: All 6 | # Revision History: March 1, 2013 - initial release 7 | # 8 | # ******************************************************************************* 9 | # Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. 10 | # 11 | # This file contains confidential and proprietary information of Xilinx, Inc. and 12 | # is protected under U.S. and international copyright and other intellectual 13 | # property laws. 14 | # 15 | # DISCLAIMER 16 | # This disclaimer is not a license and does not grant any rights to the materials 17 | # distributed herewith. Except as otherwise provided in a valid license issued to 18 | # you by Xilinx, and to the maximum extent permitted by applicable law: 19 | # (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX 20 | # HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, 21 | # INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR 22 | # FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether 23 | # in contract or tort, including negligence, or under any other theory of 24 | # liability) for any loss or damage of any kind or nature related to, arising under 25 | # or in connection with these materials, including for any direct, or any indirect, 26 | # special, incidental, or consequential loss or damage (including loss of data, 27 | # profits, goodwill, or any type of loss or damage suffered as a result of any 28 | # action brought by a third party) even if such damage or loss was reasonably 29 | # foreseeable or Xilinx had been advised of the possibility of the same. 30 | # 31 | # CRITICAL APPLICATIONS 32 | # Xilinx products are not designed or intended to be fail-safe, or for use in any 33 | # application requiring fail-safe performance, such as life-support or safety 34 | # devices or systems, Class III medical devices, nuclear facilities, applications 35 | # related to the deployment of airbags, or any other applications that could lead 36 | # to death, personal injury, or severe property or environmental damage 37 | # (individually and collectively, "Critical Applications"). Customer assumes the 38 | # sole risk and liability of any use of Xilinx products in Critical Applications, 39 | # subject only to applicable laws and regulations governing limitations on product 40 | # liability. 41 | # 42 | # THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT 43 | # ALL TIMES. 44 | 45 | ############################################## 46 | # Project settings 47 | 48 | # Create a project 49 | open_project -reset sssp_prj 50 | 51 | # The source file and test bench 52 | add_files sssp.cpp 53 | add_files -tb sssp_test.cpp 54 | add_files -tb input_graph 55 | # Specify the top-level function for synthesis 56 | set_top sssp_hls 57 | 58 | ########################### 59 | # Solution settings 60 | 61 | # Create solution1 62 | open_solution -reset solution1 63 | 64 | # Specify a Xilinx device and clock period 65 | # - Do not specify a clock uncertainty (margin) 66 | # - Let the margin to default to 12.5% of clock period 67 | set_part {xc7k160tfbg484-1} 68 | create_clock -period 4 69 | #set_clock_uncertainty 1.25 70 | 71 | # Simulate the C code 72 | #csim_design 73 | csynth_design 74 | 75 | # Do not perform any other steps 76 | # - The basic project will be opened in the GUI 77 | exit 78 | 79 | -------------------------------------------------------------------------------- /cl_chronos/hls/astar/run_sim.tcl: -------------------------------------------------------------------------------- 1 | # ******************************************************************************* 2 | # Vendor: Xilinx 3 | # Associated Filename: run_hls.tcl 4 | # Purpose: Tcl commands to setup a Vivado HLS project 5 | # Device: All 6 | # Revision History: March 1, 2013 - initial release 7 | # 8 | # ******************************************************************************* 9 | # Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. 10 | # 11 | # This file contains confidential and proprietary information of Xilinx, Inc. and 12 | # is protected under U.S. and international copyright and other intellectual 13 | # property laws. 14 | # 15 | # DISCLAIMER 16 | # This disclaimer is not a license and does not grant any rights to the materials 17 | # distributed herewith. Except as otherwise provided in a valid license issued to 18 | # you by Xilinx, and to the maximum extent permitted by applicable law: 19 | # (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX 20 | # HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, 21 | # INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR 22 | # FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether 23 | # in contract or tort, including negligence, or under any other theory of 24 | # liability) for any loss or damage of any kind or nature related to, arising under 25 | # or in connection with these materials, including for any direct, or any indirect, 26 | # special, incidental, or consequential loss or damage (including loss of data, 27 | # profits, goodwill, or any type of loss or damage suffered as a result of any 28 | # action brought by a third party) even if such damage or loss was reasonably 29 | # foreseeable or Xilinx had been advised of the possibility of the same. 30 | # 31 | # CRITICAL APPLICATIONS 32 | # Xilinx products are not designed or intended to be fail-safe, or for use in any 33 | # application requiring fail-safe performance, such as life-support or safety 34 | # devices or systems, Class III medical devices, nuclear facilities, applications 35 | # related to the deployment of airbags, or any other applications that could lead 36 | # to death, personal injury, or severe property or environmental damage 37 | # (individually and collectively, "Critical Applications"). Customer assumes the 38 | # sole risk and liability of any use of Xilinx products in Critical Applications, 39 | # subject only to applicable laws and regulations governing limitations on product 40 | # liability. 41 | # 42 | # THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT 43 | # ALL TIMES. 44 | 45 | ############################################## 46 | # Project settings 47 | 48 | # Create a project 49 | open_project -reset astar_prj 50 | 51 | # The source file and test bench 52 | add_files astar.cpp 53 | add_files -tb astar_test.cpp 54 | add_files -tb monaco.bin 55 | # Specify the top-level function for synthesis 56 | set_top astar_dist 57 | 58 | ########################### 59 | # Solution settings 60 | 61 | # Create solution1 62 | open_solution -reset solution1 63 | 64 | # Specify a Xilinx device and clock period 65 | # - Do not specify a clock uncertainty (margin) 66 | # - Let the margin to default to 12.5% of clock period 67 | set_part {xc7k160tfbg484-1} 68 | create_clock -period 8 69 | #set_clock_uncertainty 1.25 70 | 71 | # Simulate the C code 72 | #csim_design 73 | csynth_design 74 | 75 | # Do not perform any other steps 76 | # - The basic project will be opened in the GUI 77 | exit 78 | 79 | -------------------------------------------------------------------------------- /cl_chronos/hls/astar/run_hls.tcl: -------------------------------------------------------------------------------- 1 | # ******************************************************************************* 2 | # Vendor: Xilinx 3 | # Associated Filename: run_hls.tcl 4 | # Purpose: Tcl commands to setup a Vivado HLS project 5 | # Device: All 6 | # Revision History: March 1, 2013 - initial release 7 | # 8 | # ******************************************************************************* 9 | # Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. 10 | # 11 | # This file contains confidential and proprietary information of Xilinx, Inc. and 12 | # is protected under U.S. and international copyright and other intellectual 13 | # property laws. 14 | # 15 | # DISCLAIMER 16 | # This disclaimer is not a license and does not grant any rights to the materials 17 | # distributed herewith. Except as otherwise provided in a valid license issued to 18 | # you by Xilinx, and to the maximum extent permitted by applicable law: 19 | # (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX 20 | # HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, 21 | # INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR 22 | # FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether 23 | # in contract or tort, including negligence, or under any other theory of 24 | # liability) for any loss or damage of any kind or nature related to, arising under 25 | # or in connection with these materials, including for any direct, or any indirect, 26 | # special, incidental, or consequential loss or damage (including loss of data, 27 | # profits, goodwill, or any type of loss or damage suffered as a result of any 28 | # action brought by a third party) even if such damage or loss was reasonably 29 | # foreseeable or Xilinx had been advised of the possibility of the same. 30 | # 31 | # CRITICAL APPLICATIONS 32 | # Xilinx products are not designed or intended to be fail-safe, or for use in any 33 | # application requiring fail-safe performance, such as life-support or safety 34 | # devices or systems, Class III medical devices, nuclear facilities, applications 35 | # related to the deployment of airbags, or any other applications that could lead 36 | # to death, personal injury, or severe property or environmental damage 37 | # (individually and collectively, "Critical Applications"). Customer assumes the 38 | # sole risk and liability of any use of Xilinx products in Critical Applications, 39 | # subject only to applicable laws and regulations governing limitations on product 40 | # liability. 41 | # 42 | # THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT 43 | # ALL TIMES. 44 | 45 | ############################################## 46 | # Project settings 47 | 48 | # Create a project 49 | open_project -reset astar_prj 50 | 51 | # The source file and test bench 52 | add_files astar.cpp 53 | add_files -tb astar_test.cpp 54 | add_files -tb monaco.bin 55 | add_files -tb germany.bin 56 | # Specify the top-level function for synthesis 57 | set_top astar_dist 58 | 59 | ########################### 60 | # Solution settings 61 | 62 | # Create solution1 63 | open_solution -reset solution1 64 | 65 | # Specify a Xilinx device and clock period 66 | # - Do not specify a clock uncertainty (margin) 67 | # - Let the margin to default to 12.5% of clock period 68 | set_part {xc7k160tfbg484-1} 69 | create_clock -period 8 70 | #set_clock_uncertainty 1.25 71 | 72 | # Simulate the C code 73 | #csim_design 74 | #csynth_design 75 | 76 | # Do not perform any other steps 77 | # - The basic project will be opened in the GUI 78 | exit 79 | 80 | -------------------------------------------------------------------------------- /cl_chronos/design/apps/astar/sinf_or_cosf_32_3bkb_rom.dat: -------------------------------------------------------------------------------- 1 | 20000000 2 | 1FFFD886 3 | 1FFF6217 4 | 1FFE9CB4 5 | 1FFD8861 6 | 1FFC251E 7 | 1FFA72F0 8 | 1FF871DB 9 | 1FF621E4 10 | 1FF38310 11 | 1FF09566 12 | 1FED58ED 13 | 1FE9CDAD 14 | 1FE5F3AF 15 | 1FE1CAFD 16 | 1FDD53A0 17 | 1FD88DA4 18 | 1FD37914 19 | 1FCE15FE 20 | 1FC8646D 21 | 1FC26471 22 | 1FBC1618 23 | 1FB57972 24 | 1FAE8E8E 25 | 1FA7557F 26 | 1F9FCE56 27 | 1F97F925 28 | 1F8FD600 29 | 1F8764FB 30 | 1F7EA62A 31 | 1F7599A4 32 | 1F6C3F7E 33 | 1F6297D0 34 | 1F58A2B2 35 | 1F4E603B 36 | 1F43D086 37 | 1F38F3AD 38 | 1F2DC9C9 39 | 1F2252F8 40 | 1F168F54 41 | 1F0A7EFC 42 | 1EFE220C 43 | 1EF178A4 44 | 1EE482E3 45 | 1ED740E8 46 | 1EC9B2D4 47 | 1EBBD8C9 48 | 1EADB2E9 49 | 1E9F4157 50 | 1E908436 51 | 1E817BAB 52 | 1E7227DC 53 | 1E6288EC 54 | 1E529F05 55 | 1E426A4B 56 | 1E31EAE9 57 | 1E212105 58 | 1E100CCA 59 | 1DFEAE62 60 | 1DED05F8 61 | 1DDB13B7 62 | 1DC8D7CB 63 | 1DB65262 64 | 1DA383AA 65 | 1D906BCF 66 | 1D7D0B03 67 | 1D696174 68 | 1D556F53 69 | 1D4134D2 70 | 1D2CB221 71 | 1D17E775 72 | 1D02D4FF 73 | 1CED7AF5 74 | 1CD7D98A 75 | 1CC1F0F4 76 | 1CABC16A 77 | 1C954B21 78 | 1C7E8E52 79 | 1C678B35 80 | 1C504201 81 | 1C38B2F2 82 | 1C20DE40 83 | 1C08C427 84 | 1BF064E2 85 | 1BD7C0AD 86 | 1BBED7C5 87 | 1BA5AA68 88 | 1B8C38D3 89 | 1B728345 90 | 1B5889FF 91 | 1B3E4D3F 92 | 1B23CD47 93 | 1B090A58 94 | 1AEE04B5 95 | 1AD2BC9E 96 | 1AB73259 97 | 1A9B6629 98 | 1A7F5853 99 | 1A63091B 100 | 1A4678C8 101 | 1A29A7A1 102 | 1A0C95EB 103 | 19EF43F0 104 | 19D1B1F6 105 | 19B3E048 106 | 1995CF2F 107 | 19777EF5 108 | 1958EFE5 109 | 193A224A 110 | 191B1670 111 | 18FBCCA4 112 | 18DC4533 113 | 18BC806B 114 | 189C7E9B 115 | 187C4010 116 | 185BC51B 117 | 183B0E0C 118 | 181A1B34 119 | 17F8ECE4 120 | 17D7836D 121 | 17B5DF23 122 | 17940058 123 | 1771E75F 124 | 174F948E 125 | 172D0838 126 | 170A42B4 127 | 16E74455 128 | 16C40D74 129 | 1921FB54 130 | 1921F0FE 131 | 1921D1FD 132 | 19219E50 133 | 192155F8 134 | 1920F8F5 135 | 19208748 136 | 192000F1 137 | 191F65F1 138 | 191EB64A 139 | 191DF1FB 140 | 191D1907 141 | 191C2B6E 142 | 191B2933 143 | 191A1255 144 | 1918E6D8 145 | 1917A6BC 146 | 19165204 147 | 1914E8B1 148 | 19136AC6 149 | 1911D845 150 | 19103130 151 | 190E758A 152 | 190CA555 153 | 190AC093 154 | 1908C749 155 | 1906B978 156 | 19049723 157 | 1902604E 158 | 190014FD 159 | 18FDB531 160 | 18FB40F0 161 | 18F8B83C 162 | 18F61B1A 163 | 18F3698D 164 | 18F0A399 165 | 18EDC942 166 | 18EADA8D 167 | 18E7D77E 168 | 18E4C019 169 | 18E19463 170 | 18DE5460 171 | 18DB0016 172 | 18D79789 173 | 18D41ABE 174 | 18D089BB 175 | 18CCE485 176 | 18C92B20 177 | 18C55D94 178 | 18C17BE4 179 | 18BD8618 180 | 18B97C35 181 | 18B55E40 182 | 18B12C40 183 | 18ACE63C 184 | 18A88C39 185 | 18A41E3D 186 | 189F9C50 187 | 189B0679 188 | 18965CBD 189 | 18919F23 190 | 188CCDB4 191 | 1887E875 192 | 1882EF6E 193 | 187DE2A7 194 | 1878C226 195 | 18738DF4 196 | 186E4618 197 | 1868EA9A 198 | 18637B82 199 | 185DF8D7 200 | 185862A3 201 | 1852B8EC 202 | 184CFBBD 203 | 18472B1C 204 | 18414712 205 | 183B4FA9 206 | 183544EA 207 | 182F26DC 208 | 1828F589 209 | 1822B0FA 210 | 181C5938 211 | 1815EE4D 212 | 180F7043 213 | 1808DF22 214 | 18023AF4 215 | 17FB83C3 216 | 17F4B99A 217 | 17EDDC82 218 | 17E6EC85 219 | 17DFE9AD 220 | 17D8D405 221 | 17D1AB96 222 | 17CA706D 223 | 17C32293 224 | 17BBC213 225 | 17B44EF8 226 | 17ACC94C 227 | 17A5311C 228 | 179D8671 229 | 1795C958 230 | 178DF9DC 231 | 17861808 232 | 177E23E7 233 | 17761D86 234 | 176E04F0 235 | 1765DA32 236 | 175D9D56 237 | 17554E6A 238 | 174CED79 239 | 17447A90 240 | 173BF5BA 241 | 17335F06 242 | 172AB67E 243 | 1721FC31 244 | 1719302A 245 | 17105277 246 | 17076325 247 | 16FE6240 248 | 16F54FD6 249 | 16EC2BF4 250 | 16E2F6A8 251 | 16D9AFFE 252 | 16D05806 253 | 16C6EECC 254 | 16BD745D 255 | 16B3E8C9 256 | 16AA4C1D 257 | 258 | -------------------------------------------------------------------------------- /cl_chronos/design/spill_config.vh: -------------------------------------------------------------------------------- 1 | /** $lic$ 2 | * Copyright (C) 2014-2019 by Massachusetts Institute of Technology 3 | * 4 | * This file is part of the Chronos FPGA Acceleration Framework. 5 | * 6 | * Chronos is free software; you can redistribute it and/or modify it under the 7 | * terms of the GNU General Public License as published by the Free Software 8 | * Foundation, version 2. 9 | * 10 | * If you use this framework in your research, we request that you reference 11 | * the Chronos paper ("Chronos: Efficient Speculative Parallelism for 12 | * Accelerators", Abeydeera and Sanchez, ASPLOS-25, March 2020), and that 13 | * you send us a citation of your work. 14 | * 15 | * Chronos is distributed in the hope that it will be useful, but WITHOUT ANY 16 | * WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS 17 | * FOR A PARTICULAR PURPOSE. See the GNU General Public License for more 18 | * details. 19 | * 20 | * You should have received a copy of the GNU General Public License along with 21 | * this program. If not, see . 22 | */ 23 | 24 | 25 | // Task Spilling parameters 26 | parameter LOG_TQ_SPILL_SIZE = 8; 27 | // Spilled tasks are organized into two hierachical levels. 8 Tasks go into 28 | // 1 splitter and 16 splitters go into one chunk. (Configurable below) 29 | // TODO: (find a better term than splitter; this is used for both the task type and 30 | // the 8 task set) 31 | 32 | // These four parameters are fixed at design time. Base addresses are 33 | // software configurable 34 | // Splitters are allocated in terms of chunks. A LIFO stack of free chunks is 35 | // maintained in memory by coalescer and splitter cores collaboratively. The 36 | // coalescer would pop one entry and store the 16 subsequent splitters 37 | // into the space allocated for this chunk. When the splitter (core) finishes the 38 | // last splitter (task) of a chunk, it is added to back on the stack. 39 | // The splitter core will not receive all splitter tasks of the same chunks 40 | // contiguously, hence it maintains a scratchpad of bit vectors to maintain 41 | // which tasks of which chunks are free. 42 | parameter TASKS_PER_SPLITTER = 8; 43 | parameter SPLITTERS_PER_CHUNK = 16; 44 | `ifdef XILINX_SIMULATOR 45 | parameter LOG_SPLITTER_STACK_SIZE = 9; // max(16) - limited by stack entry width 46 | `else 47 | parameter LOG_SPLITTER_STACK_SIZE = 12; // max(16) - limited by stack entry width 48 | `endif 49 | parameter LOG_SPLITTER_STACK_ENTRY_WIDTH = 4; // 16-bit index 50 | 51 | // Derived: 52 | parameter LOG_SPLITTERS_PER_CHUNK = $clog2(SPLITTERS_PER_CHUNK); // 16-bit splitters 53 | parameter LOG_SPLITTER_CHUNK_WIDTH = $clog2(TQ_WIDTH) -3 + $clog2(TASKS_PER_SPLITTER); 54 | parameter LOG_SPLITTER_ENTRIES = (LOG_SPLITTER_STACK_SIZE + LOG_SPLITTERS_PER_CHUNK); 55 | 56 | // Memory requirement for each structure 57 | parameter LOG_PER_TILE_SPILL_SCRATCHPAD_SIZE_BYTES = (LOG_SPLITTER_ENTRIES - 3); // 8K 58 | parameter LOG_PER_TILE_SPILL_STACK_SIZE_BYTES = 59 | LOG_SPLITTER_STACK_SIZE + LOG_SPLITTER_STACK_ENTRY_WIDTH - 3; // 8K 60 | parameter LOG_PER_TILE_SPILL_TASK_SIZE_BYTES = 61 | LOG_SPLITTER_ENTRIES + LOG_SPLITTER_CHUNK_WIDTH; // 8M 62 | // Tasks + Stack + Scratchpad + stack_ptr (8M + 8K + 8K + 64B) 63 | 64 | parameter STACK_PTR_ADDR_OFFSET = 0; 65 | parameter STACK_BASE_OFFSET = 64; 66 | parameter SCRATCHPAD_BASE_OFFSET = STACK_BASE_OFFSET + (1<<(LOG_PER_TILE_SPILL_STACK_SIZE_BYTES)); 67 | parameter SCRATCHPAD_END_OFFSET = SCRATCHPAD_BASE_OFFSET + 68 | (1<<(LOG_PER_TILE_SPILL_SCRATCHPAD_SIZE_BYTES)); 69 | parameter SPILL_TASK_BASE_OFFSET = 1<<(LOG_PER_TILE_SPILL_TASK_SIZE_BYTES); 70 | 71 | parameter TOTAL_SPILL_ALLOCATION = SPILL_TASK_BASE_OFFSET * 2; 72 | 73 | 74 | 75 | // Default values for configurable parameters 76 | parameter SPILL_THRESHOLD = (2**LOG_TQ_SIZE) - 5; // Start coalescing when TQ size is this 77 | -------------------------------------------------------------------------------- /cl_chronos/design/types.vh: -------------------------------------------------------------------------------- 1 | /** $lic$ 2 | * Copyright (C) 2014-2019 by Massachusetts Institute of Technology 3 | * 4 | * This file is part of the Chronos FPGA Acceleration Framework. 5 | * 6 | * Chronos is free software; you can redistribute it and/or modify it under the 7 | * terms of the GNU General Public License as published by the Free Software 8 | * Foundation, version 2. 9 | * 10 | * If you use this framework in your research, we request that you reference 11 | * the Chronos paper ("Chronos: Efficient Speculative Parallelism for 12 | * Accelerators", Abeydeera and Sanchez, ASPLOS-25, March 2020), and that 13 | * you send us a citation of your work. 14 | * 15 | * Chronos is distributed in the hope that it will be useful, but WITHOUT ANY 16 | * WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS 17 | * FOR A PARTICULAR PURPOSE. See the GNU General Public License for more 18 | * details. 19 | * 20 | * You should have received a copy of the GNU General Public License along with 21 | * this program. If not, see . 22 | */ 23 | 24 | 25 | typedef struct packed { 26 | logic [CACHE_TAG_WIDTH-1:0] tag; 27 | logic [CACHE_INDEX_WIDTH-1:0] index; 28 | logic [CACHE_BYTE_WIDTH-1:0] word; // use 'word' because 'byte' is reserved 29 | } mem_addr_t; 30 | typedef struct packed { 31 | logic [TS_WIDTH-1:0] ts; 32 | logic [TB_WIDTH-1:0] tb; 33 | } vt_t; 34 | typedef logic [TS_WIDTH+TB_WIDTH-1:0] vt_unpacked_t; 35 | 36 | typedef logic [UNDO_LOG_ADDR_WIDTH-1:0] undo_log_addr_t; 37 | typedef logic [UNDO_LOG_DATA_WIDTH-1:0] undo_log_data_t; 38 | 39 | typedef logic [TASK_TYPE_WIDTH-1:0] task_type_t; 40 | typedef logic [TS_WIDTH-1:0] ts_t; 41 | typedef logic [OBJECT_WIDTH-1:0] object_t; 42 | typedef logic [ARG_WIDTH-1:0] args_t; 43 | 44 | typedef logic [$clog2(CACHE_NUM_WAYS)-1:0] lru_width_t; 45 | 46 | typedef logic [31:0] reg_data_t; 47 | 48 | typedef logic [TB_WIDTH-1:0] tb_t; 49 | 50 | typedef logic [31:0] cache_addr_t; 51 | typedef logic [ARG_WIDTH-1:0] arg_t; 52 | 53 | // Gloabl type definitions 54 | typedef struct packed { 55 | args_t args; 56 | logic producer; // task is likely to generate additional tasks 57 | logic no_write; // task will not do any write 58 | logic no_read; // task will not read any read-write data 59 | logic non_spec; // task will not be dequeued unless the GVT==ts 60 | object_t object; 61 | ts_t ts; 62 | task_type_t ttype; 63 | } task_t; 64 | 65 | 66 | typedef enum logic[2:0] {NOP, ENQ, DEQ_MIN, REPLACE, DEQ_MAX, DEQ_MAX_ENQ, 67 | DEQ_MAX_DEQ_MIN, DEQ_MAX_REPLACE } heap_op_t; 68 | 69 | typedef logic [511:0] cache_line_t; 70 | 71 | typedef logic [15:0] axi_id_t; 72 | typedef logic [63:0] axi_addr_t; 73 | typedef logic [63:0] axi_strb_t; 74 | typedef logic [7:0] axi_len_t; 75 | typedef logic [2:0] axi_size_t; 76 | typedef logic [1:0] axi_resp_t; 77 | typedef logic [511:0] axi_data_t; 78 | 79 | 80 | 81 | typedef logic [LOG_N_TILES-1:0] tile_id_t; 82 | typedef logic [LOG_TSB_SIZE-1:0] tsb_entry_id_t; 83 | typedef logic [LOG_CHILDREN_PER_TASK:0] child_id_t; 84 | typedef logic [LOG_UNDO_LOG_ENTRIES_PER_TASK-1:0] undo_id_t; 85 | 86 | typedef logic [LOG_TQ_SIZE-1:0] tq_slot_t; 87 | typedef logic [LOG_CQ_SLICE_SIZE-1:0] cq_slice_slot_t; 88 | typedef logic [5:0] core_id_t; 89 | typedef logic [$clog2(N_THREADS)-1:0] thread_id_t; 90 | typedef logic [EPOCH_WIDTH-1:0] epoch_t; 91 | 92 | typedef logic [LOG_STAGE_FIFO_SIZE:0] fifo_size_t; 93 | 94 | typedef logic [RW_WIDTH-1:0] rw_data_t; 95 | typedef struct packed { 96 | task_t task_desc; 97 | cq_slice_slot_t cq_slot; 98 | thread_id_t thread; 99 | rw_data_t object; 100 | } rw_write_t; 101 | 102 | typedef logic [LOG_N_SUB_TYPES-1:0] subtype_t; 103 | typedef logic [DATA_WIDTH-1:0] ro_data_t; 104 | 105 | typedef logic [7:0] byte_t; 106 | 107 | -------------------------------------------------------------------------------- /cl_chronos/hls/astar/astar.h: -------------------------------------------------------------------------------- 1 | /** $lic$ 2 | * Copyright (C) 2014-2019 by Massachusetts Institute of Technology 3 | * 4 | * This file is part of the Chronos FPGA Acceleration Framework. 5 | * 6 | * Chronos is free software; you can redistribute it and/or modify it under the 7 | * terms of the GNU General Public License as published by the Free Software 8 | * Foundation, version 2. 9 | * 10 | * If you use this framework in your research, we request that you reference 11 | * the Chronos paper ("Chronos: Efficient Speculative Parallelism for 12 | * Accelerators", Abeydeera and Sanchez, ASPLOS-25, March 2020), and that 13 | * you send us a citation of your work. 14 | * 15 | * Chronos is distributed in the hope that it will be useful, but WITHOUT ANY 16 | * WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS 17 | * FOR A PARTICULAR PURPOSE. See the GNU General Public License for more 18 | * details. 19 | * 20 | * You should have received a copy of the GNU General Public License along with 21 | * this program. If not, see . 22 | */ 23 | 24 | /******************************************************************************* 25 | Vendor: Xilinx 26 | Associated Filename: array_io.h 27 | Purpose: Vivado HLS tutorial example 28 | Device: All 29 | Revision History: March 1, 2013 - initial release 30 | 31 | ******************************************************************************* 32 | Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. 33 | 34 | This file contains confidential and proprietary information of Xilinx, Inc. and 35 | is protected under U.S. and international copyright and other intellectual 36 | property laws. 37 | 38 | DISCLAIMER 39 | This disclaimer is not a license and does not grant any rights to the materials 40 | distributed herewith. Except as otherwise provided in a valid license issued to 41 | you by Xilinx, and to the maximum extent permitted by applicable law: 42 | (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX 43 | HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, 44 | INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR 45 | FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether 46 | in contract or tort, including negligence, or under any other theory of 47 | liability) for any loss or damage of any kind or nature related to, arising under 48 | or in connection with these materials, including for any direct, or any indirect, 49 | special, incidental, or consequential loss or damage (including loss of data, 50 | profits, goodwill, or any type of loss or damage suffered as a result of any 51 | action brought by a third party) even if such damage or loss was reasonably 52 | foreseeable or Xilinx had been advised of the possibility of the same. 53 | 54 | CRITICAL APPLICATIONS 55 | Xilinx products are not designed or intended to be fail-safe, or for use in any 56 | application requiring fail-safe performance, such as life-support or safety 57 | devices or systems, Class III medical devices, nuclear facilities, applications 58 | related to the deployment of airbags, or any other applications that could lead 59 | to death, personal injury, or severe property or environmental damage 60 | (individually and collectively, "Critical Applications"). Customer asresultes the 61 | sole risk and liability of any use of Xilinx products in Critical Applications, 62 | subject only to applicable laws and regulations governing limitations on product 63 | liability. 64 | 65 | THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT 66 | ALL TIMES. 67 | 68 | *******************************************************************************/ 69 | #ifndef ASTAR_H_ 70 | #define ASTAR_H_ 71 | 72 | #include 73 | #include "hls_stream.h" 74 | #include "ap_int.h" 75 | 76 | typedef struct { 77 | ap_uint<32> ts; 78 | ap_uint<32> object; 79 | ap_uint<4> ttype; 80 | ap_uint<1> args; 81 | } task_t; 82 | 83 | typedef struct { 84 | ap_uint<32> addr; 85 | ap_uint<32> data; 86 | } undo_log_t; 87 | 88 | typedef ap_uint<32> addr_t; 89 | //fp_t should cover from [-pi, pi] 90 | typedef ap_fixed<32,3> fp_t; 91 | 92 | void astar_dist (fp_t x1, fp_t x2, fp_t y1, fp_t y2, unsigned int* out); 93 | #endif 94 | -------------------------------------------------------------------------------- /cl_chronos/design/task_type_fifo.sv: -------------------------------------------------------------------------------- 1 | /** $lic$ 2 | * Copyright (C) 2014-2019 by Massachusetts Institute of Technology 3 | * 4 | * This file is part of the Chronos FPGA Acceleration Framework. 5 | * 6 | * Chronos is free software; you can redistribute it and/or modify it under the 7 | * terms of the GNU General Public License as published by the Free Software 8 | * Foundation, version 2. 9 | * 10 | * If you use this framework in your research, we request that you reference 11 | * the Chronos paper ("Chronos: Efficient Speculative Parallelism for 12 | * Accelerators", Abeydeera and Sanchez, ASPLOS-25, March 2020), and that 13 | * you send us a citation of your work. 14 | * 15 | * Chronos is distributed in the hope that it will be useful, but WITHOUT ANY 16 | * WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS 17 | * FOR A PARTICULAR PURPOSE. See the GNU General Public License for more 18 | * details. 19 | * 20 | * You should have received a copy of the GNU General Public License along with 21 | * this program. If not, see . 22 | */ 23 | 24 | import chronos::*; 25 | 26 | // MODULE NOT USED ANY MORE 27 | module task_type_fifo #( 28 | parameter ID = 0 29 | ) ( 30 | input clk, 31 | input rstn, 32 | 33 | // from tq 34 | input s_wvalid, 35 | output logic s_wready, 36 | input task_t s_wdata, 37 | input cq_slice_slot_t s_wslot, 38 | 39 | // to coflict checker 40 | output task_t s_rdata, 41 | output cq_slice_slot_t s_rslot, 42 | output logic s_rvalid, 43 | input s_rresp, // 0- accept, 1 -reject 44 | input s_rresp_valid, 45 | 46 | output fifo_empty, // for termination checking 47 | 48 | output ts_t lvt, 49 | 50 | reg_bus_t.master reg_bus 51 | ); 52 | localparam WIDTH = $bits(s_wdata) + $bits(s_wslot); 53 | // Per task type FIFO queue. 54 | 55 | logic fifo_full; 56 | logic fifo_wr_en, fifo_rd_en; 57 | logic [WIDTH-1:0] fifo_rd_data, fifo_wr_data; 58 | 59 | logic [6:0] fifo_size; 60 | logic [6:0] full_threshold; 61 | 62 | always_ff @(posedge clk) begin 63 | if (!rstn) begin 64 | full_threshold <= 2; 65 | end else begin 66 | if (reg_bus.wvalid) begin 67 | case (reg_bus.waddr) 68 | DEQ_FIFO_FULL_THRESHOLD: full_threshold <= reg_bus.wdata; 69 | endcase 70 | end 71 | end 72 | end 73 | always_ff @(posedge clk) begin 74 | if (!rstn) begin 75 | reg_bus.rvalid <= 1'b0; 76 | end 77 | if (reg_bus.arvalid) begin 78 | reg_bus.rvalid <= 1'b1; 79 | case (reg_bus.araddr) 80 | DEQ_FIFO_FULL_THRESHOLD : reg_bus.rdata <= full_threshold; 81 | DEQ_FIFO_SIZE : reg_bus.rdata <= fifo_size; 82 | DEQ_FIFO_NEXT_TASK_TS : reg_bus.rdata <= s_rdata.ts; 83 | DEQ_FIFO_NEXT_TASK_OBJECT : reg_bus.rdata <= s_rdata.object; 84 | endcase 85 | end else begin 86 | reg_bus.rvalid <= 1'b0; 87 | end 88 | end 89 | 90 | fifo #( 91 | .WIDTH(WIDTH), 92 | .LOG_DEPTH(6) 93 | ) TASK_FIFO ( 94 | .clk(clk), 95 | .rstn(rstn), 96 | .wr_en(fifo_wr_en), 97 | .wr_data(fifo_wr_data), 98 | 99 | .full(), 100 | .empty(fifo_empty), 101 | 102 | .rd_en(fifo_rd_en), 103 | .rd_data(fifo_rd_data), 104 | 105 | .size(fifo_size) 106 | ); 107 | 108 | assign {s_rdata, s_rslot} = fifo_rd_data; 109 | assign s_rvalid = !fifo_empty; 110 | 111 | assign fifo_full = (fifo_size == full_threshold); 112 | 113 | // hoist this out. leads to to simulator deadlock otherwise. 114 | assign s_wready = (s_rresp_valid & s_rresp) ? 1'b0 : !fifo_full; 115 | 116 | always_comb begin 117 | if (s_rresp_valid & s_rresp) begin 118 | // conflict check failed. Re-enqueue fifo head 119 | // In case the FIFO is full, it should handle correctly 120 | fifo_wr_en = 1'b1; 121 | fifo_wr_data = fifo_rd_data; 122 | fifo_rd_en = 1'b1; 123 | end else begin 124 | fifo_wr_en = s_wvalid & s_wready; 125 | fifo_wr_data = {s_wdata, s_wslot}; 126 | fifo_rd_en = s_rresp_valid; 127 | end 128 | end 129 | 130 | endmodule 131 | -------------------------------------------------------------------------------- /cl_chronos/hls/sssp/sssp.h: -------------------------------------------------------------------------------- 1 | /** $lic$ 2 | * Copyright (C) 2014-2019 by Massachusetts Institute of Technology 3 | * 4 | * This file is part of the Chronos FPGA Acceleration Framework. 5 | * 6 | * Chronos is free software; you can redistribute it and/or modify it under the 7 | * terms of the GNU General Public License as published by the Free Software 8 | * Foundation, version 2. 9 | * 10 | * If you use this framework in your research, we request that you reference 11 | * the Chronos paper ("Chronos: Efficient Speculative Parallelism for 12 | * Accelerators", Abeydeera and Sanchez, ASPLOS-25, March 2020), and that 13 | * you send us a citation of your work. 14 | * 15 | * Chronos is distributed in the hope that it will be useful, but WITHOUT ANY 16 | * WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS 17 | * FOR A PARTICULAR PURPOSE. See the GNU General Public License for more 18 | * details. 19 | * 20 | * You should have received a copy of the GNU General Public License along with 21 | * this program. If not, see . 22 | */ 23 | 24 | /******************************************************************************* 25 | Vendor: Xilinx 26 | Associated Filename: array_io.h 27 | Purpose: Vivado HLS tutorial example 28 | Device: All 29 | Revision History: March 1, 2013 - initial release 30 | 31 | ******************************************************************************* 32 | Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. 33 | 34 | This file contains confidential and proprietary information of Xilinx, Inc. and 35 | is protected under U.S. and international copyright and other intellectual 36 | property laws. 37 | 38 | DISCLAIMER 39 | This disclaimer is not a license and does not grant any rights to the materials 40 | distributed herewith. Except as otherwise provided in a valid license issued to 41 | you by Xilinx, and to the maximum extent permitted by applicable law: 42 | (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX 43 | HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, 44 | INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR 45 | FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether 46 | in contract or tort, including negligence, or under any other theory of 47 | liability) for any loss or damage of any kind or nature related to, arising under 48 | or in connection with these materials, including for any direct, or any indirect, 49 | special, incidental, or consequential loss or damage (including loss of data, 50 | profits, goodwill, or any type of loss or damage suffered as a result of any 51 | action brought by a third party) even if such damage or loss was reasonably 52 | foreseeable or Xilinx had been advised of the possibility of the same. 53 | 54 | CRITICAL APPLICATIONS 55 | Xilinx products are not designed or intended to be fail-safe, or for use in any 56 | application requiring fail-safe performance, such as life-support or safety 57 | devices or systems, Class III medical devices, nuclear facilities, applications 58 | related to the deployment of airbags, or any other applications that could lead 59 | to death, personal injury, or severe property or environmental damage 60 | (individually and collectively, "Critical Applications"). Customer asresultes the 61 | sole risk and liability of any use of Xilinx products in Critical Applications, 62 | subject only to applicable laws and regulations governing limitations on product 63 | liability. 64 | 65 | THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT 66 | ALL TIMES. 67 | 68 | *******************************************************************************/ 69 | #ifndef SSSP_H_ 70 | #define SSSP_H_ 71 | 72 | #include 73 | #include "hls_stream.h" 74 | #include "ap_int.h" 75 | 76 | typedef struct { 77 | ap_uint<32> ts; 78 | ap_uint<32> object; 79 | ap_uint<4> ttype; 80 | ap_uint<1> args; 81 | } task_t; 82 | 83 | typedef struct { 84 | ap_uint<32> addr; 85 | ap_uint<32> data; 86 | } undo_log_t; 87 | 88 | typedef ap_uint<32> addr_t; 89 | 90 | void sssp_hls (task_t task_in, hls::stream* task_out, ap_uint<32>* l1, hls::stream* undo_log_entry); 91 | #endif 92 | -------------------------------------------------------------------------------- /cl_chronos/verif/tests/module_task_unit.sv: -------------------------------------------------------------------------------- 1 | /** $lic$ 2 | * Copyright (C) 2014-2019 by Massachusetts Institute of Technology 3 | * 4 | * This file is part of the Chronos FPGA Acceleration Framework. 5 | * 6 | * Chronos is free software; you can redistribute it and/or modify it under the 7 | * terms of the GNU General Public License as published by the Free Software 8 | * Foundation, version 2. 9 | * 10 | * If you use this framework in your research, we request that you reference 11 | * the Chronos paper ("Chronos: Efficient Speculative Parallelism for 12 | * Accelerators", Abeydeera and Sanchez, ASPLOS-25, March 2020), and that 13 | * you send us a citation of your work. 14 | * 15 | * Chronos is distributed in the hope that it will be useful, but WITHOUT ANY 16 | * WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS 17 | * FOR A PARTICULAR PURPOSE. See the GNU General Public License for more 18 | * details. 19 | * 20 | * You should have received a copy of the GNU General Public License along with 21 | * this program. If not, see . 22 | */ 23 | 24 | // Amazon FPGA Hardware Development Kit 25 | // 26 | // Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. 27 | // 28 | // Licensed under the Amazon Software License (the "License"). You may not use 29 | // this file except in compliance with the License. A copy of the License is 30 | // located at 31 | // 32 | // http://aws.amazon.com/asl/ 33 | // 34 | // or in the "license" file accompanying this file. This file is distributed on 35 | // an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or 36 | // implied. See the License for the specific language governing permissions and 37 | // limitations under the License. 38 | import chronos::*; 39 | 40 | module module_task_unit(); 41 | 42 | parameter num_tests = 100; 43 | parameter max_q_size = (1</app_tiles_threads.txt 7 | 8 | import os 9 | import sys 10 | import datetime 11 | from os import listdir 12 | 13 | def run_cmd(cmd): 14 | print(cmd) 15 | os.system(cmd) 16 | 17 | if len(sys.argv)<2: 18 | print("Usage: python run.py agfi_list.txt") 19 | exit(0) 20 | 21 | ## Save this before we go jumping around 22 | scripts_dir = os.getcwd() 23 | 24 | ## Read agfi-list 25 | fagfi = open(sys.argv[1], "r") 26 | agfi_list = {} ## indexed by agfi-tag 27 | inputs_list = {} 28 | for line in fagfi: 29 | s = line.split(); 30 | agfi_list[s[0]] = s[1] 31 | 32 | print(agfi_list) 33 | 34 | # Initialize with a random agfi 35 | agfi = agfi_list[ list(agfi_list)[0]] 36 | cmd = "sudo fpga-load-local-image -S 0 -I " + agfi 37 | run_cmd(cmd) 38 | 39 | downloaded_inputs = listdir("../inputs") 40 | #AWS_PATH = "~/.local/bin/aws" 41 | AWS_PATH = "aws" 42 | 43 | ## Read experiments 44 | 45 | ## The inputs are locates in a Zenodo hosted zip file 46 | ## The experiments.txt file specifies the 47 | ## 1. The link to the zip file 48 | ## 2. The input file names for each application 49 | ## 3. The experiments to run with these inputs 50 | # Where each experiment is a tuple [app, agfi-tag, n_tiles, n_threads] 51 | S3_BUCKET = "chronos_inputs" 52 | fexp = open("experiments.txt", "r") 53 | tests = [] 54 | for line in fexp: 55 | if line.startswith("zenodo"): 56 | url = line.split()[1] 57 | print(url) 58 | if 'chronos-inputs.zip' not in downloaded_inputs: 59 | os.chdir("../inputs/") 60 | run_cmd("wget "+url) 61 | run_cmd("unzip chronos-inputs.zip") 62 | os.chdir(scripts_dir) 63 | if line.startswith("input"): 64 | s = line.split() 65 | app = s[1] 66 | s3_loc = s[2] 67 | file_name = s[2].split("/")[-1] 68 | inputs_list[app] = file_name 69 | if line.startswith("test"): 70 | s = line.split() 71 | tests.append([s[1], s[2], s[3], s[4]]) 72 | 73 | print(inputs_list) 74 | print(tests) 75 | 76 | ## Locate runtime (and compile if necessary) 77 | if "test_chronos" not in listdir("../../software/runtime"): 78 | os.chdir("../../software/runtime") 79 | os.system("make") 80 | os.chdir(scripts_dir) 81 | 82 | if "test_chronos" not in listdir("../../software/runtime"): 83 | print("ERROR: Runtime cannot be compiled. Please investigate manually....") 84 | exit(0) 85 | 86 | 87 | d = datetime.datetime.today() 88 | index = 0 89 | runs = listdir("../runs") 90 | while(True): 91 | dirname = str(d.year) + "-" + format(d.month, '02') + "-" + format(d.day,'02') + "_" + format(index, '02') 92 | if dirname not in runs: 93 | print("creating directory "+dirname) 94 | os.mkdir("../runs/" + dirname) 95 | os.chdir("../runs/" + dirname) 96 | print(os.getcwd()) 97 | runs_dir = os.getcwd() 98 | break 99 | index = index+1 100 | 101 | 102 | ## Runs the specified experiments and save the output to ... 103 | 104 | n_repeats = 10; 105 | 106 | for t in tests: 107 | app = t[0] 108 | riscv=False 109 | Throttle=False 110 | if app.startswith("riscv"): 111 | riscv=True 112 | app = app.split("_")[1] 113 | if app.startswith("throttle"): 114 | riscv=True 115 | Throttle=True 116 | app = app.split("_")[1] 117 | if (t[1] not in agfi_list): 118 | print("%s not found in agfi-list" % t[1]) 119 | continue 120 | agfi = agfi_list[t[1]] 121 | n_tiles = t[2] 122 | n_threads = t[3] 123 | 124 | for r in range(n_repeats): 125 | cmd = "sudo fpga-load-local-image -S 0 -I " + agfi 126 | run_cmd(cmd) 127 | cmd = "sudo ../../../software/runtime/test_chronos --n_tiles=" +n_tiles 128 | if (Throttle): 129 | cmd += " --rate_ctrl=16 " 130 | cmd += " --n_threads=" + n_threads +" " + app 131 | cmd += " ../../inputs/chronos-inputs/" + inputs_list[app] 132 | if (riscv): 133 | cmd +=" ../../../riscv_code/binaries/" + app + ".hex" 134 | cmd += " | tee " + t[1] 135 | if (riscv): 136 | cmd += "_"+app 137 | cmd += "_tiles_"+n_tiles+"_threads_"+n_threads 138 | cmd += "_"+str(r) +".result" 139 | run_cmd(cmd) 140 | #exit(0) 141 | 142 | os.chdir(scripts_dir) 143 | 144 | 145 | 146 | 147 | -------------------------------------------------------------------------------- /cl_chronos/design/mem_arbiter.sv: -------------------------------------------------------------------------------- 1 | /** $lic$ 2 | * Copyright (C) 2014-2019 by Massachusetts Institute of Technology 3 | * 4 | * This file is part of the Chronos FPGA Acceleration Framework. 5 | * 6 | * Chronos is free software; you can redistribute it and/or modify it under the 7 | * terms of the GNU General Public License as published by the Free Software 8 | * Foundation, version 2. 9 | * 10 | * If you use this framework in your research, we request that you reference 11 | * the Chronos paper ("Chronos: Efficient Speculative Parallelism for 12 | * Accelerators", Abeydeera and Sanchez, ASPLOS-25, March 2020), and that 13 | * you send us a citation of your work. 14 | * 15 | * Chronos is distributed in the hope that it will be useful, but WITHOUT ANY 16 | * WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS 17 | * FOR A PARTICULAR PURPOSE. See the GNU General Public License for more 18 | * details. 19 | * 20 | * You should have received a copy of the GNU General Public License along with 21 | * this program. If not, see . 22 | */ 23 | 24 | import chronos::*; 25 | 26 | 27 | module mem_arbiter( 28 | input clk, 29 | input rstn, 30 | 31 | axi_bus_t.master l2, 32 | axi_bus_t.master pci, 33 | 34 | axi_bus_t.slave mem 35 | ); 36 | 37 | logic sel; 38 | logic last_tx_l2; 39 | // Hack until a proper AXI Xbar is implemented 40 | always_ff @(posedge clk) begin 41 | if (!rstn) begin 42 | last_tx_l2 <= 1'b0; 43 | end else begin 44 | if (l2.arvalid | l2.awvalid) begin 45 | last_tx_l2 <= 1; 46 | end else if (pci.awvalid | pci.arvalid) begin 47 | last_tx_l2 <= 0; 48 | end 49 | end 50 | end 51 | 52 | always_comb begin 53 | sel = last_tx_l2; 54 | if (l2.arvalid | l2.awvalid) begin 55 | sel = 1; 56 | end else if (pci.awvalid | pci.arvalid) begin 57 | sel = 0; 58 | end 59 | end 60 | 61 | assign l2.awready = mem.awready; 62 | assign l2.arready = mem.arready; 63 | assign l2.wready = !sel ? 0: mem.wready; 64 | assign l2.bid = !sel ? 0: mem.bid; 65 | assign l2.bresp = !sel ? 0: mem.bresp; 66 | assign l2.bvalid = !sel ? 0: mem.bvalid; 67 | assign l2.rid = !sel ? 0: mem.rid; 68 | assign l2.rdata = !sel ? 0: mem.rdata; 69 | assign l2.rresp = !sel ? 0: mem.rresp; 70 | assign l2.rlast = !sel ? 0: mem.rlast; 71 | assign l2.rvalid = !sel ? 0: mem.rvalid; 72 | 73 | assign pci.awready = mem.awready; 74 | assign pci.arready = mem.arready; 75 | assign pci.wready = sel ? 0: mem.wready; 76 | assign pci.bid = sel ? 0: mem.bid; 77 | assign pci.bresp = sel ? 0: mem.bresp; 78 | assign pci.bvalid = sel ? 0: mem.bvalid; 79 | assign pci.rid = sel ? 0: mem.rid; 80 | assign pci.rdata = sel ? 0: mem.rdata; 81 | assign pci.rresp = sel ? 0: mem.rresp; 82 | assign pci.rlast = sel ? 0: mem.rlast; 83 | assign pci.rvalid = sel ? 0: mem.rvalid; 84 | 85 | always_comb begin 86 | if (sel) begin 87 | mem.awid = l2.awid; 88 | mem.awaddr = l2.awaddr; 89 | mem.awlen = l2.awlen; 90 | mem.awsize = l2.awsize; 91 | mem.awvalid = l2.awvalid; 92 | 93 | mem.arid = l2.arid; 94 | mem.araddr = l2.araddr; 95 | mem.arlen = l2.arlen; 96 | mem.arsize = l2.arsize; 97 | mem.arvalid = l2.arvalid; 98 | 99 | mem.bready = l2.bready; 100 | 101 | mem.wid = l2.wid; 102 | mem.wdata = l2.wdata; 103 | mem.wstrb = l2.wstrb; 104 | mem.wlast = l2.wlast; 105 | mem.wvalid = l2.wvalid; 106 | 107 | mem.rready = l2.rready; 108 | end else begin 109 | mem.awid = pci.awid; 110 | mem.awaddr = pci.awaddr; 111 | mem.awlen = pci.awlen; 112 | mem.awsize = pci.awsize; 113 | mem.awvalid = pci.awvalid; 114 | 115 | mem.arid = pci.arid; 116 | mem.araddr = pci.araddr; 117 | mem.arlen = pci.arlen; 118 | mem.arsize = pci.arsize; 119 | mem.arvalid = pci.arvalid; 120 | 121 | mem.bready = pci.bready; 122 | 123 | mem.wid = pci.wid; 124 | mem.wdata = pci.wdata; 125 | mem.wstrb = pci.wstrb; 126 | mem.wlast = pci.wlast; 127 | mem.wvalid = pci.wvalid; 128 | 129 | mem.rready = pci.rready; 130 | end 131 | 132 | end 133 | 134 | 135 | 136 | endmodule 137 | 138 | -------------------------------------------------------------------------------- /cl_chronos/design/apps/astar/terminate_core.sv: -------------------------------------------------------------------------------- 1 | /** $lic$ 2 | * Copyright (C) 2014-2019 by Massachusetts Institute of Technology 3 | * 4 | * This file is part of the Chronos FPGA Acceleration Framework. 5 | * 6 | * Chronos is free software; you can redistribute it and/or modify it under the 7 | * terms of the GNU General Public License as published by the Free Software 8 | * Foundation, version 2. 9 | * 10 | * If you use this framework in your research, we request that you reference 11 | * the Chronos paper ("Chronos: Efficient Speculative Parallelism for 12 | * Accelerators", Abeydeera and Sanchez, ASPLOS-25, March 2020), and that 13 | * you send us a citation of your work. 14 | * 15 | * Chronos is distributed in the hope that it will be useful, but WITHOUT ANY 16 | * WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS 17 | * FOR A PARTICULAR PURPOSE. See the GNU General Public License for more 18 | * details. 19 | * 20 | * You should have received a copy of the GNU General Public License along with 21 | * this program. If not, see . 22 | */ 23 | 24 | `ifdef XILINX_SIMULATOR 25 | `define DEBUG 26 | `endif 27 | import chronos::*; 28 | 29 | // place where tasks go to die 30 | module terminate_core 31 | #( 32 | ) ( 33 | input ap_clk, 34 | input ap_rst_n, 35 | 36 | input ap_start, 37 | output logic ap_done, 38 | output logic ap_idle, 39 | output logic ap_ready, 40 | 41 | input [TQ_WIDTH-1:0] task_in, 42 | 43 | output logic [TQ_WIDTH-1:0] task_out_V_TDATA, 44 | output logic task_out_V_TVALID, 45 | input task_out_V_TREADY, 46 | 47 | output logic [UNDO_LOG_ADDR_WIDTH + UNDO_LOG_DATA_WIDTH -1:0] undo_log_entry, 48 | output logic undo_log_entry_ap_vld, 49 | input undo_log_entry_ap_rdy, 50 | 51 | output logic m_axi_l1_V_AWVALID , 52 | input m_axi_l1_V_AWREADY, 53 | output logic [31:0] m_axi_l1_V_AWADDR , 54 | output logic [7:0] m_axi_l1_V_AWLEN , 55 | output logic [2:0] m_axi_l1_V_AWSIZE , 56 | output logic m_axi_l1_V_WVALID , 57 | input m_axi_l1_V_WREADY , 58 | output logic [31:0] m_axi_l1_V_WDATA , 59 | output logic [3:0] m_axi_l1_V_WSTRB , 60 | output logic m_axi_l1_V_WLAST , 61 | output logic m_axi_l1_V_ARVALID, 62 | input m_axi_l1_V_ARREADY, 63 | output logic [31:0] m_axi_l1_V_ARADDR , 64 | output logic [7:0] m_axi_l1_V_ARLEN , 65 | output logic [2:0] m_axi_l1_V_ARSIZE , 66 | input m_axi_l1_V_RVALID , 67 | output logic m_axi_l1_V_RREADY , 68 | input [31:0] m_axi_l1_V_RDATA , 69 | input m_axi_l1_V_RLAST , 70 | input m_axi_l1_V_RID , 71 | input [1:0] m_axi_l1_V_RRESP , 72 | input m_axi_l1_V_BVALID , 73 | output logic m_axi_l1_V_BREADY , 74 | input [1:0] m_axi_l1_V_BRESP , 75 | input m_axi_l1_V_BID , 76 | 77 | output logic [31:0] ap_state 78 | ); 79 | 80 | typedef enum logic[1:0] { 81 | NEXT_TASK, 82 | FINISH_TASK} sssp_state_t; 83 | 84 | task_t task_rdata, task_wdata; 85 | assign {task_rdata.args, task_rdata.ttype, task_rdata.object, task_rdata.ts} = task_in; 86 | 87 | assign task_out_V_TDATA = 88 | {task_wdata.args, task_wdata.ttype, task_wdata.object, task_wdata.ts}; 89 | 90 | logic clk, rstn; 91 | assign clk = ap_clk; 92 | assign rstn = ap_rst_n; 93 | 94 | sssp_state_t state, state_next; 95 | assign ap_done = (state == FINISH_TASK); 96 | assign ap_idle = (state == NEXT_TASK); 97 | assign ap_ready = (state == NEXT_TASK); 98 | 99 | assign m_axi_l1_V_RREADY = 1'b0; 100 | always_comb begin 101 | m_axi_l1_V_ARLEN = 0; // 1 beat 102 | m_axi_l1_V_ARSIZE = 3'b010; // 32 bits 103 | m_axi_l1_V_ARVALID = 1'b0; 104 | m_axi_l1_V_ARADDR = 64'h0; 105 | 106 | task_out_V_TVALID = 1'b0; 107 | task_wdata = 'x; 108 | state_next = state; 109 | 110 | case(state) 111 | NEXT_TASK: begin 112 | if (ap_start) begin 113 | state_next = FINISH_TASK; 114 | end 115 | end 116 | FINISH_TASK: begin 117 | state_next = NEXT_TASK; 118 | end 119 | 120 | endcase 121 | end 122 | 123 | assign m_axi_l1_V_BREADY = 1'b0;; 124 | 125 | assign undo_log_entry_ap_vld = 1'b0; 126 | assign m_axi_l1_V_AWVALID = 1'b0; 127 | assign m_axi_l1_V_WVALID = 1'b0; 128 | 129 | assign ap_state = 0; 130 | 131 | 132 | always_ff @(posedge clk) begin 133 | if (~rstn) begin 134 | state <= NEXT_TASK; 135 | end else begin 136 | state <= state_next; 137 | end 138 | end 139 | 140 | endmodule 141 | -------------------------------------------------------------------------------- /cl_chronos/design/task_xbar.sv: -------------------------------------------------------------------------------- 1 | /** $lic$ 2 | * Copyright (C) 2014-2019 by Massachusetts Institute of Technology 3 | * 4 | * This file is part of the Chronos FPGA Acceleration Framework. 5 | * 6 | * Chronos is free software; you can redistribute it and/or modify it under the 7 | * terms of the GNU General Public License as published by the Free Software 8 | * Foundation, version 2. 9 | * 10 | * If you use this framework in your research, we request that you reference 11 | * the Chronos paper ("Chronos: Efficient Speculative Parallelism for 12 | * Accelerators", Abeydeera and Sanchez, ASPLOS-25, March 2020), and that 13 | * you send us a citation of your work. 14 | * 15 | * Chronos is distributed in the hope that it will be useful, but WITHOUT ANY 16 | * WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS 17 | * FOR A PARTICULAR PURPOSE. See the GNU General Public License for more 18 | * details. 19 | * 20 | * You should have received a copy of the GNU General Public License along with 21 | * this program. If not, see . 22 | */ 23 | 24 | 25 | 26 | import chronos::*; 27 | 28 | module tile_xbar 29 | #( 30 | parameter NUM_SI=N_TILES, 31 | parameter NUM_MI=N_TILES, 32 | parameter DATA_WIDTH = 32 33 | ) 34 | ( 35 | input clk, 36 | input rstn, 37 | 38 | input logic [NUM_SI-1:0] s_wvalid, 39 | output logic [NUM_SI-1:0] s_wready, 40 | input [NUM_SI-1:0] [DATA_WIDTH-1:0] s_wdata, 41 | input tile_id_t [NUM_SI-1:0] s_port, 42 | 43 | output logic [NUM_MI-1:0] m_wvalid, 44 | input [NUM_MI-1:0] m_wready, 45 | output logic [NUM_SI-1:0] [DATA_WIDTH-1:0] m_wdata 46 | ); 47 | 48 | localparam LOG_NUM_SI = $clog2(NUM_SI); 49 | localparam LOG_NUM_MI = $clog2(NUM_MI); 50 | typedef logic [NUM_SI-1:0] slave_vec_t; 51 | typedef logic [LOG_NUM_SI-1:0] slave_index_t; 52 | genvar i,j; 53 | 54 | logic [NUM_SI-1:0] s_wvalid_q; 55 | logic [NUM_SI-1:0] s_wready_q; 56 | logic [NUM_SI-1:0] [DATA_WIDTH-1:0] s_wdata_q; 57 | tile_id_t [NUM_SI-1:0] s_port_q; 58 | 59 | logic [NUM_MI-1:0] m_wvalid_p; 60 | logic [NUM_MI-1:0] m_wready_p; 61 | logic [NUM_SI-1:0] [DATA_WIDTH-1:0] m_wdata_p; 62 | 63 | // W Channel 64 | slave_vec_t [NUM_MI-1:0] w_sched_in; 65 | slave_index_t [NUM_MI-1:0] w_sched_out; 66 | logic [NUM_MI-1:0] w_can_take_new; 67 | 68 | generate 69 | for (i=0;i