├── .clang-format ├── .dockerignore ├── .editorconfig ├── .gitattributes ├── .github └── issue_template.md ├── .gitignore ├── .travis.yml ├── .travis ├── build-and-test.sh ├── common.sh ├── deploy-after-success.sh └── setup.sh ├── Brewfile ├── CHANGELOG ├── CODEOWNERS ├── COPYING ├── CodeOfConduct ├── CodingReadme ├── Dockerfile ├── Makefile ├── README.md ├── backends ├── aiger │ ├── Makefile.inc │ ├── aiger.cc │ └── xaiger.cc ├── blif │ ├── Makefile.inc │ └── blif.cc ├── btor │ ├── .gitignore │ ├── Makefile.inc │ ├── btor.cc │ └── test_cells.sh ├── cxxrtl │ ├── Makefile.inc │ ├── cxxrtl.h │ ├── cxxrtl_backend.cc │ ├── cxxrtl_capi.cc │ ├── cxxrtl_capi.h │ ├── cxxrtl_vcd.h │ ├── cxxrtl_vcd_capi.cc │ └── cxxrtl_vcd_capi.h ├── edif │ ├── Makefile.inc │ ├── edif.cc │ └── runtest.py ├── firrtl │ ├── .gitignore │ ├── Makefile.inc │ ├── firrtl.cc │ ├── test.sh │ └── test.v ├── intersynth │ ├── Makefile.inc │ └── intersynth.cc ├── json │ ├── Makefile.inc │ └── json.cc ├── protobuf │ ├── .gitignore │ ├── Makefile.inc │ └── protobuf.cc ├── rtlil │ ├── Makefile.inc │ ├── rtlil_backend.cc │ └── rtlil_backend.h ├── simplec │ ├── .gitignore │ ├── Makefile.inc │ ├── simplec.cc │ ├── test00.sh │ ├── test00_tb.c │ └── test00_uut.v ├── smt2 │ ├── .gitignore │ ├── Makefile.inc │ ├── example.v │ ├── example.ys │ ├── smt2.cc │ ├── smtbmc.py │ ├── smtio.py │ └── test_cells.sh ├── smv │ ├── .gitignore │ ├── Makefile.inc │ ├── smv.cc │ └── test_cells.sh ├── spice │ ├── Makefile.inc │ └── spice.cc ├── table │ ├── Makefile.inc │ └── table.cc └── verilog │ ├── Makefile.inc │ └── verilog_backend.cc ├── examples ├── aiger │ ├── .gitignore │ ├── README │ ├── demo.sh │ └── demo.v ├── anlogic │ ├── .gitignore │ ├── README │ ├── build.sh │ ├── build.tcl │ ├── demo.adc │ ├── demo.v │ └── demo.ys ├── basys3 │ ├── README │ ├── example.v │ ├── example.xdc │ ├── run.sh │ ├── run_prog.tcl │ ├── run_vivado.tcl │ └── run_yosys.ys ├── cmos │ ├── .gitignore │ ├── README │ ├── cmos_cells.lib │ ├── cmos_cells.sp │ ├── cmos_cells.v │ ├── cmos_cells_digital.sp │ ├── counter.v │ ├── counter.ys │ ├── counter_digital.ys │ ├── counter_tb.gtkw │ ├── counter_tb.v │ ├── testbench.sh │ ├── testbench.sp │ ├── testbench_digital.sh │ └── testbench_digital.sp ├── cxx-api │ ├── demomain.cc │ └── evaldemo.cc ├── gowin │ ├── .gitignore │ ├── README │ ├── demo.cst │ ├── demo.sdc │ ├── demo.v │ ├── device.cfg │ ├── pnr.cfg │ ├── run.sh │ ├── run.tcl │ └── testbench.v ├── igloo2 │ ├── .gitignore │ ├── example.pdc │ ├── example.sdc │ ├── example.v │ ├── libero.tcl │ └── runme.sh ├── intel │ ├── DE2i-150 │ │ ├── quartus_compile │ │ │ ├── de2i.qpf │ │ │ ├── de2i.qsf │ │ │ └── runme_quartus │ │ ├── run_cycloneiv │ │ ├── sevenseg.v │ │ └── top.v │ ├── MAX10 │ │ ├── run_max10 │ │ ├── runme_postsynth │ │ ├── sevenseg.v │ │ └── top.v │ └── asicworld_lfsr │ │ ├── README │ │ ├── lfsr_updown.v │ │ ├── lfsr_updown_tb.v │ │ ├── run_cycloneiv │ │ ├── run_max10 │ │ ├── runme_postsynth │ │ └── runme_presynth ├── mimas2 │ ├── README │ ├── example.ucf │ ├── example.v │ ├── run.sh │ └── run_yosys.ys ├── osu035 │ ├── .gitignore │ ├── Makefile │ ├── example.constr │ ├── example.v │ └── example.ys ├── python-api │ ├── .gitignore │ ├── pass.py │ └── script.py └── smtbmc │ ├── .gitignore │ ├── Makefile │ ├── demo1.v │ ├── demo2.v │ ├── demo3.smtc │ ├── demo3.v │ ├── demo4.smtc │ ├── demo4.v │ ├── demo5.v │ ├── demo6.v │ ├── demo7.v │ ├── demo8.v │ └── demo9.v ├── frontends ├── aiger │ ├── Makefile.inc │ ├── aigerparse.cc │ └── aigerparse.h ├── ast │ ├── Makefile.inc │ ├── ast.cc │ ├── ast.h │ ├── dpicall.cc │ ├── genrtlil.cc │ └── simplify.cc ├── blif │ ├── Makefile.inc │ ├── blifparse.cc │ └── blifparse.h ├── json │ ├── Makefile.inc │ └── jsonparse.cc ├── liberty │ ├── Makefile.inc │ └── liberty.cc ├── rpc │ ├── Makefile.inc │ └── rpc_frontend.cc ├── rtlil │ ├── .gitignore │ ├── Makefile.inc │ ├── rtlil_frontend.cc │ ├── rtlil_frontend.h │ ├── rtlil_lexer.l │ └── rtlil_parser.y ├── verific │ ├── Makefile.inc │ ├── README │ ├── example.sby │ ├── example.sv │ ├── verific.cc │ ├── verific.h │ └── verificsva.cc └── verilog │ ├── .gitignore │ ├── Makefile.inc │ ├── const2ast.cc │ ├── preproc.cc │ ├── preproc.h │ ├── verilog_frontend.cc │ ├── verilog_frontend.h │ ├── verilog_lexer.l │ └── verilog_parser.y ├── kernel ├── bitpattern.h ├── calc.cc ├── cellaigs.cc ├── cellaigs.h ├── celledges.cc ├── celledges.h ├── celltypes.h ├── consteval.h ├── constids.inc ├── cost.h ├── driver.cc ├── ff.h ├── ffinit.h ├── hashlib.h ├── log.cc ├── log.h ├── macc.h ├── mem.cc ├── mem.h ├── modtools.h ├── register.cc ├── register.h ├── rtlil.cc ├── rtlil.h ├── satgen.cc ├── satgen.h ├── sigtools.h ├── timinginfo.h ├── utils.h ├── yosys.cc └── yosys.h ├── libs ├── bigint │ ├── .gitignore │ ├── BigInteger.cc │ ├── BigInteger.hh │ ├── BigIntegerAlgorithms.cc │ ├── BigIntegerAlgorithms.hh │ ├── BigIntegerLibrary.hh │ ├── BigIntegerUtils.cc │ ├── BigIntegerUtils.hh │ ├── BigUnsigned.cc │ ├── BigUnsigned.hh │ ├── BigUnsignedInABase.cc │ ├── BigUnsignedInABase.hh │ ├── ChangeLog │ ├── Makefile │ ├── NumberlikeArray.hh │ ├── README │ ├── run-testsuite │ ├── sample.cc │ └── testsuite.cc ├── ezsat │ ├── .gitignore │ ├── Makefile │ ├── README │ ├── demo_bit.cc │ ├── demo_cmp.cc │ ├── demo_vec.cc │ ├── ezminisat.cc │ ├── ezminisat.h │ ├── ezsat.cc │ ├── ezsat.h │ ├── puzzle3d.cc │ ├── puzzle3d.scad │ └── testbench.cc ├── json11 │ ├── json11.cpp │ └── json11.hpp ├── minisat │ ├── 00_PATCH_mkLit_default_arg.patch │ ├── 00_PATCH_no_fpu_control.patch │ ├── 00_PATCH_remove_zlib.patch │ ├── 00_PATCH_typofixes.patch │ ├── 00_PATCH_wasm.patch │ ├── 00_UPDATE.sh │ ├── Alg.h │ ├── Alloc.h │ ├── Dimacs.h │ ├── Heap.h │ ├── IntMap.h │ ├── IntTypes.h │ ├── LICENSE │ ├── Map.h │ ├── Options.cc │ ├── Options.h │ ├── ParseUtils.h │ ├── Queue.h │ ├── Rnd.h │ ├── SimpSolver.cc │ ├── SimpSolver.h │ ├── Solver.cc │ ├── Solver.h │ ├── SolverTypes.h │ ├── Sort.h │ ├── System.cc │ ├── System.h │ ├── Vec.h │ └── XAlloc.h ├── sha1 │ ├── sha1.cpp │ └── sha1.h └── subcircuit │ ├── .gitignore │ ├── Makefile │ ├── README │ ├── demo.cc │ ├── scshell.cc │ ├── subcircuit.cc │ ├── subcircuit.h │ ├── test_large.spl │ ├── test_macc22.txt │ ├── test_mine.txt │ ├── test_perm.pl │ └── test_shorts.spl ├── manual ├── .gitignore ├── APPNOTE_010_Verilog_to_BLIF.tex ├── APPNOTE_011_Design_Investigation.tex ├── APPNOTE_011_Design_Investigation │ ├── cmos.v │ ├── cmos_00.dot │ ├── cmos_01.dot │ ├── example.v │ ├── example.ys │ ├── example_00.dot │ ├── example_01.dot │ ├── example_02.dot │ ├── example_03.dot │ ├── foobaraddsub.v │ ├── make.sh │ ├── memdemo.v │ ├── memdemo_00.dot │ ├── memdemo_01.dot │ ├── primetest.v │ ├── splice.dot │ ├── splice.v │ ├── submod.ys │ ├── submod_00.dot │ ├── submod_01.dot │ ├── submod_02.dot │ ├── submod_03.dot │ ├── sumprod.v │ ├── sumprod_00.dot │ ├── sumprod_01.dot │ ├── sumprod_02.dot │ ├── sumprod_03.dot │ ├── sumprod_04.dot │ └── sumprod_05.dot ├── APPNOTE_012_Verilog_to_BTOR.tex ├── CHAPTER_Appnotes.tex ├── CHAPTER_Approach.tex ├── CHAPTER_Auxlibs.tex ├── CHAPTER_Auxprogs.tex ├── CHAPTER_Basics.tex ├── CHAPTER_CellLib.tex ├── CHAPTER_Eval.tex ├── CHAPTER_Eval │ ├── grep-it.sh │ ├── openmsp430.prj │ ├── openmsp430_ys.prj │ ├── or1200.prj │ ├── or1200_ys.prj │ ├── run-it.sh │ └── settings.xst ├── CHAPTER_Intro.tex ├── CHAPTER_Optimize.tex ├── CHAPTER_Overview.tex ├── CHAPTER_Prog.tex ├── CHAPTER_Prog │ ├── .gitignore │ ├── Makefile │ ├── stubnets.cc │ └── test.v ├── CHAPTER_StateOfTheArt.tex ├── CHAPTER_StateOfTheArt │ ├── always01.v │ ├── always01_pub.v │ ├── always02.v │ ├── always02_pub.v │ ├── always03.v │ ├── arrays01.v │ ├── cmp_tbdata.c │ ├── forgen01.v │ ├── forgen02.v │ ├── iverilog-0.8.7-buildfixes.patch │ ├── mvsis-1.3.6-buildfixes.patch │ ├── simlib_hana.v │ ├── simlib_icarus.v │ ├── simlib_yosys.v │ ├── sis-1.3.6-buildfixes.patch │ ├── synth.sh │ └── validate_tb.sh ├── CHAPTER_Techmap.tex ├── CHAPTER_Verilog.tex ├── PRESENTATION_ExAdv.tex ├── PRESENTATION_ExAdv │ ├── .gitignore │ ├── Makefile │ ├── addshift_map.v │ ├── addshift_test.v │ ├── addshift_test.ys │ ├── macc_simple_test.v │ ├── macc_simple_test.ys │ ├── macc_simple_test_01.v │ ├── macc_simple_test_02.v │ ├── macc_simple_xmap.v │ ├── macc_xilinx_swap_map.v │ ├── macc_xilinx_test.v │ ├── macc_xilinx_test.ys │ ├── macc_xilinx_unwrap_map.v │ ├── macc_xilinx_wrap_map.v │ ├── macc_xilinx_xmap.v │ ├── mulshift_map.v │ ├── mulshift_test.v │ ├── mulshift_test.ys │ ├── mymul_map.v │ ├── mymul_test.v │ ├── mymul_test.ys │ ├── red_or3x1_cells.v │ ├── red_or3x1_map.v │ ├── red_or3x1_test.v │ ├── red_or3x1_test.ys │ ├── select.v │ ├── select.ys │ ├── sym_mul_cells.v │ ├── sym_mul_map.v │ ├── sym_mul_test.v │ └── sym_mul_test.ys ├── PRESENTATION_ExOth.tex ├── PRESENTATION_ExOth │ ├── .gitignore │ ├── Makefile │ ├── axis_master.v │ ├── axis_test.v │ ├── axis_test.ys │ ├── equiv.ys │ ├── scrambler.v │ └── scrambler.ys ├── PRESENTATION_ExSyn.tex ├── PRESENTATION_ExSyn │ ├── .gitignore │ ├── Makefile │ ├── abc_01.v │ ├── abc_01.ys │ ├── abc_01_cells.lib │ ├── abc_01_cells.v │ ├── memory_01.v │ ├── memory_01.ys │ ├── memory_02.v │ ├── memory_02.ys │ ├── opt_01.v │ ├── opt_01.ys │ ├── opt_02.v │ ├── opt_02.ys │ ├── opt_03.v │ ├── opt_03.ys │ ├── opt_04.v │ ├── opt_04.ys │ ├── proc_01.v │ ├── proc_01.ys │ ├── proc_02.v │ ├── proc_02.ys │ ├── proc_03.v │ ├── proc_03.ys │ ├── techmap_01.v │ ├── techmap_01.ys │ └── techmap_01_map.v ├── PRESENTATION_Intro.tex ├── PRESENTATION_Intro │ ├── .gitignore │ ├── Makefile │ ├── counter.v │ ├── counter.ys │ ├── mycells.lib │ └── mycells.v ├── PRESENTATION_Prog.tex ├── PRESENTATION_Prog │ ├── .gitignore │ ├── Makefile │ ├── absval_ref.v │ ├── my_cmd.cc │ └── sigmap_test.v ├── appnotes.sh ├── clean.sh ├── command-reference-manual.tex ├── literature.bib ├── manual.sh ├── manual.tex ├── presentation.sh ├── presentation.tex └── weblinks.bib ├── misc ├── __init__.py ├── create_vcxsrc.sh ├── launcher.c ├── py_wrap_generator.py ├── yosys-config.in ├── yosys.proto └── yosysjs │ ├── demo01.html │ ├── demo02.html │ ├── demo03.html │ ├── yosysjs.js │ └── yosyswrk.js ├── passes ├── cmds │ ├── Makefile.inc │ ├── add.cc │ ├── autoname.cc │ ├── blackbox.cc │ ├── bugpoint.cc │ ├── check.cc │ ├── chformal.cc │ ├── chtype.cc │ ├── connect.cc │ ├── connwrappers.cc │ ├── copy.cc │ ├── cover.cc │ ├── delete.cc │ ├── design.cc │ ├── edgetypes.cc │ ├── exec.cc │ ├── logcmd.cc │ ├── logger.cc │ ├── ltp.cc │ ├── plugin.cc │ ├── portlist.cc │ ├── printattrs.cc │ ├── qwp.cc │ ├── rename.cc │ ├── scatter.cc │ ├── scc.cc │ ├── scratchpad.cc │ ├── select.cc │ ├── setattr.cc │ ├── setundef.cc │ ├── show.cc │ ├── splice.cc │ ├── splitnets.cc │ ├── stat.cc │ ├── tee.cc │ ├── torder.cc │ ├── trace.cc │ └── write_file.cc ├── equiv │ ├── Makefile.inc │ ├── equiv_add.cc │ ├── equiv_induct.cc │ ├── equiv_make.cc │ ├── equiv_mark.cc │ ├── equiv_miter.cc │ ├── equiv_opt.cc │ ├── equiv_purge.cc │ ├── equiv_remove.cc │ ├── equiv_simple.cc │ ├── equiv_status.cc │ └── equiv_struct.cc ├── fsm │ ├── Makefile.inc │ ├── fsm.cc │ ├── fsm_detect.cc │ ├── fsm_expand.cc │ ├── fsm_export.cc │ ├── fsm_extract.cc │ ├── fsm_info.cc │ ├── fsm_map.cc │ ├── fsm_opt.cc │ ├── fsm_recode.cc │ └── fsmdata.h ├── hierarchy │ ├── Makefile.inc │ ├── hierarchy.cc │ ├── submod.cc │ └── uniquify.cc ├── memory │ ├── Makefile.inc │ ├── memory.cc │ ├── memory_bram.cc │ ├── memory_collect.cc │ ├── memory_dff.cc │ ├── memory_map.cc │ ├── memory_memx.cc │ ├── memory_nordff.cc │ ├── memory_share.cc │ └── memory_unpack.cc ├── opt │ ├── Makefile.inc │ ├── muxpack.cc │ ├── opt.cc │ ├── opt_clean.cc │ ├── opt_demorgan.cc │ ├── opt_dff.cc │ ├── opt_expr.cc │ ├── opt_lut.cc │ ├── opt_lut_ins.cc │ ├── opt_mem.cc │ ├── opt_merge.cc │ ├── opt_muxtree.cc │ ├── opt_reduce.cc │ ├── opt_share.cc │ ├── pmux2shiftx.cc │ ├── rmports.cc │ ├── share.cc │ └── wreduce.cc ├── pmgen │ ├── .gitignore │ ├── Makefile.inc │ ├── README.md │ ├── generate.h │ ├── ice40_dsp.cc │ ├── ice40_dsp.pmg │ ├── ice40_wrapcarry.cc │ ├── ice40_wrapcarry.pmg │ ├── peepopt.cc │ ├── peepopt_muldiv.pmg │ ├── peepopt_shiftmul.pmg │ ├── pmgen.py │ ├── test_pmgen.cc │ ├── test_pmgen.pmg │ ├── xilinx_dsp.cc │ ├── xilinx_dsp.pmg │ ├── xilinx_dsp48a.pmg │ ├── xilinx_dsp_CREG.pmg │ ├── xilinx_dsp_cascade.pmg │ ├── xilinx_srl.cc │ └── xilinx_srl.pmg ├── proc │ ├── Makefile.inc │ ├── proc.cc │ ├── proc_arst.cc │ ├── proc_clean.cc │ ├── proc_dff.cc │ ├── proc_dlatch.cc │ ├── proc_init.cc │ ├── proc_mux.cc │ ├── proc_prune.cc │ └── proc_rmdead.cc ├── sat │ ├── Makefile.inc │ ├── assertpmux.cc │ ├── async2sync.cc │ ├── clk2fflogic.cc │ ├── cutpoint.cc │ ├── eval.cc │ ├── example.v │ ├── example.ys │ ├── expose.cc │ ├── fmcombine.cc │ ├── fminit.cc │ ├── freduce.cc │ ├── miter.cc │ ├── mutate.cc │ ├── qbfsat.cc │ ├── qbfsat.h │ ├── sat.cc │ ├── sim.cc │ └── supercover.cc ├── techmap │ ├── Makefile.inc │ ├── abc.cc │ ├── abc9.cc │ ├── abc9_exe.cc │ ├── abc9_ops.cc │ ├── aigmap.cc │ ├── alumacc.cc │ ├── attrmap.cc │ ├── attrmvcp.cc │ ├── clkbufmap.cc │ ├── deminout.cc │ ├── dffinit.cc │ ├── dfflegalize.cc │ ├── dfflibmap.cc │ ├── dffunmap.cc │ ├── extract.cc │ ├── extract_counter.cc │ ├── extract_fa.cc │ ├── extract_reduce.cc │ ├── extractinv.cc │ ├── filterlib.cc │ ├── flatten.cc │ ├── flowmap.cc │ ├── hilomap.cc │ ├── insbuf.cc │ ├── iopadmap.cc │ ├── libparse.cc │ ├── libparse.h │ ├── lut2mux.cc │ ├── maccmap.cc │ ├── muxcover.cc │ ├── nlutmap.cc │ ├── pmuxtree.cc │ ├── shregmap.cc │ ├── simplemap.cc │ ├── simplemap.h │ ├── techmap.cc │ ├── tribuf.cc │ └── zinit.cc └── tests │ ├── Makefile.inc │ ├── flowmap │ ├── flow.v │ ├── flowp.v │ ├── pack1.v │ ├── pack1p.v │ ├── pack2.v │ ├── pack2p.v │ ├── pack3.v │ └── pack3p.v │ ├── test_abcloop.cc │ ├── test_autotb.cc │ └── test_cell.cc ├── techlibs ├── .gitignore ├── achronix │ ├── Makefile.inc │ ├── speedster22i │ │ ├── cells_arith.v │ │ ├── cells_map.v │ │ └── cells_sim.v │ └── synth_achronix.cc ├── anlogic │ ├── Makefile.inc │ ├── anlogic_eqn.cc │ ├── anlogic_fixcarry.cc │ ├── arith_map.v │ ├── cells_map.v │ ├── cells_sim.v │ ├── eagle_bb.v │ ├── lutram_init_16x4.vh │ ├── lutrams.txt │ ├── lutrams_map.v │ └── synth_anlogic.cc ├── common │ ├── .gitignore │ ├── Makefile.inc │ ├── abc9_map.v │ ├── abc9_model.v │ ├── abc9_unmap.v │ ├── adff2dff.v │ ├── cellhelp.py │ ├── cells.lib │ ├── cmp2lcu.v │ ├── cmp2lut.v │ ├── dff2ff.v │ ├── gate2lut.v │ ├── gen_fine_ffs.py │ ├── mul2dsp.v │ ├── pmux2mux.v │ ├── prep.cc │ ├── simcells.v │ ├── simlib.v │ ├── synth.cc │ └── techmap.v ├── coolrunner2 │ ├── Makefile.inc │ ├── cells_counter_map.v │ ├── cells_latch.v │ ├── cells_sim.v │ ├── coolrunner2_fixup.cc │ ├── coolrunner2_sop.cc │ ├── synth_coolrunner2.cc │ ├── tff_extract.v │ └── xc2_dff.lib ├── easic │ ├── Makefile.inc │ └── synth_easic.cc ├── ecp5 │ ├── .gitignore │ ├── Makefile.inc │ ├── arith_map.v │ ├── brams.txt │ ├── brams_connect.py │ ├── brams_init.py │ ├── brams_map.v │ ├── cells_bb.v │ ├── cells_ff.vh │ ├── cells_io.vh │ ├── cells_map.v │ ├── cells_sim.v │ ├── dsp_map.v │ ├── ecp5_gsr.cc │ ├── latches_map.v │ ├── lutrams.txt │ ├── lutrams_map.v │ ├── synth_ecp5.cc │ └── tests │ │ ├── .gitignore │ │ └── test_diamond_ffs.py ├── efinix │ ├── Makefile.inc │ ├── arith_map.v │ ├── brams.txt │ ├── brams_map.v │ ├── cells_map.v │ ├── cells_sim.v │ ├── efinix_fixcarry.cc │ ├── gbuf_map.v │ └── synth_efinix.cc ├── gowin │ ├── .gitignore │ ├── Makefile.inc │ ├── arith_map.v │ ├── brams.txt │ ├── brams_init.py │ ├── brams_init3.vh │ ├── brams_map.v │ ├── cells_map.v │ ├── cells_sim.v │ ├── lutrams.txt │ ├── lutrams_map.v │ └── synth_gowin.cc ├── greenpak4 │ ├── Makefile.inc │ ├── cells_blackbox.v │ ├── cells_latch.v │ ├── cells_map.v │ ├── cells_sim.v │ ├── cells_sim_ams.v │ ├── cells_sim_digital.v │ ├── cells_sim_wip.v │ ├── gp_dff.lib │ ├── greenpak4_dffinv.cc │ └── synth_greenpak4.cc ├── ice40 │ ├── .gitignore │ ├── Makefile.inc │ ├── abc9_model.v │ ├── arith_map.v │ ├── brams.txt │ ├── brams_init.py │ ├── brams_map.v │ ├── cells_map.v │ ├── cells_sim.v │ ├── dsp_map.v │ ├── ff_map.v │ ├── ice40_braminit.cc │ ├── ice40_opt.cc │ ├── latches_map.v │ ├── synth_ice40.cc │ └── tests │ │ ├── .gitignore │ │ ├── test_arith.v │ │ ├── test_arith.ys │ │ ├── test_bram.sh │ │ ├── test_bram.v │ │ ├── test_bram_tb.v │ │ ├── test_dsp_map.sh │ │ ├── test_dsp_model.sh │ │ ├── test_dsp_model.v │ │ ├── test_ffs.sh │ │ └── test_ffs.v ├── intel │ ├── Makefile.inc │ ├── common │ │ ├── altpll_bb.v │ │ ├── brams_m9k.txt │ │ ├── brams_map_m9k.v │ │ ├── ff_map.v │ │ └── m9k_bb.v │ ├── cyclone10lp │ │ ├── cells_arith.v │ │ ├── cells_map.v │ │ └── cells_sim.v │ ├── cycloneiv │ │ ├── cells_arith.v │ │ ├── cells_map.v │ │ └── cells_sim.v │ ├── cycloneive │ │ ├── arith_map.v │ │ ├── cells_map.v │ │ └── cells_sim.v │ ├── max10 │ │ ├── cells_arith.v │ │ ├── cells_map.v │ │ └── cells_sim.v │ └── synth_intel.cc ├── intel_alm │ ├── Makefile.inc │ ├── common │ │ ├── abc9_map.v │ │ ├── abc9_model.v │ │ ├── abc9_unmap.v │ │ ├── alm_map.v │ │ ├── alm_sim.v │ │ ├── arith_alm_map.v │ │ ├── bram_m10k.txt │ │ ├── bram_m20k.txt │ │ ├── bram_m20k_map.v │ │ ├── dff_map.v │ │ ├── dff_sim.v │ │ ├── dsp_map.v │ │ ├── dsp_sim.v │ │ ├── lutram_mlab.txt │ │ ├── megafunction_bb.v │ │ ├── mem_sim.v │ │ └── quartus_rename.v │ ├── cyclonev │ │ └── cells_sim.v │ └── synth_intel_alm.cc ├── nexus │ ├── Makefile.inc │ ├── arith_map.v │ ├── brams.txt │ ├── brams_init.vh │ ├── brams_map.v │ ├── cells_map.v │ ├── cells_sim.v │ ├── cells_xtra.py │ ├── cells_xtra.v │ ├── dsp_map.v │ ├── latches_map.v │ ├── lutrams.txt │ ├── lutrams_map.v │ ├── parse_init.vh │ └── synth_nexus.cc ├── sf2 │ ├── Makefile.inc │ ├── arith_map.v │ ├── cells_map.v │ ├── cells_sim.v │ └── synth_sf2.cc └── xilinx │ ├── .gitignore │ ├── Makefile.inc │ ├── abc9_model.v │ ├── arith_map.v │ ├── brams_init.py │ ├── cells_map.v │ ├── cells_sim.v │ ├── cells_xtra.py │ ├── cells_xtra.v │ ├── ff_map.v │ ├── lut4_lutrams.txt │ ├── lut6_lutrams.txt │ ├── lut_map.v │ ├── lutrams_map.v │ ├── mux_map.v │ ├── synth_xilinx.cc │ ├── tests │ ├── .gitignore │ ├── bram1.sh │ ├── bram1.v │ ├── bram1_tb.v │ ├── bram2.sh │ ├── bram2.v │ ├── bram2_tb.v │ ├── test_dsp48_model.sh │ ├── test_dsp48_model.v │ ├── test_dsp48a1_model.sh │ ├── test_dsp48a1_model.v │ ├── test_dsp_model.sh │ └── test_dsp_model.v │ ├── xc2v_brams.txt │ ├── xc2v_brams_map.v │ ├── xc3s_mult_map.v │ ├── xc3sa_brams.txt │ ├── xc3sda_brams.txt │ ├── xc3sda_dsp_map.v │ ├── xc4v_dsp_map.v │ ├── xc5v_dsp_map.v │ ├── xc6s_brams.txt │ ├── xc6s_brams_map.v │ ├── xc6s_dsp_map.v │ ├── xc7_brams_map.v │ ├── xc7_dsp_map.v │ ├── xc7_xcu_brams.txt │ ├── xcu_brams_map.v │ ├── xcu_dsp_map.v │ ├── xcup_urams.txt │ ├── xcup_urams_map.v │ └── xilinx_dffopt.cc └── tests ├── aiger ├── .gitignore ├── and_.aag ├── and_.aig ├── buffer.aag ├── buffer.aig ├── cnt1.aag ├── cnt1.aig ├── cnt1e.aag ├── cnt1e.aig ├── empty.aag ├── empty.aig ├── false.aag ├── false.aig ├── halfadder.aag ├── halfadder.aig ├── inverter.aag ├── inverter.aig ├── neg.ys ├── notcnt1.aag ├── notcnt1.aig ├── notcnt1e.aag ├── notcnt1e.aig ├── or_.aag ├── or_.aig ├── run-test.sh ├── symbols.aag ├── symbols.aig ├── toggle-re.aag ├── toggle-re.aig ├── toggle.aag ├── toggle.aig ├── true.aag └── true.aig ├── arch ├── anlogic │ ├── .gitignore │ ├── add_sub.ys │ ├── counter.ys │ ├── dffs.ys │ ├── fsm.ys │ ├── latches.ys │ ├── logic.ys │ ├── lutram.ys │ ├── mux.ys │ ├── run-test.sh │ ├── shifter.ys │ └── tribuf.ys ├── common │ ├── add_sub.v │ ├── adffs.v │ ├── blockram.v │ ├── blockrom.v │ ├── counter.v │ ├── dffs.v │ ├── fsm.v │ ├── latches.v │ ├── logic.v │ ├── lutram.v │ ├── memory_attributes │ │ └── attributes_test.v │ ├── mul.v │ ├── mux.v │ ├── shifter.v │ └── tribuf.v ├── ecp5 │ ├── .gitignore │ ├── add_sub.ys │ ├── adffs.ys │ ├── bug1459.ys │ ├── bug1598.ys │ ├── bug1630.il.gz │ ├── bug1630.ys │ ├── bug2409.ys │ ├── counter.ys │ ├── dffs.ys │ ├── dpram.v │ ├── dpram.ys │ ├── fsm.ys │ ├── latches.ys │ ├── latches_abc9.ys │ ├── logic.ys │ ├── lutram.ys │ ├── macc.v │ ├── macc.ys │ ├── memories.ys │ ├── mul.ys │ ├── mux.ys │ ├── opt_lut_ins.ys │ ├── rom.v │ ├── rom.ys │ ├── run-test.sh │ ├── shifter.ys │ └── tribuf.ys ├── efinix │ ├── .gitignore │ ├── add_sub.ys │ ├── adffs.ys │ ├── counter.ys │ ├── dffs.ys │ ├── fsm.ys │ ├── latches.ys │ ├── logic.ys │ ├── lutram.ys │ ├── mux.ys │ ├── run-test.sh │ ├── shifter.ys │ └── tribuf.ys ├── gowin │ ├── .gitignore │ ├── add_sub.ys │ ├── adffs.ys │ ├── counter.ys │ ├── dffs.ys │ ├── fsm.ys │ ├── init-error.ys │ ├── init.v │ ├── init.ys │ ├── logic.ys │ ├── lutram.ys │ ├── mux.ys │ ├── run-test.sh │ ├── shifter.ys │ └── tribuf.ys ├── ice40 │ ├── .gitignore │ ├── add_sub.ys │ ├── adffs.ys │ ├── bug1597.ys │ ├── bug1598.ys │ ├── bug1626.ys │ ├── bug1644.il.gz │ ├── bug1644.ys │ ├── counter.ys │ ├── dffs.ys │ ├── dpram.v │ ├── dpram.ys │ ├── fsm.ys │ ├── ice40_dsp.ys │ ├── ice40_opt.ys │ ├── ice40_wrapcarry.ys │ ├── latches.ys │ ├── logic.ys │ ├── macc.v │ ├── macc.ys │ ├── memories.ys │ ├── mul.ys │ ├── mux.ys │ ├── rom.v │ ├── rom.ys │ ├── run-test.sh │ ├── shifter.ys │ └── tribuf.ys ├── intel_alm │ ├── .gitignore │ ├── add_sub.ys │ ├── adffs.ys │ ├── blockram.ys │ ├── counter.ys │ ├── dffs.ys │ ├── fsm.ys │ ├── logic.ys │ ├── lutram.ys │ ├── mul.ys │ ├── mux.ys │ ├── quartus_ice.ys │ ├── run-test.sh │ ├── shifter.ys │ └── tribuf.ys ├── nexus │ ├── .gitignore │ ├── add_sub.ys │ ├── adffs.ys │ ├── blockram.ys │ ├── blockram_dc.v │ ├── counter.ys │ ├── dffs.ys │ ├── fsm.ys │ ├── logic.ys │ ├── lutram.ys │ ├── mul.ys │ ├── mux.ys │ ├── run-test.sh │ ├── shifter.ys │ └── tribuf.ys ├── run-test.sh └── xilinx │ ├── .gitignore │ ├── abc9_dff.ys │ ├── add_sub.ys │ ├── adffs.ys │ ├── attributes_test.ys │ ├── blockram.ys │ ├── bug1460.ys │ ├── bug1462.ys │ ├── bug1480.ys │ ├── bug1598.ys │ ├── bug1605.ys │ ├── counter.ys │ ├── dffs.ys │ ├── dsp_abc9.ys │ ├── dsp_cascade.ys │ ├── dsp_fastfir.ys │ ├── dsp_simd.ys │ ├── fsm.ys │ ├── latches.ys │ ├── logic.ys │ ├── lutram.ys │ ├── macc.sh │ ├── macc.v │ ├── macc.ys │ ├── macc_tb.v │ ├── mul.ys │ ├── mul_unsigned.v │ ├── mul_unsigned.ys │ ├── mux.ys │ ├── mux_lut4.ys │ ├── nosrl.ys │ ├── opt_lut_ins.ys │ ├── pmgen_xilinx_srl.ys │ ├── run-test.sh │ ├── shifter.ys │ ├── tribuf.sh │ ├── tribuf.ys │ ├── xilinx_dffopt.ys │ ├── xilinx_dffopt_blacklist.txt │ ├── xilinx_dsp.ys │ ├── xilinx_srl.v │ └── xilinx_srl.ys ├── asicworld ├── .gitignore ├── README ├── code_hdl_models_GrayCounter.v ├── code_hdl_models_arbiter.v ├── code_hdl_models_arbiter_tb.v ├── code_hdl_models_cam.v ├── code_hdl_models_clk_div.v ├── code_hdl_models_clk_div_45.v ├── code_hdl_models_d_ff_gates.v ├── code_hdl_models_d_latch_gates.v ├── code_hdl_models_decoder_2to4_gates.v ├── code_hdl_models_decoder_using_assign.v ├── code_hdl_models_decoder_using_case.v ├── code_hdl_models_dff_async_reset.v ├── code_hdl_models_dff_sync_reset.v ├── code_hdl_models_encoder_4to2_gates.v ├── code_hdl_models_encoder_using_case.v ├── code_hdl_models_encoder_using_if.v ├── code_hdl_models_full_adder_gates.v ├── code_hdl_models_full_subtracter_gates.v ├── code_hdl_models_gray_counter.v ├── code_hdl_models_half_adder_gates.v ├── code_hdl_models_lfsr.v ├── code_hdl_models_lfsr_updown.v ├── code_hdl_models_mux_2to1_gates.v ├── code_hdl_models_mux_using_assign.v ├── code_hdl_models_mux_using_case.v ├── code_hdl_models_mux_using_if.v ├── code_hdl_models_one_hot_cnt.v ├── code_hdl_models_parallel_crc.v ├── code_hdl_models_parity_using_assign.v ├── code_hdl_models_parity_using_bitwise.v ├── code_hdl_models_parity_using_function.v ├── code_hdl_models_pri_encoder_using_assign.v ├── code_hdl_models_rom_using_case.v ├── code_hdl_models_serial_crc.v ├── code_hdl_models_tff_async_reset.v ├── code_hdl_models_tff_sync_reset.v ├── code_hdl_models_uart.v ├── code_hdl_models_up_counter.v ├── code_hdl_models_up_counter_load.v ├── code_hdl_models_up_down_counter.v ├── code_specman_switch_fabric.v ├── code_tidbits_asyn_reset.v ├── code_tidbits_blocking.v ├── code_tidbits_fsm_using_always.v ├── code_tidbits_fsm_using_function.v ├── code_tidbits_fsm_using_single_always.v ├── code_tidbits_nonblocking.v ├── code_tidbits_reg_combo_example.v ├── code_tidbits_reg_seq_example.v ├── code_tidbits_syn_reset.v ├── code_tidbits_wire_example.v ├── code_verilog_tutorial_addbit.v ├── code_verilog_tutorial_always_example.v ├── code_verilog_tutorial_bus_con.v ├── code_verilog_tutorial_comment.v ├── code_verilog_tutorial_counter.v ├── code_verilog_tutorial_counter_tb.v ├── code_verilog_tutorial_d_ff.v ├── code_verilog_tutorial_decoder.v ├── code_verilog_tutorial_decoder_always.v ├── code_verilog_tutorial_escape_id.v ├── code_verilog_tutorial_explicit.v ├── code_verilog_tutorial_first_counter.v ├── code_verilog_tutorial_first_counter_tb.v ├── code_verilog_tutorial_flip_flop.v ├── code_verilog_tutorial_fsm_full.v ├── code_verilog_tutorial_fsm_full_tb.v ├── code_verilog_tutorial_good_code.v ├── code_verilog_tutorial_if_else.v ├── code_verilog_tutorial_multiply.v ├── code_verilog_tutorial_mux_21.v ├── code_verilog_tutorial_n_out_primitive.v ├── code_verilog_tutorial_parallel_if.v ├── code_verilog_tutorial_parity.v ├── code_verilog_tutorial_simple_function.v ├── code_verilog_tutorial_simple_if.v ├── code_verilog_tutorial_task_global.v ├── code_verilog_tutorial_tri_buf.v ├── code_verilog_tutorial_v2k_reg.v ├── code_verilog_tutorial_which_clock.v ├── run-test.sh └── xfirrtl ├── bram ├── .gitignore ├── generate.py ├── run-single.sh └── run-test.sh ├── errors ├── syntax_err01.v ├── syntax_err02.v ├── syntax_err03.v ├── syntax_err04.v ├── syntax_err05.v ├── syntax_err06.v ├── syntax_err07.v ├── syntax_err08.v ├── syntax_err09.v ├── syntax_err10.v ├── syntax_err11.v ├── syntax_err12.v └── syntax_err13.v ├── fsm ├── .gitignore ├── generate.py └── run-test.sh ├── gen-tests-makefile.sh ├── hana ├── .gitignore ├── README ├── hana_vlib.v ├── run-test.sh ├── test_intermout.v ├── test_parse2synthtrans.v ├── test_parser.v ├── test_simulation_always.v ├── test_simulation_and.v ├── test_simulation_buffer.v ├── test_simulation_decoder.v ├── test_simulation_inc.v ├── test_simulation_mux.v ├── test_simulation_nand.v ├── test_simulation_nor.v ├── test_simulation_or.v ├── test_simulation_seq.v ├── test_simulation_shifter.v ├── test_simulation_sop.v ├── test_simulation_techmap.v ├── test_simulation_techmap_tech.v ├── test_simulation_vlib.v ├── test_simulation_xnor.v └── test_simulation_xor.v ├── liberty ├── .gitignore ├── busdef.lib ├── normal.lib ├── processdefs.lib ├── run-test.sh ├── semicolextra.lib ├── semicolmissing.lib └── small.v ├── lut ├── .gitignore ├── check_map.ys ├── check_map_lut6.ys ├── map_and.v ├── map_cmp.v ├── map_mux.v ├── map_not.v ├── map_or.v ├── map_xor.v └── run-test.sh ├── memfile ├── .gitignore ├── content1.dat ├── memory.v └── run-test.sh ├── memories ├── .gitignore ├── amber23_sram_byte_en.v ├── firrtl_938.v ├── implicit_en.v ├── issue00335.v ├── issue00710.v ├── no_implicit_en.v ├── read_two_mux.v ├── run-test.sh ├── shared_ports.v └── simple_sram_byte_en.v ├── opt ├── .gitignore ├── bug1525.ys ├── bug1758.ys ├── bug2010.ys ├── bug2221.ys ├── bug2311.ys ├── bug2318.ys ├── opt_clean_init.ys ├── opt_clean_mem.ys ├── opt_dff_arst.ys ├── opt_dff_clk.ys ├── opt_dff_const.ys ├── opt_dff_dffmux.ys ├── opt_dff_en.ys ├── opt_dff_mux.ys ├── opt_dff_qd.ys ├── opt_dff_sr.ys ├── opt_dff_srst.ys ├── opt_expr.ys ├── opt_expr_alu.ys ├── opt_expr_and.ys ├── opt_expr_cmp.v ├── opt_expr_cmp.ys ├── opt_expr_combined_assign.ys ├── opt_expr_consumex.ys ├── opt_expr_or.ys ├── opt_expr_xnor.ys ├── opt_expr_xor.ys ├── opt_lut.v ├── opt_lut.ys ├── opt_lut_elim.il ├── opt_lut_elim.ys ├── opt_lut_ins.ys ├── opt_lut_port.il ├── opt_lut_port.ys ├── opt_merge_init.ys ├── opt_merge_keep.ys ├── opt_rmdff.v ├── opt_rmdff.ys ├── opt_rmdff_sat.v ├── opt_rmdff_sat.ys ├── opt_share_add_sub.v ├── opt_share_add_sub.ys ├── opt_share_bug2334.ys ├── opt_share_bug2335.ys ├── opt_share_bug2336.ys ├── opt_share_cat.v ├── opt_share_cat.ys ├── opt_share_cat_multiuser.v ├── opt_share_cat_multiuser.ys ├── opt_share_diff_port_widths.v ├── opt_share_diff_port_widths.ys ├── opt_share_extend.v ├── opt_share_extend.ys ├── opt_share_large_pmux_cat.v ├── opt_share_large_pmux_cat.ys ├── opt_share_large_pmux_cat_multipart.v ├── opt_share_large_pmux_cat_multipart.ys ├── opt_share_large_pmux_multipart.v ├── opt_share_large_pmux_multipart.ys ├── opt_share_large_pmux_part.v ├── opt_share_large_pmux_part.ys ├── opt_share_mux_tree.v ├── opt_share_mux_tree.ys └── run-test.sh ├── opt_share ├── .gitignore ├── generate.py └── run-test.sh ├── proc ├── .gitignore ├── bug_1268.v ├── bug_1268.ys └── run-test.sh ├── realmath ├── .gitignore ├── generate.py └── run-test.sh ├── rpc ├── .gitignore ├── design.v ├── exec.ys ├── frontend.py └── run-test.sh ├── sat ├── .gitignore ├── asserts.v ├── asserts.ys ├── asserts_seq.v ├── asserts_seq.ys ├── clk2fflogic.ys ├── counters-repeat.v ├── counters-repeat.ys ├── counters.v ├── counters.ys ├── dff.ys ├── expose_dff.v ├── expose_dff.ys ├── initval.v ├── initval.ys ├── run-test.sh ├── share.v ├── share.ys ├── sizebits.sv ├── sizebits.ys ├── splice.v └── splice.ys ├── select ├── .gitignore ├── blackboxes.ys ├── no_warn_assert.ys ├── no_warn_prefixed_arg_memb.ys ├── no_warn_prefixed_empty_select_arg.ys ├── run-test.sh ├── unset.ys ├── unset2.ys └── warn_empty_select_arg.ys ├── share ├── .gitignore ├── generate.py └── run-test.sh ├── simple ├── .gitignore ├── aes_kexp128.v ├── always01.v ├── always02.v ├── always03.v ├── arraycells.v ├── arrays01.v ├── arrays02.sv ├── attrib01_module.v ├── attrib02_port_decl.v ├── attrib03_parameter.v ├── attrib04_net_var.v ├── attrib05_port_conn.v.DISABLED ├── attrib06_operator_suffix.v ├── attrib07_func_call.v.DISABLED ├── attrib08_mod_inst.v ├── attrib09_case.v ├── carryadd.v ├── const_branch_finish.v ├── constmuldivmod.v ├── constpower.v ├── defvalue.sv ├── dff_different_styles.v ├── dff_init.v ├── dynslice.v ├── fiedler-cooley.v ├── forgen01.v ├── forgen02.v ├── forloops.v ├── fsm.v ├── generate.v ├── graphtest.v ├── hierarchy.v ├── hierdefparam.v ├── i2c_master_tests.v ├── implicit_ports.v ├── localparam_attr.v ├── loops.v ├── macros.v ├── mem2reg.v ├── mem_arst.v ├── memory.v ├── multiplier.v ├── muxtree.v ├── omsp_dbg_uart.v ├── operators.v ├── param_attr.v ├── paramods.v ├── partsel.v ├── process.v ├── realexpr.v ├── repwhile.v ├── retime.v ├── rotate.v ├── run-test.sh ├── scopes.v ├── signedexpr.v ├── sincos.v ├── specify.v ├── string_format.v ├── subbytes.v ├── task_func.v ├── undef_eqx_nex.v ├── usb_phy_tests.v ├── values.v ├── vloghammer.v ├── wandwor.v ├── wreduce.v └── xfirrtl ├── simple_abc9 ├── .gitignore ├── abc9.box ├── abc9.v └── run-test.sh ├── smv ├── .gitignore ├── run-single.sh └── run-test.sh ├── sva ├── .gitignore ├── Makefile ├── basic00.sv ├── basic01.sv ├── basic02.sv ├── basic03.sv ├── basic04.sv ├── basic04.vhd ├── basic05.sv ├── basic05.vhd ├── counter.sv ├── extnets.sv ├── runtest.sh ├── sva_not.sv ├── sva_range.sv └── sva_throughout.sv ├── svinterfaces ├── .gitignore ├── run-test.sh ├── runone.sh ├── svinterface1.sv ├── svinterface1_ref.v ├── svinterface1_tb.v ├── svinterface_at_top.sv ├── svinterface_at_top_ref.v ├── svinterface_at_top_tb.v ├── svinterface_at_top_tb_wrapper.v └── svinterface_at_top_wrapper.v ├── svtypes ├── .gitignore ├── enum_simple.sv ├── enum_simple.ys ├── logic_rom.sv ├── logic_rom.ys ├── multirange_array.sv ├── multirange_subarray_access.ys ├── run-test.sh ├── static_cast_negative.ys ├── static_cast_nonconst.ys ├── static_cast_simple.sv ├── static_cast_verilog.ys ├── static_cast_zero.ys ├── struct_array.sv ├── struct_simple.sv ├── typedef_memory.sv ├── typedef_memory.ys ├── typedef_memory_2.sv ├── typedef_memory_2.ys ├── typedef_package.sv ├── typedef_param.sv ├── typedef_scopes.sv ├── typedef_simple.sv ├── typedef_struct.sv └── union_simple.sv ├── techmap ├── .gitignore ├── abc9.ys ├── aigmap.ys ├── autopurge.ys ├── bug2183.ys ├── bug2321.ys ├── bug2332.ys ├── cellname.ys ├── clkbufmap.ys ├── cmp2lcu.ys ├── dffinit.ys ├── dfflegalize_adff.ys ├── dfflegalize_adff_init.ys ├── dfflegalize_adlatch.ys ├── dfflegalize_adlatch_init.ys ├── dfflegalize_dff.ys ├── dfflegalize_dff_init.ys ├── dfflegalize_dffsr.ys ├── dfflegalize_dffsr_init.ys ├── dfflegalize_dlatch.ys ├── dfflegalize_dlatch_const.ys ├── dfflegalize_dlatch_init.ys ├── dfflegalize_dlatchsr.ys ├── dfflegalize_dlatchsr_init.ys ├── dfflegalize_inv.ys ├── dfflegalize_mince.ys ├── dfflegalize_minsrst.ys ├── dfflegalize_sr.ys ├── dfflegalize_sr_init.ys ├── dfflibmap-sim.v ├── dfflibmap.lib ├── dfflibmap.ys ├── dffunmap.ys ├── extractinv.ys ├── iopadmap.ys ├── mem_simple_4x1_cells.v ├── mem_simple_4x1_map.v ├── mem_simple_4x1_runtest.sh ├── mem_simple_4x1_tb.v ├── mem_simple_4x1_uut.v ├── recursive.v ├── recursive_map.v ├── recursive_runtest.sh ├── run-test.sh ├── shiftx2mux.ys ├── techmap_replace.ys ├── wireinit.ys └── zinit.ys ├── tools ├── .gitignore ├── autotest.mk ├── autotest.sh ├── cmp_tbdata.c ├── profiler.pl ├── txt2tikztiming.py ├── vcd2txt.pl └── vcdcd.pl ├── unit ├── Makefile └── kernel │ ├── logTest.cc │ └── rtlilTest.cc ├── various ├── .gitignore ├── abc9.v ├── abc9.ys ├── async.sh ├── async.v ├── attrib05_port_conn.v ├── attrib05_port_conn.ys ├── attrib07_func_call.v ├── attrib07_func_call.ys ├── autoname.ys ├── bug1496.ys ├── bug1531.ys ├── bug1614.ys ├── bug1710.ys ├── bug1745.ys ├── bug1781.ys ├── bug1876.ys ├── bug2014.ys ├── chparam.sh ├── const_arg_loop.v ├── const_arg_loop.ys ├── const_func.v ├── const_func.ys ├── const_func_block_var.v ├── const_func_block_var.ys ├── constcomment.ys ├── constmsk_test.v ├── constmsk_test.ys ├── constmsk_testmap.v ├── deminout_unused.ys ├── design.ys ├── design1.ys ├── design2.ys ├── dynamic_part_select.ys ├── dynamic_part_select │ ├── forloop_select.v │ ├── forloop_select_gate.v │ ├── multiple_blocking.v │ ├── multiple_blocking_gate.v │ ├── nonblocking.v │ ├── nonblocking_gate.v │ ├── original.v │ ├── original_gate.v │ ├── reset_test.v │ ├── reset_test_gate.v │ ├── reversed.v │ └── reversed_gate.v ├── elab_sys_tasks.sv ├── elab_sys_tasks.ys ├── equiv_opt_multiclock.ys ├── equiv_opt_undef.ys ├── exec.ys ├── gen_if_null.v ├── gen_if_null.ys ├── global_scope.ys ├── gzip_verilog.v.gz ├── gzip_verilog.ys ├── help.ys ├── hierarchy.sh ├── hierarchy_defer.ys ├── hierarchy_param.ys ├── ice40_mince_abc9.ys ├── integer_range_bad_syntax.ys ├── integer_real_bad_syntax.ys ├── logger_error.ys ├── logger_nowarning.ys ├── logger_warn.ys ├── logger_warning.ys ├── logic_param_simple.ys ├── mem2reg.ys ├── muxcover.ys ├── muxpack.v ├── muxpack.ys ├── peepopt.ys ├── plugin.cc ├── plugin.sh ├── pmgen_reduce.ys ├── pmux2shiftx.v ├── pmux2shiftx.ys ├── primitives.ys ├── printattr.ys ├── reg_wire_error.sv ├── reg_wire_error.ys ├── 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