├── .gitignore ├── COPYING ├── CodeOfConduct ├── README.md ├── checks ├── genchecks.py ├── rvfi_causal_check.sv ├── rvfi_channel.sv ├── rvfi_cover_check.sv ├── rvfi_csrw_check.sv ├── rvfi_dmem_check.sv ├── rvfi_hang_check.sv ├── rvfi_ill_check.sv ├── rvfi_imem_check.sv ├── rvfi_insn_check.sv ├── rvfi_liveness_check.sv ├── rvfi_macros.py ├── rvfi_macros.vh ├── rvfi_pc_bwd_check.sv ├── rvfi_pc_fwd_check.sv ├── rvfi_reg_check.sv ├── rvfi_testbench.sv └── rvfi_unique_check.sv ├── cores ├── VexRiscv │ ├── .gitignore │ ├── README.md │ ├── VexRiscv.v │ ├── checks.cfg │ ├── disasm.py │ ├── dmemcheck.sby │ ├── dmemcheck.sv │ ├── imemcheck.sby │ ├── imemcheck.sv │ └── wrapper.sv ├── picorv32 │ ├── .gitignore │ ├── README.md │ ├── cexdata.sh │ ├── checks.cfg │ ├── checks.gtkw │ ├── complete.sby │ ├── complete.sv │ ├── cover.sby │ ├── cover.sv │ ├── disasm.py │ ├── dmemcheck.sv │ ├── equiv.sh │ ├── honest.sby │ ├── honest.sv │ ├── imemcheck.sv │ ├── testbugs.sh │ └── wrapper.sv ├── rocket │ ├── .gitignore │ ├── README.md │ ├── cexdata.sh │ ├── checks.gtkw │ ├── cover.gtkw │ ├── cover.sby │ ├── cover.sv │ ├── coverage.sby │ ├── coverage.sv │ ├── decode.sh │ ├── disasm.py │ ├── generate.sh │ ├── muldivlen.py │ ├── muldivlen.sby │ ├── muldivlen.sv │ ├── rocketrvfi.sv │ ├── testbench.cc │ ├── testbench.sh │ └── wrapper.sv └── serv │ ├── .gitignore │ ├── README.md │ ├── cexdata.sh │ ├── checks.cfg │ ├── cover.gtkw │ ├── cover.sby │ ├── cover.sv │ ├── disasm.py │ ├── generate.sh │ ├── sbram.sv │ └── wrapper.sv ├── docs ├── config.md ├── csrs.md ├── examplebugs.md ├── procedure.md ├── quickstart.md ├── references.md └── rvfi.md ├── insns ├── generate.py ├── insn_add.v ├── insn_addi.v ├── insn_addiw.v ├── insn_addw.v ├── insn_and.v ├── insn_andi.v ├── insn_auipc.v ├── insn_beq.v ├── insn_bge.v ├── insn_bgeu.v ├── insn_blt.v ├── insn_bltu.v ├── insn_bne.v ├── insn_c_add.v ├── insn_c_addi.v ├── insn_c_addi16sp.v ├── insn_c_addi4spn.v ├── insn_c_addiw.v ├── insn_c_addw.v ├── insn_c_and.v ├── insn_c_andi.v ├── insn_c_beqz.v ├── insn_c_bnez.v ├── insn_c_j.v ├── insn_c_jal.v ├── insn_c_jalr.v ├── insn_c_jr.v ├── insn_c_ld.v ├── insn_c_ldsp.v ├── insn_c_li.v ├── insn_c_lui.v ├── insn_c_lw.v ├── insn_c_lwsp.v ├── insn_c_mv.v ├── insn_c_or.v ├── insn_c_sd.v ├── insn_c_sdsp.v ├── insn_c_slli.v ├── insn_c_srai.v ├── insn_c_srli.v ├── insn_c_sub.v ├── insn_c_subw.v ├── insn_c_sw.v ├── insn_c_swsp.v ├── insn_c_xor.v ├── insn_div.v ├── insn_divu.v ├── insn_divuw.v ├── insn_divw.v ├── insn_jal.v ├── insn_jalr.v ├── insn_lb.v ├── insn_lbu.v ├── insn_ld.v ├── insn_lh.v ├── insn_lhu.v ├── insn_lui.v ├── insn_lw.v ├── insn_lwu.v ├── insn_mul.v ├── insn_mulh.v ├── insn_mulhsu.v ├── insn_mulhu.v ├── insn_mulw.v ├── insn_or.v ├── insn_ori.v ├── insn_rem.v ├── insn_remu.v ├── insn_remuw.v ├── insn_remw.v ├── insn_sb.v ├── insn_sd.v ├── insn_sh.v ├── insn_sll.v ├── insn_slli.v ├── insn_slliw.v ├── insn_sllw.v ├── insn_slt.v ├── insn_slti.v ├── insn_sltiu.v ├── insn_sltu.v ├── insn_sra.v ├── insn_srai.v ├── insn_sraiw.v ├── insn_sraw.v ├── insn_srl.v ├── insn_srli.v ├── insn_srliw.v ├── insn_srlw.v ├── insn_sub.v ├── insn_subw.v ├── insn_sw.v ├── insn_xor.v ├── insn_xori.v ├── isa_rv32i.txt ├── isa_rv32i.v ├── isa_rv32ic.txt ├── isa_rv32ic.v ├── isa_rv32im.txt ├── isa_rv32im.v ├── isa_rv32imc.txt ├── isa_rv32imc.v ├── isa_rv64i.txt ├── isa_rv64i.v ├── isa_rv64ic.txt ├── isa_rv64ic.v ├── isa_rv64im.txt ├── isa_rv64im.v ├── isa_rv64imc.txt └── isa_rv64imc.v ├── monitor └── generate.py └── tests ├── coverage ├── .gitignore ├── coverage.sby ├── coverage.sv ├── generate.py ├── riscv_rv32i_insn.v ├── riscv_rv32ic_insn.v ├── riscv_rv64i_insn.v └── riscv_rv64ic_insn.v ├── semantics ├── .gitignore ├── Makefile ├── cexformat.py ├── makejob.py └── top.sv └── spike ├── .gitignore ├── common.h └── generate.py /.gitignore: -------------------------------------------------------------------------------- 1 | /cores/.gitignore 2 | -------------------------------------------------------------------------------- /COPYING: -------------------------------------------------------------------------------- 1 | Copyright (C) 2017 Clifford Wolf 2 | 3 | Permission to use, copy, modify, and/or distribute this software for any 4 | purpose with or without fee is hereby granted, provided that the above 5 | copyright notice and this permission notice appear in all copies. 6 | 7 | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 8 | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 9 | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 10 | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 11 | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 12 | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 13 | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 14 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | 2 | RISC-V Formal Verification Framework 3 | ==================================== 4 | 5 | **This is work in progress. The interfaces described here are likely to change as the project matures.** 6 | 7 | About 8 | ----- 9 | 10 | `riscv-formal` is a framework for formal verification of RISC-V processors. 11 | 12 | It consists of the following components: 13 | - A processor-independent formal description of the RISC-V ISA 14 | - A set of formal testbenches for each processor supported by the framework 15 | - The specification for the [RISC-V Formal Interface (RVFI)](docs/rvfi.md) that must be implemented by a processor core to interface with `riscv-formal`. 16 | - Some auxiliary proofs and scripts, for example to prove correctness of the ISA spec agains riscv-isa-sim. 17 | 18 | See [cores/picorv32/](cores/picorv32/) for example bindings for the PicoRV32 processor core. 19 | 20 | A processor core usually will implement RVFI as an optional feature that is only enabled for verification. Sequential equivalence check can be used to prove equivalence of the processor versions with and without RVFI. 21 | 22 | The current focus is on implementing formal models of all instructions from the RISC-V RV32I and RV64I ISAs, and formally verifying those models against the models used in the RISC-V "Spike" ISA simulator. 23 | 24 | `riscv-formal` uses the FOSS SymbiYosys formal verification flow. All properties are expressed using immediate assertions/assumptions for maximal compatibility with other tools. 25 | 26 | Table of contents 27 | ----------------- 28 | 29 | - [Quickstart Guide](docs/quickstart.md) 30 | - [The RVFI Interface Specification](docs/rvfi.md) 31 | - [RISC-V Formal CSR Sematics](docs/csrs.md) 32 | - [Configuration macros used by riscv-formal](docs/config.md) 33 | - [The riscv-formal Verification Procedure](docs/procedure.md) 34 | - [Examples of bugs found with riscv-formal](docs/examplebugs.md) 35 | - [References and related work](docs/references.md) 36 | 37 | See also [this presentation slides](http://www.clifford.at/papers/2017/riscv-formal/) for an introduction to riscv-formal. 38 | 39 | -------------------------------------------------------------------------------- /checks/rvfi_causal_check.sv: -------------------------------------------------------------------------------- 1 | // Copyright (C) 2017 Clifford Wolf 2 | // 3 | // Permission to use, copy, modify, and/or distribute this software for any 4 | // purpose with or without fee is hereby granted, provided that the above 5 | // copyright notice and this permission notice appear in all copies. 6 | // 7 | // THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 8 | // WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 9 | // MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 10 | // ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 11 | // WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 12 | // ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 13 | // OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 14 | 15 | module rvfi_causal_check ( 16 | input clock, reset, check, 17 | `RVFI_INPUTS 18 | ); 19 | `rvformal_const_rand_reg [63:0] insn_order; 20 | `rvformal_const_rand_reg [4:0] register_index; 21 | reg found_non_causal = 0; 22 | 23 | integer channel_idx; 24 | always @(posedge clock) begin 25 | if (reset) begin 26 | found_non_causal = 0; 27 | end else begin 28 | if (check) begin 29 | for (channel_idx = 0; channel_idx < `RISCV_FORMAL_CHANNEL_IDX; channel_idx=channel_idx+1) begin 30 | if (rvfi_valid[channel_idx] && rvfi_order[64*channel_idx +: 64] > insn_order && 31 | (register_index == rvfi_rs1_addr[channel_idx*5 +: 5] || 32 | register_index == rvfi_rs2_addr[channel_idx*5 +: 5])) begin 33 | found_non_causal = 1; 34 | end 35 | end 36 | assume(register_index != 0); 37 | assume(rvfi_valid[`RISCV_FORMAL_CHANNEL_IDX]); 38 | assume((register_index == rvfi_rd_addr[`RISCV_FORMAL_CHANNEL_IDX*5 +: 5])); 39 | assume(insn_order == rvfi_order[64*`RISCV_FORMAL_CHANNEL_IDX +: 64]); 40 | assert(!found_non_causal); 41 | end else begin 42 | for (channel_idx = 0; channel_idx < `RISCV_FORMAL_NRET; channel_idx=channel_idx+1) begin 43 | if (rvfi_valid[channel_idx] && rvfi_order[64*channel_idx +: 64] > insn_order && 44 | (register_index == rvfi_rs1_addr[channel_idx*5 +: 5] || 45 | register_index == rvfi_rs2_addr[channel_idx*5 +: 5])) begin 46 | found_non_causal = 1; 47 | end 48 | end 49 | end 50 | end 51 | end 52 | endmodule 53 | -------------------------------------------------------------------------------- /checks/rvfi_dmem_check.sv: -------------------------------------------------------------------------------- 1 | // Copyright (C) 2017 Clifford Wolf 2 | // 3 | // Permission to use, copy, modify, and/or distribute this software for any 4 | // purpose with or without fee is hereby granted, provided that the above 5 | // copyright notice and this permission notice appear in all copies. 6 | // 7 | // THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 8 | // WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 9 | // MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 10 | // ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 11 | // WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 12 | // ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 13 | // OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 14 | 15 | module rvfi_dmem_check ( 16 | input clock, reset, enable, 17 | output [`RISCV_FORMAL_XLEN-1:0] dmem_addr, 18 | `RVFI_INPUTS 19 | ); 20 | `rvformal_const_rand_reg [`RISCV_FORMAL_XLEN-1:0] dmem_addr_randval; 21 | assign dmem_addr = dmem_addr_randval; 22 | 23 | reg [`RISCV_FORMAL_XLEN-1:0] dmem_shadow; 24 | reg [`RISCV_FORMAL_XLEN/8-1:0] dmem_written = 0; 25 | 26 | integer channel_idx; 27 | integer i; 28 | 29 | always @(posedge clock) begin 30 | if (reset) begin 31 | dmem_written <= 0; 32 | end else begin 33 | for (channel_idx = 0; channel_idx < `RISCV_FORMAL_NRET; channel_idx=channel_idx+1) begin 34 | if (rvfi_valid[channel_idx] && rvfi_mem_addr[channel_idx*`RISCV_FORMAL_XLEN +: `RISCV_FORMAL_XLEN] == dmem_addr && `rvformal_addr_valid(dmem_addr)) begin 35 | for (i = 0; i < `RISCV_FORMAL_XLEN/8; i = i+1) begin 36 | if (enable && rvfi_mem_rmask[channel_idx*`RISCV_FORMAL_XLEN/8 + i] && dmem_written[i]) 37 | assert(dmem_shadow[i*8 +: 8] == rvfi_mem_rdata[i*8 +: 8]); 38 | if (rvfi_mem_wmask[channel_idx*`RISCV_FORMAL_XLEN/8 + i]) begin 39 | dmem_shadow[i*8 +: 8] = rvfi_mem_wdata[i*8 +: 8]; 40 | dmem_written[i] = 1; 41 | end 42 | end 43 | end 44 | end 45 | end 46 | end 47 | endmodule 48 | -------------------------------------------------------------------------------- /checks/rvfi_hang_check.sv: -------------------------------------------------------------------------------- 1 | // Copyright (C) 2017 Clifford Wolf 2 | // 3 | // Permission to use, copy, modify, and/or distribute this software for any 4 | // purpose with or without fee is hereby granted, provided that the above 5 | // copyright notice and this permission notice appear in all copies. 6 | // 7 | // THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 8 | // WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 9 | // MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 10 | // ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 11 | // WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 12 | // ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 13 | // OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 14 | 15 | module rvfi_hang_check ( 16 | input clock, reset, trig, check, 17 | `RVFI_INPUTS 18 | ); 19 | reg okay = 0; 20 | 21 | integer channel_idx; 22 | always @(posedge clock) begin 23 | if (reset) begin 24 | okay <= 0; 25 | end else begin 26 | for (channel_idx = 0; channel_idx < `RISCV_FORMAL_NRET; channel_idx=channel_idx+1) begin 27 | if (rvfi_valid[channel_idx]) 28 | okay <= 1; 29 | end 30 | if (check) begin 31 | assert(okay); 32 | end 33 | end 34 | for (channel_idx = 0; channel_idx < `RISCV_FORMAL_NRET; channel_idx=channel_idx+1) begin 35 | if (rvfi_valid[channel_idx]) begin 36 | assume(!rvfi_halt[channel_idx]); 37 | assume(rvfi_insn[(channel_idx+1)*`RISCV_FORMAL_ILEN-1 : channel_idx*`RISCV_FORMAL_ILEN] != 32'b 0001000_00101_00000_000_00000_1110011); // WFI 38 | `ifdef RISCV_FORMAL_WAITINSN 39 | assume(!(`RISCV_FORMAL_WAITINSN(rvfi_insn[(channel_idx+1)*`RISCV_FORMAL_ILEN-1 : channel_idx*`RISCV_FORMAL_ILEN]))); 40 | `endif 41 | end 42 | end 43 | end 44 | endmodule 45 | -------------------------------------------------------------------------------- /checks/rvfi_imem_check.sv: -------------------------------------------------------------------------------- 1 | // Copyright (C) 2017 Clifford Wolf 2 | // 3 | // Permission to use, copy, modify, and/or distribute this software for any 4 | // purpose with or without fee is hereby granted, provided that the above 5 | // copyright notice and this permission notice appear in all copies. 6 | // 7 | // THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 8 | // WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 9 | // MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 10 | // ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 11 | // WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 12 | // ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 13 | // OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 14 | 15 | module rvfi_imem_check ( 16 | input clock, reset, enable, 17 | output [`RISCV_FORMAL_XLEN-1:0] imem_addr, 18 | output [15:0] imem_data, 19 | `RVFI_INPUTS 20 | ); 21 | `rvformal_const_rand_reg [`RISCV_FORMAL_XLEN-1:0] imem_addr_randval; 22 | `rvformal_const_rand_reg [15:0] imem_data_randval; 23 | assign imem_addr = imem_addr_randval; 24 | assign imem_data = imem_data_randval; 25 | 26 | reg [`RISCV_FORMAL_XLEN-1:0] pc; 27 | reg [`RISCV_FORMAL_ILEN-1:0] insn; 28 | 29 | integer channel_idx; 30 | integer i; 31 | 32 | always @(posedge clock) begin 33 | if (reset) begin 34 | end else begin 35 | for (channel_idx = 0; channel_idx < `RISCV_FORMAL_NRET; channel_idx=channel_idx+1) begin 36 | if (enable && rvfi_valid[channel_idx]) begin 37 | pc = rvfi_pc_rdata[channel_idx*`RISCV_FORMAL_XLEN +: `RISCV_FORMAL_XLEN]; 38 | insn = rvfi_insn[channel_idx*`RISCV_FORMAL_ILEN +: `RISCV_FORMAL_ILEN]; 39 | 40 | if (`rvformal_addr_valid(pc) && pc == imem_addr) 41 | assert(insn[15:0] == imem_data); 42 | 43 | if (insn[1:0] == 2'b11 && `rvformal_addr_valid(pc+2) && pc+2 == imem_addr) 44 | assert(insn[31:16] == imem_data); 45 | end 46 | end 47 | end 48 | end 49 | endmodule 50 | -------------------------------------------------------------------------------- /checks/rvfi_liveness_check.sv: -------------------------------------------------------------------------------- 1 | // Copyright (C) 2017 Clifford Wolf 2 | // 3 | // Permission to use, copy, modify, and/or distribute this software for any 4 | // purpose with or without fee is hereby granted, provided that the above 5 | // copyright notice and this permission notice appear in all copies. 6 | // 7 | // THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 8 | // WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 9 | // MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 10 | // ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 11 | // WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 12 | // ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 13 | // OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 14 | 15 | module rvfi_liveness_check ( 16 | input clock, reset, trig, check, 17 | `RVFI_INPUTS 18 | ); 19 | `rvformal_const_rand_reg [63:0] insn_order; 20 | reg found_next_insn = 0; 21 | 22 | integer channel_idx; 23 | always @(posedge clock) begin 24 | if (reset) begin 25 | found_next_insn = 0; 26 | end else begin 27 | for (channel_idx = 0; channel_idx < `RISCV_FORMAL_NRET; channel_idx=channel_idx+1) begin 28 | if (rvfi_valid[channel_idx] && rvfi_order[64*channel_idx +: 64] == insn_order+1) begin 29 | found_next_insn = 1; 30 | end 31 | end 32 | if (trig) begin 33 | assume(rvfi_valid[`RISCV_FORMAL_CHANNEL_IDX]); 34 | assume(!rvfi_halt[`RISCV_FORMAL_CHANNEL_IDX]); 35 | assume(insn_order == rvfi_order[64*`RISCV_FORMAL_CHANNEL_IDX +: 64]); 36 | end 37 | if (check) begin 38 | assert(found_next_insn); 39 | end 40 | end 41 | end 42 | endmodule 43 | -------------------------------------------------------------------------------- /checks/rvfi_pc_bwd_check.sv: -------------------------------------------------------------------------------- 1 | // Copyright (C) 2017 Clifford Wolf 2 | // 3 | // Permission to use, copy, modify, and/or distribute this software for any 4 | // purpose with or without fee is hereby granted, provided that the above 5 | // copyright notice and this permission notice appear in all copies. 6 | // 7 | // THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 8 | // WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 9 | // MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 10 | // ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 11 | // WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 12 | // ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 13 | // OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 14 | 15 | module rvfi_pc_bwd_check ( 16 | input clock, reset, check, 17 | `RVFI_INPUTS 18 | ); 19 | `rvformal_const_rand_reg [63:0] insn_order; 20 | reg [`RISCV_FORMAL_XLEN-1:0] expect_pc; 21 | reg expect_pc_valid = 0; 22 | 23 | wire [`RISCV_FORMAL_XLEN-1:0] pc_wdata = rvfi_pc_wdata[`RISCV_FORMAL_CHANNEL_IDX*`RISCV_FORMAL_XLEN +: `RISCV_FORMAL_XLEN]; 24 | 25 | integer channel_idx; 26 | always @(posedge clock) begin 27 | if (reset) begin 28 | expect_pc_valid = 0; 29 | end else begin 30 | if (check) begin 31 | for (channel_idx = 0; channel_idx < `RISCV_FORMAL_CHANNEL_IDX; channel_idx=channel_idx+1) begin 32 | if (rvfi_valid[channel_idx] && rvfi_order[64*channel_idx +: 64] == insn_order+1) begin 33 | expect_pc = rvfi_pc_rdata[channel_idx*`RISCV_FORMAL_XLEN +: `RISCV_FORMAL_XLEN]; 34 | expect_pc_valid = 1; 35 | end 36 | end 37 | 38 | assume(rvfi_valid[`RISCV_FORMAL_CHANNEL_IDX]); 39 | assume(insn_order == rvfi_order[64*`RISCV_FORMAL_CHANNEL_IDX +: 64]); 40 | if (expect_pc_valid) begin 41 | assert(`rvformal_addr_eq(expect_pc, pc_wdata)); 42 | end 43 | end else begin 44 | for (channel_idx = 0; channel_idx < `RISCV_FORMAL_NRET; channel_idx=channel_idx+1) begin 45 | if (rvfi_valid[channel_idx] && rvfi_order[64*channel_idx +: 64] == insn_order+1) begin 46 | expect_pc = rvfi_pc_rdata[channel_idx*`RISCV_FORMAL_XLEN +: `RISCV_FORMAL_XLEN]; 47 | expect_pc_valid = 1; 48 | end 49 | end 50 | end 51 | end 52 | end 53 | endmodule 54 | -------------------------------------------------------------------------------- /checks/rvfi_pc_fwd_check.sv: -------------------------------------------------------------------------------- 1 | // Copyright (C) 2017 Clifford Wolf 2 | // 3 | // Permission to use, copy, modify, and/or distribute this software for any 4 | // purpose with or without fee is hereby granted, provided that the above 5 | // copyright notice and this permission notice appear in all copies. 6 | // 7 | // THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 8 | // WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 9 | // MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 10 | // ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 11 | // WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 12 | // ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 13 | // OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 14 | 15 | module rvfi_pc_fwd_check ( 16 | input clock, reset, check, 17 | `RVFI_INPUTS 18 | ); 19 | `rvformal_const_rand_reg [63:0] insn_order; 20 | reg [`RISCV_FORMAL_XLEN-1:0] expect_pc; 21 | reg expect_pc_valid = 0; 22 | 23 | wire [`RISCV_FORMAL_XLEN-1:0] pc_rdata = rvfi_pc_rdata[`RISCV_FORMAL_CHANNEL_IDX*`RISCV_FORMAL_XLEN +: `RISCV_FORMAL_XLEN]; 24 | 25 | integer channel_idx; 26 | always @(posedge clock) begin 27 | if (reset) begin 28 | expect_pc_valid = 0; 29 | end else begin 30 | if (check) begin 31 | for (channel_idx = 0; channel_idx < `RISCV_FORMAL_CHANNEL_IDX; channel_idx=channel_idx+1) begin 32 | if (rvfi_valid[channel_idx] && rvfi_order[64*channel_idx +: 64] == insn_order-1) begin 33 | expect_pc = rvfi_pc_wdata[channel_idx*`RISCV_FORMAL_XLEN +: `RISCV_FORMAL_XLEN]; 34 | expect_pc_valid = 1; 35 | end 36 | end 37 | 38 | assume(rvfi_valid[`RISCV_FORMAL_CHANNEL_IDX]); 39 | assume(insn_order == rvfi_order[64*`RISCV_FORMAL_CHANNEL_IDX +: 64]); 40 | if (expect_pc_valid) begin 41 | assert(`rvformal_addr_eq(expect_pc, pc_rdata)); 42 | end 43 | end else begin 44 | for (channel_idx = 0; channel_idx < `RISCV_FORMAL_NRET; channel_idx=channel_idx+1) begin 45 | if (rvfi_valid[channel_idx] && rvfi_order[64*channel_idx +: 64] == insn_order-1) begin 46 | expect_pc = rvfi_pc_wdata[channel_idx*`RISCV_FORMAL_XLEN +: `RISCV_FORMAL_XLEN]; 47 | expect_pc_valid = 1; 48 | end 49 | end 50 | end 51 | end 52 | end 53 | endmodule 54 | -------------------------------------------------------------------------------- /checks/rvfi_unique_check.sv: -------------------------------------------------------------------------------- 1 | // Copyright (C) 2017 Clifford Wolf 2 | // 3 | // Permission to use, copy, modify, and/or distribute this software for any 4 | // purpose with or without fee is hereby granted, provided that the above 5 | // copyright notice and this permission notice appear in all copies. 6 | // 7 | // THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 8 | // WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 9 | // MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 10 | // ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 11 | // WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 12 | // ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 13 | // OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 14 | 15 | module rvfi_unique_check ( 16 | input clock, reset, trig, check, 17 | `RVFI_INPUTS 18 | ); 19 | `rvformal_const_rand_reg [63:0] insn_order; 20 | reg found_other_insn = 0; 21 | 22 | integer channel_idx; 23 | always @(posedge clock) begin 24 | if (reset) begin 25 | found_other_insn = 0; 26 | end else begin 27 | for (channel_idx = 0; channel_idx < `RISCV_FORMAL_NRET; channel_idx=channel_idx+1) begin 28 | if (rvfi_valid[channel_idx] && rvfi_order[64*channel_idx +: 64] == insn_order && 29 | (!trig || channel_idx != `RISCV_FORMAL_CHANNEL_IDX)) begin 30 | found_other_insn = 1; 31 | end 32 | end 33 | if (trig) begin 34 | assume(rvfi_valid[`RISCV_FORMAL_CHANNEL_IDX]); 35 | assume(insn_order == rvfi_order[64*`RISCV_FORMAL_CHANNEL_IDX +: 64]); 36 | end 37 | if (check) begin 38 | assert(!found_other_insn); 39 | end 40 | end 41 | end 42 | endmodule 43 | -------------------------------------------------------------------------------- /cores/VexRiscv/.gitignore: -------------------------------------------------------------------------------- 1 | cover 2 | complete 3 | /checks/ 4 | /picorv32.v 5 | /disasm.s 6 | /disasm.o 7 | -------------------------------------------------------------------------------- /cores/VexRiscv/README.md: -------------------------------------------------------------------------------- 1 | 2 | riscv-formal proofs for VexRiscv 3 | ================================ 4 | 5 | ### Current state: 6 | Test a simple VexRiscv configuration (https://github.com/SpinalHDL/VexRiscv/blob/master/src/main/scala/vexriscv/demo/FormalSimple.scala) 7 | 8 | All standards checks are passing 9 | - Instruction Checks 10 | - PC Checks 11 | - Register Checks 12 | - Causality 13 | - Liveness 14 | 15 | Others tests passing : 16 | - Instruction Memory check 17 | - Data Memory check 18 | 19 | ### Quickstart guide: 20 | 21 | First install Yosys, SymbiYosys, and the solvers. See [here](http://symbiyosys.readthedocs.io/en/latest/quickstart.html#installing) 22 | for instructions. 23 | 24 | To run all standards checks: 25 | 26 | ``` 27 | python3 ../../checks/genchecks.py 28 | make -C checks -j$(nproc) 29 | ``` 30 | 31 | To run again a single check which had failed: 32 | 33 | ``` 34 | #A single time 35 | python3 ../../checks/genchecks.py 36 | 37 | #Each time 38 | export test=insn_beq_ch0; rm -r checks/$test; make -C checks -j$(nproc) $test/PASS; python3 disasm.py checks/$test/engine_0/trace.vcd 39 | ``` 40 | 41 | 42 | To run imem/dmem checks checks : 43 | 44 | ``` 45 | sby -f imemcheck.sby 46 | sby -f dmemcheck.sby 47 | ``` 48 | 49 | ### Todo: 50 | - Integrate others VexRiscv configurations into the framework 51 | - Add Checking for equivalence of core with and without RVFI check 52 | - Add Complete check 53 | - Add Cover check 54 | 55 | 56 | 57 | 58 | -------------------------------------------------------------------------------- /cores/VexRiscv/checks.cfg: -------------------------------------------------------------------------------- 1 | 2 | [options] 3 | isa rv32i 4 | 5 | [depth] 6 | insn 20 7 | reg 15 30 8 | pc_fwd 10 30 9 | pc_bwd 10 30 10 | liveness 1 10 30 11 | unique 1 10 30 12 | causal 10 30 13 | 14 | [defines] 15 | `define RISCV_FORMAL_ALIGNED_MEM 16 | `define RISCV_FORMAL_ALTOPS 17 | `define DEBUGNETS 18 | 19 | [defines liveness] 20 | `define VEXRISCV_FAIRNESS 21 | 22 | [script-sources] 23 | read_verilog -sv @basedir@/cores/@core@/wrapper.sv 24 | read_verilog @basedir@/cores/@core@/@core@.v 25 | 26 | -------------------------------------------------------------------------------- /cores/VexRiscv/disasm.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python3 2 | 3 | from Verilog_VCD.Verilog_VCD import parse_vcd 4 | from os import system 5 | from sys import argv 6 | 7 | rvfi_valid = None 8 | rvfi_order = None 9 | rvfi_insn = None 10 | 11 | for netinfo in parse_vcd(argv[1]).values(): 12 | for net in netinfo['nets']: 13 | # print(net["hier"], net["name"]) 14 | if net["hier"] == "rvfi_testbench.wrapper" and net["name"] == "rvfi_valid": 15 | rvfi_valid = netinfo['tv'] 16 | if net["hier"] == "rvfi_testbench.wrapper" and net["name"] == "rvfi_order": 17 | rvfi_order = netinfo['tv'] 18 | if net["hier"] == "rvfi_testbench.wrapper" and net["name"] == "rvfi_insn": 19 | rvfi_insn = netinfo['tv'] 20 | 21 | assert len(rvfi_valid) == len(rvfi_order) 22 | assert len(rvfi_valid) == len(rvfi_insn) 23 | 24 | prog = list() 25 | 26 | for tv_valid, tv_order, tv_insn in zip(rvfi_valid, rvfi_order, rvfi_insn): 27 | if tv_valid[1] == '1': 28 | prog.append((int(tv_order[1], 2), int(tv_insn[1], 2))) 29 | 30 | with open("disasm.s", "w") as f: 31 | for tv_order, tv_insn in sorted(prog): 32 | if tv_insn & 3 != 3 and tv_insn & 0xffff0000 == 0: 33 | print(".hword 0x%04x # %d" % (tv_insn, tv_order), file=f) 34 | else: 35 | print(".word 0x%08x # %d" % (tv_insn, tv_order), file=f) 36 | 37 | system("riscv64-unknown-elf-gcc -c disasm.s") 38 | system("riscv64-unknown-elf-objdump -d -M numeric,no-aliases disasm.o") 39 | 40 | -------------------------------------------------------------------------------- /cores/VexRiscv/dmemcheck.sby: -------------------------------------------------------------------------------- 1 | [options] 2 | mode bmc 3 | append 0 4 | tbtop testbench.uut 5 | depth 22 6 | 7 | [engines] 8 | smtbmc --presat --unroll boolector 9 | 10 | [script] 11 | read_verilog -sv dmemcheck.sv 12 | read_verilog ../../VexRiscv.v 13 | prep -nordff -top testbench 14 | 15 | [files] 16 | dmemcheck.sv 17 | ../../checks/rvfi_macros.vh 18 | ../../checks/rvfi_channel.sv 19 | ../../checks/rvfi_testbench.sv 20 | ../../checks/rvfi_dmem_check.sv 21 | 22 | -------------------------------------------------------------------------------- /cores/VexRiscv/imemcheck.sby: -------------------------------------------------------------------------------- 1 | [options] 2 | mode bmc 3 | append 0 4 | tbtop testbench.uut 5 | depth 22 6 | 7 | [engines] 8 | smtbmc --presat --unroll boolector 9 | 10 | [script] 11 | read_verilog -sv imemcheck.sv 12 | read_verilog ../../VexRiscv.v 13 | prep -nordff -top testbench 14 | 15 | [files] 16 | imemcheck.sv 17 | ../../checks/rvfi_macros.vh 18 | ../../checks/rvfi_channel.sv 19 | ../../checks/rvfi_testbench.sv 20 | ../../checks/rvfi_imem_check.sv 21 | -------------------------------------------------------------------------------- /cores/picorv32/.gitignore: -------------------------------------------------------------------------------- 1 | /cover/ 2 | /complete/ 3 | /honest/ 4 | /checks/ 5 | /testbug[0-9][0-9][0-9].cfg 6 | /testbug[0-9][0-9][0-9]/ 7 | /testbugs.mk 8 | /cexdata-[0-9][0-9][0-9][0-9][0-9][0-9][0-9][0-9] 9 | /cexdata-[0-9][0-9][0-9][0-9][0-9][0-9][0-9][0-9].zip 10 | /picorv32.v 11 | /disasm.s 12 | /disasm.o 13 | -------------------------------------------------------------------------------- /cores/picorv32/README.md: -------------------------------------------------------------------------------- 1 | 2 | riscv-formal proofs for picorv32 3 | ================================ 4 | 5 | Quickstart guide: 6 | 7 | First install Yosys, SymbiYosys, and the solvers. See 8 | [here](http://symbiyosys.readthedocs.io/en/latest/quickstart.html#installing) 9 | for instructions. Then download the core, generate the formal checks and run them: 10 | 11 | ``` 12 | wget -O picorv32.v https://raw.githubusercontent.com/cliffordwolf/picorv32/master/picorv32.v 13 | python3 ../../checks/genchecks.py 14 | make -C checks -j$(nproc) 15 | ``` 16 | 17 | -------------------------------------------------------------------------------- /cores/picorv32/cexdata.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | set -ex 4 | cexdata="cexdata-$(date '+%Y%m%d')" 5 | 6 | rm -rf $cexdata 7 | mkdir $cexdata 8 | 9 | for x in {checks,testbug[0-9][0-9][0-9]}/*/FAIL; do 10 | test -f $x || continue 11 | x=${x%/FAIL} 12 | y=${x/\//_} 13 | cp $x/logfile.txt $cexdata/$y.log 14 | if test -f $x/engine_*/trace.vcd; then 15 | cp $x/engine_*/trace.vcd $cexdata/$y.vcd 16 | python3 disasm.py $cexdata/$y.vcd > $cexdata/$y.asm 17 | fi 18 | done 19 | 20 | for x in {checks,testbug[0-9][0-9][0-9]}/*.sby; do 21 | test -f $x || continue 22 | x=${x%.sby} 23 | if [ -f $x/PASS ]; then 24 | printf "%-30s %s %10s\n" $x pass $(sed '/Elapsed process time/ { s/.*\]: //; s/ .*//; p; }; d;' $x/logfile.txt) 25 | elif [ -f $x/FAIL ]; then 26 | printf "%-30s %s %10s\n" $x FAIL $(sed '/Elapsed process time/ { s/.*\]: //; s/ .*//; p; }; d;' $x/logfile.txt) 27 | else 28 | printf "%-30s %s\n" $x unknown 29 | fi 30 | done | awk '{ print gensub(":", "", "g", $3), $0; }' | sort -n | cut -f2- -d' ' > $cexdata/status.txt 31 | 32 | rm -f $cexdata.zip 33 | zip -r $cexdata.zip $cexdata/ 34 | -------------------------------------------------------------------------------- /cores/picorv32/checks.cfg: -------------------------------------------------------------------------------- 1 | [options] 2 | isa rv32imc 3 | 4 | [depth] 5 | insn 20 6 | reg 15 25 7 | pc_fwd 10 30 8 | pc_bwd 10 30 9 | liveness 1 10 30 10 | unique 1 10 30 11 | causal 10 30 12 | csrw 30 13 | cover 1 15 14 | 15 | [sort] 16 | reg_ch0 17 | 18 | [csrs] 19 | mcycle 20 | minstret 21 | 22 | [defines] 23 | `define RISCV_FORMAL_ALIGNED_MEM 24 | `define RISCV_FORMAL_ALTOPS 25 | `define RISCV_FORMAL_UMODE 26 | `define PICORV32_CSR_RESTRICT 27 | `define PICORV32_TESTBUG_NONE 28 | `define DEBUGNETS 29 | 30 | [defines liveness] 31 | `define PICORV32_FAIRNESS 32 | 33 | [script-sources] 34 | read_verilog -sv @basedir@/cores/@core@/wrapper.sv 35 | read_verilog @basedir@/cores/@core@/@core@.v 36 | 37 | [cover] 38 | always @* if (!reset) cover (channel[0].cnt_insns == 2); 39 | -------------------------------------------------------------------------------- /cores/picorv32/checks.gtkw: -------------------------------------------------------------------------------- 1 | [*] 2 | [*] GTKWave Analyzer v3.3.65 (w)1999-2015 BSI 3 | [*] Wed Sep 13 00:29:24 2017 4 | [*] 5 | [dumpfile] "(null)" 6 | [savefile] "/home/clifford/Work/riscv-formal/cores/picorv32/checks.gtkw" 7 | [timestart] 0 8 | [size] 1263 878 9 | [pos] -1 -1 10 | *-6.814997 100 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 11 | [treeopen] rvfi_testbench. 12 | [treeopen] rvfi_testbench.wrapper. 13 | [sst_width] 225 14 | [signals_width] 335 15 | [sst_expanded] 1 16 | [sst_vpaned_height] 258 17 | @24 18 | smt_step 19 | @200 20 | - 21 | -PicoRV32 22 | @28 23 | rvfi_testbench.wrapper.uut.resetn 24 | @820 25 | rvfi_testbench.wrapper.uut.dbg_ascii_state[127:0] 26 | rvfi_testbench.wrapper.uut.dbg_ascii_instr[63:0] 27 | @200 28 | - 29 | @28 30 | rvfi_testbench.wrapper.mem_valid 31 | rvfi_testbench.wrapper.mem_ready 32 | rvfi_testbench.wrapper.mem_instr 33 | @22 34 | rvfi_testbench.wrapper.mem_addr[31:0] 35 | rvfi_testbench.wrapper.mem_wstrb[3:0] 36 | rvfi_testbench.wrapper.mem_rdata[31:0] 37 | rvfi_testbench.wrapper.mem_wdata[31:0] 38 | @200 39 | - 40 | -RVFI 41 | @28 42 | rvfi_testbench.checker_inst.reset 43 | rvfi_testbench.checker_inst.trig 44 | rvfi_testbench.checker_inst.check 45 | @200 46 | - 47 | @28 48 | rvfi_testbench.checker_inst.rvfi_valid 49 | rvfi_testbench.checker_inst.rvfi_trap 50 | rvfi_testbench.checker_inst.rvfi_intr 51 | rvfi_testbench.checker_inst.rvfi_halt 52 | @200 53 | - 54 | @25 55 | rvfi_testbench.checker_inst.rvfi_order[63:0] 56 | @22 57 | rvfi_testbench.checker_inst.rvfi_insn[31:0] 58 | rvfi_testbench.checker_inst.rvfi_pc_rdata[31:0] 59 | rvfi_testbench.checker_inst.rvfi_pc_wdata[31:0] 60 | @200 61 | - 62 | @22 63 | rvfi_testbench.checker_inst.rvfi_rs1_addr[4:0] 64 | rvfi_testbench.checker_inst.rvfi_rs2_addr[4:0] 65 | rvfi_testbench.checker_inst.rvfi_rd_addr[4:0] 66 | @200 67 | - 68 | @22 69 | rvfi_testbench.checker_inst.rvfi_rs1_rdata[31:0] 70 | rvfi_testbench.checker_inst.rvfi_rs2_rdata[31:0] 71 | rvfi_testbench.checker_inst.rvfi_rd_wdata[31:0] 72 | @200 73 | - 74 | @22 75 | rvfi_testbench.checker_inst.rvfi_mem_addr[31:0] 76 | rvfi_testbench.checker_inst.rvfi_mem_rmask[3:0] 77 | rvfi_testbench.checker_inst.rvfi_mem_wmask[3:0] 78 | rvfi_testbench.checker_inst.rvfi_mem_rdata[31:0] 79 | rvfi_testbench.checker_inst.rvfi_mem_wdata[31:0] 80 | @200 81 | - 82 | [pattern_trace] 1 83 | [pattern_trace] 0 84 | -------------------------------------------------------------------------------- /cores/picorv32/complete.sby: -------------------------------------------------------------------------------- 1 | [options] 2 | mode bmc 3 | aigsmt z3 4 | depth 20 5 | 6 | [engines] 7 | abc bmc3 8 | 9 | [script] 10 | verilog_defines -D DEBUGNETS 11 | verilog_defines -D RISCV_FORMAL 12 | verilog_defines -D RISCV_FORMAL_NRET=1 13 | verilog_defines -D RISCV_FORMAL_XLEN=32 14 | verilog_defines -D RISCV_FORMAL_ILEN=32 15 | verilog_defines -D RISCV_FORMAL_COMPRESSED 16 | verilog_defines -D RISCV_FORMAL_ALIGNED_MEM 17 | read_verilog -sv rvfi_macros.vh 18 | read_verilog -sv picorv32.v 19 | 20 | --pycode-begin-- 21 | with open("../../insns/isa_rv32ic.txt") as f: 22 | for line in f: 23 | output("read_verilog -sv insn_%s.v" % line.strip()) 24 | --pycode-end-- 25 | 26 | read_verilog -sv isa_rv32ic.v 27 | read_verilog -sv complete.sv 28 | prep -nordff -top testbench 29 | 30 | [files] 31 | complete.sv 32 | ../../../picorv32/picorv32.v 33 | ../../checks/rvfi_macros.vh 34 | ../../insns/isa_rv32ic.v 35 | 36 | --pycode-begin-- 37 | with open("../../insns/isa_rv32ic.txt") as f: 38 | for line in f: 39 | output("../../insns/insn_%s.v" % line.strip()) 40 | --pycode-end-- 41 | 42 | -------------------------------------------------------------------------------- /cores/picorv32/complete.sv: -------------------------------------------------------------------------------- 1 | module testbench ( 2 | input clk, 3 | 4 | input mem_ready, 5 | output mem_valid, 6 | output mem_instr, 7 | output [31:0] mem_addr, 8 | output [31:0] mem_wdata, 9 | output [3:0] mem_wstrb, 10 | input [31:0] mem_rdata, 11 | 12 | ); 13 | reg resetn = 0; 14 | wire trap; 15 | 16 | always @(posedge clk) 17 | resetn <= 1; 18 | 19 | `RVFI_WIRES 20 | 21 | picorv32 #( 22 | .COMPRESSED_ISA(1), 23 | .BARREL_SHIFTER(1) 24 | ) uut ( 25 | .clk (clk ), 26 | .resetn (resetn ), 27 | .trap (trap ), 28 | 29 | .mem_valid (mem_valid ), 30 | .mem_instr (mem_instr ), 31 | .mem_ready (mem_ready ), 32 | .mem_addr (mem_addr ), 33 | .mem_wdata (mem_wdata ), 34 | .mem_wstrb (mem_wstrb ), 35 | .mem_rdata (mem_rdata ), 36 | 37 | `RVFI_CONN 38 | ); 39 | 40 | (* keep *) wire spec_valid; 41 | (* keep *) wire spec_trap; 42 | (* keep *) wire [ 4 : 0] spec_rs1_addr; 43 | (* keep *) wire [ 4 : 0] spec_rs2_addr; 44 | (* keep *) wire [ 4 : 0] spec_rd_addr; 45 | (* keep *) wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata; 46 | (* keep *) wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata; 47 | (* keep *) wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr; 48 | (* keep *) wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask; 49 | (* keep *) wire [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask; 50 | (* keep *) wire [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata; 51 | 52 | rvfi_isa_rv32ic isa_spec ( 53 | .rvfi_valid (rvfi_valid ), 54 | .rvfi_insn (rvfi_insn ), 55 | .rvfi_pc_rdata (rvfi_pc_rdata ), 56 | .rvfi_rs1_rdata(rvfi_rs1_rdata), 57 | .rvfi_rs2_rdata(rvfi_rs2_rdata), 58 | .rvfi_mem_rdata(rvfi_mem_rdata), 59 | 60 | .spec_valid (spec_valid ), 61 | .spec_trap (spec_trap ), 62 | .spec_rs1_addr (spec_rs1_addr ), 63 | .spec_rs2_addr (spec_rs2_addr ), 64 | .spec_rd_addr (spec_rd_addr ), 65 | .spec_rd_wdata (spec_rd_wdata ), 66 | .spec_pc_wdata (spec_pc_wdata ), 67 | .spec_mem_addr (spec_mem_addr ), 68 | .spec_mem_rmask(spec_mem_rmask), 69 | .spec_mem_wmask(spec_mem_wmask), 70 | .spec_mem_wdata(spec_mem_wdata) 71 | ); 72 | 73 | always @* begin 74 | if (resetn && rvfi_valid && !rvfi_trap) begin 75 | if (rvfi_insn[6:0] != 7'b1110011) 76 | assert(spec_valid && !spec_trap); 77 | end 78 | end 79 | endmodule 80 | -------------------------------------------------------------------------------- /cores/picorv32/cover.sby: -------------------------------------------------------------------------------- 1 | [options] 2 | mode cover 3 | depth 100 4 | 5 | [engines] 6 | smtbmc boolector 7 | 8 | [script] 9 | verilog_defines -D RISCV_FORMAL 10 | verilog_defines -D RISCV_FORMAL_NRET=1 11 | verilog_defines -D RISCV_FORMAL_XLEN=32 12 | verilog_defines -D RISCV_FORMAL_ILEN=32 13 | verilog_defines -D RISCV_FORMAL_ALIGNED_MEM 14 | read_verilog rvfi_macros.vh 15 | read_verilog picorv32.v 16 | read_verilog -sv -formal cover.sv 17 | prep -nordff -top testbench 18 | 19 | [files] 20 | ../../checks/rvfi_macros.vh 21 | ../../../picorv32/picorv32.v 22 | cover.sv 23 | -------------------------------------------------------------------------------- /cores/picorv32/cover.sv: -------------------------------------------------------------------------------- 1 | module testbench ( 2 | input clk, 3 | 4 | input mem_ready, 5 | output mem_valid, 6 | output mem_instr, 7 | output [31:0] mem_addr, 8 | output [31:0] mem_wdata, 9 | output [3:0] mem_wstrb, 10 | input [31:0] mem_rdata, 11 | 12 | ); 13 | reg resetn = 0; 14 | wire trap; 15 | 16 | always @(posedge clk) 17 | resetn <= 1; 18 | 19 | `RVFI_WIRES 20 | 21 | picorv32 #( 22 | .REGS_INIT_ZERO(1), 23 | .COMPRESSED_ISA(1), 24 | .BARREL_SHIFTER(1) 25 | ) uut ( 26 | .clk (clk ), 27 | .resetn (resetn ), 28 | .trap (trap ), 29 | 30 | .mem_valid (mem_valid ), 31 | .mem_instr (mem_instr ), 32 | .mem_ready (mem_ready ), 33 | .mem_addr (mem_addr ), 34 | .mem_wdata (mem_wdata ), 35 | .mem_wstrb (mem_wstrb ), 36 | .mem_rdata (mem_rdata ), 37 | 38 | `RVFI_CONN 39 | ); 40 | 41 | integer count_dmemrd = 0; 42 | integer count_dmemwr = 0; 43 | integer count_longinsn = 0; 44 | integer count_comprinsn = 0; 45 | 46 | always @(posedge clk) begin 47 | if (resetn && rvfi_valid) begin 48 | if (rvfi_mem_rmask) 49 | count_dmemrd <= count_dmemrd + 1; 50 | if (rvfi_mem_wmask) 51 | count_dmemwr <= count_dmemwr + 1; 52 | if (rvfi_insn[1:0] == 3) 53 | count_longinsn <= count_longinsn + 1; 54 | if (rvfi_insn[1:0] != 3) 55 | count_comprinsn <= count_comprinsn + 1; 56 | end 57 | end 58 | 59 | cover property (count_dmemrd); 60 | cover property (count_dmemwr); 61 | cover property (count_longinsn); 62 | cover property (count_comprinsn); 63 | 64 | cover property (count_dmemrd >= 1 && count_dmemwr >= 1 && count_longinsn >= 1 && count_comprinsn >= 1); 65 | cover property (count_dmemrd >= 2 && count_dmemwr >= 2 && count_longinsn >= 2 && count_comprinsn >= 2); 66 | cover property (count_dmemrd >= 3 && count_dmemwr >= 2 && count_longinsn >= 2 && count_comprinsn >= 2); 67 | cover property (count_dmemrd >= 2 && count_dmemwr >= 3 && count_longinsn >= 2 && count_comprinsn >= 2); 68 | cover property (count_dmemrd >= 2 && count_dmemwr >= 2 && count_longinsn >= 3 && count_comprinsn >= 2); 69 | cover property (count_dmemrd >= 2 && count_dmemwr >= 2 && count_longinsn >= 2 && count_comprinsn >= 3); 70 | endmodule 71 | -------------------------------------------------------------------------------- /cores/picorv32/disasm.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python3 2 | 3 | from Verilog_VCD.Verilog_VCD import parse_vcd 4 | from os import system 5 | from sys import argv 6 | 7 | rvfi_valid = None 8 | rvfi_order = None 9 | rvfi_insn = None 10 | 11 | for netinfo in parse_vcd(argv[1]).values(): 12 | for net in netinfo['nets']: 13 | # print(net["hier"], net["name"]) 14 | if net["hier"] == "rvfi_testbench.wrapper" and net["name"] == "rvfi_valid": 15 | rvfi_valid = netinfo['tv'] 16 | if net["hier"] == "rvfi_testbench.wrapper" and net["name"] == "rvfi_order": 17 | rvfi_order = netinfo['tv'] 18 | if net["hier"] == "rvfi_testbench.wrapper" and net["name"] == "rvfi_insn": 19 | rvfi_insn = netinfo['tv'] 20 | 21 | assert len(rvfi_valid) == len(rvfi_order) 22 | assert len(rvfi_valid) == len(rvfi_insn) 23 | 24 | prog = list() 25 | 26 | for tv_valid, tv_order, tv_insn in zip(rvfi_valid, rvfi_order, rvfi_insn): 27 | if tv_valid[1] == '1': 28 | prog.append((int(tv_order[1], 2), int(tv_insn[1], 2))) 29 | 30 | with open("disasm.s", "w") as f: 31 | for tv_order, tv_insn in sorted(prog): 32 | if tv_insn & 3 != 3 and tv_insn & 0xffff0000 == 0: 33 | print(".hword 0x%04x # %d" % (tv_insn, tv_order), file=f) 34 | else: 35 | print(".word 0x%08x # %d" % (tv_insn, tv_order), file=f) 36 | 37 | system("riscv32-unknown-elf-gcc -c disasm.s") 38 | system("riscv32-unknown-elf-objdump -d -M numeric,no-aliases disasm.o") 39 | 40 | -------------------------------------------------------------------------------- /cores/picorv32/dmemcheck.sv: -------------------------------------------------------------------------------- 1 | module testbench ( 2 | input clk, 3 | 4 | input mem_ready, 5 | output mem_valid, 6 | output mem_instr, 7 | output [31:0] mem_addr, 8 | output [31:0] mem_wdata, 9 | output [3:0] mem_wstrb, 10 | input [31:0] mem_rdata 11 | ); 12 | reg resetn = 0; 13 | wire trap; 14 | 15 | always @(posedge clk) 16 | resetn <= 1; 17 | 18 | `RVFI_WIRES 19 | 20 | wire [31:0] dmem_addr; 21 | reg [31:0] dmem_data; 22 | 23 | rvfi_dmem_check checker_inst ( 24 | .clock (clk ), 25 | .reset (!resetn ), 26 | .enable (1'b1 ), 27 | .dmem_addr (dmem_addr), 28 | `RVFI_CONN 29 | ); 30 | 31 | always @(posedge clk) begin 32 | if (resetn && mem_valid && mem_ready && mem_addr == dmem_addr) begin 33 | if (mem_wstrb[0]) dmem_data[ 7: 0] <= mem_wdata[ 7: 0]; 34 | if (mem_wstrb[1]) dmem_data[15: 8] <= mem_wdata[15: 8]; 35 | if (mem_wstrb[2]) dmem_data[23:16] <= mem_wdata[23:16]; 36 | if (mem_wstrb[3]) dmem_data[31:24] <= mem_wdata[31:24]; 37 | end 38 | end 39 | 40 | always @* begin 41 | if (resetn && mem_valid && mem_ready && mem_addr == dmem_addr && !mem_wstrb) 42 | assume(dmem_data == mem_rdata); 43 | end 44 | 45 | picorv32 #( 46 | .REGS_INIT_ZERO(1), 47 | .COMPRESSED_ISA(1), 48 | .BARREL_SHIFTER(1) 49 | ) uut ( 50 | .clk (clk ), 51 | .resetn (resetn ), 52 | .trap (trap ), 53 | 54 | .mem_valid (mem_valid ), 55 | .mem_instr (mem_instr ), 56 | .mem_ready (mem_ready ), 57 | .mem_addr (mem_addr ), 58 | .mem_wdata (mem_wdata ), 59 | .mem_wstrb (mem_wstrb ), 60 | .mem_rdata (mem_rdata ), 61 | 62 | `RVFI_CONN 63 | ); 64 | 65 | reg [4:0] mem_wait = 0; 66 | always @(posedge clk) begin 67 | mem_wait <= {mem_wait, mem_valid && !mem_ready}; 68 | // restrict(~mem_wait && !trap); 69 | end 70 | endmodule 71 | 72 | -------------------------------------------------------------------------------- /cores/picorv32/equiv.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | set -ex 3 | yosys -p ' 4 | read_verilog picorv32.v 5 | chparam -set COMPRESSED_ISA 0 -set BARREL_SHIFTER 1 picorv32 6 | prep -flatten -top picorv32 7 | design -stash gold 8 | 9 | read_verilog -D RISCV_FORMAL picorv32.v 10 | chparam -set COMPRESSED_ISA 0 -set BARREL_SHIFTER 1 picorv32 11 | prep -flatten -top picorv32 12 | delete -port picorv32/rvfi_* 13 | design -stash gate 14 | 15 | design -copy-from gold -as gold picorv32 16 | design -copy-from gate -as gate picorv32 17 | memory_map; opt -fast 18 | equiv_make gold gate equiv 19 | hierarchy -top equiv 20 | 21 | opt -fast 22 | equiv_simple 23 | equiv_induct 24 | equiv_status -assert 25 | ' 26 | -------------------------------------------------------------------------------- /cores/picorv32/honest.sby: -------------------------------------------------------------------------------- 1 | [options] 2 | mode bmc 3 | aigsmt z3 4 | depth 30 5 | 6 | [engines] 7 | abc bmc3 8 | 9 | [script] 10 | verilog_defines -D DEBUGNETS 11 | verilog_defines -D RISCV_FORMAL 12 | verilog_defines -D RISCV_FORMAL_NRET=1 13 | verilog_defines -D RISCV_FORMAL_XLEN=32 14 | verilog_defines -D RISCV_FORMAL_ILEN=32 15 | verilog_defines -D RISCV_FORMAL_COMPRESSED 16 | verilog_defines -D RISCV_FORMAL_ALIGNED_MEM 17 | read_verilog -sv rvfi_macros.vh 18 | read_verilog -sv picorv32.v 19 | read_verilog -sv honest.sv 20 | prep -nordff -top testbench 21 | 22 | [files] 23 | honest.sv 24 | ../../../picorv32/picorv32.v 25 | ../../checks/rvfi_macros.vh 26 | -------------------------------------------------------------------------------- /cores/picorv32/honest.sv: -------------------------------------------------------------------------------- 1 | module testbench ( 2 | input clk, 3 | 4 | input mem_ready, 5 | output mem_valid, 6 | output mem_instr, 7 | output [31:0] mem_addr, 8 | output [31:0] mem_wdata, 9 | output [3:0] mem_wstrb, 10 | input [31:0] mem_rdata, 11 | 12 | ); 13 | (* anyconst *) reg [31:0] monitor_insn; 14 | reg monitor_state = 0; 15 | reg [7:0] cycle = 0; 16 | 17 | reg resetn = 0; 18 | wire trap; 19 | 20 | always @(posedge clk) begin 21 | resetn <= 1; 22 | cycle <= cycle + 1; 23 | assume((!mem_valid || mem_ready) || $past(!mem_valid || mem_ready)); 24 | end 25 | 26 | `RVFI_WIRES 27 | 28 | picorv32 #( 29 | .COMPRESSED_ISA(1), 30 | .BARREL_SHIFTER(1) 31 | ) uut ( 32 | .clk (clk ), 33 | .resetn (resetn ), 34 | .trap (trap ), 35 | 36 | .mem_valid (mem_valid ), 37 | .mem_instr (mem_instr ), 38 | .mem_ready (mem_ready ), 39 | .mem_addr (mem_addr ), 40 | .mem_wdata (mem_wdata ), 41 | .mem_wstrb (mem_wstrb ), 42 | .mem_rdata (mem_rdata ), 43 | 44 | `RVFI_CONN 45 | ); 46 | 47 | always @* begin 48 | assume (mem_rdata == monitor_insn); 49 | if (!monitor_state) assert (cycle < 21); 50 | end 51 | 52 | always @(posedge clk) begin 53 | if (rvfi_valid && monitor_insn[1:0] == 3 && rvfi_insn == monitor_insn) 54 | monitor_state <= 1; 55 | if (rvfi_valid && monitor_insn[1:0] != 3 && rvfi_insn[15:0] == monitor_insn[15:0]) 56 | monitor_state <= 1; 57 | end 58 | endmodule 59 | -------------------------------------------------------------------------------- /cores/picorv32/imemcheck.sv: -------------------------------------------------------------------------------- 1 | module testbench ( 2 | input clk, 3 | 4 | input mem_ready, 5 | output mem_valid, 6 | output mem_instr, 7 | output [31:0] mem_addr, 8 | output [31:0] mem_wdata, 9 | output [3:0] mem_wstrb, 10 | input [31:0] mem_rdata 11 | ); 12 | reg resetn = 0; 13 | wire trap; 14 | 15 | always @(posedge clk) 16 | resetn <= 1; 17 | 18 | `RVFI_WIRES 19 | 20 | wire [31:0] imem_addr; 21 | wire [15:0] imem_data; 22 | 23 | rvfi_imem_check checker_inst ( 24 | .clock (clk ), 25 | .reset (!resetn ), 26 | .enable (1'b1 ), 27 | .imem_addr (imem_addr), 28 | .imem_data (imem_data), 29 | `RVFI_CONN 30 | ); 31 | 32 | always @* begin 33 | if (resetn && mem_valid && mem_ready) begin 34 | if (mem_addr == imem_addr) 35 | assume(mem_rdata[15:0] == imem_data); 36 | if (mem_addr+2 == imem_addr) 37 | assume(mem_rdata[31:16] == imem_data); 38 | end 39 | end 40 | 41 | picorv32 #( 42 | .REGS_INIT_ZERO(1), 43 | .COMPRESSED_ISA(1), 44 | .BARREL_SHIFTER(1) 45 | ) uut ( 46 | .clk (clk ), 47 | .resetn (resetn ), 48 | .trap (trap ), 49 | 50 | .mem_valid (mem_valid ), 51 | .mem_instr (mem_instr ), 52 | .mem_ready (mem_ready ), 53 | .mem_addr (mem_addr ), 54 | .mem_wdata (mem_wdata ), 55 | .mem_wstrb (mem_wstrb ), 56 | .mem_rdata (mem_rdata ), 57 | 58 | `RVFI_CONN 59 | ); 60 | 61 | reg [4:0] mem_wait = 0; 62 | always @(posedge clk) begin 63 | mem_wait <= {mem_wait, mem_valid && !mem_ready}; 64 | // restrict(~mem_wait && !trap); 65 | end 66 | endmodule 67 | 68 | -------------------------------------------------------------------------------- /cores/picorv32/testbugs.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | set -ex 4 | 5 | echo "all: checks" > testbugs.mk 6 | echo "checks::" >> testbugs.mk 7 | echo " \$(MAKE) -C checks" >> testbugs.mk 8 | if [ ! -d checks ]; then 9 | python3 ../../checks/genchecks.py 10 | fi 11 | for bug in 001 002 003 004 005; do 12 | sed "s/PICORV32_TESTBUG_NONE/PICORV32_TESTBUG_${bug}/" < checks.cfg > testbug${bug}.cfg 13 | echo "checks::" >> testbugs.mk 14 | echo " \$(MAKE) -C testbug${bug}" >> testbugs.mk 15 | if [ ! -d testbug${bug} ]; then 16 | python3 ../../checks/genchecks.py testbug${bug} 17 | fi 18 | done 19 | -------------------------------------------------------------------------------- /cores/picorv32/wrapper.sv: -------------------------------------------------------------------------------- 1 | module rvfi_wrapper ( 2 | input clock, 3 | input reset, 4 | `RVFI_OUTPUTS 5 | ); 6 | (* keep *) wire trap; 7 | 8 | (* keep *) `rvformal_rand_reg mem_ready; 9 | (* keep *) `rvformal_rand_reg [31:0] mem_rdata; 10 | 11 | (* keep *) wire mem_valid; 12 | (* keep *) wire mem_instr; 13 | (* keep *) wire [31:0] mem_addr; 14 | (* keep *) wire [31:0] mem_wdata; 15 | (* keep *) wire [3:0] mem_wstrb; 16 | 17 | picorv32 #( 18 | .COMPRESSED_ISA(1), 19 | .ENABLE_FAST_MUL(1), 20 | .ENABLE_DIV(1), 21 | .BARREL_SHIFTER(1) 22 | ) uut ( 23 | .clk (clock ), 24 | .resetn (!reset ), 25 | .trap (trap ), 26 | 27 | .mem_valid (mem_valid), 28 | .mem_instr (mem_instr), 29 | .mem_ready (mem_ready), 30 | .mem_addr (mem_addr ), 31 | .mem_wdata (mem_wdata), 32 | .mem_wstrb (mem_wstrb), 33 | .mem_rdata (mem_rdata), 34 | 35 | `RVFI_CONN 36 | ); 37 | 38 | `ifdef PICORV32_FAIRNESS 39 | reg [2:0] mem_wait = 0; 40 | always @(posedge clock) begin 41 | mem_wait <= {mem_wait, mem_valid && !mem_ready}; 42 | assume (~mem_wait || trap); 43 | end 44 | `endif 45 | 46 | `ifdef PICORV32_CSR_RESTRICT 47 | always @* begin 48 | if (rvfi_valid && rvfi_insn[6:0] == 7'b1110011) begin 49 | if (rvfi_insn[14:12] == 3'b010) begin 50 | assume (rvfi_insn[31:20] == 12'hC00 || rvfi_insn[31:20] == 12'hC01 || rvfi_insn[31:20] == 12'hC02 || 51 | rvfi_insn[31:20] == 12'hC80 || rvfi_insn[31:20] == 12'hC81 || rvfi_insn[31:20] == 12'hC82); 52 | assume (rvfi_insn[19:15] == 0); 53 | end 54 | assume (rvfi_insn[14:12] != 3'b001); 55 | assume (rvfi_insn[14:12] != 3'b011); 56 | assume (rvfi_insn[14:12] != 3'b101); 57 | assume (rvfi_insn[14:12] != 3'b110); 58 | assume (rvfi_insn[14:12] != 3'b111); 59 | end 60 | end 61 | `endif 62 | endmodule 63 | 64 | -------------------------------------------------------------------------------- /cores/rocket/.gitignore: -------------------------------------------------------------------------------- 1 | /riscv-tools 2 | /riscv-tools-build 3 | /rocket-chip 4 | /rocket-syn 5 | /cover 6 | /coverage 7 | /checks 8 | /checks.cfg 9 | /testbench 10 | /testbench.v 11 | /testbench.vcd 12 | /obj_dir 13 | /disasm.s 14 | /disasm.o 15 | /cexdata-[0-9][0-9][0-9][0-9][0-9][0-9][0-9][0-9] 16 | /cexdata-[0-9][0-9][0-9][0-9][0-9][0-9][0-9][0-9].zip 17 | /muldivlen_cover 18 | /muldivlen_check 19 | -------------------------------------------------------------------------------- /cores/rocket/README.md: -------------------------------------------------------------------------------- 1 | 2 | riscv-formal proofs for rocket-chip 3 | =================================== 4 | 5 | Quickstart guide: 6 | 7 | First install Yosys, SymbiYosys, and the solvers. See 8 | [here](http://symbiyosys.readthedocs.io/en/latest/quickstart.html#installing) 9 | for instructions. Then build the version of rocket-chip with RVFI support and 10 | rsicv-tools, and generate the formal checks: 11 | 12 | ``` 13 | sudo apt-get install autoconf automake autotools-dev curl \ 14 | device-tree-compiler libmpc-dev libmpfr-dev \ 15 | libgmp-dev gawk build-essential bison flex \ 16 | texinfo gperf libtool patchutils bc zlib1g-dev \ 17 | libusb-1.0-0-dev openjdk-8-jdk-headless 18 | bash generate.sh 19 | ``` 20 | 21 | Then run the formal checks: 22 | 23 | ``` 24 | make -C checks -j$(nproc) 25 | ``` 26 | 27 | Or if you just want to simulate Rocket with RVFIMonitor: 28 | 29 | ``` 30 | export CONFIG=DefaultConfigWithRVFIMonitors 31 | export RISCV=$PWD/riscv-tools 32 | cd rocket-chip/emulator 33 | make -j$(nproc) 34 | make run 35 | ``` 36 | 37 | Important Notes 38 | =============== 39 | 40 | This check sets all dangling wires in the design to constant zero. Without this 41 | there would be a problem with propagating Xs and the checks would fail. Obviously 42 | this is a problem that needs to be addressed in the design, but for now we work 43 | around it here so we can continue writing checks. 44 | 45 | -------------------------------------------------------------------------------- /cores/rocket/cexdata.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | set -ex 4 | cexdata="cexdata-$(date '+%Y%m%d')" 5 | 6 | rm -rf $cexdata 7 | mkdir $cexdata 8 | 9 | while read dir; do echo "$dir $(git -C $dir log -n1 --oneline)"; \ 10 | done < <( echo .; find rocket-chip -name '.git' -printf '%h\n'; ) | \ 11 | expand -t30 > $cexdata/version.txt 12 | 13 | cp rocket-chip/vsim/generated-src/freechips.rocketchip.system.DefaultConfigWithRVFIMonitors.v $cexdata/rocketchip.v 14 | cp rocket-chip/vsim/generated-src/freechips.rocketchip.system.DefaultConfigWithRVFIMonitors.fir $cexdata/rocketchip.fir 15 | gzip $cexdata/rocketchip.v $cexdata/rocketchip.fir 16 | 17 | cp rocket-chip/src/main/scala/system/Configs.scala $cexdata/Configs.scala 18 | git -C rocket-chip diff src/main/scala/system/Configs.scala > $cexdata/Configs.scala.diff 19 | 20 | vcd2fst rocket-syn/init.vcd $cexdata/init.fst 21 | 22 | for x in checks/*/{FAIL,ERROR} coverage/{FAIL,ERROR}; do 23 | test -f $x || continue 24 | x=${x%/FAIL} 25 | x=${x%/ERROR} 26 | y=${x#checks/} 27 | cp $x/logfile.txt $cexdata/$y.log 28 | if test -f $x/engine_*/trace.vcd; then 29 | cp $x/engine_*/trace.vcd $cexdata/$y.vcd 30 | if grep -q "^isa rv64" checks.cfg; then 31 | python3 disasm.py --64 $cexdata/$y.vcd > $cexdata/$y.asm 32 | fi 33 | if grep -q "^isa rv32" checks.cfg; then 34 | python3 disasm.py $cexdata/$y.vcd > $cexdata/$y.asm 35 | fi 36 | vcd2fst $cexdata/$y.vcd $cexdata/$y.fst 37 | rm -f $cexdata/$y.vcd 38 | fi 39 | done 40 | 41 | for x in checks/*.sby; do 42 | x=${x%.sby} 43 | x=${x#checks/} 44 | if [ -f checks/$x/PASS ]; then 45 | printf "%-20s %s %10s\n" $x pass $(sed '/Elapsed process time/ { s/.*\]: //; s/ .*//; p; }; d;' checks/$x/logfile.txt) 46 | elif [ -f checks/$x/FAIL ]; then 47 | printf "%-20s %s %10s\n" $x FAIL $(sed '/Elapsed process time/ { s/.*\]: //; s/ .*//; p; }; d;' checks/$x/logfile.txt) 48 | elif [ -f checks/$x/ERROR ]; then 49 | printf "%-20s %s\n" $x ERROR 50 | else 51 | printf "%-20s %s\n" $x unknown 52 | fi 53 | done | awk '{ print gensub(":", "", "g", $3), $0; }' | sort -n | cut -f2- -d' ' > $cexdata/status.txt 54 | 55 | rm -f $cexdata.zip 56 | zip -r $cexdata.zip $cexdata/ 57 | 58 | -------------------------------------------------------------------------------- /cores/rocket/checks.gtkw: -------------------------------------------------------------------------------- 1 | [*] 2 | [*] GTKWave Analyzer v3.3.65 (w)1999-2015 BSI 3 | [*] Tue Sep 12 08:17:07 2017 4 | [*] 5 | [dumpfile] "/home/clifford/Work/riscv-formal/cores/rocket/checks/pc_fwd_ch0/engine_0/trace.vcd" 6 | [dumpfile_mtime] "Tue Sep 12 00:05:15 2017" 7 | [dumpfile_size] 4236356 8 | [savefile] "/home/clifford/Work/riscv-formal/cores/rocket/checks.gtkw" 9 | [timestart] 218 10 | [size] 1024 1256 11 | [pos] 999 -429 12 | *-6.374269 285 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 13 | [treeopen] rvfi_testbench. 14 | [treeopen] rvfi_testbench.wrapper. 15 | [sst_width] 225 16 | [signals_width] 269 17 | [sst_expanded] 1 18 | [sst_vpaned_height] 391 19 | @24 20 | smt_step 21 | @28 22 | rvfi_testbench.checker_inst.reset 23 | rvfi_testbench.checker_inst.check 24 | @200 25 | - 26 | @22 27 | rvfi_testbench.checker_inst.insn_order[63:0] 28 | rvfi_testbench.checker_inst.expect_pc[31:0] 29 | @29 30 | rvfi_testbench.checker_inst.expect_pc_valid 31 | @200 32 | - 33 | -RVFI #0 34 | @28 35 | rvfi_testbench.wrapper.rvfi_channel_0.valid 36 | rvfi_testbench.wrapper.rvfi_channel_0.trap 37 | rvfi_testbench.wrapper.rvfi_channel_0.intr 38 | @24 39 | rvfi_testbench.wrapper.rvfi_channel_0.order[63:0] 40 | @22 41 | rvfi_testbench.wrapper.rvfi_channel_0.insn[31:0] 42 | rvfi_testbench.wrapper.rvfi_channel_0.pc_rdata[31:0] 43 | rvfi_testbench.wrapper.rvfi_channel_0.pc_wdata[31:0] 44 | @200 45 | - 46 | -RVFI #1 47 | @28 48 | rvfi_testbench.wrapper.rvfi_channel_1.valid 49 | rvfi_testbench.wrapper.rvfi_channel_1.trap 50 | rvfi_testbench.wrapper.rvfi_channel_1.intr 51 | @24 52 | rvfi_testbench.wrapper.rvfi_channel_1.order[63:0] 53 | @22 54 | rvfi_testbench.wrapper.rvfi_channel_1.insn[31:0] 55 | rvfi_testbench.wrapper.rvfi_channel_1.pc_rdata[31:0] 56 | rvfi_testbench.wrapper.rvfi_channel_1.pc_wdata[31:0] 57 | [pattern_trace] 1 58 | [pattern_trace] 0 59 | -------------------------------------------------------------------------------- /cores/rocket/cover.gtkw: -------------------------------------------------------------------------------- 1 | [*] 2 | [*] GTKWave Analyzer v3.3.89 (w)1999-2018 BSI 3 | [*] Wed Mar 28 21:36:23 2018 4 | [*] 5 | [dumpfile] "/home/clifford/Work/riscv-formal/cores/rocket/cover/engine_0/trace8.vcd" 6 | [dumpfile_mtime] "Wed Mar 28 21:28:42 2018" 7 | [dumpfile_size] 3363780 8 | [savefile] "/home/clifford/Work/riscv-formal/cores/rocket/cover.gtkw" 9 | [timestart] 0 10 | [size] 1400 947 11 | [pos] 471 0 12 | *-6.307628 100 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 13 | [treeopen] testbench. 14 | [treeopen] testbench.uut. 15 | [sst_width] 225 16 | [signals_width] 362 17 | [sst_expanded] 1 18 | [sst_vpaned_height] 277 19 | @28 20 | testbench.clk 21 | @200 22 | - 23 | @28 24 | testbench.rvfi_valid_ch0 25 | @22 26 | testbench.rvfi_insn_ch0[31:0] 27 | testbench.rvfi_pc_rdata_ch0[63:0] 28 | testbench.rvfi_mem_addr_ch0[63:0] 29 | @200 30 | - 31 | @28 32 | testbench.rvfi_valid_ch1 33 | @22 34 | testbench.rvfi_insn_ch1[31:0] 35 | testbench.rvfi_pc_rdata_ch1[63:0] 36 | testbench.rvfi_mem_addr_ch1[63:0] 37 | @200 38 | - 39 | @29 40 | testbench.p0o0 41 | @28 42 | testbench.p0o1 43 | testbench.p0o2 44 | testbench.p0o3m0 45 | testbench.p0o3m1 46 | testbench.p0o4m0 47 | testbench.p0o4m1 48 | testbench.p1o0 49 | testbench.p1o1 50 | testbench.p1o2 51 | testbench.p1o3m0 52 | testbench.p1o3m1 53 | testbench.p1o4m0 54 | testbench.p1o4m1 55 | @200 56 | - 57 | @28 58 | testbench.uut.tilelink_slave.channel_a_valid 59 | testbench.uut.tilelink_slave.channel_a_ready 60 | @22 61 | testbench.uut.tilelink_slave.channel_a_bits_size[3:0] 62 | testbench.uut.tilelink_slave.channel_a_bits_address[31:0] 63 | @200 64 | - 65 | @28 66 | testbench.uut.tilelink_slave.channel_d_valid 67 | testbench.uut.tilelink_slave.channel_d_ready 68 | @22 69 | testbench.uut.tilelink_slave.channel_d_bits_data[63:0] 70 | [pattern_trace] 1 71 | [pattern_trace] 0 72 | -------------------------------------------------------------------------------- /cores/rocket/cover.sby: -------------------------------------------------------------------------------- 1 | [options] 2 | mode cover 3 | tbtop uut.rocket 4 | depth 55 5 | 6 | [engines] 7 | smtbmc boolector 8 | 9 | [script] 10 | verilog_defines -D RISCV_FORMAL 11 | verilog_defines -D RISCV_FORMAL_NRET=2 12 | verilog_defines -D RISCV_FORMAL_XLEN=64 13 | verilog_defines -D RISCV_FORMAL_ILEN=32 14 | verilog_defines -D RISCV_FORMAL_COMPRESSED 15 | verilog_defines -D RISCV_FORMAL_FAIRNESS 16 | verilog_defines -D RISCV_FORMAL_CSR_MCYCLE 17 | verilog_defines -D RISCV_FORMAL_CSR_MISA 18 | verilog_defines -D ROCKET_NORESET 19 | read_verilog -sv rvfi_macros.vh 20 | read_verilog -sv rvfi_channel.sv 21 | read_verilog -sv wrapper.sv 22 | read_verilog -sv cover.sv 23 | read_ilang rocket-hier.il 24 | prep -flatten -top testbench 25 | 26 | [files] 27 | cover.sv 28 | wrapper.sv 29 | rocket-syn/rocket-hier.il 30 | ../../checks/rvfi_macros.vh 31 | ../../checks/rvfi_channel.sv 32 | -------------------------------------------------------------------------------- /cores/rocket/coverage.sby: -------------------------------------------------------------------------------- 1 | [options] 2 | mode bmc 3 | tbtop uut.rocket 4 | depth 20 5 | append 2 6 | 7 | [engines] 8 | smtbmc boolector 9 | 10 | [script] 11 | verilog_defines -D RISCV_FORMAL 12 | verilog_defines -D RISCV_FORMAL_NRET=2 13 | verilog_defines -D RISCV_FORMAL_XLEN=64 14 | verilog_defines -D RISCV_FORMAL_ILEN=32 15 | verilog_defines -D RISCV_FORMAL_COMPRESSED 16 | verilog_defines -D RISCV_FORMAL_FAIRNESS 17 | verilog_defines -D RISCV_FORMAL_CSR_MCYCLE 18 | verilog_defines -D ROCKET_NORESET 19 | read_verilog -sv rvfi_macros.vh 20 | read_verilog -sv rvfi_channel.sv 21 | read_verilog -sv riscv_rv64ic_insn.v 22 | read_verilog -sv wrapper.sv 23 | read_verilog -sv coverage.sv 24 | read_ilang rocket-hier.il 25 | prep -flatten -top testbench 26 | 27 | [files] 28 | coverage.sv 29 | wrapper.sv 30 | rocket-syn/rocket-hier.il 31 | ../../checks/rvfi_macros.vh 32 | ../../checks/rvfi_channel.sv 33 | ../../tests/coverage/riscv_rv64ic_insn.v 34 | -------------------------------------------------------------------------------- /cores/rocket/coverage.sv: -------------------------------------------------------------------------------- 1 | module testbench ( 2 | input clk, reset 3 | ); 4 | `RVFI_WIRES 5 | 6 | `RVFI_CHANNEL(rvfi_ch0, 0) 7 | `RVFI_CHANNEL(rvfi_ch1, 1) 8 | 9 | `ifdef YOSYS 10 | assume property (reset == $initstate); 11 | `endif 12 | 13 | rvfi_wrapper uut ( 14 | .clock (clk ), 15 | .reset (reset), 16 | `RVFI_CONN 17 | ); 18 | 19 | wire valid_ch0; 20 | wire valid_ch1; 21 | 22 | riscv_rv64ic_insn riscv_rv64ic_insn_ch0 ( 23 | .insn(rvfi_insn_ch0), 24 | .valid(valid_ch0) 25 | ); 26 | 27 | riscv_rv64ic_insn riscv_rv64ic_insn_ch1 ( 28 | .insn(rvfi_insn_ch1), 29 | .valid(valid_ch1) 30 | ); 31 | 32 | function [0:0] check_insn; 33 | input [31:0] insn; 34 | begin 35 | check_insn = 0; 36 | casez (insn) 37 | 32'b 0000000000000000_010_?00000?????_10:; // C.LWSP (fix pending) 38 | 32'b 0000000000000000_011_?00000?????_10:; // C.LDSP (fix pending) 39 | 32'b ???????_?????_?????_???_?????_1110011:; // SYSTEM 40 | 32'b ???????_?????_?????_000_?????_0001111:; // FENCE 41 | 32'b ???????_?????_?????_001_?????_0001111:; // FENCE.I 42 | 32'b 00010??_00000_?????_???_?????_0101111:; // LR.W 43 | 32'b 00011??_?????_?????_???_?????_0101111:; // SC.W 44 | 32'b 00001??_?????_?????_???_?????_0101111:; // AMOSWAP.W 45 | 32'b 00000??_?????_?????_???_?????_0101111:; // AMOADD.W 46 | 32'b 00100??_?????_?????_???_?????_0101111:; // AMOXOR.W 47 | 32'b 01100??_?????_?????_???_?????_0101111:; // AMOAND.W 48 | 32'b 01000??_?????_?????_???_?????_0101111:; // AMOOR.W 49 | 32'b 10000??_?????_?????_???_?????_0101111:; // AMOMIN.W 50 | 32'b 10100??_?????_?????_???_?????_0101111:; // AMOMAX.W 51 | 32'b 11000??_?????_?????_???_?????_0101111:; // AMOMINU.W 52 | 32'b 11100??_?????_?????_???_?????_0101111:; // AMOMAXU.W 53 | default: check_insn = 1; 54 | endcase 55 | end 56 | endfunction 57 | 58 | wire check_insn_ch0 = check_insn(rvfi_insn_ch0); 59 | wire check_insn_ch1 = check_insn(rvfi_insn_ch1); 60 | 61 | always @* begin 62 | if (!reset && rvfi_valid_ch0 && check_insn_ch0 && !rvfi_trap_ch0) begin 63 | assert (valid_ch0); 64 | end 65 | if (!reset && rvfi_valid_ch1 && check_insn_ch1 && !rvfi_trap_ch1) begin 66 | assert (valid_ch1); 67 | end 68 | end 69 | endmodule 70 | -------------------------------------------------------------------------------- /cores/rocket/decode.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | riscv=riscv32 3 | case "$1" in 4 | -a) mopt="-M numeric"; shift;; 5 | -n) mopt="-M no-aliases"; shift;; 6 | -an) mopt=""; shift;; 7 | -64) riscv=riscv64; shift;; 8 | *) mopt="-M numeric,no-aliases" 9 | esac 10 | for w; do echo ".word 0x${w#0x}"; done > decode.s 11 | ${riscv}-unknown-elf-gcc -c decode.s 12 | ${riscv}-unknown-elf-objdump -d $mopt decode.o | grep -A999 ^000 13 | rm -f decode.s decode.o 14 | -------------------------------------------------------------------------------- /cores/rocket/muldivlen.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python3 2 | 3 | import os 4 | from Verilog_VCD.Verilog_VCD import parse_vcd 5 | 6 | lines = list() 7 | 8 | for i in range(100): 9 | fn = None 10 | in1 = None 11 | in2 = None 12 | vcd = "muldivlen_cover/engine_0/trace%d.vcd" % i 13 | if not os.path.isfile(vcd): 14 | break 15 | for netinfo in parse_vcd(vcd).values(): 16 | for net in netinfo['nets']: 17 | if net["hier"] != "muldivlen": 18 | continue 19 | if net["name"] == "io_req_bits_fn": 20 | fn = netinfo['tv'][0][1] 21 | if net["name"] == "io_req_bits_in1": 22 | in1 = netinfo['tv'][0][1] 23 | if net["name"] == "io_req_bits_in2": 24 | in2 = netinfo['tv'][0][1] 25 | lines.append("%s %s %s" % (fn, in1, in2)) 26 | 27 | assert(len(lines) == 24) 28 | 29 | for line in sorted(lines): 30 | print(line) 31 | 32 | -------------------------------------------------------------------------------- /cores/rocket/muldivlen.sby: -------------------------------------------------------------------------------- 1 | [tasks] 2 | check 3 | cover 4 | 5 | [options] 6 | check: mode bmc 7 | cover: mode cover 8 | depth 100 9 | 10 | [engines] 11 | smtbmc yices 12 | 13 | [script] 14 | read_verilog freechips.rocketchip.system.DefaultConfigWithRVFIMonitors.v 15 | read_verilog -sv muldivlen.sv 16 | prep -nordff -top muldivlen 17 | chformal -assume -early 18 | opt_clean 19 | 20 | [files] 21 | rocket-chip/vsim/generated-src/freechips.rocketchip.system.DefaultConfigWithRVFIMonitors.v 22 | muldivlen.sv 23 | -------------------------------------------------------------------------------- /cores/rocket/testbench.cc: -------------------------------------------------------------------------------- 1 | #include "Vtestbench.h" 2 | #include "verilated.h" 3 | #include "verilated_vcd_c.h" 4 | 5 | int timer = 0; 6 | 7 | double sc_time_stamp() 8 | { 9 | return timer; 10 | } 11 | 12 | int main(int argc, char **argv, char **env) 13 | { 14 | Verilated::traceEverOn(true); 15 | 16 | Verilated::commandArgs(argc, argv); 17 | Vtestbench *tb = new Vtestbench; 18 | 19 | VerilatedVcdC *tfp = new VerilatedVcdC; 20 | tb->trace(tfp, 99); 21 | tfp->open("testbench.vcd"); 22 | 23 | tb->clock = 0; 24 | tb->eval(); 25 | tfp->dump(timer++); 26 | 27 | while (tb->genclock) 28 | { 29 | if (timer > 1) 30 | tb->clock = ~tb->clock; 31 | 32 | tb->eval(); 33 | tfp->dump(timer++); 34 | } 35 | 36 | tfp->close(); 37 | 38 | delete tfp; 39 | delete tb; 40 | 41 | return 0; 42 | } 43 | -------------------------------------------------------------------------------- /cores/rocket/testbench.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | set -ex 4 | 5 | use_iverilog=false 6 | tracetb=insncheck/insn_sw_ch0/engine_0/trace_tb.v 7 | 8 | egrep -v 'UUT.(core.rvfi_|core.io_status_dprv|core.csr.io_time|core.csr.io_status_dprv|frontend.icache.io_resp_bits)' $tracetb > testbench.v 9 | 10 | if $use_iverilog; then 11 | iverilog -o testbench -s testbench -DSIMULATION -DRANDOMIZE_REG_INIT -DRANDOMIZE_MEM_INIT testbench.v \ 12 | rocket-chip/vsim/generated-src/freechips.rocketchip.system.DefaultConfigWithRVFIMonitors.v \ 13 | rocket-chip/vsim/generated-src/freechips.rocketchip.system.DefaultConfigWithRVFIMonitors.behav_srams.v \ 14 | rocket-chip/vsrc/plusarg_reader.v rocket-chip/vsrc/RVFIMonitor.v 15 | ./testbench +vcd=testbench.vcd 16 | else 17 | verilator --exe --cc -Wno-fatal --top-module testbench --trace --trace-underscore -DSIMULATION testbench.v testbench.cc \ 18 | rocket-chip/vsim/generated-src/freechips.rocketchip.system.DefaultConfigWithRVFIMonitors.v \ 19 | rocket-chip/vsim/generated-src/freechips.rocketchip.system.DefaultConfigWithRVFIMonitors.behav_srams.v \ 20 | rocket-chip/vsrc/plusarg_reader.v rocket-chip/vsrc/RVFIMonitor.v 21 | make -C obj_dir -f Vtestbench.mk 22 | ./obj_dir/Vtestbench 23 | fi 24 | 25 | -------------------------------------------------------------------------------- /cores/serv/.gitignore: -------------------------------------------------------------------------------- 1 | /checks 2 | /cover 3 | /serv-src 4 | /cexdata 5 | /cexdata.zip 6 | /disasm.s 7 | /disasm.o 8 | -------------------------------------------------------------------------------- /cores/serv/README.md: -------------------------------------------------------------------------------- 1 | riscv-formal proofs for SErial RiscV (SERV) 2 | =========================================== 3 | 4 | Quickstart guide: 5 | 6 | First install Yosys, SymbiYosys, and the solvers. See 7 | [here](http://symbiyosys.readthedocs.io/en/latest/quickstart.html#installing) 8 | for instructions. Then build the version of SERV with RVFI support and 9 | rsicv-tools, and generate the formal checks: 10 | 11 | ``` 12 | bash generate.sh 13 | ``` 14 | 15 | Then run the formal checks: 16 | 17 | ``` 18 | make -C checks -j$(nproc) 19 | bash cexdata.sh 20 | ``` 21 | -------------------------------------------------------------------------------- /cores/serv/cexdata.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | set -ex 4 | 5 | rm -rf cexdata 6 | mkdir cexdata 7 | 8 | while read dir; do echo "$dir $(git -C $dir log -n1 --oneline)"; \ 9 | done < <( echo .; find serv-src -name '.git' -printf '%h\n'; ) | \ 10 | expand -t30 > cexdata/version.txt 11 | 12 | for x in checks/*/FAIL; do 13 | test -f $x || continue 14 | x=${x%/FAIL} 15 | y=${x#checks/} 16 | cp $x/logfile.txt cexdata/$y.log 17 | if test -f $x/engine_*/trace.vcd; then 18 | cp $x/engine_*/trace.vcd cexdata/$y.vcd 19 | if grep -q "^isa rv64" checks.cfg; then 20 | python3 disasm.py --64 cexdata/$y.vcd > cexdata/$y.asm 21 | fi 22 | if grep -q "^isa rv32" checks.cfg; then 23 | python3 disasm.py cexdata/$y.vcd > cexdata/$y.asm 24 | fi 25 | fi 26 | done 27 | 28 | for x in checks/*.sby; do 29 | x=${x%.sby} 30 | x=${x#checks/} 31 | if [ -f checks/$x/PASS ]; then 32 | printf "%-20s %s %10s\n" $x pass $(sed '/Elapsed process time/ { s/.*\]: //; s/ .*//; p; }; d;' checks/$x/logfile.txt) 33 | elif [ -f checks/$x/FAIL ]; then 34 | printf "%-20s %s %10s\n" $x FAIL $(sed '/Elapsed process time/ { s/.*\]: //; s/ .*//; p; }; d;' checks/$x/logfile.txt) 35 | else 36 | printf "%-20s %s\n" $x unknown 37 | fi 38 | done | awk '{ print gensub(":", "", "g", $3), $0; }' | sort -n | cut -f2- -d' ' > cexdata/status.txt 39 | 40 | rm -f cexdata.zip 41 | zip -r cexdata.zip cexdata/ 42 | 43 | -------------------------------------------------------------------------------- /cores/serv/checks.cfg: -------------------------------------------------------------------------------- 1 | [options] 2 | isa rv32i 3 | nret 1 4 | 5 | [depth] 6 | insn 80 7 | reg 1 80 8 | pc_fwd 1 80 9 | pc_bwd 1 80 10 | liveness 1 40 80 11 | unique 1 40 80 12 | causal 1 80 13 | 14 | [defines] 15 | `define RISCV_FORMAL_ALIGNED_MEM 16 | 17 | [script-sources] 18 | read_verilog -sv @basedir@/cores/@core@/wrapper.sv 19 | read_verilog -sv -defer @basedir@/cores/@core@/serv-src/rtl/ser_add.v 20 | read_verilog -sv -defer @basedir@/cores/@core@/serv-src/rtl/ser_lt.v 21 | read_verilog -sv -defer @basedir@/cores/@core@/serv-src/rtl/ser_shift.v 22 | read_verilog -sv -defer @basedir@/cores/@core@/serv-src/rtl/serv_alu.v 23 | read_verilog -sv -defer @basedir@/cores/@core@/serv-src/rtl/serv_bufreg.v 24 | read_verilog -sv -defer @basedir@/cores/@core@/serv-src/rtl/serv_csr.v 25 | read_verilog -sv -defer @basedir@/cores/@core@/serv-src/rtl/serv_ctrl.v 26 | read_verilog -sv -defer @basedir@/cores/@core@/serv-src/rtl/serv_decode.v 27 | read_verilog -sv -defer @basedir@/cores/@core@/serv-src/rtl/serv_mem_if.v 28 | read_verilog -sv -defer @basedir@/cores/@core@/serv-src/rtl/serv_mpram.v 29 | read_verilog -sv -defer @basedir@/cores/@core@/serv-src/rtl/serv_params.vh 30 | read_verilog -sv -defer @basedir@/cores/@core@/serv-src/rtl/serv_regfile.v 31 | read_verilog -sv -defer @basedir@/cores/@core@/serv-src/rtl/serv_top.v 32 | read_verilog -sv -defer @basedir@/cores/@core@/serv-src/rtl/shift_reg.v 33 | -------------------------------------------------------------------------------- /cores/serv/cover.gtkw: -------------------------------------------------------------------------------- 1 | [*] 2 | [*] GTKWave Analyzer v3.3.89 (w)1999-2018 BSI 3 | [*] Thu Nov 1 11:25:45 2018 4 | [*] 5 | [dumpfile] "/home/clifford/Work/riscv-formal/cores/serv/cover/engine_0/trace0.vcd" 6 | [dumpfile_mtime] "Thu Nov 1 11:24:51 2018" 7 | [dumpfile_size] 121959 8 | [savefile] "/home/clifford/Work/riscv-formal/cores/serv/cover.gtkw" 9 | [timestart] 0 10 | [size] 1394 830 11 | [pos] -1 -1 12 | *-5.990967 5 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 13 | [treeopen] testbench. 14 | [treeopen] testbench.wrapper. 15 | [sst_width] 225 16 | [signals_width] 310 17 | [sst_expanded] 1 18 | [sst_vpaned_height] 241 19 | @24 20 | testbench.cycle[31:0] 21 | testbench.wrapper.icnt[31:0] 22 | @25 23 | testbench.wrapper.dcnt[31:0] 24 | @200 25 | - 26 | @28 27 | testbench.wrapper.clock 28 | testbench.wrapper.reset 29 | @200 30 | - 31 | -I-MEM 32 | @28 33 | testbench.wrapper.o_i_ca_vld 34 | testbench.wrapper.i_i_ca_rdy 35 | @22 36 | testbench.wrapper.o_i_ca_adr[31:0] 37 | @200 38 | - 39 | @28 40 | testbench.wrapper.i_i_rd_vld 41 | testbench.wrapper.o_i_rd_rdy 42 | @22 43 | testbench.wrapper.i_i_rd_dat[31:0] 44 | @200 45 | - 46 | -D-MEM 47 | @28 48 | testbench.wrapper.o_d_ca_vld 49 | testbench.wrapper.i_d_ca_rdy 50 | testbench.wrapper.o_d_ca_cmd 51 | @22 52 | testbench.wrapper.o_d_ca_adr[31:0] 53 | @200 54 | - 55 | @28 56 | testbench.wrapper.o_d_dm_vld 57 | testbench.wrapper.i_d_dm_rdy 58 | @22 59 | testbench.wrapper.o_d_dm_dat[31:0] 60 | testbench.wrapper.o_d_dm_msk[3:0] 61 | @200 62 | - 63 | @28 64 | testbench.wrapper.i_d_rd_vld 65 | testbench.wrapper.o_d_rd_rdy 66 | @22 67 | testbench.wrapper.i_d_rd_dat[31:0] 68 | @200 69 | - 70 | -RVFI 71 | @28 72 | testbench.wrapper.rvfi_valid 73 | @22 74 | testbench.wrapper.rvfi_insn[31:0] 75 | testbench.wrapper.rvfi_pc_rdata[31:0] 76 | @200 77 | - 78 | - 79 | [pattern_trace] 1 80 | [pattern_trace] 0 81 | -------------------------------------------------------------------------------- /cores/serv/cover.sby: -------------------------------------------------------------------------------- 1 | [options] 2 | mode cover 3 | append 0 4 | tbtop wrapper.uut 5 | depth 150 6 | 7 | [engines] 8 | smtbmc boolector 9 | 10 | [script] 11 | read_verilog -sv defines.sv 12 | read_verilog -sv cover.sv 13 | read_verilog -sv wrapper.sv 14 | read_verilog -sv -defer sbram.sv 15 | read_verilog -sv -defer camd_ram.v 16 | read_verilog -sv -defer ser_add.v 17 | read_verilog -sv -defer ser_eq.v 18 | read_verilog -sv -defer ser_lt.v 19 | read_verilog -sv -defer ser_shift.v 20 | read_verilog -sv -defer serv_alu.v 21 | read_verilog -sv -defer serv_ctrl.v 22 | read_verilog -sv -defer serv_decode.v 23 | read_verilog -sv -defer serv_mem_if.v 24 | read_verilog -sv -defer serv_params.vh 25 | read_verilog -sv -defer serv_regfile.v 26 | read_verilog -sv -defer serv_top.v 27 | read_verilog -sv -defer shift_reg.v 28 | prep -flatten -nordff -top testbench 29 | 30 | [files] 31 | cover.sv 32 | wrapper.sv 33 | sbram.sv 34 | serv-src/rtl/camd_ram.v 35 | serv-src/rtl/ser_add.v 36 | serv-src/rtl/ser_eq.v 37 | serv-src/rtl/ser_lt.v 38 | serv-src/rtl/ser_shift.v 39 | serv-src/rtl/serv_alu.v 40 | serv-src/rtl/serv_ctrl.v 41 | serv-src/rtl/serv_decode.v 42 | serv-src/rtl/serv_mem_if.v 43 | serv-src/rtl/serv_params.vh 44 | serv-src/rtl/serv_regfile.v 45 | serv-src/rtl/serv_top.v 46 | serv-src/rtl/shift_reg.v 47 | ../../checks/rvfi_macros.vh 48 | 49 | [file defines.sv] 50 | `define RISCV_FORMAL 51 | `define RISCV_FORMAL_NRET 1 52 | `define RISCV_FORMAL_XLEN 32 53 | `define RISCV_FORMAL_ILEN 32 54 | `define RISCV_FORMAL_RESET_CYCLES 1 55 | `define RISCV_FORMAL_CHECK_CYCLE 20 56 | `define RISCV_FORMAL_CHANNEL_IDX 0 57 | `define RISCV_FORMAL_CHECKER rvfi_insn_check 58 | `define RISCV_FORMAL_INSN_MODEL rvfi_insn_add 59 | `define RISCV_FORMAL_ALIGNED_MEM 60 | `define MEMIO_FAIRNESS 61 | `include "rvfi_macros.vh" 62 | -------------------------------------------------------------------------------- /cores/serv/cover.sv: -------------------------------------------------------------------------------- 1 | module testbench ( 2 | input clock, 3 | input reset, 4 | `RVFI_OUTPUTS 5 | ); 6 | rvfi_wrapper wrapper ( 7 | .clock(clock), 8 | .reset(reset), 9 | `RVFI_CONN 10 | ); 11 | 12 | integer cycle = 0; 13 | always @(posedge clock) cycle <= cycle + 1; 14 | 15 | always @(posedge clock) begin 16 | assume (reset == (cycle == 0)); 17 | cover (rvfi_valid); 18 | end 19 | endmodule 20 | -------------------------------------------------------------------------------- /cores/serv/disasm.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python3 2 | 3 | from Verilog_VCD.Verilog_VCD import parse_vcd 4 | from os import system 5 | from sys import argv, exit 6 | from getopt import getopt 7 | 8 | def usage(): 9 | print("Usage: %s " % argv[0]) 10 | exit(1) 11 | 12 | try: 13 | opts, args = getopt(argv[1:], "", []) 14 | except: 15 | usage() 16 | 17 | for o, a in opts: 18 | if o == "--64": 19 | pass 20 | else: 21 | usage() 22 | 23 | if len(args) != 1: 24 | usage() 25 | 26 | rvfi_valid = None 27 | rvfi_order = None 28 | rvfi_insn = None 29 | 30 | for netinfo in parse_vcd(args[0]).values(): 31 | for net in netinfo['nets']: 32 | # print(net["hier"], net["name"]) 33 | if net["hier"] in ["rvfi_testbench.wrapper"] and net["name"] == "rvfi_valid": 34 | rvfi_valid = netinfo['tv'] 35 | if net["hier"] in ["rvfi_testbench.wrapper"] and net["name"] == "rvfi_order": 36 | rvfi_order = netinfo['tv'] 37 | if net["hier"] in ["rvfi_testbench.wrapper"] and net["name"] == "rvfi_insn": 38 | rvfi_insn = netinfo['tv'] 39 | 40 | assert len(rvfi_valid) == len(rvfi_order) 41 | assert len(rvfi_valid) == len(rvfi_insn) 42 | 43 | prog = list() 44 | 45 | for tv_valid, tv_order, tv_insn in zip(rvfi_valid, rvfi_order, rvfi_insn): 46 | if tv_valid[1] == '1': 47 | prog.append((int(tv_order[1], 2), int(tv_insn[1], 2))) 48 | 49 | with open("disasm.s", "w") as f: 50 | for tv_order, tv_insn in sorted(prog): 51 | if tv_insn & 3 != 3 and tv_insn & 0xffff0000 == 0: 52 | print(".hword 0x%04x # %d" % (tv_insn, tv_order), file=f) 53 | else: 54 | print(".word 0x%08x # %d" % (tv_insn, tv_order), file=f) 55 | 56 | system("/opt/riscv32imc/bin/riscv32-unknown-elf-gcc -c disasm.s") 57 | system("/opt/riscv32imc/bin/riscv32-unknown-elf-objdump -d -M numeric,no-aliases disasm.o") 58 | 59 | -------------------------------------------------------------------------------- /cores/serv/generate.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | set -ex 3 | rm -rf serv-src 4 | git clone git@github.com:olofk/serv.git serv-src 5 | sed -i -e '/define RISCV_FORMAL/ d;' serv-src/rtl/serv_top.v 6 | python3 ../../checks/genchecks.py 7 | -------------------------------------------------------------------------------- /cores/serv/wrapper.sv: -------------------------------------------------------------------------------- 1 | module rvfi_wrapper ( 2 | input clock, 3 | input reset, 4 | `RVFI_OUTPUTS 5 | ); 6 | // I-MEM 7 | (* keep *) wire [31:0] ibus_adr; 8 | (* keep *) wire ibus_cyc; 9 | (* keep *) rand reg [31:0] ibus_rdt; 10 | (* keep *) rand reg ibus_ack; 11 | 12 | // D-MEM 13 | (* keep *) wire [31:0] dbus_adr; 14 | (* keep *) wire [31:0] dbus_dat; 15 | (* keep *) wire [3:0] dbus_sel; 16 | (* keep *) wire dbus_we; 17 | (* keep *) wire dbus_cyc; 18 | (* keep *) rand reg [31:0] dbus_rdt; 19 | (* keep *) rand reg dbus_ack; 20 | 21 | serv_top uut ( 22 | .clk(clock), 23 | .i_rst(reset), 24 | .i_timer_irq(1'b0), 25 | 26 | `RVFI_CONN, 27 | 28 | .o_ibus_adr(ibus_adr), 29 | .o_ibus_cyc(ibus_cyc), 30 | .i_ibus_rdt(ibus_rdt), 31 | .i_ibus_ack(ibus_ack), 32 | .o_dbus_adr(dbus_adr), 33 | .o_dbus_dat(dbus_dat), 34 | .o_dbus_sel(dbus_sel), 35 | .o_dbus_we (dbus_we ), 36 | .o_dbus_cyc(dbus_cyc), 37 | .i_dbus_rdt(dbus_rdt), 38 | .i_dbus_ack(dbus_ack) 39 | ); 40 | 41 | // I-MEM 42 | always @(posedge clock) begin 43 | if (reset) begin 44 | assume (!ibus_ack); 45 | end 46 | if (!ibus_cyc) begin 47 | assume (!ibus_ack); 48 | end 49 | end 50 | 51 | // D-MEM 52 | always @(posedge clock) begin 53 | if (reset) begin 54 | assume (!dbus_ack); 55 | end 56 | if (!dbus_cyc) begin 57 | assume (!dbus_ack); 58 | end 59 | end 60 | 61 | `ifdef MEMIO_FAIRNESS 62 | reg [2:0] timeout_ibus = 0; 63 | reg [2:0] timeout_dbus = 0; 64 | 65 | always @(posedge clock) begin 66 | timeout_ibus <= 0; 67 | timeout_dbus <= 0; 68 | 69 | if (ibus_cyc && !ibus_ack) 70 | timeout_ibus <= timeout_ibus + 1; 71 | 72 | if (dbus_cyc && !dbus_ack) 73 | timeout_dbus <= timeout_dbus + 1; 74 | 75 | assume (!timeout_ibus[2]); 76 | assume (!timeout_dbus[2]); 77 | end 78 | `endif 79 | endmodule 80 | -------------------------------------------------------------------------------- /docs/csrs.md: -------------------------------------------------------------------------------- 1 | RISC-V Formal CSR Sematics 2 | ========================== 3 | 4 | For the most part the CSR values output via RVFI match exactly the CSR values 5 | observable via the ISA. But there are a few minor differences that are outlined 6 | here. 7 | 8 | Most importantly, for RV64 processors in RV32 mode, the values output via 9 | RVFI are still following RV64 CSR encondings, including some of the information 10 | that is not available through the RV32 ISA, such as SXL and UXL in `mstatus`. 11 | 12 | Counters are always output as singe 64-bit wide CSRs even on RV32 targets. 13 | 14 | M-mode CSRs 15 | ----------- 16 | 17 | ### Machine Information Registers 18 | 19 | #### mvendorid, marchid, mimpid, mhartid 20 | 21 | Nothing special for these CSRs. 22 | 23 | ### Machine Trap Setup 24 | 25 | #### mstatus, misa 26 | 27 | Nothing special for these CSRs. (Reminder: RV64 processors in RV32 mode are 28 | expected to output the RV64 format.) 29 | 30 | #### medeleg, mideleg, mie, mtvec 31 | 32 | Nothing special for these CSRs. 33 | 34 | #### mcounteren 35 | 36 | Currently only the `IR` and `CY` bits of `mcounteren` are supported by 37 | riscv-formal. The other bits are ignored. 38 | 39 | ### Machine Trap Handling 40 | 41 | #### mscratch 42 | 43 | Nothing special for this CSR. 44 | 45 | #### mepc 46 | 47 | The version of `mepc` observable through the ISA masks `mepc[1]` on CSR reads 48 | when the processor is in a mode that does not supprt 16-bit instruction 49 | alignment. However, writes to that bit shall still modify the underlying 50 | architectural state. 51 | 52 | In riscv-formal semantics the `mepc` value output via RVFI must be the actual 53 | architectural state with `mepc[1]` not masked. 54 | 55 | #### mcause, mtval, mip 56 | 57 | Nothing special for these CSRs. 58 | 59 | ### Machine Protection and Translation 60 | 61 | TBD 62 | 63 | ### Machine Counter/Timers 64 | 65 | #### mcycle, minstret 66 | 67 | Always 64-bit wide, even on pure RV32 processors (no mcycleh/minstreth). 68 | 69 | Incrementing those counters should happen "between instructions", this means 70 | for example that an instruction that isn't a CSR write to `mcycle` should 71 | always have `rvfi_csr_mcycle_rdata == rvfi_csr_mcycle_wdata`. 72 | 73 | #### mhpmcounter, mhpmevent 74 | 75 | Machine performance-monitoring counters are currently not supported by riscv-formal. 76 | 77 | Debug-Mode CSRs 78 | --------------- 79 | 80 | TBD 81 | 82 | U-Mode CSRs 83 | ----------- 84 | 85 | TBD 86 | 87 | S-Mode CSRs 88 | ----------- 89 | 90 | TBD 91 | -------------------------------------------------------------------------------- /docs/references.md: -------------------------------------------------------------------------------- 1 | 2 | References and related work 3 | =========================== 4 | 5 | ARM's [ISA-Formal Framework](https://alastairreid.github.io/papers/cav2016_isa_formal.pdf) follows a similar set of ideas and has inspired the work on `riscv-formal`. 6 | 7 | Other RISC-V formal verification projects and related materials: 8 | 9 | - [Kami: A Framework for (RISC-V) HW Verification](https://riscv.org/wp-content/uploads/2016/07/Wed1130_Kami_Framework_Murali_Vijayaraghavan.pdf) ([kami on github](https://github.com/mit-plv/kami)) 10 | - [Rewrite of Kami by SiFive](https://github.com/sifive/Kami) 11 | - [Verifying a RISC-V Processor, Nirav Dave, Prashanth Mundkur, SRI International](https://riscv.org/wp-content/uploads/2015/06/riscv-verification-workshop-june2015.pdf) ([l3riscv on github](https://github.com/SRI-CSL/l3riscv)) 12 | - [RISC-V ISA Model in Bluespec BSV by Rishiyur S. Nikhil](https://github.com/rsnikhil/RISCV_ISA_Formal_Spec_in_BSV) 13 | - [RISC-V ISA Model in Haskell by Adam Chlipala and group (MIT)](https://github.com/mit-plv/riscv-semantics) 14 | - [RISC-V ISA Specification in Coq by MIT CSAIL](https://github.com/mit-plv/riscv-coq) 15 | - [RISC-V ISA Specification in Coq by SiFive](https://github.com/sifive/RiscvSpecFormal) 16 | - [RISC-V ISA specification work in Sail 2](https://github.com/rems-project/sail/tree/sail2/riscv) 17 | - [Sail: a language for describing instruction semantics](http://www.cl.cam.ac.uk/~pes20/sail/) 18 | - [riscv-fs: F# RISC-V Instruction Set formal specification](https://github.com/mrLSD/riscv-fs) 19 | 20 | Please [open an issue](https://github.com/cliffordwolf/riscv-formal/issues/new) if you know of other RISC-V formal verification projects I should link to in this section. 21 | 22 | -------------------------------------------------------------------------------- /insns/insn_add.v: -------------------------------------------------------------------------------- 1 | // DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py 2 | 3 | module rvfi_insn_add ( 4 | input rvfi_valid, 5 | input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, 6 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, 7 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, 8 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, 9 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, 10 | `ifdef RISCV_FORMAL_CSR_MISA 11 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, 12 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, 13 | `endif 14 | 15 | output spec_valid, 16 | output spec_trap, 17 | output [ 4 : 0] spec_rs1_addr, 18 | output [ 4 : 0] spec_rs2_addr, 19 | output [ 4 : 0] spec_rd_addr, 20 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, 21 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, 22 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, 23 | output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, 24 | output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, 25 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata 26 | ); 27 | 28 | // R-type instruction format 29 | wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 32; 30 | wire [6:0] insn_funct7 = rvfi_insn[31:25]; 31 | wire [4:0] insn_rs2 = rvfi_insn[24:20]; 32 | wire [4:0] insn_rs1 = rvfi_insn[19:15]; 33 | wire [2:0] insn_funct3 = rvfi_insn[14:12]; 34 | wire [4:0] insn_rd = rvfi_insn[11: 7]; 35 | wire [6:0] insn_opcode = rvfi_insn[ 6: 0]; 36 | 37 | `ifdef RISCV_FORMAL_CSR_MISA 38 | wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 0) == `RISCV_FORMAL_XLEN'h 0; 39 | assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 0; 40 | `else 41 | wire misa_ok = 1; 42 | `endif 43 | 44 | // ADD instruction 45 | wire [`RISCV_FORMAL_XLEN-1:0] result = rvfi_rs1_rdata + rvfi_rs2_rdata; 46 | assign spec_valid = rvfi_valid && !insn_padding && insn_funct7 == 7'b 0000000 && insn_funct3 == 3'b 000 && insn_opcode == 7'b 0110011; 47 | assign spec_rs1_addr = insn_rs1; 48 | assign spec_rs2_addr = insn_rs2; 49 | assign spec_rd_addr = insn_rd; 50 | assign spec_rd_wdata = spec_rd_addr ? result : 0; 51 | assign spec_pc_wdata = rvfi_pc_rdata + 4; 52 | 53 | // default assignments 54 | assign spec_trap = !misa_ok; 55 | assign spec_mem_addr = 0; 56 | assign spec_mem_rmask = 0; 57 | assign spec_mem_wmask = 0; 58 | assign spec_mem_wdata = 0; 59 | endmodule 60 | -------------------------------------------------------------------------------- /insns/insn_addi.v: -------------------------------------------------------------------------------- 1 | // DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py 2 | 3 | module rvfi_insn_addi ( 4 | input rvfi_valid, 5 | input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, 6 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, 7 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, 8 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, 9 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, 10 | `ifdef RISCV_FORMAL_CSR_MISA 11 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, 12 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, 13 | `endif 14 | 15 | output spec_valid, 16 | output spec_trap, 17 | output [ 4 : 0] spec_rs1_addr, 18 | output [ 4 : 0] spec_rs2_addr, 19 | output [ 4 : 0] spec_rd_addr, 20 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, 21 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, 22 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, 23 | output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, 24 | output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, 25 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata 26 | ); 27 | 28 | // I-type instruction format 29 | wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 32; 30 | wire [`RISCV_FORMAL_XLEN-1:0] insn_imm = $signed(rvfi_insn[31:20]); 31 | wire [4:0] insn_rs1 = rvfi_insn[19:15]; 32 | wire [2:0] insn_funct3 = rvfi_insn[14:12]; 33 | wire [4:0] insn_rd = rvfi_insn[11: 7]; 34 | wire [6:0] insn_opcode = rvfi_insn[ 6: 0]; 35 | 36 | `ifdef RISCV_FORMAL_CSR_MISA 37 | wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 0) == `RISCV_FORMAL_XLEN'h 0; 38 | assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 0; 39 | `else 40 | wire misa_ok = 1; 41 | `endif 42 | 43 | // ADDI instruction 44 | wire [`RISCV_FORMAL_XLEN-1:0] result = rvfi_rs1_rdata + insn_imm; 45 | assign spec_valid = rvfi_valid && !insn_padding && insn_funct3 == 3'b 000 && insn_opcode == 7'b 0010011; 46 | assign spec_rs1_addr = insn_rs1; 47 | assign spec_rd_addr = insn_rd; 48 | assign spec_rd_wdata = spec_rd_addr ? result : 0; 49 | assign spec_pc_wdata = rvfi_pc_rdata + 4; 50 | 51 | // default assignments 52 | assign spec_rs2_addr = 0; 53 | assign spec_trap = !misa_ok; 54 | assign spec_mem_addr = 0; 55 | assign spec_mem_rmask = 0; 56 | assign spec_mem_wmask = 0; 57 | assign spec_mem_wdata = 0; 58 | endmodule 59 | -------------------------------------------------------------------------------- /insns/insn_addiw.v: -------------------------------------------------------------------------------- 1 | // DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py 2 | 3 | module rvfi_insn_addiw ( 4 | input rvfi_valid, 5 | input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, 6 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, 7 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, 8 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, 9 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, 10 | `ifdef RISCV_FORMAL_CSR_MISA 11 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, 12 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, 13 | `endif 14 | 15 | output spec_valid, 16 | output spec_trap, 17 | output [ 4 : 0] spec_rs1_addr, 18 | output [ 4 : 0] spec_rs2_addr, 19 | output [ 4 : 0] spec_rd_addr, 20 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, 21 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, 22 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, 23 | output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, 24 | output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, 25 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata 26 | ); 27 | 28 | // I-type instruction format 29 | wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 32; 30 | wire [`RISCV_FORMAL_XLEN-1:0] insn_imm = $signed(rvfi_insn[31:20]); 31 | wire [4:0] insn_rs1 = rvfi_insn[19:15]; 32 | wire [2:0] insn_funct3 = rvfi_insn[14:12]; 33 | wire [4:0] insn_rd = rvfi_insn[11: 7]; 34 | wire [6:0] insn_opcode = rvfi_insn[ 6: 0]; 35 | 36 | `ifdef RISCV_FORMAL_CSR_MISA 37 | wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 0) == `RISCV_FORMAL_XLEN'h 0; 38 | assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 0; 39 | `else 40 | wire misa_ok = 1; 41 | `endif 42 | 43 | // ADDIW instruction 44 | wire [31:0] result = rvfi_rs1_rdata[31:0] + insn_imm[31:0]; 45 | assign spec_valid = rvfi_valid && !insn_padding && insn_funct3 == 3'b 000 && insn_opcode == 7'b 0011011; 46 | assign spec_rs1_addr = insn_rs1; 47 | assign spec_rd_addr = insn_rd; 48 | assign spec_rd_wdata = spec_rd_addr ? {{`RISCV_FORMAL_XLEN-32{result[31]}}, result} : 0; 49 | assign spec_pc_wdata = rvfi_pc_rdata + 4; 50 | 51 | // default assignments 52 | assign spec_rs2_addr = 0; 53 | assign spec_trap = !misa_ok; 54 | assign spec_mem_addr = 0; 55 | assign spec_mem_rmask = 0; 56 | assign spec_mem_wmask = 0; 57 | assign spec_mem_wdata = 0; 58 | endmodule 59 | -------------------------------------------------------------------------------- /insns/insn_addw.v: -------------------------------------------------------------------------------- 1 | // DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py 2 | 3 | module rvfi_insn_addw ( 4 | input rvfi_valid, 5 | input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, 6 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, 7 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, 8 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, 9 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, 10 | `ifdef RISCV_FORMAL_CSR_MISA 11 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, 12 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, 13 | `endif 14 | 15 | output spec_valid, 16 | output spec_trap, 17 | output [ 4 : 0] spec_rs1_addr, 18 | output [ 4 : 0] spec_rs2_addr, 19 | output [ 4 : 0] spec_rd_addr, 20 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, 21 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, 22 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, 23 | output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, 24 | output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, 25 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata 26 | ); 27 | 28 | // R-type instruction format 29 | wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 32; 30 | wire [6:0] insn_funct7 = rvfi_insn[31:25]; 31 | wire [4:0] insn_rs2 = rvfi_insn[24:20]; 32 | wire [4:0] insn_rs1 = rvfi_insn[19:15]; 33 | wire [2:0] insn_funct3 = rvfi_insn[14:12]; 34 | wire [4:0] insn_rd = rvfi_insn[11: 7]; 35 | wire [6:0] insn_opcode = rvfi_insn[ 6: 0]; 36 | 37 | `ifdef RISCV_FORMAL_CSR_MISA 38 | wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 0) == `RISCV_FORMAL_XLEN'h 0; 39 | assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 0; 40 | `else 41 | wire misa_ok = 1; 42 | `endif 43 | 44 | // ADDW instruction 45 | wire [31:0] result = rvfi_rs1_rdata[31:0] + rvfi_rs2_rdata[31:0]; 46 | assign spec_valid = rvfi_valid && !insn_padding && insn_funct7 == 7'b 0000000 && insn_funct3 == 3'b 000 && insn_opcode == 7'b 0111011; 47 | assign spec_rs1_addr = insn_rs1; 48 | assign spec_rs2_addr = insn_rs2; 49 | assign spec_rd_addr = insn_rd; 50 | assign spec_rd_wdata = spec_rd_addr ? {{`RISCV_FORMAL_XLEN-32{result[31]}}, result} : 0; 51 | assign spec_pc_wdata = rvfi_pc_rdata + 4; 52 | 53 | // default assignments 54 | assign spec_trap = !misa_ok; 55 | assign spec_mem_addr = 0; 56 | assign spec_mem_rmask = 0; 57 | assign spec_mem_wmask = 0; 58 | assign spec_mem_wdata = 0; 59 | endmodule 60 | -------------------------------------------------------------------------------- /insns/insn_and.v: -------------------------------------------------------------------------------- 1 | // DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py 2 | 3 | module rvfi_insn_and ( 4 | input rvfi_valid, 5 | input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, 6 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, 7 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, 8 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, 9 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, 10 | `ifdef RISCV_FORMAL_CSR_MISA 11 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, 12 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, 13 | `endif 14 | 15 | output spec_valid, 16 | output spec_trap, 17 | output [ 4 : 0] spec_rs1_addr, 18 | output [ 4 : 0] spec_rs2_addr, 19 | output [ 4 : 0] spec_rd_addr, 20 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, 21 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, 22 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, 23 | output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, 24 | output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, 25 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata 26 | ); 27 | 28 | // R-type instruction format 29 | wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 32; 30 | wire [6:0] insn_funct7 = rvfi_insn[31:25]; 31 | wire [4:0] insn_rs2 = rvfi_insn[24:20]; 32 | wire [4:0] insn_rs1 = rvfi_insn[19:15]; 33 | wire [2:0] insn_funct3 = rvfi_insn[14:12]; 34 | wire [4:0] insn_rd = rvfi_insn[11: 7]; 35 | wire [6:0] insn_opcode = rvfi_insn[ 6: 0]; 36 | 37 | `ifdef RISCV_FORMAL_CSR_MISA 38 | wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 0) == `RISCV_FORMAL_XLEN'h 0; 39 | assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 0; 40 | `else 41 | wire misa_ok = 1; 42 | `endif 43 | 44 | // AND instruction 45 | wire [`RISCV_FORMAL_XLEN-1:0] result = rvfi_rs1_rdata & rvfi_rs2_rdata; 46 | assign spec_valid = rvfi_valid && !insn_padding && insn_funct7 == 7'b 0000000 && insn_funct3 == 3'b 111 && insn_opcode == 7'b 0110011; 47 | assign spec_rs1_addr = insn_rs1; 48 | assign spec_rs2_addr = insn_rs2; 49 | assign spec_rd_addr = insn_rd; 50 | assign spec_rd_wdata = spec_rd_addr ? result : 0; 51 | assign spec_pc_wdata = rvfi_pc_rdata + 4; 52 | 53 | // default assignments 54 | assign spec_trap = !misa_ok; 55 | assign spec_mem_addr = 0; 56 | assign spec_mem_rmask = 0; 57 | assign spec_mem_wmask = 0; 58 | assign spec_mem_wdata = 0; 59 | endmodule 60 | -------------------------------------------------------------------------------- /insns/insn_andi.v: -------------------------------------------------------------------------------- 1 | // DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py 2 | 3 | module rvfi_insn_andi ( 4 | input rvfi_valid, 5 | input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, 6 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, 7 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, 8 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, 9 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, 10 | `ifdef RISCV_FORMAL_CSR_MISA 11 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, 12 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, 13 | `endif 14 | 15 | output spec_valid, 16 | output spec_trap, 17 | output [ 4 : 0] spec_rs1_addr, 18 | output [ 4 : 0] spec_rs2_addr, 19 | output [ 4 : 0] spec_rd_addr, 20 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, 21 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, 22 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, 23 | output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, 24 | output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, 25 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata 26 | ); 27 | 28 | // I-type instruction format 29 | wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 32; 30 | wire [`RISCV_FORMAL_XLEN-1:0] insn_imm = $signed(rvfi_insn[31:20]); 31 | wire [4:0] insn_rs1 = rvfi_insn[19:15]; 32 | wire [2:0] insn_funct3 = rvfi_insn[14:12]; 33 | wire [4:0] insn_rd = rvfi_insn[11: 7]; 34 | wire [6:0] insn_opcode = rvfi_insn[ 6: 0]; 35 | 36 | `ifdef RISCV_FORMAL_CSR_MISA 37 | wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 0) == `RISCV_FORMAL_XLEN'h 0; 38 | assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 0; 39 | `else 40 | wire misa_ok = 1; 41 | `endif 42 | 43 | // ANDI instruction 44 | wire [`RISCV_FORMAL_XLEN-1:0] result = rvfi_rs1_rdata & insn_imm; 45 | assign spec_valid = rvfi_valid && !insn_padding && insn_funct3 == 3'b 111 && insn_opcode == 7'b 0010011; 46 | assign spec_rs1_addr = insn_rs1; 47 | assign spec_rd_addr = insn_rd; 48 | assign spec_rd_wdata = spec_rd_addr ? result : 0; 49 | assign spec_pc_wdata = rvfi_pc_rdata + 4; 50 | 51 | // default assignments 52 | assign spec_rs2_addr = 0; 53 | assign spec_trap = !misa_ok; 54 | assign spec_mem_addr = 0; 55 | assign spec_mem_rmask = 0; 56 | assign spec_mem_wmask = 0; 57 | assign spec_mem_wdata = 0; 58 | endmodule 59 | -------------------------------------------------------------------------------- /insns/insn_auipc.v: -------------------------------------------------------------------------------- 1 | // DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py 2 | 3 | module rvfi_insn_auipc ( 4 | input rvfi_valid, 5 | input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, 6 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, 7 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, 8 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, 9 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, 10 | `ifdef RISCV_FORMAL_CSR_MISA 11 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, 12 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, 13 | `endif 14 | 15 | output spec_valid, 16 | output spec_trap, 17 | output [ 4 : 0] spec_rs1_addr, 18 | output [ 4 : 0] spec_rs2_addr, 19 | output [ 4 : 0] spec_rd_addr, 20 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, 21 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, 22 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, 23 | output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, 24 | output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, 25 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata 26 | ); 27 | 28 | // U-type instruction format 29 | wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 32; 30 | wire [`RISCV_FORMAL_XLEN-1:0] insn_imm = $signed({rvfi_insn[31:12], 12'b0}); 31 | wire [4:0] insn_rd = rvfi_insn[11:7]; 32 | wire [6:0] insn_opcode = rvfi_insn[ 6:0]; 33 | 34 | `ifdef RISCV_FORMAL_CSR_MISA 35 | wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 0) == `RISCV_FORMAL_XLEN'h 0; 36 | assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 0; 37 | `else 38 | wire misa_ok = 1; 39 | `endif 40 | 41 | // AUIPC instruction 42 | assign spec_valid = rvfi_valid && !insn_padding && insn_opcode == 7'b 0010111; 43 | assign spec_rd_addr = insn_rd; 44 | assign spec_rd_wdata = spec_rd_addr ? rvfi_pc_rdata + insn_imm : 0; 45 | assign spec_pc_wdata = rvfi_pc_rdata + 4; 46 | 47 | // default assignments 48 | assign spec_rs1_addr = 0; 49 | assign spec_rs2_addr = 0; 50 | assign spec_trap = !misa_ok; 51 | assign spec_mem_addr = 0; 52 | assign spec_mem_rmask = 0; 53 | assign spec_mem_wmask = 0; 54 | assign spec_mem_wdata = 0; 55 | endmodule 56 | -------------------------------------------------------------------------------- /insns/insn_c_add.v: -------------------------------------------------------------------------------- 1 | // DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py 2 | 3 | module rvfi_insn_c_add ( 4 | input rvfi_valid, 5 | input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, 6 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, 7 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, 8 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, 9 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, 10 | `ifdef RISCV_FORMAL_CSR_MISA 11 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, 12 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, 13 | `endif 14 | 15 | output spec_valid, 16 | output spec_trap, 17 | output [ 4 : 0] spec_rs1_addr, 18 | output [ 4 : 0] spec_rs2_addr, 19 | output [ 4 : 0] spec_rd_addr, 20 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, 21 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, 22 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, 23 | output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, 24 | output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, 25 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata 26 | ); 27 | 28 | // CI-type instruction format 29 | wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16; 30 | wire [3:0] insn_funct4 = rvfi_insn[15:12]; 31 | wire [4:0] insn_rs1_rd = rvfi_insn[11:7]; 32 | wire [4:0] insn_rs2 = rvfi_insn[6:2]; 33 | wire [1:0] insn_opcode = rvfi_insn[1:0]; 34 | 35 | `ifdef RISCV_FORMAL_CSR_MISA 36 | wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 4) == `RISCV_FORMAL_XLEN'h 4; 37 | assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 4; 38 | `else 39 | wire misa_ok = 1; 40 | `endif 41 | 42 | // C_ADD instruction 43 | wire [`RISCV_FORMAL_XLEN-1:0] result = rvfi_rs1_rdata + rvfi_rs2_rdata; 44 | assign spec_valid = rvfi_valid && !insn_padding && insn_funct4 == 4'b 1001 && insn_rs2 && insn_opcode == 2'b 10; 45 | assign spec_rs1_addr = insn_rs1_rd; 46 | assign spec_rs2_addr = insn_rs2; 47 | assign spec_rd_addr = insn_rs1_rd; 48 | assign spec_rd_wdata = spec_rd_addr ? result : 0; 49 | assign spec_pc_wdata = rvfi_pc_rdata + 2; 50 | 51 | // default assignments 52 | assign spec_trap = !misa_ok; 53 | assign spec_mem_addr = 0; 54 | assign spec_mem_rmask = 0; 55 | assign spec_mem_wmask = 0; 56 | assign spec_mem_wdata = 0; 57 | endmodule 58 | -------------------------------------------------------------------------------- /insns/insn_c_addi.v: -------------------------------------------------------------------------------- 1 | // DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py 2 | 3 | module rvfi_insn_c_addi ( 4 | input rvfi_valid, 5 | input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, 6 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, 7 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, 8 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, 9 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, 10 | `ifdef RISCV_FORMAL_CSR_MISA 11 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, 12 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, 13 | `endif 14 | 15 | output spec_valid, 16 | output spec_trap, 17 | output [ 4 : 0] spec_rs1_addr, 18 | output [ 4 : 0] spec_rs2_addr, 19 | output [ 4 : 0] spec_rd_addr, 20 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, 21 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, 22 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, 23 | output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, 24 | output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, 25 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata 26 | ); 27 | 28 | // CI-type instruction format 29 | wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16; 30 | wire [`RISCV_FORMAL_XLEN-1:0] insn_imm = $signed({rvfi_insn[12], rvfi_insn[6:2]}); 31 | wire [2:0] insn_funct3 = rvfi_insn[15:13]; 32 | wire [4:0] insn_rs1_rd = rvfi_insn[11:7]; 33 | wire [1:0] insn_opcode = rvfi_insn[1:0]; 34 | 35 | `ifdef RISCV_FORMAL_CSR_MISA 36 | wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 4) == `RISCV_FORMAL_XLEN'h 4; 37 | assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 4; 38 | `else 39 | wire misa_ok = 1; 40 | `endif 41 | 42 | // C_ADDI instruction 43 | wire [`RISCV_FORMAL_XLEN-1:0] result = rvfi_rs1_rdata + insn_imm; 44 | assign spec_valid = rvfi_valid && !insn_padding && insn_funct3 == 3'b 000 && insn_opcode == 2'b 01; 45 | assign spec_rs1_addr = insn_rs1_rd; 46 | assign spec_rd_addr = insn_rs1_rd; 47 | assign spec_rd_wdata = spec_rd_addr ? result : 0; 48 | assign spec_pc_wdata = rvfi_pc_rdata + 2; 49 | 50 | // default assignments 51 | assign spec_rs2_addr = 0; 52 | assign spec_trap = !misa_ok; 53 | assign spec_mem_addr = 0; 54 | assign spec_mem_rmask = 0; 55 | assign spec_mem_wmask = 0; 56 | assign spec_mem_wdata = 0; 57 | endmodule 58 | -------------------------------------------------------------------------------- /insns/insn_c_addi16sp.v: -------------------------------------------------------------------------------- 1 | // DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py 2 | 3 | module rvfi_insn_c_addi16sp ( 4 | input rvfi_valid, 5 | input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, 6 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, 7 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, 8 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, 9 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, 10 | `ifdef RISCV_FORMAL_CSR_MISA 11 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, 12 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, 13 | `endif 14 | 15 | output spec_valid, 16 | output spec_trap, 17 | output [ 4 : 0] spec_rs1_addr, 18 | output [ 4 : 0] spec_rs2_addr, 19 | output [ 4 : 0] spec_rd_addr, 20 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, 21 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, 22 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, 23 | output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, 24 | output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, 25 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata 26 | ); 27 | 28 | // CI-type instruction format (SP variation) 29 | wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16; 30 | wire [`RISCV_FORMAL_XLEN-1:0] insn_imm = $signed({rvfi_insn[12], rvfi_insn[4:3], rvfi_insn[5], rvfi_insn[2], rvfi_insn[6], 4'b0}); 31 | wire [2:0] insn_funct3 = rvfi_insn[15:13]; 32 | wire [4:0] insn_rs1_rd = rvfi_insn[11:7]; 33 | wire [1:0] insn_opcode = rvfi_insn[1:0]; 34 | 35 | `ifdef RISCV_FORMAL_CSR_MISA 36 | wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 4) == `RISCV_FORMAL_XLEN'h 4; 37 | assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 4; 38 | `else 39 | wire misa_ok = 1; 40 | `endif 41 | 42 | // C_ADDI16SP instruction 43 | wire [`RISCV_FORMAL_XLEN-1:0] result = rvfi_rs1_rdata + insn_imm; 44 | assign spec_valid = rvfi_valid && !insn_padding && insn_funct3 == 3'b 011 && insn_opcode == 2'b 01 && insn_rs1_rd == 5'd 2 && insn_imm; 45 | assign spec_rs1_addr = insn_rs1_rd; 46 | assign spec_rd_addr = insn_rs1_rd; 47 | assign spec_rd_wdata = spec_rd_addr ? result : 0; 48 | assign spec_pc_wdata = rvfi_pc_rdata + 2; 49 | 50 | // default assignments 51 | assign spec_rs2_addr = 0; 52 | assign spec_trap = !misa_ok; 53 | assign spec_mem_addr = 0; 54 | assign spec_mem_rmask = 0; 55 | assign spec_mem_wmask = 0; 56 | assign spec_mem_wdata = 0; 57 | endmodule 58 | -------------------------------------------------------------------------------- /insns/insn_c_addi4spn.v: -------------------------------------------------------------------------------- 1 | // DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py 2 | 3 | module rvfi_insn_c_addi4spn ( 4 | input rvfi_valid, 5 | input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, 6 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, 7 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, 8 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, 9 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, 10 | `ifdef RISCV_FORMAL_CSR_MISA 11 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, 12 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, 13 | `endif 14 | 15 | output spec_valid, 16 | output spec_trap, 17 | output [ 4 : 0] spec_rs1_addr, 18 | output [ 4 : 0] spec_rs2_addr, 19 | output [ 4 : 0] spec_rd_addr, 20 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, 21 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, 22 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, 23 | output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, 24 | output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, 25 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata 26 | ); 27 | 28 | // CIW-type instruction format 29 | wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16; 30 | wire [`RISCV_FORMAL_XLEN-1:0] insn_imm = {rvfi_insn[10:7], rvfi_insn[12:11], rvfi_insn[5], rvfi_insn[6], 2'b00}; 31 | wire [2:0] insn_funct3 = rvfi_insn[15:13]; 32 | wire [4:0] insn_rd = {1'b1, rvfi_insn[4:2]}; 33 | wire [1:0] insn_opcode = rvfi_insn[1:0]; 34 | 35 | `ifdef RISCV_FORMAL_CSR_MISA 36 | wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 4) == `RISCV_FORMAL_XLEN'h 4; 37 | assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 4; 38 | `else 39 | wire misa_ok = 1; 40 | `endif 41 | 42 | // C_ADDI4SPN instruction 43 | wire [`RISCV_FORMAL_XLEN-1:0] result = rvfi_rs1_rdata + insn_imm; 44 | assign spec_valid = rvfi_valid && !insn_padding && insn_funct3 == 3'b 000 && insn_opcode == 2'b 00 && insn_imm; 45 | assign spec_rs1_addr = 2; 46 | assign spec_rd_addr = insn_rd; 47 | assign spec_rd_wdata = spec_rd_addr ? result : 0; 48 | assign spec_pc_wdata = rvfi_pc_rdata + 2; 49 | 50 | // default assignments 51 | assign spec_rs2_addr = 0; 52 | assign spec_trap = !misa_ok; 53 | assign spec_mem_addr = 0; 54 | assign spec_mem_rmask = 0; 55 | assign spec_mem_wmask = 0; 56 | assign spec_mem_wdata = 0; 57 | endmodule 58 | -------------------------------------------------------------------------------- /insns/insn_c_addiw.v: -------------------------------------------------------------------------------- 1 | // DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py 2 | 3 | module rvfi_insn_c_addiw ( 4 | input rvfi_valid, 5 | input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, 6 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, 7 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, 8 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, 9 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, 10 | `ifdef RISCV_FORMAL_CSR_MISA 11 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, 12 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, 13 | `endif 14 | 15 | output spec_valid, 16 | output spec_trap, 17 | output [ 4 : 0] spec_rs1_addr, 18 | output [ 4 : 0] spec_rs2_addr, 19 | output [ 4 : 0] spec_rd_addr, 20 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, 21 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, 22 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, 23 | output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, 24 | output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, 25 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata 26 | ); 27 | 28 | // CI-type instruction format 29 | wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16; 30 | wire [`RISCV_FORMAL_XLEN-1:0] insn_imm = $signed({rvfi_insn[12], rvfi_insn[6:2]}); 31 | wire [2:0] insn_funct3 = rvfi_insn[15:13]; 32 | wire [4:0] insn_rs1_rd = rvfi_insn[11:7]; 33 | wire [1:0] insn_opcode = rvfi_insn[1:0]; 34 | 35 | `ifdef RISCV_FORMAL_CSR_MISA 36 | wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 4) == `RISCV_FORMAL_XLEN'h 4; 37 | assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 4; 38 | `else 39 | wire misa_ok = 1; 40 | `endif 41 | 42 | // C_ADDIW instruction 43 | wire [31:0] result = rvfi_rs1_rdata[31:0] + insn_imm[31:0]; 44 | assign spec_valid = rvfi_valid && !insn_padding && insn_funct3 == 3'b 001 && insn_opcode == 2'b 01 && insn_rs1_rd != 5'd 0; 45 | assign spec_rs1_addr = insn_rs1_rd; 46 | assign spec_rd_addr = insn_rs1_rd; 47 | assign spec_rd_wdata = spec_rd_addr ? {{`RISCV_FORMAL_XLEN-32{result[31]}}, result} : 0; 48 | assign spec_pc_wdata = rvfi_pc_rdata + 2; 49 | 50 | // default assignments 51 | assign spec_rs2_addr = 0; 52 | assign spec_trap = !misa_ok; 53 | assign spec_mem_addr = 0; 54 | assign spec_mem_rmask = 0; 55 | assign spec_mem_wmask = 0; 56 | assign spec_mem_wdata = 0; 57 | endmodule 58 | -------------------------------------------------------------------------------- /insns/insn_c_addw.v: -------------------------------------------------------------------------------- 1 | // DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py 2 | 3 | module rvfi_insn_c_addw ( 4 | input rvfi_valid, 5 | input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, 6 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, 7 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, 8 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, 9 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, 10 | `ifdef RISCV_FORMAL_CSR_MISA 11 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, 12 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, 13 | `endif 14 | 15 | output spec_valid, 16 | output spec_trap, 17 | output [ 4 : 0] spec_rs1_addr, 18 | output [ 4 : 0] spec_rs2_addr, 19 | output [ 4 : 0] spec_rd_addr, 20 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, 21 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, 22 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, 23 | output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, 24 | output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, 25 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata 26 | ); 27 | 28 | // CS-type instruction format (ALU version) 29 | wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16; 30 | wire [5:0] insn_funct6 = rvfi_insn[15:10]; 31 | wire [1:0] insn_funct2 = rvfi_insn[6:5]; 32 | wire [4:0] insn_rs1_rd = {1'b1, rvfi_insn[9:7]}; 33 | wire [4:0] insn_rs2 = {1'b1, rvfi_insn[4:2]}; 34 | wire [1:0] insn_opcode = rvfi_insn[1:0]; 35 | 36 | `ifdef RISCV_FORMAL_CSR_MISA 37 | wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 4) == `RISCV_FORMAL_XLEN'h 4; 38 | assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 4; 39 | `else 40 | wire misa_ok = 1; 41 | `endif 42 | 43 | // C_ADDW instruction 44 | wire [31:0] result = rvfi_rs1_rdata[31:0] + rvfi_rs2_rdata[31:0]; 45 | assign spec_valid = rvfi_valid && !insn_padding && insn_funct6 == 6'b 100111 && insn_funct2 == 2'b 01 && insn_opcode == 2'b 01; 46 | assign spec_rs1_addr = insn_rs1_rd; 47 | assign spec_rs2_addr = insn_rs2; 48 | assign spec_rd_addr = insn_rs1_rd; 49 | assign spec_rd_wdata = spec_rd_addr ? {{`RISCV_FORMAL_XLEN-32{result[31]}}, result} : 0; 50 | assign spec_pc_wdata = rvfi_pc_rdata + 2; 51 | 52 | // default assignments 53 | assign spec_trap = !misa_ok; 54 | assign spec_mem_addr = 0; 55 | assign spec_mem_rmask = 0; 56 | assign spec_mem_wmask = 0; 57 | assign spec_mem_wdata = 0; 58 | endmodule 59 | -------------------------------------------------------------------------------- /insns/insn_c_and.v: -------------------------------------------------------------------------------- 1 | // DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py 2 | 3 | module rvfi_insn_c_and ( 4 | input rvfi_valid, 5 | input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, 6 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, 7 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, 8 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, 9 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, 10 | `ifdef RISCV_FORMAL_CSR_MISA 11 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, 12 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, 13 | `endif 14 | 15 | output spec_valid, 16 | output spec_trap, 17 | output [ 4 : 0] spec_rs1_addr, 18 | output [ 4 : 0] spec_rs2_addr, 19 | output [ 4 : 0] spec_rd_addr, 20 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, 21 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, 22 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, 23 | output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, 24 | output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, 25 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata 26 | ); 27 | 28 | // CS-type instruction format (ALU version) 29 | wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16; 30 | wire [5:0] insn_funct6 = rvfi_insn[15:10]; 31 | wire [1:0] insn_funct2 = rvfi_insn[6:5]; 32 | wire [4:0] insn_rs1_rd = {1'b1, rvfi_insn[9:7]}; 33 | wire [4:0] insn_rs2 = {1'b1, rvfi_insn[4:2]}; 34 | wire [1:0] insn_opcode = rvfi_insn[1:0]; 35 | 36 | `ifdef RISCV_FORMAL_CSR_MISA 37 | wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 4) == `RISCV_FORMAL_XLEN'h 4; 38 | assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 4; 39 | `else 40 | wire misa_ok = 1; 41 | `endif 42 | 43 | // C_AND instruction 44 | wire [`RISCV_FORMAL_XLEN-1:0] result = rvfi_rs1_rdata & rvfi_rs2_rdata; 45 | assign spec_valid = rvfi_valid && !insn_padding && insn_funct6 == 6'b 100011 && insn_funct2 == 2'b 11 && insn_opcode == 2'b 01; 46 | assign spec_rs1_addr = insn_rs1_rd; 47 | assign spec_rs2_addr = insn_rs2; 48 | assign spec_rd_addr = insn_rs1_rd; 49 | assign spec_rd_wdata = spec_rd_addr ? result : 0; 50 | assign spec_pc_wdata = rvfi_pc_rdata + 2; 51 | 52 | // default assignments 53 | assign spec_trap = !misa_ok; 54 | assign spec_mem_addr = 0; 55 | assign spec_mem_rmask = 0; 56 | assign spec_mem_wmask = 0; 57 | assign spec_mem_wdata = 0; 58 | endmodule 59 | -------------------------------------------------------------------------------- /insns/insn_c_andi.v: -------------------------------------------------------------------------------- 1 | // DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py 2 | 3 | module rvfi_insn_c_andi ( 4 | input rvfi_valid, 5 | input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, 6 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, 7 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, 8 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, 9 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, 10 | `ifdef RISCV_FORMAL_CSR_MISA 11 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, 12 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, 13 | `endif 14 | 15 | output spec_valid, 16 | output spec_trap, 17 | output [ 4 : 0] spec_rs1_addr, 18 | output [ 4 : 0] spec_rs2_addr, 19 | output [ 4 : 0] spec_rd_addr, 20 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, 21 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, 22 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, 23 | output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, 24 | output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, 25 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata 26 | ); 27 | 28 | // CI-type instruction format (ANDI variation) 29 | wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16; 30 | wire [`RISCV_FORMAL_XLEN-1:0] insn_imm = $signed({rvfi_insn[12], rvfi_insn[6:2]}); 31 | wire [2:0] insn_funct3 = rvfi_insn[15:13]; 32 | wire [1:0] insn_funct2 = rvfi_insn[11:10]; 33 | wire [4:0] insn_rs1_rd = {1'b1, rvfi_insn[9:7]}; 34 | wire [1:0] insn_opcode = rvfi_insn[1:0]; 35 | 36 | `ifdef RISCV_FORMAL_CSR_MISA 37 | wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 4) == `RISCV_FORMAL_XLEN'h 4; 38 | assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 4; 39 | `else 40 | wire misa_ok = 1; 41 | `endif 42 | 43 | // C_ANDI instruction 44 | wire [`RISCV_FORMAL_XLEN-1:0] result = rvfi_rs1_rdata & insn_imm; 45 | assign spec_valid = rvfi_valid && !insn_padding && insn_funct3 == 3'b 100 && insn_funct2 == 2'b 10 && insn_opcode == 2'b 01; 46 | assign spec_rs1_addr = insn_rs1_rd; 47 | assign spec_rd_addr = insn_rs1_rd; 48 | assign spec_rd_wdata = spec_rd_addr ? result : 0; 49 | assign spec_pc_wdata = rvfi_pc_rdata + 2; 50 | 51 | // default assignments 52 | assign spec_rs2_addr = 0; 53 | assign spec_trap = !misa_ok; 54 | assign spec_mem_addr = 0; 55 | assign spec_mem_rmask = 0; 56 | assign spec_mem_wmask = 0; 57 | assign spec_mem_wdata = 0; 58 | endmodule 59 | -------------------------------------------------------------------------------- /insns/insn_c_beqz.v: -------------------------------------------------------------------------------- 1 | // DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py 2 | 3 | module rvfi_insn_c_beqz ( 4 | input rvfi_valid, 5 | input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, 6 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, 7 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, 8 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, 9 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, 10 | `ifdef RISCV_FORMAL_CSR_MISA 11 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, 12 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, 13 | `endif 14 | 15 | output spec_valid, 16 | output spec_trap, 17 | output [ 4 : 0] spec_rs1_addr, 18 | output [ 4 : 0] spec_rs2_addr, 19 | output [ 4 : 0] spec_rd_addr, 20 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, 21 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, 22 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, 23 | output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, 24 | output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, 25 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata 26 | ); 27 | 28 | // CB-type instruction format 29 | wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16; 30 | wire [`RISCV_FORMAL_XLEN-1:0] insn_imm = $signed({rvfi_insn[12], rvfi_insn[6:5], rvfi_insn[2], rvfi_insn[11:10], rvfi_insn[4:3], 1'b0}); 31 | wire [2:0] insn_funct3 = rvfi_insn[15:13]; 32 | wire [4:0] insn_rs1 = {1'b1, rvfi_insn[9:7]}; 33 | wire [1:0] insn_opcode = rvfi_insn[1:0]; 34 | 35 | `ifdef RISCV_FORMAL_CSR_MISA 36 | wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 4) == `RISCV_FORMAL_XLEN'h 4; 37 | assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 4; 38 | `else 39 | wire misa_ok = 1; 40 | `endif 41 | 42 | // C_BEQZ instruction 43 | wire cond = rvfi_rs1_rdata == 0; 44 | wire [`RISCV_FORMAL_XLEN-1:0] next_pc = cond ? rvfi_pc_rdata + insn_imm : rvfi_pc_rdata + 2; 45 | assign spec_valid = rvfi_valid && !insn_padding && insn_funct3 == 3'b 110 && insn_opcode == 2'b 01; 46 | assign spec_rs1_addr = insn_rs1; 47 | assign spec_pc_wdata = next_pc; 48 | assign spec_trap = (next_pc[0] != 0) || !misa_ok; 49 | 50 | // default assignments 51 | assign spec_rs2_addr = 0; 52 | assign spec_rd_addr = 0; 53 | assign spec_rd_wdata = 0; 54 | assign spec_mem_addr = 0; 55 | assign spec_mem_rmask = 0; 56 | assign spec_mem_wmask = 0; 57 | assign spec_mem_wdata = 0; 58 | endmodule 59 | -------------------------------------------------------------------------------- /insns/insn_c_bnez.v: -------------------------------------------------------------------------------- 1 | // DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py 2 | 3 | module rvfi_insn_c_bnez ( 4 | input rvfi_valid, 5 | input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, 6 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, 7 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, 8 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, 9 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, 10 | `ifdef RISCV_FORMAL_CSR_MISA 11 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, 12 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, 13 | `endif 14 | 15 | output spec_valid, 16 | output spec_trap, 17 | output [ 4 : 0] spec_rs1_addr, 18 | output [ 4 : 0] spec_rs2_addr, 19 | output [ 4 : 0] spec_rd_addr, 20 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, 21 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, 22 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, 23 | output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, 24 | output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, 25 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata 26 | ); 27 | 28 | // CB-type instruction format 29 | wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16; 30 | wire [`RISCV_FORMAL_XLEN-1:0] insn_imm = $signed({rvfi_insn[12], rvfi_insn[6:5], rvfi_insn[2], rvfi_insn[11:10], rvfi_insn[4:3], 1'b0}); 31 | wire [2:0] insn_funct3 = rvfi_insn[15:13]; 32 | wire [4:0] insn_rs1 = {1'b1, rvfi_insn[9:7]}; 33 | wire [1:0] insn_opcode = rvfi_insn[1:0]; 34 | 35 | `ifdef RISCV_FORMAL_CSR_MISA 36 | wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 4) == `RISCV_FORMAL_XLEN'h 4; 37 | assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 4; 38 | `else 39 | wire misa_ok = 1; 40 | `endif 41 | 42 | // C_BNEZ instruction 43 | wire cond = rvfi_rs1_rdata != 0; 44 | wire [`RISCV_FORMAL_XLEN-1:0] next_pc = cond ? rvfi_pc_rdata + insn_imm : rvfi_pc_rdata + 2; 45 | assign spec_valid = rvfi_valid && !insn_padding && insn_funct3 == 3'b 111 && insn_opcode == 2'b 01; 46 | assign spec_rs1_addr = insn_rs1; 47 | assign spec_pc_wdata = next_pc; 48 | assign spec_trap = (next_pc[0] != 0) || !misa_ok; 49 | 50 | // default assignments 51 | assign spec_rs2_addr = 0; 52 | assign spec_rd_addr = 0; 53 | assign spec_rd_wdata = 0; 54 | assign spec_mem_addr = 0; 55 | assign spec_mem_rmask = 0; 56 | assign spec_mem_wmask = 0; 57 | assign spec_mem_wdata = 0; 58 | endmodule 59 | -------------------------------------------------------------------------------- /insns/insn_c_j.v: -------------------------------------------------------------------------------- 1 | // DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py 2 | 3 | module rvfi_insn_c_j ( 4 | input rvfi_valid, 5 | input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, 6 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, 7 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, 8 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, 9 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, 10 | `ifdef RISCV_FORMAL_CSR_MISA 11 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, 12 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, 13 | `endif 14 | 15 | output spec_valid, 16 | output spec_trap, 17 | output [ 4 : 0] spec_rs1_addr, 18 | output [ 4 : 0] spec_rs2_addr, 19 | output [ 4 : 0] spec_rd_addr, 20 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, 21 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, 22 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, 23 | output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, 24 | output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, 25 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata 26 | ); 27 | 28 | // CJ-type instruction format 29 | wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16; 30 | wire [`RISCV_FORMAL_XLEN-1:0] insn_imm = $signed({rvfi_insn[12], rvfi_insn[8], rvfi_insn[10], rvfi_insn[9], 31 | rvfi_insn[6], rvfi_insn[7], rvfi_insn[2], rvfi_insn[11], rvfi_insn[5], rvfi_insn[4], rvfi_insn[3], 1'b0}); 32 | wire [2:0] insn_funct3 = rvfi_insn[15:13]; 33 | wire [1:0] insn_opcode = rvfi_insn[1:0]; 34 | 35 | `ifdef RISCV_FORMAL_CSR_MISA 36 | wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 4) == `RISCV_FORMAL_XLEN'h 4; 37 | assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 4; 38 | `else 39 | wire misa_ok = 1; 40 | `endif 41 | 42 | // C_J instruction 43 | wire [`RISCV_FORMAL_XLEN-1:0] next_pc = rvfi_pc_rdata + insn_imm; 44 | assign spec_valid = rvfi_valid && !insn_padding && insn_funct3 == 3'b 101 && insn_opcode == 2'b 01; 45 | assign spec_pc_wdata = next_pc; 46 | 47 | // default assignments 48 | assign spec_rs1_addr = 0; 49 | assign spec_rs2_addr = 0; 50 | assign spec_rd_addr = 0; 51 | assign spec_rd_wdata = 0; 52 | assign spec_trap = !misa_ok; 53 | assign spec_mem_addr = 0; 54 | assign spec_mem_rmask = 0; 55 | assign spec_mem_wmask = 0; 56 | assign spec_mem_wdata = 0; 57 | endmodule 58 | -------------------------------------------------------------------------------- /insns/insn_c_jal.v: -------------------------------------------------------------------------------- 1 | // DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py 2 | 3 | module rvfi_insn_c_jal ( 4 | input rvfi_valid, 5 | input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, 6 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, 7 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, 8 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, 9 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, 10 | `ifdef RISCV_FORMAL_CSR_MISA 11 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, 12 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, 13 | `endif 14 | 15 | output spec_valid, 16 | output spec_trap, 17 | output [ 4 : 0] spec_rs1_addr, 18 | output [ 4 : 0] spec_rs2_addr, 19 | output [ 4 : 0] spec_rd_addr, 20 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, 21 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, 22 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, 23 | output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, 24 | output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, 25 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata 26 | ); 27 | 28 | // CJ-type instruction format 29 | wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16; 30 | wire [`RISCV_FORMAL_XLEN-1:0] insn_imm = $signed({rvfi_insn[12], rvfi_insn[8], rvfi_insn[10], rvfi_insn[9], 31 | rvfi_insn[6], rvfi_insn[7], rvfi_insn[2], rvfi_insn[11], rvfi_insn[5], rvfi_insn[4], rvfi_insn[3], 1'b0}); 32 | wire [2:0] insn_funct3 = rvfi_insn[15:13]; 33 | wire [1:0] insn_opcode = rvfi_insn[1:0]; 34 | 35 | `ifdef RISCV_FORMAL_CSR_MISA 36 | wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 4) == `RISCV_FORMAL_XLEN'h 4; 37 | assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 4; 38 | `else 39 | wire misa_ok = 1; 40 | `endif 41 | 42 | // C_JAL instruction 43 | wire [`RISCV_FORMAL_XLEN-1:0] next_pc = rvfi_pc_rdata + insn_imm; 44 | assign spec_valid = rvfi_valid && !insn_padding && insn_funct3 == 3'b 001 && insn_opcode == 2'b 01; 45 | assign spec_rd_addr = 5'd 1; 46 | assign spec_rd_wdata = rvfi_pc_rdata + 2; 47 | assign spec_pc_wdata = next_pc; 48 | 49 | // default assignments 50 | assign spec_rs1_addr = 0; 51 | assign spec_rs2_addr = 0; 52 | assign spec_trap = !misa_ok; 53 | assign spec_mem_addr = 0; 54 | assign spec_mem_rmask = 0; 55 | assign spec_mem_wmask = 0; 56 | assign spec_mem_wdata = 0; 57 | endmodule 58 | -------------------------------------------------------------------------------- /insns/insn_c_jalr.v: -------------------------------------------------------------------------------- 1 | // DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py 2 | 3 | module rvfi_insn_c_jalr ( 4 | input rvfi_valid, 5 | input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, 6 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, 7 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, 8 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, 9 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, 10 | `ifdef RISCV_FORMAL_CSR_MISA 11 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, 12 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, 13 | `endif 14 | 15 | output spec_valid, 16 | output spec_trap, 17 | output [ 4 : 0] spec_rs1_addr, 18 | output [ 4 : 0] spec_rs2_addr, 19 | output [ 4 : 0] spec_rd_addr, 20 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, 21 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, 22 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, 23 | output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, 24 | output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, 25 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata 26 | ); 27 | 28 | // CI-type instruction format 29 | wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16; 30 | wire [3:0] insn_funct4 = rvfi_insn[15:12]; 31 | wire [4:0] insn_rs1_rd = rvfi_insn[11:7]; 32 | wire [4:0] insn_rs2 = rvfi_insn[6:2]; 33 | wire [1:0] insn_opcode = rvfi_insn[1:0]; 34 | 35 | `ifdef RISCV_FORMAL_CSR_MISA 36 | wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 4) == `RISCV_FORMAL_XLEN'h 4; 37 | assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 4; 38 | `else 39 | wire misa_ok = 1; 40 | `endif 41 | 42 | // C_JALR instruction 43 | wire [`RISCV_FORMAL_XLEN-1:0] next_pc = rvfi_rs1_rdata & ~1; 44 | assign spec_valid = rvfi_valid && !insn_padding && insn_funct4 == 4'b 1001 && insn_rs1_rd && !insn_rs2 && insn_opcode == 2'b 10; 45 | assign spec_rs1_addr = insn_rs1_rd; 46 | assign spec_rd_addr = 5'd 1; 47 | assign spec_rd_wdata = rvfi_pc_rdata + 2; 48 | assign spec_pc_wdata = next_pc; 49 | assign spec_trap = (next_pc[0] != 0) || !misa_ok; 50 | 51 | // default assignments 52 | assign spec_rs2_addr = 0; 53 | assign spec_mem_addr = 0; 54 | assign spec_mem_rmask = 0; 55 | assign spec_mem_wmask = 0; 56 | assign spec_mem_wdata = 0; 57 | endmodule 58 | -------------------------------------------------------------------------------- /insns/insn_c_jr.v: -------------------------------------------------------------------------------- 1 | // DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py 2 | 3 | module rvfi_insn_c_jr ( 4 | input rvfi_valid, 5 | input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, 6 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, 7 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, 8 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, 9 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, 10 | `ifdef RISCV_FORMAL_CSR_MISA 11 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, 12 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, 13 | `endif 14 | 15 | output spec_valid, 16 | output spec_trap, 17 | output [ 4 : 0] spec_rs1_addr, 18 | output [ 4 : 0] spec_rs2_addr, 19 | output [ 4 : 0] spec_rd_addr, 20 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, 21 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, 22 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, 23 | output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, 24 | output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, 25 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata 26 | ); 27 | 28 | // CI-type instruction format 29 | wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16; 30 | wire [3:0] insn_funct4 = rvfi_insn[15:12]; 31 | wire [4:0] insn_rs1_rd = rvfi_insn[11:7]; 32 | wire [4:0] insn_rs2 = rvfi_insn[6:2]; 33 | wire [1:0] insn_opcode = rvfi_insn[1:0]; 34 | 35 | `ifdef RISCV_FORMAL_CSR_MISA 36 | wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 4) == `RISCV_FORMAL_XLEN'h 4; 37 | assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 4; 38 | `else 39 | wire misa_ok = 1; 40 | `endif 41 | 42 | // C_JR instruction 43 | wire [`RISCV_FORMAL_XLEN-1:0] next_pc = rvfi_rs1_rdata & ~1; 44 | assign spec_valid = rvfi_valid && !insn_padding && insn_funct4 == 4'b 1000 && insn_rs1_rd && !insn_rs2 && insn_opcode == 2'b 10; 45 | assign spec_rs1_addr = insn_rs1_rd; 46 | assign spec_pc_wdata = next_pc; 47 | assign spec_trap = (next_pc[0] != 0) || !misa_ok; 48 | 49 | // default assignments 50 | assign spec_rs2_addr = 0; 51 | assign spec_rd_addr = 0; 52 | assign spec_rd_wdata = 0; 53 | assign spec_mem_addr = 0; 54 | assign spec_mem_rmask = 0; 55 | assign spec_mem_wmask = 0; 56 | assign spec_mem_wdata = 0; 57 | endmodule 58 | -------------------------------------------------------------------------------- /insns/insn_c_li.v: -------------------------------------------------------------------------------- 1 | // DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py 2 | 3 | module rvfi_insn_c_li ( 4 | input rvfi_valid, 5 | input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, 6 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, 7 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, 8 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, 9 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, 10 | `ifdef RISCV_FORMAL_CSR_MISA 11 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, 12 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, 13 | `endif 14 | 15 | output spec_valid, 16 | output spec_trap, 17 | output [ 4 : 0] spec_rs1_addr, 18 | output [ 4 : 0] spec_rs2_addr, 19 | output [ 4 : 0] spec_rd_addr, 20 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, 21 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, 22 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, 23 | output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, 24 | output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, 25 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata 26 | ); 27 | 28 | // CI-type instruction format 29 | wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16; 30 | wire [`RISCV_FORMAL_XLEN-1:0] insn_imm = $signed({rvfi_insn[12], rvfi_insn[6:2]}); 31 | wire [2:0] insn_funct3 = rvfi_insn[15:13]; 32 | wire [4:0] insn_rs1_rd = rvfi_insn[11:7]; 33 | wire [1:0] insn_opcode = rvfi_insn[1:0]; 34 | 35 | `ifdef RISCV_FORMAL_CSR_MISA 36 | wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 4) == `RISCV_FORMAL_XLEN'h 4; 37 | assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 4; 38 | `else 39 | wire misa_ok = 1; 40 | `endif 41 | 42 | // C_LI instruction 43 | wire [`RISCV_FORMAL_XLEN-1:0] result = insn_imm; 44 | assign spec_valid = rvfi_valid && !insn_padding && insn_funct3 == 3'b 010 && insn_opcode == 2'b 01; 45 | assign spec_rd_addr = insn_rs1_rd; 46 | assign spec_rd_wdata = spec_rd_addr ? result : 0; 47 | assign spec_pc_wdata = rvfi_pc_rdata + 2; 48 | 49 | // default assignments 50 | assign spec_rs1_addr = 0; 51 | assign spec_rs2_addr = 0; 52 | assign spec_trap = !misa_ok; 53 | assign spec_mem_addr = 0; 54 | assign spec_mem_rmask = 0; 55 | assign spec_mem_wmask = 0; 56 | assign spec_mem_wdata = 0; 57 | endmodule 58 | -------------------------------------------------------------------------------- /insns/insn_c_lui.v: -------------------------------------------------------------------------------- 1 | // DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py 2 | 3 | module rvfi_insn_c_lui ( 4 | input rvfi_valid, 5 | input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, 6 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, 7 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, 8 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, 9 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, 10 | `ifdef RISCV_FORMAL_CSR_MISA 11 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, 12 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, 13 | `endif 14 | 15 | output spec_valid, 16 | output spec_trap, 17 | output [ 4 : 0] spec_rs1_addr, 18 | output [ 4 : 0] spec_rs2_addr, 19 | output [ 4 : 0] spec_rd_addr, 20 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, 21 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, 22 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, 23 | output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, 24 | output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, 25 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata 26 | ); 27 | 28 | // CI-type instruction format (LUI variation) 29 | wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16; 30 | wire [`RISCV_FORMAL_XLEN-1:0] insn_imm = $signed({rvfi_insn[12], rvfi_insn[6:2], 12'b0}); 31 | wire [2:0] insn_funct3 = rvfi_insn[15:13]; 32 | wire [4:0] insn_rs1_rd = rvfi_insn[11:7]; 33 | wire [1:0] insn_opcode = rvfi_insn[1:0]; 34 | 35 | `ifdef RISCV_FORMAL_CSR_MISA 36 | wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 4) == `RISCV_FORMAL_XLEN'h 4; 37 | assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 4; 38 | `else 39 | wire misa_ok = 1; 40 | `endif 41 | 42 | // C_LUI instruction 43 | wire [`RISCV_FORMAL_XLEN-1:0] result = insn_imm; 44 | assign spec_valid = rvfi_valid && !insn_padding && insn_funct3 == 3'b 011 && insn_opcode == 2'b 01 && insn_rs1_rd != 5'd 2 && insn_imm; 45 | assign spec_rd_addr = insn_rs1_rd; 46 | assign spec_rd_wdata = spec_rd_addr ? result : 0; 47 | assign spec_pc_wdata = rvfi_pc_rdata + 2; 48 | 49 | // default assignments 50 | assign spec_rs1_addr = 0; 51 | assign spec_rs2_addr = 0; 52 | assign spec_trap = !misa_ok; 53 | assign spec_mem_addr = 0; 54 | assign spec_mem_rmask = 0; 55 | assign spec_mem_wmask = 0; 56 | assign spec_mem_wdata = 0; 57 | endmodule 58 | -------------------------------------------------------------------------------- /insns/insn_c_mv.v: -------------------------------------------------------------------------------- 1 | // DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py 2 | 3 | module rvfi_insn_c_mv ( 4 | input rvfi_valid, 5 | input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, 6 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, 7 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, 8 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, 9 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, 10 | `ifdef RISCV_FORMAL_CSR_MISA 11 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, 12 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, 13 | `endif 14 | 15 | output spec_valid, 16 | output spec_trap, 17 | output [ 4 : 0] spec_rs1_addr, 18 | output [ 4 : 0] spec_rs2_addr, 19 | output [ 4 : 0] spec_rd_addr, 20 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, 21 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, 22 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, 23 | output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, 24 | output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, 25 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata 26 | ); 27 | 28 | // CI-type instruction format 29 | wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16; 30 | wire [3:0] insn_funct4 = rvfi_insn[15:12]; 31 | wire [4:0] insn_rs1_rd = rvfi_insn[11:7]; 32 | wire [4:0] insn_rs2 = rvfi_insn[6:2]; 33 | wire [1:0] insn_opcode = rvfi_insn[1:0]; 34 | 35 | `ifdef RISCV_FORMAL_CSR_MISA 36 | wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 4) == `RISCV_FORMAL_XLEN'h 4; 37 | assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 4; 38 | `else 39 | wire misa_ok = 1; 40 | `endif 41 | 42 | // C_MV instruction 43 | wire [`RISCV_FORMAL_XLEN-1:0] result = rvfi_rs2_rdata; 44 | assign spec_valid = rvfi_valid && !insn_padding && insn_funct4 == 4'b 1000 && insn_rs2 && insn_opcode == 2'b 10; 45 | assign spec_rs2_addr = insn_rs2; 46 | assign spec_rd_addr = insn_rs1_rd; 47 | assign spec_rd_wdata = spec_rd_addr ? result : 0; 48 | assign spec_pc_wdata = rvfi_pc_rdata + 2; 49 | 50 | // default assignments 51 | assign spec_rs1_addr = 0; 52 | assign spec_trap = !misa_ok; 53 | assign spec_mem_addr = 0; 54 | assign spec_mem_rmask = 0; 55 | assign spec_mem_wmask = 0; 56 | assign spec_mem_wdata = 0; 57 | endmodule 58 | -------------------------------------------------------------------------------- /insns/insn_c_or.v: -------------------------------------------------------------------------------- 1 | // DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py 2 | 3 | module rvfi_insn_c_or ( 4 | input rvfi_valid, 5 | input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, 6 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, 7 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, 8 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, 9 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, 10 | `ifdef RISCV_FORMAL_CSR_MISA 11 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, 12 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, 13 | `endif 14 | 15 | output spec_valid, 16 | output spec_trap, 17 | output [ 4 : 0] spec_rs1_addr, 18 | output [ 4 : 0] spec_rs2_addr, 19 | output [ 4 : 0] spec_rd_addr, 20 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, 21 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, 22 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, 23 | output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, 24 | output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, 25 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata 26 | ); 27 | 28 | // CS-type instruction format (ALU version) 29 | wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16; 30 | wire [5:0] insn_funct6 = rvfi_insn[15:10]; 31 | wire [1:0] insn_funct2 = rvfi_insn[6:5]; 32 | wire [4:0] insn_rs1_rd = {1'b1, rvfi_insn[9:7]}; 33 | wire [4:0] insn_rs2 = {1'b1, rvfi_insn[4:2]}; 34 | wire [1:0] insn_opcode = rvfi_insn[1:0]; 35 | 36 | `ifdef RISCV_FORMAL_CSR_MISA 37 | wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 4) == `RISCV_FORMAL_XLEN'h 4; 38 | assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 4; 39 | `else 40 | wire misa_ok = 1; 41 | `endif 42 | 43 | // C_OR instruction 44 | wire [`RISCV_FORMAL_XLEN-1:0] result = rvfi_rs1_rdata | rvfi_rs2_rdata; 45 | assign spec_valid = rvfi_valid && !insn_padding && insn_funct6 == 6'b 100011 && insn_funct2 == 2'b 10 && insn_opcode == 2'b 01; 46 | assign spec_rs1_addr = insn_rs1_rd; 47 | assign spec_rs2_addr = insn_rs2; 48 | assign spec_rd_addr = insn_rs1_rd; 49 | assign spec_rd_wdata = spec_rd_addr ? result : 0; 50 | assign spec_pc_wdata = rvfi_pc_rdata + 2; 51 | 52 | // default assignments 53 | assign spec_trap = !misa_ok; 54 | assign spec_mem_addr = 0; 55 | assign spec_mem_rmask = 0; 56 | assign spec_mem_wmask = 0; 57 | assign spec_mem_wdata = 0; 58 | endmodule 59 | -------------------------------------------------------------------------------- /insns/insn_c_slli.v: -------------------------------------------------------------------------------- 1 | // DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py 2 | 3 | module rvfi_insn_c_slli ( 4 | input rvfi_valid, 5 | input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, 6 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, 7 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, 8 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, 9 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, 10 | `ifdef RISCV_FORMAL_CSR_MISA 11 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, 12 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, 13 | `endif 14 | 15 | output spec_valid, 16 | output spec_trap, 17 | output [ 4 : 0] spec_rs1_addr, 18 | output [ 4 : 0] spec_rs2_addr, 19 | output [ 4 : 0] spec_rd_addr, 20 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, 21 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, 22 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, 23 | output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, 24 | output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, 25 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata 26 | ); 27 | 28 | // CI-type instruction format (SLI variation) 29 | wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16; 30 | wire [5:0] insn_shamt = {rvfi_insn[12], rvfi_insn[6:2]}; 31 | wire [2:0] insn_funct3 = rvfi_insn[15:13]; 32 | wire [4:0] insn_rs1_rd = rvfi_insn[11:7]; 33 | wire [1:0] insn_opcode = rvfi_insn[1:0]; 34 | 35 | `ifdef RISCV_FORMAL_CSR_MISA 36 | wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 4) == `RISCV_FORMAL_XLEN'h 4; 37 | assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 4; 38 | `else 39 | wire misa_ok = 1; 40 | `endif 41 | 42 | // C_SLLI instruction 43 | wire [`RISCV_FORMAL_XLEN-1:0] result = rvfi_rs1_rdata << insn_shamt; 44 | assign spec_valid = rvfi_valid && !insn_padding && insn_funct3 == 3'b 000 && insn_opcode == 2'b 10 && (!insn_shamt[5] || `RISCV_FORMAL_XLEN == 64); 45 | assign spec_rs1_addr = insn_rs1_rd; 46 | assign spec_rd_addr = insn_rs1_rd; 47 | assign spec_rd_wdata = spec_rd_addr ? result : 0; 48 | assign spec_pc_wdata = rvfi_pc_rdata + 2; 49 | 50 | // default assignments 51 | assign spec_rs2_addr = 0; 52 | assign spec_trap = !misa_ok; 53 | assign spec_mem_addr = 0; 54 | assign spec_mem_rmask = 0; 55 | assign spec_mem_wmask = 0; 56 | assign spec_mem_wdata = 0; 57 | endmodule 58 | -------------------------------------------------------------------------------- /insns/insn_c_srai.v: -------------------------------------------------------------------------------- 1 | // DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py 2 | 3 | module rvfi_insn_c_srai ( 4 | input rvfi_valid, 5 | input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, 6 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, 7 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, 8 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, 9 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, 10 | `ifdef RISCV_FORMAL_CSR_MISA 11 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, 12 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, 13 | `endif 14 | 15 | output spec_valid, 16 | output spec_trap, 17 | output [ 4 : 0] spec_rs1_addr, 18 | output [ 4 : 0] spec_rs2_addr, 19 | output [ 4 : 0] spec_rd_addr, 20 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, 21 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, 22 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, 23 | output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, 24 | output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, 25 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata 26 | ); 27 | 28 | // CI-type instruction format (SRI variation) 29 | wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16; 30 | wire [5:0] insn_shamt = {rvfi_insn[12], rvfi_insn[6:2]}; 31 | wire [2:0] insn_funct3 = rvfi_insn[15:13]; 32 | wire [1:0] insn_funct2 = rvfi_insn[11:10]; 33 | wire [4:0] insn_rs1_rd = {1'b1, rvfi_insn[9:7]}; 34 | wire [1:0] insn_opcode = rvfi_insn[1:0]; 35 | 36 | `ifdef RISCV_FORMAL_CSR_MISA 37 | wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 4) == `RISCV_FORMAL_XLEN'h 4; 38 | assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 4; 39 | `else 40 | wire misa_ok = 1; 41 | `endif 42 | 43 | // C_SRAI instruction 44 | wire [`RISCV_FORMAL_XLEN-1:0] result = $signed(rvfi_rs1_rdata) >>> insn_shamt; 45 | assign spec_valid = rvfi_valid && !insn_padding && insn_funct3 == 3'b 100 && insn_funct2 == 2'b 01 && insn_opcode == 2'b 01 && (!insn_shamt[5] || `RISCV_FORMAL_XLEN == 64); 46 | assign spec_rs1_addr = insn_rs1_rd; 47 | assign spec_rd_addr = insn_rs1_rd; 48 | assign spec_rd_wdata = spec_rd_addr ? result : 0; 49 | assign spec_pc_wdata = rvfi_pc_rdata + 2; 50 | 51 | // default assignments 52 | assign spec_rs2_addr = 0; 53 | assign spec_trap = !misa_ok; 54 | assign spec_mem_addr = 0; 55 | assign spec_mem_rmask = 0; 56 | assign spec_mem_wmask = 0; 57 | assign spec_mem_wdata = 0; 58 | endmodule 59 | -------------------------------------------------------------------------------- /insns/insn_c_srli.v: -------------------------------------------------------------------------------- 1 | // DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py 2 | 3 | module rvfi_insn_c_srli ( 4 | input rvfi_valid, 5 | input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, 6 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, 7 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, 8 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, 9 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, 10 | `ifdef RISCV_FORMAL_CSR_MISA 11 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, 12 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, 13 | `endif 14 | 15 | output spec_valid, 16 | output spec_trap, 17 | output [ 4 : 0] spec_rs1_addr, 18 | output [ 4 : 0] spec_rs2_addr, 19 | output [ 4 : 0] spec_rd_addr, 20 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, 21 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, 22 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, 23 | output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, 24 | output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, 25 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata 26 | ); 27 | 28 | // CI-type instruction format (SRI variation) 29 | wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16; 30 | wire [5:0] insn_shamt = {rvfi_insn[12], rvfi_insn[6:2]}; 31 | wire [2:0] insn_funct3 = rvfi_insn[15:13]; 32 | wire [1:0] insn_funct2 = rvfi_insn[11:10]; 33 | wire [4:0] insn_rs1_rd = {1'b1, rvfi_insn[9:7]}; 34 | wire [1:0] insn_opcode = rvfi_insn[1:0]; 35 | 36 | `ifdef RISCV_FORMAL_CSR_MISA 37 | wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 4) == `RISCV_FORMAL_XLEN'h 4; 38 | assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 4; 39 | `else 40 | wire misa_ok = 1; 41 | `endif 42 | 43 | // C_SRLI instruction 44 | wire [`RISCV_FORMAL_XLEN-1:0] result = rvfi_rs1_rdata >> insn_shamt; 45 | assign spec_valid = rvfi_valid && !insn_padding && insn_funct3 == 3'b 100 && insn_funct2 == 2'b 00 && insn_opcode == 2'b 01 && (!insn_shamt[5] || `RISCV_FORMAL_XLEN == 64); 46 | assign spec_rs1_addr = insn_rs1_rd; 47 | assign spec_rd_addr = insn_rs1_rd; 48 | assign spec_rd_wdata = spec_rd_addr ? result : 0; 49 | assign spec_pc_wdata = rvfi_pc_rdata + 2; 50 | 51 | // default assignments 52 | assign spec_rs2_addr = 0; 53 | assign spec_trap = !misa_ok; 54 | assign spec_mem_addr = 0; 55 | assign spec_mem_rmask = 0; 56 | assign spec_mem_wmask = 0; 57 | assign spec_mem_wdata = 0; 58 | endmodule 59 | -------------------------------------------------------------------------------- /insns/insn_c_sub.v: -------------------------------------------------------------------------------- 1 | // DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py 2 | 3 | module rvfi_insn_c_sub ( 4 | input rvfi_valid, 5 | input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, 6 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, 7 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, 8 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, 9 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, 10 | `ifdef RISCV_FORMAL_CSR_MISA 11 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, 12 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, 13 | `endif 14 | 15 | output spec_valid, 16 | output spec_trap, 17 | output [ 4 : 0] spec_rs1_addr, 18 | output [ 4 : 0] spec_rs2_addr, 19 | output [ 4 : 0] spec_rd_addr, 20 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, 21 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, 22 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, 23 | output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, 24 | output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, 25 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata 26 | ); 27 | 28 | // CS-type instruction format (ALU version) 29 | wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16; 30 | wire [5:0] insn_funct6 = rvfi_insn[15:10]; 31 | wire [1:0] insn_funct2 = rvfi_insn[6:5]; 32 | wire [4:0] insn_rs1_rd = {1'b1, rvfi_insn[9:7]}; 33 | wire [4:0] insn_rs2 = {1'b1, rvfi_insn[4:2]}; 34 | wire [1:0] insn_opcode = rvfi_insn[1:0]; 35 | 36 | `ifdef RISCV_FORMAL_CSR_MISA 37 | wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 4) == `RISCV_FORMAL_XLEN'h 4; 38 | assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 4; 39 | `else 40 | wire misa_ok = 1; 41 | `endif 42 | 43 | // C_SUB instruction 44 | wire [`RISCV_FORMAL_XLEN-1:0] result = rvfi_rs1_rdata - rvfi_rs2_rdata; 45 | assign spec_valid = rvfi_valid && !insn_padding && insn_funct6 == 6'b 100011 && insn_funct2 == 2'b 00 && insn_opcode == 2'b 01; 46 | assign spec_rs1_addr = insn_rs1_rd; 47 | assign spec_rs2_addr = insn_rs2; 48 | assign spec_rd_addr = insn_rs1_rd; 49 | assign spec_rd_wdata = spec_rd_addr ? result : 0; 50 | assign spec_pc_wdata = rvfi_pc_rdata + 2; 51 | 52 | // default assignments 53 | assign spec_trap = !misa_ok; 54 | assign spec_mem_addr = 0; 55 | assign spec_mem_rmask = 0; 56 | assign spec_mem_wmask = 0; 57 | assign spec_mem_wdata = 0; 58 | endmodule 59 | -------------------------------------------------------------------------------- /insns/insn_c_subw.v: -------------------------------------------------------------------------------- 1 | // DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py 2 | 3 | module rvfi_insn_c_subw ( 4 | input rvfi_valid, 5 | input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, 6 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, 7 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, 8 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, 9 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, 10 | `ifdef RISCV_FORMAL_CSR_MISA 11 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, 12 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, 13 | `endif 14 | 15 | output spec_valid, 16 | output spec_trap, 17 | output [ 4 : 0] spec_rs1_addr, 18 | output [ 4 : 0] spec_rs2_addr, 19 | output [ 4 : 0] spec_rd_addr, 20 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, 21 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, 22 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, 23 | output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, 24 | output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, 25 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata 26 | ); 27 | 28 | // CS-type instruction format (ALU version) 29 | wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16; 30 | wire [5:0] insn_funct6 = rvfi_insn[15:10]; 31 | wire [1:0] insn_funct2 = rvfi_insn[6:5]; 32 | wire [4:0] insn_rs1_rd = {1'b1, rvfi_insn[9:7]}; 33 | wire [4:0] insn_rs2 = {1'b1, rvfi_insn[4:2]}; 34 | wire [1:0] insn_opcode = rvfi_insn[1:0]; 35 | 36 | `ifdef RISCV_FORMAL_CSR_MISA 37 | wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 4) == `RISCV_FORMAL_XLEN'h 4; 38 | assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 4; 39 | `else 40 | wire misa_ok = 1; 41 | `endif 42 | 43 | // C_SUBW instruction 44 | wire [31:0] result = rvfi_rs1_rdata[31:0] - rvfi_rs2_rdata[31:0]; 45 | assign spec_valid = rvfi_valid && !insn_padding && insn_funct6 == 6'b 100111 && insn_funct2 == 2'b 00 && insn_opcode == 2'b 01; 46 | assign spec_rs1_addr = insn_rs1_rd; 47 | assign spec_rs2_addr = insn_rs2; 48 | assign spec_rd_addr = insn_rs1_rd; 49 | assign spec_rd_wdata = spec_rd_addr ? {{`RISCV_FORMAL_XLEN-32{result[31]}}, result} : 0; 50 | assign spec_pc_wdata = rvfi_pc_rdata + 2; 51 | 52 | // default assignments 53 | assign spec_trap = !misa_ok; 54 | assign spec_mem_addr = 0; 55 | assign spec_mem_rmask = 0; 56 | assign spec_mem_wmask = 0; 57 | assign spec_mem_wdata = 0; 58 | endmodule 59 | -------------------------------------------------------------------------------- /insns/insn_c_xor.v: -------------------------------------------------------------------------------- 1 | // DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py 2 | 3 | module rvfi_insn_c_xor ( 4 | input rvfi_valid, 5 | input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, 6 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, 7 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, 8 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, 9 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, 10 | `ifdef RISCV_FORMAL_CSR_MISA 11 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, 12 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, 13 | `endif 14 | 15 | output spec_valid, 16 | output spec_trap, 17 | output [ 4 : 0] spec_rs1_addr, 18 | output [ 4 : 0] spec_rs2_addr, 19 | output [ 4 : 0] spec_rd_addr, 20 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, 21 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, 22 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, 23 | output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, 24 | output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, 25 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata 26 | ); 27 | 28 | // CS-type instruction format (ALU version) 29 | wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 16; 30 | wire [5:0] insn_funct6 = rvfi_insn[15:10]; 31 | wire [1:0] insn_funct2 = rvfi_insn[6:5]; 32 | wire [4:0] insn_rs1_rd = {1'b1, rvfi_insn[9:7]}; 33 | wire [4:0] insn_rs2 = {1'b1, rvfi_insn[4:2]}; 34 | wire [1:0] insn_opcode = rvfi_insn[1:0]; 35 | 36 | `ifdef RISCV_FORMAL_CSR_MISA 37 | wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 4) == `RISCV_FORMAL_XLEN'h 4; 38 | assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 4; 39 | `else 40 | wire misa_ok = 1; 41 | `endif 42 | 43 | // C_XOR instruction 44 | wire [`RISCV_FORMAL_XLEN-1:0] result = rvfi_rs1_rdata ^ rvfi_rs2_rdata; 45 | assign spec_valid = rvfi_valid && !insn_padding && insn_funct6 == 6'b 100011 && insn_funct2 == 2'b 01 && insn_opcode == 2'b 01; 46 | assign spec_rs1_addr = insn_rs1_rd; 47 | assign spec_rs2_addr = insn_rs2; 48 | assign spec_rd_addr = insn_rs1_rd; 49 | assign spec_rd_wdata = spec_rd_addr ? result : 0; 50 | assign spec_pc_wdata = rvfi_pc_rdata + 2; 51 | 52 | // default assignments 53 | assign spec_trap = !misa_ok; 54 | assign spec_mem_addr = 0; 55 | assign spec_mem_rmask = 0; 56 | assign spec_mem_wmask = 0; 57 | assign spec_mem_wdata = 0; 58 | endmodule 59 | -------------------------------------------------------------------------------- /insns/insn_lui.v: -------------------------------------------------------------------------------- 1 | // DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py 2 | 3 | module rvfi_insn_lui ( 4 | input rvfi_valid, 5 | input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, 6 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, 7 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, 8 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, 9 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, 10 | `ifdef RISCV_FORMAL_CSR_MISA 11 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, 12 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, 13 | `endif 14 | 15 | output spec_valid, 16 | output spec_trap, 17 | output [ 4 : 0] spec_rs1_addr, 18 | output [ 4 : 0] spec_rs2_addr, 19 | output [ 4 : 0] spec_rd_addr, 20 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, 21 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, 22 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, 23 | output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, 24 | output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, 25 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata 26 | ); 27 | 28 | // U-type instruction format 29 | wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 32; 30 | wire [`RISCV_FORMAL_XLEN-1:0] insn_imm = $signed({rvfi_insn[31:12], 12'b0}); 31 | wire [4:0] insn_rd = rvfi_insn[11:7]; 32 | wire [6:0] insn_opcode = rvfi_insn[ 6:0]; 33 | 34 | `ifdef RISCV_FORMAL_CSR_MISA 35 | wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 0) == `RISCV_FORMAL_XLEN'h 0; 36 | assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 0; 37 | `else 38 | wire misa_ok = 1; 39 | `endif 40 | 41 | // LUI instruction 42 | assign spec_valid = rvfi_valid && !insn_padding && insn_opcode == 7'b 0110111; 43 | assign spec_rd_addr = insn_rd; 44 | assign spec_rd_wdata = spec_rd_addr ? insn_imm : 0; 45 | assign spec_pc_wdata = rvfi_pc_rdata + 4; 46 | 47 | // default assignments 48 | assign spec_rs1_addr = 0; 49 | assign spec_rs2_addr = 0; 50 | assign spec_trap = !misa_ok; 51 | assign spec_mem_addr = 0; 52 | assign spec_mem_rmask = 0; 53 | assign spec_mem_wmask = 0; 54 | assign spec_mem_wdata = 0; 55 | endmodule 56 | -------------------------------------------------------------------------------- /insns/insn_or.v: -------------------------------------------------------------------------------- 1 | // DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py 2 | 3 | module rvfi_insn_or ( 4 | input rvfi_valid, 5 | input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, 6 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, 7 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, 8 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, 9 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, 10 | `ifdef RISCV_FORMAL_CSR_MISA 11 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, 12 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, 13 | `endif 14 | 15 | output spec_valid, 16 | output spec_trap, 17 | output [ 4 : 0] spec_rs1_addr, 18 | output [ 4 : 0] spec_rs2_addr, 19 | output [ 4 : 0] spec_rd_addr, 20 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, 21 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, 22 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, 23 | output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, 24 | output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, 25 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata 26 | ); 27 | 28 | // R-type instruction format 29 | wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 32; 30 | wire [6:0] insn_funct7 = rvfi_insn[31:25]; 31 | wire [4:0] insn_rs2 = rvfi_insn[24:20]; 32 | wire [4:0] insn_rs1 = rvfi_insn[19:15]; 33 | wire [2:0] insn_funct3 = rvfi_insn[14:12]; 34 | wire [4:0] insn_rd = rvfi_insn[11: 7]; 35 | wire [6:0] insn_opcode = rvfi_insn[ 6: 0]; 36 | 37 | `ifdef RISCV_FORMAL_CSR_MISA 38 | wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 0) == `RISCV_FORMAL_XLEN'h 0; 39 | assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 0; 40 | `else 41 | wire misa_ok = 1; 42 | `endif 43 | 44 | // OR instruction 45 | wire [`RISCV_FORMAL_XLEN-1:0] result = rvfi_rs1_rdata | rvfi_rs2_rdata; 46 | assign spec_valid = rvfi_valid && !insn_padding && insn_funct7 == 7'b 0000000 && insn_funct3 == 3'b 110 && insn_opcode == 7'b 0110011; 47 | assign spec_rs1_addr = insn_rs1; 48 | assign spec_rs2_addr = insn_rs2; 49 | assign spec_rd_addr = insn_rd; 50 | assign spec_rd_wdata = spec_rd_addr ? result : 0; 51 | assign spec_pc_wdata = rvfi_pc_rdata + 4; 52 | 53 | // default assignments 54 | assign spec_trap = !misa_ok; 55 | assign spec_mem_addr = 0; 56 | assign spec_mem_rmask = 0; 57 | assign spec_mem_wmask = 0; 58 | assign spec_mem_wdata = 0; 59 | endmodule 60 | -------------------------------------------------------------------------------- /insns/insn_ori.v: -------------------------------------------------------------------------------- 1 | // DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py 2 | 3 | module rvfi_insn_ori ( 4 | input rvfi_valid, 5 | input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, 6 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, 7 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, 8 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, 9 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, 10 | `ifdef RISCV_FORMAL_CSR_MISA 11 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, 12 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, 13 | `endif 14 | 15 | output spec_valid, 16 | output spec_trap, 17 | output [ 4 : 0] spec_rs1_addr, 18 | output [ 4 : 0] spec_rs2_addr, 19 | output [ 4 : 0] spec_rd_addr, 20 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, 21 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, 22 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, 23 | output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, 24 | output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, 25 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata 26 | ); 27 | 28 | // I-type instruction format 29 | wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 32; 30 | wire [`RISCV_FORMAL_XLEN-1:0] insn_imm = $signed(rvfi_insn[31:20]); 31 | wire [4:0] insn_rs1 = rvfi_insn[19:15]; 32 | wire [2:0] insn_funct3 = rvfi_insn[14:12]; 33 | wire [4:0] insn_rd = rvfi_insn[11: 7]; 34 | wire [6:0] insn_opcode = rvfi_insn[ 6: 0]; 35 | 36 | `ifdef RISCV_FORMAL_CSR_MISA 37 | wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 0) == `RISCV_FORMAL_XLEN'h 0; 38 | assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 0; 39 | `else 40 | wire misa_ok = 1; 41 | `endif 42 | 43 | // ORI instruction 44 | wire [`RISCV_FORMAL_XLEN-1:0] result = rvfi_rs1_rdata | insn_imm; 45 | assign spec_valid = rvfi_valid && !insn_padding && insn_funct3 == 3'b 110 && insn_opcode == 7'b 0010011; 46 | assign spec_rs1_addr = insn_rs1; 47 | assign spec_rd_addr = insn_rd; 48 | assign spec_rd_wdata = spec_rd_addr ? result : 0; 49 | assign spec_pc_wdata = rvfi_pc_rdata + 4; 50 | 51 | // default assignments 52 | assign spec_rs2_addr = 0; 53 | assign spec_trap = !misa_ok; 54 | assign spec_mem_addr = 0; 55 | assign spec_mem_rmask = 0; 56 | assign spec_mem_wmask = 0; 57 | assign spec_mem_wdata = 0; 58 | endmodule 59 | -------------------------------------------------------------------------------- /insns/insn_slli.v: -------------------------------------------------------------------------------- 1 | // DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py 2 | 3 | module rvfi_insn_slli ( 4 | input rvfi_valid, 5 | input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, 6 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, 7 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, 8 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, 9 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, 10 | `ifdef RISCV_FORMAL_CSR_MISA 11 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, 12 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, 13 | `endif 14 | 15 | output spec_valid, 16 | output spec_trap, 17 | output [ 4 : 0] spec_rs1_addr, 18 | output [ 4 : 0] spec_rs2_addr, 19 | output [ 4 : 0] spec_rd_addr, 20 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, 21 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, 22 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, 23 | output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, 24 | output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, 25 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata 26 | ); 27 | 28 | // I-type instruction format (shift variation) 29 | wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 32; 30 | wire [6:0] insn_funct6 = rvfi_insn[31:26]; 31 | wire [5:0] insn_shamt = rvfi_insn[25:20]; 32 | wire [4:0] insn_rs1 = rvfi_insn[19:15]; 33 | wire [2:0] insn_funct3 = rvfi_insn[14:12]; 34 | wire [4:0] insn_rd = rvfi_insn[11: 7]; 35 | wire [6:0] insn_opcode = rvfi_insn[ 6: 0]; 36 | 37 | `ifdef RISCV_FORMAL_CSR_MISA 38 | wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 0) == `RISCV_FORMAL_XLEN'h 0; 39 | assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 0; 40 | `else 41 | wire misa_ok = 1; 42 | `endif 43 | 44 | // SLLI instruction 45 | wire [`RISCV_FORMAL_XLEN-1:0] result = rvfi_rs1_rdata << insn_shamt; 46 | assign spec_valid = rvfi_valid && !insn_padding && insn_funct6 == 6'b 000000 && insn_funct3 == 3'b 001 && insn_opcode == 7'b 0010011 && (!insn_shamt[5] || `RISCV_FORMAL_XLEN == 64); 47 | assign spec_rs1_addr = insn_rs1; 48 | assign spec_rd_addr = insn_rd; 49 | assign spec_rd_wdata = spec_rd_addr ? result : 0; 50 | assign spec_pc_wdata = rvfi_pc_rdata + 4; 51 | 52 | // default assignments 53 | assign spec_rs2_addr = 0; 54 | assign spec_trap = !misa_ok; 55 | assign spec_mem_addr = 0; 56 | assign spec_mem_rmask = 0; 57 | assign spec_mem_wmask = 0; 58 | assign spec_mem_wdata = 0; 59 | endmodule 60 | -------------------------------------------------------------------------------- /insns/insn_slliw.v: -------------------------------------------------------------------------------- 1 | // DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py 2 | 3 | module rvfi_insn_slliw ( 4 | input rvfi_valid, 5 | input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, 6 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, 7 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, 8 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, 9 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, 10 | `ifdef RISCV_FORMAL_CSR_MISA 11 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, 12 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, 13 | `endif 14 | 15 | output spec_valid, 16 | output spec_trap, 17 | output [ 4 : 0] spec_rs1_addr, 18 | output [ 4 : 0] spec_rs2_addr, 19 | output [ 4 : 0] spec_rd_addr, 20 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, 21 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, 22 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, 23 | output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, 24 | output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, 25 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata 26 | ); 27 | 28 | // I-type instruction format (shift variation) 29 | wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 32; 30 | wire [6:0] insn_funct6 = rvfi_insn[31:26]; 31 | wire [5:0] insn_shamt = rvfi_insn[25:20]; 32 | wire [4:0] insn_rs1 = rvfi_insn[19:15]; 33 | wire [2:0] insn_funct3 = rvfi_insn[14:12]; 34 | wire [4:0] insn_rd = rvfi_insn[11: 7]; 35 | wire [6:0] insn_opcode = rvfi_insn[ 6: 0]; 36 | 37 | `ifdef RISCV_FORMAL_CSR_MISA 38 | wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 0) == `RISCV_FORMAL_XLEN'h 0; 39 | assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 0; 40 | `else 41 | wire misa_ok = 1; 42 | `endif 43 | 44 | // SLLIW instruction 45 | wire [31:0] result = rvfi_rs1_rdata[31:0] << insn_shamt; 46 | assign spec_valid = rvfi_valid && !insn_padding && insn_funct6 == 6'b 000000 && insn_funct3 == 3'b 001 && insn_opcode == 7'b 0011011 && !insn_shamt[5]; 47 | assign spec_rs1_addr = insn_rs1; 48 | assign spec_rd_addr = insn_rd; 49 | assign spec_rd_wdata = spec_rd_addr ? {{`RISCV_FORMAL_XLEN-32{result[31]}}, result} : 0; 50 | assign spec_pc_wdata = rvfi_pc_rdata + 4; 51 | 52 | // default assignments 53 | assign spec_rs2_addr = 0; 54 | assign spec_trap = !misa_ok; 55 | assign spec_mem_addr = 0; 56 | assign spec_mem_rmask = 0; 57 | assign spec_mem_wmask = 0; 58 | assign spec_mem_wdata = 0; 59 | endmodule 60 | -------------------------------------------------------------------------------- /insns/insn_sllw.v: -------------------------------------------------------------------------------- 1 | // DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py 2 | 3 | module rvfi_insn_sllw ( 4 | input rvfi_valid, 5 | input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, 6 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, 7 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, 8 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, 9 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, 10 | `ifdef RISCV_FORMAL_CSR_MISA 11 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, 12 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, 13 | `endif 14 | 15 | output spec_valid, 16 | output spec_trap, 17 | output [ 4 : 0] spec_rs1_addr, 18 | output [ 4 : 0] spec_rs2_addr, 19 | output [ 4 : 0] spec_rd_addr, 20 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, 21 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, 22 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, 23 | output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, 24 | output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, 25 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata 26 | ); 27 | 28 | // R-type instruction format 29 | wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 32; 30 | wire [6:0] insn_funct7 = rvfi_insn[31:25]; 31 | wire [4:0] insn_rs2 = rvfi_insn[24:20]; 32 | wire [4:0] insn_rs1 = rvfi_insn[19:15]; 33 | wire [2:0] insn_funct3 = rvfi_insn[14:12]; 34 | wire [4:0] insn_rd = rvfi_insn[11: 7]; 35 | wire [6:0] insn_opcode = rvfi_insn[ 6: 0]; 36 | 37 | `ifdef RISCV_FORMAL_CSR_MISA 38 | wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 0) == `RISCV_FORMAL_XLEN'h 0; 39 | assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 0; 40 | `else 41 | wire misa_ok = 1; 42 | `endif 43 | 44 | // SLLW instruction 45 | wire [4:0] shamt = rvfi_rs2_rdata[4:0]; 46 | wire [31:0] result = rvfi_rs1_rdata[31:0] << shamt; 47 | assign spec_valid = rvfi_valid && !insn_padding && insn_funct7 == 7'b 0000000 && insn_funct3 == 3'b 001 && insn_opcode == 7'b 0111011; 48 | assign spec_rs1_addr = insn_rs1; 49 | assign spec_rs2_addr = insn_rs2; 50 | assign spec_rd_addr = insn_rd; 51 | assign spec_rd_wdata = spec_rd_addr ? {{`RISCV_FORMAL_XLEN-32{result[31]}}, result} : 0; 52 | assign spec_pc_wdata = rvfi_pc_rdata + 4; 53 | 54 | // default assignments 55 | assign spec_trap = !misa_ok; 56 | assign spec_mem_addr = 0; 57 | assign spec_mem_rmask = 0; 58 | assign spec_mem_wmask = 0; 59 | assign spec_mem_wdata = 0; 60 | endmodule 61 | -------------------------------------------------------------------------------- /insns/insn_slt.v: -------------------------------------------------------------------------------- 1 | // DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py 2 | 3 | module rvfi_insn_slt ( 4 | input rvfi_valid, 5 | input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, 6 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, 7 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, 8 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, 9 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, 10 | `ifdef RISCV_FORMAL_CSR_MISA 11 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, 12 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, 13 | `endif 14 | 15 | output spec_valid, 16 | output spec_trap, 17 | output [ 4 : 0] spec_rs1_addr, 18 | output [ 4 : 0] spec_rs2_addr, 19 | output [ 4 : 0] spec_rd_addr, 20 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, 21 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, 22 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, 23 | output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, 24 | output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, 25 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata 26 | ); 27 | 28 | // R-type instruction format 29 | wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 32; 30 | wire [6:0] insn_funct7 = rvfi_insn[31:25]; 31 | wire [4:0] insn_rs2 = rvfi_insn[24:20]; 32 | wire [4:0] insn_rs1 = rvfi_insn[19:15]; 33 | wire [2:0] insn_funct3 = rvfi_insn[14:12]; 34 | wire [4:0] insn_rd = rvfi_insn[11: 7]; 35 | wire [6:0] insn_opcode = rvfi_insn[ 6: 0]; 36 | 37 | `ifdef RISCV_FORMAL_CSR_MISA 38 | wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 0) == `RISCV_FORMAL_XLEN'h 0; 39 | assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 0; 40 | `else 41 | wire misa_ok = 1; 42 | `endif 43 | 44 | // SLT instruction 45 | wire [`RISCV_FORMAL_XLEN-1:0] result = $signed(rvfi_rs1_rdata) < $signed(rvfi_rs2_rdata); 46 | assign spec_valid = rvfi_valid && !insn_padding && insn_funct7 == 7'b 0000000 && insn_funct3 == 3'b 010 && insn_opcode == 7'b 0110011; 47 | assign spec_rs1_addr = insn_rs1; 48 | assign spec_rs2_addr = insn_rs2; 49 | assign spec_rd_addr = insn_rd; 50 | assign spec_rd_wdata = spec_rd_addr ? result : 0; 51 | assign spec_pc_wdata = rvfi_pc_rdata + 4; 52 | 53 | // default assignments 54 | assign spec_trap = !misa_ok; 55 | assign spec_mem_addr = 0; 56 | assign spec_mem_rmask = 0; 57 | assign spec_mem_wmask = 0; 58 | assign spec_mem_wdata = 0; 59 | endmodule 60 | -------------------------------------------------------------------------------- /insns/insn_slti.v: -------------------------------------------------------------------------------- 1 | // DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py 2 | 3 | module rvfi_insn_slti ( 4 | input rvfi_valid, 5 | input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, 6 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, 7 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, 8 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, 9 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, 10 | `ifdef RISCV_FORMAL_CSR_MISA 11 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, 12 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, 13 | `endif 14 | 15 | output spec_valid, 16 | output spec_trap, 17 | output [ 4 : 0] spec_rs1_addr, 18 | output [ 4 : 0] spec_rs2_addr, 19 | output [ 4 : 0] spec_rd_addr, 20 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, 21 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, 22 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, 23 | output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, 24 | output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, 25 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata 26 | ); 27 | 28 | // I-type instruction format 29 | wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 32; 30 | wire [`RISCV_FORMAL_XLEN-1:0] insn_imm = $signed(rvfi_insn[31:20]); 31 | wire [4:0] insn_rs1 = rvfi_insn[19:15]; 32 | wire [2:0] insn_funct3 = rvfi_insn[14:12]; 33 | wire [4:0] insn_rd = rvfi_insn[11: 7]; 34 | wire [6:0] insn_opcode = rvfi_insn[ 6: 0]; 35 | 36 | `ifdef RISCV_FORMAL_CSR_MISA 37 | wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 0) == `RISCV_FORMAL_XLEN'h 0; 38 | assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 0; 39 | `else 40 | wire misa_ok = 1; 41 | `endif 42 | 43 | // SLTI instruction 44 | wire [`RISCV_FORMAL_XLEN-1:0] result = $signed(rvfi_rs1_rdata) < $signed(insn_imm); 45 | assign spec_valid = rvfi_valid && !insn_padding && insn_funct3 == 3'b 010 && insn_opcode == 7'b 0010011; 46 | assign spec_rs1_addr = insn_rs1; 47 | assign spec_rd_addr = insn_rd; 48 | assign spec_rd_wdata = spec_rd_addr ? result : 0; 49 | assign spec_pc_wdata = rvfi_pc_rdata + 4; 50 | 51 | // default assignments 52 | assign spec_rs2_addr = 0; 53 | assign spec_trap = !misa_ok; 54 | assign spec_mem_addr = 0; 55 | assign spec_mem_rmask = 0; 56 | assign spec_mem_wmask = 0; 57 | assign spec_mem_wdata = 0; 58 | endmodule 59 | -------------------------------------------------------------------------------- /insns/insn_sltiu.v: -------------------------------------------------------------------------------- 1 | // DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py 2 | 3 | module rvfi_insn_sltiu ( 4 | input rvfi_valid, 5 | input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, 6 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, 7 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, 8 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, 9 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, 10 | `ifdef RISCV_FORMAL_CSR_MISA 11 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, 12 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, 13 | `endif 14 | 15 | output spec_valid, 16 | output spec_trap, 17 | output [ 4 : 0] spec_rs1_addr, 18 | output [ 4 : 0] spec_rs2_addr, 19 | output [ 4 : 0] spec_rd_addr, 20 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, 21 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, 22 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, 23 | output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, 24 | output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, 25 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata 26 | ); 27 | 28 | // I-type instruction format 29 | wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 32; 30 | wire [`RISCV_FORMAL_XLEN-1:0] insn_imm = $signed(rvfi_insn[31:20]); 31 | wire [4:0] insn_rs1 = rvfi_insn[19:15]; 32 | wire [2:0] insn_funct3 = rvfi_insn[14:12]; 33 | wire [4:0] insn_rd = rvfi_insn[11: 7]; 34 | wire [6:0] insn_opcode = rvfi_insn[ 6: 0]; 35 | 36 | `ifdef RISCV_FORMAL_CSR_MISA 37 | wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 0) == `RISCV_FORMAL_XLEN'h 0; 38 | assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 0; 39 | `else 40 | wire misa_ok = 1; 41 | `endif 42 | 43 | // SLTIU instruction 44 | wire [`RISCV_FORMAL_XLEN-1:0] result = rvfi_rs1_rdata < insn_imm; 45 | assign spec_valid = rvfi_valid && !insn_padding && insn_funct3 == 3'b 011 && insn_opcode == 7'b 0010011; 46 | assign spec_rs1_addr = insn_rs1; 47 | assign spec_rd_addr = insn_rd; 48 | assign spec_rd_wdata = spec_rd_addr ? result : 0; 49 | assign spec_pc_wdata = rvfi_pc_rdata + 4; 50 | 51 | // default assignments 52 | assign spec_rs2_addr = 0; 53 | assign spec_trap = !misa_ok; 54 | assign spec_mem_addr = 0; 55 | assign spec_mem_rmask = 0; 56 | assign spec_mem_wmask = 0; 57 | assign spec_mem_wdata = 0; 58 | endmodule 59 | -------------------------------------------------------------------------------- /insns/insn_sltu.v: -------------------------------------------------------------------------------- 1 | // DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py 2 | 3 | module rvfi_insn_sltu ( 4 | input rvfi_valid, 5 | input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, 6 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, 7 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, 8 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, 9 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, 10 | `ifdef RISCV_FORMAL_CSR_MISA 11 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, 12 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, 13 | `endif 14 | 15 | output spec_valid, 16 | output spec_trap, 17 | output [ 4 : 0] spec_rs1_addr, 18 | output [ 4 : 0] spec_rs2_addr, 19 | output [ 4 : 0] spec_rd_addr, 20 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, 21 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, 22 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, 23 | output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, 24 | output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, 25 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata 26 | ); 27 | 28 | // R-type instruction format 29 | wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 32; 30 | wire [6:0] insn_funct7 = rvfi_insn[31:25]; 31 | wire [4:0] insn_rs2 = rvfi_insn[24:20]; 32 | wire [4:0] insn_rs1 = rvfi_insn[19:15]; 33 | wire [2:0] insn_funct3 = rvfi_insn[14:12]; 34 | wire [4:0] insn_rd = rvfi_insn[11: 7]; 35 | wire [6:0] insn_opcode = rvfi_insn[ 6: 0]; 36 | 37 | `ifdef RISCV_FORMAL_CSR_MISA 38 | wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 0) == `RISCV_FORMAL_XLEN'h 0; 39 | assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 0; 40 | `else 41 | wire misa_ok = 1; 42 | `endif 43 | 44 | // SLTU instruction 45 | wire [`RISCV_FORMAL_XLEN-1:0] result = rvfi_rs1_rdata < rvfi_rs2_rdata; 46 | assign spec_valid = rvfi_valid && !insn_padding && insn_funct7 == 7'b 0000000 && insn_funct3 == 3'b 011 && insn_opcode == 7'b 0110011; 47 | assign spec_rs1_addr = insn_rs1; 48 | assign spec_rs2_addr = insn_rs2; 49 | assign spec_rd_addr = insn_rd; 50 | assign spec_rd_wdata = spec_rd_addr ? result : 0; 51 | assign spec_pc_wdata = rvfi_pc_rdata + 4; 52 | 53 | // default assignments 54 | assign spec_trap = !misa_ok; 55 | assign spec_mem_addr = 0; 56 | assign spec_mem_rmask = 0; 57 | assign spec_mem_wmask = 0; 58 | assign spec_mem_wdata = 0; 59 | endmodule 60 | -------------------------------------------------------------------------------- /insns/insn_srai.v: -------------------------------------------------------------------------------- 1 | // DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py 2 | 3 | module rvfi_insn_srai ( 4 | input rvfi_valid, 5 | input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, 6 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, 7 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, 8 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, 9 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, 10 | `ifdef RISCV_FORMAL_CSR_MISA 11 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, 12 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, 13 | `endif 14 | 15 | output spec_valid, 16 | output spec_trap, 17 | output [ 4 : 0] spec_rs1_addr, 18 | output [ 4 : 0] spec_rs2_addr, 19 | output [ 4 : 0] spec_rd_addr, 20 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, 21 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, 22 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, 23 | output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, 24 | output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, 25 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata 26 | ); 27 | 28 | // I-type instruction format (shift variation) 29 | wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 32; 30 | wire [6:0] insn_funct6 = rvfi_insn[31:26]; 31 | wire [5:0] insn_shamt = rvfi_insn[25:20]; 32 | wire [4:0] insn_rs1 = rvfi_insn[19:15]; 33 | wire [2:0] insn_funct3 = rvfi_insn[14:12]; 34 | wire [4:0] insn_rd = rvfi_insn[11: 7]; 35 | wire [6:0] insn_opcode = rvfi_insn[ 6: 0]; 36 | 37 | `ifdef RISCV_FORMAL_CSR_MISA 38 | wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 0) == `RISCV_FORMAL_XLEN'h 0; 39 | assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 0; 40 | `else 41 | wire misa_ok = 1; 42 | `endif 43 | 44 | // SRAI instruction 45 | wire [`RISCV_FORMAL_XLEN-1:0] result = $signed(rvfi_rs1_rdata) >>> insn_shamt; 46 | assign spec_valid = rvfi_valid && !insn_padding && insn_funct6 == 6'b 010000 && insn_funct3 == 3'b 101 && insn_opcode == 7'b 0010011 && (!insn_shamt[5] || `RISCV_FORMAL_XLEN == 64); 47 | assign spec_rs1_addr = insn_rs1; 48 | assign spec_rd_addr = insn_rd; 49 | assign spec_rd_wdata = spec_rd_addr ? result : 0; 50 | assign spec_pc_wdata = rvfi_pc_rdata + 4; 51 | 52 | // default assignments 53 | assign spec_rs2_addr = 0; 54 | assign spec_trap = !misa_ok; 55 | assign spec_mem_addr = 0; 56 | assign spec_mem_rmask = 0; 57 | assign spec_mem_wmask = 0; 58 | assign spec_mem_wdata = 0; 59 | endmodule 60 | -------------------------------------------------------------------------------- /insns/insn_sraiw.v: -------------------------------------------------------------------------------- 1 | // DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py 2 | 3 | module rvfi_insn_sraiw ( 4 | input rvfi_valid, 5 | input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, 6 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, 7 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, 8 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, 9 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, 10 | `ifdef RISCV_FORMAL_CSR_MISA 11 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, 12 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, 13 | `endif 14 | 15 | output spec_valid, 16 | output spec_trap, 17 | output [ 4 : 0] spec_rs1_addr, 18 | output [ 4 : 0] spec_rs2_addr, 19 | output [ 4 : 0] spec_rd_addr, 20 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, 21 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, 22 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, 23 | output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, 24 | output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, 25 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata 26 | ); 27 | 28 | // I-type instruction format (shift variation) 29 | wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 32; 30 | wire [6:0] insn_funct6 = rvfi_insn[31:26]; 31 | wire [5:0] insn_shamt = rvfi_insn[25:20]; 32 | wire [4:0] insn_rs1 = rvfi_insn[19:15]; 33 | wire [2:0] insn_funct3 = rvfi_insn[14:12]; 34 | wire [4:0] insn_rd = rvfi_insn[11: 7]; 35 | wire [6:0] insn_opcode = rvfi_insn[ 6: 0]; 36 | 37 | `ifdef RISCV_FORMAL_CSR_MISA 38 | wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 0) == `RISCV_FORMAL_XLEN'h 0; 39 | assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 0; 40 | `else 41 | wire misa_ok = 1; 42 | `endif 43 | 44 | // SRAIW instruction 45 | wire [31:0] result = $signed(rvfi_rs1_rdata[31:0]) >>> insn_shamt; 46 | assign spec_valid = rvfi_valid && !insn_padding && insn_funct6 == 6'b 010000 && insn_funct3 == 3'b 101 && insn_opcode == 7'b 0011011 && !insn_shamt[5]; 47 | assign spec_rs1_addr = insn_rs1; 48 | assign spec_rd_addr = insn_rd; 49 | assign spec_rd_wdata = spec_rd_addr ? {{`RISCV_FORMAL_XLEN-32{result[31]}}, result} : 0; 50 | assign spec_pc_wdata = rvfi_pc_rdata + 4; 51 | 52 | // default assignments 53 | assign spec_rs2_addr = 0; 54 | assign spec_trap = !misa_ok; 55 | assign spec_mem_addr = 0; 56 | assign spec_mem_rmask = 0; 57 | assign spec_mem_wmask = 0; 58 | assign spec_mem_wdata = 0; 59 | endmodule 60 | -------------------------------------------------------------------------------- /insns/insn_srli.v: -------------------------------------------------------------------------------- 1 | // DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py 2 | 3 | module rvfi_insn_srli ( 4 | input rvfi_valid, 5 | input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, 6 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, 7 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, 8 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, 9 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, 10 | `ifdef RISCV_FORMAL_CSR_MISA 11 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, 12 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, 13 | `endif 14 | 15 | output spec_valid, 16 | output spec_trap, 17 | output [ 4 : 0] spec_rs1_addr, 18 | output [ 4 : 0] spec_rs2_addr, 19 | output [ 4 : 0] spec_rd_addr, 20 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, 21 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, 22 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, 23 | output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, 24 | output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, 25 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata 26 | ); 27 | 28 | // I-type instruction format (shift variation) 29 | wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 32; 30 | wire [6:0] insn_funct6 = rvfi_insn[31:26]; 31 | wire [5:0] insn_shamt = rvfi_insn[25:20]; 32 | wire [4:0] insn_rs1 = rvfi_insn[19:15]; 33 | wire [2:0] insn_funct3 = rvfi_insn[14:12]; 34 | wire [4:0] insn_rd = rvfi_insn[11: 7]; 35 | wire [6:0] insn_opcode = rvfi_insn[ 6: 0]; 36 | 37 | `ifdef RISCV_FORMAL_CSR_MISA 38 | wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 0) == `RISCV_FORMAL_XLEN'h 0; 39 | assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 0; 40 | `else 41 | wire misa_ok = 1; 42 | `endif 43 | 44 | // SRLI instruction 45 | wire [`RISCV_FORMAL_XLEN-1:0] result = rvfi_rs1_rdata >> insn_shamt; 46 | assign spec_valid = rvfi_valid && !insn_padding && insn_funct6 == 6'b 000000 && insn_funct3 == 3'b 101 && insn_opcode == 7'b 0010011 && (!insn_shamt[5] || `RISCV_FORMAL_XLEN == 64); 47 | assign spec_rs1_addr = insn_rs1; 48 | assign spec_rd_addr = insn_rd; 49 | assign spec_rd_wdata = spec_rd_addr ? result : 0; 50 | assign spec_pc_wdata = rvfi_pc_rdata + 4; 51 | 52 | // default assignments 53 | assign spec_rs2_addr = 0; 54 | assign spec_trap = !misa_ok; 55 | assign spec_mem_addr = 0; 56 | assign spec_mem_rmask = 0; 57 | assign spec_mem_wmask = 0; 58 | assign spec_mem_wdata = 0; 59 | endmodule 60 | -------------------------------------------------------------------------------- /insns/insn_srliw.v: -------------------------------------------------------------------------------- 1 | // DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py 2 | 3 | module rvfi_insn_srliw ( 4 | input rvfi_valid, 5 | input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, 6 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, 7 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, 8 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, 9 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, 10 | `ifdef RISCV_FORMAL_CSR_MISA 11 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, 12 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, 13 | `endif 14 | 15 | output spec_valid, 16 | output spec_trap, 17 | output [ 4 : 0] spec_rs1_addr, 18 | output [ 4 : 0] spec_rs2_addr, 19 | output [ 4 : 0] spec_rd_addr, 20 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, 21 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, 22 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, 23 | output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, 24 | output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, 25 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata 26 | ); 27 | 28 | // I-type instruction format (shift variation) 29 | wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 32; 30 | wire [6:0] insn_funct6 = rvfi_insn[31:26]; 31 | wire [5:0] insn_shamt = rvfi_insn[25:20]; 32 | wire [4:0] insn_rs1 = rvfi_insn[19:15]; 33 | wire [2:0] insn_funct3 = rvfi_insn[14:12]; 34 | wire [4:0] insn_rd = rvfi_insn[11: 7]; 35 | wire [6:0] insn_opcode = rvfi_insn[ 6: 0]; 36 | 37 | `ifdef RISCV_FORMAL_CSR_MISA 38 | wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 0) == `RISCV_FORMAL_XLEN'h 0; 39 | assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 0; 40 | `else 41 | wire misa_ok = 1; 42 | `endif 43 | 44 | // SRLIW instruction 45 | wire [31:0] result = rvfi_rs1_rdata[31:0] >> insn_shamt; 46 | assign spec_valid = rvfi_valid && !insn_padding && insn_funct6 == 6'b 000000 && insn_funct3 == 3'b 101 && insn_opcode == 7'b 0011011 && !insn_shamt[5]; 47 | assign spec_rs1_addr = insn_rs1; 48 | assign spec_rd_addr = insn_rd; 49 | assign spec_rd_wdata = spec_rd_addr ? {{`RISCV_FORMAL_XLEN-32{result[31]}}, result} : 0; 50 | assign spec_pc_wdata = rvfi_pc_rdata + 4; 51 | 52 | // default assignments 53 | assign spec_rs2_addr = 0; 54 | assign spec_trap = !misa_ok; 55 | assign spec_mem_addr = 0; 56 | assign spec_mem_rmask = 0; 57 | assign spec_mem_wmask = 0; 58 | assign spec_mem_wdata = 0; 59 | endmodule 60 | -------------------------------------------------------------------------------- /insns/insn_sub.v: -------------------------------------------------------------------------------- 1 | // DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py 2 | 3 | module rvfi_insn_sub ( 4 | input rvfi_valid, 5 | input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, 6 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, 7 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, 8 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, 9 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, 10 | `ifdef RISCV_FORMAL_CSR_MISA 11 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, 12 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, 13 | `endif 14 | 15 | output spec_valid, 16 | output spec_trap, 17 | output [ 4 : 0] spec_rs1_addr, 18 | output [ 4 : 0] spec_rs2_addr, 19 | output [ 4 : 0] spec_rd_addr, 20 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, 21 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, 22 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, 23 | output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, 24 | output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, 25 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata 26 | ); 27 | 28 | // R-type instruction format 29 | wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 32; 30 | wire [6:0] insn_funct7 = rvfi_insn[31:25]; 31 | wire [4:0] insn_rs2 = rvfi_insn[24:20]; 32 | wire [4:0] insn_rs1 = rvfi_insn[19:15]; 33 | wire [2:0] insn_funct3 = rvfi_insn[14:12]; 34 | wire [4:0] insn_rd = rvfi_insn[11: 7]; 35 | wire [6:0] insn_opcode = rvfi_insn[ 6: 0]; 36 | 37 | `ifdef RISCV_FORMAL_CSR_MISA 38 | wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 0) == `RISCV_FORMAL_XLEN'h 0; 39 | assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 0; 40 | `else 41 | wire misa_ok = 1; 42 | `endif 43 | 44 | // SUB instruction 45 | wire [`RISCV_FORMAL_XLEN-1:0] result = rvfi_rs1_rdata - rvfi_rs2_rdata; 46 | assign spec_valid = rvfi_valid && !insn_padding && insn_funct7 == 7'b 0100000 && insn_funct3 == 3'b 000 && insn_opcode == 7'b 0110011; 47 | assign spec_rs1_addr = insn_rs1; 48 | assign spec_rs2_addr = insn_rs2; 49 | assign spec_rd_addr = insn_rd; 50 | assign spec_rd_wdata = spec_rd_addr ? result : 0; 51 | assign spec_pc_wdata = rvfi_pc_rdata + 4; 52 | 53 | // default assignments 54 | assign spec_trap = !misa_ok; 55 | assign spec_mem_addr = 0; 56 | assign spec_mem_rmask = 0; 57 | assign spec_mem_wmask = 0; 58 | assign spec_mem_wdata = 0; 59 | endmodule 60 | -------------------------------------------------------------------------------- /insns/insn_subw.v: -------------------------------------------------------------------------------- 1 | // DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py 2 | 3 | module rvfi_insn_subw ( 4 | input rvfi_valid, 5 | input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, 6 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, 7 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, 8 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, 9 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, 10 | `ifdef RISCV_FORMAL_CSR_MISA 11 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, 12 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, 13 | `endif 14 | 15 | output spec_valid, 16 | output spec_trap, 17 | output [ 4 : 0] spec_rs1_addr, 18 | output [ 4 : 0] spec_rs2_addr, 19 | output [ 4 : 0] spec_rd_addr, 20 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, 21 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, 22 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, 23 | output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, 24 | output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, 25 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata 26 | ); 27 | 28 | // R-type instruction format 29 | wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 32; 30 | wire [6:0] insn_funct7 = rvfi_insn[31:25]; 31 | wire [4:0] insn_rs2 = rvfi_insn[24:20]; 32 | wire [4:0] insn_rs1 = rvfi_insn[19:15]; 33 | wire [2:0] insn_funct3 = rvfi_insn[14:12]; 34 | wire [4:0] insn_rd = rvfi_insn[11: 7]; 35 | wire [6:0] insn_opcode = rvfi_insn[ 6: 0]; 36 | 37 | `ifdef RISCV_FORMAL_CSR_MISA 38 | wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 0) == `RISCV_FORMAL_XLEN'h 0; 39 | assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 0; 40 | `else 41 | wire misa_ok = 1; 42 | `endif 43 | 44 | // SUBW instruction 45 | wire [31:0] result = rvfi_rs1_rdata[31:0] - rvfi_rs2_rdata[31:0]; 46 | assign spec_valid = rvfi_valid && !insn_padding && insn_funct7 == 7'b 0100000 && insn_funct3 == 3'b 000 && insn_opcode == 7'b 0111011; 47 | assign spec_rs1_addr = insn_rs1; 48 | assign spec_rs2_addr = insn_rs2; 49 | assign spec_rd_addr = insn_rd; 50 | assign spec_rd_wdata = spec_rd_addr ? {{`RISCV_FORMAL_XLEN-32{result[31]}}, result} : 0; 51 | assign spec_pc_wdata = rvfi_pc_rdata + 4; 52 | 53 | // default assignments 54 | assign spec_trap = !misa_ok; 55 | assign spec_mem_addr = 0; 56 | assign spec_mem_rmask = 0; 57 | assign spec_mem_wmask = 0; 58 | assign spec_mem_wdata = 0; 59 | endmodule 60 | -------------------------------------------------------------------------------- /insns/insn_xor.v: -------------------------------------------------------------------------------- 1 | // DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py 2 | 3 | module rvfi_insn_xor ( 4 | input rvfi_valid, 5 | input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, 6 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, 7 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, 8 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, 9 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, 10 | `ifdef RISCV_FORMAL_CSR_MISA 11 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, 12 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, 13 | `endif 14 | 15 | output spec_valid, 16 | output spec_trap, 17 | output [ 4 : 0] spec_rs1_addr, 18 | output [ 4 : 0] spec_rs2_addr, 19 | output [ 4 : 0] spec_rd_addr, 20 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, 21 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, 22 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, 23 | output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, 24 | output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, 25 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata 26 | ); 27 | 28 | // R-type instruction format 29 | wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 32; 30 | wire [6:0] insn_funct7 = rvfi_insn[31:25]; 31 | wire [4:0] insn_rs2 = rvfi_insn[24:20]; 32 | wire [4:0] insn_rs1 = rvfi_insn[19:15]; 33 | wire [2:0] insn_funct3 = rvfi_insn[14:12]; 34 | wire [4:0] insn_rd = rvfi_insn[11: 7]; 35 | wire [6:0] insn_opcode = rvfi_insn[ 6: 0]; 36 | 37 | `ifdef RISCV_FORMAL_CSR_MISA 38 | wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 0) == `RISCV_FORMAL_XLEN'h 0; 39 | assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 0; 40 | `else 41 | wire misa_ok = 1; 42 | `endif 43 | 44 | // XOR instruction 45 | wire [`RISCV_FORMAL_XLEN-1:0] result = rvfi_rs1_rdata ^ rvfi_rs2_rdata; 46 | assign spec_valid = rvfi_valid && !insn_padding && insn_funct7 == 7'b 0000000 && insn_funct3 == 3'b 100 && insn_opcode == 7'b 0110011; 47 | assign spec_rs1_addr = insn_rs1; 48 | assign spec_rs2_addr = insn_rs2; 49 | assign spec_rd_addr = insn_rd; 50 | assign spec_rd_wdata = spec_rd_addr ? result : 0; 51 | assign spec_pc_wdata = rvfi_pc_rdata + 4; 52 | 53 | // default assignments 54 | assign spec_trap = !misa_ok; 55 | assign spec_mem_addr = 0; 56 | assign spec_mem_rmask = 0; 57 | assign spec_mem_wmask = 0; 58 | assign spec_mem_wdata = 0; 59 | endmodule 60 | -------------------------------------------------------------------------------- /insns/insn_xori.v: -------------------------------------------------------------------------------- 1 | // DO NOT EDIT -- auto-generated from riscv-formal/insns/generate.py 2 | 3 | module rvfi_insn_xori ( 4 | input rvfi_valid, 5 | input [`RISCV_FORMAL_ILEN - 1 : 0] rvfi_insn, 6 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_pc_rdata, 7 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs1_rdata, 8 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_rs2_rdata, 9 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_mem_rdata, 10 | `ifdef RISCV_FORMAL_CSR_MISA 11 | input [`RISCV_FORMAL_XLEN - 1 : 0] rvfi_csr_misa_rdata, 12 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_csr_misa_rmask, 13 | `endif 14 | 15 | output spec_valid, 16 | output spec_trap, 17 | output [ 4 : 0] spec_rs1_addr, 18 | output [ 4 : 0] spec_rs2_addr, 19 | output [ 4 : 0] spec_rd_addr, 20 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_rd_wdata, 21 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_pc_wdata, 22 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_addr, 23 | output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_rmask, 24 | output [`RISCV_FORMAL_XLEN/8 - 1 : 0] spec_mem_wmask, 25 | output [`RISCV_FORMAL_XLEN - 1 : 0] spec_mem_wdata 26 | ); 27 | 28 | // I-type instruction format 29 | wire [`RISCV_FORMAL_ILEN-1:0] insn_padding = rvfi_insn >> 32; 30 | wire [`RISCV_FORMAL_XLEN-1:0] insn_imm = $signed(rvfi_insn[31:20]); 31 | wire [4:0] insn_rs1 = rvfi_insn[19:15]; 32 | wire [2:0] insn_funct3 = rvfi_insn[14:12]; 33 | wire [4:0] insn_rd = rvfi_insn[11: 7]; 34 | wire [6:0] insn_opcode = rvfi_insn[ 6: 0]; 35 | 36 | `ifdef RISCV_FORMAL_CSR_MISA 37 | wire misa_ok = (rvfi_csr_misa_rdata & `RISCV_FORMAL_XLEN'h 0) == `RISCV_FORMAL_XLEN'h 0; 38 | assign spec_csr_misa_rmask = `RISCV_FORMAL_XLEN'h 0; 39 | `else 40 | wire misa_ok = 1; 41 | `endif 42 | 43 | // XORI instruction 44 | wire [`RISCV_FORMAL_XLEN-1:0] result = rvfi_rs1_rdata ^ insn_imm; 45 | assign spec_valid = rvfi_valid && !insn_padding && insn_funct3 == 3'b 100 && insn_opcode == 7'b 0010011; 46 | assign spec_rs1_addr = insn_rs1; 47 | assign spec_rd_addr = insn_rd; 48 | assign spec_rd_wdata = spec_rd_addr ? result : 0; 49 | assign spec_pc_wdata = rvfi_pc_rdata + 4; 50 | 51 | // default assignments 52 | assign spec_rs2_addr = 0; 53 | assign spec_trap = !misa_ok; 54 | assign spec_mem_addr = 0; 55 | assign spec_mem_rmask = 0; 56 | assign spec_mem_wmask = 0; 57 | assign spec_mem_wdata = 0; 58 | endmodule 59 | -------------------------------------------------------------------------------- /insns/isa_rv32i.txt: -------------------------------------------------------------------------------- 1 | add 2 | addi 3 | and 4 | andi 5 | auipc 6 | beq 7 | bge 8 | bgeu 9 | blt 10 | bltu 11 | bne 12 | jal 13 | jalr 14 | lb 15 | lbu 16 | lh 17 | lhu 18 | lui 19 | lw 20 | or 21 | ori 22 | sb 23 | sh 24 | sll 25 | slli 26 | slt 27 | slti 28 | sltiu 29 | sltu 30 | sra 31 | srai 32 | srl 33 | srli 34 | sub 35 | sw 36 | xor 37 | xori 38 | -------------------------------------------------------------------------------- /insns/isa_rv32ic.txt: -------------------------------------------------------------------------------- 1 | add 2 | addi 3 | and 4 | andi 5 | auipc 6 | beq 7 | bge 8 | bgeu 9 | blt 10 | bltu 11 | bne 12 | c_add 13 | c_addi 14 | c_addi16sp 15 | c_addi4spn 16 | c_and 17 | c_andi 18 | c_beqz 19 | c_bnez 20 | c_j 21 | c_jal 22 | c_jalr 23 | c_jr 24 | c_li 25 | c_lui 26 | c_lw 27 | c_lwsp 28 | c_mv 29 | c_or 30 | c_slli 31 | c_srai 32 | c_srli 33 | c_sub 34 | c_sw 35 | c_swsp 36 | c_xor 37 | jal 38 | jalr 39 | lb 40 | lbu 41 | lh 42 | lhu 43 | lui 44 | lw 45 | or 46 | ori 47 | sb 48 | sh 49 | sll 50 | slli 51 | slt 52 | slti 53 | sltiu 54 | sltu 55 | sra 56 | srai 57 | srl 58 | srli 59 | sub 60 | sw 61 | xor 62 | xori 63 | -------------------------------------------------------------------------------- /insns/isa_rv32im.txt: -------------------------------------------------------------------------------- 1 | add 2 | addi 3 | and 4 | andi 5 | auipc 6 | beq 7 | bge 8 | bgeu 9 | blt 10 | bltu 11 | bne 12 | div 13 | divu 14 | jal 15 | jalr 16 | lb 17 | lbu 18 | lh 19 | lhu 20 | lui 21 | lw 22 | mul 23 | mulh 24 | mulhsu 25 | mulhu 26 | or 27 | ori 28 | rem 29 | remu 30 | sb 31 | sh 32 | sll 33 | slli 34 | slt 35 | slti 36 | sltiu 37 | sltu 38 | sra 39 | srai 40 | srl 41 | srli 42 | sub 43 | sw 44 | xor 45 | xori 46 | -------------------------------------------------------------------------------- /insns/isa_rv32imc.txt: -------------------------------------------------------------------------------- 1 | add 2 | addi 3 | and 4 | andi 5 | auipc 6 | beq 7 | bge 8 | bgeu 9 | blt 10 | bltu 11 | bne 12 | c_add 13 | c_addi 14 | c_addi16sp 15 | c_addi4spn 16 | c_and 17 | c_andi 18 | c_beqz 19 | c_bnez 20 | c_j 21 | c_jal 22 | c_jalr 23 | c_jr 24 | c_li 25 | c_lui 26 | c_lw 27 | c_lwsp 28 | c_mv 29 | c_or 30 | c_slli 31 | c_srai 32 | c_srli 33 | c_sub 34 | c_sw 35 | c_swsp 36 | c_xor 37 | div 38 | divu 39 | jal 40 | jalr 41 | lb 42 | lbu 43 | lh 44 | lhu 45 | lui 46 | lw 47 | mul 48 | mulh 49 | mulhsu 50 | mulhu 51 | or 52 | ori 53 | rem 54 | remu 55 | sb 56 | sh 57 | sll 58 | slli 59 | slt 60 | slti 61 | sltiu 62 | sltu 63 | sra 64 | srai 65 | srl 66 | srli 67 | sub 68 | sw 69 | xor 70 | xori 71 | -------------------------------------------------------------------------------- /insns/isa_rv64i.txt: -------------------------------------------------------------------------------- 1 | add 2 | addi 3 | addiw 4 | addw 5 | and 6 | andi 7 | auipc 8 | beq 9 | bge 10 | bgeu 11 | blt 12 | bltu 13 | bne 14 | jal 15 | jalr 16 | lb 17 | lbu 18 | ld 19 | lh 20 | lhu 21 | lui 22 | lw 23 | lwu 24 | or 25 | ori 26 | sb 27 | sd 28 | sh 29 | sll 30 | slli 31 | slliw 32 | sllw 33 | slt 34 | slti 35 | sltiu 36 | sltu 37 | sra 38 | srai 39 | sraiw 40 | sraw 41 | srl 42 | srli 43 | srliw 44 | srlw 45 | sub 46 | subw 47 | sw 48 | xor 49 | xori 50 | -------------------------------------------------------------------------------- /insns/isa_rv64ic.txt: -------------------------------------------------------------------------------- 1 | add 2 | addi 3 | addiw 4 | addw 5 | and 6 | andi 7 | auipc 8 | beq 9 | bge 10 | bgeu 11 | blt 12 | bltu 13 | bne 14 | c_add 15 | c_addi 16 | c_addi16sp 17 | c_addi4spn 18 | c_addiw 19 | c_addw 20 | c_and 21 | c_andi 22 | c_beqz 23 | c_bnez 24 | c_j 25 | c_jalr 26 | c_jr 27 | c_ld 28 | c_ldsp 29 | c_li 30 | c_lui 31 | c_lw 32 | c_lwsp 33 | c_mv 34 | c_or 35 | c_sd 36 | c_sdsp 37 | c_slli 38 | c_srai 39 | c_srli 40 | c_sub 41 | c_subw 42 | c_sw 43 | c_swsp 44 | c_xor 45 | jal 46 | jalr 47 | lb 48 | lbu 49 | ld 50 | lh 51 | lhu 52 | lui 53 | lw 54 | lwu 55 | or 56 | ori 57 | sb 58 | sd 59 | sh 60 | sll 61 | slli 62 | slliw 63 | sllw 64 | slt 65 | slti 66 | sltiu 67 | sltu 68 | sra 69 | srai 70 | sraiw 71 | sraw 72 | srl 73 | srli 74 | srliw 75 | srlw 76 | sub 77 | subw 78 | sw 79 | xor 80 | xori 81 | -------------------------------------------------------------------------------- /insns/isa_rv64im.txt: -------------------------------------------------------------------------------- 1 | add 2 | addi 3 | addiw 4 | addw 5 | and 6 | andi 7 | auipc 8 | beq 9 | bge 10 | bgeu 11 | blt 12 | bltu 13 | bne 14 | div 15 | divu 16 | divuw 17 | divw 18 | jal 19 | jalr 20 | lb 21 | lbu 22 | ld 23 | lh 24 | lhu 25 | lui 26 | lw 27 | lwu 28 | mul 29 | mulh 30 | mulhsu 31 | mulhu 32 | mulw 33 | or 34 | ori 35 | rem 36 | remu 37 | remuw 38 | remw 39 | sb 40 | sd 41 | sh 42 | sll 43 | slli 44 | slliw 45 | sllw 46 | slt 47 | slti 48 | sltiu 49 | sltu 50 | sra 51 | srai 52 | sraiw 53 | sraw 54 | srl 55 | srli 56 | srliw 57 | srlw 58 | sub 59 | subw 60 | sw 61 | xor 62 | xori 63 | -------------------------------------------------------------------------------- /insns/isa_rv64imc.txt: -------------------------------------------------------------------------------- 1 | add 2 | addi 3 | addiw 4 | addw 5 | and 6 | andi 7 | auipc 8 | beq 9 | bge 10 | bgeu 11 | blt 12 | bltu 13 | bne 14 | c_add 15 | c_addi 16 | c_addi16sp 17 | c_addi4spn 18 | c_addiw 19 | c_addw 20 | c_and 21 | c_andi 22 | c_beqz 23 | c_bnez 24 | c_j 25 | c_jalr 26 | c_jr 27 | c_ld 28 | c_ldsp 29 | c_li 30 | c_lui 31 | c_lw 32 | c_lwsp 33 | c_mv 34 | c_or 35 | c_sd 36 | c_sdsp 37 | c_slli 38 | c_srai 39 | c_srli 40 | c_sub 41 | c_subw 42 | c_sw 43 | c_swsp 44 | c_xor 45 | div 46 | divu 47 | divuw 48 | divw 49 | jal 50 | jalr 51 | lb 52 | lbu 53 | ld 54 | lh 55 | lhu 56 | lui 57 | lw 58 | lwu 59 | mul 60 | mulh 61 | mulhsu 62 | mulhu 63 | mulw 64 | or 65 | ori 66 | rem 67 | remu 68 | remuw 69 | remw 70 | sb 71 | sd 72 | sh 73 | sll 74 | slli 75 | slliw 76 | sllw 77 | slt 78 | slti 79 | sltiu 80 | sltu 81 | sra 82 | srai 83 | sraiw 84 | sraw 85 | srl 86 | srli 87 | srliw 88 | srlw 89 | sub 90 | subw 91 | sw 92 | xor 93 | xori 94 | -------------------------------------------------------------------------------- /tests/coverage/.gitignore: -------------------------------------------------------------------------------- 1 | /coverage_rv32 2 | /coverage_rv64 3 | /isa_coverage_rv32i.v 4 | /isa_coverage_rv32ic.v 5 | /isa_coverage_rv64i.v 6 | /isa_coverage_rv64ic.v 7 | -------------------------------------------------------------------------------- /tests/coverage/coverage.sby: -------------------------------------------------------------------------------- 1 | [tasks] 2 | rv32 3 | rv64 4 | 5 | [options] 6 | mode bmc 7 | depth 1 8 | 9 | [engines] 10 | smtbmc yices 11 | 12 | [script] 13 | verilog_defines -D RISCV_FORMAL 14 | verilog_defines -D RISCV_FORMAL_NRET=1 15 | rv32: verilog_defines -D RISCV_FORMAL_XLEN=32 16 | rv64: verilog_defines -D RISCV_FORMAL_XLEN=64 17 | verilog_defines -D RISCV_FORMAL_ILEN=32 18 | verilog_defines -D RISCV_FORMAL_COMPRESSED 19 | read_verilog -sv rvfi_macros.vh 20 | 21 | --pycode-begin-- 22 | import os 23 | for filename in os.listdir("../../insns/"): 24 | if filename.startswith("insn_") and filename.endswith(".v"): 25 | output("read_verilog -sv %s" % filename) 26 | --pycode-end-- 27 | 28 | read_verilog isa_coverage_rv32i.v 29 | read_verilog isa_coverage_rv32ic.v 30 | 31 | read_verilog isa_coverage_rv64i.v 32 | read_verilog isa_coverage_rv64ic.v 33 | 34 | read_verilog riscv_rv32i_insn.v 35 | read_verilog riscv_rv32ic_insn.v 36 | 37 | read_verilog riscv_rv64i_insn.v 38 | read_verilog riscv_rv64ic_insn.v 39 | 40 | read_verilog -sv coverage.sv 41 | rv32: prep -flatten -top coverage32 42 | rv64: prep -flatten -top coverage64 43 | 44 | [files] 45 | coverage.sv 46 | ../../checks/rvfi_macros.vh 47 | 48 | --pycode-begin-- 49 | import os 50 | for filename in os.listdir("../../insns/"): 51 | if filename.startswith("insn_") and filename.endswith(".v"): 52 | output("../../insns/%s" % filename) 53 | --pycode-end-- 54 | 55 | isa_coverage_rv32i.v 56 | isa_coverage_rv32ic.v 57 | 58 | isa_coverage_rv64i.v 59 | isa_coverage_rv64ic.v 60 | 61 | riscv_rv32i_insn.v 62 | riscv_rv32ic_insn.v 63 | 64 | riscv_rv64i_insn.v 65 | riscv_rv64ic_insn.v 66 | -------------------------------------------------------------------------------- /tests/coverage/coverage.sv: -------------------------------------------------------------------------------- 1 | module coverage32(input [31:0] insn); 2 | wire [`ISA_COVERAGE_LEN_RV32I-1:0] insn_valid_rv32i; 3 | wire [`ISA_COVERAGE_LEN_RV32IC-1:0] insn_valid_rv32ic; 4 | 5 | wire riscv_rv32i_valid; 6 | wire riscv_rv32ic_valid; 7 | 8 | isa_coverage_rv32i isa_coverage_rv32i_inst (.insn(insn), .valid(insn_valid_rv32i )); 9 | isa_coverage_rv32ic isa_coverage_rv32ic_inst (.insn(insn), .valid(insn_valid_rv32ic)); 10 | 11 | riscv_rv32i_insn riscv_rv32i_insn_inst (.insn(insn), .valid(riscv_rv32i_valid )); 12 | riscv_rv32ic_insn riscv_rv32ic_insn_inst (.insn(insn), .valid(riscv_rv32ic_valid)); 13 | 14 | always_comb begin 15 | // check one-hot conditions 16 | assert(insn_valid_rv32i == (insn_valid_rv32i & -insn_valid_rv32i )); 17 | assert(insn_valid_rv32ic == (insn_valid_rv32ic & -insn_valid_rv32ic)); 18 | 19 | // check insn hierarchy 20 | if (insn_valid_rv32i) assert(insn_valid_rv32ic); 21 | 22 | // check hand-written checkers 23 | assert(riscv_rv32i_valid == |insn_valid_rv32i); 24 | assert(riscv_rv32ic_valid == |insn_valid_rv32ic); 25 | end 26 | endmodule 27 | 28 | module coverage64(input [31:0] insn); 29 | wire [`ISA_COVERAGE_LEN_RV64I-1:0] insn_valid_rv64i; 30 | wire [`ISA_COVERAGE_LEN_RV64IC-1:0] insn_valid_rv64ic; 31 | 32 | wire riscv_rv64i_valid; 33 | wire riscv_rv64ic_valid; 34 | 35 | isa_coverage_rv64i isa_coverage_rv64i_inst (.insn(insn), .valid(insn_valid_rv64i )); 36 | isa_coverage_rv64ic isa_coverage_rv64ic_inst (.insn(insn), .valid(insn_valid_rv64ic)); 37 | 38 | riscv_rv64i_insn riscv_rv64i_insn_inst (.insn(insn), .valid(riscv_rv64i_valid )); 39 | riscv_rv64ic_insn riscv_rv64ic_insn_inst (.insn(insn), .valid(riscv_rv64ic_valid)); 40 | 41 | always_comb begin 42 | // check one-hot conditions 43 | assert(insn_valid_rv64i == (insn_valid_rv64i & -insn_valid_rv64i )); 44 | assert(insn_valid_rv64ic == (insn_valid_rv64ic & -insn_valid_rv64ic)); 45 | 46 | // check insn hierarchy 47 | if (insn_valid_rv64i) assert(insn_valid_rv64ic); 48 | 49 | // check hand-written checkers 50 | assert(riscv_rv64i_valid == |insn_valid_rv64i); 51 | assert(riscv_rv64ic_valid == |insn_valid_rv64ic); 52 | end 53 | endmodule 54 | -------------------------------------------------------------------------------- /tests/coverage/generate.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python3 2 | 3 | def handle_isa(isa): 4 | with open("../../insns/isa_%s.txt" % isa, "r") as f: 5 | insns = f.read().split() 6 | 7 | with open("isa_coverage_%s.v" % isa, "w") as f: 8 | print("// DO NOT EDIT -- auto-generated from riscv-formal/tests/coverage/generate.py", file=f) 9 | print("", file=f) 10 | 11 | print("`define ISA_COVERAGE_LEN_%s %d" % (isa.upper(), len(insns)), file=f) 12 | print("module isa_coverage_%s (input [31:0] insn, output [%d:0] valid);" % (isa, len(insns)-1), file=f) 13 | 14 | for index, insn in enumerate(sorted(insns)): 15 | print(" rvfi_insn_%s insn_%s (" % (insn, insn), file=f) 16 | print(" .rvfi_valid(1'b1),", file=f) 17 | print(" .rvfi_insn(insn),", file=f) 18 | print(" .rvfi_pc_rdata(32'h00000000),", file=f) 19 | print(" .rvfi_rs1_rdata(32'h00000000),", file=f) 20 | print(" .rvfi_rs2_rdata(32'h00000000),", file=f) 21 | print(" .rvfi_mem_rdata(32'h00000000),", file=f) 22 | print(" .spec_valid(valid[%d])" % index, file=f) 23 | print(" );", file=f) 24 | 25 | print("endmodule", file=f) 26 | 27 | handle_isa("rv32i") 28 | handle_isa("rv32ic") 29 | handle_isa("rv64i") 30 | handle_isa("rv64ic") 31 | -------------------------------------------------------------------------------- /tests/coverage/riscv_rv32i_insn.v: -------------------------------------------------------------------------------- 1 | // Check if a given instruction is an RV32I instruction (without SYSTEM opcode) 2 | // 3 | module riscv_rv32i_insn ( 4 | input [31:0] insn, 5 | output reg valid 6 | ); 7 | always @* begin 8 | valid = 0; 9 | 10 | if (insn[6:0] == 7'b 01_101_11) valid = 1; // LUI 11 | if (insn[6:0] == 7'b 00_101_11) valid = 1; // AUIPC 12 | if (insn[6:0] == 7'b 11_011_11) valid = 1; // JAL 13 | 14 | if (insn[6:0] == 7'b 11_001_11) begin // JALR 15 | valid = insn[14:12] == 3'b 000; 16 | end 17 | 18 | if (insn[6:0] == 7'b 11_000_11) begin // BRANCH 19 | valid = (insn[14:12] != 3'b 010) && (insn[14:12] != 3'b 011); 20 | end 21 | 22 | if (insn[6:0] == 7'b 00_000_11) begin // LOAD 23 | valid = (insn[14:12] != 3'b 011) && (insn[14:12] != 3'b 110) && (insn[14:12] != 3'b 111); 24 | end 25 | 26 | if (insn[6:0] == 7'b 01_000_11) begin // STORE 27 | valid = (insn[14:12] == 3'b 000) || (insn[14:12] == 3'b 001) || (insn[14:12] == 3'b 010); 28 | end 29 | 30 | if (insn[6:0] == 7'b 00_100_11) begin // OP-IMM 31 | case (insn[14:12]) 32 | 3'b 001: begin // SLLI 33 | valid = insn[31:25] == 7'b 0000000; 34 | end 35 | 3'b 101: begin // SRLI SRAI 36 | valid = (insn[31:25] == 7'b 0000000) || (insn[31:25] == 7'b 0100000); 37 | end 38 | default: begin 39 | valid = 1; 40 | end 41 | endcase 42 | end 43 | 44 | if (insn[6:0] == 7'b 01_100_11) begin // OP 45 | case (insn[14:12]) 46 | 3'b 000, 3'b 101: begin // ADD SUB SRL SRA 47 | valid = (insn[31:25] == 7'b 0000000) || (insn[31:25] == 7'b 0100000); 48 | end 49 | default: begin 50 | valid = insn[31:25] == 7'b 0000000; 51 | end 52 | endcase 53 | end 54 | end 55 | endmodule 56 | -------------------------------------------------------------------------------- /tests/coverage/riscv_rv64i_insn.v: -------------------------------------------------------------------------------- 1 | // Check if a given instruction is an RV64I instruction (without SYSTEM opcode) 2 | // 3 | module riscv_rv64i_insn ( 4 | input [31:0] insn, 5 | output reg valid 6 | ); 7 | always @* begin 8 | valid = 0; 9 | 10 | if (insn[6:0] == 7'b 01_101_11) valid = 1; // LUI 11 | if (insn[6:0] == 7'b 00_101_11) valid = 1; // AUIPC 12 | if (insn[6:0] == 7'b 11_011_11) valid = 1; // JAL 13 | 14 | if (insn[6:0] == 7'b 11_001_11) begin // JALR 15 | valid = insn[14:12] == 3'b 000; 16 | end 17 | 18 | if (insn[6:0] == 7'b 11_000_11) begin // BRANCH 19 | valid = (insn[14:12] != 3'b 010) && (insn[14:12] != 3'b 011); 20 | end 21 | 22 | if (insn[6:0] == 7'b 00_000_11) begin // LOAD 23 | valid = (insn[14:12] != 3'b 111); 24 | end 25 | 26 | if (insn[6:0] == 7'b 01_000_11) begin // STORE 27 | valid = (insn[14:12] == 3'b 000) || (insn[14:12] == 3'b 001) || (insn[14:12] == 3'b 010) || (insn[14:12] == 3'b 011); 28 | end 29 | 30 | if (insn[6:0] == 7'b 00_100_11) begin // OP-IMM 31 | case (insn[14:12]) 32 | 3'b 001: begin // SLLI 33 | valid = insn[31:26] == 6'b 000000; 34 | end 35 | 3'b 101: begin // SRLI SRAI 36 | valid = (insn[31:26] == 6'b 000000) || (insn[31:26] == 6'b 010000); 37 | end 38 | default: begin 39 | valid = 1; 40 | end 41 | endcase 42 | end 43 | 44 | if (insn[6:0] == 7'b 01_100_11) begin // OP 45 | case (insn[14:12]) 46 | 3'b 000, 3'b 101: begin // ADD SUB SRL SRA 47 | valid = (insn[31:25] == 7'b 0000000) || (insn[31:25] == 7'b 0100000); 48 | end 49 | default: begin 50 | valid = insn[31:25] == 7'b 0000000; 51 | end 52 | endcase 53 | end 54 | 55 | if (insn[6:0] == 7'b 00_110_11) begin // OP-IMM-32 56 | case (insn[14:12]) 57 | 3'b 001: begin // SLLIW 58 | valid = insn[31:25] == 7'b 0000000; 59 | end 60 | 3'b 101: begin // SRLIW SRAIW 61 | valid = (insn[31:25] == 7'b 0000000) || (insn[31:25] == 7'b 0100000); 62 | end 63 | 3'b 000: begin // ADDIW 64 | valid = 1; 65 | end 66 | endcase 67 | end 68 | 69 | if (insn[6:0] == 7'b 01_110_11) begin // OP-32 70 | case (insn[14:12]) 71 | 3'b 000, 3'b 101: begin // ADDW SUBW SRLW SRAW 72 | valid = (insn[31:25] == 7'b 0000000) || (insn[31:25] == 7'b 0100000); 73 | end 74 | 3'b 001: begin // SLLW 75 | valid = insn[31:25] == 7'b 0000000; 76 | end 77 | endcase 78 | end 79 | end 80 | endmodule 81 | -------------------------------------------------------------------------------- /tests/semantics/.gitignore: -------------------------------------------------------------------------------- 1 | /riscv-semantics 2 | /insn_* 3 | -------------------------------------------------------------------------------- /tests/semantics/Makefile: -------------------------------------------------------------------------------- 1 | define template 2 | all:: insn_$(1)/PASS 3 | 4 | insn_$(1)/PASS: insn_$(1).sby riscv-semantics/.stamp 5 | sby -f insn_$(1).sby 6 | 7 | insn_$(1).sby: makejob.py riscv-semantics/.stamp 8 | python3 makejob.py $(1) 9 | 10 | clean:: 11 | rm -rf insn_$(1) insn_$(1).sby 12 | endef 13 | 14 | $(foreach job,$(shell cat ../../insns/isa_rv32i.txt),$(eval $(call template,$(job)))) 15 | 16 | riscv-semantics/.stamp: 17 | set -ex; git clone --recursive https://github.com/mit-plv/riscv-semantics; \ 18 | cd riscv-semantics; ./install.sh; ./install-clash.sh; ./make-circuit.sh 19 | touch riscv-semantics/.stamp 20 | 21 | distclean: clean 22 | rm -rf riscv-semantics 23 | -------------------------------------------------------------------------------- /tests/semantics/makejob.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python3 2 | 3 | import sys, glob, os 4 | 5 | insn = sys.argv[1] 6 | clash_files = glob.glob("riscv-semantics/src/verilog/Clash/rvspec/*.v") 7 | 8 | with open("insn_%s.sby" % insn, "w") as f: 9 | print("[options]", file=f) 10 | print("mode bmc", file=f) 11 | print("depth 1", file=f) 12 | print("", file=f) 13 | 14 | print("[engines]", file=f) 15 | print("smtbmc boolector", file=f) 16 | print("", file=f) 17 | 18 | print("[script]", file=f) 19 | print("read_verilog -sv defines.vh", file=f) 20 | print("read_verilog -sv rvfi_macros.vh", file=f) 21 | print("read_verilog -sv top.sv", file=f) 22 | print("read_verilog -sv insn_%s.v" % insn, file=f) 23 | for fn in clash_files: 24 | print("read_verilog %s" % os.path.basename(fn), file=f) 25 | print("prep -nordff -top top", file=f) 26 | print("flatten rvspec", file=f) 27 | print("hierarchy", file=f) 28 | print("opt -fast", file=f) 29 | 30 | print("[file defines.vh]", file=f) 31 | print("`define RISCV_FORMAL", file=f) 32 | print("`define RISCV_FORMAL_XLEN 32", file=f) 33 | print("`define RISCV_FORMAL_ILEN 32", file=f) 34 | print("`define RISCV_FORMAL_INSN_MODEL rvfi_insn_%s" % insn, file=f) 35 | print("`define RISCV_FORMAL_ALIGNED_MEM", file=f) 36 | # print("`define RISCV_FORMAL_COMPRESSED", file=f) 37 | print("", file=f) 38 | 39 | print("[files]", file=f) 40 | print("top.sv", file=f) 41 | print("../../checks/rvfi_macros.vh", file=f) 42 | print("../../insns/insn_%s.v" % insn, file=f) 43 | for fn in clash_files: 44 | print(fn, file=f) 45 | -------------------------------------------------------------------------------- /tests/spike/.gitignore: -------------------------------------------------------------------------------- 1 | test_*.cc 2 | test_*.h 3 | test_*.ok 4 | test_*.v 5 | test_*.yslog 6 | test_*.cbmc_out 7 | riscv-isa-sim 8 | makefile 9 | --------------------------------------------------------------------------------