├── .gitignore ├── LICENSE ├── README.md ├── examples └── loopback │ ├── README.md │ ├── create_project.tcl │ ├── hardware │ └── loopback.vhd │ └── software │ ├── Makefile │ └── loopback.cpp ├── hardware ├── src │ ├── common │ │ ├── channel_types.vhd │ │ ├── host_types.vhd │ │ ├── tlp_types.vhd │ │ ├── transceiver_128bit_types.vhd │ │ └── utils.vhd │ ├── debug │ │ ├── dbg_entities.vhd │ │ ├── dbg_host_rx_channel_monitor.vhd │ │ ├── dbg_host_tx_channel_monitor.vhd │ │ └── dbg_types.vhd │ ├── endpoint │ │ ├── config_channel │ │ │ ├── cfg_channel_completer.vhd │ │ │ ├── cfg_channel_controller.vhd │ │ │ ├── cfg_channel_decoder.vhd │ │ │ ├── cfg_channel_memory.vhd │ │ │ ├── cfg_channel_types.vhd │ │ │ └── config_channel.vhd │ │ ├── endpoint_core.vhd │ │ ├── gen2_endpoint.vhd │ │ ├── msix_table.vhd │ │ ├── packet_arbiter.vhd │ │ ├── rx_axi_converter.vhd │ │ ├── rx_bar_demux.vhd │ │ ├── rx_cpld_preprocessor.vhd │ │ ├── tlp_tag_mapper │ │ │ ├── rx_tag_restorer.vhd │ │ │ ├── tlp_tag_mapper.vhd │ │ │ ├── tlp_tag_memory.vhd │ │ │ ├── tx_tag_replacer.vhd │ │ │ └── virtual_tag_memory.vhd │ │ ├── tx_axi_converter.vhd │ │ ├── tx_interrupt_mux.vhd │ │ └── tx_tlp_mux.vhd │ ├── fpga_channel │ │ ├── filter.vhd │ │ ├── fpga_rx_channel.vhd │ │ ├── fpga_tx_channel.vhd │ │ ├── rx_cfg_ctrl.vhd │ │ ├── rx_fifo.vhd │ │ ├── rx_fifo_internal.vhd │ │ ├── rx_filter.vhd │ │ ├── rx_output_count.vhd │ │ ├── rx_repack.vhd │ │ ├── rx_write_request.vhd │ │ ├── tx_cfg_ctrl.vhd │ │ ├── tx_cfg_ctrl_types.vhd │ │ ├── tx_controller.vhd │ │ ├── tx_fifo.vhd │ │ ├── tx_fifo_internal.vhd │ │ ├── tx_fifo_types.vhd │ │ ├── tx_pack_data.vhd │ │ └── tx_write_cpld.vhd │ ├── host_channel │ │ ├── channel_DNCtoDVC.vhd │ │ ├── channel_DVCtoDNC.vhd │ │ ├── dma_decoder.vhd │ │ ├── dma_decoder_filter.vhd │ │ ├── dma_decoder_instructor.vhd │ │ ├── dma_interrupt_handler.vhd │ │ ├── dma_requester.vhd │ │ ├── dma_writer_packer.vhd │ │ ├── host_channel_types.vhd │ │ ├── host_rx_channel.vhd │ │ ├── host_tx_channel.vhd │ │ ├── input_ctrl.vhd │ │ ├── output_buf.vhd │ │ ├── output_ctrl.vhd │ │ ├── pipe_reg.vhd │ │ ├── pipe_register.vhd │ │ ├── rx_dma_buffer.vhd │ │ ├── rx_dma_interrupt_handler.vhd │ │ ├── rx_dma_interrupt_handler_filter.vhd │ │ ├── rx_dma_writer.vhd │ │ ├── rx_dma_writer_arbiter.vhd │ │ ├── tx_dma_fifo.vhd │ │ ├── tx_dma_interrupt_handler.vhd │ │ ├── tx_dma_interrupt_handler_filter.vhd │ │ ├── tx_dma_writer.vhd │ │ ├── tx_dma_writer_buffer.vhd │ │ └── tx_mwr32_shifter_128.vhd │ ├── ip │ │ ├── VC707_PCIe_constraints.xdc │ │ └── pcie_7x_0.xci │ ├── pcie.vhd │ ├── pcie_utilities.vhd │ └── utilities │ │ └── tx_timeout.vhd └── tests │ ├── hw │ ├── dbg_controller.vhd │ ├── dbg_endpoint_monitor.vhd │ ├── dbg_host_rx_channel_monitor.vhd │ ├── dbg_host_tx_channel_monitor.vhd │ ├── dbg_rx_channel_evaluator.vhd │ ├── dbg_tx_channel_evaluator.vhd │ ├── dbg_types.vhd │ ├── fpga_multichannel_eval_top.vhd │ └── host_multichannel_eval_top.vhd │ └── sim │ ├── fpga_channel │ ├── tb_pcie_fifo_128.vhd │ ├── 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