├── .gitignore ├── INSTALL ├── LICENSE ├── Makefile.am ├── README.md ├── autogen.sh ├── configure.ac ├── doc ├── .gitignore ├── DoxygenLayout.xml ├── README ├── contact.md ├── development.md ├── docgroups.dox ├── download.md ├── doxygen.cfg ├── examples.md ├── examples │ └── glip-simple.c ├── img │ └── glip-overview.svg ├── logic.md └── mainpage.md ├── doxygen.am ├── include └── libglip.h ├── libglip.pc.in ├── m4 ├── .gitignore └── ax_prog_doxygen.m4 └── src ├── Makefile.am ├── backend_cypressfx2 ├── doc │ ├── firmware.md │ ├── logic.md │ ├── overview.md │ └── sw.md ├── fw │ └── ztex │ │ ├── .gitignore │ │ ├── Makefile │ │ └── fw.c ├── logic │ ├── boards │ │ ├── ztex_115 │ │ │ ├── fx2.sdc │ │ │ └── fx2.ucf │ │ └── ztex_213 │ │ │ ├── fx2.sdc │ │ │ ├── fx2.ucf │ │ │ └── fx2.xdc │ ├── demo │ │ ├── ztex_115_loopback │ │ │ ├── .gitignore │ │ │ ├── Makefile │ │ │ ├── README.md │ │ │ ├── loopback_synplify.prj │ │ │ ├── ztex_115.sdc │ │ │ ├── ztex_115.ucf │ │ │ └── ztex_115_loopback.v │ │ └── ztex_213_loopback │ │ │ ├── .gitignore │ │ │ ├── Makefile │ │ │ ├── README.md │ │ │ ├── loopback_synplify.prj │ │ │ ├── loopback_vivado.tcl │ │ │ ├── ztex_213.sdc │ │ │ ├── ztex_213.ucf │ │ │ ├── ztex_213.xdc │ │ │ └── ztex_213_loopback.v │ └── verilog │ │ └── glip_cypressfx2_toplevel.v └── sw │ ├── backend_cypressfx2.c │ └── backend_cypressfx2.h ├── backend_cypressfx3 ├── doc │ ├── firmware.md │ ├── logic.md │ ├── overview.md │ └── sw.md ├── fw │ ├── SlaveFifoSync16.img │ ├── SlaveFifoSync16.patch │ ├── SlaveFifoSync32.img │ └── SlaveFifoSync32.patch ├── logic │ ├── backend_cypressfx3.core │ ├── backend_cypressfx3_vcu108_16.core │ ├── backend_cypressfx3_vcu108_32.core │ ├── boards │ │ ├── kc705 │ │ │ └── fx3.xdc │ │ └── vcu108 │ │ │ ├── fmc_hpc1.xdc │ │ │ └── fmc_hpc1_32.xdc │ ├── demo │ │ ├── kc705_loopback │ │ │ ├── .gitignore │ │ │ ├── Makefile │ │ │ ├── README.md │ │ │ ├── kc705.xdc │ │ │ ├── kc705_debug.xdc │ │ │ ├── kc705_loopback.v │ │ │ ├── kc705_loopback_clock.v │ │ │ ├── lcd.v │ │ │ ├── measure_count.v │ │ │ ├── vivado_16.tcl │ │ │ └── vivado_32.tcl │ │ ├── vcu108_loopback │ │ │ ├── .gitignore │ │ │ ├── Makefile │ │ │ ├── README.md │ │ │ ├── vcu108.xdc │ │ │ ├── vcu108_loopback.v │ │ │ ├── vcu108_loopback_clock.v │ │ │ ├── vivado_16.tcl │ │ │ └── vivado_32.tcl │ │ └── vcu108_stress_test │ │ │ ├── .gitignore │ │ │ ├── Makefile │ │ │ ├── README.md │ │ │ ├── vcu108.xdc │ │ │ ├── vcu108_fx3_stress_test.v │ │ │ ├── vcu108_stress_test_clock.v │ │ │ ├── vivado_16.tcl │ │ │ └── vivado_32.tcl │ └── verilog │ │ └── glip_cypressfx3_toplevel.sv └── sw │ ├── backend_cypressfx3.c │ └── backend_cypressfx3.h ├── backend_jtag ├── doc │ ├── logic.md │ ├── overview.md │ ├── protocol.md │ └── sw.md ├── logic │ ├── boards │ │ └── ztex_115 │ │ │ ├── jtag.sdc │ │ │ └── jtag.ucf │ ├── demo │ │ └── ztex_115_loopback │ │ │ ├── .gitignore │ │ │ ├── Makefile │ │ │ ├── README.md │ │ │ ├── loopback_synplify.prj │ │ │ ├── ztex_115.ucf │ │ │ └── ztex_115_loopback.v │ └── verilog │ │ ├── glip_jtag_config_discovery_fsm.v │ │ ├── glip_jtag_fifo.v │ │ ├── glip_jtag_input_fsm.v │ │ ├── glip_jtag_output_fsm.v │ │ ├── glip_jtag_tap.v │ │ ├── glip_jtag_tap_defines.v │ │ └── glip_jtag_toplevel.v ├── openocd │ └── glip.cfg └── sw │ ├── backend_jtag.c │ └── backend_jtag.h ├── backend_tcp ├── doc │ └── overview.md ├── logic │ ├── demo │ │ ├── verilator_dpi_loopback │ │ │ ├── .gitignore │ │ │ ├── Makefile │ │ │ ├── main.cpp │ │ │ └── tb_verilator_dpi_loopback.v │ │ └── verilator_dpi_stress_test │ │ │ ├── .gitignore │ │ │ ├── Makefile │ │ │ ├── main.cpp │ │ │ └── tb_verilator_dpi_stress_test.v │ ├── dpi │ │ ├── GlipTcp.cpp │ │ ├── GlipTcp.h │ │ ├── glip_tcp.core │ │ ├── glip_tcp_dpi.cpp │ │ └── glip_tcp_toplevel.sv │ └── systemc │ │ ├── glip_tcp_toplevel.cpp │ │ └── glip_tcp_toplevel.h └── sw │ ├── backend_tcp.c │ └── backend_tcp.h ├── backend_uart ├── doc │ ├── logic.md │ ├── overview.md │ ├── protocol.md │ └── sw.md ├── logic │ ├── backend_uart.core │ ├── boards │ │ ├── nexys4ddr │ │ │ └── nexys4ddr.xdc │ │ └── vcu108 │ │ │ └── vcu108.xdc │ ├── demo │ │ ├── nexys4ddr │ │ │ ├── .gitignore │ │ │ ├── Makefile │ │ │ ├── README.md │ │ │ ├── nexys4ddr.v │ │ │ └── vivado.tcl │ │ ├── vcu108_loopback │ │ │ ├── .gitignore │ │ │ ├── Makefile │ │ │ ├── README.md │ │ │ ├── vcu108_loopback.v │ │ │ └── vivado.tcl │ │ └── vcu108_stress_test │ │ │ ├── .gitignore │ │ │ ├── Makefile │ │ │ ├── README.md │ │ │ ├── vcu108_stress_test.v │ │ │ └── vivado.tcl │ └── verilog │ │ ├── glip_uart_control.v │ │ ├── glip_uart_control_egress.v │ │ ├── glip_uart_control_ingress.v │ │ ├── glip_uart_receive.v │ │ ├── glip_uart_toplevel.v │ │ └── glip_uart_transmit.v └── sw │ ├── backend_uart.c │ └── backend_uart.h ├── cbuf.c ├── cbuf.h ├── common └── logic │ ├── bcdcounter │ ├── README.md │ └── bcdcounter.v │ ├── credit │ ├── glip_credit.core │ └── verilog │ │ ├── README.md │ │ ├── creditor.v │ │ └── debtor.v │ ├── fifo │ ├── fifo_dualclock_fwft.core │ ├── fifo_dualclock_standard.core │ ├── fifo_singleclock_fwft.core │ ├── fifo_singleclock_noc.core │ ├── fifo_singleclock_standard.core │ ├── test │ │ ├── fifo_test_common.py │ │ ├── test_fifo_dualclock_fwft.manifest.yaml │ │ ├── test_fifo_dualclock_fwft.py │ │ ├── test_fifo_dualclock_standard.manifest.yaml │ │ ├── test_fifo_dualclock_standard.py │ │ ├── test_fifo_singleclock_fwft.manifest.yaml │ │ ├── test_fifo_singleclock_fwft.py │ │ ├── test_fifo_singleclock_standard.manifest.yaml │ │ └── test_fifo_singleclock_standard.py │ └── verilog │ │ ├── fifo_dualclock_fwft.sv │ │ ├── fifo_dualclock_standard.sv │ │ ├── fifo_singleclock_fwft.sv │ │ ├── fifo_singleclock_noc.sv │ │ └── fifo_singleclock_standard.sv │ ├── interface │ ├── glip_channel.core │ └── glip_channel.sv │ ├── measure │ ├── README.md │ ├── glip_measure.v │ └── glip_measure_sevensegment.v │ ├── nexys4ddr │ └── nexys4ddr_display.v │ ├── scaler │ ├── glip_scaler.core │ └── verilog │ │ ├── glip_downscale.sv │ │ └── glip_upscale.sv │ ├── sevensegment │ ├── README.md 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