├── .vscode └── systemverilog.code-snippets ├── README.md ├── experiment ├── 01display │ ├── Nexys4DDR_Master.xdc │ ├── controller.sv │ ├── display.bit │ ├── sim.sv │ ├── sources.tcl │ └── top.sv ├── 02simulation │ ├── decoder.sv │ └── sim.sv ├── lab1 │ ├── Nexys4DDR_Master.xdc │ ├── README.pdf │ ├── ans.v │ ├── display │ │ ├── decoder2_4.sv │ │ ├── encoder4_2.sv │ │ └── priority_encoder4_2.sv │ ├── lab1.sv │ ├── myans.sv │ ├── readme.md │ ├── sim.sv │ ├── sources.tcl │ └── top.sv ├── lab2 │ ├── Nexys4DDR_Master.xdc │ ├── ans.v │ ├── decoder.sv │ ├── display │ │ └── lab2.drawio │ ├── imem.sv │ ├── lab2.sv │ ├── lab2.svh │ ├── myans.sv │ ├── readme.md │ ├── ref.svh │ ├── sim.sv │ ├── sources.tcl │ └── top.sv ├── lab3 │ ├── Nexys4DDR_Master.xdc │ ├── lab3 copy.sv │ ├── lab3 加更.md │ ├── lab3.sv │ ├── sim.sv │ ├── sources.tcl │ └── top.sv ├── lab4 │ ├── 74LS138.pdf │ ├── 74LS151.pdf │ ├── Nexys4DDR_Master.xdc │ ├── ans.sv │ ├── lab4.md │ ├── lab4.pdf │ ├── lab4.sv │ ├── lab4display.md │ ├── sim.sv │ ├── sources.tcl │ └── top.sv ├── lab5 │ ├── 74LS194.pdf │ ├── Nexys4DDR_Master.xdc │ ├── asset │ │ ├── circuit.jpg │ │ ├── ff.jpg │ │ ├── ff_reset.jpg │ │ └── 微信图片_20201119201959.jpg │ ├── clock_convert.sv │ ├── display.md │ ├── lab5.sv │ ├── sim.sv │ ├── sn74ls175.pdf │ ├── sources.tcl │ ├── submit.md │ ├── top.sv │ └── 实验五 提交.pdf ├── lab6 │ ├── Nexys4DDR_Master.xdc │ ├── display.md │ ├── lab6.md │ ├── lab6.pdf │ ├── lab6.sv │ ├── lab6.svh │ ├── sim.sv │ ├── sources.tcl │ └── top.sv └── lab7 │ ├── 74LS377.pdf │ ├── Nexys4DDR_Master.xdc │ ├── lab7.md │ ├── lab7.pdf │ ├── lab7.sv │ ├── ram2.sv │ ├── sim.sv │ ├── sources.tcl │ └── top.sv ├── notes ├── 00引言 │ └── 00引言.md ├── 01开发流程（上） │ ├── 01开发流程（上）.md │ ├── 01开发流程（上）.pdf │ └── assets │ │ ├── account.PNG │ │ ├── agree.PNG │ │ ├── customize.PNG │ │ ├── directory.PNG │ │ ├── edition.PNG │ │ ├── progress.PNG │ │ ├── structure.PNG │ │ └── summary.PNG ├── 02开发流程（中） │ ├── 02开发流程（中）.md │ ├── 02开发流程（中）.pdf │ ├── assets │ │ ├── board_files.PNG │ │ ├── circuit.jpg │ │ ├── default_board.PNG │ │ └── default_part.PNG │ └── board_files.zip ├── 03开发流程（下） │ ├── 03开发流程（下）.md │ └── 03开发流程（下）.pdf ├── lab1 │ ├── SV Syntax for lab1.md │ └── display.md ├── systemverilog │ ├── 1.jpg │ ├── 2.jpg │ ├── systemverilog语法简介.md │ └── systemverilog语法简介.pdf ├── 实验一 │ ├── img │ │ ├── decoder │ │ └── encoder │ ├── 实验一 译码器与编码器.md │ └── 实验一 译码器与编码器.pdf ├── 实验三 │ └── 实验三 加法器及快速进位电路的设计.md ├── 实验二 │ ├── img_lab2 │ │ └── 身份证.jpg │ ├── 实验二 译码与编码的应用.md │ └── 实验二 译码与编码的应用.pdf ├── 实验五 │ └── 实验五 触发器和寄存器.md ├── 实验六 │ ├── light.jpg │ └── 实验六 有限状态机_1.md └── 实验四 │ └── 实验四 算数逻辑单元的设计.md └── syntax ├── 10interface └── interface.md ├── 1bits ├── bits.drawio └── bits.md ├── 2oprators └── oprator.md ├── 3assign └── assign.md ├── 4module └── module.md ├── 5always_comb ├── always_comb.md ├── case.md └── if_for.md ├── 6always_ff └── always_ff.md ├── 7typedef └── typedef.md ├── 8parameter └── parameter.md └── 9precomplie └── 预编译.md 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