├── and.inc ├── nand.inc ├── nor.inc ├── not.inc ├── fig ├── .gitignore ├── schematic.sh ├── inv_schematic.tex ├── nor2_schematic.tex ├── nand2_schematic.tex ├── nand4_schematic.tex ├── nand8_schematic.tex ├── SR_latch_clk_schematic.tex ├── and8a_schematic.tex ├── and8b_schematic.tex ├── and8c_schematic.tex ├── and8a.tex ├── and8b.tex ├── inv.tex ├── nand2.tex ├── nor2.tex ├── and8c.tex ├── nand4.tex ├── SR_latch_clk.tex ├── nand8.tex ├── plot_inv_t.svg ├── plot_and8c_t.svg ├── plot_and8b_t.svg ├── plot_and2_t.svg ├── plot_and8a_t.svg ├── plot_nor2_t.svg ├── plot_nand2_t.svg ├── plot_sr_latch_t.svg └── and8a_schematic.svg ├── .spiceinit ├── .gitattributes ├── report ├── NGSPICE_CMOS_Report.pdf └── ref.bib ├── pages ├── LIC.md ├── inv_cir.md ├── inv_inc.md ├── nand2_cir.md ├── nand2_inc.md ├── spiceinit.md └── FreePDK45_README.md ├── _config.yml ├── FreePDK45 ├── ff.inc ├── ss.inc ├── nom.inc ├── README └── tran_models │ ├── models_ff │ ├── PMOS_THKOX.inc │ ├── NMOS_THKOX.inc │ ├── NMOS_VTG.inc │ ├── NMOS_VTL.inc │ ├── PMOS_VTH.inc │ ├── NMOS_VTH.inc │ └── PMOS_VTG.inc │ ├── models_ss │ ├── PMOS_THKOX.inc │ ├── NMOS_THKOX.inc │ ├── NMOS_VTG.inc │ ├── NMOS_VTL.inc │ ├── PMOS_VTH.inc │ ├── NMOS_VTH.inc │ └── PMOS_VTG.inc │ └── models_nom │ ├── NMOS_THKOX.inc │ ├── PMOS_THKOX.inc │ ├── NMOS_VTG.inc │ ├── NMOS_VTL.inc │ ├── PMOS_VTH.inc │ └── NMOS_VTH.inc ├── and8a.inc ├── and4b.inc ├── and2.inc ├── and8b.inc ├── .vscode └── settings.json ├── inv.inc ├── nand4a.inc ├── and8c.inc ├── and8_test_pow.inc ├── SR_latch_clk.inc ├── nor2.inc ├── nand2.inc ├── LICENSE ├── and8_test_inv2.inc ├── nand8a.inc ├── .github └── workflows │ └── jekyll-gh-pages.yml ├── inv.cir ├── nor2.cir ├── nand2.cir ├── and2.cir ├── SR_latch_clk.cir ├── and8b.cir ├── and8c.cir ├── and8a.cir └── .gitignore /and.inc: -------------------------------------------------------------------------------- 1 | and2.inc -------------------------------------------------------------------------------- /nand.inc: -------------------------------------------------------------------------------- 1 | nand2.inc -------------------------------------------------------------------------------- /nor.inc: -------------------------------------------------------------------------------- 1 | nor2.inc -------------------------------------------------------------------------------- /not.inc: -------------------------------------------------------------------------------- 1 | inv.inc -------------------------------------------------------------------------------- /fig/.gitignore: -------------------------------------------------------------------------------- 1 | *.pdf 2 | *.ps 3 | -------------------------------------------------------------------------------- /.spiceinit: -------------------------------------------------------------------------------- 1 | * Compatibility with HSPICE 2 | set ngbehavior=hs 3 | -------------------------------------------------------------------------------- /.gitattributes: -------------------------------------------------------------------------------- 1 | *.cir linguist-language=SPICE 2 | *.inc linguist-language=SPICE 3 | 4 | FreePDK45/**/* linguist-vendored 5 | -------------------------------------------------------------------------------- /report/NGSPICE_CMOS_Report.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Teddy-van-Jerry/ngspice-cmos/HEAD/report/NGSPICE_CMOS_Report.pdf -------------------------------------------------------------------------------- /pages/LIC.md: -------------------------------------------------------------------------------- 1 | --- 2 | title: LICENSE 3 | permalink: /LICENSE 4 | redirect_to: https://github.com/Teddy-van-Jerry/ngspice-cmos/blob/master/LICENSE 5 | --- 6 | -------------------------------------------------------------------------------- /pages/inv_cir.md: -------------------------------------------------------------------------------- 1 | --- 2 | title: inv.cir 3 | permalink: /inv.cir 4 | redirect_to: https://github.com/Teddy-van-Jerry/ngspice-cmos/blob/master/inv.cir 5 | --- 6 | -------------------------------------------------------------------------------- /pages/inv_inc.md: -------------------------------------------------------------------------------- 1 | --- 2 | title: inv.inc 3 | permalink: /inv.inc 4 | redirect_to: https://github.com/Teddy-van-Jerry/ngspice-cmos/blob/master/inv.inc 5 | --- 6 | -------------------------------------------------------------------------------- /pages/nand2_cir.md: -------------------------------------------------------------------------------- 1 | --- 2 | title: nand2.cir 3 | permalink: /nand2.cir 4 | redirect_to: https://github.com/Teddy-van-Jerry/ngspice-cmos/blob/master/nand2.cir 5 | --- 6 | -------------------------------------------------------------------------------- /pages/nand2_inc.md: -------------------------------------------------------------------------------- 1 | --- 2 | title: nand2.inc 3 | permalink: /nand2.inc 4 | redirect_to: https://github.com/Teddy-van-Jerry/ngspice-cmos/blob/master/nand2.inc 5 | --- 6 | -------------------------------------------------------------------------------- /pages/spiceinit.md: -------------------------------------------------------------------------------- 1 | --- 2 | title: .spiceinit 3 | permalink: /.spiceinit 4 | redirect_to: https://github.com/Teddy-van-Jerry/ngspice-cmos/blob/master/.spiceinit 5 | --- 6 | -------------------------------------------------------------------------------- /pages/FreePDK45_README.md: -------------------------------------------------------------------------------- 1 | --- 2 | title: FreePDK45 README 3 | permalink: FreePDK45/README 4 | redirect_to: https://github.com/Teddy-van-Jerry/ngspice-cmos/blob/master/FreePDK45/README 5 | --- 6 | -------------------------------------------------------------------------------- /_config.yml: -------------------------------------------------------------------------------- 1 | title: NGSPICE CMOS 2 | author: Wuqiong Zhao 3 | 4 | markdown: kramdown 5 | kramdown: 6 | input: GFM 7 | 8 | plugins: 9 | - jekyll-redirect-from 10 | whitelist: 11 | - jekyll-redirect-from 12 | 13 | exclude: 14 | - FreePDK45 15 | - LICENSE 16 | - "*.cir" 17 | - "*.inc" 18 | - "*.tex" 19 | - .spiceinit 20 | - .github 21 | - .gitignore 22 | - .gitattributes 23 | - .vscode 24 | -------------------------------------------------------------------------------- /fig/schematic.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | if [ -e "inv.tex" ]; then 4 | prefix="" 5 | else 6 | prefix="fig/" 7 | fi 8 | 9 | for cir in and8a and8b and8c inv nand2 nand4 nand8 nor2 SR_latch_clk; do 10 | latexmk -pdf -cd ${prefix}${cir}_schematic.tex 11 | pdf2svg ${prefix}${cir}_schematic.pdf ${prefix}${cir}_schematic.svg 12 | latexmk -pdf -cd -C ${prefix}${cir}_schematic.tex 13 | done 14 | 15 | echo "Finished generating all schematic SVGs!" 16 | -------------------------------------------------------------------------------- /fig/inv_schematic.tex: -------------------------------------------------------------------------------- 1 | \documentclass{standalone} 2 | \usepackage{tikz} 3 | \usepackage{siunitx} 4 | \usepackage{newtxtext,newtxmath} 5 | \usepackage{circuitikz} 6 | \usetikzlibrary{calc, positioning} 7 | \ctikzset{ 8 | , bipoles/capacitor/width=.1 9 | , bipoles/capacitor/height=.3 10 | , label/align = straight 11 | , tripoles/pmos style/emptycircle 12 | } 13 | 14 | \begin{document} 15 | \pagecolor{white} 16 | \input{inv} 17 | \end{document} 18 | -------------------------------------------------------------------------------- /fig/nor2_schematic.tex: -------------------------------------------------------------------------------- 1 | \documentclass{standalone} 2 | \usepackage{tikz} 3 | \usepackage{siunitx} 4 | \usepackage{newtxtext,newtxmath} 5 | \usepackage{circuitikz} 6 | \usetikzlibrary{calc, positioning} 7 | \ctikzset{ 8 | , bipoles/capacitor/width=.1 9 | , bipoles/capacitor/height=.3 10 | , label/align = straight 11 | , tripoles/pmos style/emptycircle 12 | } 13 | 14 | \begin{document} 15 | \pagecolor{white} 16 | \input{nor2} 17 | \end{document} 18 | -------------------------------------------------------------------------------- /fig/nand2_schematic.tex: -------------------------------------------------------------------------------- 1 | \documentclass{standalone} 2 | \usepackage{tikz} 3 | \usepackage{siunitx} 4 | \usepackage{newtxtext,newtxmath} 5 | \usepackage{circuitikz} 6 | \usetikzlibrary{calc, positioning} 7 | \ctikzset{ 8 | , bipoles/capacitor/width=.1 9 | , bipoles/capacitor/height=.3 10 | , label/align = straight 11 | , tripoles/pmos style/emptycircle 12 | } 13 | 14 | \begin{document} 15 | \pagecolor{white} 16 | \input{nand2} 17 | \end{document} 18 | -------------------------------------------------------------------------------- /fig/nand4_schematic.tex: -------------------------------------------------------------------------------- 1 | \documentclass{standalone} 2 | \usepackage{tikz} 3 | \usepackage{siunitx} 4 | \usepackage{newtxtext,newtxmath} 5 | \usepackage{circuitikz} 6 | \usetikzlibrary{calc, positioning} 7 | \ctikzset{ 8 | , bipoles/capacitor/width=.1 9 | , bipoles/capacitor/height=.3 10 | , label/align = straight 11 | , tripoles/pmos style/emptycircle 12 | } 13 | 14 | \begin{document} 15 | \pagecolor{white} 16 | \input{nand4} 17 | \end{document} 18 | -------------------------------------------------------------------------------- /fig/nand8_schematic.tex: -------------------------------------------------------------------------------- 1 | \documentclass{standalone} 2 | \usepackage{tikz} 3 | \usepackage{siunitx} 4 | \usepackage{newtxtext,newtxmath} 5 | \usepackage{circuitikz} 6 | \usetikzlibrary{calc, positioning} 7 | \ctikzset{ 8 | , bipoles/capacitor/width=.1 9 | , bipoles/capacitor/height=.3 10 | , label/align = straight 11 | , tripoles/pmos style/emptycircle 12 | } 13 | 14 | \begin{document} 15 | \pagecolor{white} 16 | \input{nand8} 17 | \end{document} 18 | -------------------------------------------------------------------------------- /FreePDK45/ff.inc: -------------------------------------------------------------------------------- 1 | * SPICE FF 2 | * fast-fast corner (fastest operating corner) 3 | 4 | .inc ./tran_models/models_ff/NMOS_VTG.inc 5 | .inc ./tran_models/models_ff/PMOS_VTG.inc 6 | 7 | .inc ./tran_models/models_ff/NMOS_VTL.inc 8 | .inc ./tran_models/models_ff/PMOS_VTL.inc 9 | 10 | .inc ./tran_models/models_ff/NMOS_VTH.inc 11 | .inc ./tran_models/models_ff/PMOS_VTH.inc 12 | 13 | .inc ./tran_models/models_ff/NMOS_THKOX.inc 14 | .inc ./tran_models/models_ff/PMOS_THKOX.inc 15 | -------------------------------------------------------------------------------- /FreePDK45/ss.inc: -------------------------------------------------------------------------------- 1 | * SPICE SS 2 | * slow-slow corner (slowest operating corner) 3 | 4 | .inc ./tran_models/models_ss/NMOS_VTG.inc 5 | .inc ./tran_models/models_ss/PMOS_VTG.inc 6 | 7 | .inc ./tran_models/models_ss/NMOS_VTL.inc 8 | .inc ./tran_models/models_ss/PMOS_VTL.inc 9 | 10 | .inc ./tran_models/models_ss/NMOS_VTH.inc 11 | .inc ./tran_models/models_ss/PMOS_VTH.inc 12 | 13 | .inc ./tran_models/models_ss/NMOS_THKOX.inc 14 | .inc ./tran_models/models_ss/PMOS_THKOX.inc 15 | -------------------------------------------------------------------------------- /fig/SR_latch_clk_schematic.tex: -------------------------------------------------------------------------------- 1 | \documentclass{standalone} 2 | \usepackage{tikz} 3 | \usepackage{siunitx} 4 | \usepackage{newtxtext,newtxmath} 5 | \usepackage{circuitikz} 6 | \usetikzlibrary{calc, positioning} 7 | \ctikzset{ 8 | , bipoles/capacitor/width=.1 9 | , bipoles/capacitor/height=.3 10 | , label/align = straight 11 | , tripoles/pmos style/emptycircle 12 | } 13 | 14 | \begin{document} 15 | \pagecolor{white} 16 | \input{SR_latch_clk} 17 | \end{document} 18 | -------------------------------------------------------------------------------- /fig/and8a_schematic.tex: -------------------------------------------------------------------------------- 1 | \documentclass{standalone} 2 | \usepackage{tikz} 3 | \usepackage{siunitx} 4 | \usepackage{newtxtext,newtxmath} 5 | \usepackage{circuitikz} 6 | \usetikzlibrary{calc, positioning} 7 | \ctikzset{ 8 | , bipoles/capacitor/width=.1 9 | , bipoles/capacitor/height=.3 10 | , label/align = straight 11 | , tripoles/pmos style/emptycircle 12 | , logic ports=ieee 13 | } 14 | 15 | \begin{document} 16 | \pagecolor{white} 17 | \input{and8a} 18 | \end{document} 19 | -------------------------------------------------------------------------------- /fig/and8b_schematic.tex: -------------------------------------------------------------------------------- 1 | \documentclass{standalone} 2 | \usepackage{tikz} 3 | \usepackage{siunitx} 4 | \usepackage{newtxtext,newtxmath} 5 | \usepackage{circuitikz} 6 | \usetikzlibrary{calc, positioning} 7 | \ctikzset{ 8 | , bipoles/capacitor/width=.1 9 | , bipoles/capacitor/height=.3 10 | , label/align = straight 11 | , tripoles/pmos style/emptycircle 12 | , logic ports=ieee 13 | } 14 | 15 | \begin{document} 16 | \pagecolor{white} 17 | \input{and8b} 18 | \end{document} 19 | -------------------------------------------------------------------------------- /fig/and8c_schematic.tex: -------------------------------------------------------------------------------- 1 | \documentclass{standalone} 2 | \usepackage{tikz} 3 | \usepackage{siunitx} 4 | \usepackage{newtxtext,newtxmath} 5 | \usepackage{circuitikz} 6 | \usetikzlibrary{calc, positioning} 7 | \ctikzset{ 8 | , bipoles/capacitor/width=.1 9 | , bipoles/capacitor/height=.3 10 | , label/align = straight 11 | , tripoles/pmos style/emptycircle 12 | , logic ports=ieee 13 | } 14 | 15 | \begin{document} 16 | \pagecolor{white} 17 | \input{and8c} 18 | \end{document} 19 | -------------------------------------------------------------------------------- /FreePDK45/nom.inc: -------------------------------------------------------------------------------- 1 | * SPICE NOM 2 | * nominal operating corner (average operating corner) 3 | 4 | .inc ./tran_models/models_nom/NMOS_VTG.inc 5 | .inc ./tran_models/models_nom/PMOS_VTG.inc 6 | 7 | .inc ./tran_models/models_nom/NMOS_VTL.inc 8 | .inc ./tran_models/models_nom/PMOS_VTL.inc 9 | 10 | .inc ./tran_models/models_nom/NMOS_VTH.inc 11 | .inc ./tran_models/models_nom/PMOS_VTH.inc 12 | 13 | .inc ./tran_models/models_nom/NMOS_THKOX.inc 14 | .inc ./tran_models/models_nom/PMOS_THKOX.inc 15 | -------------------------------------------------------------------------------- /fig/and8a.tex: -------------------------------------------------------------------------------- 1 | \begin{circuitikz}[ 2 | , null n/.style = { 3 | , inner sep = 0 4 | , outer sep = 0 5 | , minimum size = 0 6 | } 7 | , la/.style = { 8 | , font = \sffamily 9 | } 10 | , P/.style = { 11 | , pmos 12 | , font = \footnotesize 13 | } 14 | , N/.style = { 15 | , nmos 16 | , font = \footnotesize 17 | } 18 | ] 19 | \draw 20 | (0, 0) node[nand port, number inputs=8] (nand) {} 21 | (2, 0) node[not port] (inv) {} 22 | (nand.out) -- (inv.in) 23 | ; 24 | \end{circuitikz}% 25 | -------------------------------------------------------------------------------- /report/ref.bib: -------------------------------------------------------------------------------- 1 | @misc{ngspice, 2 | author = {Vogt, Holger and Giles, Atkinson and Nenzi, Paolo and Warning, Dietmar}, 3 | title = {{NGSPICE} 40 --- Open source spice simulator}, 4 | year = {2023}, 5 | url = {https://ngspice.sourceforge.io/} 6 | } 7 | 8 | @manual{manual, 9 | author = {Vogt, Holger and Giles, Atkinson and Nenzi, Paolo and Warning, Dietmar}, 10 | title = {Ngspice User’s Manual Version 40 (ngspice release version)}, 11 | year = {2023}, 12 | month = apr, 13 | url = {https://ngspice.sourceforge.io/docs/ngspice-40-manual.pdf} 14 | } 15 | -------------------------------------------------------------------------------- /and8a.inc: -------------------------------------------------------------------------------- 1 | * ============================================================================= 2 | * Circuit : CMOS AND8 Gate Type A 3 | * Description: 8 PMOS + 8 NMOS (Symmetrical Design) + 1 Inv 4 | * 5 | * Author : Wuqiong Zhao (me@wqzhao.org) 6 | * Date : 2023-06-02 7 | * License : MIT 8 | * ============================================================================= 9 | 10 | .subckt AND8A gnd i1 i2 i3 i4 i5 i6 i7 i8 o vdd 11 | XNAND8a gnd i1 i2 i3 i4 i5 i6 i7 i8 o_inv vdd NAND8A 12 | Xinv gnd o_inv o vdd INV 13 | .ends AND8A 14 | 15 | .inc ./nand8a.inc 16 | .inc ./inv.inc 17 | -------------------------------------------------------------------------------- /and4b.inc: -------------------------------------------------------------------------------- 1 | * ============================================================================= 2 | * Circuit : CMOS AND4 Gate Type B 3 | * Description: NAND2 * 2 + NOR * 1 4 | * 5 | * Author : Wuqiong Zhao (me@wqzhao.org) 6 | * Date : 2023-06-02 7 | * License : MIT 8 | * ============================================================================= 9 | 10 | .subckt AND4B gnd i1 i2 i3 i4 o vdd 11 | * src gate drain body type 12 | XNAND2_1 gnd i1 i2 t1 vdd NAND2 13 | XNAND2_2 gnd i3 i4 t2 vdd NAND2 14 | XNOR gnd t1 t2 o vdd NOR2 15 | .ends AND4B 16 | 17 | .inc ./nand2.inc 18 | .inc ./nor2.inc 19 | -------------------------------------------------------------------------------- /fig/and8b.tex: -------------------------------------------------------------------------------- 1 | \begin{circuitikz}[ 2 | , null n/.style = { 3 | , inner sep = 0 4 | , outer sep = 0 5 | , minimum size = 0 6 | } 7 | , la/.style = { 8 | , font = \sffamily 9 | } 10 | , P/.style = { 11 | , pmos 12 | , font = \footnotesize 13 | } 14 | , N/.style = { 15 | , nmos 16 | , font = \footnotesize 17 | } 18 | ] 19 | \draw 20 | (0, 1) node[nand port, number inputs=4] (nand1) {} 21 | (0, -1) node[nand port, number inputs=4] (nand2) {} 22 | (2.5, 0) node[nor port] (nor) {} 23 | (nand1.out) -| (nor.in 1) 24 | (nand2.out) -| (nor.in 2) 25 | ; 26 | \end{circuitikz}% 27 | -------------------------------------------------------------------------------- /and2.inc: -------------------------------------------------------------------------------- 1 | * ============================================================================= 2 | * Circuit : CMOS AND2 Gate 3 | * Description: NMOS2 + Inverter (3 PMOS + 3 NMOS) 4 | * 5 | * Author : Wuqiong Zhao (me@wqzhao.org) 6 | * Date : 2023-06-02 7 | * License : MIT 8 | * ============================================================================= 9 | 10 | .subckt AND2 gnd i1 i2 o vdd 11 | XNAND gnd i1 i2 o1 vdd NAND2 12 | XInv gnd o1 o vdd INV 13 | .ends AND2 14 | 15 | .subckt AND gnd i1 i2 o vdd 16 | XNAND gnd i1 i2 o1 vdd NAND2 17 | XInv gnd o1 o vdd INV 18 | .ends AND 19 | 20 | .inc ./nand2.inc 21 | .inc ./inv.inc 22 | -------------------------------------------------------------------------------- /and8b.inc: -------------------------------------------------------------------------------- 1 | * ============================================================================= 2 | * Circuit : CMOS AND8 Gate Type B 3 | * Description: NAND4A * 2 + NOR2 * 1 4 | * 5 | * Author : Wuqiong Zhao (me@wqzhao.org) 6 | * Date : 2023-06-02 7 | * License : MIT 8 | * ============================================================================= 9 | 10 | .subckt AND8B gnd i1 i2 i3 i4 i5 i6 i7 i8 o vdd 11 | * src gate drain body type 12 | XNAND4A_1 gnd i1 i2 i3 i4 t1 vdd NAND4A 13 | XNAND4A_2 gnd i5 i6 i7 i8 t2 vdd NAND4A 14 | XNOR2 gnd t1 t2 o vdd NOR2 15 | .ends AND8B 16 | 17 | .inc ./nand4a.inc 18 | .inc ./nor2.inc 19 | -------------------------------------------------------------------------------- /.vscode/settings.json: -------------------------------------------------------------------------------- 1 | { 2 | "files.associations": { 3 | "*.cir": "spice", 4 | "*.inc": "spice" 5 | }, 6 | "cSpell.words": [ 7 | "NGSPICE", 8 | "VLSI" 9 | ], 10 | "latex-workshop.latex.tools": [ 11 | { 12 | "name": "latexmk", 13 | "command": "latexmk", 14 | "args": [ 15 | "-shell-escape", 16 | "-synctex=1", 17 | "-interaction=nonstopmode", 18 | "-file-line-error", 19 | "-pdf", 20 | "-outdir=%OUTDIR%", 21 | "%DOC%" 22 | ], 23 | "env": {} 24 | }, 25 | ] 26 | } -------------------------------------------------------------------------------- /inv.inc: -------------------------------------------------------------------------------- 1 | * ============================================================================= 2 | * Circuit : CMOS Inverter 3 | * Description: 1 PMOS + 1 NMOS 4 | * 5 | * Author : Wuqiong Zhao (me@wqzhao.org) 6 | * Date : 2023-06-02 7 | * License : MIT 8 | * ============================================================================= 9 | 10 | .subckt INV gnd i o vdd 11 | * src gate drain body type 12 | M1 vdd i o vdd PMOS_VTL W=360nm L=45nm 13 | M2 gnd i o gnd NMOS_VTL W=225nm L=45nm 14 | .ends INV 15 | 16 | .subckt NOT gnd i o vdd 17 | * src gate drain body type 18 | M1 vdd i o vdd PMOS_VTL W=360nm L=45nm 19 | M2 gnd i o gnd NMOS_VTL W=225nm L=45nm 20 | .ends NOT 21 | -------------------------------------------------------------------------------- /nand4a.inc: -------------------------------------------------------------------------------- 1 | * ============================================================================= 2 | * Circuit : CMOS NAND4 Gate Type 3 | * Description: 4 PMOS + 4 NMOS (Symmetrical Design) 4 | * 5 | * Author : Wuqiong Zhao (me@wqzhao.org) 6 | * Date : 2023-06-02 7 | * License : MIT 8 | * ============================================================================= 9 | 10 | .subckt NAND4A gnd i1 i2 i3 i4 o vdd 11 | * src gate drain body type 12 | Mp1 vdd i1 o vdd PMOS_VTL W=360nm L=45nm 13 | Mp2 vdd i2 o vdd PMOS_VTL W=360nm L=45nm 14 | Mp3 vdd i3 o vdd PMOS_VTL W=360nm L=45nm 15 | Mp4 vdd i4 o vdd PMOS_VTL W=360nm L=45nm 16 | Mn1 t1 i1 o gnd NMOS_VTL W=900nm L=45nm 17 | Mn2 t2 i2 t1 gnd NMOS_VTL W=900nm L=45nm 18 | Mn3 t3 i3 t2 gnd NMOS_VTL W=900nm L=45nm 19 | Mn4 gnd i4 t3 gnd NMOS_VTL W=900nm L=45nm 20 | .ends NAND4A 21 | -------------------------------------------------------------------------------- /and8c.inc: -------------------------------------------------------------------------------- 1 | * ============================================================================= 2 | * Circuit : CMOS AND8 Gate Type C 3 | * Description: AND4B * 2 + AND2 * 1 4 | * 5 | * Author : Wuqiong Zhao (me@wqzhao.org) 6 | * Date : 2023-06-02 7 | * License : MIT 8 | * ============================================================================= 9 | 10 | * The following warning may be raised: 11 | * 12 | * Warning: redefinition of .subckt nand2, ignored 13 | * Warning: redefinition of .subckt nand, ignored 14 | * 15 | * This is due to recursive .inc commands load the same .subckt. 16 | * You can safely ignore these 2 warnings. 17 | 18 | .subckt AND8C gnd i1 i2 i3 i4 i5 i6 i7 i8 o vdd 19 | * src gate drain body type 20 | XAND4B_1 gnd i1 i2 i3 i4 t1 vdd AND4B 21 | XAND4B_2 gnd i5 i6 i7 i8 t2 vdd AND4B 22 | XAND2 gnd t1 t2 o vdd AND2 23 | .ends AND8C 24 | 25 | .inc ./and4b.inc 26 | .inc ./and2.inc 27 | -------------------------------------------------------------------------------- /fig/inv.tex: -------------------------------------------------------------------------------- 1 | \begin{circuitikz}[ 2 | , null n/.style = { 3 | , inner sep = 0 4 | , outer sep = 0 5 | , minimum size = 0 6 | } 7 | , la/.style = { 8 | , font = \sffamily 9 | } 10 | ] 11 | \draw 12 | (0, 1) node (M1) [pmos] {$M_1$} 13 | (0, -1) node (M2) [nmos] {$M_2$} 14 | (M1.G) to[short, -*] ++ (0, -1) node [null n] (in-branch) {} 15 | (in-branch) to[short, -o] ++ (-1, 0) node [left, la, mark=*] {in} 16 | (in-branch) to[short] ++ (0, -1) (M2.G) 17 | (M1.S) to[short] ++ (0, 0) node [vdd] {$V_{DD}=\qty{1}{V}$} 18 | (M2.S) to ++ (0, 0) node [tlground] {} 19 | ($(M1.D)!0.5!(M2.D)$) node [null n] (out-branch) {} 20 | (M1.D) to (M2.D) 21 | (out-branch) to[short, *-*] ++ (1, 0) node [right, null n] (L) {} 22 | (L) to[short, -o] ++ (0.5, 0) node [right, la] {out} 23 | (L) to[short, C, l={$C_L=\qty{24}{fF}$}] ++ (0, -1) node [tlground] {} 24 | ; 25 | \end{circuitikz}% 26 | -------------------------------------------------------------------------------- /and8_test_pow.inc: -------------------------------------------------------------------------------- 1 | * ============================================================================= 2 | * Script : Measure AND8 Gate Static and Dynamic Power 3 | * Description: Measure the power for device 'xand8'. 4 | * 5 | * Author : Wuqiong Zhao (me@wqzhao.org) 6 | * Date : 2023-06-02 7 | * License : MIT 8 | * ============================================================================= 9 | 10 | .probe P(XAND8) 11 | .control 12 | * Total power 13 | let p_total = mean(xand8:power) 14 | * Static power (average of high and low) 15 | let p_static = 16 | + ( 17 | + mean(xand8:power[length(xand8:power) / 6, length(xand8:power) / 3]) + 18 | + mean(xand8:power[length(xand8:power) / 2, length(xand8:power) / 1.5]) 19 | + ) / 2 20 | * Dynamic power (difference of total power and static power) 21 | let p_dynamic = p_total - p_static 22 | print p_total 23 | print p_static 24 | print p_dynamic 25 | .endc 26 | -------------------------------------------------------------------------------- /SR_latch_clk.inc: -------------------------------------------------------------------------------- 1 | * ============================================================================= 2 | * Circuit : Clock Controlled SR Latch 3 | * Description: 2 PMOS + 6 NMOS 4 | * 5 | * Author : Wuqiong Zhao (me@wqzhao.org) 6 | * Date : 2023-06-03 7 | * License : MIT 8 | * ============================================================================= 9 | 10 | * .param WL = 5 11 | .subckt SR_LATCH_CLK gnd s r clk q qn vdd 12 | * src gate drain body type 13 | M1 qn q gnd gnd NMOS_VTL W= 90nm L=45nm 14 | M2 qn q vdd vdd PMOS_VTL W= 270nm L=45nm 15 | M3 q qn gnd gnd NMOS_VTL W= 90nm L=45nm 16 | M4 q qn vdd vdd PMOS_VTL W= 270nm L=45nm 17 | M5 ts s gnd gnd NMOS_VTL W={WL*45nm} L=45nm 18 | M6 qn clk ts gnd NMOS_VTL W={WL*45nm} L=45nm 19 | M7 tr r gnd gnd NMOS_VTL W={WL*45nm} L=45nm 20 | M8 q clk tr gnd NMOS_VTL W={WL*45nm} L=45nm 21 | .ends SR_LATCH_CLK 22 | -------------------------------------------------------------------------------- /nor2.inc: -------------------------------------------------------------------------------- 1 | * ============================================================================= 2 | * Circuit : CMOS NOR2 Gate 3 | * Description: 2 PMOS + 2 NMOS 4 | * 5 | * Author : Wuqiong Zhao (me@wqzhao.org) 6 | * Date : 2023-06-01 7 | * License : MIT 8 | * ============================================================================= 9 | 10 | .subckt NOR2 gnd i1 i2 o vdd 11 | * src gate drain body type 12 | Mp1 t1 i1 o vdd PMOS_VTL W=720nm L=45nm 13 | Mp2 vdd i2 t1 vdd PMOS_VTL W=720nm L=45nm 14 | Mn1 gnd i1 o gnd NMOS_VTL W=225nm L=45nm 15 | Mn2 gnd i2 o gnd NMOS_VTL W=225nm L=45nm 16 | .ends NOR2 17 | 18 | .subckt NOR gnd i1 i2 o vdd 19 | * src gate drain body type 20 | Mp1 t1 i1 o vdd PMOS_VTL W=720nm L=45nm 21 | Mp2 vdd i2 t1 vdd PMOS_VTL W=720nm L=45nm 22 | Mn1 gnd i1 o gnd NMOS_VTL W=225nm L=45nm 23 | Mn2 gnd i2 o gnd NMOS_VTL W=225nm L=45nm 24 | .ends NOR 25 | -------------------------------------------------------------------------------- /nand2.inc: -------------------------------------------------------------------------------- 1 | * ============================================================================= 2 | * Circuit : CMOS NAND2 Gate 3 | * Description: 2 PMOS + 2 NMOS 4 | * 5 | * Author : Wuqiong Zhao (me@wqzhao.org) 6 | * Date : 2023-06-01 7 | * License : MIT 8 | * ============================================================================= 9 | 10 | .subckt NAND2 gnd i1 i2 o vdd 11 | * src gate drain body type 12 | Mp1 vdd i1 o vdd PMOS_VTL W=360nm L=45nm 13 | Mp2 vdd i2 o vdd PMOS_VTL W=360nm L=45nm 14 | Mn1 t1 i1 o gnd NMOS_VTL W=450nm L=45nm 15 | Mn2 gnd i2 t1 gnd NMOS_VTL W=450nm L=45nm 16 | .ends NAND2 17 | 18 | .subckt NAND gnd i1 i2 o vdd 19 | * src gate drain body type 20 | Mp1 vdd i1 o vdd PMOS_VTL W=360nm L=45nm 21 | Mp2 vdd i2 o vdd PMOS_VTL W=360nm L=45nm 22 | Mn1 t1 i1 o gnd NMOS_VTL W=450nm L=45nm 23 | Mn2 gnd i2 t1 gnd NMOS_VTL W=450nm L=45nm 24 | .ends NAND 25 | -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | MIT License 2 | 3 | Copyright (c) 2023 Wuqiong Zhao (Teddy van Jerry) 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in all 13 | copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 | SOFTWARE. 22 | -------------------------------------------------------------------------------- /fig/nand2.tex: -------------------------------------------------------------------------------- 1 | \begin{circuitikz}[ 2 | , null n/.style = { 3 | , inner sep = 0 4 | , outer sep = 0 5 | , minimum size = 0 6 | } 7 | , la/.style = { 8 | , font = \sffamily 9 | } 10 | , P/.style = { 11 | , pmos 12 | , font = \footnotesize 13 | } 14 | , N/.style = { 15 | , nmos 16 | , font = \footnotesize 17 | } 18 | ] 19 | \draw 20 | (-1, 1) node (Mp1) [P] {\hspace{-1em}8} 21 | (1, 1) node (Mp2) [P] {\hspace{-1em}8} 22 | ([xshift = -7pt]Mp1.S) -- ([xshift=7pt]Mp2.S) node [midway, above] {$V_{DD}$} 23 | (Mp1.D) -- (Mp2.D) 24 | (0, -1) node (Mn1) [N] {\hspace{-1em}10} 25 | (0, -2.5) node (Mn2) [N] {\hspace{-1em}10} 26 | % (Mn1.S) -- (Mn2.D) 27 | (Mn1.D) to[short, -*] (Mp1.D -| Mn1.D) 28 | (Mn1.D) to[short, *-o] ++ (0.5, 0) node [right, la, mark=*] {out} 29 | (Mn2.S) ++ (0, 0) node [tlground] {} 30 | (Mp1.G) to[short, -o] ++ (-0, 0) node [left, la, mark=*] {in1} 31 | (Mp2.G) to[short, -o] ++ (-0, 0) node [left, la, mark=*] {in2} 32 | (Mn1.G) to[short, -o] ++ (-0, 0) node [left, la, mark=*] {in1} 33 | (Mn2.G) to[short, -o] ++ (-0, 0) node [left, la, mark=*] {in2} 34 | ; 35 | \end{circuitikz}% 36 | -------------------------------------------------------------------------------- /fig/nor2.tex: -------------------------------------------------------------------------------- 1 | \begin{circuitikz}[ 2 | , null n/.style = { 3 | , inner sep = 0 4 | , outer sep = 0 5 | , minimum size = 0 6 | } 7 | , la/.style = { 8 | , font = \sffamily 9 | } 10 | , P/.style = { 11 | , pmos 12 | , font = \footnotesize 13 | } 14 | , N/.style = { 15 | , nmos 16 | , font = \footnotesize 17 | } 18 | ] 19 | \draw 20 | (0, 1) node (Mp1) [P] {\hspace{-1em}16} 21 | (0, 2.5) node (Mp2) [P] {\hspace{-1em}16} 22 | (-1, -1) node (Mn1) [N] {\hspace{-1em}5} 23 | (1, -1) node (Mn2) [N] {\hspace{-1em}5} 24 | % (1.4, -1) node [null n] {} % to make sure the above 10 is not cropped 25 | ([xshift = -7pt]Mn1.S) -- ([xshift=7pt]Mn2.S) node [midway, ground] {} 26 | (Mn1.D) -- (Mn2.D) 27 | (Mp1.D) to[short, -*] (Mn1.D -| Mp1.D) 28 | (Mp1.D) to[short, *-o] ++ (0.5, 0) node [right, la, mark=*] {out} 29 | (Mp2.S) to[short] ++ (0, 0) node [vdd] {$V_{DD}$} 30 | (Mp1.G) to[short, -o] ++ (-0, 0) node [left, la, mark=*] {in1} 31 | (Mp2.G) to[short, -o] ++ (-0, 0) node [left, la, mark=*] {in2} 32 | (Mn1.G) to[short, -o] ++ (-0, 0) node [left, la, mark=*] {in1} 33 | (Mn2.G) to[short, -o] ++ (-0, 0) node [left, la, mark=*] {in2} 34 | ; 35 | \end{circuitikz}% 36 | -------------------------------------------------------------------------------- /and8_test_inv2.inc: -------------------------------------------------------------------------------- 1 | * ============================================================================= 2 | * Circuit : Test Circuit With Capicitor Load 3 | * Description: 2 Inverters at the Input 4 | * 5 | * Author : Wuqiong Zhao (me@wqzhao.org) 6 | * Date : 2023-06-02 7 | * License : MIT 8 | * ============================================================================= 9 | 10 | .subckt INV2_TEST gnd 11 | + i1 i2 i3 i4 i5 i6 i7 i8 12 | + t1 t2 t3 t4 t5 t6 t7 t8 13 | + out vdd 14 | * gnd i o vdd 15 | XInv_ss1 gnd i1 t1 vdd INV_SS 16 | XInv_ss2 gnd i2 t2 vdd INV_SS 17 | XInv_ss3 gnd i3 t3 vdd INV_SS 18 | XInv_ss4 gnd i4 t4 vdd INV_SS 19 | XInv_ss5 gnd i5 t5 vdd INV_SS 20 | XInv_ss6 gnd i6 t6 vdd INV_SS 21 | XInv_ss7 gnd i7 t7 vdd INV_SS 22 | XInv_ss8 gnd i8 t8 vdd INV_SS 23 | * Load 24 | CL out gnd 24fF 25 | .ends INV2_TEST 26 | 27 | .subckt INV_SS gnd i o vdd 28 | XInv_s1 gnd i t vdd INV_S 29 | XInv_s2 gnd t o vdd INV_S 30 | .ends 31 | 32 | * Inverter used in the test circuit 33 | .subckt INV_S gnd i o vdd 34 | * src gate drain body type 35 | M1 vdd i o vdd PMOS_VTL W=0.75um L=0.25um 36 | M2 gnd i o gnd NMOS_VTL W=2.60um L=0.25um 37 | .ends INV_S 38 | -------------------------------------------------------------------------------- /nand8a.inc: -------------------------------------------------------------------------------- 1 | * ============================================================================= 2 | * Circuit : CMOS NAND8 Gate Type A 3 | * Description: 8 PMOS + 8 NMOS (Symmetrical Design) 4 | * 5 | * Author : Wuqiong Zhao (me@wqzhao.org) 6 | * Date : 2023-06-02 7 | * License : MIT 8 | * ============================================================================= 9 | 10 | .subckt NAND8A gnd i1 i2 i3 i4 i5 i6 i7 i8 o vdd 11 | * src gate drain body type 12 | Mp1 vdd i1 o vdd PMOS_VTL W=360nm L=45nm 13 | Mp2 vdd i2 o vdd PMOS_VTL W=360nm L=45nm 14 | Mp3 vdd i3 o vdd PMOS_VTL W=360nm L=45nm 15 | Mp4 vdd i4 o vdd PMOS_VTL W=360nm L=45nm 16 | Mp5 vdd i5 o vdd PMOS_VTL W=360nm L=45nm 17 | Mp6 vdd i6 o vdd PMOS_VTL W=360nm L=45nm 18 | Mp7 vdd i7 o vdd PMOS_VTL W=360nm L=45nm 19 | Mp8 vdd i8 o vdd PMOS_VTL W=360nm L=45nm 20 | Mn1 t1 i1 o gnd NMOS_VTL W=1.8um L=45nm 21 | Mn2 t2 i2 t1 gnd NMOS_VTL W=1.8um L=45nm 22 | Mn3 t3 i3 t2 gnd NMOS_VTL W=1.8um L=45nm 23 | Mn4 t4 i4 t3 gnd NMOS_VTL W=1.8um L=45nm 24 | Mn5 t5 i5 t4 gnd NMOS_VTL W=1.8um L=45nm 25 | Mn6 t6 i6 t5 gnd NMOS_VTL W=1.8um L=45nm 26 | Mn7 t7 i7 t6 gnd NMOS_VTL W=1.8um L=45nm 27 | Mn8 gnd i8 t7 gnd NMOS_VTL W=1.8um L=45nm 28 | .ends NAND8A 29 | -------------------------------------------------------------------------------- /FreePDK45/README: -------------------------------------------------------------------------------- 1 | This is part of FreePDK, modified by Wuqiong Zhao (me@wqzhao.org) for NGSPICE. 2 | 3 | =============================================================================== 4 | FreePDK 45nm verion 1.4 (2011-04-07) 5 | (Subversion Repository revision 173) 6 | 7 | Copyright 2007 - W. Rhett Davis, Paul Franzon, Michael Bucher, 8 | and Sunil Basavarajaiah, North Carolina State University 9 | Copyright 2008 - W. Rhett Davis, Michael Bucher, and Sunil Basavarajaiah, 10 | North Carolina State University (ncsu_basekit subtree) 11 | James Stine, and Ivan Castellanos, 12 | and Oklahoma State University (osu_soc subtree) 13 | Copyright 2011 - W. Rhett Davis, and Harun Demircioglu, 14 | North Carolina State University 15 | 16 | SVRF Technology in this kit is licensed under the the agreement found 17 | in the file SVRF_EULA_06Feb09.txt in this directory. All other files 18 | are licensed under the Apache License, Version 2.0 (the "License"); 19 | you may not use these files except in compliance with the License. 20 | You may obtain a copy of the License at 21 | 22 | http://www.apache.org/licenses/LICENSE-2.0 23 | 24 | Unless required by applicable law or agreed to in writing, software 25 | distributed under the License is distributed on an "AS IS" BASIS, 26 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 27 | See the License for the specific language governing permissions and 28 | limitations under the License. 29 | =============================================================================== 30 | -------------------------------------------------------------------------------- /fig/and8c.tex: -------------------------------------------------------------------------------- 1 | \begin{circuitikz}[ 2 | , null n/.style = { 3 | , inner sep = 0 4 | , outer sep = 0 5 | , minimum size = 0 6 | } 7 | , la/.style = { 8 | , font = \sffamily 9 | } 10 | , P/.style = { 11 | , pmos 12 | , font = \footnotesize 13 | } 14 | , N/.style = { 15 | , nmos 16 | , font = \footnotesize 17 | } 18 | ] 19 | \draw 20 | (0, 0) node[nand port, number inputs=2] (nand) {} 21 | (2, 0) node[not port] (inv) {} 22 | (-2.5, 2*0.8) node[nor port] (nor1) {} 23 | (-2.5, -2*0.8) node[nor port] (nor2) {} 24 | (-5, 3*0.8) node [nand port] (nand1) {} 25 | (-5, 1*0.8) node [nand port] (nand2) {} 26 | (-5, -1*0.8) node [nand port] (nand3) {} 27 | (-5, -3*0.8) node [nand port] (nand4) {} 28 | (nor1.out) -| (nand.in 1) 29 | (nor2.out) -| (nand.in 2) 30 | (nand1.out) -| (nor1.in 1) 31 | (nand2.out) -| (nor1.in 2) 32 | (nand3.out) -| (nor2.in 1) 33 | (nand4.out) -| (nor2.in 2) 34 | (nand.out) -- (inv.in) 35 | (inv.out) to[short, -o] ++ (0, 0) node [right, la] {out} 36 | (nand1.in 1) to[short, -o] ++ (-0, 0) node [left, la] {in1} 37 | (nand1.in 2) to[short, -o] ++ (-0, 0) node [left, la] {in2} 38 | (nand2.in 1) to[short, -o] ++ (-0, 0) node [left, la] {in3} 39 | (nand2.in 2) to[short, -o] ++ (-0, 0) node [left, la] {in4} 40 | (nand3.in 1) to[short, -o] ++ (-0, 0) node [left, la] {in5} 41 | (nand3.in 2) to[short, -o] ++ (-0, 0) node [left, la] {in6} 42 | (nand4.in 1) to[short, -o] ++ (-0, 0) node [left, la] {in7} 43 | (nand4.in 2) to[short, -o] ++ (-0, 0) node [left, la] {in8} 44 | ; 45 | \end{circuitikz}% 46 | -------------------------------------------------------------------------------- /fig/nand4.tex: -------------------------------------------------------------------------------- 1 | \begin{circuitikz}[ 2 | , null n/.style = { 3 | , inner sep = 0 4 | , outer sep = 0 5 | , minimum size = 0 6 | } 7 | , la/.style = { 8 | , font = \sffamily 9 | } 10 | , P/.style = { 11 | , pmos 12 | , font = \footnotesize 13 | } 14 | , N/.style = { 15 | , nmos 16 | , font = \footnotesize 17 | } 18 | ] 19 | \draw 20 | (-3, 1) node (Mp1) [P] {\hspace{-1em}8} 21 | (-1, 1) node (Mp2) [P] {\hspace{-1em}8} 22 | (1, 1) node (Mp3) [P] {\hspace{-1em}8} 23 | (3, 1) node (Mp4) [P] {\hspace{-1em}8} 24 | ([xshift = -7pt]Mp1.S) -- ([xshift=7pt]Mp4.S) node [midway, above] {$V_{DD}$} 25 | (Mp1.D) -- (Mp4.D) 26 | (0, -1) node (Mn1) [N] {\hspace{-1em}20} 27 | (0, -2.5) node (Mn2) [N] {\hspace{-1em}20} 28 | (0, -4) node (Mn3) [N] {\hspace{-1em}20} 29 | (0, -5.5) node (Mn4) [N] {\hspace{-1em}20} 30 | (Mn1.D) to[short, -*] (Mp1.D -| Mn1.D) 31 | (Mn1.D) to[short, *-o] ++ (0.5, 0) node [right, la, mark=*] {out} 32 | (Mn4.S) ++ (0, 0) node [tlground] {} 33 | (Mp1.G) to[short, -o] ++ (-0, 0) node [left, la, mark=*] {in1} 34 | (Mp2.G) to[short, -o] ++ (-0, 0) node [left, la, mark=*] {in2} 35 | (Mp3.G) to[short, -o] ++ (-0, 0) node [left, la, mark=*] {in3} 36 | (Mp4.G) to[short, -o] ++ (-0, 0) node [left, la, mark=*] {in4} 37 | (Mn1.G) to[short, -o] ++ (-0, 0) node [left, la, mark=*] {in1} 38 | (Mn2.G) to[short, -o] ++ (-0, 0) node [left, la, mark=*] {in2} 39 | (Mn3.G) to[short, -o] ++ (-0, 0) node [left, la, mark=*] {in3} 40 | (Mn4.G) to[short, -o] ++ (-0, 0) node [left, la, mark=*] {in4} 41 | ; 42 | \end{circuitikz}% 43 | -------------------------------------------------------------------------------- /.github/workflows/jekyll-gh-pages.yml: -------------------------------------------------------------------------------- 1 | # Sample workflow for building and deploying a Jekyll site to GitHub Pages 2 | name: Deploy Jekyll with GitHub Pages dependencies preinstalled 3 | 4 | on: 5 | # Runs on pushes targeting the default branch 6 | push: 7 | branches: ["master"] 8 | 9 | # Allows you to run this workflow manually from the Actions tab 10 | workflow_dispatch: 11 | 12 | # Sets permissions of the GITHUB_TOKEN to allow deployment to GitHub Pages 13 | permissions: 14 | contents: read 15 | pages: write 16 | id-token: write 17 | 18 | # Allow only one concurrent deployment, skipping runs queued between the run in-progress and latest queued. 19 | # However, do NOT cancel in-progress runs as we want to allow these production deployments to complete. 20 | concurrency: 21 | group: "pages" 22 | cancel-in-progress: false 23 | 24 | jobs: 25 | # Build job 26 | build: 27 | runs-on: ubuntu-latest 28 | steps: 29 | - name: Checkout 30 | uses: actions/checkout@v3 31 | - name: Install QPDF 32 | run: sudo apt-get -y install qpdf 33 | - name: Run QPDF 34 | run: qpdf report/NGSPICE_CMOS_Report.pdf --replace-input --linearize 35 | - name: Setup Pages 36 | uses: actions/configure-pages@v3 37 | - name: Build with Jekyll 38 | uses: actions/jekyll-build-pages@v1 39 | with: 40 | source: ./ 41 | destination: ./_site 42 | - name: Upload artifact 43 | uses: actions/upload-pages-artifact@v1 44 | 45 | # Deployment job 46 | deploy: 47 | environment: 48 | name: github-pages 49 | url: ${{ steps.deployment.outputs.page_url }} 50 | runs-on: ubuntu-latest 51 | needs: build 52 | steps: 53 | - name: Deploy to GitHub Pages 54 | id: deployment 55 | uses: actions/deploy-pages@v2 56 | -------------------------------------------------------------------------------- /fig/SR_latch_clk.tex: -------------------------------------------------------------------------------- 1 | \begin{circuitikz}[ 2 | , null n/.style = { 3 | , inner sep = 0 4 | , outer sep = 0 5 | , minimum size = 0 6 | } 7 | , la/.style = { 8 | , font = \sffamily 9 | } 10 | , P/.style = { 11 | , pmos 12 | } 13 | , N/.style = { 14 | , nmos 15 | } 16 | ] 17 | \draw 18 | (-1.2, -1) node (M1) [N, xscale=-1, label={[xshift=.5em]center:\footnotesize$M_1$}] {} 19 | (1.2, -1) node (M3) [N, label={[xshift=-.5em]center:\footnotesize$M_3$}] {} 20 | (-1.2, 1) node (M2) [P, xscale=-1, label={[xshift=.5em]center:\footnotesize$M_2$}] {} 21 | (1.2, 1) node (M4) [P, label={[xshift=-.5em]center:\footnotesize$M_4$}] {} 22 | (M1.G) -- (M2.G) 23 | (M3.G) -- (M4.G) 24 | (M1.D) -- (M2.D) 25 | (M3.D) -- (M4.D) 26 | (M1.D) to[short, *-*] (M1.D -| M3.G) 27 | (M4.D) to[short, *-*] (M4.D -| M2.G) 28 | (-1.7, -0.9) node (M6) [N, label={[xshift=-.2em]center:\footnotesize$M_6$}, scale=.7] {} 29 | (1.7, -0.9) node (M8) [N, label={[xshift=.2em]center:\footnotesize$M_8$}, scale=-.7] {} 30 | (-1.7, -1.8) node (M5) [N, label={[xshift=-.2em]center:\footnotesize$M_5$}, scale=.7] {} 31 | (1.7, -1.8) node (M7) [N, label={[xshift=.2em]center:\footnotesize$M_7$}, scale=-.7] {} 32 | ([xshift=-5mm]M5.S) -- ([xshift=5mm]M7.D) node [midway, ground] {} 33 | ([xshift=-5mm]M2.S) -- ([xshift=5mm]M4.S) node [midway, above] {$V_{DD}$} 34 | (M1.S) -- (M1.S |- M7.D) 35 | (M3.S) -- (M3.S |- M5.S) 36 | (M6.D) |- (M1.D) node [above left] {$\overline{Q}$} 37 | (M8.S) |- (M4.D) node [above right] {$Q$} 38 | (M6.G) to[short, -o] ++ (-0, 0) node [la, left] {clk} 39 | (M8.G) to[short, -o] ++ (0, 0) node [la, right] {clk} 40 | (M5.G) to[short, -o] ++ (-0, 0) node [la, left] {$S$} 41 | (M7.G) to[short, -o] ++ (0, 0) node [la, right] {$R$} 42 | ; 43 | \end{circuitikz}% 44 | -------------------------------------------------------------------------------- /fig/nand8.tex: -------------------------------------------------------------------------------- 1 | \begin{circuitikz}[ 2 | , null n/.style = { 3 | , inner sep = 0 4 | , outer sep = 0 5 | , minimum size = 0 6 | } 7 | , la/.style = { 8 | , font = \sffamily 9 | } 10 | , P/.style = { 11 | , pmos 12 | , font = \footnotesize 13 | } 14 | , N/.style = { 15 | , nmos 16 | , font = \footnotesize 17 | } 18 | ] 19 | \draw 20 | (-7, 1) node (Mp1) [P] {\hspace{-1em}8} 21 | (-5, 1) node (Mp2) [P] {\hspace{-1em}8} 22 | (-3, 1) node (Mp3) [P] {\hspace{-1em}8} 23 | (-1, 1) node (Mp4) [P] {\hspace{-1em}8} 24 | (1, 1) node (Mp5) [P] {\hspace{-1em}8} 25 | (3, 1) node (Mp6) [P] {\hspace{-1em}8} 26 | (5, 1) node (Mp7) [P] {\hspace{-1em}8} 27 | (7, 1) node (Mp8) [P] {\hspace{-1em}8} 28 | ([xshift = -7pt]Mp1.S) -- ([xshift=7pt]Mp8.S) node [midway, above] {$V_{DD}$} 29 | (Mp1.D) -- (Mp8.D) 30 | (0, -1) node (Mn1) [N] {\hspace{-1em}40} 31 | (0, -2.5) node (Mn2) [N] {\hspace{-1em}40} 32 | (0, -4) node (Mn3) [N] {\hspace{-1em}40} 33 | (0, -5.5) node (Mn4) [N] {\hspace{-1em}40} 34 | (0, -7) node (Mn5) [N] {\hspace{-1em}40} 35 | (0, -8.5) node (Mn6) [N] {\hspace{-1em}40} 36 | (0, -10) node (Mn7) [N] {\hspace{-1em}40} 37 | (0, -11.5) node (Mn8) [N] {\hspace{-1em}40} 38 | (Mn1.D) to[short, -*] (Mp1.D -| Mn1.D) 39 | (Mn1.D) to[short, *-o] ++ (0.5, 0) node [right, la, mark=*] {out} 40 | (Mn8.S) ++ (0, 0) node [tlground] {} 41 | (Mp1.G) to[short, -o] ++ (-0, 0) node [left, la, mark=*] {in1} 42 | (Mp2.G) to[short, -o] ++ (-0, 0) node [left, la, mark=*] {in2} 43 | (Mp3.G) to[short, -o] ++ (-0, 0) node [left, la, mark=*] {in3} 44 | (Mp4.G) to[short, -o] ++ (-0, 0) node [left, la, mark=*] {in4} 45 | (Mp5.G) to[short, -o] ++ (-0, 0) node [left, la, mark=*] {in5} 46 | (Mp6.G) to[short, -o] ++ (-0, 0) node [left, la, mark=*] {in6} 47 | (Mp7.G) to[short, -o] ++ (-0, 0) node [left, la, mark=*] {in7} 48 | (Mp8.G) to[short, -o] ++ (-0, 0) node [left, la, mark=*] {in8} 49 | (Mn1.G) to[short, -o] ++ (-0, 0) node [left, la, mark=*] {in1} 50 | (Mn2.G) to[short, -o] ++ (-0, 0) node [left, la, mark=*] {in2} 51 | (Mn3.G) to[short, -o] ++ (-0, 0) node [left, la, mark=*] {in3} 52 | (Mn4.G) to[short, -o] ++ (-0, 0) node [left, la, mark=*] {in4} 53 | (Mn5.G) to[short, -o] ++ (-0, 0) node [left, la, mark=*] {in5} 54 | (Mn6.G) to[short, -o] ++ (-0, 0) node [left, la, mark=*] {in6} 55 | (Mn7.G) to[short, -o] ++ (-0, 0) node [left, la, mark=*] {in7} 56 | (Mn8.G) to[short, -o] ++ (-0, 0) node [left, la, mark=*] {in8} 57 | ; 58 | \end{circuitikz}% 59 | -------------------------------------------------------------------------------- /inv.cir: -------------------------------------------------------------------------------- 1 | * ============================================================================= 2 | * Circuit : CMOS Inverter with 1 PMOS + 1 NMOS 3 | * Description: tr = tf when C_L = 0.024pF 4 | * 5 | * Author : Wuqiong Zhao (me@wqzhao.org) 6 | * Date : 2023-06-01 7 | * License : MIT 8 | * ============================================================================= 9 | 10 | * Reference: 11 | * https://github.com/cornell-ece5745/ece5745-tut10-spice/blob/master/sim/inv-sim.sp 12 | 13 | .title CMOS Inverter 14 | 15 | * Parameters and Model 16 | * ----------------------------------------------------------------------------- 17 | .param VDD='1.0V' 18 | .temp 27 19 | .inc ./FreePDK45/ff.inc 20 | 21 | * Supply Voltage Source 22 | * ----------------------------------------------------------------------------- 23 | Vdd vdd gnd VDD 24 | 25 | * Inverter 26 | * ----------------------------------------------------------------------------- 27 | .inc ./inv.inc 28 | XInv gnd in out vdd INV 29 | 30 | * Load Capacitor 31 | * ----------------------------------------------------------------------------- 32 | CL out gnd 24fF 33 | 34 | * Input Signals 35 | * ----------------------------------------------------------------------------- 36 | Vin in gnd PWL 37 | + ( 38 | + 0.0ns 0V 39 | + 0.9ns 0V 40 | + 1.1ns VDD 41 | + 1.9ns VDD 42 | + 2.1ns 0V 43 | + 3.0ns 0V 44 | + ) 45 | 46 | * Analysis 47 | * ----------------------------------------------------------------------------- 48 | .ic V(out)=VDD 49 | .tran 0.005ns 3ns 50 | 51 | .control 52 | run 53 | * >>>>> plot >>>>>> 54 | set xgridwidth = 2 55 | set xbrushwidth = 3 56 | * "svgwidth", "svgheight", "svgfont-size", "svgfont-width", "svguse-color", "svgstroke-width", "svggrid-width", 57 | set svg_intopts = ( 1024 256 16 0 1 2 0 ) 58 | * "svgbackground", "svgfont-family", "svgfont" 59 | setcs svg_stropts = ( white Arial Arial ) 60 | set hcopydevtype = svg 61 | set color1 = black 62 | set color2 = blue 63 | set color3 = red 64 | 65 | hardcopy fig/plot_inv_t.svg 66 | + out in 67 | + title 'CMOS Inverter' 68 | + xlabel 't' 69 | + ylabel 'Voltage' 70 | + ylimit 0 1 71 | 72 | * for MS Windows, using Edge 73 | if $oscompiled = 1 | $oscompiled = 8 74 | shell Start fig/plot_inv_t.svg 75 | else 76 | if $oscompiled = 7 77 | * macOS (using Safari, no need to install X11) 78 | shell open -a safari fig/plot_inv_t.svg & 79 | else 80 | * for CYGWIN, Linux, using feh and X11 81 | shell feh --magick-timeout 1 fig/plot_inv_t.svg & 82 | end 83 | end 84 | * <<<<< plot <<<<< 85 | .endc 86 | 87 | * Measurement 88 | * ----------------------------------------------------------------------------- 89 | .measure tran tr trig V(out) val='VDD*0.1' rise=1 targ V(out) val='VDD*0.9' rise=1 90 | .measure tran tf trig V(out) val='VDD*0.9' fall=1 targ V(out) val='VDD*0.1' fall=1 91 | .measure tran tpdr trig V(in) val='VDD/2' fall=1 targ V(out) val='VDD/2' rise=1 92 | .measure tran tpdf trig V(in) val='VDD/2' rise=1 targ V(out) val='VDD/2' fall=1 93 | .measure tran tpd param='(tpdr+tpdf)/2' 94 | 95 | .end 96 | -------------------------------------------------------------------------------- /nor2.cir: -------------------------------------------------------------------------------- 1 | * ============================================================================= 2 | * Circuit : CMOS NOR2 Gate 3 | * Description: 2 PMOS + 2 NMOS 4 | * 5 | * Author : Wuqiong Zhao (me@wqzhao.org) 6 | * Date : 2023-06-02 7 | * License : MIT 8 | * ============================================================================= 9 | 10 | .title CMOS NOR2 11 | 12 | * Parameters and Model 13 | * ----------------------------------------------------------------------------- 14 | .param VDD='1.0V' 15 | .temp 27 16 | .inc ./FreePDK45/ff.inc 17 | 18 | * Supply Voltage Source 19 | * ----------------------------------------------------------------------------- 20 | Vdd vdd gnd VDD 21 | 22 | * NOR2 23 | * ----------------------------------------------------------------------------- 24 | XNOR2 gnd in1 in2 out vdd NOR2 25 | .inc ./nor2.inc 26 | 27 | * Load Capacitor 28 | * ----------------------------------------------------------------------------- 29 | CL out gnd 24fF 30 | 31 | * Input Signals 32 | * ----------------------------------------------------------------------------- 33 | Vin1 in1 gnd PWL 34 | + ( 35 | + 0.0ns VDD 36 | + 0.9ns VDD 37 | + 1.1ns 0V 38 | + 3.0ns 0V 39 | + ) 40 | 41 | Vin2 in2 gnd PWL 42 | + ( 43 | + 0.0ns VDD 44 | + 0.9ns VDD 45 | + 1.1ns 0V 46 | + 1.9ns 0V 47 | + 2.1ns VDD 48 | + 3.0ns VDD 49 | + ) 50 | 51 | * Analysis 52 | * ----------------------------------------------------------------------------- 53 | .ic V(out)=0V 54 | .tran 0.005ns 3ns 55 | 56 | .control 57 | run 58 | * >>>>> plot >>>>>> 59 | set xgridwidth = 2 60 | set xbrushwidth = 3 61 | * "svgwidth", "svgheight", "svgfont-size", "svgfont-width", "svguse-color", "svgstroke-width", "svggrid-width", 62 | set svg_intopts = ( 1024 256 16 0 1 2 0 ) 63 | * "svgbackground", "svgfont-family", "svgfont" 64 | setcs svg_stropts = ( white Arial Arial ) 65 | set hcopydevtype = svg 66 | set color1 = black 67 | set color2 = red 68 | set color3 = blue 69 | set color4 = green 70 | 71 | hardcopy fig/plot_nor2_t.svg 72 | + in1 out in2 73 | + title 'CMOS NOR2' 74 | + xlabel 't' 75 | + ylabel 'Voltage' 76 | + ylimit 0 1 77 | 78 | * for MS Windows, using Edge 79 | if $oscompiled = 1 | $oscompiled = 8 80 | shell Start fig/plot_nor2_t.svg 81 | else 82 | if $oscompiled = 7 83 | * macOS (using Safari, no need to install X11) 84 | shell open -a safari fig/plot_nor2_t.svg & 85 | else 86 | * for CYGWIN, Linux, using feh and X11 87 | shell feh --magick-timeout 1 fig/plot_nor2_t.svg & 88 | end 89 | end 90 | * <<<<< plot <<<<< 91 | .endc 92 | 93 | * Measurement 94 | * ----------------------------------------------------------------------------- 95 | .measure tran tr trig V(out) val='VDD*0.1' rise=1 targ V(out) val='VDD*0.9' rise=1 96 | .measure tran tf trig V(out) val='VDD*0.9' fall=1 targ V(out) val='VDD*0.1' fall=1 97 | .measure tran tpdr trig V(in2) val='VDD/2' fall=1 targ V(out) val='VDD/2' rise=1 98 | .measure tran tpdf trig V(in2) val='VDD/2' rise=1 targ V(out) val='VDD/2' fall=1 99 | .measure tran tpd param='(tpdr+tpdf)/2' 100 | 101 | .end 102 | -------------------------------------------------------------------------------- /nand2.cir: -------------------------------------------------------------------------------- 1 | * ============================================================================= 2 | * Circuit : CMOS NAND2 Gate 3 | * Description: 2 PMOS + 2 NMOS 4 | * 5 | * Author : Wuqiong Zhao (me@wqzhao.org) 6 | * Date : 2023-06-01 7 | * License : MIT 8 | * ============================================================================= 9 | 10 | .title CMOS NAND2 11 | 12 | * Parameters and Model 13 | * ----------------------------------------------------------------------------- 14 | .param VDD='1.0V' 15 | .temp 27 16 | .inc ./FreePDK45/ff.inc 17 | 18 | * Supply Voltage Source 19 | * ----------------------------------------------------------------------------- 20 | Vdd vdd gnd VDD 21 | 22 | * NAND2 23 | * ----------------------------------------------------------------------------- 24 | XNAND2 gnd in1 in2 out vdd NAND2 25 | .inc ./nand2.inc 26 | 27 | * Load Capacitor 28 | * ----------------------------------------------------------------------------- 29 | CL out gnd 24fF 30 | 31 | * Input Signals 32 | * ----------------------------------------------------------------------------- 33 | Vin1 in1 gnd PWL 34 | + ( 35 | + 0.0ns 0V 36 | + 0.9ns 0V 37 | + 1.1ns VDD 38 | + 3.0ns VDD 39 | + ) 40 | 41 | Vin2 in2 gnd PWL 42 | + ( 43 | + 0.0ns 0V 44 | + 0.9ns 0V 45 | + 1.1ns VDD 46 | + 1.9ns VDD 47 | + 2.1ns 0V 48 | + 3.0ns 0V 49 | + ) 50 | 51 | * Analysis 52 | * ----------------------------------------------------------------------------- 53 | .ic V(out)=VDD 54 | .tran 0.005ns 3ns 55 | 56 | .control 57 | run 58 | * >>>>> plot >>>>>> 59 | set xgridwidth = 2 60 | set xbrushwidth = 3 61 | * "svgwidth", "svgheight", "svgfont-size", "svgfont-width", "svguse-color", "svgstroke-width", "svggrid-width", 62 | set svg_intopts = ( 1024 256 16 0 1 2 0 ) 63 | * "svgbackground", "svgfont-family", "svgfont" 64 | setcs svg_stropts = ( white Arial Arial ) 65 | set hcopydevtype = svg 66 | set color1 = black 67 | set color2 = red 68 | set color3 = blue 69 | set color4 = green 70 | 71 | hardcopy fig/plot_nand2_t.svg 72 | + in1 out in2 73 | + title 'CMOS NAND2' 74 | + xlabel 't' 75 | + ylabel 'Voltage' 76 | + ylimit 0 1 77 | 78 | * for MS Windows, using Edge 79 | if $oscompiled = 1 | $oscompiled = 8 80 | shell Start fig/plot_nand2_t.svg 81 | else 82 | if $oscompiled = 7 83 | * macOS (using Safari, no need to install X11) 84 | shell open -a safari fig/plot_nand2_t.svg & 85 | else 86 | * for CYGWIN, Linux, using feh and X11 87 | shell feh --magick-timeout 1 fig/plot_nand2_t.svg & 88 | end 89 | end 90 | * <<<<< plot <<<<< 91 | .endc 92 | 93 | * Measurement 94 | * ----------------------------------------------------------------------------- 95 | .measure tran tr trig V(out) val='VDD*0.1' rise=1 targ V(out) val='VDD*0.9' rise=1 96 | .measure tran tf trig V(out) val='VDD*0.9' fall=1 targ V(out) val='VDD*0.1' fall=1 97 | .measure tran tpdr trig V(in2) val='VDD/2' fall=1 targ V(out) val='VDD/2' rise=1 98 | .measure tran tpdf trig V(in1) val='VDD/2' rise=1 targ V(out) val='VDD/2' fall=1 99 | .measure tran tpd param='(tpdr+tpdf)/2' 100 | 101 | .end 102 | -------------------------------------------------------------------------------- /and2.cir: -------------------------------------------------------------------------------- 1 | * ============================================================================= 2 | * Circuit : CMOS AND2 Gate 3 | * Description: NMOS2 + Inverter (3 PMOS + 3 NMOS) 4 | * 5 | * Author : Wuqiong Zhao (me@wqzhao.org) 6 | * Date : 2023-06-02 7 | * License : MIT 8 | * ============================================================================= 9 | 10 | .title CMOS AND2 11 | 12 | * Parameters and Model 13 | * ----------------------------------------------------------------------------- 14 | .param VDD='1.0V' 15 | .temp 27 16 | .inc ./FreePDK45/ff.inc 17 | 18 | * Supply Voltage Source 19 | * ----------------------------------------------------------------------------- 20 | Vdd vdd gnd VDD 21 | 22 | * AND2 23 | * ----------------------------------------------------------------------------- 24 | XAND2 gnd in1 in2 out vdd AND2 25 | .inc ./and2.inc 26 | 27 | * Load Capacitor 28 | * ----------------------------------------------------------------------------- 29 | CL out gnd 24fF 30 | 31 | * Input Signals 32 | * ----------------------------------------------------------------------------- 33 | Vin1 in1 gnd PWL 34 | + ( 35 | + 0.0ns 0V 36 | + 0.9ns 0V 37 | + 1.1ns VDD 38 | + 3.0ns VDD 39 | + ) 40 | 41 | Vin2 in2 gnd PWL 42 | + ( 43 | + 0.0ns 0V 44 | + 0.9ns 0V 45 | + 1.1ns VDD 46 | + 1.9ns VDD 47 | + 2.1ns 0V 48 | + 3.0ns 0V 49 | + ) 50 | 51 | * Analysis 52 | * ----------------------------------------------------------------------------- 53 | .ic V(out)=0 54 | .tran 0.005ns 3ns 55 | 56 | .control 57 | run 58 | * >>>>> plot >>>>>> 59 | set xgridwidth = 2 60 | set xbrushwidth = 3 61 | * "svgwidth", "svgheight", "svgfont-size", "svgfont-width", "svguse-color", "svgstroke-width", "svggrid-width", 62 | set svg_intopts = ( 1024 256 16 0 1 2 0 ) 63 | * "svgbackground", "svgfont-family", "svgfont" 64 | setcs svg_stropts = ( white Arial Arial ) 65 | set hcopydevtype = svg 66 | set color1 = black 67 | set color2 = red 68 | set color3 = blue 69 | set color4 = green 70 | 71 | hardcopy fig/plot_and2_t.svg 72 | + in1 out in2 73 | + title 'CMOS AND2' 74 | + xlabel 't' 75 | + ylabel 'Voltage' 76 | + ylimit 0 1 77 | 78 | * for MS Windows, using Edge 79 | if $oscompiled = 1 | $oscompiled = 8 80 | shell Start fig/plot_and2_t.svg 81 | else 82 | if $oscompiled = 7 83 | * macOS (using Safari, no need to install X11) 84 | shell open -a safari fig/plot_and2_t.svg & 85 | else 86 | * for CYGWIN, Linux, using feh and X11 87 | shell feh --magick-timeout 1 fig/plot_and2_t.svg & 88 | end 89 | end 90 | * <<<<< plot <<<<< 91 | .endc 92 | 93 | * Measurement 94 | * ----------------------------------------------------------------------------- 95 | .measure tran tr trig V(out) val='VDD*0.1' rise=1 targ V(out) val='VDD*0.9' rise=1 96 | .measure tran tf trig V(out) val='VDD*0.9' fall=1 targ V(out) val='VDD*0.1' fall=1 97 | .measure tran tpdr trig V(in1) val='VDD/2' rise=1 targ V(out) val='VDD/2' rise=1 98 | .measure tran tpdf trig V(in2) val='VDD/2' fall=1 targ V(out) val='VDD/2' fall=1 99 | .measure tran tpd param='(tpdr+tpdf)/2' 100 | 101 | .end 102 | -------------------------------------------------------------------------------- /fig/plot_inv_t.svg: -------------------------------------------------------------------------------- 1 | 2 | 4 | 9 | 10 | 11 | 12 | 13 | 14 | t 15 | 16 | 17 | voltage 18 | 19 | 20 | tran1: cmos inverter 21 | 22 | 23 | 24 | 0.0 25 | 26 | 27 | 28 | 0.5 29 | 30 | 31 | 32 | 1.0 33 | 34 | 35 | 36 | 1.5 37 | 38 | 39 | 40 | 2.0 41 | 42 | 43 | 44 | 2.5 45 | 46 | 47 | 48 | 3.0 49 | 50 | 51 | ns 52 | 53 | 54 | 55 | 0.0 56 | 57 | 58 | 59 | 0.5 60 | 61 | 62 | 63 | 1.0 64 | 65 | 66 | V 67 | 68 | 69 | 70 | out 71 | 72 | 73 | 74 | 75 | 76 | 77 | in 78 | 79 | 80 | 81 | 82 | -------------------------------------------------------------------------------- /SR_latch_clk.cir: -------------------------------------------------------------------------------- 1 | * ============================================================================= 2 | * Circuit : Clock Controlled SR Latch 3 | * Description: 2 PMOS + 6 NMOS 4 | * 5 | * Author : Wuqiong Zhao (me@wqzhao.org) 6 | * Date : 2023-06-03 7 | * License : MIT 8 | * ============================================================================= 9 | 10 | .title CMOS Clock Controlled SR Latch 11 | 12 | * Parameters and Model 13 | * ----------------------------------------------------------------------------- 14 | .param VDD='1.0V' 15 | .temp 27 16 | .inc ./FreePDK45/ff.inc 17 | 18 | * Supply Voltage Source 19 | * ----------------------------------------------------------------------------- 20 | Vdd vdd gnd VDD 21 | 22 | * Clock Controlled SR Latch 23 | * ----------------------------------------------------------------------------- 24 | .inc ./SR_latch_clk.inc 25 | XLatch gnd s r clk q qn vdd SR_LATCH_CLK 26 | 27 | * Input Signals 28 | * ----------------------------------------------------------------------------- 29 | Vs s gnd PWL 30 | + ( 31 | + 0.0ns 0V 32 | + 0.9ns 0V 33 | + 1.1ns VDD 34 | + 1.9ns VDD 35 | + 2.1ns 0V 36 | + 3.0ns 0V 37 | + ) 38 | 39 | Vr r gnd PWL 40 | + ( 41 | + 0.0ns 0V 42 | + 2.4ns 0V 43 | + 2.6ns VDD 44 | + 3.5ns VDD 45 | + ) 46 | 47 | Vclk clk gnd PWL 48 | + ( 49 | + 0.0ns VDD 50 | + 3.0ns VDD 51 | + ) 52 | 53 | * Analysis 54 | * ----------------------------------------------------------------------------- 55 | .ic V(qn)=VDD 56 | .ic V(q) =0V 57 | .tran 0.005ns 3ns 58 | 59 | .param WL = 10 60 | .probe V(qn) 61 | 62 | .control 63 | set xgridwidth = 2 64 | set xbrushwidth = 3 65 | * "svgwidth", "svgheight", "svgfont-size", "svgfont-width", "svguse-color", "svgstroke-width", "svggrid-width", 66 | set svg_intopts = ( 1024 256 16 0 1 2 0 ) 67 | * "svgbackground", "svgfont-family", "svgfont" 68 | setcs svg_stropts = ( white Arial Arial ) 69 | set hcopydevtype = svg 70 | set color1 = black 71 | 72 | * Sweep Parameters 73 | foreach x 2 4 4.2 4.5 5 6 8 74 | alterparam WL = $x 75 | reset 76 | run 77 | end 78 | 79 | let WL2 = tran1.V(qn) 80 | let WL4 = tran2.V(qn) 81 | let WL4.2 = tran3.V(qn) 82 | let WL4.5 = tran4.V(qn) 83 | let WL5 = tran5.V(qn) 84 | let WL6 = tran6.V(qn) 85 | let WL8 = tran7.V(qn) 86 | 87 | hardcopy fig/plot_sr_latch_wl_t.svg 88 | + s r WL2 WL4 WL4.2 WL4.5 WL5 WL6 WL8 89 | + title 'CMOS Clock Controlled SR Latch With Different W/L' 90 | + xlabel 't' 91 | + ylabel 'Voltage' 92 | + ylimit 0 1 93 | 94 | * for MS Windows, using Edge 95 | if $oscompiled = 1 | $oscompiled = 8 96 | shell Start fig/plot_sr_latch_wl_t.svg 97 | else 98 | if $oscompiled = 7 99 | * macOS (using Safari, no need to install X11) 100 | shell open -a safari fig/plot_sr_latch_wl_t.svg & 101 | else 102 | * for CYGWIN, Linux, using feh and X11 103 | shell feh --magick-timeout 1 fig/plot_sr_latch_wl_t.svg & 104 | end 105 | end 106 | 107 | * One example that This SR Latch will work. 108 | alterparam WL = 6 109 | reset 110 | run 111 | set color2 = red 112 | set color3 = blue 113 | set color4 = green 114 | set color5 = brown 115 | 116 | hardcopy fig/plot_sr_latch_t.svg 117 | + qn q s r 118 | + title 'CMOS Clock Controlled SR Latch' 119 | + xlabel 't' 120 | + ylabel 'Voltage' 121 | + ylimit 0 1 122 | 123 | * for MS Windows, using Edge 124 | if $oscompiled = 1 | $oscompiled = 8 125 | shell Start fig/plot_sr_latch_t.svg 126 | else 127 | if $oscompiled = 7 128 | * macOS (using Safari, no need to install X11) 129 | shell open -a safari fig/plot_sr_latch_t.svg & 130 | else 131 | * for CYGWIN, Linux, using feh and X11 132 | shell feh --magick-timeout 1 fig/plot_sr_latch_t.svg & 133 | end 134 | end 135 | .endc 136 | 137 | .end 138 | -------------------------------------------------------------------------------- /fig/plot_and8c_t.svg: -------------------------------------------------------------------------------- 1 | 2 | 4 | 9 | 10 | 11 | 12 | 13 | 14 | t 15 | 16 | 17 | voltage 18 | 19 | 20 | tran1: cmos and8c 21 | 22 | 23 | 24 | 0.0 25 | 26 | 27 | 28 | 0.5 29 | 30 | 31 | 32 | 1.0 33 | 34 | 35 | 36 | 1.5 37 | 38 | 39 | 40 | 2.0 41 | 42 | 43 | 44 | 2.5 45 | 46 | 47 | 48 | 3.0 49 | 50 | 51 | ns 52 | 53 | 54 | 55 | -0.2 56 | 57 | 58 | 59 | 0.5 60 | 61 | 62 | 63 | 1.2 64 | 65 | 66 | V 67 | 68 | 69 | 70 | in1 71 | 72 | 73 | 74 | 75 | out 76 | 77 | 78 | 79 | 80 | 81 | in8 82 | 83 | 84 | 85 | 86 | -------------------------------------------------------------------------------- /fig/plot_and8b_t.svg: -------------------------------------------------------------------------------- 1 | 2 | 4 | 9 | 10 | 11 | 12 | 13 | 14 | t 15 | 16 | 17 | voltage 18 | 19 | 20 | tran1: cmos and8b 21 | 22 | 23 | 24 | 0.0 25 | 26 | 27 | 28 | 0.5 29 | 30 | 31 | 32 | 1.0 33 | 34 | 35 | 36 | 1.5 37 | 38 | 39 | 40 | 2.0 41 | 42 | 43 | 44 | 2.5 45 | 46 | 47 | 48 | 3.0 49 | 50 | 51 | ns 52 | 53 | 54 | 55 | -0.2 56 | 57 | 58 | 59 | 0.5 60 | 61 | 62 | 63 | 1.2 64 | 65 | 66 | V 67 | 68 | 69 | 70 | in1 71 | 72 | 73 | 74 | 75 | out 76 | 77 | 78 | 79 | 80 | 81 | in8 82 | 83 | 84 | 85 | 86 | -------------------------------------------------------------------------------- /fig/plot_and2_t.svg: -------------------------------------------------------------------------------- 1 | 2 | 4 | 9 | 10 | 11 | 12 | 13 | 14 | t 15 | 16 | 17 | voltage 18 | 19 | 20 | tran1: cmos and2 21 | 22 | 23 | 24 | 0.0 25 | 26 | 27 | 28 | 0.5 29 | 30 | 31 | 32 | 1.0 33 | 34 | 35 | 36 | 1.5 37 | 38 | 39 | 40 | 2.0 41 | 42 | 43 | 44 | 2.5 45 | 46 | 47 | 48 | 3.0 49 | 50 | 51 | ns 52 | 53 | 54 | 55 | 0.0 56 | 57 | 58 | 59 | 0.5 60 | 61 | 62 | 63 | 1.0 64 | 65 | 66 | V 67 | 68 | 69 | 70 | in1 71 | 72 | 73 | 74 | 75 | 76 | out 77 | 78 | 79 | 80 | 81 | 82 | in2 83 | 84 | 85 | 86 | 87 | -------------------------------------------------------------------------------- /fig/plot_and8a_t.svg: -------------------------------------------------------------------------------- 1 | 2 | 4 | 9 | 10 | 11 | 12 | 13 | 14 | t 15 | 16 | 17 | voltage 18 | 19 | 20 | tran1: cmos and8a 21 | 22 | 23 | 24 | 0.0 25 | 26 | 27 | 28 | 0.5 29 | 30 | 31 | 32 | 1.0 33 | 34 | 35 | 36 | 1.5 37 | 38 | 39 | 40 | 2.0 41 | 42 | 43 | 44 | 2.5 45 | 46 | 47 | 48 | 3.0 49 | 50 | 51 | ns 52 | 53 | 54 | 55 | -0.2 56 | 57 | 58 | 59 | 0.5 60 | 61 | 62 | 63 | 1.2 64 | 65 | 66 | V 67 | 68 | 69 | 70 | in1 71 | 72 | 73 | 74 | 75 | 76 | out 77 | 78 | 79 | 80 | 81 | 82 | in8 83 | 84 | 85 | 86 | 87 | -------------------------------------------------------------------------------- /and8b.cir: -------------------------------------------------------------------------------- 1 | * ============================================================================= 2 | * Circuit : CMOS AND8 Gate Type B 3 | * Description: NAND4A * 2 + NOR2 * 1 4 | * 5 | * Author : Wuqiong Zhao (me@wqzhao.org) 6 | * Date : 2023-06-02 7 | * License : MIT 8 | * ============================================================================= 9 | 10 | .title CMOS AND8B 11 | 12 | * Parameters and Model 13 | * ----------------------------------------------------------------------------- 14 | .param VDD='1.0V' 15 | .temp 25 16 | .inc ./FreePDK45/ff.inc 17 | 18 | * Supply Voltage Source 19 | * ----------------------------------------------------------------------------- 20 | Vdd vdd gnd VDD 21 | 22 | * AND8B 23 | * ----------------------------------------------------------------------------- 24 | XAND8 gnd in1 in2 in3 in4 in5 in6 in7 in8 out vdd AND8B 25 | .inc ./and8b.inc 26 | 27 | * Test Circuit 28 | * ----------------------------------------------------------------------------- 29 | XTest gnd 30 | + ii1 ii2 ii3 ii4 ii5 ii6 ii7 ii8 31 | + in1 in2 in3 in4 in5 in6 in7 in8 32 | + out vdd INV2_TEST 33 | .inc ./and8_test_inv2.inc 34 | 35 | * Input Signals 36 | * ----------------------------------------------------------------------------- 37 | Vii1 ii1 gnd PWL 38 | + ( 39 | + 0.0ns 0V 40 | + 0.9ns 0V 41 | + 1.1ns VDD 42 | + 3.0ns VDD 43 | + ) 44 | 45 | Vii2 ii2 gnd PWL 46 | + ( 47 | + 0.0ns 0V 48 | + 0.9ns 0V 49 | + 1.1ns VDD 50 | + 3.0ns VDD 51 | + ) 52 | 53 | Vii3 ii3 gnd PWL 54 | + ( 55 | + 0.0ns 0V 56 | + 0.9ns 0V 57 | + 1.1ns VDD 58 | + 3.0ns VDD 59 | + ) 60 | 61 | Vii4 ii4 gnd PWL 62 | + ( 63 | + 0.0ns 0V 64 | + 0.9ns 0V 65 | + 1.1ns VDD 66 | + 3.0ns VDD 67 | + ) 68 | 69 | Vii5 ii5 gnd PWL 70 | + ( 71 | + 0.0ns 0V 72 | + 0.9ns 0V 73 | + 1.1ns VDD 74 | + 3.0ns VDD 75 | + ) 76 | 77 | Vii6 ii6 gnd PWL 78 | + ( 79 | + 0.0ns 0V 80 | + 0.9ns 0V 81 | + 1.1ns VDD 82 | + 3.0ns VDD 83 | + ) 84 | 85 | Vii7 ii7 gnd PWL 86 | + ( 87 | + 0.0ns 0V 88 | + 0.9ns 0V 89 | + 1.1ns VDD 90 | + 3.0ns VDD 91 | + ) 92 | 93 | Vii8 ii8 gnd PWL 94 | + ( 95 | + 0.0ns 0V 96 | + 0.9ns 0V 97 | + 1.1ns VDD 98 | + 1.9ns VDD 99 | + 2.1ns 0V 100 | + 3.0ns 0V 101 | + ) 102 | 103 | * Analysis 104 | * ----------------------------------------------------------------------------- 105 | .ic V(out)=0 106 | .tran 0.005ns 3ns 107 | 108 | .control 109 | run 110 | * >>>>> plot >>>>>> 111 | set xgridwidth = 2 112 | set xbrushwidth = 3 113 | * "svgwidth", "svgheight", "svgfont-size", "svgfont-width", "svguse-color", "svgstroke-width", "svggrid-width", 114 | set svg_intopts = ( 1024 256 16 0 1 2 0 ) 115 | * "svgbackground", "svgfont-family", "svgfont" 116 | setcs svg_stropts = ( white Arial Arial ) 117 | set hcopydevtype = svg 118 | set color1 = black 119 | set color2 = red 120 | set color3 = blue 121 | set color4 = green 122 | 123 | hardcopy fig/plot_and8b_t.svg 124 | + in1 out in8 125 | + title 'CMOS AND8b' 126 | + xlabel 't' 127 | + ylabel 'Voltage' 128 | + ylimit -0.2 1.2 129 | + ydelta 0.5 130 | 131 | * for MS Windows, using Edge 132 | if $oscompiled = 1 | $oscompiled = 8 133 | shell Start fig/plot_and8b_t.svg 134 | else 135 | if $oscompiled = 7 136 | * macOS (using Safari, no need to install X11) 137 | shell open -a safari fig/plot_and8b_t.svg & 138 | else 139 | * for CYGWIN, Linux, using feh and X11 140 | shell feh --magick-timeout 1 fig/plot_and8b_t.svg & 141 | end 142 | end 143 | * <<<<< plot <<<<< 144 | .endc 145 | 146 | * Measurement 147 | * ----------------------------------------------------------------------------- 148 | .measure tran tr trig V(out) val='VDD*0.1' rise=1 targ V(out) val='VDD*0.9' rise=1 149 | .measure tran tf trig V(out) val='VDD*0.9' fall=1 targ V(out) val='VDD*0.1' fall=1 150 | .measure tran tpdr trig V(in1) val='VDD/2' rise=1 targ V(out) val='VDD/2' rise=1 151 | .measure tran tpdf trig V(in8) val='VDD/2' fall=1 targ V(out) val='VDD/2' fall=1 152 | .measure tran tpd param='(tpdr+tpdf)/2' 153 | 154 | * power dissipation of the AND8 gate 155 | .inc ./and8_test_pow.inc 156 | 157 | .end 158 | -------------------------------------------------------------------------------- /and8c.cir: -------------------------------------------------------------------------------- 1 | * ============================================================================= 2 | * Circuit : CMOS AND8 Gate Type C 3 | * Description: AND4B * 2 + AND2 * 1 4 | * 5 | * Author : Wuqiong Zhao (me@wqzhao.org) 6 | * Date : 2023-06-02 7 | * License : MIT 8 | * ============================================================================= 9 | 10 | .title CMOS AND8C 11 | 12 | * Parameters and Model 13 | * ----------------------------------------------------------------------------- 14 | .param VDD='1.0V' 15 | .temp 25 16 | .inc ./FreePDK45/ff.inc 17 | 18 | * Supply Voltage Source 19 | * ----------------------------------------------------------------------------- 20 | Vdd vdd gnd VDD 21 | 22 | * AND8C 23 | * ----------------------------------------------------------------------------- 24 | XAND8 gnd in1 in2 in3 in4 in5 in6 in7 in8 out vdd AND8C 25 | .inc ./and8c.inc 26 | 27 | * Test Circuit 28 | * ----------------------------------------------------------------------------- 29 | XTest gnd 30 | + ii1 ii2 ii3 ii4 ii5 ii6 ii7 ii8 31 | + in1 in2 in3 in4 in5 in6 in7 in8 32 | + out vdd INV2_TEST 33 | .inc ./and8_test_inv2.inc 34 | 35 | * Input Signals 36 | * ----------------------------------------------------------------------------- 37 | Vii1 ii1 gnd PWL 38 | + ( 39 | + 0.0ns 0V 40 | + 0.9ns 0V 41 | + 1.1ns VDD 42 | + 3.0ns VDD 43 | + ) 44 | 45 | Vii2 ii2 gnd PWL 46 | + ( 47 | + 0.0ns 0V 48 | + 0.9ns 0V 49 | + 1.1ns VDD 50 | + 3.0ns VDD 51 | + ) 52 | 53 | Vii3 ii3 gnd PWL 54 | + ( 55 | + 0.0ns 0V 56 | + 0.9ns 0V 57 | + 1.1ns VDD 58 | + 3.0ns VDD 59 | + ) 60 | 61 | Vii4 ii4 gnd PWL 62 | + ( 63 | + 0.0ns 0V 64 | + 0.9ns 0V 65 | + 1.1ns VDD 66 | + 3.0ns VDD 67 | + ) 68 | 69 | Vii5 ii5 gnd PWL 70 | + ( 71 | + 0.0ns 0V 72 | + 0.9ns 0V 73 | + 1.1ns VDD 74 | + 3.0ns VDD 75 | + ) 76 | 77 | Vii6 ii6 gnd PWL 78 | + ( 79 | + 0.0ns 0V 80 | + 0.9ns 0V 81 | + 1.1ns VDD 82 | + 3.0ns VDD 83 | + ) 84 | 85 | Vii7 ii7 gnd PWL 86 | + ( 87 | + 0.0ns 0V 88 | + 0.9ns 0V 89 | + 1.1ns VDD 90 | + 3.0ns VDD 91 | + ) 92 | 93 | Vii8 ii8 gnd PWL 94 | + ( 95 | + 0.0ns 0V 96 | + 0.9ns 0V 97 | + 1.1ns VDD 98 | + 1.9ns VDD 99 | + 2.1ns 0V 100 | + 3.0ns 0V 101 | + ) 102 | 103 | * Analysis 104 | * ----------------------------------------------------------------------------- 105 | .ic V(out)=0 106 | .tran 0.005ns 3ns 107 | 108 | .control 109 | run 110 | * >>>>> plot >>>>>> 111 | set xgridwidth = 2 112 | set xbrushwidth = 3 113 | * "svgwidth", "svgheight", "svgfont-size", "svgfont-width", "svguse-color", "svgstroke-width", "svggrid-width", 114 | set svg_intopts = ( 1024 256 16 0 1 2 0 ) 115 | * "svgbackground", "svgfont-family", "svgfont" 116 | setcs svg_stropts = ( white Arial Arial ) 117 | set hcopydevtype = svg 118 | set color1 = black 119 | set color2 = red 120 | set color3 = blue 121 | set color4 = green 122 | 123 | hardcopy fig/plot_and8c_t.svg 124 | + in1 out in8 125 | + title 'CMOS AND8c' 126 | + xlabel 't' 127 | + ylabel 'Voltage' 128 | + ylimit -0.2 1.2 129 | + ydelta 0.5 130 | 131 | * for MS Windows, using Edge 132 | if $oscompiled = 1 | $oscompiled = 8 133 | shell Start fig/plot_and8c_t.svg 134 | else 135 | if $oscompiled = 7 136 | * macOS (using Safari, no need to install X11) 137 | shell open -a safari fig/plot_and8c_t.svg & 138 | else 139 | * for CYGWIN, Linux, using feh and X11 140 | shell feh --magick-timeout 1 fig/plot_and8c_t.svg & 141 | end 142 | end 143 | * <<<<< plot <<<<< 144 | .endc 145 | 146 | * Measurement 147 | * ----------------------------------------------------------------------------- 148 | .measure tran tr trig V(out) val='VDD*0.1' rise=1 targ V(out) val='VDD*0.9' rise=1 149 | .measure tran tf trig V(out) val='VDD*0.9' fall=1 targ V(out) val='VDD*0.1' fall=1 150 | .measure tran tpdr trig V(in1) val='VDD/2' rise=1 targ V(out) val='VDD/2' rise=1 151 | .measure tran tpdf trig V(in8) val='VDD/2' fall=1 targ V(out) val='VDD/2' fall=1 152 | .measure tran tpd param='(tpdr+tpdf)/2' 153 | 154 | * power dissipation of the AND8 gate 155 | .inc ./and8_test_pow.inc 156 | 157 | .end 158 | -------------------------------------------------------------------------------- /fig/plot_nor2_t.svg: -------------------------------------------------------------------------------- 1 | 2 | 4 | 9 | 10 | 11 | 12 | 13 | 14 | t 15 | 16 | 17 | voltage 18 | 19 | 20 | tran1: cmos nor2 21 | 22 | 23 | 24 | 0.0 25 | 26 | 27 | 28 | 0.5 29 | 30 | 31 | 32 | 1.0 33 | 34 | 35 | 36 | 1.5 37 | 38 | 39 | 40 | 2.0 41 | 42 | 43 | 44 | 2.5 45 | 46 | 47 | 48 | 3.0 49 | 50 | 51 | ns 52 | 53 | 54 | 55 | 0.0 56 | 57 | 58 | 59 | 0.5 60 | 61 | 62 | 63 | 1.0 64 | 65 | 66 | V 67 | 68 | 69 | 70 | in1 71 | 72 | 73 | 74 | 75 | out 76 | 77 | 78 | 79 | 80 | 81 | 82 | in2 83 | 84 | 85 | 86 | 87 | -------------------------------------------------------------------------------- /and8a.cir: -------------------------------------------------------------------------------- 1 | * ============================================================================= 2 | * Circuit : CMOS AND8 Gate Type A 3 | * Description: 8 PMOS + 8 NMOS (Symmetrical Design) + 1 Inv 4 | * 5 | * Author : Wuqiong Zhao (me@wqzhao.org) 6 | * Date : 2023-06-02 7 | * License : MIT 8 | * ============================================================================= 9 | 10 | .title CMOS AND8A 11 | 12 | * Parameters and Model 13 | * ----------------------------------------------------------------------------- 14 | .param VDD='1.0V' 15 | .temp 25 16 | .inc ./FreePDK45/ff.inc 17 | 18 | * Supply Voltage Source 19 | * ----------------------------------------------------------------------------- 20 | Vdd vdd gnd VDD 21 | 22 | * AND8A 23 | * ----------------------------------------------------------------------------- 24 | XAND8 gnd in1 in2 in3 in4 in5 in6 in7 in8 out vdd AND8A 25 | .inc ./and8a.inc 26 | 27 | * Test Circuit 28 | * ----------------------------------------------------------------------------- 29 | XTest gnd 30 | + ii1 ii2 ii3 ii4 ii5 ii6 ii7 ii8 31 | + in1 in2 in3 in4 in5 in6 in7 in8 32 | + out vdd INV2_TEST 33 | .inc ./and8_test_inv2.inc 34 | 35 | * Input Signals 36 | * ----------------------------------------------------------------------------- 37 | Vii1 ii1 gnd PWL 38 | + ( 39 | + 0.0ns 0V 40 | + 0.9ns 0V 41 | + 1.1ns VDD 42 | + 3.0ns VDD 43 | + ) 44 | 45 | Vii2 ii2 gnd PWL 46 | + ( 47 | + 0.0ns 0V 48 | + 0.9ns 0V 49 | + 1.1ns VDD 50 | + 3.0ns VDD 51 | + ) 52 | 53 | Vii3 ii3 gnd PWL 54 | + ( 55 | + 0.0ns 0V 56 | + 0.9ns 0V 57 | + 1.1ns VDD 58 | + 3.0ns VDD 59 | + ) 60 | 61 | Vii4 ii4 gnd PWL 62 | + ( 63 | + 0.0ns 0V 64 | + 0.9ns 0V 65 | + 1.1ns VDD 66 | + 3.0ns VDD 67 | + ) 68 | 69 | Vii5 ii5 gnd PWL 70 | + ( 71 | + 0.0ns 0V 72 | + 0.9ns 0V 73 | + 1.1ns VDD 74 | + 3.0ns VDD 75 | + ) 76 | 77 | Vii6 ii6 gnd PWL 78 | + ( 79 | + 0.0ns 0V 80 | + 0.9ns 0V 81 | + 1.1ns VDD 82 | + 3.0ns VDD 83 | + ) 84 | 85 | Vii7 ii7 gnd PWL 86 | + ( 87 | + 0.0ns 0V 88 | + 0.9ns 0V 89 | + 1.1ns VDD 90 | + 3.0ns VDD 91 | + ) 92 | 93 | Vii8 ii8 gnd PWL 94 | + ( 95 | + 0.0ns 0V 96 | + 0.9ns 0V 97 | + 1.1ns VDD 98 | + 1.9ns VDD 99 | + 2.1ns 0V 100 | + 3.0ns 0V 101 | + ) 102 | 103 | * Analysis 104 | * ----------------------------------------------------------------------------- 105 | .ic V(out)=0 106 | .tran 0.005ns 3ns 107 | 108 | .control 109 | run 110 | * >>>>> plot >>>>>> 111 | set xgridwidth = 2 112 | set xbrushwidth = 3 113 | * "svgwidth", "svgheight", "svgfont-size", "svgfont-width", "svguse-color", "svgstroke-width", "svggrid-width", 114 | set svg_intopts = ( 1024 256 16 0 1 2 0 ) 115 | * "svgbackground", "svgfont-family", "svgfont" 116 | setcs svg_stropts = ( white Arial Arial ) 117 | set hcopydevtype = svg 118 | set color1 = black 119 | set color2 = red 120 | set color3 = blue 121 | set color4 = green 122 | 123 | hardcopy fig/plot_and8a_t.svg 124 | + in1 out in8 125 | + title 'CMOS AND8a' 126 | + xlabel 't' 127 | + ylabel 'Voltage' 128 | + ylimit -0.2 1.2 129 | + ydelta 0.5 130 | 131 | * for MS Windows, using Edge 132 | if $oscompiled = 1 | $oscompiled = 8 133 | shell Start fig/plot_and8a_t.svg 134 | else 135 | if $oscompiled = 7 136 | * macOS (using Safari, no need to install X11) 137 | shell open -a safari fig/plot_and8a_t.svg & 138 | else 139 | * for CYGWIN, Linux, using feh and X11 140 | shell feh --magick-timeout 1 fig/plot_and8a_t.svg & 141 | end 142 | end 143 | * <<<<< plot <<<<< 144 | .endc 145 | 146 | * Measurement 147 | * ----------------------------------------------------------------------------- 148 | .measure tran tr trig V(out) val='VDD*0.1' rise=1 targ V(out) val='VDD*0.9' rise=1 149 | .measure tran tf trig V(out) val='VDD*0.9' fall=1 targ V(out) val='VDD*0.1' fall=1 150 | .measure tran tpdr trig V(in1) val='VDD/2' rise=1 targ V(out) val='VDD/2' rise=1 151 | .measure tran tpdf trig V(in8) val='VDD/2' fall=1 targ V(out) val='VDD/2' fall=1 152 | .measure tran tpd param='(tpdr+tpdf)/2' 153 | 154 | * power dissipation of the AND8 gate 155 | .inc ./and8_test_pow.inc 156 | 157 | .end 158 | -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | ## Core latex/pdflatex auxiliary files: 2 | *.aux 3 | *.lof 4 | *.log 5 | *.lot 6 | *.fls 7 | *.out 8 | *.toc 9 | *.fmt 10 | *.fot 11 | *.cb 12 | *.cb2 13 | .*.lb 14 | 15 | ## Intermediate documents: 16 | *.dvi 17 | *.xdv 18 | *-converted-to.* 19 | # these rules might exclude image files for figures etc. 20 | # *.ps 21 | # *.eps 22 | # *.pdf 23 | 24 | ## Generated if empty string is given at "Please type another file name for output:" 25 | .pdf 26 | 27 | ## Bibliography auxiliary files (bibtex/biblatex/biber): 28 | *.bbl 29 | *.bcf 30 | *.blg 31 | *-blx.aux 32 | *-blx.bib 33 | *.run.xml 34 | 35 | ## Build tool auxiliary files: 36 | *.fdb_latexmk 37 | *.synctex 38 | *.synctex(busy) 39 | *.synctex.gz 40 | *.synctex.gz(busy) 41 | *.pdfsync 42 | 43 | ## Build tool directories for auxiliary files 44 | # latexrun 45 | latex.out/ 46 | 47 | ## Auxiliary and intermediate files from other packages: 48 | # algorithms 49 | *.alg 50 | *.loa 51 | 52 | # achemso 53 | acs-*.bib 54 | 55 | # amsthm 56 | *.thm 57 | 58 | # beamer 59 | *.nav 60 | *.pre 61 | *.snm 62 | *.vrb 63 | 64 | # changes 65 | *.soc 66 | 67 | # comment 68 | *.cut 69 | 70 | # cprotect 71 | *.cpt 72 | 73 | # elsarticle (documentclass of Elsevier journals) 74 | *.spl 75 | 76 | # endnotes 77 | *.ent 78 | 79 | # fixme 80 | *.lox 81 | 82 | # feynmf/feynmp 83 | *.mf 84 | *.mp 85 | *.t[1-9] 86 | *.t[1-9][0-9] 87 | *.tfm 88 | 89 | #(r)(e)ledmac/(r)(e)ledpar 90 | *.end 91 | *.?end 92 | *.[1-9] 93 | *.[1-9][0-9] 94 | *.[1-9][0-9][0-9] 95 | *.[1-9]R 96 | *.[1-9][0-9]R 97 | *.[1-9][0-9][0-9]R 98 | *.eledsec[1-9] 99 | *.eledsec[1-9]R 100 | *.eledsec[1-9][0-9] 101 | *.eledsec[1-9][0-9]R 102 | *.eledsec[1-9][0-9][0-9] 103 | *.eledsec[1-9][0-9][0-9]R 104 | 105 | # glossaries 106 | *.acn 107 | *.acr 108 | *.glg 109 | *.glo 110 | *.gls 111 | *.glsdefs 112 | *.lzo 113 | *.lzs 114 | 115 | # uncomment this for glossaries-extra (will ignore makeindex's style files!) 116 | # *.ist 117 | 118 | # gnuplottex 119 | *-gnuplottex-* 120 | 121 | # gregoriotex 122 | *.gaux 123 | *.gtex 124 | 125 | # htlatex 126 | *.4ct 127 | *.4tc 128 | *.idv 129 | *.lg 130 | *.trc 131 | *.xref 132 | 133 | # hyperref 134 | *.brf 135 | 136 | # knitr 137 | *-concordance.tex 138 | # TODO Comment the next line if you want to keep your tikz graphics files 139 | *.tikz 140 | *-tikzDictionary 141 | 142 | # listings 143 | *.lol 144 | 145 | # luatexja-ruby 146 | *.ltjruby 147 | 148 | # makeidx 149 | *.idx 150 | *.ilg 151 | *.ind 152 | 153 | # minitoc 154 | *.maf 155 | *.mlf 156 | *.mlt 157 | *.mtc[0-9]* 158 | *.slf[0-9]* 159 | *.slt[0-9]* 160 | *.stc[0-9]* 161 | 162 | # minted 163 | _minted* 164 | *.pyg 165 | 166 | # morewrites 167 | *.mw 168 | 169 | # nomencl 170 | *.nlg 171 | *.nlo 172 | *.nls 173 | 174 | # pax 175 | *.pax 176 | 177 | # pdfpcnotes 178 | *.pdfpc 179 | 180 | # sagetex 181 | *.sagetex.sage 182 | *.sagetex.py 183 | *.sagetex.scmd 184 | 185 | # scrwfile 186 | *.wrt 187 | 188 | # sympy 189 | *.sout 190 | *.sympy 191 | sympy-plots-for-*.tex/ 192 | 193 | # pdfcomment 194 | *.upa 195 | *.upb 196 | 197 | # pythontex 198 | *.pytxcode 199 | pythontex-files-*/ 200 | 201 | # tcolorbox 202 | *.listing 203 | 204 | # thmtools 205 | *.loe 206 | 207 | # TikZ & PGF 208 | *.dpth 209 | *.md5 210 | *.auxlock 211 | 212 | # todonotes 213 | *.tdo 214 | 215 | # vhistory 216 | *.hst 217 | *.ver 218 | 219 | # easy-todo 220 | *.lod 221 | 222 | # xcolor 223 | *.xcp 224 | 225 | # xmpincl 226 | *.xmpi 227 | 228 | # xindy 229 | *.xdy 230 | 231 | # xypic precompiled matrices and outlines 232 | *.xyc 233 | *.xyd 234 | 235 | # endfloat 236 | *.ttt 237 | *.fff 238 | 239 | # Latexian 240 | TSWLatexianTemp* 241 | 242 | ## Editors: 243 | # WinEdt 244 | *.bak 245 | *.sav 246 | 247 | # Texpad 248 | .texpadtmp 249 | 250 | # LyX 251 | *.lyx~ 252 | 253 | # Kile 254 | *.backup 255 | 256 | # gummi 257 | .*.swp 258 | 259 | # KBibTeX 260 | *~[0-9]* 261 | 262 | # TeXnicCenter 263 | *.tps 264 | 265 | # auto folder when using emacs and auctex 266 | ./auto/* 267 | *.el 268 | 269 | # expex forward references with \gathertags 270 | *-tags.tex 271 | 272 | # standalone packages 273 | *.sta 274 | 275 | # Makeindex log files 276 | *.lpz 277 | 278 | # SVG Plots 279 | svg-inkscape 280 | *.svg 281 | !fig/*.svg 282 | 283 | # macOS 284 | .DS_Store 285 | -------------------------------------------------------------------------------- /fig/plot_nand2_t.svg: -------------------------------------------------------------------------------- 1 | 2 | 4 | 9 | 10 | 11 | 12 | 13 | 14 | t 15 | 16 | 17 | voltage 18 | 19 | 20 | tran1: cmos nand2 21 | 22 | 23 | 24 | 0.0 25 | 26 | 27 | 28 | 0.5 29 | 30 | 31 | 32 | 1.0 33 | 34 | 35 | 36 | 1.5 37 | 38 | 39 | 40 | 2.0 41 | 42 | 43 | 44 | 2.5 45 | 46 | 47 | 48 | 3.0 49 | 50 | 51 | ns 52 | 53 | 54 | 55 | 0.0 56 | 57 | 58 | 59 | 0.5 60 | 61 | 62 | 63 | 1.0 64 | 65 | 66 | V 67 | 68 | 69 | 70 | in1 71 | 72 | 73 | 74 | 75 | 76 | out 77 | 78 | 79 | 80 | 81 | 82 | 83 | in2 84 | 85 | 86 | 87 | 88 | -------------------------------------------------------------------------------- /fig/plot_sr_latch_t.svg: -------------------------------------------------------------------------------- 1 | 2 | 4 | 9 | 10 | 11 | 12 | 13 | 14 | t 15 | 16 | 17 | voltage 18 | 19 | 20 | tran8: cmos clock controlled sr latch 21 | 22 | 23 | 24 | 0.0 25 | 26 | 27 | 28 | 0.5 29 | 30 | 31 | 32 | 1.0 33 | 34 | 35 | 36 | 1.5 37 | 38 | 39 | 40 | 2.0 41 | 42 | 43 | 44 | 2.5 45 | 46 | 47 | 48 | 3.0 49 | 50 | 51 | ns 52 | 53 | 54 | 55 | 0.0 56 | 57 | 58 | 59 | 0.5 60 | 61 | 62 | 63 | 1.0 64 | 65 | 66 | V 67 | 68 | 69 | 70 | qn 71 | 72 | 73 | 74 | 75 | q 76 | 77 | 78 | 79 | 80 | s 81 | 82 | 83 | 84 | 85 | 86 | r 87 | 88 | 89 | 90 | 91 | -------------------------------------------------------------------------------- /fig/and8a_schematic.svg: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | -------------------------------------------------------------------------------- /FreePDK45/tran_models/models_ff/PMOS_THKOX.inc: -------------------------------------------------------------------------------- 1 | * Customized PTM 45 PMOS: ff 2 | 3 | .model PMOS_THKOX pmos level = 54 4 | 5 | +version = 4.0 binunit = 1 paramchk= 1 mobmod = 0 6 | +capmod = 2 igcmod = 1 igbmod = 1 geomod = 1 7 | +diomod = 1 rdsmod = 0 rbodymod= 1 rgatemod= 1 8 | +permod = 1 acnqsmod= 0 trnqsmod= 0 9 | 10 | * parameters related to the technology node 11 | +tnom = 27 epsrox = 3.9 12 | +eta0 = 0.0049 nfactor = 2.1 wint = 5e-09 13 | +cgso = 1.1e-10 cgdo = 1.1e-10 xl = -2e-08 14 | 15 | * parameters customized by the user 16 | +toxe = 6.75e-09 toxp = 6e-09 toxm = 6.75e-09 toxref = 6.75e-09 17 | +dtox = 7.5e-10 lint = 4.625e-09 18 | +vth0 = -1.414 k1 = 1.515 u0 = 0.00589 vsat = 70000 19 | +rdsw = 155 ndep = 1.88e+18 xj = 1.26e-08 20 | 21 | *secondary parameters 22 | +ll = 0 wl = 0 lln = 1 wln = 1 23 | +lw = 0 ww = 0 lwn = 1 wwn = 1 24 | +lwl = 0 wwl = 0 xpart = 0 25 | +k2 = -0.01 k3 = 0 26 | +k3b = 0 w0 = 2.5e-006 dvt0 = 1 dvt1 = 2 27 | +dvt2 = -0.032 dvt0w = 0 dvt1w = 0 dvt2w = 0 28 | +dsub = 0.1 minv = 0.05 voffl = 0 dvtp0 = 1e-009 29 | +dvtp1 = 0.05 lpe0 = 0 lpeb = 0 30 | +ngate = 2e+020 nsd = 2e+020 phin = 0 31 | +cdsc = 0.000 cdscb = 0 cdscd = 0 cit = 0 32 | +voff = -0.126 etab = 0 33 | +vfb = 0.55 ua = 2.0e-009 ub = 0.5e-018 34 | +uc = 0 a0 = 1.0 ags = 1e-020 35 | +a1 = 0 a2 = 1 b0 = -1e-020 b1 = 0 36 | +keta = -0.047 dwg = 0 dwb = 0 pclm = 0.12 37 | +pdiblc1 = 0.001 pdiblc2 = 0.001 pdiblcb = 3.4e-008 drout = 0.56 38 | +pvag = 1e-020 delta = 0.01 pscbe1 = 8.14e+008 pscbe2 = 9.58e-007 39 | +fprout = 0.2 pdits = 0.08 pditsd = 0.23 pditsl = 2.3e+006 40 | +rsh = 5 rsw = 85 rdw = 85 41 | +rdswmin = 0 rdwmin = 0 rswmin = 0 prwg = 3.22e-008 42 | +prwb = 6.8e-011 wr = 1 alpha0 = 0.074 alpha1 = 0.005 43 | +beta0 = 30 agidl = 0.0002 bgidl = 2.1e+009 cgidl = 0.0002 44 | +egidl = 0.8 45 | 46 | +aigbacc = 0.012 bigbacc = 0.0028 cigbacc = 0.002 47 | +nigbacc = 1 aigbinv = 0.014 bigbinv = 0.004 cigbinv = 0.004 48 | +eigbinv = 1.1 nigbinv = 3 aigc = 0.69 bigc = 0.0012 49 | +cigc = 0.0008 aigsd = 0.0087 bigsd = 0.0012 cigsd = 0.0008 50 | +nigc = 1 poxedge = 1 pigcd = 1 ntox = 1 51 | 52 | +xrcrg1 = 12 xrcrg2 = 5 53 | +cgbo = 2.56e-011 cgdl = 2.653e-10 54 | +cgsl = 2.653e-10 ckappas = 0.03 ckappad = 0.03 acde = 1 55 | +moin = 15 noff = 0.9 voffcv = 0.02 56 | 57 | +kt1 = -0.11 kt1l = 0 kt2 = 0.022 ute = -1.5 58 | +ua1 = 4.31e-009 ub1 = 7.61e-018 uc1 = -5.6e-011 prt = 0 59 | +at = 33000 60 | 61 | +fnoimod = 1 tnoimod = 0 62 | 63 | +jss = 0.0001 jsws = 1e-011 jswgs = 1e-010 njs = 1 64 | +ijthsfwd= 0.01 ijthsrev= 0.001 bvs = 10 xjbvs = 1 65 | +jsd = 0.0001 jswd = 1e-011 jswgd = 1e-010 njd = 1 66 | +ijthdfwd= 0.01 ijthdrev= 0.001 bvd = 10 xjbvd = 1 67 | +pbs = 1 cjs = 0.0005 mjs = 0.5 pbsws = 1 68 | +cjsws = 5e-010 mjsws = 0.33 pbswgs = 1 cjswgs = 3e-010 69 | +mjswgs = 0.33 pbd = 1 cjd = 0.0005 mjd = 0.5 70 | +pbswd = 1 cjswd = 5e-010 mjswd = 0.33 pbswgd = 1 71 | +cjswgd = 5e-010 mjswgd = 0.33 tpb = 0.005 tcj = 0.001 72 | +tpbsw = 0.005 tcjsw = 0.001 tpbswg = 0.005 tcjswg = 0.001 73 | +xtis = 3 xtid = 3 74 | 75 | +dmcg = 0e-006 dmci = 0e-006 dmdg = 0e-006 dmcgt = 0e-007 76 | +dwj = 0.0e-008 xgw = 0e-007 xgl = 0e-008 77 | 78 | +rshg = 0.4 gbmin = 1e-010 rbpb = 5 rbpd = 15 79 | +rbps = 15 rbdb = 15 rbsb = 15 ngcon = 1 80 | 81 | 82 | 83 | -------------------------------------------------------------------------------- /FreePDK45/tran_models/models_ss/PMOS_THKOX.inc: -------------------------------------------------------------------------------- 1 | * Customized PTM 45 PMOS: ss 2 | 3 | .model PMOS_THKOX pmos level = 54 4 | 5 | +version = 4.0 binunit = 1 paramchk= 1 mobmod = 0 6 | +capmod = 2 igcmod = 1 igbmod = 1 geomod = 1 7 | +diomod = 1 rdsmod = 0 rbodymod= 1 rgatemod= 1 8 | +permod = 1 acnqsmod= 0 trnqsmod= 0 9 | 10 | * parameters related to the technology node 11 | +tnom = 27 epsrox = 3.9 12 | +eta0 = 0.0049 nfactor = 2.1 wint = 5e-09 13 | +cgso = 1.1e-10 cgdo = 1.1e-10 xl = -2e-08 14 | 15 | * parameters customized by the user 16 | +toxe = 6.75e-09 toxp = 6e-09 toxm = 6.75e-09 toxref = 6.75e-09 17 | +dtox = 7.5e-10 lint = 2.875e-09 18 | +vth0 = -1.471 k1 = 1.568 u0 = 0.00555 vsat = 70000 19 | +rdsw = 155 ndep = 1.94e+18 xj = 1.54e-08 20 | 21 | *secondary parameters 22 | +ll = 0 wl = 0 lln = 1 wln = 1 23 | +lw = 0 ww = 0 lwn = 1 wwn = 1 24 | +lwl = 0 wwl = 0 xpart = 0 25 | +k2 = -0.01 k3 = 0 26 | +k3b = 0 w0 = 2.5e-006 dvt0 = 1 dvt1 = 2 27 | +dvt2 = -0.032 dvt0w = 0 dvt1w = 0 dvt2w = 0 28 | +dsub = 0.1 minv = 0.05 voffl = 0 dvtp0 = 1e-009 29 | +dvtp1 = 0.05 lpe0 = 0 lpeb = 0 30 | +ngate = 2e+020 nsd = 2e+020 phin = 0 31 | +cdsc = 0.000 cdscb = 0 cdscd = 0 cit = 0 32 | +voff = -0.126 etab = 0 33 | +vfb = 0.55 ua = 2.0e-009 ub = 0.5e-018 34 | +uc = 0 a0 = 1.0 ags = 1e-020 35 | +a1 = 0 a2 = 1 b0 = -1e-020 b1 = 0 36 | +keta = -0.047 dwg = 0 dwb = 0 pclm = 0.12 37 | +pdiblc1 = 0.001 pdiblc2 = 0.001 pdiblcb = 3.4e-008 drout = 0.56 38 | +pvag = 1e-020 delta = 0.01 pscbe1 = 8.14e+008 pscbe2 = 9.58e-007 39 | +fprout = 0.2 pdits = 0.08 pditsd = 0.23 pditsl = 2.3e+006 40 | +rsh = 5 rsw = 85 rdw = 85 41 | +rdswmin = 0 rdwmin = 0 rswmin = 0 prwg = 3.22e-008 42 | +prwb = 6.8e-011 wr = 1 alpha0 = 0.074 alpha1 = 0.005 43 | +beta0 = 30 agidl = 0.0002 bgidl = 2.1e+009 cgidl = 0.0002 44 | +egidl = 0.8 45 | 46 | +aigbacc = 0.012 bigbacc = 0.0028 cigbacc = 0.002 47 | +nigbacc = 1 aigbinv = 0.014 bigbinv = 0.004 cigbinv = 0.004 48 | +eigbinv = 1.1 nigbinv = 3 aigc = 0.69 bigc = 0.0012 49 | +cigc = 0.0008 aigsd = 0.0087 bigsd = 0.0012 cigsd = 0.0008 50 | +nigc = 1 poxedge = 1 pigcd = 1 ntox = 1 51 | 52 | +xrcrg1 = 12 xrcrg2 = 5 53 | +cgbo = 2.56e-011 cgdl = 2.653e-10 54 | +cgsl = 2.653e-10 ckappas = 0.03 ckappad = 0.03 acde = 1 55 | +moin = 15 noff = 0.9 voffcv = 0.02 56 | 57 | +kt1 = -0.11 kt1l = 0 kt2 = 0.022 ute = -1.5 58 | +ua1 = 4.31e-009 ub1 = 7.61e-018 uc1 = -5.6e-011 prt = 0 59 | +at = 33000 60 | 61 | +fnoimod = 1 tnoimod = 0 62 | 63 | +jss = 0.0001 jsws = 1e-011 jswgs = 1e-010 njs = 1 64 | +ijthsfwd= 0.01 ijthsrev= 0.001 bvs = 10 xjbvs = 1 65 | +jsd = 0.0001 jswd = 1e-011 jswgd = 1e-010 njd = 1 66 | +ijthdfwd= 0.01 ijthdrev= 0.001 bvd = 10 xjbvd = 1 67 | +pbs = 1 cjs = 0.0005 mjs = 0.5 pbsws = 1 68 | +cjsws = 5e-010 mjsws = 0.33 pbswgs = 1 cjswgs = 3e-010 69 | +mjswgs = 0.33 pbd = 1 cjd = 0.0005 mjd = 0.5 70 | +pbswd = 1 cjswd = 5e-010 mjswd = 0.33 pbswgd = 1 71 | +cjswgd = 5e-010 mjswgd = 0.33 tpb = 0.005 tcj = 0.001 72 | +tpbsw = 0.005 tcjsw = 0.001 tpbswg = 0.005 tcjswg = 0.001 73 | +xtis = 3 xtid = 3 74 | 75 | +dmcg = 0e-006 dmci = 0e-006 dmdg = 0e-006 dmcgt = 0e-007 76 | +dwj = 0.0e-008 xgw = 0e-007 xgl = 0e-008 77 | 78 | +rshg = 0.4 gbmin = 1e-010 rbpb = 5 rbpd = 15 79 | +rbps = 15 rbdb = 15 rbsb = 15 ngcon = 1 80 | 81 | 82 | 83 | -------------------------------------------------------------------------------- /FreePDK45/tran_models/models_ff/NMOS_THKOX.inc: -------------------------------------------------------------------------------- 1 | * Customized PTM 45 NMOS: ff 2 | 3 | .model NMOS_THKOX nmos level = 54 4 | 5 | +version = 4.0 binunit = 1 paramchk= 1 mobmod = 0 6 | +capmod = 2 igcmod = 1 igbmod = 1 geomod = 1 7 | +diomod = 1 rdsmod = 0 rbodymod= 1 rgatemod= 1 8 | +permod = 1 acnqsmod= 0 trnqsmod= 0 9 | 10 | * parameters related to the technology node 11 | +tnom = 27 epsrox = 3.9 12 | +eta0 = 0.0049 nfactor = 2.1 wint = 5e-09 13 | +cgso = 1.1e-10 cgdo = 1.1e-10 xl = -2e-08 14 | 15 | * parameters customized by the user 16 | +toxe = 6.65e-09 toxp = 6e-09 toxm = 6.65e-09 toxref = 6.65e-09 17 | +dtox = 6.5e-10 lint = 4.625e-09 18 | +vth0 = 1.474 k1 = 1.569 u0 = 0.05404 vsat = 147390 19 | +rdsw = 155 ndep = 2.08e+18 xj = 1.26e-08 20 | 21 | * secondary parameters 22 | +ll = 0 wl = 0 lln = 1 wln = 1 23 | +lw = 0 ww = 0 lwn = 1 wwn = 1 24 | +lwl = 0 wwl = 0 xpart = 0 25 | +k2 = 0.01 k3 = 0 26 | +k3b = 0 w0 = 2.5e-006 dvt0 = 1 dvt1 = 2 27 | +dvt2 = -0.032 dvt0w = 0 dvt1w = 0 dvt2w = 0 28 | +dsub = 0.1 minv = 0.05 voffl = 0 dvtp0 = 1.0e-009 29 | +dvtp1 = 0.1 lpe0 = 0 lpeb = 0 30 | +ngate = 2e+020 nsd = 2e+020 phin = 0 31 | +cdsc = 0.000 cdscb = 0 cdscd = 0 cit = 0 32 | +voff = -0.13 etab = 0 33 | +vfb = -0.55 ua = 6e-010 ub = 1.2e-018 34 | +uc = 0 a0 = 1.0 ags = 1e-020 35 | +a1 = 0 a2 = 1.0 b0 = 0 b1 = 0 36 | +keta = 0.04 dwg = 0 dwb = 0 pclm = 0.04 37 | +pdiblc1 = 0.001 pdiblc2 = 0.001 pdiblcb = -0.005 drout = 0.5 38 | +pvag = 1e-020 delta = 0.01 pscbe1 = 8.14e+008 pscbe2 = 1e-007 39 | +fprout = 0.2 pdits = 0.08 pditsd = 0.23 pditsl = 2.3e+006 40 | +rsh = 5 rsw = 85 rdw = 85 41 | +rdswmin = 0 rdwmin = 0 rswmin = 0 prwg = 0 42 | +prwb = 6.8e-011 wr = 1 alpha0 = 0.074 alpha1 = 0.005 43 | +beta0 = 30 agidl = 0.0002 bgidl = 2.1e+009 cgidl = 0.0002 44 | +egidl = 0.8 45 | 46 | +aigbacc = 0.012 bigbacc = 0.0028 cigbacc = 0.002 47 | +nigbacc = 1 aigbinv = 0.014 bigbinv = 0.004 cigbinv = 0.004 48 | +eigbinv = 1.1 nigbinv = 3 aigc = 0.012 bigc = 0.0028 49 | +cigc = 0.002 aigsd = 0.012 bigsd = 0.0028 cigsd = 0.002 50 | +nigc = 1 poxedge = 1 pigcd = 1 ntox = 1 51 | 52 | +xrcrg1 = 12 xrcrg2 = 5 53 | +cgbo = 2.56e-011 cgdl = 2.653e-10 54 | +cgsl = 2.653e-10 ckappas = 0.03 ckappad = 0.03 acde = 1 55 | +moin = 15 noff = 0.9 voffcv = 0.02 56 | 57 | +kt1 = -0.11 kt1l = 0 kt2 = 0.022 ute = -1.5 58 | +ua1 = 4.31e-009 ub1 = 7.61e-018 uc1 = -5.6e-011 prt = 0 59 | +at = 33000 60 | 61 | +fnoimod = 1 tnoimod = 0 62 | 63 | +jss = 0.0001 jsws = 1e-011 jswgs = 1e-010 njs = 1 64 | +ijthsfwd= 0.01 ijthsrev= 0.001 bvs = 10 xjbvs = 1 65 | +jsd = 0.0001 jswd = 1e-011 jswgd = 1e-010 njd = 1 66 | +ijthdfwd= 0.01 ijthdrev= 0.001 bvd = 10 xjbvd = 1 67 | +pbs = 1 cjs = 0.0005 mjs = 0.5 pbsws = 1 68 | +cjsws = 5e-010 mjsws = 0.33 pbswgs = 1 cjswgs = 3e-010 69 | +mjswgs = 0.33 pbd = 1 cjd = 0.0005 mjd = 0.5 70 | +pbswd = 1 cjswd = 5e-010 mjswd = 0.33 pbswgd = 1 71 | +cjswgd = 5e-010 mjswgd = 0.33 tpb = 0.005 tcj = 0.001 72 | +tpbsw = 0.005 tcjsw = 0.001 tpbswg = 0.005 tcjswg = 0.001 73 | +xtis = 3 xtid = 3 74 | 75 | +dmcg = 0e-006 dmci = 0e-006 dmdg = 0e-006 dmcgt = 0e-007 76 | +dwj = 0.0e-008 xgw = 0e-007 xgl = 0e-008 77 | 78 | +rshg = 0.4 gbmin = 1e-010 rbpb = 5 rbpd = 15 79 | +rbps = 15 rbdb = 15 rbsb = 15 ngcon = 1 80 | -------------------------------------------------------------------------------- /FreePDK45/tran_models/models_nom/NMOS_THKOX.inc: -------------------------------------------------------------------------------- 1 | * Customized PTM 45 NMOS NMOS_THKOX 2 | 3 | .model NMOS_THKOX nmos level = 54 4 | 5 | +version = 4.0 binunit = 1 paramchk= 1 mobmod = 0 6 | +capmod = 2 igcmod = 1 igbmod = 1 geomod = 1 7 | +diomod = 1 rdsmod = 0 rbodymod= 1 rgatemod= 1 8 | +permod = 1 acnqsmod= 0 trnqsmod= 0 9 | 10 | * parameters related to the technology node 11 | +tnom = 27 epsrox = 3.9 12 | +eta0 = 0.0049 nfactor = 2.1 wint = 5e-09 13 | +cgso = 1.1e-10 cgdo = 1.1e-10 xl = -2e-08 14 | 15 | * parameters customized by the user 16 | +toxe = 6.65e-09 toxp = 6e-09 toxm = 6.65e-09 toxref = 6.65e-09 17 | +dtox = 6.5e-10 lint = 3.75e-09 18 | +vth0 = 1.507 k1 = 1.6 u0 = 0.05323 vsat = 147390 19 | +rdsw = 155 ndep = 2.08e+18 xj = 1.4e-08 20 | 21 | * secondary parameters 22 | +ll = 0 wl = 0 lln = 1 wln = 1 23 | +lw = 0 ww = 0 lwn = 1 wwn = 1 24 | +lwl = 0 wwl = 0 xpart = 0 25 | +k2 = 0.01 k3 = 0 26 | +k3b = 0 w0 = 2.5e-006 dvt0 = 1 dvt1 = 2 27 | +dvt2 = -0.032 dvt0w = 0 dvt1w = 0 dvt2w = 0 28 | +dsub = 0.1 minv = 0.05 voffl = 0 dvtp0 = 1.0e-009 29 | +dvtp1 = 0.1 lpe0 = 0 lpeb = 0 30 | +ngate = 2e+020 nsd = 2e+020 phin = 0 31 | +cdsc = 0.000 cdscb = 0 cdscd = 0 cit = 0 32 | +voff = -0.13 etab = 0 33 | +vfb = -0.55 ua = 6e-010 ub = 1.2e-018 34 | +uc = 0 a0 = 1.0 ags = 1e-020 35 | +a1 = 0 a2 = 1.0 b0 = 0 b1 = 0 36 | +keta = 0.04 dwg = 0 dwb = 0 pclm = 0.04 37 | +pdiblc1 = 0.001 pdiblc2 = 0.001 pdiblcb = -0.005 drout = 0.5 38 | +pvag = 1e-020 delta = 0.01 pscbe1 = 8.14e+008 pscbe2 = 1e-007 39 | +fprout = 0.2 pdits = 0.08 pditsd = 0.23 pditsl = 2.3e+006 40 | +rsh = 5 rsw = 85 rdw = 85 41 | +rdswmin = 0 rdwmin = 0 rswmin = 0 prwg = 0 42 | +prwb = 6.8e-011 wr = 1 alpha0 = 0.074 alpha1 = 0.005 43 | +beta0 = 30 agidl = 0.0002 bgidl = 2.1e+009 cgidl = 0.0002 44 | +egidl = 0.8 45 | 46 | +aigbacc = 0.012 bigbacc = 0.0028 cigbacc = 0.002 47 | +nigbacc = 1 aigbinv = 0.014 bigbinv = 0.004 cigbinv = 0.004 48 | +eigbinv = 1.1 nigbinv = 3 aigc = 0.012 bigc = 0.0028 49 | +cigc = 0.002 aigsd = 0.012 bigsd = 0.0028 cigsd = 0.002 50 | +nigc = 1 poxedge = 1 pigcd = 1 ntox = 1 51 | 52 | +xrcrg1 = 12 xrcrg2 = 5 53 | +cgbo = 2.56e-011 cgdl = 2.653e-10 54 | +cgsl = 2.653e-10 ckappas = 0.03 ckappad = 0.03 acde = 1 55 | +moin = 15 noff = 0.9 voffcv = 0.02 56 | 57 | +kt1 = -0.11 kt1l = 0 kt2 = 0.022 ute = -1.5 58 | +ua1 = 4.31e-009 ub1 = 7.61e-018 uc1 = -5.6e-011 prt = 0 59 | +at = 33000 60 | 61 | +fnoimod = 1 tnoimod = 0 62 | 63 | +jss = 0.0001 jsws = 1e-011 jswgs = 1e-010 njs = 1 64 | +ijthsfwd= 0.01 ijthsrev= 0.001 bvs = 10 xjbvs = 1 65 | +jsd = 0.0001 jswd = 1e-011 jswgd = 1e-010 njd = 1 66 | +ijthdfwd= 0.01 ijthdrev= 0.001 bvd = 10 xjbvd = 1 67 | +pbs = 1 cjs = 0.0005 mjs = 0.5 pbsws = 1 68 | +cjsws = 5e-010 mjsws = 0.33 pbswgs = 1 cjswgs = 3e-010 69 | +mjswgs = 0.33 pbd = 1 cjd = 0.0005 mjd = 0.5 70 | +pbswd = 1 cjswd = 5e-010 mjswd = 0.33 pbswgd = 1 71 | +cjswgd = 5e-010 mjswgd = 0.33 tpb = 0.005 tcj = 0.001 72 | +tpbsw = 0.005 tcjsw = 0.001 tpbswg = 0.005 tcjswg = 0.001 73 | +xtis = 3 xtid = 3 74 | 75 | +dmcg = 0e-006 dmci = 0e-006 dmdg = 0e-006 dmcgt = 0e-007 76 | +dwj = 0.0e-008 xgw = 0e-007 xgl = 0e-008 77 | 78 | +rshg = 0.4 gbmin = 1e-010 rbpb = 5 rbpd = 15 79 | +rbps = 15 rbdb = 15 rbsb = 15 ngcon = 1 80 | -------------------------------------------------------------------------------- /FreePDK45/tran_models/models_nom/PMOS_THKOX.inc: -------------------------------------------------------------------------------- 1 | * Customized PTM 45 PMOS PMOS_THKOX 2 | 3 | .model PMOS_THKOX pmos level = 54 4 | 5 | +version = 4.0 binunit = 1 paramchk= 1 mobmod = 0 6 | +capmod = 2 igcmod = 1 igbmod = 1 geomod = 1 7 | +diomod = 1 rdsmod = 0 rbodymod= 1 rgatemod= 1 8 | +permod = 1 acnqsmod= 0 trnqsmod= 0 9 | 10 | * parameters related to the technology node 11 | +tnom = 27 epsrox = 3.9 12 | +eta0 = 0.0049 nfactor = 2.1 wint = 5e-09 13 | +cgso = 1.1e-10 cgdo = 1.1e-10 xl = -2e-08 14 | 15 | * parameters customized by the user 16 | +toxe = 6.75e-09 toxp = 6e-09 toxm = 6.75e-09 toxref = 6.75e-09 17 | +dtox = 7.5e-10 lint = 3.75e-09 18 | +vth0 = -1.445 k1 = 1.544 u0 = 0.00571 vsat = 70000 19 | +rdsw = 155 ndep = 1.88e+18 xj = 1.4e-08 20 | 21 | *secondary parameters 22 | +ll = 0 wl = 0 lln = 1 wln = 1 23 | +lw = 0 ww = 0 lwn = 1 wwn = 1 24 | +lwl = 0 wwl = 0 xpart = 0 25 | +k2 = -0.01 k3 = 0 26 | +k3b = 0 w0 = 2.5e-006 dvt0 = 1 dvt1 = 2 27 | +dvt2 = -0.032 dvt0w = 0 dvt1w = 0 dvt2w = 0 28 | +dsub = 0.1 minv = 0.05 voffl = 0 dvtp0 = 1e-009 29 | +dvtp1 = 0.05 lpe0 = 0 lpeb = 0 30 | +ngate = 2e+020 nsd = 2e+020 phin = 0 31 | +cdsc = 0.000 cdscb = 0 cdscd = 0 cit = 0 32 | +voff = -0.126 etab = 0 33 | +vfb = 0.55 ua = 2.0e-009 ub = 0.5e-018 34 | +uc = 0 a0 = 1.0 ags = 1e-020 35 | +a1 = 0 a2 = 1 b0 = -1e-020 b1 = 0 36 | +keta = -0.047 dwg = 0 dwb = 0 pclm = 0.12 37 | +pdiblc1 = 0.001 pdiblc2 = 0.001 pdiblcb = 3.4e-008 drout = 0.56 38 | +pvag = 1e-020 delta = 0.01 pscbe1 = 8.14e+008 pscbe2 = 9.58e-007 39 | +fprout = 0.2 pdits = 0.08 pditsd = 0.23 pditsl = 2.3e+006 40 | +rsh = 5 rsw = 85 rdw = 85 41 | +rdswmin = 0 rdwmin = 0 rswmin = 0 prwg = 3.22e-008 42 | +prwb = 6.8e-011 wr = 1 alpha0 = 0.074 alpha1 = 0.005 43 | +beta0 = 30 agidl = 0.0002 bgidl = 2.1e+009 cgidl = 0.0002 44 | +egidl = 0.8 45 | 46 | +aigbacc = 0.012 bigbacc = 0.0028 cigbacc = 0.002 47 | +nigbacc = 1 aigbinv = 0.014 bigbinv = 0.004 cigbinv = 0.004 48 | +eigbinv = 1.1 nigbinv = 3 aigc = 0.69 bigc = 0.0012 49 | +cigc = 0.0008 aigsd = 0.0087 bigsd = 0.0012 cigsd = 0.0008 50 | +nigc = 1 poxedge = 1 pigcd = 1 ntox = 1 51 | 52 | +xrcrg1 = 12 xrcrg2 = 5 53 | +cgbo = 2.56e-011 cgdl = 2.653e-10 54 | +cgsl = 2.653e-10 ckappas = 0.03 ckappad = 0.03 acde = 1 55 | +moin = 15 noff = 0.9 voffcv = 0.02 56 | 57 | +kt1 = -0.11 kt1l = 0 kt2 = 0.022 ute = -1.5 58 | +ua1 = 4.31e-009 ub1 = 7.61e-018 uc1 = -5.6e-011 prt = 0 59 | +at = 33000 60 | 61 | +fnoimod = 1 tnoimod = 0 62 | 63 | +jss = 0.0001 jsws = 1e-011 jswgs = 1e-010 njs = 1 64 | +ijthsfwd= 0.01 ijthsrev= 0.001 bvs = 10 xjbvs = 1 65 | +jsd = 0.0001 jswd = 1e-011 jswgd = 1e-010 njd = 1 66 | +ijthdfwd= 0.01 ijthdrev= 0.001 bvd = 10 xjbvd = 1 67 | +pbs = 1 cjs = 0.0005 mjs = 0.5 pbsws = 1 68 | +cjsws = 5e-010 mjsws = 0.33 pbswgs = 1 cjswgs = 3e-010 69 | +mjswgs = 0.33 pbd = 1 cjd = 0.0005 mjd = 0.5 70 | +pbswd = 1 cjswd = 5e-010 mjswd = 0.33 pbswgd = 1 71 | +cjswgd = 5e-010 mjswgd = 0.33 tpb = 0.005 tcj = 0.001 72 | +tpbsw = 0.005 tcjsw = 0.001 tpbswg = 0.005 tcjswg = 0.001 73 | +xtis = 3 xtid = 3 74 | 75 | +dmcg = 0e-006 dmci = 0e-006 dmdg = 0e-006 dmcgt = 0e-007 76 | +dwj = 0.0e-008 xgw = 0e-007 xgl = 0e-008 77 | 78 | +rshg = 0.4 gbmin = 1e-010 rbpb = 5 rbpd = 15 79 | +rbps = 15 rbdb = 15 rbsb = 15 ngcon = 1 80 | 81 | 82 | 83 | -------------------------------------------------------------------------------- /FreePDK45/tran_models/models_ss/NMOS_THKOX.inc: -------------------------------------------------------------------------------- 1 | * Customized PTM 45 NMOS: ss 2 | 3 | .model NMOS_THKOX nmos level = 54 4 | 5 | +version = 4.0 binunit = 1 paramchk= 1 mobmod = 0 6 | +capmod = 2 igcmod = 1 igbmod = 1 geomod = 1 7 | +diomod = 1 rdsmod = 0 rbodymod= 1 rgatemod= 1 8 | +permod = 1 acnqsmod= 0 trnqsmod= 0 9 | 10 | * parameters related to the technology node 11 | +tnom = 27 epsrox = 3.9 12 | +eta0 = 0.0049 nfactor = 2.1 wint = 5e-09 13 | +cgso = 1.1e-10 cgdo = 1.1e-10 xl = -2e-08 14 | 15 | * parameters customized by the user 16 | +toxe = 6.65e-09 toxp = 6e-09 toxm = 6.65e-09 toxref = 6.65e-09 17 | +dtox = 6.5e-10 lint = 2.875e-09 18 | +vth0 = 1.536 k1 = 1.626 u0 = 0.05255 vsat = 147390 19 | +rdsw = 155 ndep = 2.15e+18 xj = 1.54e-08 20 | 21 | * secondary parameters 22 | +ll = 0 wl = 0 lln = 1 wln = 1 23 | +lw = 0 ww = 0 lwn = 1 wwn = 1 24 | +lwl = 0 wwl = 0 xpart = 0 25 | +k2 = 0.01 k3 = 0 26 | +k3b = 0 w0 = 2.5e-006 dvt0 = 1 dvt1 = 2 27 | +dvt2 = -0.032 dvt0w = 0 dvt1w = 0 dvt2w = 0 28 | +dsub = 0.1 minv = 0.05 voffl = 0 dvtp0 = 1.0e-009 29 | +dvtp1 = 0.1 lpe0 = 0 lpeb = 0 30 | +ngate = 2e+020 nsd = 2e+020 phin = 0 31 | +cdsc = 0.000 cdscb = 0 cdscd = 0 cit = 0 32 | +voff = -0.13 etab = 0 33 | +vfb = -0.55 ua = 6e-010 ub = 1.2e-018 34 | +uc = 0 a0 = 1.0 ags = 1e-020 35 | +a1 = 0 a2 = 1.0 b0 = 0 b1 = 0 36 | +keta = 0.04 dwg = 0 dwb = 0 pclm = 0.04 37 | +pdiblc1 = 0.001 pdiblc2 = 0.001 pdiblcb = -0.005 drout = 0.5 38 | +pvag = 1e-020 delta = 0.01 pscbe1 = 8.14e+008 pscbe2 = 1e-007 39 | +fprout = 0.2 pdits = 0.08 pditsd = 0.23 pditsl = 2.3e+006 40 | +rsh = 5 rsw = 85 rdw = 85 41 | +rdswmin = 0 rdwmin = 0 rswmin = 0 prwg = 0 42 | +prwb = 6.8e-011 wr = 1 alpha0 = 0.074 alpha1 = 0.005 43 | +beta0 = 30 agidl = 0.0002 bgidl = 2.1e+009 cgidl = 0.0002 44 | +egidl = 0.8 45 | 46 | +aigbacc = 0.012 bigbacc = 0.0028 cigbacc = 0.002 47 | +nigbacc = 1 aigbinv = 0.014 bigbinv = 0.004 cigbinv = 0.004 48 | +eigbinv = 1.1 nigbinv = 3 aigc = 0.012 bigc = 0.0028 49 | +cigc = 0.002 aigsd = 0.012 bigsd = 0.0028 cigsd = 0.002 50 | +nigc = 1 poxedge = 1 pigcd = 1 ntox = 1 51 | 52 | +xrcrg1 = 12 xrcrg2 = 5 53 | +cgbo = 2.56e-011 cgdl = 2.653e-10 54 | +cgsl = 2.653e-10 ckappas = 0.03 ckappad = 0.03 acde = 1 55 | +moin = 15 noff = 0.9 voffcv = 0.02 56 | 57 | +kt1 = -0.11 kt1l = 0 kt2 = 0.022 ute = -1.5 58 | +ua1 = 4.31e-009 ub1 = 7.61e-018 uc1 = -5.6e-011 prt = 0 59 | +at = 33000 60 | 61 | +fnoimod = 1 tnoimod = 0 62 | 63 | +jss = 0.0001 jsws = 1e-011 jswgs = 1e-010 njs = 1 64 | +ijthsfwd= 0.01 ijthsrev= 0.001 bvs = 10 xjbvs = 1 65 | +jsd = 0.0001 jswd = 1e-011 jswgd = 1e-010 njd = 1 66 | +ijthdfwd= 0.01 ijthdrev= 0.001 bvd = 10 xjbvd = 1 67 | +pbs = 1 cjs = 0.0005 mjs = 0.5 pbsws = 1 68 | +cjsws = 5e-010 mjsws = 0.33 pbswgs = 1 cjswgs = 3e-010 69 | +mjswgs = 0.33 pbd = 1 cjd = 0.0005 mjd = 0.5 70 | +pbswd = 1 cjswd = 5e-010 mjswd = 0.33 pbswgd = 1 71 | +cjswgd = 5e-010 mjswgd = 0.33 tpb = 0.005 tcj = 0.001 72 | +tpbsw = 0.005 tcjsw = 0.001 tpbswg = 0.005 tcjswg = 0.001 73 | +xtis = 3 xtid = 3 74 | 75 | +dmcg = 0e-006 dmci = 0e-006 dmdg = 0e-006 dmcgt = 0e-007 76 | +dwj = 0.0e-008 xgw = 0e-007 xgl = 0e-008 77 | 78 | +rshg = 0.4 gbmin = 1e-010 rbpb = 5 rbpd = 15 79 | +rbps = 15 rbdb = 15 rbsb = 15 ngcon = 1 80 | -------------------------------------------------------------------------------- /FreePDK45/tran_models/models_ff/NMOS_VTG.inc: -------------------------------------------------------------------------------- 1 | * Customized PTM 45 NMOS ff 2 | 3 | .model NMOS_VTG nmos level = 54 4 | 5 | * parameters related to the technology node 6 | +tnom = 27 epsrox = 3.9 7 | +eta0 = 0.006 nfactor = 2.1 wint = 5e-09 8 | +cgso = 1.1e-10 cgdo = 1.1e-10 xl = -2e-08 9 | 10 | * parameters customized by the user 11 | +toxe = 1.1e-09 toxp = 1e-09 toxm = 1.1e-09 toxref = 1.1e-09 12 | +dtox = 0.1e-09 lint = 4.275e-09 13 | +vth0 = 0.3856 k1 = 0.4 u0 = 0.046 vsat = 123000 14 | +rdsw = 155 ndep = 3.4e+18 xj = 1.9e-08 15 | 16 | 17 | 18 | 19 | +version = 4.0 binunit = 1 paramchk= 1 mobmod = 0 20 | +capmod = 2 igcmod = 1 igbmod = 1 geomod = 1 21 | +diomod = 1 rdsmod = 0 rbodymod= 1 rgatemod= 1 22 | +permod = 1 acnqsmod= 0 trnqsmod= 0 23 | 24 | +ll = 0 wl = 0 lln = 1 wln = 1 25 | +lw = 0 ww = 0 lwn = 1 wwn = 1 26 | +lwl = 0 wwl = 0 xpart = 0 27 | 28 | +k2 = 0 k3 = 0 29 | +k3b = 0 w0 = 2.5e-006 dvt0 = 1 dvt1 = 2 30 | +dvt2 = 0 dvt0w = 0 dvt1w = 0 dvt2w = 0 31 | +dsub = 0.1 minv = 0.05 voffl = 0 dvtp0 = 1e-010 32 | +dvtp1 = 0.1 lpe0 = 0 lpeb = 0 33 | +ngate = 3e+20 nsd = 2e+020 phin = 0 34 | +cdsc = 0 cdscb = 0 cdscd = 0 cit = 0 35 | +voff = -0.13 etab = 0 36 | +vfb = -0.55 ua = 6e-010 ub = 1.2e-018 37 | +uc = 0 a0 = 1 ags = 0 38 | +a1 = 0 a2 = 1 b0 = 0 b1 = 0 39 | +keta = 0.04 dwg = 0 dwb = 0 pclm = 0.02 40 | +pdiblc1 = 0.001 pdiblc2 = 0.001 pdiblcb = -0.005 drout = 0.5 41 | +pvag = 1e-020 delta = 0.01 pscbe1 = 8.14e+008 pscbe2 = 1e-007 42 | +fprout = 0.2 pdits = 0.08 pditsd = 0.23 pditsl = 2300000 43 | +rsh = 5 rsw = 80 rdw = 80 44 | +rdswmin = 0 rdwmin = 0 rswmin = 0 prwg = 0 45 | +prwb = 0 wr = 1 alpha0 = 0.074 alpha1 = 0.005 46 | +beta0 = 30 agidl = 0.0002 bgidl = 2.1e+009 cgidl = 0.0002 47 | +egidl = 0.8 aigbacc = 0.012 bigbacc = 0.0028 cigbacc = 0.002 48 | +nigbacc = 1 aigbinv = 0.014 bigbinv = 0.004 cigbinv = 0.004 49 | +eigbinv = 1.1 nigbinv = 3 aigc = 0.02 bigc = 0.0027 50 | +cigc = 0.002 aigsd = 0.02 bigsd = 0.0027 cigsd = 0.002 51 | +nigc = 1 poxedge = 1 pigcd = 1 ntox = 1 52 | +xrcrg1 = 12 xrcrg2 = 5 53 | 54 | +cgbo = 2.56e-011 cgdl = 2.653e-010 55 | +cgsl = 2.653e-010 ckappas = 0.03 ckappad = 0.03 acde = 1 56 | +moin = 15 noff = 0.9 voffcv = 0.02 57 | 58 | +kt1 = -0.11 kt1l = 0 kt2 = 0.022 ute = -1.5 59 | +ua1 = 4.31e-009 ub1 = 7.61e-018 uc1 = -5.6e-011 prt = 0 60 | +at = 33000 61 | 62 | +fnoimod = 1 tnoimod = 0 63 | 64 | +jss = 0.0001 jsws = 1e-011 jswgs = 1e-010 njs = 1 65 | +ijthsfwd= 0.01 ijthsrev= 0.001 bvs = 10 xjbvs = 1 66 | +jsd = 0.0001 jswd = 1e-011 jswgd = 1e-010 njd = 1 67 | +ijthdfwd= 0.01 ijthdrev= 0.001 bvd = 10 xjbvd = 1 68 | +pbs = 1 cjs = 0.0005 mjs = 0.5 pbsws = 1 69 | +cjsws = 5e-010 mjsws = 0.33 pbswgs = 1 cjswgs = 3e-010 70 | +mjswgs = 0.33 pbd = 1 cjd = 0.0005 mjd = 0.5 71 | +pbswd = 1 cjswd = 5e-010 mjswd = 0.33 pbswgd = 1 72 | +cjswgd = 5e-010 mjswgd = 0.33 tpb = 0.005 tcj = 0.001 73 | +tpbsw = 0.005 tcjsw = 0.001 tpbswg = 0.005 tcjswg = 0.001 74 | +xtis = 3 xtid = 3 75 | 76 | +dmcg = 0 dmci = 0 dmdg = 0 dmcgt = 0 77 | +dwj = 0 xgw = 0 xgl = 0 78 | 79 | +rshg = 0.4 gbmin = 1e-010 rbpb = 5 rbpd = 15 80 | +rbps = 15 rbdb = 15 rbsb = 15 ngcon = 1 -------------------------------------------------------------------------------- /FreePDK45/tran_models/models_ff/NMOS_VTL.inc: -------------------------------------------------------------------------------- 1 | * Customized PTM 45 NMOS ff 2 | 3 | .model NMOS_VTL nmos level = 54 4 | 5 | * parameters related to the technology node 6 | +tnom = 27 epsrox = 3.9 7 | +eta0 = 0.006 nfactor = 2.1 wint = 5e-09 8 | +cgso = 1.1e-10 cgdo = 1.1e-10 xl = -2e-08 9 | 10 | * parameters customized by the user 11 | +toxe = 1.1e-09 toxp = 1e-09 toxm = 1.1e-09 toxref = 1.1e-09 12 | +dtox = 0.1e-09 lint = 4.275e-09 13 | +vth0 = 0.297 k1 = 0.4 u0 = 0.046 vsat = 148000 14 | +rdsw = 155 ndep = 3.4e+18 xj = 1.9e-08 15 | 16 | 17 | 18 | 19 | +version = 4.0 binunit = 1 paramchk= 1 mobmod = 0 20 | +capmod = 2 igcmod = 1 igbmod = 1 geomod = 1 21 | +diomod = 1 rdsmod = 0 rbodymod= 1 rgatemod= 1 22 | +permod = 1 acnqsmod= 0 trnqsmod= 0 23 | 24 | +ll = 0 wl = 0 lln = 1 wln = 1 25 | +lw = 0 ww = 0 lwn = 1 wwn = 1 26 | +lwl = 0 wwl = 0 xpart = 0 27 | 28 | +k2 = 0 k3 = 0 29 | +k3b = 0 w0 = 2.5e-006 dvt0 = 1 dvt1 = 2 30 | +dvt2 = 0 dvt0w = 0 dvt1w = 0 dvt2w = 0 31 | +dsub = 0.1 minv = 0.05 voffl = 0 dvtp0 = 1e-010 32 | +dvtp1 = 0.1 lpe0 = 0 lpeb = 0 33 | +ngate = 3e+20 nsd = 2e+020 phin = 0 34 | +cdsc = 0 cdscb = 0 cdscd = 0 cit = 0 35 | +voff = -0.13 etab = 0 36 | +vfb = -0.55 ua = 6e-010 ub = 1.2e-018 37 | +uc = 0 a0 = 1 ags = 0 38 | +a1 = 0 a2 = 1 b0 = 0 b1 = 0 39 | +keta = 0.04 dwg = 0 dwb = 0 pclm = 0.02 40 | +pdiblc1 = 0.001 pdiblc2 = 0.001 pdiblcb = -0.005 drout = 0.5 41 | +pvag = 1e-020 delta = 0.01 pscbe1 = 8.14e+008 pscbe2 = 1e-007 42 | +fprout = 0.2 pdits = 0.08 pditsd = 0.23 pditsl = 2300000 43 | +rsh = 5 rsw = 80 rdw = 80 44 | +rdswmin = 0 rdwmin = 0 rswmin = 0 prwg = 0 45 | +prwb = 0 wr = 1 alpha0 = 0.074 alpha1 = 0.005 46 | +beta0 = 30 agidl = 0.0002 bgidl = 2.1e+009 cgidl = 0.0002 47 | +egidl = 0.8 aigbacc = 0.012 bigbacc = 0.0028 cigbacc = 0.002 48 | +nigbacc = 1 aigbinv = 0.014 bigbinv = 0.004 cigbinv = 0.004 49 | +eigbinv = 1.1 nigbinv = 3 aigc = 0.02 bigc = 0.0027 50 | +cigc = 0.002 aigsd = 0.02 bigsd = 0.0027 cigsd = 0.002 51 | +nigc = 1 poxedge = 1 pigcd = 1 ntox = 1 52 | +xrcrg1 = 12 xrcrg2 = 5 53 | 54 | +cgbo = 2.56e-011 cgdl = 2.653e-010 55 | +cgsl = 2.653e-010 ckappas = 0.03 ckappad = 0.03 acde = 1 56 | +moin = 15 noff = 0.9 voffcv = 0.02 57 | 58 | +kt1 = -0.11 kt1l = 0 kt2 = 0.022 ute = -1.5 59 | +ua1 = 4.31e-009 ub1 = 7.61e-018 uc1 = -5.6e-011 prt = 0 60 | +at = 33000 61 | 62 | +fnoimod = 1 tnoimod = 0 63 | 64 | +jss = 0.0001 jsws = 1e-011 jswgs = 1e-010 njs = 1 65 | +ijthsfwd= 0.01 ijthsrev= 0.001 bvs = 10 xjbvs = 1 66 | +jsd = 0.0001 jswd = 1e-011 jswgd = 1e-010 njd = 1 67 | +ijthdfwd= 0.01 ijthdrev= 0.001 bvd = 10 xjbvd = 1 68 | +pbs = 1 cjs = 0.0005 mjs = 0.5 pbsws = 1 69 | +cjsws = 5e-010 mjsws = 0.33 pbswgs = 1 cjswgs = 3e-010 70 | +mjswgs = 0.33 pbd = 1 cjd = 0.0005 mjd = 0.5 71 | +pbswd = 1 cjswd = 5e-010 mjswd = 0.33 pbswgd = 1 72 | +cjswgd = 5e-010 mjswgd = 0.33 tpb = 0.005 tcj = 0.001 73 | +tpbsw = 0.005 tcjsw = 0.001 tpbswg = 0.005 tcjswg = 0.001 74 | +xtis = 3 xtid = 3 75 | 76 | +dmcg = 0 dmci = 0 dmdg = 0 dmcgt = 0 77 | +dwj = 0 xgw = 0 xgl = 0 78 | 79 | +rshg = 0.4 gbmin = 1e-010 rbpb = 5 rbpd = 15 80 | +rbps = 15 rbdb = 15 rbsb = 15 ngcon = 1 -------------------------------------------------------------------------------- /FreePDK45/tran_models/models_nom/NMOS_VTG.inc: -------------------------------------------------------------------------------- 1 | * Customized PTM 45 NMOS nom 2 | 3 | .model NMOS_VTG nmos level = 54 4 | 5 | * parameters related to the technology node 6 | +tnom = 27 epsrox = 3.9 7 | +eta0 = 0.006 nfactor = 2.1 wint = 5e-09 8 | +cgso = 1.1e-10 cgdo = 1.1e-10 xl = -2e-08 9 | 10 | * parameters customized by the user 11 | +toxe = 1.14e-09 toxp = 1e-09 toxm = 1.14e-09 toxref = 1.14e-09 12 | +dtox = 0.14e-09 lint = 3.75e-09 13 | +vth0 = 0.4106 k1 = 0.4 u0 = 0.045 vsat = 123000 14 | +rdsw = 155 ndep = 3.4e+18 xj = 1.98e-08 15 | 16 | 17 | 18 | 19 | +version = 4.0 binunit = 1 paramchk= 1 mobmod = 0 20 | +capmod = 2 igcmod = 1 igbmod = 1 geomod = 1 21 | +diomod = 1 rdsmod = 0 rbodymod= 1 rgatemod= 1 22 | +permod = 1 acnqsmod= 0 trnqsmod= 0 23 | 24 | +ll = 0 wl = 0 lln = 1 wln = 1 25 | +lw = 0 ww = 0 lwn = 1 wwn = 1 26 | +lwl = 0 wwl = 0 xpart = 0 27 | 28 | +k2 = 0 k3 = 0 29 | +k3b = 0 w0 = 2.5e-006 dvt0 = 1 dvt1 = 2 30 | +dvt2 = 0 dvt0w = 0 dvt1w = 0 dvt2w = 0 31 | +dsub = 0.1 minv = 0.05 voffl = 0 dvtp0 = 1e-010 32 | +dvtp1 = 0.1 lpe0 = 0 lpeb = 0 33 | +ngate = 3e+20 nsd = 2e+020 phin = 0 34 | +cdsc = 0 cdscb = 0 cdscd = 0 cit = 0 35 | +voff = -0.13 etab = 0 36 | +vfb = -0.55 ua = 6e-010 ub = 1.2e-018 37 | +uc = 0 a0 = 1 ags = 0 38 | +a1 = 0 a2 = 1 b0 = 0 b1 = 0 39 | +keta = 0.04 dwg = 0 dwb = 0 pclm = 0.02 40 | +pdiblc1 = 0.001 pdiblc2 = 0.001 pdiblcb = -0.005 drout = 0.5 41 | +pvag = 1e-020 delta = 0.01 pscbe1 = 8.14e+008 pscbe2 = 1e-007 42 | +fprout = 0.2 pdits = 0.08 pditsd = 0.23 pditsl = 2300000 43 | +rsh = 5 rsw = 80 rdw = 80 44 | +rdswmin = 0 rdwmin = 0 rswmin = 0 prwg = 0 45 | +prwb = 0 wr = 1 alpha0 = 0.074 alpha1 = 0.005 46 | +beta0 = 30 agidl = 0.0002 bgidl = 2.1e+009 cgidl = 0.0002 47 | +egidl = 0.8 aigbacc = 0.012 bigbacc = 0.0028 cigbacc = 0.002 48 | +nigbacc = 1 aigbinv = 0.014 bigbinv = 0.004 cigbinv = 0.004 49 | +eigbinv = 1.1 nigbinv = 3 aigc = 0.02 bigc = 0.0027 50 | +cigc = 0.002 aigsd = 0.02 bigsd = 0.0027 cigsd = 0.002 51 | +nigc = 1 poxedge = 1 pigcd = 1 ntox = 1 52 | +xrcrg1 = 12 xrcrg2 = 5 53 | 54 | +cgbo = 2.56e-011 cgdl = 2.653e-010 55 | +cgsl = 2.653e-010 ckappas = 0.03 ckappad = 0.03 acde = 1 56 | +moin = 15 noff = 0.9 voffcv = 0.02 57 | 58 | +kt1 = -0.11 kt1l = 0 kt2 = 0.022 ute = -1.5 59 | +ua1 = 4.31e-009 ub1 = 7.61e-018 uc1 = -5.6e-011 prt = 0 60 | +at = 33000 61 | 62 | +fnoimod = 1 tnoimod = 0 63 | 64 | +jss = 0.0001 jsws = 1e-011 jswgs = 1e-010 njs = 1 65 | +ijthsfwd= 0.01 ijthsrev= 0.001 bvs = 10 xjbvs = 1 66 | +jsd = 0.0001 jswd = 1e-011 jswgd = 1e-010 njd = 1 67 | +ijthdfwd= 0.01 ijthdrev= 0.001 bvd = 10 xjbvd = 1 68 | +pbs = 1 cjs = 0.0005 mjs = 0.5 pbsws = 1 69 | +cjsws = 5e-010 mjsws = 0.33 pbswgs = 1 cjswgs = 3e-010 70 | +mjswgs = 0.33 pbd = 1 cjd = 0.0005 mjd = 0.5 71 | +pbswd = 1 cjswd = 5e-010 mjswd = 0.33 pbswgd = 1 72 | +cjswgd = 5e-010 mjswgd = 0.33 tpb = 0.005 tcj = 0.001 73 | +tpbsw = 0.005 tcjsw = 0.001 tpbswg = 0.005 tcjswg = 0.001 74 | +xtis = 3 xtid = 3 75 | 76 | +dmcg = 0 dmci = 0 dmdg = 0 dmcgt = 0 77 | +dwj = 0 xgw = 0 xgl = 0 78 | 79 | +rshg = 0.4 gbmin = 1e-010 rbpb = 5 rbpd = 15 80 | +rbps = 15 rbdb = 15 rbsb = 15 ngcon = 1 -------------------------------------------------------------------------------- /FreePDK45/tran_models/models_nom/NMOS_VTL.inc: -------------------------------------------------------------------------------- 1 | * Customized PTM 45 NMOS nom 2 | 3 | .model NMOS_VTL nmos level = 54 4 | 5 | * parameters related to the technology node 6 | +tnom = 27 epsrox = 3.9 7 | +eta0 = 0.006 nfactor = 2.1 wint = 5e-09 8 | +cgso = 1.1e-10 cgdo = 1.1e-10 xl = -2e-08 9 | 10 | * parameters customized by the user 11 | +toxe = 1.14e-09 toxp = 1e-09 toxm = 1.14e-09 toxref = 1.14e-09 12 | +dtox = 0.14e-09 lint = 3.75e-09 13 | +vth0 = 0.322 k1 = 0.4 u0 = 0.045 vsat = 148000 14 | +rdsw = 155 ndep = 3.4e+18 xj = 1.98e-08 15 | 16 | 17 | 18 | 19 | +version = 4.0 binunit = 1 paramchk= 1 mobmod = 0 20 | +capmod = 2 igcmod = 1 igbmod = 1 geomod = 1 21 | +diomod = 1 rdsmod = 0 rbodymod= 1 rgatemod= 1 22 | +permod = 1 acnqsmod= 0 trnqsmod= 0 23 | 24 | +ll = 0 wl = 0 lln = 1 wln = 1 25 | +lw = 0 ww = 0 lwn = 1 wwn = 1 26 | +lwl = 0 wwl = 0 xpart = 0 27 | 28 | +k2 = 0 k3 = 0 29 | +k3b = 0 w0 = 2.5e-006 dvt0 = 1 dvt1 = 2 30 | +dvt2 = 0 dvt0w = 0 dvt1w = 0 dvt2w = 0 31 | +dsub = 0.1 minv = 0.05 voffl = 0 dvtp0 = 1e-010 32 | +dvtp1 = 0.1 lpe0 = 0 lpeb = 0 33 | +ngate = 3e+20 nsd = 2e+020 phin = 0 34 | +cdsc = 0 cdscb = 0 cdscd = 0 cit = 0 35 | +voff = -0.13 etab = 0 36 | +vfb = -0.55 ua = 6e-010 ub = 1.2e-018 37 | +uc = 0 a0 = 1 ags = 0 38 | +a1 = 0 a2 = 1 b0 = 0 b1 = 0 39 | +keta = 0.04 dwg = 0 dwb = 0 pclm = 0.02 40 | +pdiblc1 = 0.001 pdiblc2 = 0.001 pdiblcb = -0.005 drout = 0.5 41 | +pvag = 1e-020 delta = 0.01 pscbe1 = 8.14e+008 pscbe2 = 1e-007 42 | +fprout = 0.2 pdits = 0.08 pditsd = 0.23 pditsl = 2300000 43 | +rsh = 5 rsw = 80 rdw = 80 44 | +rdswmin = 0 rdwmin = 0 rswmin = 0 prwg = 0 45 | +prwb = 0 wr = 1 alpha0 = 0.074 alpha1 = 0.005 46 | +beta0 = 30 agidl = 0.0002 bgidl = 2.1e+009 cgidl = 0.0002 47 | +egidl = 0.8 aigbacc = 0.012 bigbacc = 0.0028 cigbacc = 0.002 48 | +nigbacc = 1 aigbinv = 0.014 bigbinv = 0.004 cigbinv = 0.004 49 | +eigbinv = 1.1 nigbinv = 3 aigc = 0.02 bigc = 0.0027 50 | +cigc = 0.002 aigsd = 0.02 bigsd = 0.0027 cigsd = 0.002 51 | +nigc = 1 poxedge = 1 pigcd = 1 ntox = 1 52 | +xrcrg1 = 12 xrcrg2 = 5 53 | 54 | +cgbo = 2.56e-011 cgdl = 2.653e-010 55 | +cgsl = 2.653e-010 ckappas = 0.03 ckappad = 0.03 acde = 1 56 | +moin = 15 noff = 0.9 voffcv = 0.02 57 | 58 | +kt1 = -0.11 kt1l = 0 kt2 = 0.022 ute = -1.5 59 | +ua1 = 4.31e-009 ub1 = 7.61e-018 uc1 = -5.6e-011 prt = 0 60 | +at = 33000 61 | 62 | +fnoimod = 1 tnoimod = 0 63 | 64 | +jss = 0.0001 jsws = 1e-011 jswgs = 1e-010 njs = 1 65 | +ijthsfwd= 0.01 ijthsrev= 0.001 bvs = 10 xjbvs = 1 66 | +jsd = 0.0001 jswd = 1e-011 jswgd = 1e-010 njd = 1 67 | +ijthdfwd= 0.01 ijthdrev= 0.001 bvd = 10 xjbvd = 1 68 | +pbs = 1 cjs = 0.0005 mjs = 0.5 pbsws = 1 69 | +cjsws = 5e-010 mjsws = 0.33 pbswgs = 1 cjswgs = 3e-010 70 | +mjswgs = 0.33 pbd = 1 cjd = 0.0005 mjd = 0.5 71 | +pbswd = 1 cjswd = 5e-010 mjswd = 0.33 pbswgd = 1 72 | +cjswgd = 5e-010 mjswgd = 0.33 tpb = 0.005 tcj = 0.001 73 | +tpbsw = 0.005 tcjsw = 0.001 tpbswg = 0.005 tcjswg = 0.001 74 | +xtis = 3 xtid = 3 75 | 76 | +dmcg = 0 dmci = 0 dmdg = 0 dmcgt = 0 77 | +dwj = 0 xgw = 0 xgl = 0 78 | 79 | +rshg = 0.4 gbmin = 1e-010 rbpb = 5 rbpd = 15 80 | +rbps = 15 rbdb = 15 rbsb = 15 ngcon = 1 -------------------------------------------------------------------------------- /FreePDK45/tran_models/models_ss/NMOS_VTG.inc: -------------------------------------------------------------------------------- 1 | * Customized PTM 45 NMOS ss 2 | 3 | .model NMOS_VTG nmos level = 54 4 | 5 | * parameters related to the technology node 6 | +tnom = 27 epsrox = 3.9 7 | +eta0 = 0.006 nfactor = 2.1 wint = 5e-09 8 | +cgso = 1.1e-10 cgdo = 1.1e-10 xl = -2e-08 9 | 10 | * parameters customized by the user 11 | +toxe = 1.17e-09 toxp = 1e-09 toxm = 1.17e-09 toxref = 1.17e-09 12 | +dtox = 0.17e-09 lint = 3.225e-09 13 | +vth0 = 0.4356 k1 = 0.4 u0 = 0.044 vsat = 123000 14 | +rdsw = 155 ndep = 3.6e+18 xj = 2.05e-08 15 | 16 | 17 | 18 | 19 | +version = 4.0 binunit = 1 paramchk= 1 mobmod = 0 20 | +capmod = 2 igcmod = 1 igbmod = 1 geomod = 1 21 | +diomod = 1 rdsmod = 0 rbodymod= 1 rgatemod= 1 22 | +permod = 1 acnqsmod= 0 trnqsmod= 0 23 | 24 | +ll = 0 wl = 0 lln = 1 wln = 1 25 | +lw = 0 ww = 0 lwn = 1 wwn = 1 26 | +lwl = 0 wwl = 0 xpart = 0 27 | 28 | +k2 = 0 k3 = 0 29 | +k3b = 0 w0 = 2.5e-006 dvt0 = 1 dvt1 = 2 30 | +dvt2 = 0 dvt0w = 0 dvt1w = 0 dvt2w = 0 31 | +dsub = 0.1 minv = 0.05 voffl = 0 dvtp0 = 1e-010 32 | +dvtp1 = 0.1 lpe0 = 0 lpeb = 0 33 | +ngate = 3e+20 nsd = 2e+020 phin = 0 34 | +cdsc = 0 cdscb = 0 cdscd = 0 cit = 0 35 | +voff = -0.13 etab = 0 36 | +vfb = -0.55 ua = 6e-010 ub = 1.2e-018 37 | +uc = 0 a0 = 1 ags = 0 38 | +a1 = 0 a2 = 1 b0 = 0 b1 = 0 39 | +keta = 0.04 dwg = 0 dwb = 0 pclm = 0.02 40 | +pdiblc1 = 0.001 pdiblc2 = 0.001 pdiblcb = -0.005 drout = 0.5 41 | +pvag = 1e-020 delta = 0.01 pscbe1 = 8.14e+008 pscbe2 = 1e-007 42 | +fprout = 0.2 pdits = 0.08 pditsd = 0.23 pditsl = 2300000 43 | +rsh = 5 rsw = 80 rdw = 80 44 | +rdswmin = 0 rdwmin = 0 rswmin = 0 prwg = 0 45 | +prwb = 0 wr = 1 alpha0 = 0.074 alpha1 = 0.005 46 | +beta0 = 30 agidl = 0.0002 bgidl = 2.1e+009 cgidl = 0.0002 47 | +egidl = 0.8 aigbacc = 0.012 bigbacc = 0.0028 cigbacc = 0.002 48 | +nigbacc = 1 aigbinv = 0.014 bigbinv = 0.004 cigbinv = 0.004 49 | +eigbinv = 1.1 nigbinv = 3 aigc = 0.02 bigc = 0.0027 50 | +cigc = 0.002 aigsd = 0.02 bigsd = 0.0027 cigsd = 0.002 51 | +nigc = 1 poxedge = 1 pigcd = 1 ntox = 1 52 | +xrcrg1 = 12 xrcrg2 = 5 53 | 54 | +cgbo = 2.56e-011 cgdl = 2.653e-010 55 | +cgsl = 2.653e-010 ckappas = 0.03 ckappad = 0.03 acde = 1 56 | +moin = 15 noff = 0.9 voffcv = 0.02 57 | 58 | +kt1 = -0.11 kt1l = 0 kt2 = 0.022 ute = -1.5 59 | +ua1 = 4.31e-009 ub1 = 7.61e-018 uc1 = -5.6e-011 prt = 0 60 | +at = 33000 61 | 62 | +fnoimod = 1 tnoimod = 0 63 | 64 | +jss = 0.0001 jsws = 1e-011 jswgs = 1e-010 njs = 1 65 | +ijthsfwd= 0.01 ijthsrev= 0.001 bvs = 10 xjbvs = 1 66 | +jsd = 0.0001 jswd = 1e-011 jswgd = 1e-010 njd = 1 67 | +ijthdfwd= 0.01 ijthdrev= 0.001 bvd = 10 xjbvd = 1 68 | +pbs = 1 cjs = 0.0005 mjs = 0.5 pbsws = 1 69 | +cjsws = 5e-010 mjsws = 0.33 pbswgs = 1 cjswgs = 3e-010 70 | +mjswgs = 0.33 pbd = 1 cjd = 0.0005 mjd = 0.5 71 | +pbswd = 1 cjswd = 5e-010 mjswd = 0.33 pbswgd = 1 72 | +cjswgd = 5e-010 mjswgd = 0.33 tpb = 0.005 tcj = 0.001 73 | +tpbsw = 0.005 tcjsw = 0.001 tpbswg = 0.005 tcjswg = 0.001 74 | +xtis = 3 xtid = 3 75 | 76 | +dmcg = 0 dmci = 0 dmdg = 0 dmcgt = 0 77 | +dwj = 0 xgw = 0 xgl = 0 78 | 79 | +rshg = 0.4 gbmin = 1e-010 rbpb = 5 rbpd = 15 80 | +rbps = 15 rbdb = 15 rbsb = 15 ngcon = 1 -------------------------------------------------------------------------------- /FreePDK45/tran_models/models_ss/NMOS_VTL.inc: -------------------------------------------------------------------------------- 1 | * Customized PTM 45 NMOS ss 2 | 3 | .model NMOS_VTL nmos level = 54 4 | 5 | * parameters related to the technology node 6 | +tnom = 27 epsrox = 3.9 7 | +eta0 = 0.006 nfactor = 2.1 wint = 5e-09 8 | +cgso = 1.1e-10 cgdo = 1.1e-10 xl = -2e-08 9 | 10 | * parameters customized by the user 11 | +toxe = 1.17e-09 toxp = 1e-09 toxm = 1.17e-09 toxref = 1.17e-09 12 | +dtox = 0.17e-09 lint = 3.225e-09 13 | +vth0 = 0.347 k1 = 0.4 u0 = 0.044 vsat = 148000 14 | +rdsw = 155 ndep = 3.6e+18 xj = 2.05e-08 15 | 16 | 17 | 18 | 19 | +version = 4.0 binunit = 1 paramchk= 1 mobmod = 0 20 | +capmod = 2 igcmod = 1 igbmod = 1 geomod = 1 21 | +diomod = 1 rdsmod = 0 rbodymod= 1 rgatemod= 1 22 | +permod = 1 acnqsmod= 0 trnqsmod= 0 23 | 24 | +ll = 0 wl = 0 lln = 1 wln = 1 25 | +lw = 0 ww = 0 lwn = 1 wwn = 1 26 | +lwl = 0 wwl = 0 xpart = 0 27 | 28 | +k2 = 0 k3 = 0 29 | +k3b = 0 w0 = 2.5e-006 dvt0 = 1 dvt1 = 2 30 | +dvt2 = 0 dvt0w = 0 dvt1w = 0 dvt2w = 0 31 | +dsub = 0.1 minv = 0.05 voffl = 0 dvtp0 = 1e-010 32 | +dvtp1 = 0.1 lpe0 = 0 lpeb = 0 33 | +ngate = 3e+20 nsd = 2e+020 phin = 0 34 | +cdsc = 0 cdscb = 0 cdscd = 0 cit = 0 35 | +voff = -0.13 etab = 0 36 | +vfb = -0.55 ua = 6e-010 ub = 1.2e-018 37 | +uc = 0 a0 = 1 ags = 0 38 | +a1 = 0 a2 = 1 b0 = 0 b1 = 0 39 | +keta = 0.04 dwg = 0 dwb = 0 pclm = 0.02 40 | +pdiblc1 = 0.001 pdiblc2 = 0.001 pdiblcb = -0.005 drout = 0.5 41 | +pvag = 1e-020 delta = 0.01 pscbe1 = 8.14e+008 pscbe2 = 1e-007 42 | +fprout = 0.2 pdits = 0.08 pditsd = 0.23 pditsl = 2300000 43 | +rsh = 5 rsw = 80 rdw = 80 44 | +rdswmin = 0 rdwmin = 0 rswmin = 0 prwg = 0 45 | +prwb = 0 wr = 1 alpha0 = 0.074 alpha1 = 0.005 46 | +beta0 = 30 agidl = 0.0002 bgidl = 2.1e+009 cgidl = 0.0002 47 | +egidl = 0.8 aigbacc = 0.012 bigbacc = 0.0028 cigbacc = 0.002 48 | +nigbacc = 1 aigbinv = 0.014 bigbinv = 0.004 cigbinv = 0.004 49 | +eigbinv = 1.1 nigbinv = 3 aigc = 0.02 bigc = 0.0027 50 | +cigc = 0.002 aigsd = 0.02 bigsd = 0.0027 cigsd = 0.002 51 | +nigc = 1 poxedge = 1 pigcd = 1 ntox = 1 52 | +xrcrg1 = 12 xrcrg2 = 5 53 | 54 | +cgbo = 2.56e-011 cgdl = 2.653e-010 55 | +cgsl = 2.653e-010 ckappas = 0.03 ckappad = 0.03 acde = 1 56 | +moin = 15 noff = 0.9 voffcv = 0.02 57 | 58 | +kt1 = -0.11 kt1l = 0 kt2 = 0.022 ute = -1.5 59 | +ua1 = 4.31e-009 ub1 = 7.61e-018 uc1 = -5.6e-011 prt = 0 60 | +at = 33000 61 | 62 | +fnoimod = 1 tnoimod = 0 63 | 64 | +jss = 0.0001 jsws = 1e-011 jswgs = 1e-010 njs = 1 65 | +ijthsfwd= 0.01 ijthsrev= 0.001 bvs = 10 xjbvs = 1 66 | +jsd = 0.0001 jswd = 1e-011 jswgd = 1e-010 njd = 1 67 | +ijthdfwd= 0.01 ijthdrev= 0.001 bvd = 10 xjbvd = 1 68 | +pbs = 1 cjs = 0.0005 mjs = 0.5 pbsws = 1 69 | +cjsws = 5e-010 mjsws = 0.33 pbswgs = 1 cjswgs = 3e-010 70 | +mjswgs = 0.33 pbd = 1 cjd = 0.0005 mjd = 0.5 71 | +pbswd = 1 cjswd = 5e-010 mjswd = 0.33 pbswgd = 1 72 | +cjswgd = 5e-010 mjswgd = 0.33 tpb = 0.005 tcj = 0.001 73 | +tpbsw = 0.005 tcjsw = 0.001 tpbswg = 0.005 tcjswg = 0.001 74 | +xtis = 3 xtid = 3 75 | 76 | +dmcg = 0 dmci = 0 dmdg = 0 dmcgt = 0 77 | +dwj = 0 xgw = 0 xgl = 0 78 | 79 | +rshg = 0.4 gbmin = 1e-010 rbpb = 5 rbpd = 15 80 | +rbps = 15 rbdb = 15 rbsb = 15 ngcon = 1 -------------------------------------------------------------------------------- /FreePDK45/tran_models/models_nom/PMOS_VTH.inc: -------------------------------------------------------------------------------- 1 | * Customized PTM 45 PMOS PMOS_VTH 2 | 3 | .model PMOS_VTH pmos level = 54 4 | 5 | +version = 4.0 binunit = 1 paramchk= 1 mobmod = 0 6 | +capmod = 2 igcmod = 1 igbmod = 1 geomod = 1 7 | +diomod = 1 rdsmod = 0 rbodymod= 1 rgatemod= 1 8 | +permod = 1 acnqsmod= 0 trnqsmod= 0 9 | 10 | +tnom = 27 toxe = 1.6e-009 toxp = 1e-009 toxm = 1.6e-009 11 | +dtox = 6e-010 epsrox = 3.9 wint = 5e-009 lint = 3.75e-009 12 | +ll = 0 wl = 0 lln = 1 wln = 1 13 | +lw = 0 ww = 0 lwn = 1 wwn = 1 14 | +lwl = 0 wwl = 0 xpart = 0 toxref = 1.6e-009 15 | 16 | +vth0 = -0.5044 k1 = 0.4 k2 = -0.01 k3 = 0 17 | +k3b = 0 w0 = 2.5e-006 dvt0 = 1 dvt1 = 2 18 | +dvt2 = -0.032 dvt0w = 0 dvt1w = 0 dvt2w = 0 19 | +dsub = 0.1 minv = 0.05 voffl = 0 dvtp0 = 1e-011 20 | +dvtp1 = 0.05 lpe0 = 0 lpeb = 0 xj = 1.4e-008 21 | +ngate = 2e+020 ndep = 2.44e+018 nsd = 2e+020 phin = 0 22 | +cdsc = 0 cdscb = 0 cdscd = 0 cit = 0 23 | +voff = -0.126 nfactor = 1.8 eta0 = 0.0125 etab = 0 24 | +vfb = 0.55 u0 = 0.021 ua = 2e-009 ub = 5e-019 25 | +uc = 0 vsat = 80000 a0 = 1 ags = 1e-020 26 | +a1 = 0 a2 = 1 b0 = 0 b1 = 0 27 | +keta = -0.047 dwg = 0 dwb = 0 pclm = 0.12 28 | +pdiblc1 = 0.001 pdiblc2 = 0.001 pdiblcb = 3.4e-008 drout = 0.56 29 | +pvag = 1e-020 delta = 0.01 pscbe1 = 8.14e+008 pscbe2 = 9.58e-007 30 | +fprout = 0.2 pdits = 0.08 pditsd = 0.23 pditsl = 2300000 31 | +rsh = 5 rdsw = 250 rsw = 75 rdw = 75 32 | +rdswmin = 0 rdwmin = 0 rswmin = 0 prwg = 0 33 | +prwb = 0 wr = 1 alpha0 = 0.074 alpha1 = 0.005 34 | +beta0 = 30 agidl = 0.0002 bgidl = 2.1e+009 cgidl = 0.0002 35 | +egidl = 0.8 aigbacc = 0.012 bigbacc = 0.0028 cigbacc = 0.002 36 | +nigbacc = 1 aigbinv = 0.014 bigbinv = 0.004 cigbinv = 0.004 37 | +eigbinv = 1.1 nigbinv = 3 aigc = 0.0097 bigc = 0.00125 38 | +cigc = 0.0008 aigsd = 0.0097 bigsd = 0.00125 cigsd = 0.0008 39 | +nigc = 1 poxedge = 1 pigcd = 1 ntox = 1 40 | +xrcrg1 = 12 xrcrg2 = 5 41 | 42 | +cgso = 1.1e-010 cgdo = 1.1e-010 cgbo = 2.56e-011 cgdl = 2.653e-010 43 | +cgsl = 2.653e-010 ckappas = 0.03 ckappad = 0.03 acde = 1 44 | +moin = 15 noff = 0.9 voffcv = 0.02 45 | 46 | +kt1 = -0.11 kt1l = 0 kt2 = 0.022 ute = -1.5 47 | +ua1 = 4.31e-009 ub1 = 7.61e-018 uc1 = -5.6e-011 prt = 0 48 | +at = 33000 49 | 50 | +fnoimod = 1 tnoimod = 0 51 | 52 | +jss = 0.0001 jsws = 1e-011 jswgs = 1e-010 njs = 1 53 | +ijthsfwd= 0.01 ijthsrev= 0.001 bvs = 10 xjbvs = 1 54 | +jsd = 0.0001 jswd = 1e-011 jswgd = 1e-010 njd = 1 55 | +ijthdfwd= 0.01 ijthdrev= 0.001 bvd = 10 xjbvd = 1 56 | +pbs = 1 cjs = 0.0005 mjs = 0.5 pbsws = 1 57 | +cjsws = 5e-010 mjsws = 0.33 pbswgs = 1 cjswgs = 3e-010 58 | +mjswgs = 0.33 pbd = 1 cjd = 0.0005 mjd = 0.5 59 | +pbswd = 1 cjswd = 5e-010 mjswd = 0.33 pbswgd = 1 60 | +cjswgd = 5e-010 mjswgd = 0.33 tpb = 0.005 tcj = 0.001 61 | +tpbsw = 0.005 tcjsw = 0.001 tpbswg = 0.005 tcjswg = 0.001 62 | +xtis = 3 xtid = 3 63 | 64 | +dmcg = 0 dmci = 0 dmdg = 0 dmcgt = 0 65 | +dwj = 0 xgw = 0 xgl = 0 66 | 67 | +rshg = 0.4 gbmin = 1e-010 rbpb = 5 rbpd = 15 68 | +rbps = 15 rbdb = 15 rbsb = 15 ngcon = 1 -------------------------------------------------------------------------------- /FreePDK45/tran_models/models_ss/PMOS_VTH.inc: -------------------------------------------------------------------------------- 1 | * Customized PTM 45 PMOS PMOS_VTH 2 | 3 | .model PMOS_VTH pmos level = 54 4 | 5 | +version = 4.0 binunit = 1 paramchk= 1 mobmod = 0 6 | +capmod = 2 igcmod = 1 igbmod = 1 geomod = 1 7 | +diomod = 1 rdsmod = 0 rbodymod= 1 rgatemod= 1 8 | +permod = 1 acnqsmod= 0 trnqsmod= 0 9 | 10 | +tnom = 27 toxe = 1.65e-009 toxp = 1e-009 toxm = 1.65e-009 11 | +dtox = 6.5e-010 epsrox = 3.9 wint = 5e-009 lint = 3.225e-009 12 | +ll = 0 wl = 0 lln = 1 wln = 1 13 | +lw = 0 ww = 0 lwn = 1 wwn = 1 14 | +lwl = 0 wwl = 0 xpart = 0 toxref = 1.65e-009 15 | 16 | +vth0 = -0.5294 k1 = 0.4 k2 = -0.01 k3 = 0 17 | +k3b = 0 w0 = 2.5e-006 dvt0 = 1 dvt1 = 2 18 | +dvt2 = -0.032 dvt0w = 0 dvt1w = 0 dvt2w = 0 19 | +dsub = 0.1 minv = 0.05 voffl = 0 dvtp0 = 1e-011 20 | +dvtp1 = 0.05 lpe0 = 0 lpeb = 0 xj = 1.4e-008 21 | +ngate = 2e+020 ndep = 2.44e+018 nsd = 2e+020 phin = 0 22 | +cdsc = 0 cdscb = 0 cdscd = 0 cit = 0 23 | +voff = -0.126 nfactor = 1.8 eta0 = 0.0125 etab = 0 24 | +vfb = 0.55 u0 = 0.021 ua = 2e-009 ub = 5e-019 25 | +uc = 0 vsat = 80000 a0 = 1 ags = 1e-020 26 | +a1 = 0 a2 = 1 b0 = 0 b1 = 0 27 | +keta = -0.047 dwg = 0 dwb = 0 pclm = 0.12 28 | +pdiblc1 = 0.001 pdiblc2 = 0.001 pdiblcb = 3.4e-008 drout = 0.56 29 | +pvag = 1e-020 delta = 0.01 pscbe1 = 8.14e+008 pscbe2 = 9.58e-007 30 | +fprout = 0.2 pdits = 0.08 pditsd = 0.23 pditsl = 2300000 31 | +rsh = 5 rdsw = 250 rsw = 75 rdw = 75 32 | +rdswmin = 0 rdwmin = 0 rswmin = 0 prwg = 0 33 | +prwb = 0 wr = 1 alpha0 = 0.074 alpha1 = 0.005 34 | +beta0 = 30 agidl = 0.0002 bgidl = 2.1e+009 cgidl = 0.0002 35 | +egidl = 0.8 aigbacc = 0.012 bigbacc = 0.0028 cigbacc = 0.002 36 | +nigbacc = 1 aigbinv = 0.014 bigbinv = 0.004 cigbinv = 0.004 37 | +eigbinv = 1.1 nigbinv = 3 aigc = 0.0097 bigc = 0.00125 38 | +cigc = 0.0008 aigsd = 0.0097 bigsd = 0.00125 cigsd = 0.0008 39 | +nigc = 1 poxedge = 1 pigcd = 1 ntox = 1 40 | +xrcrg1 = 12 xrcrg2 = 5 41 | 42 | +cgso = 1.1e-010 cgdo = 1.1e-010 cgbo = 2.56e-011 cgdl = 2.653e-010 43 | +cgsl = 2.653e-010 ckappas = 0.03 ckappad = 0.03 acde = 1 44 | +moin = 15 noff = 0.9 voffcv = 0.02 45 | 46 | +kt1 = -0.11 kt1l = 0 kt2 = 0.022 ute = -1.5 47 | +ua1 = 4.31e-009 ub1 = 7.61e-018 uc1 = -5.6e-011 prt = 0 48 | +at = 33000 49 | 50 | +fnoimod = 1 tnoimod = 0 51 | 52 | +jss = 0.0001 jsws = 1e-011 jswgs = 1e-010 njs = 1 53 | +ijthsfwd= 0.01 ijthsrev= 0.001 bvs = 10 xjbvs = 1 54 | +jsd = 0.0001 jswd = 1e-011 jswgd = 1e-010 njd = 1 55 | +ijthdfwd= 0.01 ijthdrev= 0.001 bvd = 10 xjbvd = 1 56 | +pbs = 1 cjs = 0.0005 mjs = 0.5 pbsws = 1 57 | +cjsws = 5e-010 mjsws = 0.33 pbswgs = 1 cjswgs = 3e-010 58 | +mjswgs = 0.33 pbd = 1 cjd = 0.0005 mjd = 0.5 59 | +pbswd = 1 cjswd = 5e-010 mjswd = 0.33 pbswgd = 1 60 | +cjswgd = 5e-010 mjswgd = 0.33 tpb = 0.005 tcj = 0.001 61 | +tpbsw = 0.005 tcjsw = 0.001 tpbswg = 0.005 tcjswg = 0.001 62 | +xtis = 3 xtid = 3 63 | 64 | +dmcg = 0 dmci = 0 dmdg = 0 dmcgt = 0 65 | +dwj = 0 xgw = 0 xgl = 0 66 | 67 | +rshg = 0.4 gbmin = 1e-010 rbpb = 5 rbpd = 15 68 | +rbps = 15 rbdb = 15 rbsb = 15 ngcon = 1 -------------------------------------------------------------------------------- /FreePDK45/tran_models/models_ff/PMOS_VTH.inc: -------------------------------------------------------------------------------- 1 | * Customized PTM 45 PMOS PMOS_VTH ff 2 | 3 | .model PMOS_VTH pmos level = 54 4 | 5 | +version = 4.0 binunit = 1 paramchk= 1 mobmod = 0 6 | +capmod = 2 igcmod = 1 igbmod = 1 geomod = 1 7 | +diomod = 1 rdsmod = 0 rbodymod= 1 rgatemod= 1 8 | +permod = 1 acnqsmod= 0 trnqsmod= 0 9 | 10 | +tnom = 27 toxe = 1.55e-009 toxp = 1e-009 toxm = 1.55e-009 11 | +dtox = 5.5e-010 epsrox = 3.9 wint = 5e-009 lint = 4.275e-009 12 | +ll = 0 wl = 0 lln = 1 wln = 1 13 | +lw = 0 ww = 0 lwn = 1 wwn = 1 14 | +lwl = 0 wwl = 0 xpart = 0 toxref = 1.55e-009 15 | 16 | +vth0 = -0.4794 k1 = 0.4 k2 = -0.01 k3 = 0 17 | +k3b = 0 w0 = 2.5e-006 dvt0 = 1 dvt1 = 2 18 | +dvt2 = -0.032 dvt0w = 0 dvt1w = 0 dvt2w = 0 19 | +dsub = 0.1 minv = 0.05 voffl = 0 dvtp0 = 1e-011 20 | +dvtp1 = 0.05 lpe0 = 0 lpeb = 0 xj = 1.4e-008 21 | +ngate = 2e+020 ndep = 2.44e+018 nsd = 2e+020 phin = 0 22 | +cdsc = 0 cdscb = 0 cdscd = 0 cit = 0 23 | +voff = -0.126 nfactor = 1.8 eta0 = 0.0125 etab = 0 24 | +vfb = 0.55 u0 = 0.021 ua = 2e-009 ub = 5e-019 25 | +uc = 0 vsat = 80000 a0 = 1 ags = 1e-020 26 | +a1 = 0 a2 = 1 b0 = 0 b1 = 0 27 | +keta = -0.047 dwg = 0 dwb = 0 pclm = 0.12 28 | +pdiblc1 = 0.001 pdiblc2 = 0.001 pdiblcb = 3.4e-008 drout = 0.56 29 | +pvag = 1e-020 delta = 0.01 pscbe1 = 8.14e+008 pscbe2 = 9.58e-007 30 | +fprout = 0.2 pdits = 0.08 pditsd = 0.23 pditsl = 2300000 31 | +rsh = 5 rdsw = 250 rsw = 75 rdw = 75 32 | +rdswmin = 0 rdwmin = 0 rswmin = 0 prwg = 0 33 | +prwb = 0 wr = 1 alpha0 = 0.074 alpha1 = 0.005 34 | +beta0 = 30 agidl = 0.0002 bgidl = 2.1e+009 cgidl = 0.0002 35 | +egidl = 0.8 aigbacc = 0.012 bigbacc = 0.0028 cigbacc = 0.002 36 | +nigbacc = 1 aigbinv = 0.014 bigbinv = 0.004 cigbinv = 0.004 37 | +eigbinv = 1.1 nigbinv = 3 aigc = 0.0097 bigc = 0.00125 38 | +cigc = 0.0008 aigsd = 0.0097 bigsd = 0.00125 cigsd = 0.0008 39 | +nigc = 1 poxedge = 1 pigcd = 1 ntox = 1 40 | +xrcrg1 = 12 xrcrg2 = 5 41 | 42 | +cgso = 1.1e-010 cgdo = 1.1e-010 cgbo = 2.56e-011 cgdl = 2.653e-010 43 | +cgsl = 2.653e-010 ckappas = 0.03 ckappad = 0.03 acde = 1 44 | +moin = 15 noff = 0.9 voffcv = 0.02 45 | 46 | +kt1 = -0.11 kt1l = 0 kt2 = 0.022 ute = -1.5 47 | +ua1 = 4.31e-009 ub1 = 7.61e-018 uc1 = -5.6e-011 prt = 0 48 | +at = 33000 49 | 50 | +fnoimod = 1 tnoimod = 0 51 | 52 | +jss = 0.0001 jsws = 1e-011 jswgs = 1e-010 njs = 1 53 | +ijthsfwd= 0.01 ijthsrev= 0.001 bvs = 10 xjbvs = 1 54 | +jsd = 0.0001 jswd = 1e-011 jswgd = 1e-010 njd = 1 55 | +ijthdfwd= 0.01 ijthdrev= 0.001 bvd = 10 xjbvd = 1 56 | +pbs = 1 cjs = 0.0005 mjs = 0.5 pbsws = 1 57 | +cjsws = 5e-010 mjsws = 0.33 pbswgs = 1 cjswgs = 3e-010 58 | +mjswgs = 0.33 pbd = 1 cjd = 0.0005 mjd = 0.5 59 | +pbswd = 1 cjswd = 5e-010 mjswd = 0.33 pbswgd = 1 60 | +cjswgd = 5e-010 mjswgd = 0.33 tpb = 0.005 tcj = 0.001 61 | +tpbsw = 0.005 tcjsw = 0.001 tpbswg = 0.005 tcjswg = 0.001 62 | +xtis = 3 xtid = 3 63 | 64 | +dmcg = 0 dmci = 0 dmdg = 0 dmcgt = 0 65 | +dwj = 0 xgw = 0 xgl = 0 66 | 67 | +rshg = 0.4 gbmin = 1e-010 rbpb = 5 rbpd = 15 68 | +rbps = 15 rbdb = 15 rbsb = 15 ngcon = 1 -------------------------------------------------------------------------------- /FreePDK45/tran_models/models_nom/NMOS_VTH.inc: -------------------------------------------------------------------------------- 1 | * Customized PTM 45 NMOS NMOS_VTH 2 | 3 | .model NMOS_VTH nmos level = 54 4 | 5 | * parameters related to the technology node 6 | +tnom = 27 epsrox = 3.9 7 | +eta0 = 0.008 nfactor = 1.6 wint = 5e-09 8 | +cgso = 1.1e-010 cgdo = 1.1e-10 9 | 10 | * parameters customized by the user 11 | +toxe = 1.63e-09 toxp = 1.0e-09 toxm = 1.63e-09 toxref = 1.63e-09 12 | +dtox = 6.3e-10 lint = 3.75e-09 13 | +vth0 = 0.6078 k1 = 0.4 u0 = 0.05 vsat = 170000 14 | +rdsw = 155 ndep = 3.24e+018 xj = 1.98e-08 15 | 16 | 17 | 18 | +version = 4.0 binunit = 1 paramchk= 1 mobmod = 0 19 | +capmod = 2 igcmod = 1 igbmod = 1 geomod = 1 20 | +diomod = 1 rdsmod = 0 rbodymod= 1 rgatemod= 1 21 | +permod = 1 acnqsmod= 0 trnqsmod= 0 22 | 23 | +ll = 0 wl = 0 lln = 1 wln = 1 24 | +lw = 0 ww = 0 lwn = 1 wwn = 1 25 | +lwl = 0 wwl = 0 xpart = 0 26 | 27 | +k2 = 0 k3 = 0 28 | +k3b = 0 w0 = 2.5e-006 dvt0 = 1 dvt1 = 2 29 | +dvt2 = 0 dvt0w = 0 dvt1w = 0 dvt2w = 0 30 | +dsub = 0.1 minv = 0.05 voffl = 0 dvtp0 = 1e-010 31 | +dvtp1 = 0.1 lpe0 = 0 lpeb = 0 32 | +ngate = 3e+020 nsd = 2e+020 phin = 0 33 | +cdsc = 0 cdscb = 0 cdscd = 0 cit = 0 34 | +voff = -0.13 etab = 0 35 | +vfb = -0.55 u0 = 0.049 ua = 6e-010 ub = 1.2e-018 36 | +uc = 0 a0 = 1 ags = 0 37 | +a1 = 0 a2 = 1 b0 = 0 b1 = 0 38 | +keta = 0.04 dwg = 0 dwb = 0 pclm = 0.02 39 | +pdiblc1 = 0.001 pdiblc2 = 0.001 pdiblcb = -0.005 drout = 0.5 40 | +pvag = 1e-020 delta = 0.01 pscbe1 = 8.14e+008 pscbe2 = 1e-007 41 | +fprout = 0.2 pdits = 0.08 pditsd = 0.23 pditsl = 2300000 42 | +rsh = 5 rsw = 80 rdw = 80 43 | +rdswmin = 0 rdwmin = 0 rswmin = 0 prwg = 0 44 | +prwb = 0 wr = 1 alpha0 = 0.074 alpha1 = 0.005 45 | +beta0 = 30 agidl = 0.0002 bgidl = 2.1e+009 cgidl = 0.0002 46 | +egidl = 0.8 aigbacc = 0.012 bigbacc = 0.0028 cigbacc = 0.002 47 | +nigbacc = 1 aigbinv = 0.014 bigbinv = 0.004 cigbinv = 0.004 48 | +eigbinv = 1.1 nigbinv = 3 aigc = 0.015211 bigc = 0.0027432 49 | +cigc = 0.002 aigsd = 0.015211 bigsd = 0.0027432 cigsd = 0.002 50 | +nigc = 1 poxedge = 1 pigcd = 1 ntox = 1 51 | +xrcrg1 = 12 xrcrg2 = 5 52 | 53 | +cgbo = 2.56e-011 cgdl = 2.653e-010 54 | +cgsl = 2.653e-010 ckappas = 0.03 ckappad = 0.03 acde = 1 55 | +moin = 15 noff = 0.9 voffcv = 0.02 56 | 57 | +kt1 = -0.11 kt1l = 0 kt2 = 0.022 ute = -1.5 58 | +ua1 = 4.31e-009 ub1 = 7.61e-018 uc1 = -5.6e-011 prt = 0 59 | +at = 33000 60 | 61 | +fnoimod = 1 tnoimod = 0 62 | 63 | +jss = 0.0001 jsws = 1e-011 jswgs = 1e-010 njs = 1 64 | +ijthsfwd= 0.01 ijthsrev= 0.001 bvs = 10 xjbvs = 1 65 | +jsd = 0.0001 jswd = 1e-011 jswgd = 1e-010 njd = 1 66 | +ijthdfwd= 0.01 ijthdrev= 0.001 bvd = 10 xjbvd = 1 67 | +pbs = 1 cjs = 0.0005 mjs = 0.5 pbsws = 1 68 | +cjsws = 5e-010 mjsws = 0.33 pbswgs = 1 cjswgs = 3e-010 69 | +mjswgs = 0.33 pbd = 1 cjd = 0.0005 mjd = 0.5 70 | +pbswd = 1 cjswd = 5e-010 mjswd = 0.33 pbswgd = 1 71 | +cjswgd = 5e-010 mjswgd = 0.33 tpb = 0.005 tcj = 0.001 72 | +tpbsw = 0.005 tcjsw = 0.001 tpbswg = 0.005 tcjswg = 0.001 73 | +xtis = 3 xtid = 3 74 | 75 | +dmcg = 0 dmci = 0 dmdg = 0 dmcgt = 0 76 | +dwj = 0 xgw = 0 xgl = 0 77 | 78 | +rshg = 0.4 gbmin = 1e-010 rbpb = 5 rbpd = 15 79 | +rbps = 15 rbdb = 15 rbsb = 15 ngcon = 1 80 | 81 | -------------------------------------------------------------------------------- /FreePDK45/tran_models/models_ff/NMOS_VTH.inc: -------------------------------------------------------------------------------- 1 | * Customized PTM 45 NMOS NMOS_VTH ff 2 | 3 | .model NMOS_VTH nmos level = 54 4 | 5 | * parameters related to the technology node 6 | +tnom = 27 epsrox = 3.9 7 | +eta0 = 0.008 nfactor = 1.6 wint = 5e-09 8 | +cgso = 1.1e-010 cgdo = 1.1e-10 9 | 10 | * parameters customized by the user 11 | +toxe = 1.58e-09 toxp = 1.0e-09 toxm = 1.58e-09 toxref = 1.58e-09 12 | +dtox = 5.8e-10 lint = 4.275e-09 13 | +vth0 = 0.5828 k1 = 0.4 u0 = 0.05 vsat = 170000 14 | +rdsw = 155 ndep = 3.24e+018 xj = 1.9e-08 15 | 16 | 17 | 18 | +version = 4.0 binunit = 1 paramchk= 1 mobmod = 0 19 | +capmod = 2 igcmod = 1 igbmod = 1 geomod = 1 20 | +diomod = 1 rdsmod = 0 rbodymod= 1 rgatemod= 1 21 | +permod = 1 acnqsmod= 0 trnqsmod= 0 22 | 23 | +ll = 0 wl = 0 lln = 1 wln = 1 24 | +lw = 0 ww = 0 lwn = 1 wwn = 1 25 | +lwl = 0 wwl = 0 xpart = 0 26 | 27 | +k2 = 0 k3 = 0 28 | +k3b = 0 w0 = 2.5e-006 dvt0 = 1 dvt1 = 2 29 | +dvt2 = 0 dvt0w = 0 dvt1w = 0 dvt2w = 0 30 | +dsub = 0.1 minv = 0.05 voffl = 0 dvtp0 = 1e-010 31 | +dvtp1 = 0.1 lpe0 = 0 lpeb = 0 32 | +ngate = 3e+020 nsd = 2e+020 phin = 0 33 | +cdsc = 0 cdscb = 0 cdscd = 0 cit = 0 34 | +voff = -0.13 etab = 0 35 | +vfb = -0.55 u0 = 0.049 ua = 6e-010 ub = 1.2e-018 36 | +uc = 0 a0 = 1 ags = 0 37 | +a1 = 0 a2 = 1 b0 = 0 b1 = 0 38 | +keta = 0.04 dwg = 0 dwb = 0 pclm = 0.02 39 | +pdiblc1 = 0.001 pdiblc2 = 0.001 pdiblcb = -0.005 drout = 0.5 40 | +pvag = 1e-020 delta = 0.01 pscbe1 = 8.14e+008 pscbe2 = 1e-007 41 | +fprout = 0.2 pdits = 0.08 pditsd = 0.23 pditsl = 2300000 42 | +rsh = 5 rsw = 80 rdw = 80 43 | +rdswmin = 0 rdwmin = 0 rswmin = 0 prwg = 0 44 | +prwb = 0 wr = 1 alpha0 = 0.074 alpha1 = 0.005 45 | +beta0 = 30 agidl = 0.0002 bgidl = 2.1e+009 cgidl = 0.0002 46 | +egidl = 0.8 aigbacc = 0.012 bigbacc = 0.0028 cigbacc = 0.002 47 | +nigbacc = 1 aigbinv = 0.014 bigbinv = 0.004 cigbinv = 0.004 48 | +eigbinv = 1.1 nigbinv = 3 aigc = 0.015211 bigc = 0.0027432 49 | +cigc = 0.002 aigsd = 0.015211 bigsd = 0.0027432 cigsd = 0.002 50 | +nigc = 1 poxedge = 1 pigcd = 1 ntox = 1 51 | +xrcrg1 = 12 xrcrg2 = 5 52 | 53 | +cgbo = 2.56e-011 cgdl = 2.653e-010 54 | +cgsl = 2.653e-010 ckappas = 0.03 ckappad = 0.03 acde = 1 55 | +moin = 15 noff = 0.9 voffcv = 0.02 56 | 57 | +kt1 = -0.11 kt1l = 0 kt2 = 0.022 ute = -1.5 58 | +ua1 = 4.31e-009 ub1 = 7.61e-018 uc1 = -5.6e-011 prt = 0 59 | +at = 33000 60 | 61 | +fnoimod = 1 tnoimod = 0 62 | 63 | +jss = 0.0001 jsws = 1e-011 jswgs = 1e-010 njs = 1 64 | +ijthsfwd= 0.01 ijthsrev= 0.001 bvs = 10 xjbvs = 1 65 | +jsd = 0.0001 jswd = 1e-011 jswgd = 1e-010 njd = 1 66 | +ijthdfwd= 0.01 ijthdrev= 0.001 bvd = 10 xjbvd = 1 67 | +pbs = 1 cjs = 0.0005 mjs = 0.5 pbsws = 1 68 | +cjsws = 5e-010 mjsws = 0.33 pbswgs = 1 cjswgs = 3e-010 69 | +mjswgs = 0.33 pbd = 1 cjd = 0.0005 mjd = 0.5 70 | +pbswd = 1 cjswd = 5e-010 mjswd = 0.33 pbswgd = 1 71 | +cjswgd = 5e-010 mjswgd = 0.33 tpb = 0.005 tcj = 0.001 72 | +tpbsw = 0.005 tcjsw = 0.001 tpbswg = 0.005 tcjswg = 0.001 73 | +xtis = 3 xtid = 3 74 | 75 | +dmcg = 0 dmci = 0 dmdg = 0 dmcgt = 0 76 | +dwj = 0 xgw = 0 xgl = 0 77 | 78 | +rshg = 0.4 gbmin = 1e-010 rbpb = 5 rbpd = 15 79 | +rbps = 15 rbdb = 15 rbsb = 15 ngcon = 1 80 | 81 | -------------------------------------------------------------------------------- /FreePDK45/tran_models/models_ss/NMOS_VTH.inc: -------------------------------------------------------------------------------- 1 | * Customized PTM 45 NMOS NMOS_VTH ss 2 | 3 | .model NMOS_VTH nmos level = 54 4 | 5 | * parameters related to the technology node 6 | +tnom = 27 epsrox = 3.9 7 | +eta0 = 0.008 nfactor = 1.6 wint = 5e-09 8 | +cgso = 1.1e-010 cgdo = 1.1e-10 9 | 10 | * parameters customized by the user 11 | +toxe = 1.68e-09 toxp = 1.0e-09 toxm = 1.68e-09 toxref = 1.68e-09 12 | +dtox = 6.8e-10 lint = 3.225e-09 13 | +vth0 = 0.6328 k1 = 0.4 u0 = 0.05 vsat = 170000 14 | +rdsw = 155 ndep = 3.4e+018 xj = 2.05e-08 15 | 16 | 17 | 18 | +version = 4.0 binunit = 1 paramchk= 1 mobmod = 0 19 | +capmod = 2 igcmod = 1 igbmod = 1 geomod = 1 20 | +diomod = 1 rdsmod = 0 rbodymod= 1 rgatemod= 1 21 | +permod = 1 acnqsmod= 0 trnqsmod= 0 22 | 23 | +ll = 0 wl = 0 lln = 1 wln = 1 24 | +lw = 0 ww = 0 lwn = 1 wwn = 1 25 | +lwl = 0 wwl = 0 xpart = 0 26 | 27 | +k2 = 0 k3 = 0 28 | +k3b = 0 w0 = 2.5e-006 dvt0 = 1 dvt1 = 2 29 | +dvt2 = 0 dvt0w = 0 dvt1w = 0 dvt2w = 0 30 | +dsub = 0.1 minv = 0.05 voffl = 0 dvtp0 = 1e-010 31 | +dvtp1 = 0.1 lpe0 = 0 lpeb = 0 32 | +ngate = 3e+020 nsd = 2e+020 phin = 0 33 | +cdsc = 0 cdscb = 0 cdscd = 0 cit = 0 34 | +voff = -0.13 etab = 0 35 | +vfb = -0.55 u0 = 0.049 ua = 6e-010 ub = 1.2e-018 36 | +uc = 0 a0 = 1 ags = 0 37 | +a1 = 0 a2 = 1 b0 = 0 b1 = 0 38 | +keta = 0.04 dwg = 0 dwb = 0 pclm = 0.02 39 | +pdiblc1 = 0.001 pdiblc2 = 0.001 pdiblcb = -0.005 drout = 0.5 40 | +pvag = 1e-020 delta = 0.01 pscbe1 = 8.14e+008 pscbe2 = 1e-007 41 | +fprout = 0.2 pdits = 0.08 pditsd = 0.23 pditsl = 2300000 42 | +rsh = 5 rsw = 80 rdw = 80 43 | +rdswmin = 0 rdwmin = 0 rswmin = 0 prwg = 0 44 | +prwb = 0 wr = 1 alpha0 = 0.074 alpha1 = 0.005 45 | +beta0 = 30 agidl = 0.0002 bgidl = 2.1e+009 cgidl = 0.0002 46 | +egidl = 0.8 aigbacc = 0.012 bigbacc = 0.0028 cigbacc = 0.002 47 | +nigbacc = 1 aigbinv = 0.014 bigbinv = 0.004 cigbinv = 0.004 48 | +eigbinv = 1.1 nigbinv = 3 aigc = 0.015211 bigc = 0.0027432 49 | +cigc = 0.002 aigsd = 0.015211 bigsd = 0.0027432 cigsd = 0.002 50 | +nigc = 1 poxedge = 1 pigcd = 1 ntox = 1 51 | +xrcrg1 = 12 xrcrg2 = 5 52 | 53 | +cgbo = 2.56e-011 cgdl = 2.653e-010 54 | +cgsl = 2.653e-010 ckappas = 0.03 ckappad = 0.03 acde = 1 55 | +moin = 15 noff = 0.9 voffcv = 0.02 56 | 57 | +kt1 = -0.11 kt1l = 0 kt2 = 0.022 ute = -1.5 58 | +ua1 = 4.31e-009 ub1 = 7.61e-018 uc1 = -5.6e-011 prt = 0 59 | +at = 33000 60 | 61 | +fnoimod = 1 tnoimod = 0 62 | 63 | +jss = 0.0001 jsws = 1e-011 jswgs = 1e-010 njs = 1 64 | +ijthsfwd= 0.01 ijthsrev= 0.001 bvs = 10 xjbvs = 1 65 | +jsd = 0.0001 jswd = 1e-011 jswgd = 1e-010 njd = 1 66 | +ijthdfwd= 0.01 ijthdrev= 0.001 bvd = 10 xjbvd = 1 67 | +pbs = 1 cjs = 0.0005 mjs = 0.5 pbsws = 1 68 | +cjsws = 5e-010 mjsws = 0.33 pbswgs = 1 cjswgs = 3e-010 69 | +mjswgs = 0.33 pbd = 1 cjd = 0.0005 mjd = 0.5 70 | +pbswd = 1 cjswd = 5e-010 mjswd = 0.33 pbswgd = 1 71 | +cjswgd = 5e-010 mjswgd = 0.33 tpb = 0.005 tcj = 0.001 72 | +tpbsw = 0.005 tcjsw = 0.001 tpbswg = 0.005 tcjswg = 0.001 73 | +xtis = 3 xtid = 3 74 | 75 | +dmcg = 0 dmci = 0 dmdg = 0 dmcgt = 0 76 | +dwj = 0 xgw = 0 xgl = 0 77 | 78 | +rshg = 0.4 gbmin = 1e-010 rbpb = 5 rbpd = 15 79 | +rbps = 15 rbdb = 15 rbsb = 15 ngcon = 1 80 | 81 | -------------------------------------------------------------------------------- /FreePDK45/tran_models/models_ss/PMOS_VTG.inc: -------------------------------------------------------------------------------- 1 | * Customized PTM 45 PMOS PMOS_VTG ss 2 | 3 | .model PMOS_VTG pmos level = 54 4 | 5 | * parameter customized by user 6 | +vth0 = -0.4092 toxref = 1.3e-009 vsat = 62000 7 | +toxe = 1.3e-009 toxp = 1.0e-009 toxm = 1.3e-009 8 | +dtox = 3e-010 epsrox = 3.9 wint = 5e-009 lint = 3.225e-009 9 | 10 | +version = 4.0 binunit = 1 paramchk= 1 mobmod = 0 11 | +capmod = 2 igcmod = 1 igbmod = 1 geomod = 1 12 | +diomod = 1 rdsmod = 0 rbodymod= 1 rgatemod= 1 13 | +permod = 1 acnqsmod= 0 trnqsmod= 0 14 | 15 | +tnom = 27 16 | 17 | +ll = 0 wl = 0 lln = 1 wln = 1 18 | +lw = 0 ww = 0 lwn = 1 wwn = 1 19 | +lwl = 0 wwl = 0 xpart = 0 toxref = 1.3e-009 20 | +xl = -20e-9 21 | 22 | +k1 = 0.4 k2 = -0.01 k3 = 0 23 | +k3b = 0 w0 = 2.5e-006 dvt0 = 1 dvt1 = 2 24 | +dvt2 = -0.032 dvt0w = 0 dvt1w = 0 dvt2w = 0 25 | +dsub = 0.1 minv = 0.05 voffl = 0 dvtp0 = 1e-011 26 | +dvtp1 = 0.05 lpe0 = 0 lpeb = 0 xj = 1.98e-008 27 | +ngate = 2e+020 ndep = 2.44e+018 nsd = 2e+020 phin = 0 28 | +cdsc = 0 cdscb = 0 cdscd = 0 cit = 0 29 | +voff = -0.126 nfactor = 2.22 eta0 = 0.0055 etab = 0 30 | +vfb = 0.55 u0 = 0.02 ua = 2e-009 ub = 5e-019 31 | +uc = 0 a0 = 1 ags = 1e-020 32 | +a1 = 0 a2 = 1 b0 = 0 b1 = 0 33 | +keta = -0.047 dwg = 0 dwb = 0 pclm = 0.12 34 | +pdiblc1 = 0.001 pdiblc2 = 0.001 pdiblcb = 3.4e-008 drout = 0.56 35 | +pvag = 1e-020 delta = 0.01 pscbe1 = 8.14e+008 pscbe2 = 9.58e-007 36 | +fprout = 0.2 pdits = 0.08 pditsd = 0.23 pditsl = 2300000 37 | +rsh = 5 rdsw = 155 rsw = 75 rdw = 75 38 | +rdswmin = 0 rdwmin = 0 rswmin = 0 prwg = 0 39 | +prwb = 0 wr = 1 alpha0 = 0.074 alpha1 = 0.005 40 | +beta0 = 30 agidl = 0.0002 bgidl = 2.1e+009 cgidl = 0.0002 41 | +egidl = 0.8 aigbacc = 0.012 bigbacc = 0.0028 cigbacc = 0.002 42 | +nigbacc = 1 aigbinv = 0.014 bigbinv = 0.004 cigbinv = 0.004 43 | +eigbinv = 1.1 nigbinv = 3 aigc = 0.010687 bigc = 0.0012607 44 | +cigc = 0.0008 aigsd = 0.010687 bigsd = 0.0012607 cigsd = 0.0008 45 | +nigc = 1 poxedge = 1 pigcd = 1 ntox = 1 46 | +xrcrg1 = 12 xrcrg2 = 5 47 | 48 | +cgso = 1.1e-010 cgdo = 1.1e-010 cgbo = 2.56e-011 cgdl = 2.653e-010 49 | +cgsl = 2.653e-010 ckappas = 0.03 ckappad = 0.03 acde = 1 50 | +moin = 15 noff = 0.9 voffcv = 0.02 51 | 52 | +kt1 = -0.11 kt1l = 0 kt2 = 0.022 ute = -1.5 53 | +ua1 = 4.31e-009 ub1 = 7.61e-018 uc1 = -5.6e-011 prt = 0 54 | +at = 33000 55 | 56 | +fnoimod = 1 tnoimod = 0 57 | 58 | +jss = 0.0001 jsws = 1e-011 jswgs = 1e-010 njs = 1 59 | +ijthsfwd= 0.01 ijthsrev= 0.001 bvs = 10 xjbvs = 1 60 | +jsd = 0.0001 jswd = 1e-011 jswgd = 1e-010 njd = 1 61 | +ijthdfwd= 0.01 ijthdrev= 0.001 bvd = 10 xjbvd = 1 62 | +pbs = 1 cjs = 0.0005 mjs = 0.5 pbsws = 1 63 | +cjsws = 5e-010 mjsws = 0.33 pbswgs = 1 cjswgs = 3e-010 64 | +mjswgs = 0.33 pbd = 1 cjd = 0.0005 mjd = 0.5 65 | +pbswd = 1 cjswd = 5e-010 mjswd = 0.33 pbswgd = 1 66 | +cjswgd = 5e-010 mjswgd = 0.33 tpb = 0.005 tcj = 0.001 67 | +tpbsw = 0.005 tcjsw = 0.001 tpbswg = 0.005 tcjswg = 0.001 68 | +xtis = 3 xtid = 3 69 | 70 | +dmcg = 0 dmci = 0 dmdg = 0 dmcgt = 0 71 | +dwj = 0 xgw = 0 xgl = 0 72 | 73 | +rshg = 0.4 gbmin = 1e-010 rbpb = 5 rbpd = 15 74 | +rbps = 15 rbdb = 15 rbsb = 15 -------------------------------------------------------------------------------- /FreePDK45/tran_models/models_ff/PMOS_VTG.inc: -------------------------------------------------------------------------------- 1 | * Customized PTM 45 PMOS PMOS_VTG ff 2 | 3 | .model PMOS_VTG pmos level = 54 4 | 5 | * parameter customized by user 6 | +vth0 = -0.3592 toxref = 1.22e-009 vsat = 62000 7 | +toxe = 1.22e-009 toxp = 1.0e-009 toxm = 1.22e-009 8 | +dtox = 2.2e-010 epsrox = 3.9 wint = 5e-009 lint = 4.275e-009 9 | 10 | +version = 4.0 binunit = 1 paramchk= 1 mobmod = 0 11 | +capmod = 2 igcmod = 1 igbmod = 1 geomod = 1 12 | +diomod = 1 rdsmod = 0 rbodymod= 1 rgatemod= 1 13 | +permod = 1 acnqsmod= 0 trnqsmod= 0 14 | 15 | +tnom = 27 16 | 17 | +ll = 0 wl = 0 lln = 1 wln = 1 18 | +lw = 0 ww = 0 lwn = 1 wwn = 1 19 | +lwl = 0 wwl = 0 xpart = 0 toxref = 1.3e-009 20 | +xl = -20e-9 21 | 22 | +k1 = 0.4 k2 = -0.01 k3 = 0 23 | +k3b = 0 w0 = 2.5e-006 dvt0 = 1 dvt1 = 2 24 | +dvt2 = -0.032 dvt0w = 0 dvt1w = 0 dvt2w = 0 25 | +dsub = 0.1 minv = 0.05 voffl = 0 dvtp0 = 1e-011 26 | +dvtp1 = 0.05 lpe0 = 0 lpeb = 0 xj = 1.98e-008 27 | +ngate = 2e+020 ndep = 2.44e+018 nsd = 2e+020 phin = 0 28 | +cdsc = 0 cdscb = 0 cdscd = 0 cit = 0 29 | +voff = -0.126 nfactor = 2.22 eta0 = 0.0055 etab = 0 30 | +vfb = 0.55 u0 = 0.02 ua = 2e-009 ub = 5e-019 31 | +uc = 0 a0 = 1 ags = 1e-020 32 | +a1 = 0 a2 = 1 b0 = 0 b1 = 0 33 | +keta = -0.047 dwg = 0 dwb = 0 pclm = 0.12 34 | +pdiblc1 = 0.001 pdiblc2 = 0.001 pdiblcb = 3.4e-008 drout = 0.56 35 | +pvag = 1e-020 delta = 0.01 pscbe1 = 8.14e+008 pscbe2 = 9.58e-007 36 | +fprout = 0.2 pdits = 0.08 pditsd = 0.23 pditsl = 2300000 37 | +rsh = 5 rdsw = 155 rsw = 75 rdw = 75 38 | +rdswmin = 0 rdwmin = 0 rswmin = 0 prwg = 0 39 | +prwb = 0 wr = 1 alpha0 = 0.074 alpha1 = 0.005 40 | +beta0 = 30 agidl = 0.0002 bgidl = 2.1e+009 cgidl = 0.0002 41 | +egidl = 0.8 aigbacc = 0.012 bigbacc = 0.0028 cigbacc = 0.002 42 | +nigbacc = 1 aigbinv = 0.014 bigbinv = 0.004 cigbinv = 0.004 43 | +eigbinv = 1.1 nigbinv = 3 aigc = 0.010687 bigc = 0.0012607 44 | +cigc = 0.0008 aigsd = 0.010687 bigsd = 0.0012607 cigsd = 0.0008 45 | +nigc = 1 poxedge = 1 pigcd = 1 ntox = 1 46 | +xrcrg1 = 12 xrcrg2 = 5 47 | 48 | +cgso = 1.1e-010 cgdo = 1.1e-010 cgbo = 2.56e-011 cgdl = 2.653e-010 49 | +cgsl = 2.653e-010 ckappas = 0.03 ckappad = 0.03 acde = 1 50 | +moin = 15 noff = 0.9 voffcv = 0.02 51 | 52 | +kt1 = -0.11 kt1l = 0 kt2 = 0.022 ute = -1.5 53 | +ua1 = 4.31e-009 ub1 = 7.61e-018 uc1 = -5.6e-011 prt = 0 54 | +at = 33000 55 | 56 | +fnoimod = 1 tnoimod = 0 57 | 58 | +jss = 0.0001 jsws = 1e-011 jswgs = 1e-010 njs = 1 59 | +ijthsfwd= 0.01 ijthsrev= 0.001 bvs = 10 xjbvs = 1 60 | +jsd = 0.0001 jswd = 1e-011 jswgd = 1e-010 njd = 1 61 | +ijthdfwd= 0.01 ijthdrev= 0.001 bvd = 10 xjbvd = 1 62 | +pbs = 1 cjs = 0.0005 mjs = 0.5 pbsws = 1 63 | +cjsws = 5e-010 mjsws = 0.33 pbswgs = 1 cjswgs = 3e-010 64 | +mjswgs = 0.33 pbd = 1 cjd = 0.0005 mjd = 0.5 65 | +pbswd = 1 cjswd = 5e-010 mjswd = 0.33 pbswgd = 1 66 | +cjswgd = 5e-010 mjswgd = 0.33 tpb = 0.005 tcj = 0.001 67 | +tpbsw = 0.005 tcjsw = 0.001 tpbswg = 0.005 tcjswg = 0.001 68 | +xtis = 3 xtid = 3 69 | 70 | +dmcg = 0 dmci = 0 dmdg = 0 dmcgt = 0 71 | +dwj = 0 xgw = 0 xgl = 0 72 | 73 | +rshg = 0.4 gbmin = 1e-010 rbpb = 5 rbpd = 15 74 | +rbps = 15 rbdb = 15 rbsb = 15 --------------------------------------------------------------------------------