├── 32 bit adder ├── 32 bit adder.jpg ├── adder32.v └── adder32_tb.v ├── Array Multiplier ├── array_multiplier.jpg └── array_multiplier.v ├── Barrel Shifter ├── barrel_shifter_8bit.jpg ├── barrel_shifter_8bit.v ├── barrel_shifter_8bit_tb.v └── mux2X1.v ├── Binary Divider 16 by 8 └── binary_divider.v ├── Booth Multiplication ├── booth_multiplication.jpg └── booth_multiplication.v ├── CRC Coding ├── CRC Coding.pdf ├── CRC_16_parallel │ ├── CRC_16_parallel.jpg │ ├── CRC_16_parallel.v │ └── CRC_16_parallel_tb.v ├── CRC_16_serial │ ├── CRC_16_serial.jpg │ ├── CRC_16_serial.v │ └── CRC_16_serial_tb.v ├── CRC_32_parallel │ ├── CRC_32_parallel.jpg │ ├── CRC_32_parallel.v │ └── CRC_32_parallel_tb.v └── CRC_32_serial │ ├── CRC_32_serial.jpg │ ├── CRC_32_serial.v │ └── CRC_32_serial_tb.v ├── Carry Select and Carry Look Ahead Adder ├── carry_look_ahead_adder.jpg ├── carry_look_ahead_adder.v ├── carry_select_adder.jpg └── carry_select_adder.v ├── Carry Skip and Carry Save Adder ├── carry_save_adder.jpg ├── carry_save_adder.v ├── carry_skip_adder.jpg └── carry_skip_adder.v ├── Complex Multiplier ├── complex_multiplication.jpg └── complex_multiplication.v ├── Dice Game └── dice_game.v ├── FIFO ├── fifo.jpg ├── fifo.v └── fifo_tb.v ├── Fixed Point Adder and Subtractor ├── fixed_point_adder.v ├── fixed_point_adder1.jpg ├── fixed_point_adder2.jpg ├── fixed_point_subtractor.v ├── fixed_point_subtractor1.jpg └── fixed_point_subtractor2.jpg ├── Fixed Point Multiplier and Divider ├── fixed_point_divider.v ├── fixed_point_divider1.jpg ├── fixed_point_divider2.jpg ├── fixed_point_multiplier.v ├── fixed_point_multiplier1.jpg └── fixed_point_multiplier2.jpg ├── Floating Point IEEE 754 Addition Subtraction ├── Addition_Subtraction.v └── IEEE_754_Addition_Substraction.jpg ├── Floating Point IEEE 754 Division ├── IEEE_754_Division.jpg ├── Test.txt ├── TestGenerator.py └── division.v ├── Floating Point IEEE 754 Multiplication ├── IEEE_754_Multiplication.jpg └── Multiplication.v ├── Fraction Multiplier ├── fraction multiplier.jpg ├── fraction_multiplication.jpg ├── fraction_multiplication.v └── fraction_multiplication_tb.v ├── High Radix Multiplier ├── high radix.png ├── high_radix_multiplication.v ├── high_radix_mutiplication_tb.v └── multiplier.jpg ├── I2C and SPI Protocols ├── I2C │ ├── I2C.jpg │ ├── Master.v │ ├── Slave.v │ ├── i2c frame.png │ └── tbmast.v └── SPI │ ├── Loopback.jpg │ ├── Loopback.v │ ├── Loopback_tb.v │ ├── Master.jpg │ ├── Master.v │ ├── Master_tb.v │ ├── Slave.v │ └── images.png ├── LFSR and CFSR ├── CFSR │ ├── cfsr.jpg │ ├── cfsr.v │ └── cfsr.vec └── LFSR │ ├── lfsr.jpg │ ├── lfsr.v │ └── lfsr_tb.v ├── LICENCE.txt ├── Logarithm Implementation ├── log.jpg └── log.v ├── Mealy and Moore State Machine Implementation of Sequence Detector ├── mealy.jpg ├── mealy.v ├── moore.jpg └── moore.v ├── Modified Booth Algorithm ├── modified_booth.jpg ├── modified_booth.v └── modified_booth_tb.v ├── Pipelined Multiplier ├── pipelined multiplier.jpg ├── pipelined_multiplier.v └── pipelined_multiplier_tb.v ├── README.md ├── Restoring and Non Restoring Division ├── Non Restoring Division Radix 2.jpg ├── Restoring Division Radix 2.jpg ├── Restoring Division Radix 4.jpg ├── non_restoring_div_R2.v ├── restoring_div_R2.v └── restoring_div_R4.v ├── Sequential Multiplier ├── SR1.v ├── SR2.v ├── adder.v ├── counter.v ├── pipo.v ├── prod1.v ├── sequential_multiplication.v ├── sequential_multiplication1.jpg ├── sequential_multiplication2.jpg └── sequential_multiplication_tb.v ├── Shift and Add Binary Multiplier ├── shift and add multiplier.jpg ├── shift and add.png └── shift_add_multiplication.v ├── Traffic Light Controller ├── test_commands.v ├── traffic_light.jpg └── traffic_light.v ├── Universal_Shift_Register ├── D_FlipFlop.v ├── Mux_8_to_1.v ├── Universal_shift_reg.jpg ├── Universal_shift_reg.v ├── Universal_shift_reg_tb.v └── usr.png ├── bcd_adder ├── bcd_adder.jpg └── bcd_adder.v ├── dual_address_ram ├── dual_address_ram.v ├── dual_address_ram0.jpg ├── dual_address_ram1.jpg ├── dual_address_ram2.jpg └── dual_address_ram3.jpg └── dual_address_rom ├── dual_address_rom.jpg └── dual_address_rom.v /32 bit adder/32 bit adder.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Test134n/32-Verilog-Mini-Projects/f6458719db15c2b348ec63d70c5ab7572b771341/32 bit adder/32 bit adder.jpg -------------------------------------------------------------------------------- /32 bit adder/adder32.v: -------------------------------------------------------------------------------- 1 | module Adder32 (A, B, Ci, S, Co); 2 | 3 | input[31:0] A; 4 | input[31:0] B; 5 | input Ci; 6 | output[31:0] S; 7 | output Co; 8 | wire[32:0] Sum33; 9 | assign Sum33 = A + B + Ci ; 10 | assign S = Sum33[31:0] ; 11 | assign Co = Sum33[32] ; 12 | endmodule 13 | -------------------------------------------------------------------------------- /32 bit adder/adder32_tb.v: -------------------------------------------------------------------------------- 1 | module adder32_tb; 2 | reg clk; 3 | reg[31:0]a,b; 4 | wire[31:0]sum; 5 | reg cin; 6 | wire cout; 7 | Adder32 DUT (.A(a),.B(b),.Ci(cin),.Co(cout),.S(sum)); 8 | initial begin 9 | #10; 10 | a=0; 11 | b=0; 12 | cin=0; 13 | clk=0; 14 | #10; 15 | end 16 | always @ (posedge clk) 17 | begin 18 | #50; 19 | #10 a=32'b11111111110000000000111111111100; 20 | #10 b=32'b11111111111111111111000000000011; 21 | end 22 | always # 10 clk=~clk; 23 | always @ (a or b) 24 | #50 $display($time,"clk=%b,a=%b,b=%b,cin=%b",$time,clk,a,b,cin); 25 | initial 26 | #100 $finish; 27 | endmodule 28 | -------------------------------------------------------------------------------- /Array Multiplier/array_multiplier.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Test134n/32-Verilog-Mini-Projects/f6458719db15c2b348ec63d70c5ab7572b771341/Array Multiplier/array_multiplier.jpg -------------------------------------------------------------------------------- /Array Multiplier/array_multiplier.v: -------------------------------------------------------------------------------- 1 | module array16(a,b,c); 2 | 3 | input [15:0]a,b; 4 | output [31:0]c; 5 | 6 | wire [15:0]q0,q1,q2,q3,q4,temp1; 7 | wire [31:0]c; 8 | wire [23:0]q5,q6,temp2,temp3,temp4; 9 | 10 | array8 z1(a[7:0],b[7:0],q0[15:0]); 11 | array8 z2(a[15:8],b[7:0],q1[15:0]); 12 | array8 z3(a[7:0],b[15:8],q2[15:0]); 13 | array8 z4(a[15:8],b[15:8],q3[15:0]); 14 | assign temp1 ={8'b0,q0[15:8]}; 15 | assign q4 = q1[15:0]+temp1; 16 | assign temp2 ={8'b0,q2[15:0]}; 17 | assign temp3 ={q3[15:0],8'b0}; 18 | assign q5 = temp2+temp3; 19 | assign temp4={8'b0,q4[15:0]}; 20 | 21 | assign q6 = temp4 + q5; 22 | 23 | assign c[7:0]=q0[7:0]; 24 | assign c[31:8]=q6[23:0]; 25 | 26 | endmodule 27 | 28 | module array2(a, b, c); 29 | input [1:0]a, b; 30 | output [3:0]c; 31 | wire [3:0]c, temp; 32 | 33 | assign c[0]=a[0]&b[0]; 34 | assign temp[0]=a[1]&b[0]; 35 | assign temp[1]=a[0]&b[1]; 36 | assign temp[2]=a[1]&b[1]; 37 | ha z1(temp[0],temp[1],c[1],temp[3]); 38 | ha z2(temp[2],temp[3],c[2],c[3]); 39 | 40 | endmodule 41 | 42 | module array4(a,b,c); 43 | input [3:0]a, b; 44 | output [7:0]c; 45 | 46 | wire [3:0]q0,q1,q2,q3,q4,temp1; 47 | 48 | wire [7:0]c; 49 | wire [5:0]q5,q6,temp2,temp3,temp4; 50 | 51 | array2 z1(a[1:0],b[1:0],q0[3:0]); 52 | array2 z2(a[3:2],b[1:0],q1[3:0]); 53 | array2 z3(a[1:0],b[3:2],q2[3:0]); 54 | array2 z4(a[3:2],b[3:2],q3[3:0]); 55 | 56 | assign temp1 ={2'b0,q0[3:2]}; 57 | assign q4 = q1[3:0]+temp1; 58 | assign temp2 ={2'b0,q2[3:0]}; 59 | assign temp3 ={q3[3:0],2'b0}; 60 | assign q5 = temp2+temp3; 61 | assign temp4={2'b0,q4[3:0]}; 62 | assign q6 = temp4+q5; 63 | 64 | assign c[1:0]=q0[1:0]; 65 | assign c[7:2]=q6[5:0]; 66 | endmodule 67 | 68 | module array8(a,b,c); 69 | input [7:0]a,b; 70 | output [15:0]c; 71 | 72 | wire [15:0]q0,q1,q2,q3,c; 73 | wire [7:0]q4,temp1; 74 | wire [11:0]q5,q6,temp2temp3,temp4; 75 | 76 | array4 z1(a[3:0],b[3:0],q0[15:0]); 77 | array4 z2(a[7:4],b[3:0],q1[15:0]); 78 | array4 z3(a[3:0],b[7:4],q2[15:0]); 79 | array4 z4(a[7:4],b[7:4],q3[15:0]); 80 | 81 | assign temp1 ={4'b0,q0[7:4]}; 82 | assign q4 = q1[7:0]+temp1; 83 | assign temp2 ={4'b0,q2[7:0]}; 84 | assign temp3 ={q3[7:0],4'b0}; 85 | assign q5 = temp2+temp3; 86 | assign temp4={4'b0,q4[7:0]}; 87 | 88 | 89 | assign q6 = temp4+q5; 90 | 91 | assign c[3:0]=q0[3:0]; 92 | assign c[15:4]=q6[11:0]; 93 | endmodule 94 | 95 | module ha(a,b,s,c); 96 | input a,b; 97 | output s,c; 98 | 99 | assign s = a^b; 100 | assign c = a&b; 101 | endmodule 102 | -------------------------------------------------------------------------------- /Barrel Shifter/barrel_shifter_8bit.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Test134n/32-Verilog-Mini-Projects/f6458719db15c2b348ec63d70c5ab7572b771341/Barrel Shifter/barrel_shifter_8bit.jpg -------------------------------------------------------------------------------- /Barrel Shifter/barrel_shifter_8bit.v: -------------------------------------------------------------------------------- 1 | module barrel_shifter_8bit (in, ctrl, out); 2 | input [7:0] in; 3 | input [2:0] ctrl; 4 | output [7:0] out; 5 | wire [7:0] x,y; 6 | 7 | //4bit shift right 8 | mux2X1 ins_17 (.in0(in[7]),.in1(1'b0),.sel(ctrl[2]),.out(x[7])); 9 | mux2X1 ins_16 (.in0(in[6]),.in1(1'b0),.sel(ctrl[2]),.out(x[6])); 10 | mux2X1 ins_15 (.in0(in[5]),.in1(1'b0),.sel(ctrl[2]),.out(x[5])); 11 | mux2X1 ins_14 (.in0(in[4]),.in1(1'b0),.sel(ctrl[2]),.out(x[4])); 12 | mux2X1 ins_13 (.in0(in[3]),.in1(in[7]),.sel(ctrl[2]),.out(x[3])); 13 | mux2X1 ins_12 (.in0(in[2]),.in1(in[6]),.sel(ctrl[2]),.out(x[2])); 14 | mux2X1 ins_11 (.in0(in[1]),.in1(in[5]),.sel(ctrl[2]),.out(x[1])); 15 | mux2X1 ins_10 (.in0(in[0]),.in1(in[4]),.sel(ctrl[2]),.out(x[0])); 16 | 17 | //2 bit shift right 18 | 19 | mux2X1 ins_27 (.in0(x[7]),.in1(1'b0),.sel(ctrl[1]),.out(y[7])); 20 | mux2X1 ins_26 (.in0(x[6]),.in1(1'b0),.sel(ctrl[1]),.out(y[6])); 21 | mux2X1 ins_25 (.in0(x[5]),.in1(x[7]),.sel(ctrl[1]),.out(y[5])); 22 | mux2X1 ins_24 (.in0(x[4]),.in1(x[6]),.sel(ctrl[1]),.out(y[4])); 23 | mux2X1 ins_23 (.in0(x[3]),.in1(x[5]),.sel(ctrl[1]),.out(y[3])); 24 | mux2X1 ins_22 (.in0(x[2]),.in1(x[4]),.sel(ctrl[1]),.out(y[2])); 25 | mux2X1 ins_21 (.in0(x[1]),.in1(x[3]),.sel(ctrl[1]),.out(y[1])); 26 | mux2X1 ins_20 (.in0(x[0]),.in1(x[2]),.sel(ctrl[1]),.out(y[0])); 27 | 28 | //1 bit shift right 29 | mux2X1 ins_07 (.in0(y[7]),.in1(1'b0),.sel(ctrl[0]),.out(out[7])); 30 | mux2X1 ins_06 (.in0(y[6]),.in1(y[7]),.sel(ctrl[0]),.out(out[6])); 31 | mux2X1 ins_05 (.in0(y[5]),.in1(y[6]),.sel(ctrl[0]),.out(out[5])); 32 | mux2X1 ins_04 (.in0(y[4]),.in1(y[5]),.sel(ctrl[0]),.out(out[4])); 33 | mux2X1 ins_03 (.in0(y[3]),.in1(y[4]),.sel(ctrl[0]),.out(out[3])); 34 | mux2X1 ins_02 (.in0(y[2]),.in1(y[3]),.sel(ctrl[0]),.out(out[2])); 35 | mux2X1 ins_01 (.in0(y[1]),.in1(y[2]),.sel(ctrl[0]),.out(out[1])); 36 | mux2X1 ins_00 (.in0(y[0]),.in1(y[1]),.sel(ctrl[0]),.out(out[0])); 37 | 38 | endmodule 39 | -------------------------------------------------------------------------------- /Barrel Shifter/barrel_shifter_8bit_tb.v: -------------------------------------------------------------------------------- 1 | module barrel_shifter_8bit_tb; 2 | reg [7:0] in; 3 | reg [2:0] ctrl; 4 | wire [7:0] out; 5 | 6 | barrel_shifter_8bit uut(.in(in), .ctrl(ctrl), .out(out)); 7 | 8 | initial 9 | begin 10 | $display($time, " << Starting the Simulation >>"); 11 | in= 8'd0; ctrl=3'd0; //no shift 12 | #10 in=8'd128; ctrl= 3'd4; //shift 4 bit 13 | #10 in=8'd128; ctrl= 3'd2; //shift 2 bit 14 | #10 in=8'd128; ctrl= 3'd1; //shift by 1 bit 15 | #10 in=8'd255; ctrl= 3'd7; //shift by 7bit 16 | end 17 | initial begin 18 | $monitor("Input=%d, Control=%d, Output=%d",in,ctrl,out); 19 | end 20 | endmodule 21 | -------------------------------------------------------------------------------- /Barrel Shifter/mux2X1.v: -------------------------------------------------------------------------------- 1 | module mux2X1( in0,in1,sel,out); 2 | input in0,in1; 3 | input sel; 4 | output out; 5 | assign out=(sel)?in1:in0; 6 | endmodule 7 | -------------------------------------------------------------------------------- /Binary Divider 16 by 8/binary_divider.v: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /Booth Multiplication/booth_multiplication.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Test134n/32-Verilog-Mini-Projects/f6458719db15c2b348ec63d70c5ab7572b771341/Booth Multiplication/booth_multiplication.jpg -------------------------------------------------------------------------------- /Booth Multiplication/booth_multiplication.v: -------------------------------------------------------------------------------- 1 | module invert(output ib,input b); 2 | assign ib = ~b; 3 | endmodule 4 | 5 | module and2 (input wire i0, i1, output wire o); 6 | assign o = i0 & i1; 7 | endmodule 8 | 9 | module or2 (input wire i0, i1, output wire o); 10 | assign o = i0 | i1; 11 | endmodule 12 | 13 | module xor2 (input wire i0, i1, output wire o); 14 | assign o = i0 ^ i1; 15 | endmodule 16 | 17 | module nand2 (input wire i0, i1, output wire o); 18 | wire t; 19 | and2 and2_0 (i0, i1, t); 20 | invert invert_0 (o, t); 21 | endmodule 22 | 23 | module nor2 (input wire i0, i1, output wire o); 24 | wire t; 25 | or2 or2_0 (i0, i1, t); 26 | invert invert_0 (o, t); 27 | endmodule 28 | 29 | module xnor2 (input wire i0, i1, output wire o); 30 | wire t; 31 | xor2 xor2_0 (i0, i1, t); 32 | invert invert_0 (o, t); 33 | endmodule 34 | 35 | module and3 (input wire i0, i1, i2, output wire o); 36 | wire t; 37 | and2 and2_0 (i0, i1, t); 38 | and2 and2_1 (i2, t, o); 39 | endmodule 40 | 41 | module or3 (input wire i0, i1, i2, output wire o); 42 | wire t; 43 | or2 or2_0 (i0, i1, t); 44 | or2 or2_1 (i2, t, o); 45 | endmodule 46 | 47 | module nor3 (input wire i0, i1, i2, output wire o); 48 | wire t; 49 | or2 or2_0 (i0, i1, t); 50 | nor2 nor2_0 (i2, t, o); 51 | endmodule 52 | 53 | module nand3 (input wire i0, i1, i2, output wire o); 54 | wire t; 55 | and2 and2_0 (i0, i1, t); 56 | nand2 nand2_1 (i2, t, o); 57 | endmodule 58 | 59 | module xor3 (input wire i0, i1, i2, output wire o); 60 | wire t; 61 | xor2 xor2_0 (i0, i1, t); 62 | xor2 xor2_1 (i2, t, o); 63 | endmodule 64 | 65 | module xnor3 (input wire i0, i1, i2, output wire o); 66 | wire t; 67 | xor2 xor2_0 (i0, i1, t); 68 | xnor2 xnor2_0 (i2, t, o); 69 | endmodule 70 | 71 | 72 | 73 | module fa (input wire i0, i1, cin, output wire sum, cout); 74 | wire t0, t1, t2; 75 | xor3 _i0 (i0, i1, cin, sum); 76 | and2 _i1 (i0, i1, t0); 77 | and2 _i2 (i1, cin, t1); 78 | and2 _i3 (cin, i0, t2); 79 | or3 _i4 (t0, t1, t2, cout); 80 | endmodule 81 | 82 | 83 | module Adder(a,b,sum); 84 | input [7:0] a,b; 85 | output [7:0]sum; 86 | wire cout; 87 | wire [7:0] q; 88 | fa fa1(a[0],b[0],1'b0,sum[0],q[0]); 89 | fa fa2(a[1],b[1],q[0],sum[1],q[1]); 90 | fa fa3(a[2],b[2],q[1],sum[2],q[2]); 91 | fa fa4(a[3],b[3],q[2],sum[3],q[3]); 92 | fa fa5(a[4],b[4],q[3],sum[4],q[4]); 93 | fa fa6(a[5],b[5],q[4],sum[5],q[5]); 94 | fa fa7(a[6],b[6],q[5],sum[6],q[6]); 95 | fa fa8(a[7],b[7],q[6],sum[7],cout); 96 | 97 | endmodule 98 | 99 | module subtractor(a,b,sum); 100 | input [7:0] a,b; 101 | output [7:0]sum; 102 | wire [7:0] ib; 103 | wire cout; 104 | invert b1(ib[0],b[0]); 105 | invert b2(ib[1],b[1]); 106 | invert b3(ib[2],b[2]); 107 | invert b4(ib[3],b[3]); 108 | invert b5(ib[4],b[4]); 109 | invert b6(ib[5],b[5]); 110 | invert b7(ib[6],b[6]); 111 | invert b8(ib[7],b[7]); 112 | 113 | wire [7:0] q; 114 | fa fa1(a[0],ib[0],1'b1,sum[0],q[0]); 115 | fa fa2(a[1],ib[1],q[0],sum[1],q[1]); 116 | fa fa3(a[2],ib[2],q[1],sum[2],q[2]); 117 | fa fa4(a[3],ib[3],q[2],sum[3],q[3]); 118 | fa fa5(a[4],ib[4],q[3],sum[4],q[4]); 119 | fa fa6(a[5],ib[5],q[4],sum[5],q[5]); 120 | fa fa7(a[6],ib[6],q[5],sum[6],q[6]); 121 | fa fa8(a[7],ib[7],q[6],sum[7],cout); 122 | 123 | endmodule 124 | 125 | 126 | 127 | module booth_substep(input wire signed [7:0]a,Q,input wire signed q0,input wire signed [7:0] m,output reg signed [7:0] f8,output reg signed [7:0] l8,output reg cq0); 128 | wire [7:0] addam,subam; 129 | Adder myadd(a,m,addam); 130 | subtractor mysub(a,m,subam); 131 | always @(*) begin 132 | if(Q[0] == q0) begin 133 | cq0 = Q[0]; 134 | l8 = Q>>1; 135 | l8[7] = a[0]; 136 | f8 = a>>1; 137 | if (a[7] == 1) 138 | f8[7] = 1; 139 | end 140 | 141 | else if(Q[0] == 1 && q0 ==0) begin 142 | cq0 = Q[0]; 143 | l8 = Q>>1; 144 | l8[7] = subam[0]; 145 | f8 = subam>>1; 146 | if (subam[7] == 1) 147 | f8[7] = 1; 148 | end 149 | 150 | else begin 151 | cq0 = Q[0]; 152 | l8 = Q>>1; 153 | l8[7] = addam[0]; 154 | f8 = addam>>1; 155 | if (addam[7] == 1) 156 | f8[7] = 1; 157 | end 158 | 159 | 160 | 161 | 162 | 163 | 164 | end 165 | endmodule 166 | 167 | 168 | 169 | 170 | 171 | 172 | module boothmul(input signed[7:0]a,b,output signed [15:0] c); 173 | wire signed [7:0]Q0,Q1,Q2,Q3,Q4,Q5,Q6,Q7; 174 | wire signed [7:0] m; 175 | wire signed [7:0] A1,A0,A3,A2; 176 | wire signed [7:0] A4,A5,A6,A7; 177 | wire signed[7:0] q0; 178 | wire qout; 179 | 180 | booth_substep step1(8'b00000000,a,1'b0,b,A1,Q1,q0[1]); 181 | booth_substep step2(A1,Q1,q0[1],b,A2,Q2,q0[2]); 182 | booth_substep step3(A2,Q2,q0[2],b,A3,Q3,q0[3]); 183 | booth_substep step4(A3,Q3,q0[3],b,A4,Q4,q0[4]); 184 | booth_substep step5(A4,Q4,q0[4],b,A5,Q5,q0[5]); 185 | booth_substep step6(A5,Q5,q0[5],b,A6,Q6,q0[6]); 186 | booth_substep step7(A6,Q6,q0[6],b,A7,Q7,q0[7]); 187 | booth_substep step8(A7,Q7,q0[7],b,c[15:8],c[7:0],qout); 188 | 189 | 190 | endmodule 191 | 192 | module tb; 193 | wire signed [15:0] z; 194 | reg signed [7:0] a,b; 195 | 196 | 197 | boothmul my_booth(.a(a),.b(b),.c(z)); 198 | 199 | initial begin 200 | end 201 | 202 | initial 203 | begin 204 | $monitor($time,"Multiplication: %d * %d = %d",a,b,z ); 205 | a = 8'b11110000; 206 | b = 8'b11110000; 207 | 208 | #10 209 | 210 | a = 8'b10010101; 211 | b = 8'b100000; 212 | 213 | #10 214 | 215 | a = 8'b0111; 216 | b = 8'b0; 217 | 218 | #10 219 | 220 | b = 8'b1; 221 | a = 8'b1; 222 | 223 | #10 224 | 225 | a = 8'b00111100; 226 | b = 8'b0101; 227 | 228 | #10 229 | 230 | a = 8'b10101010; 231 | b = 8'b100011; 232 | 233 | #10 234 | 235 | a = 8'b010001; 236 | b = 8'b11100; 237 | 238 | #10 239 | a = 8'b1000; 240 | b = 8'b10111111; 241 | 242 | end 243 | endmodule 244 | -------------------------------------------------------------------------------- /CRC Coding/CRC Coding.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Test134n/32-Verilog-Mini-Projects/f6458719db15c2b348ec63d70c5ab7572b771341/CRC Coding/CRC Coding.pdf -------------------------------------------------------------------------------- /CRC Coding/CRC_16_parallel/CRC_16_parallel.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Test134n/32-Verilog-Mini-Projects/f6458719db15c2b348ec63d70c5ab7572b771341/CRC Coding/CRC_16_parallel/CRC_16_parallel.jpg -------------------------------------------------------------------------------- /CRC Coding/CRC_16_parallel/CRC_16_parallel.v: -------------------------------------------------------------------------------- 1 | module CRC_16_parallel(clk,rst,load,d_finish,crc_in,crc_out); 2 | 3 | input clk; 4 | input rst; 5 | input load; 6 | input d_finish; 7 | input [7:0] crc_in; 8 | output [7:0] crc_out; 9 | reg [7:0] crc_out; 10 | reg [15:0] crc_reg; 11 | reg [1:0] count; 12 | reg [1:0] state; 13 | wire [15:0] next_crc_reg; // 14 | parameter idle = 2'b00; // 15 | parameter compute = 2'b01;// 16 | parameter finish = 2'b10; // 17 | // 18 | 19 | assign next_crc_reg[0] = (^crc_in[7:0]) ^ (^crc_reg[15:8]); 20 | assign next_crc_reg[1] = (^crc_in[6:0]) ^ (^crc_reg[15:9]); 21 | assign next_crc_reg[2] = crc_in[7] ^ crc_in[6] ^ crc_reg[9] ^ crc_reg[8]; 22 | assign next_crc_reg[3] = crc_in[6] ^ crc_in[5] ^ crc_reg[10] ^ 23 | crc_reg[9]; 24 | assign next_crc_reg[4] = crc_in[5] ^ crc_in[4] ^ crc_reg[11] ^ 25 | crc_reg[10]; 26 | assign next_crc_reg[5] = crc_in[4] ^ crc_in[3] ^ crc_reg[12] ^ 27 | crc_reg[11]; 28 | assign next_crc_reg[6] = crc_in[3] ^ crc_in[2] ^ crc_reg[13] ^ 29 | crc_reg[12]; 30 | assign next_crc_reg[7] = crc_in[2] ^ crc_in[1] ^ crc_reg[14] ^ 31 | crc_reg[13]; 32 | assign next_crc_reg[8] = crc_in[1] ^ crc_in[0] ^ crc_reg[15] ^ crc_reg[14] 33 | ^ crc_reg[0]; 34 | assign next_crc_reg[9] = crc_in[0] ^ crc_reg[15] ^ crc_reg[1]; 35 | assign next_crc_reg[14:10] = crc_reg[6:2]; 36 | assign next_crc_reg[15] = (^crc_in[7:0]) ^ (^crc_reg[15:7]); 37 | always@(posedge clk) // 38 | begin 39 | case(state) // 40 | idle:begin // 41 | if(load) // 42 | state <= compute; 43 | else 44 | state <= idle; 45 | end 46 | compute:begin 47 | if(d_finish)// 48 | state <= finish; 49 | else 50 | state <= compute; 51 | end 52 | finish:begin 53 | if(count==2)// 54 | state <= idle; 55 | else 56 | state <= finish; 57 | end 58 | endcase 59 | end 60 | always@(posedge clk or negedge rst)// 61 | if(rst) 62 | begin 63 | crc_reg[15:0] <= 16'b0000_0000_0000_0000;// 64 | state <= idle; 65 | count <= 2'b00; 66 | end 67 | else 68 | case(state) 69 | idle:begin // 70 | crc_reg[15:0] <= 16'b0000_0000_0000_0000; 71 | count <= 2'b00; // Reset count in idle 72 | end 73 | compute:begin // 74 | crc_reg[15:0]<= next_crc_reg[15:0]; 75 | crc_out[7:0] <= crc_in[7:0]; 76 | count <= 2'b00; // Reset count in compute 77 | end 78 | finish:begin // 79 | crc_reg[15:0] <= {crc_reg[7:0],8'b0000_0000}; 80 | crc_out[7:0] <= crc_reg[15:8]; 81 | count <= count + 1'b1; // Increment count in finish 82 | end 83 | endcase 84 | endmodule 85 | -------------------------------------------------------------------------------- /CRC Coding/CRC_16_parallel/CRC_16_parallel_tb.v: -------------------------------------------------------------------------------- 1 | // 2 | module CRC_16_parallel_test; 3 | reg clk; 4 | reg rst; 5 | reg load; 6 | reg d_finish; 7 | reg [7:0] crc_in; 8 | wire [7:0] crc_out; 9 | parameter clk_period = 40; 10 | 11 | initial 12 | begin 13 | #clk_period clk = 1; 14 | #clk_period rst = 1; 15 | #clk_period rst = 0; 16 | #clk_period crc_in[7:0] = 8'b1010_1010; // 17 | #clk_period load = 1; 18 | #clk_period load = 0; 19 | #clk_period d_finish = 0; 20 | #(10*clk_period) d_finish = 1; 21 | #clk_period d_finish = 0; 22 | end 23 | always #(clk_period/2) clk = ~clk; 24 | always #(clk_period) crc_in[7:0] = ~crc_in[7:0]; // 25 | // 26 | CRC_16_parallel u1(.clk(clk), .rst(rst), .load(load), .d_finish(d_finish), .crc_in(crc_in), .crc_out(crc_out)); 27 | endmodule 28 | -------------------------------------------------------------------------------- /CRC Coding/CRC_16_serial/CRC_16_serial.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Test134n/32-Verilog-Mini-Projects/f6458719db15c2b348ec63d70c5ab7572b771341/CRC Coding/CRC_16_serial/CRC_16_serial.jpg -------------------------------------------------------------------------------- /CRC Coding/CRC_16_serial/CRC_16_serial.v: -------------------------------------------------------------------------------- 1 | //module CRC_16_serial 2 | //Module function: The module is a coding circuit of crc-16 check code, which uses a serial linear shift stage 3 | module CRC_16_serial(clk,rst,load,d_finish,crc_in,crc_out); 4 | input clk; //Clk signal 5 | input rst; //Reset signal 6 | input load; //Start encoding the signal 7 | input d_finish; //Encode the end signal 8 | input crc_in; //The word input to be encoded 9 | output crc_out; //Code word output after encoding 10 | reg crc_out; //Code word output staging, 1bit 11 | reg [15:0] crc_reg; //Linear shift staging, 16bits 12 | reg [1:0] state; //State staging, 2bit 13 | reg [4:0] count; //Count staging, 5bit 14 | parameter idle = 2'b00; //Wait state 15 | parameter compute = 2'b01;//calculated status 16 | parameter finish = 2'b10; //Calculate the end state 17 | always@ (posedge clk) //executed each time the clk is triggered for a positive edge 18 | begin // can be seen as the upper parenthesis in the c language, and end can be seen as the lower parenthesis 19 | case (state) // Select case in state 20 | idle: begin // is the wait state 21 | if (load) //load signal enters the compute state effectively 22 | state <= compute; 23 | else 24 | state <= idle; 25 | end 26 | compute:begin //d_finish signal enters the finish state effectively 27 | if(d_finish) 28 | state <= finish; 29 | else 30 | state <= compute; 31 | end 32 | finish: begin // Determines whether the data in the 16 stagings is fully output 33 | if(count==16) 34 | state <= idle; 35 | else 36 | count <= count+1; 37 | end 38 | endcase 39 | end 40 | always@ (posedge clk or negedge rst)//whenever the clk positive trigger or rst negative edge trigger is executed 41 | if(rst) 42 | begin 43 | //crc_reg the initial value < pre-installed b0000_0000_0000_0000 15:0, 15:0, 16' 44 | count <= 5'b0_0000; 45 | state <= idle; 46 | end 47 | else 48 | case(state) 49 | idle:begin 50 | crc_reg[15:0] <= 16'b0000_0000_0000_0000; 51 | end 52 | compute:begin 53 | //Produces a polynomial x^16+x^15+x^2+1 54 | crc_reg[0] <= crc_reg[15] ^ crc_in; 55 | crc_reg[1] <= crc_reg[0]; 56 | crc_reg[2] <= crc_reg[1] ^ crc_reg[15] ^ crc_in; 57 | crc_reg[14:3] <= crc_reg[13:2]; 58 | crc_reg[15] <= crc_reg[14] ^ crc_reg[15] ^ crc_in; 59 | crc_out <= crc_in; // The input is the output 60 | end 61 | finish:begin 62 | crc_out <= crc_reg[15]; // Stager 15 as output 63 | crc_reg[15:0] <= {crc_reg[14:0],1'b0}; // Shift. 64 | end 65 | endcase 66 | endmodule 67 | 68 | 69 | 70 | 71 | 72 | -------------------------------------------------------------------------------- /CRC Coding/CRC_16_serial/CRC_16_serial_tb.v: -------------------------------------------------------------------------------- 1 | //Module CRC-16-test 2 | //Module function: The module is a crc16 check code serial coding circuit, 3 | //This encoding circuit encodes the data entered serially 4 | module CRC_16_serial_test; 5 | reg clk; 6 | reg rst; 7 | reg load; 8 | reg d_finish; 9 | reg crc_in; 10 | wire crc_out;//wire-net data, 1bit 11 | parameter clk_period = 40; //The clk cycle is 40ns 12 | initial //initializes the relevant value 13 | begin 14 | #clk_period clk = 1; 15 | #clk_period rst = 1; 16 | #clk_period rst = 0; 17 | #clk_period crc_in = 1; // Enter the data to be encoded 18 | #clk_period load = 1; 19 | #clk_period load = 0; 20 | #clk_period d_finish = 0; 21 | #(80*clk_period) d_finish = 1; 22 | #clk_period d_finish = 0; 23 | end 24 | always #(clk_period/2) clk = ~clk; //Change the power level every 20ns 25 | always #(2*clk_period) crc_in = ~crc_in; // change the input level for the word to be encoded every 80ns 26 | 27 | //Call the serial encoding module 28 | CRC_16_serial u1(.clk(clk), .rst(rst), .load(load), .d_finish(d_finish), .crc_in(crc_in), .crc_out(crc_out)); 29 | 30 | endmodule 31 | -------------------------------------------------------------------------------- /CRC Coding/CRC_32_parallel/CRC_32_parallel.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Test134n/32-Verilog-Mini-Projects/f6458719db15c2b348ec63d70c5ab7572b771341/CRC Coding/CRC_32_parallel/CRC_32_parallel.jpg -------------------------------------------------------------------------------- /CRC Coding/CRC_32_parallel/CRC_32_parallel.v: -------------------------------------------------------------------------------- 1 | // 2 | module CRC_32_parallel(clk,rst,load,d_finish,crc_in,crc_out); 3 | input clk; // 4 | input rst; // 5 | input load; // 6 | input d_finish; // 7 | input [7:0] crc_in; // 8 | output [7:0] crc_out; // 9 | reg [7:0] crc_out; // 10 | reg [31:0] crc_reg; // 11 | reg [1:0] count; // 12 | reg [1:0] state; // 13 | wire [31:0] next_crc_reg; // 14 | parameter idle = 2'b00; // 15 | parameter compute = 2'b01; // 16 | parameter finish = 2'b10; // 17 | // 18 | assign next_crc_reg[0] = crc_reg[24] ^ crc_reg[30] ^ crc_in[0] ^ 19 | crc_in[6]; 20 | assign next_crc_reg[1] = crc_reg[24] ^ crc_reg[25] ^ crc_reg[30] ^ 21 | crc_reg[31] ^ crc_in[0] ^ crc_in[1] ^ crc_in[6] ^ crc_in[7]; 22 | assign next_crc_reg[2] = crc_reg[24] ^ crc_reg[25] ^ crc_reg[26] ^ 23 | crc_reg[30] ^ crc_reg[31] ^ crc_in[0] ^ crc_in[1] ^ crc_in[2] ^ crc_in[6] 24 | ^ crc_in[7]; 25 | assign next_crc_reg[3] = crc_reg[25] ^ crc_reg[26] ^ crc_reg[27] ^ 26 | crc_reg[31] ^ crc_in[1] ^ crc_in[2] ^ crc_in[3] ^ crc_in[7]; 27 | assign next_crc_reg[4] = crc_reg[24] ^ crc_reg[26] ^ crc_reg[27] ^ 28 | crc_reg[28] ^ crc_reg[30] ^ crc_in[0] ^ crc_in[2] ^ crc_in[3] ^ crc_in[4] 29 | ^ crc_in[6]; 30 | assign next_crc_reg[5] = crc_reg[24] ^ crc_reg[25] ^ crc_reg[27] ^ 31 | crc_reg[28] ^ crc_reg[29] ^ crc_reg[30] ^ crc_reg[31] ^ crc_in[0] ^ 32 | crc_in[1] ^ crc_in[3] ^ crc_in[4] ^ crc_in[5] ^ crc_in[6] ^ crc_in[7]; 33 | assign next_crc_reg[6] = crc_reg[25] ^ crc_reg[26] ^ crc_reg[28] ^ 34 | crc_reg[29] ^ crc_reg[30] ^ crc_reg[31] ^ crc_in[1] ^ crc_in[2] ^ crc_in[4] 35 | ^ crc_in[5] ^ crc_in[6] ^ crc_in[7]; 36 | assign next_crc_reg[7] = crc_reg[24] ^ crc_reg[26] ^ crc_reg[27] ^ 37 | crc_reg[29] ^ crc_reg[31] ^ crc_in[0] ^ crc_in[2] ^ crc_in[3] ^ crc_in[5] 38 | ^ crc_in[7]; 39 | assign next_crc_reg[8] = crc_reg[0] ^ crc_reg[24] ^ crc_reg[25] ^ 40 | crc_reg[27] ^ crc_reg[28] ^ crc_in[0] ^ crc_in[1] ^ crc_in[3] ^ crc_in[4]; 41 | assign next_crc_reg[9] = crc_reg[1] ^ crc_reg[25] ^ crc_reg[26] ^ 42 | crc_reg[28] ^ crc_reg[29] ^ crc_in[1] ^ crc_in[2] ^ crc_in[4] ^ crc_in[5]; 43 | assign next_crc_reg[10] = crc_reg[2] ^ crc_reg[24] ^ crc_reg[26] ^ 44 | crc_reg[27] ^ crc_reg[29] ^ crc_in[0] ^ crc_in[2] ^ crc_in[3] ^ crc_in[5]; 45 | assign next_crc_reg[11] = crc_reg[3] ^ crc_reg[24] ^ crc_reg[25] ^ 46 | crc_reg[27] ^ crc_reg[28] ^ crc_in[0] ^ crc_in[1] ^ crc_in[3] ^ crc_in[4]; 47 | assign next_crc_reg[12] = crc_reg[4] ^ crc_reg[24] ^ crc_reg[25] ^ 48 | crc_reg[26] ^ crc_reg[28] ^ crc_reg[29] ^ crc_reg[30] ^ crc_in[0] ^ 49 | crc_in[1] ^ crc_in[2] ^ crc_in[4] ^ crc_in[5] ^ crc_in[6]; 50 | assign next_crc_reg[13] = crc_reg[5] ^ crc_reg[25] ^ crc_reg[26] ^ 51 | crc_reg[27] ^ crc_reg[29] ^ crc_reg[30] ^ crc_reg[31] ^ crc_in[1] ^ 52 | crc_in[2] ^ crc_in[3] ^ crc_in[5] ^ crc_in[6] ^ crc_in[7]; 53 | assign next_crc_reg[14] = crc_reg[6] ^ crc_reg[26] ^ crc_reg[27] ^ 54 | crc_reg[28] ^ crc_reg[30] ^ crc_reg[31] ^ crc_in[2] ^ crc_in[3] ^ crc_in[4] 55 | ^ crc_in[6] ^ crc_in[7]; 56 | assign next_crc_reg[15] = crc_reg[7] ^ crc_reg[27] ^ crc_reg[28] ^ 57 | crc_reg[29] ^ crc_reg[31] ^ crc_in[3] ^ crc_in[4] ^ crc_in[5] ^ crc_in[7]; 58 | assign next_crc_reg[16] = crc_reg[8] ^ crc_reg[24] ^ crc_reg[28] ^ 59 | crc_reg[29] ^ crc_in[0] ^ crc_in[4] ^ crc_in[5]; 60 | assign next_crc_reg[17] = crc_reg[9] ^ crc_reg[25] ^ crc_reg[29] ^ 61 | crc_reg[30] ^ crc_in[1] ^ crc_in[5] ^ crc_in[6]; 62 | assign next_crc_reg[18] = crc_reg[10] ^ crc_reg[26] ^ crc_reg[30] ^ 63 | crc_reg[31] ^ crc_in[2] ^ crc_in[6] ^ crc_in[7]; 64 | assign next_crc_reg[19] = crc_reg[11] ^ crc_reg[27] ^ crc_reg[31] ^ 65 | crc_in[3] ^ crc_in[7]; 66 | assign next_crc_reg[20] = crc_reg[12] ^ crc_reg[28] ^ crc_in[4]; 67 | assign next_crc_reg[21] = crc_reg[13] ^ crc_reg[29] ^ crc_in[5]; 68 | assign next_crc_reg[22] = crc_reg[14] ^ crc_reg[24] ^ crc_in[0]; 69 | assign next_crc_reg[23] = crc_reg[15] ^ crc_reg[24] ^ crc_reg[25] ^ 70 | crc_reg[30] ^ crc_in[0] ^ crc_in[1] ^ crc_in[6]; 71 | assign next_crc_reg[24] = crc_reg[16] ^ crc_reg[25] ^ crc_reg[26] ^ 72 | crc_reg[31] ^ crc_in[1] ^ crc_in[2] ^ crc_in[7]; 73 | assign next_crc_reg[25] = crc_reg[17] ^ crc_reg[26] ^ crc_reg[27] ^ 74 | crc_in[2] ^ crc_in[3]; 75 | assign next_crc_reg[26] = crc_reg[18] ^ crc_reg[24] ^ crc_reg[27] ^ 76 | crc_reg[28] ^ crc_reg[30] ^ crc_in[0] ^ crc_in[3] ^ crc_in[4] ^ crc_in[6]; 77 | assign next_crc_reg[27] = crc_reg[19] ^ crc_reg[25] ^ crc_reg[28] ^ 78 | crc_reg[29] ^ crc_reg[31] ^ crc_in[1] ^ crc_in[4] ^ crc_in[5] ^ crc_in[7]; 79 | assign next_crc_reg[28] = crc_reg[20] ^ crc_reg[26] ^ crc_reg[29] ^ 80 | crc_reg[30] ^ crc_in[2] ^ crc_in[5] ^ crc_in[6]; 81 | assign next_crc_reg[29] = crc_reg[21] ^ crc_reg[27] ^ crc_reg[30] ^ 82 | crc_reg[31] ^ crc_in[3] ^ crc_in[6] ^ crc_in[7]; 83 | assign next_crc_reg[30] = crc_reg[22] ^ crc_reg[28] ^ crc_reg[31] ^ 84 | crc_in[4] ^ crc_in[7]; 85 | assign next_crc_reg[31] = crc_reg[23] ^ crc_reg[29] ^ crc_in[5]; 86 | // 87 | always@(posedge clk) 88 | begin 89 | case(state) // 90 | idle:begin // 91 | if(load) //l 92 | state <= compute; 93 | else 94 | state <= idle; 95 | end 96 | compute:begin 97 | if(d_finish) // 98 | state <= finish; 99 | else 100 | state <= compute; 101 | end 102 | finish:begin 103 | if(count==2) // 104 | state <= idle; 105 | else 106 | state <= finish; 107 | end 108 | endcase 109 | end 110 | always@(posedge clk or negedge rst) // 111 | if(rst) 112 | begin 113 | crc_reg[31:0] <= 32'b0000_0000_0000_0000_0000_0000_0000_0000; // 114 | 115 | state <= idle; 116 | count <= 2'b00; 117 | end 118 | else 119 | case(state) 120 | idle:begin // 121 | crc_reg[31:0] <= 122 | 32'b0000_0000_0000_0000_0000_0000_0000_0000; 123 | end 124 | compute:begin // 125 | crc_reg[31:0]<= next_crc_reg[31:0]; 126 | crc_out[7:0] <= crc_in[7:0]; 127 | end 128 | finish:begin // 129 | crc_reg[31:0] <= {crc_reg[23:0],8'b0000_0000}; 130 | crc_out[7:0] <= crc_reg[31:24]; 131 | end 132 | endcase 133 | endmodule 134 | -------------------------------------------------------------------------------- /CRC Coding/CRC_32_parallel/CRC_32_parallel_tb.v: -------------------------------------------------------------------------------- 1 | // 2 | module CRC_32_parallel_test; 3 | reg clk; 4 | reg rst; 5 | reg load; 6 | reg d_finish; 7 | reg [7:0] crc_in; 8 | wire [7:0] crc_out; 9 | parameter clk_period = 40; 10 | // 11 | initial 12 | begin 13 | #clk_period clk = 1; 14 | #clk_period rst = 1; 15 | #clk_period rst = 0; 16 | #clk_period crc_in[7:0] = 8'b1010_1010; // 17 | #clk_period load = 1; 18 | #clk_period load = 0; 19 | #clk_period d_finish = 0; 20 | #(10*clk_period) d_finish = 1; 21 | #clk_period d_finish = 0; 22 | end 23 | always #(clk_period/2) clk = ~clk; 24 | always #(clk_period) crc_in[7:0] = ~crc_in[7:0]; // 25 | // 26 | CRC_32_parallel 27 | u1(.clk(clk), .rst(rst), .load(load), .d_finish(d_finish), .crc_in(crc_in), .crc_out(crc_out)); 28 | endmodule 29 | -------------------------------------------------------------------------------- /CRC Coding/CRC_32_serial/CRC_32_serial.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Test134n/32-Verilog-Mini-Projects/f6458719db15c2b348ec63d70c5ab7572b771341/CRC Coding/CRC_32_serial/CRC_32_serial.jpg -------------------------------------------------------------------------------- /CRC Coding/CRC_32_serial/CRC_32_serial.v: -------------------------------------------------------------------------------- 1 | module CRC_32_serial(clk,rst,load,d_finish,crc_in,crc_out); 2 | input clk; // 3 | input rst; // 4 | input load; // 5 | input d_finish; // 6 | input crc_in; // 7 | output crc_out; // 8 | reg crc_out; // 9 | reg [31:0] crc_reg; // 10 | reg [1:0] state; // 11 | reg [5:0] count; // 12 | parameter idle = 2'b00; // 13 | parameter compute = 2'b01; // 14 | parameter finish = 2'b10; // 15 | always@ (posedge clk) // 16 | begin // 17 | case (state) // 18 | idle: begin // 19 | if (load) // 20 | state <= compute; 21 | else 22 | state <= idle; 23 | end 24 | compute:begin // 25 | if(d_finish) 26 | state <= finish; 27 | else 28 | state <= compute; 29 | end 30 | finish: begin // 31 | if(count==32) 32 | state <= idle; 33 | else 34 | count <= count+1; 35 | end 36 | endcase 37 | end 38 | always@ (posedge clk or negedge rst)// 39 | if(rst) 40 | begin 41 | count <= 5'b0_0000; 42 | state <= idle; 43 | end 44 | else 45 | case(state) 46 | idle:begin 47 | crc_reg[31:0] <= 32'b0000_0000_0000_0000_0000_0000_0000_0000; 48 | end 49 | compute:begin 50 | //Produces a polynomial x^16+x^15+x^2+1 51 | crc_reg[0] <= crc_reg[31] ^ crc_in; 52 | crc_reg[1] <= crc_reg[0]; 53 | crc_reg[2] <= crc_reg[1] ^ crc_reg[31] ^ crc_in; 54 | crc_reg[30:3] <= crc_reg[29:2]; 55 | crc_reg[31] <= crc_reg[30] ^ crc_reg[31] ^ crc_in; 56 | crc_out <= crc_in; // 57 | end 58 | finish:begin 59 | crc_out <= crc_reg[31]; 60 | crc_reg[31:0] <= {crc_reg[30:0],1'b0}; 61 | end 62 | endcase 63 | endmodule 64 | -------------------------------------------------------------------------------- /CRC Coding/CRC_32_serial/CRC_32_serial_tb.v: -------------------------------------------------------------------------------- 1 | module CRC_32_serial_test; 2 | reg clk; 3 | reg rst; 4 | reg load; 5 | reg d_finish; 6 | reg crc_in; 7 | wire crc_out; 8 | parameter clk_period = 40; 9 | initial 10 | begin 11 | #clk_period clk = 1; 12 | #clk_period rst = 1; 13 | #clk_period rst = 0; 14 | #clk_period crc_in = 1; 15 | #clk_period load = 1; 16 | #clk_period load = 0; 17 | #clk_period d_finish = 0; 18 | #(80*clk_period) d_finish = 1; 19 | #clk_period d_finish = 0; 20 | end 21 | always #(clk_period/2) clk = ~clk; 22 | always #(2*clk_period) crc_in = ~crc_in; 23 | 24 | CRC_32_serial u1(.clk(clk), .rst(rst), .load(load), .d_finish(d_finish), .crc_in(crc_in), .crc_out(crc_out)); 25 | 26 | endmodule 27 | -------------------------------------------------------------------------------- /Carry Select and Carry Look Ahead Adder/carry_look_ahead_adder.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Test134n/32-Verilog-Mini-Projects/f6458719db15c2b348ec63d70c5ab7572b771341/Carry Select and Carry Look Ahead Adder/carry_look_ahead_adder.jpg -------------------------------------------------------------------------------- /Carry Select and Carry Look Ahead Adder/carry_look_ahead_adder.v: -------------------------------------------------------------------------------- 1 | module carry_look_ahead_16bit(a,b, cin, sum,cout); 2 | input [15:0] a,b; 3 | input cin; 4 | output [15:0] sum; 5 | output cout; 6 | wire c1,c2,c3; 7 | 8 | carry_look_ahead_4bit cla1 (.a(a[3:0]), .b(b[3:0]), .cin(cin), .sum(sum[3:0]), .cout(c1)); 9 | carry_look_ahead_4bit cla2 (.a(a[7:4]), .b(b[7:4]), .cin(c1), .sum(sum[7:4]), .cout(c2)); 10 | carry_look_ahead_4bit cla3(.a(a[11:8]), .b(b[11:8]), .cin(c2), .sum(sum[11:8]), .cout(c3)); 11 | carry_look_ahead_4bit cla4(.a(a[15:12]), .b(b[15:12]), .cin(c3), .sum(sum[15:12]), .cout(cout)); 12 | 13 | endmodule 14 | 15 | module carry_look_ahead_4bit(a,b, cin, sum,cout); 16 | input [3:0] a,b; 17 | input cin; 18 | output [3:0] sum; 19 | output cout; 20 | 21 | wire [3:0] p,g,c; 22 | 23 | assign p=a^b; 24 | assign g=a&b; 25 | 26 | assign c[0]=cin; 27 | assign c[1]= g[0]|(p[0]&c[0]); 28 | assign c[2]= g[1] | (p[1]&g[0]) | p[1]&p[0]&c[0]; 29 | assign c[3]= g[2] | (p[2]&g[1]) | p[2]&p[1]&g[0] | p[2]&p[1]&p[0]&c[0]; 30 | assign cout= g[3] | (p[3]&g[2]) | p[3]&p[2]&g[1] | p[3]&p[2]&p[1]&g[0] | p[3]&p[2]&p[1]&p[0]&c[0]; 31 | assign sum=p^c; 32 | 33 | endmodule 34 | 35 | module carry_look_ahead_16bit_tb; 36 | reg [15:0] a,b; 37 | reg cin; 38 | wire [15:0] sum; 39 | wire cout; 40 | 41 | carry_look_ahead_16bit uut(.a(a), .b(b),.cin(cin),.sum(sum),.cout(cout)); 42 | 43 | initial begin 44 | a=0; b=0; cin=0; 45 | #20 a=16'd2; b=16'd2; cin=1'd1; 46 | #20 a=16'd2; b=16'd3; cin=1'd1; 47 | #20 a=16'd18; b=16'd18; cin=1'd0; 48 | #20 a=16'd100; b=16'd0; cin=1'd1; 49 | end 50 | 51 | initial 52 | $monitor( "A=%d, B=%d, Cin= %d, Sum=%d, Cout=%d", a,b,cin,sum,cout); 53 | endmodule 54 | -------------------------------------------------------------------------------- /Carry Select and Carry Look Ahead Adder/carry_select_adder.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Test134n/32-Verilog-Mini-Projects/f6458719db15c2b348ec63d70c5ab7572b771341/Carry Select and Carry Look Ahead Adder/carry_select_adder.jpg -------------------------------------------------------------------------------- /Carry Select and Carry Look Ahead Adder/carry_select_adder.v: -------------------------------------------------------------------------------- 1 | module carry_select_adder_16bit(a, b, cin, sum, cout); 2 | input [15:0] a,b; 3 | input cin; 4 | output [15:0] sum; 5 | output cout; 6 | 7 | wire [2:0] c; 8 | 9 | ripple_carry_4_bit rca1( 10 | .a(a[3:0]), 11 | .b(b[3:0]), 12 | .cin(cin), 13 | .sum(sum[3:0]), 14 | .cout(c[0])); 15 | 16 | 17 | carry_select_adder_4bit_slice csa_slice1( 18 | .a(a[7:4]), 19 | .b(b[7:4]), 20 | .cin(c[0]), 21 | .sum(sum[7:4]), 22 | .cout(c[1])); 23 | 24 | carry_select_adder_4bit_slice csa_slice2( 25 | .a(a[11:8]), 26 | .b(b[11:8]), 27 | .cin(c[1]), 28 | .sum(sum[11:8]), 29 | .cout(c[2])); 30 | 31 | carry_select_adder_4bit_slice csa_slice3( 32 | .a(a[15:12]), 33 | .b(b[15:12]), 34 | .cin(c[2]), 35 | .sum(sum[15:12]), 36 | .cout(cout)); 37 | endmodule 38 | 39 | 40 | module carry_select_adder_4bit_slice(a, b, cin, sum, cout); 41 | input [3:0] a,b; 42 | input cin; 43 | output [3:0] sum; 44 | output cout; 45 | 46 | wire [3:0] s0,s1; 47 | wire c0,c1; 48 | 49 | ripple_carry_4_bit rca1( 50 | .a(a[3:0]), 51 | .b(b[3:0]), 52 | .cin(1'b0), 53 | .sum(s0[3:0]), 54 | .cout(c0)); 55 | 56 | ripple_carry_4_bit rca2( 57 | .a(a[3:0]), 58 | .b(b[3:0]), 59 | .cin(1'b1), 60 | .sum(s1[3:0]), 61 | .cout(c1)); 62 | 63 | mux2X1 #(4) ms0( 64 | .in0(s0[3:0]), 65 | .in1(s1[3:0]), 66 | .sel(cin), 67 | .out(sum[3:0])); 68 | 69 | mux2X1 #(1) mc0( 70 | .in0(c0), 71 | .in1(c1), 72 | .sel(cin), 73 | .out(cout)); 74 | endmodule 75 | 76 | 77 | module mux2X1( in0,in1,sel,out); 78 | parameter width=16; 79 | input [width-1:0] in0,in1; 80 | input sel; 81 | output [width-1:0] out; 82 | assign out=(sel)?in1:in0; 83 | endmodule 84 | 85 | 86 | module ripple_carry_4_bit(a, b, cin, sum, cout); 87 | input [3:0] a,b; 88 | input cin; 89 | output [3:0] sum; 90 | output cout; 91 | 92 | wire c1,c2,c3; 93 | 94 | full_adder fa0( 95 | .a(a[0]), 96 | .b(b[0]), 97 | .cin(cin), 98 | .sum(sum[0]), 99 | .cout(c1)); 100 | 101 | full_adder fa1( 102 | .a(a[1]), 103 | .b(b[1]), 104 | .cin(c1), 105 | .sum(sum[1]), 106 | .cout(c2)); 107 | 108 | full_adder fa2( 109 | .a(a[2]), 110 | .b(b[2]), 111 | .cin(c2), 112 | .sum(sum[2]), 113 | .cout(c3)); 114 | 115 | full_adder fa3( 116 | .a(a[3]), 117 | .b(b[3]), 118 | .cin(c3), 119 | .sum(sum[3]), 120 | .cout(cout)); 121 | endmodule 122 | 123 | 124 | module full_adder(a,b,cin,sum, cout); 125 | input a,b,cin; 126 | output sum, cout; 127 | 128 | wire x,y,z; 129 | 130 | half_adder h1(.a(a), .b(b), .sum(x), .cout(y)); 131 | half_adder h2(.a(x), .b(cin), .sum(sum), .cout(z)); 132 | or or_1(cout,z,y); 133 | endmodule 134 | 135 | 136 | module half_adder( a,b, sum, cout ); 137 | input a,b; 138 | output sum, cout; 139 | xor xor_1 (sum,a,b); 140 | and and_1 (cout,a,b); 141 | endmodule 142 | 143 | module carry_select_adder_16bit_tb; 144 | reg [15:0] a,b; 145 | reg cin; 146 | wire [15:0] sum; 147 | wire cout; 148 | 149 | carry_select_adder_16bit uut(.a(a), .b(b),.cin(cin),.sum(sum),.cout(cout)); 150 | 151 | initial begin 152 | a=0; b=0; cin=0; 153 | #10 a=16'd2; b=16'd2; cin=1'd1; 154 | #10 a=16'd2; b=16'd4; cin=1'd1; 155 | #10 a=16'd100; b=16'd0; cin=1'd0; 156 | #10 a=16'd12; b=16'd3; cin=1'd1; 157 | end 158 | 159 | initial 160 | $monitor( "A=%d, B=%d, Cin= %d, Sum=%d, Cout=%d", a,b,cin,sum,cout); 161 | endmodule 162 | -------------------------------------------------------------------------------- /Carry Skip and Carry Save Adder/carry_save_adder.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Test134n/32-Verilog-Mini-Projects/f6458719db15c2b348ec63d70c5ab7572b771341/Carry Skip and Carry Save Adder/carry_save_adder.jpg -------------------------------------------------------------------------------- /Carry Skip and Carry Save Adder/carry_save_adder.v: -------------------------------------------------------------------------------- 1 | module carry_save_adder(a,b,c,d, sum,cout); 2 | input [3:0] a, b,c,d; 3 | output [4:0] sum; 4 | output cout; 5 | 6 | wire [3:0] s0,s1; 7 | wire [3:0] c0, c1; 8 | 9 | //1st Statge 10 | full_adder fa0( .a(a[0]), .b(b[0]), .cin(c[0]), .sum(s0[0]), .cout(c0[0])); 11 | full_adder fa1( .a(a[1]), .b(b[1]), .cin(c[1]), .sum(s0[1]), .cout(c0[1])); 12 | full_adder fa2( .a(a[2]), .b(b[2]), .cin(c[2]), .sum(s0[2]), .cout(c0[2])); 13 | full_adder fa3( .a(a[3]), .b(b[3]), .cin(c[3]), .sum(s0[3]), .cout(c0[3])); 14 | 15 | //2nd Stage 16 | full_adder fa4( .a(d[0]), .b(s0[0]), .cin(1'b0), .sum(sum[0]), .cout(c1[0])); 17 | full_adder fa5( .a(d[1]), .b(s0[1]), .cin(c0[0]), .sum(s1[0]), .cout(c1[1])); 18 | full_adder fa6( .a(d[2]), .b(s0[2]), .cin(c0[1]), .sum(s1[1]), .cout(c1[2])); 19 | full_adder fa7( .a(d[3]), .b(s0[3]), .cin(c0[2]), .sum(s1[2]), .cout(c1[3])); 20 | 21 | ripple_carry_4_bit rca1 (.a(c1[3:0]),.b({c0[3],s1[2:0]}), .cin(1'b0),.sum(sum[4:1]), .cout(cout)); 22 | 23 | endmodule 24 | 25 | 26 | module ripple_carry_4_bit(a, b, cin, sum, cout); 27 | input [3:0] a,b; 28 | input cin; 29 | wire c1,c2,c3; 30 | output [3:0] sum; 31 | output cout; 32 | 33 | full_adder fa0(.a(a[0]), .b(b[0]),.cin(cin), .sum(sum[0]),.cout(c1)); 34 | full_adder fa1(.a(a[1]), .b(b[1]), .cin(c1), .sum(sum[1]),.cout(c2)); 35 | full_adder fa2(.a(a[2]), .b(b[2]), .cin(c2), .sum(sum[2]),.cout(c3)); 36 | full_adder fa3(.a(a[3]), .b(b[3]), .cin(c3), .sum(sum[3]),.cout(cout)); 37 | endmodule 38 | 39 | 40 | module full_adder(a,b,cin,sum, cout); 41 | input a,b,cin; 42 | output sum, cout; 43 | wire x,y,z; 44 | half_adder h1(.a(a), .b(b), .sum(x), .cout(y)); 45 | half_adder h2(.a(x), .b(cin), .sum(sum), .cout(z)); 46 | assign cout= y|z; 47 | endmodule 48 | 49 | 50 | module half_adder( a,b, sum, cout ); 51 | input a,b; 52 | output sum, cout; 53 | assign sum= a^b; 54 | assign cout= a & b; 55 | endmodule 56 | 57 | module carry_save_tb; 58 | wire [4:0] sum; 59 | wire cout; 60 | reg [3:0] a,b,c,d; 61 | 62 | carry_save_adder uut( 63 | .a(a), 64 | .b(b), 65 | .c(c), 66 | .d(d), 67 | .sum(sum), 68 | .cout(cout)); 69 | 70 | initial begin 71 | $display($time, " Starting the Simulation"); 72 | a=0; b=0; c=0; d=0; 73 | #100 a= 4'd10; b=4'd0; c=4'd0; d=4'd0; 74 | #100 a= 4'd10; b=4'd10; c=4'd0; d=4'd0; 75 | #100 a= 4'd4; b=4'd6; c=4'd12; d=4'd0; 76 | #100 a= 4'd11; b=4'd2; c=4'd4; d=4'd7; 77 | #100 a= 4'd20; b=4'd0; c=4'd20; d=4'd0; 78 | #100 a= 4'd12; b=4'd5; c=4'd10; d=4'd10; 79 | #100 a= 4'd7; b=4'd6; c=4'd12; d=4'd8; 80 | #100 a= 4'd15; b=4'd15; c=4'd15; d=4'd15; 81 | 82 | end 83 | 84 | initial 85 | $monitor("A=%d, B=%d, C=%d,D=%d,Sum= %d, Cout=%d",a,b,c,d,sum,cout); 86 | endmodule 87 | -------------------------------------------------------------------------------- /Carry Skip and Carry Save Adder/carry_skip_adder.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Test134n/32-Verilog-Mini-Projects/f6458719db15c2b348ec63d70c5ab7572b771341/Carry Skip and Carry Save Adder/carry_skip_adder.jpg -------------------------------------------------------------------------------- /Carry Skip and Carry Save Adder/carry_skip_adder.v: -------------------------------------------------------------------------------- 1 | module carry_skip_16bit(a, b, cin, sum, cout); 2 | input [15:0] a,b; 3 | input cin; 4 | output cout; 5 | output [15:0] sum; 6 | 7 | wire [2:0] c; 8 | 9 | carry_skip_4bit csa1(.a(a[3:0]), .b(b[3:0]), .cin(cin), .sum(sum[3:0]), .cout(c[0])); 10 | carry_skip_4bit csa2 (.a(a[7:4]), .b(b[7:4]), .cin(c[0]), .sum(sum[7:4]), .cout(c[1])); 11 | carry_skip_4bit csa3(.a(a[11:8]), .b(b[11:8]), .cin(c[1]), .sum(sum[11:8]), .cout(c[2])); 12 | carry_skip_4bit csa4(.a(a[15:12]), .b(b[15:12]), .cin(c[2]), .sum(sum[15:12]), .cout(cout)); 13 | 14 | endmodule 15 | 16 | module carry_skip_4bit(a, b, cin, sum, cout); 17 | input [3:0] a,b; 18 | input cin; 19 | output [3:0] sum; 20 | output cout; 21 | wire [3:0] p; 22 | wire c0; 23 | wire bp; 24 | 25 | ripple_carry_4_bit rca1 (.a(a[3:0]), .b(b[3:0]), .cin(cin), .sum(sum[3:0]), .cout(c0)); 26 | generate_p p1(a,b,p,bp); 27 | mux2X1 m0(.in0(c0),.in1(cin),.sel(bp),.out(cout)); 28 | 29 | endmodule 30 | 31 | module generate_p(a,b,p,bp); 32 | input [3:0] a,b; 33 | output [3:0] p; 34 | output bp; 35 | assign p= a^b; 36 | assign bp= &p; 37 | endmodule 38 | 39 | 40 | module ripple_carry_4_bit(a, b, cin, sum, cout); 41 | input [3:0] a,b; 42 | input cin; 43 | wire c1,c2,c3; 44 | output [3:0] sum; 45 | output cout; 46 | 47 | full_adder fa0(.a(a[0]), .b(b[0]),.cin(cin), .sum(sum[0]),.cout(c1)); 48 | full_adder fa1(.a(a[1]), .b(b[1]), .cin(c1), .sum(sum[1]),.cout(c2)); 49 | full_adder fa2(.a(a[2]), .b(b[2]), .cin(c2), .sum(sum[2]),.cout(c3)); 50 | full_adder fa3(.a(a[3]), .b(b[3]), .cin(c3), .sum(sum[3]),.cout(cout)); 51 | endmodule 52 | 53 | module full_adder(a,b,cin,sum, cout); 54 | input a,b,cin; 55 | output sum, cout; 56 | wire x,y,z; 57 | half_adder h1(.a(a), .b(b), .sum(x), .cout(y)); 58 | half_adder h2(.a(x), .b(cin), .sum(sum), .cout(z)); 59 | or or_1(cout,z,y); 60 | endmodule 61 | 62 | 63 | module half_adder( a,b, sum, cout ); 64 | input a,b; 65 | output sum, cout; 66 | xor xor_1 (sum,a,b); 67 | and and_1 (cout,a,b); 68 | endmodule 69 | 70 | 71 | module mux2X1( in0,in1,sel,out); 72 | input in0,in1; 73 | input sel; 74 | output out; 75 | assign out=(sel)?in1:in0; 76 | endmodule 77 | 78 | 79 | module carry_skip_16bit_tb; 80 | wire [15:0] sum; 81 | wire cout; 82 | reg [15:0] a,b; 83 | reg cin; 84 | 85 | carry_skip_16bit uut(.a(a),.b(b),.cin(cin),.sum(sum),.cout(cout)); 86 | 87 | initial begin 88 | a=0; b=0; cin=0; 89 | #10 a= 16'b0000000000000101; b=16'b000000000000101; cin=1'b1; 90 | #10 a= 16'b0000000000011111; b=16'b000000000001100; cin=1'b0; 91 | #10 a= 16'b0000000000011111; b=16'b000000000001100; cin=1'b0; 92 | #10 a= 16'b1100011000011111; b=16'b000000110001100; cin=1'b1; 93 | #10 a= 16'b1111111111111111; b=16'b000000000000000; cin=1'b1; 94 | #10 a =16'b0000000000000001; b=16'b000000000000001; cin=1'b1; 95 | #10 a =16'b0000000000000010; b=16'b000000000000010; cin=1'b1; 96 | end 97 | 98 | initial 99 | $monitor("time= ", $time, "A=%b, B=&b, Cin=%b : Sum= %b, Cout=%cout",a,b,cin,sum,cout); 100 | endmodule 101 | -------------------------------------------------------------------------------- /Complex Multiplier/complex_multiplication.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Test134n/32-Verilog-Mini-Projects/f6458719db15c2b348ec63d70c5ab7572b771341/Complex Multiplier/complex_multiplication.jpg -------------------------------------------------------------------------------- /Complex Multiplier/complex_multiplication.v: -------------------------------------------------------------------------------- 1 | module compmul(c1,c2,product); 2 | input [15:0]c1,c2; 3 | output [31:0]product; 4 | assign product={((c1[15:8]*c2[15:8])-(c1[7:0]*c2[7:0])),((c1[15:8]*c2[7:0])+(c1[7:0]*c2[15:8]))}; 5 | endmodule 6 | 7 | module compmul_tb(); 8 | reg [15:0]c1,c2; 9 | wire [31:0]product; 10 | compmul a(c1,c2,product); 11 | initial 12 | begin 13 | c1<=16'b0000001000000010; 14 | c2<=16'b0000011000000010; 15 | #50 16 | $display("output for mul %b",product); 17 | c1<=16'b00001111100001000; 18 | c2<=16'b00000000000010000; 19 | #50 20 | $display("output for mul %b",product); 21 | c1<=16'b0000101110001000; 22 | c2<=16'b0000000000001000; 23 | #50 24 | $display("output for mul %b",product); 25 | c1<=16'b0000100000001000; 26 | c2<=16'b0001111000001000; 27 | #50 28 | $display("output for mul %b",product); 29 | c1<=16'b0000100001101000; 30 | c2<=16'b0000001000001000; 31 | #50 32 | $display("output for mul %b",product); 33 | c1<=16'b0000100000001000; 34 | c2<=16'b0001111111101000; 35 | #50 36 | $display("output for mul %b",product); 37 | c1<=16'b1111111111111111; 38 | c2<=16'b1111111111111111; 39 | #50 40 | $display("output for mul %b",product); 41 | 42 | end 43 | endmodule 44 | 45 | 46 | 47 | -------------------------------------------------------------------------------- /Dice Game/dice_game.v: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /FIFO/fifo.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Test134n/32-Verilog-Mini-Projects/f6458719db15c2b348ec63d70c5ab7572b771341/FIFO/fifo.jpg -------------------------------------------------------------------------------- /FIFO/fifo.v: -------------------------------------------------------------------------------- 1 | module FIFObuffer( Clk, 2 | 3 | dataIn, 4 | 5 | RD, 6 | 7 | WR, 8 | 9 | EN, 10 | 11 | dataOut, 12 | 13 | Rst, 14 | 15 | EMPTY, 16 | 17 | FULL 18 | 19 | ); 20 | 21 | input Clk, 22 | 23 | RD, 24 | 25 | WR, 26 | 27 | EN, 28 | 29 | Rst; 30 | 31 | output EMPTY, 32 | 33 | FULL; 34 | 35 | input [31:0] dataIn; 36 | 37 | output reg [31:0] dataOut; // internal registers 38 | 39 | reg [3:0] Count = 0; 40 | 41 | reg [31:0] FIFO [0:7]; 42 | 43 | reg [3:0] readCounter = 0, 44 | 45 | writeCounter = 0; 46 | 47 | assign EMPTY = (Count==0)? 1'b1:1'b0; 48 | 49 | assign FULL = (Count==8)? 1'b1:1'b0; 50 | 51 | always @ (posedge Clk) 52 | 53 | begin 54 | 55 | if (EN==0); 56 | 57 | else begin 58 | 59 | if (Rst) begin 60 | 61 | readCounter = 0; 62 | 63 | writeCounter = 0; 64 | 65 | end 66 | 67 | else if (RD ==1'b1 && Count!=0) begin 68 | 69 | dataOut = FIFO[readCounter]; 70 | 71 | readCounter = readCounter+1; 72 | 73 | end 74 | 75 | else if (WR==1'b1 && Count<8) begin 76 | FIFO[writeCounter] = dataIn; 77 | 78 | writeCounter = writeCounter+1; 79 | 80 | end 81 | 82 | else; 83 | 84 | end 85 | 86 | if (writeCounter==8) 87 | 88 | writeCounter=0; 89 | 90 | else if (readCounter==8) 91 | 92 | readCounter=0; 93 | 94 | else; 95 | 96 | if (readCounter > writeCounter) begin 97 | 98 | Count=readCounter-writeCounter; 99 | 100 | end 101 | 102 | else if (writeCounter > readCounter) 103 | 104 | Count=writeCounter-readCounter; 105 | 106 | else; 107 | 108 | end 109 | 110 | endmodule 111 | -------------------------------------------------------------------------------- /FIFO/fifo_tb.v: -------------------------------------------------------------------------------- 1 | 2 | `timescale 1ns / 1ps 3 | 4 | module FIFObuffer_tb; 5 | 6 | // Inputs 7 | 8 | reg Clk; 9 | 10 | reg [31:0] dataIn; 11 | 12 | reg RD; 13 | 14 | reg WR; 15 | 16 | reg EN; 17 | 18 | reg Rst; 19 | 20 | // Outputs 21 | 22 | wire [31:0] dataOut; 23 | 24 | wire EMPTY; 25 | 26 | wire FULL; 27 | 28 | // Instantiate the Unit Under Test (UUT) 29 | 30 | FIFObuffer uut ( 31 | 32 | .Clk(Clk), 33 | 34 | .dataIn(dataIn), 35 | 36 | .RD(RD), 37 | 38 | .WR(WR), 39 | 40 | .EN(EN), 41 | 42 | .dataOut(dataOut), 43 | 44 | .Rst(Rst), 45 | 46 | .EMPTY(EMPTY), 47 | 48 | .FULL(FULL) 49 | 50 | ); 51 | 52 | initial begin 53 | 54 | // Initialize Inputs 55 | 56 | Clk = 1'b0; 57 | 58 | dataIn = 32'h0; 59 | 60 | RD = 1'b0; 61 | 62 | WR = 1'b0; 63 | 64 | EN = 1'b0; 65 | 66 | Rst = 1'b1; 67 | 68 | // Wait 100 ns for global reset to finish 69 | 70 | #100; 71 | 72 | // Add stimulus here 73 | 74 | EN = 1'b1; 75 | 76 | Rst = 1'b1; 77 | 78 | #20; 79 | 80 | Rst = 1'b0; 81 | 82 | WR = 1'b1; 83 | 84 | dataIn = 32'h0; 85 | 86 | #20; 87 | 88 | dataIn = 32'h1; 89 | 90 | #20; 91 | 92 | dataIn = 32'h2; 93 | 94 | #20; 95 | 96 | dataIn = 32'h3; 97 | 98 | #20; 99 | 100 | dataIn = 32'h4; 101 | 102 | #20; 103 | 104 | WR = 1'b0; 105 | 106 | RD = 1'b1; 107 | 108 | end 109 | 110 | always #10 Clk = ~Clk; 111 | 112 | endmodule 113 | -------------------------------------------------------------------------------- /Fixed Point Adder and Subtractor/fixed_point_adder.v: -------------------------------------------------------------------------------- 1 | module qadd #( 2 | //Parameterized values 3 | parameter Q = 15, 4 | parameter N = 32 5 | ) 6 | ( 7 | input [N-1:0] a, 8 | input [N-1:0] b, 9 | output [N-1:0] c 10 | ); 11 | 12 | reg [N-1:0] res; 13 | 14 | assign c = res; 15 | 16 | always @(a,b) begin 17 | // both negative or both positive 18 | if(a[N-1] == b[N-1]) begin 19 | res[N-2:0] = a[N-2:0] + b[N-2:0]; 20 | res[N-1] = a[N-1]; 21 | 22 | 23 | end 24 | // one of them is negative... 25 | else if(a[N-1] == 0 && b[N-1] == 1) begin 26 | if( a[N-2:0] > b[N-2:0] ) begin 27 | res[N-2:0] = a[N-2:0] - b[N-2:0]; 28 | res[N-1] = 0; 29 | end 30 | else begin 31 | res[N-2:0] = b[N-2:0] - a[N-2:0]; 32 | if (res[N-2:0] == 0) 33 | res[N-1] = 0; 34 | else 35 | res[N-1] = 1; 36 | end 37 | end 38 | else begin 39 | if( a[N-2:0] > b[N-2:0] ) begin 40 | res[N-2:0] = a[N-2:0] - b[N-2:0]; 41 | if (res[N-2:0] == 0) 42 | res[N-1] = 0; 43 | else 44 | res[N-1] = 1; 45 | end 46 | else begin 47 | res[N-2:0] = b[N-2:0] - a[N-2:0]; 48 | res[N-1] = 0; 49 | end 50 | end 51 | end 52 | endmodule 53 | 54 | module Test_add; 55 | 56 | // Inputs 57 | reg [31:0] a; 58 | reg [31:0] b; 59 | 60 | // Outputs 61 | wire [31:0] c; 62 | 63 | // Instantiate the Unit Under Test (UUT) 64 | qadd #(19,32) uut ( 65 | .a(a), 66 | .b(b), 67 | .c(c) 68 | ); 69 | 70 | // These are to monitor the values... 71 | wire [30:0] c_out; 72 | wire [30:0] a_in; 73 | wire [30:0] b_in; 74 | wire a_sign; 75 | wire b_sign; 76 | wire c_sign; 77 | 78 | 79 | assign a_in = a[30:0]; 80 | assign b_in = b[30:0]; 81 | assign c_out = c[30:0]; 82 | assign a_sign = a[31]; 83 | assign b_sign = b[31]; 84 | assign c_sign = c[31]; 85 | 86 | 87 | initial begin 88 | // Initialize Inputs 89 | a[30:0] = 0; 90 | a[31] = 0; 91 | b[31] = 1; 92 | b[30:0] = 0; 93 | 94 | // Wait 100 ns for global reset to finish 95 | #100; 96 | 97 | // Add stimulus here 98 | forever begin 99 | #1 a = a+5179347; 100 | a[31] = 0; // a is negative... 101 | b[31] = 1; 102 | 103 | 104 | if (a[30:0] > 2.1E9) // input will always be "positive" 105 | begin 106 | a = 0; 107 | b[31] = 1; // b is negative... 108 | b[30:0] = b[30:0] + 3779351; 109 | end 110 | end 111 | 112 | end 113 | 114 | endmodule 115 | -------------------------------------------------------------------------------- /Fixed Point Adder and Subtractor/fixed_point_adder1.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Test134n/32-Verilog-Mini-Projects/f6458719db15c2b348ec63d70c5ab7572b771341/Fixed Point Adder and Subtractor/fixed_point_adder1.jpg -------------------------------------------------------------------------------- /Fixed Point Adder and Subtractor/fixed_point_adder2.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Test134n/32-Verilog-Mini-Projects/f6458719db15c2b348ec63d70c5ab7572b771341/Fixed Point Adder and Subtractor/fixed_point_adder2.jpg -------------------------------------------------------------------------------- /Fixed Point Adder and Subtractor/fixed_point_subtractor.v: -------------------------------------------------------------------------------- 1 | module qsubtract #( 2 | //Parameterized values 3 | parameter Q = 15, 4 | parameter N = 32 5 | ) 6 | ( 7 | input [N-1:0] a, 8 | input [N-1:0] b, 9 | output [N-1:0] c 10 | ); 11 | 12 | reg [N-1:0] res; 13 | 14 | assign c = res; 15 | 16 | always @(a,b) begin 17 | // both negative or both positive 18 | if(a[N-1] == b[N-1]) begin 19 | res[N-2:0] = a[N-2:0] - b[N-2:0]; 20 | res[N-1] = a[N-1]; 21 | 22 | 23 | end 24 | // one of them is negative... 25 | else if(a[N-1] == 0 && b[N-1] == 1) begin 26 | if( a[N-2:0] > b[N-2:0] ) begin 27 | res[N-2:0] = a[N-2:0] + b[N-2:0]; 28 | res[N-1] = 0; 29 | end 30 | else begin 31 | res[N-2:0] = b[N-2:0] + a[N-2:0]; 32 | if (res[N-2:0] == 0) 33 | res[N-1] = 0; 34 | else 35 | res[N-1] = 1; 36 | end 37 | end 38 | else begin 39 | if( a[N-2:0] > b[N-2:0] ) begin 40 | res[N-2:0] = a[N-2:0] + b[N-2:0]; 41 | if (res[N-2:0] == 0) 42 | res[N-1] = 0; 43 | else 44 | res[N-1] = 1; 45 | end 46 | else begin 47 | res[N-2:0] = b[N-2:0] + a[N-2:0]; 48 | res[N-1] = 0; 49 | end 50 | end 51 | end 52 | endmodule 53 | 54 | module Test_subtract; 55 | 56 | // Inputs 57 | reg [31:0] a; 58 | reg [31:0] b; 59 | 60 | // Outputs 61 | wire [31:0] c; 62 | 63 | // Instantiate the Unit Under Test (UUT) 64 | qsubtract #(19,32) uut ( 65 | .a(a), 66 | .b(b), 67 | .c(c) 68 | ); 69 | 70 | // These are to monitor the values... 71 | wire [30:0] c_out; 72 | wire [30:0] a_in; 73 | wire [30:0] b_in; 74 | wire a_sign; 75 | wire b_sign; 76 | wire c_sign; 77 | 78 | 79 | assign a_in = a[30:0]; 80 | assign b_in = b[30:0]; 81 | assign c_out = c[30:0]; 82 | assign a_sign = a[31]; 83 | assign b_sign = b[31]; 84 | assign c_sign = c[31]; 85 | 86 | 87 | initial begin 88 | // Initialize Inputs 89 | a[30:0] = 0; 90 | a[31] = 0; 91 | b[31] = 1; 92 | b[30:0] = 0; 93 | 94 | // Wait 100 ns for global reset to finish 95 | #100; 96 | 97 | // Add stimulus here 98 | forever begin 99 | #1 a = a+5179347; 100 | a[31] = 0; // a is negative... 101 | b[31] = 1; 102 | 103 | 104 | if (a[30:0] > 2.1E9) // input will always be "positive" 105 | begin 106 | a = 0; 107 | b[31] = 1; // b is negative... 108 | b[30:0] = b[30:0] + 3779351; 109 | end 110 | end 111 | 112 | end 113 | 114 | endmodule 115 | -------------------------------------------------------------------------------- /Fixed Point Adder and Subtractor/fixed_point_subtractor1.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Test134n/32-Verilog-Mini-Projects/f6458719db15c2b348ec63d70c5ab7572b771341/Fixed Point Adder and Subtractor/fixed_point_subtractor1.jpg -------------------------------------------------------------------------------- /Fixed Point Adder and Subtractor/fixed_point_subtractor2.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Test134n/32-Verilog-Mini-Projects/f6458719db15c2b348ec63d70c5ab7572b771341/Fixed Point Adder and Subtractor/fixed_point_subtractor2.jpg -------------------------------------------------------------------------------- /Fixed Point Multiplier and Divider/fixed_point_divider.v: -------------------------------------------------------------------------------- 1 | module qdiv #( 2 | //Parameterized values 3 | parameter Q = 15, 4 | parameter N = 32 5 | ) 6 | ( 7 | input [N-1:0] i_dividend, 8 | input [N-1:0] i_divisor, 9 | input i_start, 10 | input i_clk, 11 | output [N-1:0] o_quotient_out, 12 | output o_complete, 13 | output o_overflow 14 | ); 15 | 16 | reg [2*N+Q-3:0] reg_working_quotient; 17 | reg [N-1:0] reg_quotient; 18 | reg [N-2+Q:0] reg_working_dividend; 19 | reg [2*N+Q-3:0] reg_working_divisor; 20 | 21 | reg [N-1:0] reg_count; 22 | 23 | 24 | reg reg_done; 25 | reg reg_sign; 26 | reg reg_overflow; 27 | 28 | initial reg_done = 1'b1; 29 | initial reg_overflow = 1'b0; 30 | initial reg_sign = 1'b0; 31 | 32 | initial reg_working_quotient = 0; 33 | initial reg_quotient = 0; 34 | initial reg_working_dividend = 0; 35 | initial reg_working_divisor = 0; 36 | initial reg_count = 0; 37 | 38 | 39 | assign o_quotient_out[N-2:0] = reg_quotient[N-2:0]; 40 | assign o_quotient_out[N-1] = reg_sign; 41 | assign o_complete = reg_done; 42 | assign o_overflow = reg_overflow; 43 | 44 | always @( posedge i_clk ) begin 45 | if( reg_done && i_start ) begin 46 | 47 | reg_done <= 1'b0; 48 | reg_count <= N+Q-1; 49 | reg_working_quotient <= 0; 50 | reg_working_dividend <= 0; 51 | reg_working_divisor <= 0; 52 | reg_overflow <= 1'b0; 53 | 54 | reg_working_dividend[N+Q-2:Q] <= i_dividend[N-2:0]; 55 | reg_working_divisor[2*N+Q-3:N+Q-1] <= i_divisor[N-2:0]; 56 | 57 | reg_sign <= i_dividend[N-1] ^ i_divisor[N-1]; 58 | end 59 | else if(!reg_done) begin 60 | reg_working_divisor <= reg_working_divisor >> 1; 61 | reg_count <= reg_count - 1; 62 | 63 | // If the dividend is greater than the divisor 64 | if(reg_working_dividend >= reg_working_divisor) begin 65 | reg_working_quotient[reg_count] <= 1'b1; 66 | reg_working_dividend <= reg_working_dividend - reg_working_divisor; 67 | end 68 | 69 | //stop condition 70 | if(reg_count == 0) begin 71 | reg_done <= 1'b1; 72 | reg_quotient <= reg_working_quotient; 73 | if (reg_working_quotient[2*N+Q-3:N]>0) 74 | reg_overflow <= 1'b1; 75 | end 76 | else 77 | reg_count <= reg_count - 1; 78 | end 79 | end 80 | endmodule 81 | 82 | module Test_Div; 83 | 84 | // Inputs 85 | reg [31:0] i_dividend; 86 | reg [31:0] i_divisor; 87 | reg i_start; 88 | reg i_clk; 89 | 90 | // Outputs 91 | wire [31:0] o_quotient_out; 92 | wire o_complete; 93 | wire o_overflow; 94 | 95 | // Instantiate the Unit Under Test (UUT) 96 | qdiv uut ( 97 | .i_dividend(i_dividend), 98 | .i_divisor(i_divisor), 99 | .i_start(i_start), 100 | .i_clk(i_clk), 101 | .o_quotient_out(o_quotient_out), 102 | .o_complete(o_complete), 103 | .o_overflow(o_overflow) 104 | ); 105 | 106 | reg [10:0] count; 107 | 108 | initial begin 109 | // Initialize Inputs 110 | i_dividend = 1; 111 | i_divisor = 1; 112 | i_start = 0; 113 | i_clk = 0; 114 | 115 | count <= 0; 116 | 117 | // Wait 100 ns for global reset to finish 118 | #100; 119 | 120 | // Add stimulus here 121 | forever #2 i_clk = ~i_clk; 122 | end 123 | 124 | always @(posedge i_clk) begin 125 | if (count == 47) begin 126 | count <= 0; 127 | i_start <= 1'b1; 128 | end 129 | else begin 130 | count <= count + 1; 131 | i_start <= 1'b0; 132 | end 133 | end 134 | 135 | always @(count) begin 136 | if (count == 47) begin 137 | if ( i_divisor > 32'h1FFFFFFF ) begin 138 | i_divisor <= 1; 139 | i_dividend = (i_dividend << 1) + 3; 140 | end 141 | else 142 | i_divisor = (i_divisor << 1) + 1; 143 | end 144 | end 145 | 146 | always @(posedge o_complete) 147 | $display ("%b,%b,%b, %b", i_dividend, i_divisor, o_quotient_out, o_overflow); 148 | 149 | endmodule 150 | -------------------------------------------------------------------------------- /Fixed Point Multiplier and Divider/fixed_point_divider1.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Test134n/32-Verilog-Mini-Projects/f6458719db15c2b348ec63d70c5ab7572b771341/Fixed Point Multiplier and Divider/fixed_point_divider1.jpg -------------------------------------------------------------------------------- /Fixed Point Multiplier and Divider/fixed_point_divider2.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Test134n/32-Verilog-Mini-Projects/f6458719db15c2b348ec63d70c5ab7572b771341/Fixed Point Multiplier and Divider/fixed_point_divider2.jpg -------------------------------------------------------------------------------- /Fixed Point Multiplier and Divider/fixed_point_multiplier.v: -------------------------------------------------------------------------------- 1 | module qmult #( 2 | //Parameterized values 3 | parameter Q = 15, 4 | parameter N = 32 5 | ) 6 | ( 7 | input [N-1:0] i_multiplicand, 8 | input [N-1:0] i_multiplier, 9 | output [N-1:0] o_result, 10 | output reg ovr 11 | ); 12 | 13 | 14 | 15 | reg [2*N-1:0] r_result; 16 | 17 | reg [N-1:0] r_RetVal; 18 | 19 | 20 | assign o_result = r_RetVal; 21 | 22 | always @(i_multiplicand, i_multiplier) begin 23 | r_result <= i_multiplicand[N-2:0] * i_multiplier[N-2:0]; 24 | 25 | ovr <= 1'b0; 26 | end 27 | 28 | 29 | always @(r_result) begin 30 | r_RetVal[N-1] <= i_multiplicand[N-1] ^ i_multiplier[N-1]; 31 | r_RetVal[N-2:0] <= r_result[N-2+Q:Q]; 32 | 33 | if (r_result[2*N-2:N-1+Q] > 0) 34 | ovr <= 1'b1; 35 | end 36 | 37 | endmodule 38 | module Test_mult; 39 | 40 | // Inputs 41 | reg [31:0] i_multiplicand; 42 | reg [31:0] i_multiplier; 43 | 44 | // Outputs 45 | wire [31:0] o_result; 46 | wire ovr; 47 | 48 | // Instantiate the Unit Under Test (UUT) 49 | qmult #(19,32) uut ( 50 | .i_multiplicand(i_multiplicand), 51 | .i_multiplier(i_multiplier), 52 | .o_result(o_result), 53 | .ovr(ovr) 54 | ); 55 | 56 | initial begin 57 | $monitor ("%b,%b,%b,%b", i_multiplicand, i_multiplier, o_result, ovr); 58 | 59 | // Initialize Inputs 60 | i_multiplicand = 32'b00000000000110010010000111111011; //pi = 3.141592 61 | i_multiplicand[31] = 0; 62 | i_multiplier[31] = 0; 63 | i_multiplier[30:0] = 0; 64 | 65 | // Wait 100 ns for global reset to finish 66 | #100; 67 | #100 i_multiplier[0] = 1; // 1.91E-6 68 | end 69 | 70 | // Add stimulus here 71 | always begin 72 | #10 i_multiplier[30:0] = (i_multiplier[30:0] << 1) + 1; 73 | end 74 | 75 | endmodule 76 | -------------------------------------------------------------------------------- /Fixed Point Multiplier and Divider/fixed_point_multiplier1.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Test134n/32-Verilog-Mini-Projects/f6458719db15c2b348ec63d70c5ab7572b771341/Fixed Point Multiplier and Divider/fixed_point_multiplier1.jpg -------------------------------------------------------------------------------- /Fixed Point Multiplier and Divider/fixed_point_multiplier2.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Test134n/32-Verilog-Mini-Projects/f6458719db15c2b348ec63d70c5ab7572b771341/Fixed Point Multiplier and Divider/fixed_point_multiplier2.jpg -------------------------------------------------------------------------------- /Floating Point IEEE 754 Addition Subtraction/Addition_Subtraction.v: -------------------------------------------------------------------------------- 1 | module priority_encoder( 2 | input [24:0] significand, 3 | input [7:0] exp_a, 4 | output reg [24:0] Significand, 5 | output [7:0] exp_sub 6 | ); 7 | 8 | reg [4:0] shift; 9 | 10 | always @(significand) 11 | begin 12 | casex (significand) 13 | 25'b1_1xxx_xxxx_xxxx_xxxx_xxxx_xxxx : begin 14 | Significand = significand; 15 | shift = 5'd0; 16 | end 17 | 25'b1_01xx_xxxx_xxxx_xxxx_xxxx_xxxx : begin 18 | Significand = significand << 1; 19 | shift = 5'd1; 20 | end 21 | 22 | 25'b1_001x_xxxx_xxxx_xxxx_xxxx_xxxx : begin 23 | Significand = significand << 2; 24 | shift = 5'd2; 25 | end 26 | 27 | 25'b1_0001_xxxx_xxxx_xxxx_xxxx_xxxx : begin 28 | Significand = significand << 3; 29 | shift = 5'd3; 30 | end 31 | 32 | 25'b1_0000_1xxx_xxxx_xxxx_xxxx_xxxx : begin 33 | Significand = significand << 4; 34 | shift = 5'd4; 35 | end 36 | 37 | 25'b1_0000_01xx_xxxx_xxxx_xxxx_xxxx : begin 38 | Significand = significand << 5; 39 | shift = 5'd5; 40 | end 41 | 42 | 25'b1_0000_001x_xxxx_xxxx_xxxx_xxxx : begin // 24'h020000 43 | Significand = significand << 6; 44 | shift = 5'd6; 45 | end 46 | 47 | 25'b1_0000_0001_xxxx_xxxx_xxxx_xxxx : begin // 24'h010000 48 | Significand = significand << 7; 49 | shift = 5'd7; 50 | end 51 | 52 | 25'b1_0000_0000_1xxx_xxxx_xxxx_xxxx : begin // 24'h008000 53 | Significand = significand << 8; 54 | shift = 5'd8; 55 | end 56 | 57 | 25'b1_0000_0000_01xx_xxxx_xxxx_xxxx : begin // 24'h004000 58 | Significand = significand << 9; 59 | shift = 5'd9; 60 | end 61 | 62 | 25'b1_0000_0000_001x_xxxx_xxxx_xxxx : begin // 24'h002000 63 | Significand = significand << 10; 64 | shift = 5'd10; 65 | end 66 | 67 | 25'b1_0000_0000_0001_xxxx_xxxx_xxxx : begin // 24'h001000 68 | Significand = significand << 11; 69 | shift = 5'd11; 70 | end 71 | 72 | 25'b1_0000_0000_0000_1xxx_xxxx_xxxx : begin // 24'h000800 73 | Significand = significand << 12; 74 | shift = 5'd12; 75 | end 76 | 77 | 25'b1_0000_0000_0000_01xx_xxxx_xxxx : begin // 24'h000400 78 | Significand = significand << 13; 79 | shift = 5'd13; 80 | end 81 | 82 | 25'b1_0000_0000_0000_001x_xxxx_xxxx : begin // 24'h000200 83 | Significand = significand << 14; 84 | shift = 5'd14; 85 | end 86 | 87 | 25'b1_0000_0000_0000_0001_xxxx_xxxx : begin // 24'h000100 88 | Significand = significand << 15; 89 | shift = 5'd15; 90 | end 91 | 92 | 25'b1_0000_0000_0000_0000_1xxx_xxxx : begin // 24'h000080 93 | Significand = significand << 16; 94 | shift = 5'd16; 95 | end 96 | 97 | 25'b1_0000_0000_0000_0000_01xx_xxxx : begin // 24'h000040 98 | Significand = significand << 17; 99 | shift = 5'd17; 100 | end 101 | 102 | 25'b1_0000_0000_0000_0000_001x_xxxx : begin // 24'h000020 103 | Significand = significand << 18; 104 | shift = 5'd18; 105 | end 106 | 107 | 25'b1_0000_0000_0000_0000_0001_xxxx : begin // 24'h000010 108 | Significand = significand << 19; 109 | shift = 5'd19; 110 | end 111 | 112 | 25'b1_0000_0000_0000_0000_0000_1xxx : begin // 24'h000008 113 | Significand = significand << 20; 114 | shift = 5'd20; 115 | end 116 | 117 | 25'b1_0000_0000_0000_0000_0000_01xx : begin // 24'h000004 118 | Significand = significand << 21; 119 | shift = 5'd21; 120 | end 121 | 122 | 25'b1_0000_0000_0000_0000_0000_001x : begin // 24'h000002 123 | Significand = significand << 22; 124 | shift = 5'd22; 125 | end 126 | 127 | 25'b1_0000_0000_0000_0000_0000_0001 : begin // 24'h000001 128 | Significand = significand << 23; 129 | shift = 5'd23; 130 | end 131 | 132 | 25'b1_0000_0000_0000_0000_0000_0000 : begin // 24'h000000 133 | Significand = significand << 24; 134 | shift = 5'd24; 135 | end 136 | default : begin 137 | Significand = (~significand) + 1'b1; 138 | shift = 8'd0; 139 | end 140 | 141 | endcase 142 | end 143 | assign exp_sub = exp_a - shift; 144 | 145 | endmodule 146 | 147 | module Addition_Subtraction(input [31:0] a,b, 148 | input add_sub_signal, // If 1 then addition otherwise subtraction 149 | output exception, 150 | output [31:0] res ); 151 | 152 | wire operation_add_sub_signal; 153 | wire enable; 154 | wire output_sign; 155 | 156 | wire [31:0] op_a,op_b; 157 | wire [23:0] significand_a,significand_b; 158 | wire [7:0] exp_diff; 159 | 160 | 161 | wire [23:0] significand_b_add_sub; 162 | wire [7:0] exp_b_add_sub; 163 | 164 | wire [24:0] significand_add; 165 | wire [30:0] add_sum; 166 | 167 | wire [23:0] significand_sub_complement; 168 | wire [24:0] significand_sub; 169 | wire [30:0] sub_diff; 170 | wire [24:0] subtraction_diff; 171 | wire [7:0] exp_sub; 172 | 173 | assign {enable,op_a,op_b} = (a[30:0] < b[30:0]) ? {1'b1,b,a} : {1'b0,a,b}; // For operations always op_a must not be less than b 174 | 175 | assign exp_a = op_a[30:23]; 176 | assign exp_b = op_b[30:23]; 177 | 178 | assign exception = (&op_a[30:23]) | (&op_b[30:23]) | (add_sub_signal ? ((|(op_a[30:0] ^ op_b[30:0])) || ~(op_a[31] ^ op_b[31])) : |(op_a ^ op_b)); // Exception flag sets 1 if either one of the exponent is 255. 179 | 180 | assign output_sign = add_sub_signal ? enable ? !op_a[31] : op_a[31] : op_a[31] ; 181 | 182 | assign operation_add_sub_signal = add_sub_signal ? op_a[31] ^ op_b[31] : ~(op_a[31] ^ op_b[31]); 183 | // Assign significand values according to Hidden Bit. 184 | assign significand_a = (|op_a[30:23]) ? {1'b1,op_a[22:0]} : {1'b0,op_a[22:0]}; // If exponent is zero,hidden bit = 0,else 1 185 | assign significand_b = (|op_b[30:23]) ? {1'b1,op_b[22:0]} : {1'b0,op_b[22:0]}; 186 | 187 | assign exp_diff = op_a[30:23] - op_b[30:23]; // Exponent difference calculation 188 | assign significand_b_add_sub = significand_b >> exp_diff; 189 | assign exp_b_add_sub = op_b[30:23] + exp_diff; 190 | 191 | assign perform = (op_a[30:23] == exp_b_add_sub); // Checking if exponents are same 192 | 193 | 194 | // Add Block // 195 | assign significand_add = (perform & operation_add_sub_signal) ? (significand_a + significand_b_add_sub) : 25'd0; 196 | 197 | assign add_sum[22:0] = significand_add[24] ? significand_add[23:1] : significand_add[22:0]; // res will be most 23 bits if carry generated, else least 22 bits. 198 | 199 | assign add_sum[30:23] = significand_add[24] ? (1'b1 + op_a[30:23]) : op_a[30:23]; // If carry generates in sum value then exponent is added with 1 else feed as it is. 200 | 201 | // Sub Block // 202 | assign significand_sub_complement = (perform & !operation_add_sub_signal) ? ~(significand_b_add_sub) + 24'd1 : 24'd0 ; 203 | 204 | assign significand_sub = perform ? (significand_a + significand_sub_complement) : 25'd0; 205 | 206 | priority_encoder pe(significand_sub,op_a[30:23],subtraction_diff,exp_sub); 207 | 208 | assign sub_diff[30:23] = exp_sub; 209 | 210 | assign sub_diff[22:0] = subtraction_diff[22:0]; 211 | 212 | // Output // 213 | assign res = exception ? 32'b0 : ((!operation_add_sub_signal) ? {output_sign,sub_diff} : {output_sign,add_sum}); 214 | 215 | endmodule 216 | 217 | 218 | module Addition_Subtraction_tb; 219 | 220 | reg [31:0] a,b; 221 | reg clk=1'b0, 222 | reset =1'b1; 223 | reg add_sub_signal; 224 | 225 | wire [31:0] res; 226 | wire exception; 227 | 228 | Addition_Subtraction dut(a,b,add_sub_signal,exception,res); 229 | 230 | always #5 clk = ~clk; 231 | 232 | initial 233 | begin 234 | 235 | add_sub_signal = 1'b0; 236 | 237 | iteration (32'h4201_51EC,32'h4242_147B,32'h42A1_B333,`__LINE__); //32.33 + 48.52 = 80.85 238 | 239 | iteration (32'h4068_51EC,32'h4090_A3D7,32'h4102_6666,`__LINE__); //3.63 + 4.52 = 8.15. 240 | 241 | iteration (32'h4195_0A3D,32'h419B_47AE,32'h4218_28F6,`__LINE__); //18.63 + 19.41 = 38.04. 242 | 243 | iteration (32'h4217_999A,32'h3F8C_CCCD,32'h421C_0000,`__LINE__); //37.9 + 1.1 = 39. 244 | 245 | iteration (32'h4383_C7AE,32'h4164_F5C3,32'h438A_EF5C,`__LINE__); //263.56 + 14.31 = 277.87 246 | 247 | iteration (32'h4542_77D7,32'h453B_8FD7,32'h45BF_03D7,`__LINE__); //3111.49 + 3000.99 = 6112.48 248 | 249 | iteration (32'h3F3A_E148,32'h3EB33333,32'h3F8A_3D71,`__LINE__); //0.73 + 0.35 = 1.08. 250 | 251 | iteration (32'h3F7D_70A4,32'h3F7D_70A4,32'h3FFD_70A4,`__LINE__); //0.99 + 0.99 = 1.98 252 | 253 | iteration (32'h3F40_0000,32'h3E94_7AE1,32'h3F85_1EB8,`__LINE__); //0.75 + 0.29 = 1.04 254 | 255 | iteration (32'h4B7F_FFFF,32'h3F80_0000,32'h4B80_0000,`__LINE__); //16777215 + 1 = 16777216 256 | // Corner Case 257 | 258 | iteration (32'h4B7F_FFFF,32'h4000_0000,32'h4B80_0001,`__LINE__); //16777215 + 2 = 16777217. 259 | // Corner Case 260 | 261 | iteration (32'h4B7F_FFFF,32'h4B7F_FFFF,32'h4BFF_FFFF,`__LINE__); //16777215 + 16777215 = 33554430 262 | // Working 263 | 264 | iteration (32'h4B7F_FFFE,32'h3F80_0000,32'h4B7F_FFFF,`__LINE__); //16777214 + 1 = 16777215 265 | 266 | iteration (32'hBF3A_E148,32'h3EC7_AE14,32'hBEAE_147B,`__LINE__); //-0.73 + 0.39 = -0.34 267 | 268 | iteration (32'hC207_C28F,32'h4243_B852,32'h416F_D70A,`__LINE__); //-33.94 + 48.93 = 14.99 269 | 270 | iteration (32'hBDB2_2D0E,32'h4305_970A,32'h4305_80C5,`__LINE__); //-0.087 + 133.59 = 133.503 271 | 272 | iteration (32'h4E6B_79A3,32'hCCEB_79A3,32'h4E4E_0A6F,`__LINE__); //987654321 - 123456789 = 864197532 273 | 274 | iteration (32'h4B80_0000,32'hCB80_0000,32'h0000_0000,`__LINE__); //16777216 - 16777216 = 0 275 | 276 | iteration (32'h4B7F_FFFF,32'hCB7F_FFFF,32'h0000_0000,`__LINE__); //16777215 - 16777215 = 0 277 | 278 | // Subtraction // 279 | 280 | add_sub_signal = 1'b1; 281 | 282 | iteration (32'h40A00000,32'h40C00000,32'hBF800000,`__LINE__); //5 - 6 = -1 283 | 284 | iteration (32'h40C00000,32'h40A00000,32'h3F800000,`__LINE__); //6 - 5 = 1 285 | 286 | iteration (32'hC0C00000,32'hC0A00000,32'hBF800000,`__LINE__); //-6 - (-5) = -1 287 | 288 | iteration (32'hC0A00000,32'hC0C00000,32'h3F800000,`__LINE__); // -5 - (-6) = 1 289 | 290 | iteration (32'h40C00000,32'hC0A00000,32'h41300000,`__LINE__); // 6 - (-5) = 11 291 | 292 | iteration (32'h40A00000,32'hC0C00000,32'h41300000,`__LINE__); // 5 - (-6) = 11 293 | 294 | iteration (32'hC0A00000,32'h40C00000,32'hC1300000,`__LINE__); // -5 - (6) = -11 295 | 296 | iteration (32'hC0C00000,32'h40A00000,32'hC1300000,`__LINE__); // -6 - (+5) = -11 297 | 298 | // Exception Cases // 299 | 300 | iteration (32'h0000_0000,32'h3EC7_AE14,32'h3EC7_AE14,`__LINE__); 301 | 302 | iteration (32'h3EC7_AE14,32'h0000_0000,32'h3EC7_AE14,`__LINE__); 303 | 304 | iteration (32'h0000_0000,32'h0000_0000,32'h0000_0000,`__LINE__); 305 | 306 | iteration (32'h7F80_0000,32'h7F90_0100,32'h0000_0000,`__LINE__); 307 | 308 | iteration (32'h7F80_0000,32'h3EC7_AE14,32'h0000_0000,`__LINE__); 309 | 310 | iteration (32'h3EC7_AE14,32'h7F80_0000,32'h0000_0000,`__LINE__); 311 | 312 | iteration (32'h7F80_0000,32'h0000_0000,32'h0000_0000,`__LINE__); 313 | 314 | iteration (32'h7F90_0100,32'h7F80_0000,32'h0000_0000,`__LINE__); 315 | 316 | @(negedge clk) 317 | $stop; 318 | 319 | end 320 | 321 | task iteration( 322 | input [31:0] op_a,op_b,expected_value, 323 | input integer line_num ); 324 | 325 | begin 326 | @(negedge clk) 327 | begin 328 | a = op_a; 329 | b = op_b; 330 | end 331 | 332 | @(posedge clk) 333 | begin 334 | #1; 335 | if (expected_value == res) 336 | $display ("Success: Line Number -> %d",line_num); 337 | else 338 | $display ("Failed: \t\n A => %h, \t\n B => %h, \t\n Result Obtained => %h, \t\n Expected Value => %h - Line Number",op_a,op_b,res,expected_value,line_num); 339 | end 340 | end 341 | endtask 342 | 343 | endmodule 344 | -------------------------------------------------------------------------------- /Floating Point IEEE 754 Addition Subtraction/IEEE_754_Addition_Substraction.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Test134n/32-Verilog-Mini-Projects/f6458719db15c2b348ec63d70c5ab7572b771341/Floating Point IEEE 754 Addition Subtraction/IEEE_754_Addition_Substraction.jpg -------------------------------------------------------------------------------- /Floating Point IEEE 754 Division/IEEE_754_Division.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Test134n/32-Verilog-Mini-Projects/f6458719db15c2b348ec63d70c5ab7572b771341/Floating Point IEEE 754 Division/IEEE_754_Division.jpg -------------------------------------------------------------------------------- /Floating Point IEEE 754 Division/TestGenerator.py: -------------------------------------------------------------------------------- 1 | import bitstring, random 2 | 3 | span = 10000000 4 | iteration = 100000 5 | 6 | def ieee754(flt): 7 | b = bitstring.BitArray(float=flt, length=32) 8 | return b 9 | 10 | with open("Test.txt", "w") as f: 11 | 12 | for i in range(iteration): 13 | a = ieee754(random.uniform(-span, span)) 14 | b = ieee754(random.uniform(-span, span)) 15 | ab = ieee754(a.float / b.float) 16 | 17 | f.write(a.hex +"_" + b.hex + "_" + ab.hex + "\n") 18 | -------------------------------------------------------------------------------- /Floating Point IEEE 754 Division/division.v: -------------------------------------------------------------------------------- 1 | // Priority Encoder 2 | 3 | module priority_encoder( 4 | input [24:0] significand, 5 | input [7:0] exp_a, 6 | output reg [24:0] Significand, 7 | output [7:0] exp_sub 8 | ); 9 | 10 | reg [4:0] shift; 11 | 12 | always @(significand) 13 | begin 14 | casex (significand) 15 | 25'b1_1xxx_xxxx_xxxx_xxxx_xxxx_xxxx : begin 16 | Significand = significand; 17 | shift = 5'd0; 18 | end 19 | 25'b1_01xx_xxxx_xxxx_xxxx_xxxx_xxxx : begin 20 | Significand = significand << 1; 21 | shift = 5'd1; 22 | end 23 | 24 | 25'b1_001x_xxxx_xxxx_xxxx_xxxx_xxxx : begin 25 | Significand = significand << 2; 26 | shift = 5'd2; 27 | end 28 | 29 | 25'b1_0001_xxxx_xxxx_xxxx_xxxx_xxxx : begin 30 | Significand = significand << 3; 31 | shift = 5'd3; 32 | end 33 | 34 | 25'b1_0000_1xxx_xxxx_xxxx_xxxx_xxxx : begin 35 | Significand = significand << 4; 36 | shift = 5'd4; 37 | end 38 | 39 | 25'b1_0000_01xx_xxxx_xxxx_xxxx_xxxx : begin 40 | Significand = significand << 5; 41 | shift = 5'd5; 42 | end 43 | 44 | 25'b1_0000_001x_xxxx_xxxx_xxxx_xxxx : begin // 24'h020000 45 | Significand = significand << 6; 46 | shift = 5'd6; 47 | end 48 | 49 | 25'b1_0000_0001_xxxx_xxxx_xxxx_xxxx : begin // 24'h010000 50 | Significand = significand << 7; 51 | shift = 5'd7; 52 | end 53 | 54 | 25'b1_0000_0000_1xxx_xxxx_xxxx_xxxx : begin // 24'h008000 55 | Significand = significand << 8; 56 | shift = 5'd8; 57 | end 58 | 59 | 25'b1_0000_0000_01xx_xxxx_xxxx_xxxx : begin // 24'h004000 60 | Significand = significand << 9; 61 | shift = 5'd9; 62 | end 63 | 64 | 25'b1_0000_0000_001x_xxxx_xxxx_xxxx : begin // 24'h002000 65 | Significand = significand << 10; 66 | shift = 5'd10; 67 | end 68 | 69 | 25'b1_0000_0000_0001_xxxx_xxxx_xxxx : begin // 24'h001000 70 | Significand = significand << 11; 71 | shift = 5'd11; 72 | end 73 | 74 | 25'b1_0000_0000_0000_1xxx_xxxx_xxxx : begin // 24'h000800 75 | Significand = significand << 12; 76 | shift = 5'd12; 77 | end 78 | 79 | 25'b1_0000_0000_0000_01xx_xxxx_xxxx : begin // 24'h000400 80 | Significand = significand << 13; 81 | shift = 5'd13; 82 | end 83 | 84 | 25'b1_0000_0000_0000_001x_xxxx_xxxx : begin // 24'h000200 85 | Significand = significand << 14; 86 | shift = 5'd14; 87 | end 88 | 89 | 25'b1_0000_0000_0000_0001_xxxx_xxxx : begin // 24'h000100 90 | Significand = significand << 15; 91 | shift = 5'd15; 92 | end 93 | 94 | 25'b1_0000_0000_0000_0000_1xxx_xxxx : begin // 24'h000080 95 | Significand = significand << 16; 96 | shift = 5'd16; 97 | end 98 | 99 | 25'b1_0000_0000_0000_0000_01xx_xxxx : begin // 24'h000040 100 | Significand = significand << 17; 101 | shift = 5'd17; 102 | end 103 | 104 | 25'b1_0000_0000_0000_0000_001x_xxxx : begin // 24'h000020 105 | Significand = significand << 18; 106 | shift = 5'd18; 107 | end 108 | 109 | 25'b1_0000_0000_0000_0000_0001_xxxx : begin // 24'h000010 110 | Significand = significand << 19; 111 | shift = 5'd19; 112 | end 113 | 114 | 25'b1_0000_0000_0000_0000_0000_1xxx : begin // 24'h000008 115 | Significand = significand << 20; 116 | shift = 5'd20; 117 | end 118 | 119 | 25'b1_0000_0000_0000_0000_0000_01xx : begin // 24'h000004 120 | Significand = significand << 21; 121 | shift = 5'd21; 122 | end 123 | 124 | 25'b1_0000_0000_0000_0000_0000_001x : begin // 24'h000002 125 | Significand = significand << 22; 126 | shift = 5'd22; 127 | end 128 | 129 | 25'b1_0000_0000_0000_0000_0000_0001 : begin // 24'h000001 130 | Significand = significand << 23; 131 | shift = 5'd23; 132 | end 133 | 134 | 25'b1_0000_0000_0000_0000_0000_0000 : begin // 24'h000000 135 | Significand = significand << 24; 136 | shift = 5'd24; 137 | end 138 | default : begin 139 | Significand = (~significand) + 1'b1; 140 | shift = 8'd0; 141 | end 142 | 143 | endcase 144 | end 145 | assign exp_sub = exp_a - shift; 146 | 147 | endmodule 148 | 149 | //Addition and Subtraction 150 | 151 | module Addition_Subtraction( 152 | input [31:0] a,b, 153 | input add_sub_signal, // If 1 then addition otherwise subtraction 154 | output exception, 155 | output [31:0] res 156 | ); 157 | 158 | wire operation_add_sub_signal; 159 | wire enable; 160 | wire output_sign; 161 | 162 | wire [31:0] op_a,op_b; 163 | wire [23:0] significand_a,significand_b; 164 | wire [7:0] exponent_diff; 165 | 166 | 167 | wire [23:0] significand_b_add_sub; 168 | wire [7:0] exp_b_add_sub; 169 | 170 | wire [24:0] significand_add; 171 | wire [30:0] add_sum; 172 | 173 | wire [23:0] significand_sub_complement; 174 | wire [24:0] significand_sub; 175 | wire [30:0] sub_diff; 176 | wire [24:0] subtraction_diff; 177 | wire [7:0] exp_sub; 178 | 179 | assign {enable,op_a,op_b} = (a[30:0] < b[30:0]) ? {1'b1,b,a} : {1'b0,a,b}; // For operations always op_a must not be less than b 180 | 181 | assign exp_a = op_a[30:23]; 182 | assign exp_b = op_b[30:23]; 183 | 184 | assign exception = (&op_a[30:23]) | (&op_b[30:23]); // Exception flag sets 1 if either one of the exponent is 255. 185 | 186 | assign output_sign = add_sub_signal ? enable ? !op_a[31] : op_a[31] : op_a[31] ; 187 | 188 | assign operation_add_sub_signal = add_sub_signal ? op_a[31] ^ op_b[31] : ~(op_a[31] ^ op_b[31]); // Assign significand values according to Hidden Bit. 189 | 190 | assign significand_a = (|op_a[30:23]) ? {1'b1,op_a[22:0]} : {1'b0,op_a[22:0]}; // If exponent is zero,hidden bit = 0,else 1 191 | assign significand_b = (|op_b[30:23]) ? {1'b1,op_b[22:0]} : {1'b0,op_b[22:0]}; 192 | 193 | assign exponent_diff = op_a[30:23] - op_b[30:23]; // Exponent difference calculation 194 | 195 | assign significand_b_add_sub = significand_b >> exponent_diff; 196 | 197 | assign exp_b_add_sub = op_b[30:23] + exponent_diff; 198 | 199 | assign perform = (op_a[30:23] == exp_b_add_sub); // Checking if exponents are same 200 | 201 | // Add Block // 202 | assign significand_add = (perform & operation_add_sub_signal) ? (significand_a + significand_b_add_sub) : 25'd0; 203 | 204 | assign add_sum[22:0] = significand_add[24] ? significand_add[23:1] : significand_add[22:0]; // res will be most 23 bits if carry generated, else least 22 bits. 205 | 206 | assign add_sum[30:23] = significand_add[24] ? (1'b1 + op_a[30:23]) : op_a[30:23]; // If carry generates in sum value then exponent is added with 1 else feed as it is. 207 | 208 | // Sub Block // 209 | assign significand_sub_complement = (perform & !operation_add_sub_signal) ? ~(significand_b_add_sub) + 24'd1 : 24'd0 ; 210 | 211 | assign significand_sub = perform ? (significand_a + significand_sub_complement) : 25'd0; 212 | 213 | priority_encoder pe(significand_sub,op_a[30:23],subtraction_diff,exp_sub); 214 | 215 | assign sub_diff[30:23] = exp_sub; 216 | 217 | assign sub_diff[22:0] = subtraction_diff[22:0]; 218 | 219 | 220 | // Output // 221 | assign res = exception ? 32'b0 : ((!operation_add_sub_signal) ? {output_sign,sub_diff} : {output_sign,add_sum}); 222 | 223 | endmodule 224 | 225 | 226 | // Multiplication 227 | module Multiplication( 228 | input [31:0] a, 229 | input [31:0] b, 230 | output exception,overflow,underflow, 231 | output [31:0] res 232 | ); 233 | 234 | wire sign,product_round,normalised,zero; 235 | wire [8:0] exponent,sum_exponent; 236 | wire [22:0] product_mantissa; 237 | wire [23:0] op_a,op_b; 238 | wire [47:0] product,product_normalised; //48 Bits 239 | 240 | 241 | assign sign = a[31] ^ b[31]; // XOR of 32nd bit 242 | 243 | assign exception = (&a[30:23]) | (&b[30:23]); // Execption sets to 1 when exponent of any a or b is 255 244 | // If exponent is 0, hidden bit is 0 245 | 246 | 247 | 248 | assign op_a = (|a[30:23]) ? {1'b1,a[22:0]} : {1'b0,a[22:0]}; 249 | 250 | assign op_b = (|b[30:23]) ? {1'b1,b[22:0]} : {1'b0,b[22:0]}; 251 | 252 | assign product = op_a * op_b; // Product 253 | 254 | assign product_round = |product_normalised[22:0]; // Last 22 bits are ORed for rounding off purpose 255 | 256 | assign normalised = product[47] ? 1'b1 : 1'b0; 257 | 258 | assign product_normalised = normalised ? product : product << 1; // Normalized value based on 48th bit 259 | 260 | assign product_mantissa = product_normalised[46:24] + {21'b0,(product_normalised[23] & product_round)}; // Mantissa 261 | 262 | assign zero = exception ? 1'b0 : (product_mantissa == 23'd0) ? 1'b1 : 1'b0; 263 | 264 | assign sum_exponent = a[30:23] + b[30:23]; 265 | 266 | assign exponent = sum_exponent - 8'd127 + normalised; 267 | 268 | assign overflow = ((exponent[8] & !exponent[7]) & !zero) ; // Overall exponent is greater than 255 then Overflow 269 | 270 | assign underflow = ((exponent[8] & exponent[7]) & !zero) ? 1'b1 : 1'b0; // Sum of exponents is less than 255 then Underflow 271 | 272 | assign res = exception ? 32'd0 : zero ? {sign,31'd0} : overflow ? {sign,8'hFF,23'd0} : underflow ? {sign,31'd0} : {sign,exponent[7:0],product_mantissa}; 273 | 274 | 275 | endmodule 276 | 277 | 278 | // Iteration 279 | module Iteration( 280 | input [31:0] operand_1, 281 | input [31:0] operand_2, 282 | output [31:0] solution 283 | ); 284 | 285 | wire [31:0] Intermediate_Value1,Intermediate_Value2; 286 | 287 | Multiplication M1(operand_1,operand_2,,,,Intermediate_Value1); 288 | 289 | //32'h4000_0000 -> 2. 290 | Addition_Subtraction A1(32'h4000_0000,{1'b1,Intermediate_Value1[30:0]},1'b0,,Intermediate_Value2); 291 | 292 | Multiplication M2(operand_1,Intermediate_Value2,,,,solution); 293 | 294 | endmodule 295 | 296 | // Division 297 | module division( 298 | input [31:0] a, 299 | input [31:0] b, 300 | output exception, 301 | output [31:0] res 302 | ); 303 | 304 | wire sign; 305 | wire [7:0] shift; 306 | wire [7:0] exp_a; 307 | wire [31:0] divisor; 308 | wire [31:0] op_a; 309 | wire [31:0] Intermediate_X0; 310 | wire [31:0] Iteration_X0; 311 | wire [31:0] Iteration_X1; 312 | wire [31:0] Iteration_X2; 313 | wire [31:0] Iteration_X3; 314 | wire [31:0] solution; 315 | 316 | wire [31:0] denominator; 317 | wire [31:0] op_a_change; 318 | 319 | assign exception = (&a[30:23]) | (&b[30:23]); 320 | 321 | assign sign = a[31] ^ b[31]; 322 | 323 | assign shift = 8'd126 - b[30:23]; 324 | 325 | assign divisor = {1'b0,8'd126,b[22:0]}; 326 | 327 | assign denominator = divisor; 328 | 329 | assign exp_a = a[30:23] + shift; 330 | 331 | assign op_a = {a[31],exp_a,a[22:0]}; 332 | 333 | assign op_a_change = op_a; 334 | 335 | //32'hC00B_4B4B = (-37)/17 336 | Multiplication x0(32'hC00B_4B4B,divisor,,,,Intermediate_X0); 337 | 338 | //32'h4034_B4B5 = 48/17 339 | Addition_Subtraction X0(Intermediate_X0,32'h4034_B4B5,1'b0,,Iteration_X0); 340 | 341 | Iteration X1(Iteration_X0,divisor,Iteration_X1); 342 | 343 | Iteration X2(Iteration_X1,divisor,Iteration_X2); 344 | 345 | Iteration X3(Iteration_X2,divisor,Iteration_X3); 346 | 347 | Multiplication END(Iteration_X3,op_a,,,,solution); 348 | 349 | assign res = {sign,solution[30:0]}; 350 | endmodule 351 | 352 | `define N_TESTS 100000 353 | 354 | module division_tb; 355 | 356 | reg clk = 0; 357 | reg [31:0] a; 358 | reg [31:0] b; 359 | 360 | wire [31:0] res; 361 | wire exception; 362 | 363 | reg [31:0] expected_res; 364 | 365 | reg [95:0] testVector [`N_TESTS-1:0]; 366 | 367 | reg test_stop_enable; 368 | 369 | integer mcd; 370 | integer test_n = 0; 371 | integer pass = 0; 372 | integer error = 0; 373 | 374 | division DUT(a,b,exception,res); 375 | 376 | always #5 clk = ~clk; 377 | 378 | initial 379 | begin 380 | $readmemh("Test.txt", testVector); 381 | mcd = $fopen("Error_Results.txt"); 382 | end 383 | 384 | always @(posedge clk) 385 | begin 386 | {a,b,expected_res} = testVector[test_n]; 387 | test_n = test_n + 1'b1; 388 | 389 | #2; 390 | if (res[31:12] == expected_res[31:12]) 391 | begin 392 | //$fdisplay (mcd,"TestPassed Test Number -> %d",test_n); 393 | pass = pass + 1'b1; 394 | end 395 | 396 | if (res[31:12] != expected_res[31:12]) 397 | begin 398 | $fdisplay (mcd,"Test Failed Expected res = %h,Obtained res = %h,Test Number-> %d",expected_res,res,test_n); 399 | $display ("Zero Division Error or some other error",mcd,"Test Failed Expected res = %h,Obtained res = %h,Test Number-> %d",expected_res,res,test_n); 400 | error = error + 1'b1; 401 | end 402 | 403 | if (test_n >= `N_TESTS) 404 | begin 405 | $fdisplay(mcd,"Completed %d tests, %d passes and %d fails.", test_n, pass, error); 406 | test_stop_enable = 1'b1; 407 | end 408 | end 409 | 410 | always @(posedge test_stop_enable) 411 | begin 412 | $fclose(mcd); 413 | $finish; 414 | end 415 | 416 | endmodule 417 | 418 | -------------------------------------------------------------------------------- /Floating Point IEEE 754 Multiplication/IEEE_754_Multiplication.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Test134n/32-Verilog-Mini-Projects/f6458719db15c2b348ec63d70c5ab7572b771341/Floating Point IEEE 754 Multiplication/IEEE_754_Multiplication.jpg -------------------------------------------------------------------------------- /Floating Point IEEE 754 Multiplication/Multiplication.v: -------------------------------------------------------------------------------- 1 | module Multiplication(input [31:0] a,input [31:0] b,output exception,overflow,underflow,output [31:0] res); 2 | 3 | wire sign,round,normalised,zero; 4 | wire [8:0] exponent,sum_exponent; 5 | wire [22:0] product_mantissa; 6 | wire [23:0] op_a,op_b; 7 | wire [47:0] product,product_normalised; 8 | 9 | 10 | assign sign = a[31] ^ b[31]; // XOR of 32nd bit 11 | assign exception = (&a[30:23]) | (&b[30:23]); // Execption sets to 1 when exponent of any a or b is 255 12 | // If exponent is 0, hidden bit is 0 13 | 14 | assign op_a = (|a[30:23]) ? {1'b1,a[22:0]} : {1'b0,a[22:0]}; 15 | assign op_b = (|b[30:23]) ? {1'b1,b[22:0]} : {1'b0,b[22:0]}; 16 | 17 | assign product = op_a * op_b; // Product 18 | assign round = |product_normalised[22:0]; // Last 22 bits are ORed for rounding off purpose 19 | assign normalised = product[47] ? 1'b1 : 1'b0; 20 | assign product_normalised = normalised ? product : product << 1; // Normalized value based on 48th bit 21 | assign product_mantissa = product_normalised[46:24] + (product_normalised[23] & round); // Mantissa 22 | assign zero = exception ? 1'b0 : (product_mantissa == 23'd0) ? 1'b1 : 1'b0; 23 | assign sum_exponent = a[30:23] + b[30:23]; 24 | assign exponent = sum_exponent - 8'd127 + normalised; 25 | assign overflow = ((exponent[8] & !exponent[7]) & !zero) ; // Overall exponent is greater than 255 then Overflow 26 | assign underflow = ((exponent[8] & exponent[7]) & !zero) ? 1'b1 : 1'b0; // Sum of exponents is less than 255 then Underflow 27 | assign res = exception ? 32'd0 : zero ? {sign,31'd0} : overflow ? {sign,8'hFF,23'd0} : underflow ? {sign,31'd0} : {sign,exponent[7:0],product_mantissa}; 28 | 29 | endmodule 30 | 31 | 32 | 33 | module multiplication_tb; 34 | 35 | reg [31:0] a,b; 36 | wire exception,overflow,underflow; 37 | wire [31:0] res; 38 | 39 | reg clk = 1'b1; 40 | 41 | Multiplication dut(a,b,exception,overflow,underflow,res); 42 | 43 | always clk = #5 ~clk; 44 | 45 | initial 46 | begin 47 | iteration (32'h0200_0000,32'h0200_0000,1'b0,1'b0,1'b0,32'h0000_0000,`__LINE__); 48 | 49 | iteration (32'h4234_851F,32'h427C_851F,1'b0,1'b0,1'b0,32'h4532_10E9,`__LINE__); // 45.13 * 63.13 = 2849.0569; 50 | 51 | iteration (32'h4049_999A,32'hC166_3D71,1'b0,1'b0,1'b0,32'hC235_5062,`__LINE__); //3.15 * -14.39 = -45.3285 52 | 53 | iteration (32'hC152_6666,32'hC240_A3D7,1'b0,1'b0,1'b0,32'h441E_5375,`__LINE__); //-13.15 * -48.16 = 633.304 54 | 55 | iteration (32'h4580_0000,32'h4580_0000,1'b0,1'b0,1'b0,32'h4B80_0000,`__LINE__); //4096 * 4096 = 16777216 56 | 57 | iteration (32'h3ACA_62C1,32'h3ACA_62C1,1'b0,1'b0,1'b0,32'h361F_FFE7,`__LINE__); //0.00154408081 * 0.00154408081 = 0.00000238418 58 | 59 | iteration (32'h0000_0000,32'h0000_0000,1'b0,1'b0,1'b0,32'h0000_0000,`__LINE__); // 0 * 0 = 0; 60 | 61 | iteration (32'hC152_6666,32'h0000_0000,1'b0,1'b0,1'b0,32'h441E_5375,`__LINE__); //-13.15 * 0 = 0; 62 | 63 | iteration (32'h7F80_0000,32'h7F80_0000,1'b1,1'b1,1'b0,32'h0000_0000,`__LINE__); 64 | 65 | $stop; 66 | 67 | end 68 | 69 | task iteration( 70 | input [31:0] op_a,op_b, 71 | input Expected_Exception,Expected_Overflow,Expected_Underflow, 72 | input [31:0] Expected_result, 73 | input integer linenum 74 | ); 75 | begin 76 | @(negedge clk) 77 | begin 78 | a = op_a; 79 | b = op_b; 80 | end 81 | 82 | @(posedge clk) 83 | begin 84 | if ((Expected_result == res) && (Expected_Exception == exception) && (Expected_Overflow == overflow) && (Expected_Underflow == underflow)) 85 | $display ("Success : %d",linenum); 86 | 87 | else 88 | $display ("Failed : Expected_result = %h, Result = %h, \n Expected_Exception = %d, Exception = %d,\n Expected_Overflow = %d, Overflow = %d, \n Expected_Underflow = %d, Underflow = %d - %d \n ",Expected_result,res,Expected_Exception,exception,Expected_Overflow,overflow,Expected_Underflow,underflow,linenum); 89 | end 90 | end 91 | endtask 92 | endmodule 93 | -------------------------------------------------------------------------------- /Fraction Multiplier/fraction multiplier.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Test134n/32-Verilog-Mini-Projects/f6458719db15c2b348ec63d70c5ab7572b771341/Fraction Multiplier/fraction multiplier.jpg -------------------------------------------------------------------------------- /Fraction Multiplier/fraction_multiplication.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Test134n/32-Verilog-Mini-Projects/f6458719db15c2b348ec63d70c5ab7572b771341/Fraction Multiplier/fraction_multiplication.jpg -------------------------------------------------------------------------------- /Fraction Multiplier/fraction_multiplication.v: -------------------------------------------------------------------------------- 1 | `define M B[0] 2 | module fraction_multiplication (CLK, St, Mplier, Mcand, Product, Done); 3 | input CLK; 4 | input St; 5 | input[3:0] Mplier; 6 | input[3:0] Mcand; 7 | output[6:0] Product; 8 | output Done; 9 | reg[2:0] State; 10 | reg[3:0] A; 11 | reg[3:0] B; 12 | reg[3:0] addout; 13 | initial 14 | begin 15 | State = 0; 16 | end 17 | 18 | always @(posedge CLK) 19 | begin 20 | case (State) 21 | 0 : 22 | begin 23 | if (St == 1'b1) 24 | begin 25 | A <= 4'b0000 ; 26 | B <= Mplier ; 27 | State <= 1 ; 28 | end 29 | else 30 | State <= 0; 31 | end 32 | 1, 2, 3 : 33 | begin 34 | if (`M == 1'b1) 35 | begin 36 | addout = A + Mcand; 37 | A <= {Mcand[3], addout[3:1]} ; 38 | B <= {addout[0], B[3:1]} ; 39 | end 40 | else 41 | begin 42 | A <= {A[3], A[3:1]} ; 43 | B <= {A[0], B[3:1]} ; 44 | end 45 | State <= State + 1 ; 46 | end 47 | 4 : 48 | begin 49 | if (`M == 1'b1) 50 | begin 51 | addout = A + ~Mcand + 1; 52 | A <= {~Mcand[3], addout[3:1]} ; 53 | B <= {addout[0], B[3:1]} ; 54 | end 55 | else 56 | begin 57 | A <= {A[3], A[3:1]} ; 58 | B <= {A[0], B[3:1]} ; 59 | end 60 | State <= 5 ; 61 | end 62 | 5 : 63 | begin 64 | State <= 0 ; 65 | end 66 | 67 | default : 68 | begin 69 | State <= 0 ; 70 | end 71 | endcase 72 | end 73 | assign Done = (State == 5) ? 1'b1 : 1'b0 ; 74 | assign Product = {A[2:0], B} ; 75 | endmodule 76 | -------------------------------------------------------------------------------- /Fraction Multiplier/fraction_multiplication_tb.v: -------------------------------------------------------------------------------- 1 | module fraction_multiplication_tb; 2 | 3 | reg [3:0] Mplier,Mcand; 4 | wire [6:0] Product; 5 | reg CLK,St; 6 | wire Done; 7 | fraction_multiplication x1 (CLK, St, Mplier, Mcand, Product, Done); 8 | 9 | initial 10 | begin 11 | CLK=1; 12 | forever #5 CLK=~CLK; 13 | end 14 | 15 | initial 16 | begin 17 | #20; 18 | 19 | 20 | St=1; 21 | Mplier=255; 22 | Mcand=255; 23 | #10 24 | St=0; 25 | #100 26 | 27 | 28 | #20 29 | 30 | St=1; 31 | Mplier=128; 32 | Mcand=128; 33 | #10 34 | St=0; 35 | #100 36 | 37 | St=1; 38 | Mplier=128; 39 | Mcand=0; 40 | #10 41 | St=0; 42 | #100 43 | 44 | St=1; 45 | Mplier=128; 46 | Mcand=1; 47 | #10 48 | St=0; 49 | #100 50 | 51 | St=1; 52 | Mplier=25; 53 | Mcand=5; 54 | #10 55 | St=0; 56 | #100 57 | 58 | St=1; 59 | Mplier=64; 60 | Mcand=64; 61 | #10 62 | St=0; 63 | #100 64 | 65 | St=1; 66 | Mplier=36; 67 | Mcand=36; 68 | #10 69 | St=0; 70 | #100 71 | 72 | St=1; 73 | Mplier=11; 74 | Mcand=33; 75 | #10 76 | St=0; 77 | #100 78 | 79 | St=1; 80 | Mplier=80; 81 | Mcand=10; 82 | #10 83 | St=0; 84 | #100; 85 | end 86 | endmodule 87 | -------------------------------------------------------------------------------- /High Radix Multiplier/high radix.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Test134n/32-Verilog-Mini-Projects/f6458719db15c2b348ec63d70c5ab7572b771341/High Radix Multiplier/high radix.png -------------------------------------------------------------------------------- /High Radix Multiplier/high_radix_multiplication.v: -------------------------------------------------------------------------------- 1 | 2 | 3 | module multiplier (clk,reset,x,y,out); 4 | input clk,reset; 5 | input [15:0] x,y; 6 | output reg [31:0] out; 7 | 8 | reg [2:0] c=0 ; 9 | 10 | reg [31:0] pp=0; //partial products 11 | reg [31:0] spp=0; //shifted partial products 12 | reg [31:0] prod=0; 13 | reg [15:0] i=0,j=0; 14 | reg flag=0, temp=0 ; 15 | wire [15:0] inv_x ; 16 | //assign x= (~x) +1'b1; 17 | assign inv_x = (~x) +1'b1; 18 | always@(posedge clk) 19 | begin 20 | if(reset) 21 | begin 22 | out=0; 23 | c=0; 24 | pp=0; 25 | flag=0; 26 | spp=0; 27 | i=0; 28 | j=0; 29 | prod=0; 30 | end 31 | else begin 32 | 33 | if(!flag) 34 | c={y[1],y[0],1'b0}; 35 | flag=1; 36 | case(c) 37 | //////////////////////// 38 | 3'b000,3'b111: begin 39 | if(i<8) 40 | begin i=i+1; 41 | c={y[2*i+1],y[2*i],y[2*i-1]}; end 42 | else 43 | c=3'bxxx; 44 | end 45 | //////////////////////////// 46 | 3'b001,3'b010: 47 | begin 48 | if(i<8) 49 | begin 50 | i=i+1; 51 | c={y[2*i+1],y[2*i],y[2*i-1]}; 52 | pp={{16{x[15]}},x}; 53 | if(i==1'b1) 54 | prod=pp; 55 | else 56 | begin 57 | temp=pp[31]; 58 | j=i-1; 59 | j=j<<1; 60 | spp=pp<=14)begin 63 | sda = register2[7]; 64 | register2 = register2<<1; 65 | end 66 | if(rw==0 && i>=23)begin 67 | sda = data_wr_dup[7]; 68 | data_wr_dup = data_wr_dup<<1; 69 | end 70 | i = i + 1; 71 | if(i>32 && rw ==0) 72 | sda= 1; 73 | else if(i>25 && rw==1) 74 | sda = 1; 75 | end 76 | slave slv(data,sda,scl); 77 | endmodule 78 | -------------------------------------------------------------------------------- /I2C and SPI Protocols/I2C/Slave.v: -------------------------------------------------------------------------------- 1 | module slave(out,sda,scl); 2 | input sda; 3 | input scl; 4 | output reg [7:0]out; 5 | integer j = 0; 6 | reg [6:0]temp; 7 | reg [7:0]add; 8 | reg rw; 9 | reg [7:0]register_address; 10 | reg bitin; 11 | reg [7:0]storage[0:38]; 12 | initial 13 | storage[37]=16; 14 | parameter address = 7'b1101001; 15 | always @(posedge scl)begin 16 | //if({sda,scl}==2'b01)begin 17 | bitin = sda; 18 | if(j<8) 19 | temp = {temp,bitin}; 20 | if(j==8) 21 | if(bitin==0) 22 | rw = 0; 23 | else 24 | rw = 1; 25 | j = j +1 ; 26 | if(temp==address && (j>15 && j<24) && rw==1)begin 27 | add = {add,bitin}; 28 | end 29 | if(temp==address && rw == 0 && j>15 && j!=24 && j<33)begin 30 | add = {add,bitin}; 31 | end 32 | else if(j==24) 33 | register_address = add; 34 | if(j==33 && rw==0) 35 | storage[register_address]=add; 36 | out = storage[add]; 37 | end 38 | endmodule 39 | -------------------------------------------------------------------------------- /I2C and SPI Protocols/I2C/i2c frame.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Test134n/32-Verilog-Mini-Projects/f6458719db15c2b348ec63d70c5ab7572b771341/I2C and SPI Protocols/I2C/i2c frame.png -------------------------------------------------------------------------------- /I2C and SPI Protocols/I2C/tbmast.v: -------------------------------------------------------------------------------- 1 | module tbmast; 2 | 3 | // Inputs 4 | reg [6:0] address; 5 | reg [7:0] register; 6 | reg [7:0] data; 7 | reg [7:0] data_wr; 8 | reg clk; 9 | reg rw; 10 | 11 | // Outputs 12 | wire sda; 13 | wire scl; 14 | 15 | // Instantiate the Unit Under Test (UUT) 16 | master uut ( 17 | .address(address), 18 | .register(register), 19 | .clk(clk), 20 | .rw(rw), 21 | .sda(sda), 22 | .scl(scl), 23 | .data(data), 24 | .data_wr(data_wr) 25 | ); 26 | 27 | initial begin 28 | // Initialize Inputs 29 | address = 105; 30 | register = 7'b0100101; 31 | clk = 0; 32 | rw = 0; 33 | data_wr = 20; 34 | 35 | // Wait 100 ns for global reset to finish 36 | #100; 37 | 38 | // Add stimulus here 39 | 40 | end 41 | always 42 | #1 clk = !clk; 43 | endmodule 44 | -------------------------------------------------------------------------------- /I2C and SPI Protocols/SPI/Loopback.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Test134n/32-Verilog-Mini-Projects/f6458719db15c2b348ec63d70c5ab7572b771341/I2C and SPI Protocols/SPI/Loopback.jpg -------------------------------------------------------------------------------- /I2C and SPI Protocols/SPI/Loopback.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns/1ps 2 | 3 | module SPI_loopback 4 | #( 5 | parameter CLK_FREQUENCE = 50_000_000 , //system clk frequence 6 | SPI_FREQUENCE = 5_000_000 , //spi clk frequence 7 | DATA_WIDTH = 8 , //serial word length 8 | CPOL = 0 , //SPI mode selection (mode 0 default) 9 | CPHA = 0 //CPOL = clock polarity, CPHA = clock phase 10 | ) 11 | ( 12 | input clk , 13 | input rst_n , 14 | input [DATA_WIDTH-1:0] data_m_in , 15 | input [DATA_WIDTH-1:0] data_s_in , 16 | input start_m , 17 | output finish_m , 18 | output [DATA_WIDTH-1:0] data_m_out , 19 | output [DATA_WIDTH-1:0] data_s_out , 20 | output data_valid_s 21 | ); 22 | 23 | wire miso ; 24 | wire mosi ; 25 | wire cs_n ; 26 | wire sclk ; 27 | 28 | spi_master 29 | #( 30 | .CLK_FREQUENCE (CLK_FREQUENCE ), 31 | .SPI_FREQUENCE (SPI_FREQUENCE ), 32 | .DATA_WIDTH (DATA_WIDTH ), 33 | .CPOL (CPOL ), 34 | .CPHA (CPHA ) 35 | ) 36 | u_spi_master( 37 | .clk (clk ), 38 | .rst_n (rst_n ), 39 | .data_in (data_m_in ), 40 | .start (start_m ), 41 | .miso (miso ), 42 | .sclk (sclk ), 43 | .cs_n (cs_n ), 44 | .mosi (mosi ), 45 | .finish (finish_m ), 46 | .data_out (data_m_out ) 47 | ); 48 | 49 | SPI_Slave 50 | #( 51 | .CLK_FREQUENCE (CLK_FREQUENCE ), 52 | .SPI_FREQUENCE (SPI_FREQUENCE ), 53 | .DATA_WIDTH (DATA_WIDTH ), 54 | .CPOL (CPOL ), 55 | .CPHA (CPHA ) 56 | ) 57 | u_SPI_Slave( 58 | .clk (clk ), 59 | .rst_n (rst_n ), 60 | .data_in (data_s_in ), 61 | .sclk (sclk ), 62 | .cs_n (cs_n ), 63 | .mosi (mosi ), 64 | .miso (miso ), 65 | .data_valid (data_valid_s ), 66 | .data_out (data_s_out ) 67 | ); 68 | 69 | endmodule 70 | -------------------------------------------------------------------------------- /I2C and SPI Protocols/SPI/Loopback_tb.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns/1ps 2 | 3 | module SPI_loopback_tb(); 4 | 5 | parameter CLK_FREQUENCE = 50_000_000 , 6 | SPI_FREQUENCE = 5_000_000 , 7 | DATA_WIDTH = 8 , 8 | CPOL = 0 , 9 | CPHA = 0 ; 10 | 11 | reg clk ; 12 | reg rst_n ; 13 | reg [DATA_WIDTH-1:0] data_m_in ; 14 | reg [DATA_WIDTH-1:0] data_s_in ; 15 | reg start_m ; 16 | wire finish_m ; 17 | wire [DATA_WIDTH-1:0] data_m_out ; 18 | wire [DATA_WIDTH-1:0] data_s_out ; 19 | wire data_valid_s; 20 | //the clk generation 21 | initial begin 22 | clk = 1; 23 | forever #10 clk = ~clk; 24 | end 25 | //the rst_n generation 26 | initial begin 27 | rst_n = 1'b0; 28 | #22 rst_n = 1'b1; 29 | end 30 | //the main block 31 | initial fork 32 | data_m_in_generate; 33 | data_s_in_generate; 34 | start_change; 35 | join 36 | //to generate data_m_in 37 | task data_m_in_generate; 38 | begin 39 | data_m_in = 'd0; 40 | @(posedge rst_n) 41 | data_m_in <= 8'b10100101; 42 | @(posedge finish_m) 43 | data_m_in <= 8'b10011010; 44 | end 45 | endtask 46 | //to generate data_s_in 47 | task data_s_in_generate; 48 | begin 49 | data_s_in = 'd0; 50 | @(posedge rst_n) 51 | data_s_in <= $random; 52 | @(posedge finish_m) 53 | data_s_in <= $random; 54 | @(negedge data_valid_s) 55 | ; 56 | @(negedge data_valid_s) 57 | #20 $finish; 58 | end 59 | endtask 60 | //to generate the start signal 61 | task start_change; 62 | begin 63 | start_m = 1'b0; 64 | @(posedge rst_n) 65 | #20 start_m <= 1'b1; 66 | #20 start_m = 1'b0; 67 | @(negedge finish_m) 68 | #20 start_m = 1'b1; 69 | #20 start_m = 1'b0; 70 | end 71 | endtask 72 | //to generate uart_frame_tx_tb.vcd 73 | initial begin 74 | $dumpfile("SPI_loopback_tb.vcd"); 75 | $dumpvars(); 76 | end 77 | //Debug information 78 | reg data_valid_1; 79 | reg data_valid_2; 80 | always @(posedge clk or negedge rst_n) begin 81 | data_valid_1 <= data_valid_s; 82 | data_valid_2 <= data_valid_1; 83 | end 84 | 85 | assign data_valid_pos = ~data_valid_2 & data_valid_1; 86 | 87 | always @(posedge clk) begin 88 | if (data_valid_pos) 89 | if (data_s_out == data_m_in) 90 | $display("PASS! data_s_out = %h, data_m_in = %h", data_s_out, data_m_in); 91 | else 92 | $display("FAIL! data_s_out = %h, data_m_in = %h", data_s_out, data_m_in); 93 | end 94 | 95 | always @(posedge clk) begin 96 | if (data_valid_pos) 97 | if (data_m_out == data_s_in) 98 | $display("PASS! data_m_out = %h, data_s_in = %h", data_m_out, data_s_in); 99 | else 100 | $display("FAIL! data_m_out = %h, data_s_in = %h", data_m_out, data_s_in); 101 | end 102 | //DUT 103 | SPI_loopback 104 | #( 105 | .CLK_FREQUENCE (CLK_FREQUENCE ), 106 | .SPI_FREQUENCE (SPI_FREQUENCE ), 107 | .DATA_WIDTH (DATA_WIDTH ), 108 | .CPOL (CPOL ), 109 | .CPHA (CPHA ) 110 | ) 111 | u_SPI_loopback( 112 | .clk (clk ), 113 | .rst_n (rst_n ), 114 | .data_m_in (data_m_in ), 115 | .data_s_in (data_s_in ), 116 | .start_m (start_m ), 117 | .finish_m (finish_m ), 118 | .data_m_out (data_m_out ), 119 | .data_s_out (data_s_out ), 120 | .data_valid_s (data_valid_s ) 121 | ); 122 | 123 | endmodule // SPI_loopback_tb 124 | -------------------------------------------------------------------------------- /I2C and SPI Protocols/SPI/Master.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Test134n/32-Verilog-Mini-Projects/f6458719db15c2b348ec63d70c5ab7572b771341/I2C and SPI Protocols/SPI/Master.jpg -------------------------------------------------------------------------------- /I2C and SPI Protocols/SPI/Master.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns/1ps 2 | 3 | module spi_master 4 | #( 5 | parameter CLK_FREQUENCE = 50_000_000 , //system clk frequence 6 | SPI_FREQUENCE = 5_000_000 , //spi clk frequence 7 | DATA_WIDTH = 8 , //serial word length 8 | CPOL = 0 , //SPI mode selection (mode 0 default) 9 | CPHA = 0 //CPOL = clock polarity, CPHA = clock phase 10 | ) 11 | ( 12 | input clk , //system clk 13 | input rst_n , //system reset 14 | input [DATA_WIDTH-1:0] data_in , //the data sent by mosi 15 | input start , //a pluse to start the SPI transmission 16 | input miso , //spi bus miso input 17 | output reg sclk , //spi bus sclk 18 | output reg cs_n , //spi bus slave select line 19 | output mosi , //spi bus mosi output 20 | output reg finish , //a pluse to indicate the SPI transmission finish and the data_out valid 21 | output reg [DATA_WIDTH-1:0] data_out //the data received by miso,valid when the finish is high 22 | ); 23 | 24 | localparam FREQUENCE_CNT = CLK_FREQUENCE/SPI_FREQUENCE - 1 , 25 | SHIFT_WIDTH = log2(DATA_WIDTH) , 26 | CNT_WIDTH = log2(FREQUENCE_CNT) ; 27 | 28 | localparam IDLE = 3'b000 , 29 | LOAD = 3'b001 , 30 | SHIFT = 3'b010 , 31 | DONE = 3'b100 ; 32 | 33 | reg [2:0] cstate ; //FSM current state 34 | reg [2:0] nstate ; //FSM next state 35 | reg clk_cnt_en ; //start clk_cnt to generate sclk 36 | reg sclk_a ; //sclk register to capture the edge of sclk 37 | reg sclk_b ; //sclk register to capture the edge of sclk 38 | wire sclk_posedge; //posedge of sclk 39 | wire sclk_negedge; //negedge of sclk 40 | wire shift_en ; //the signal to enable shift register to generate mosi 41 | wire sampl_en ; //the signal to sample the data from miso 42 | reg [CNT_WIDTH-1:0] clk_cnt ; //the counter to generate sclk 43 | reg [SHIFT_WIDTH-1:0] shift_cnt ; //the counter to count the number of shifts 44 | reg [DATA_WIDTH-1:0] data_reg ; //the register to latch the data_in,also the shift register 45 | //the counter to generate the sclk 46 | always @(posedge clk or negedge rst_n) begin 47 | if (!rst_n) 48 | clk_cnt <= 'd0; 49 | else if (clk_cnt_en) 50 | if (clk_cnt == FREQUENCE_CNT) 51 | clk_cnt <= 'd0; 52 | else 53 | clk_cnt <= clk_cnt + 1'b1; 54 | else 55 | clk_cnt <= 'd0; 56 | end 57 | //generate the sclk 58 | always @(posedge clk or negedge rst_n) begin 59 | if (!rst_n) 60 | sclk <= CPOL; 61 | else if (clk_cnt_en) 62 | if (clk_cnt == FREQUENCE_CNT) 63 | sclk <= ~sclk; 64 | else 65 | sclk <= sclk; 66 | else 67 | sclk <= CPOL; 68 | end 69 | //------------------------------------------ 70 | //to capture the edge of sclk 71 | always @(posedge clk or negedge rst_n) begin 72 | if (!rst_n) begin 73 | sclk_a <= CPOL; 74 | sclk_b <= CPOL; 75 | end else if (clk_cnt_en) begin 76 | sclk_a <= sclk; 77 | sclk_b <= sclk_a; 78 | end 79 | end 80 | 81 | assign sclk_posedge = ~sclk_b & sclk_a; 82 | assign sclk_negedge = ~sclk_a & sclk_b; 83 | //---------------------------------------- 84 | //============================================== 85 | //==============GENERATE BLOCKS================= 86 | generate 87 | case (CPHA) 88 | 0: assign sampl_en = sclk_posedge; 89 | 1: assign sampl_en = sclk_negedge; 90 | default: assign sampl_en = sclk_posedge; 91 | endcase 92 | endgenerate 93 | 94 | generate 95 | case (CPHA) 96 | 0: assign shift_en = sclk_negedge; 97 | 1: assign shift_en = sclk_posedge; 98 | default: assign shift_en = sclk_posedge; 99 | endcase 100 | endgenerate 101 | //============================================= 102 | //FSM-1 103 | always @(posedge clk or negedge rst_n) begin 104 | if (!rst_n) 105 | cstate <= IDLE; 106 | else 107 | cstate <= nstate; 108 | end 109 | //FSM-2 110 | always @(*) begin 111 | case (cstate) 112 | IDLE : nstate = start ? LOAD : IDLE; 113 | LOAD : nstate = SHIFT; 114 | SHIFT : nstate = (shift_cnt == DATA_WIDTH) ? DONE : SHIFT; 115 | DONE : nstate = IDLE; 116 | default: nstate = IDLE; 117 | endcase 118 | end 119 | //FSM-3 120 | always @(posedge clk or negedge rst_n) begin 121 | if (!rst_n) begin 122 | clk_cnt_en <= 1'b0 ; 123 | data_reg <= 'd0 ; 124 | cs_n <= 1'b1 ; 125 | shift_cnt <= 'd0 ; 126 | finish <= 1'b0 ; 127 | end else begin 128 | case (nstate) 129 | IDLE : begin 130 | clk_cnt_en <= 1'b0 ; 131 | data_reg <= 'd0 ; 132 | cs_n <= 1'b1 ; 133 | shift_cnt <= 'd0 ; 134 | finish <= 1'b0 ; 135 | end 136 | LOAD : begin 137 | clk_cnt_en <= 1'b1 ; 138 | data_reg <= data_in ; 139 | cs_n <= 1'b0 ; 140 | shift_cnt <= 'd0 ; 141 | finish <= 1'b0 ; 142 | end 143 | SHIFT : begin 144 | if (shift_en) begin 145 | shift_cnt <= shift_cnt + 1'b1 ; 146 | data_reg <= {data_reg[DATA_WIDTH-2:0],1'b0}; 147 | end else begin 148 | shift_cnt <= shift_cnt ; 149 | data_reg <= data_reg ; 150 | end 151 | clk_cnt_en <= 1'b1 ; 152 | cs_n <= 1'b0 ; 153 | finish <= 1'b0 ; 154 | end 155 | DONE : begin 156 | clk_cnt_en <= 1'b0 ; 157 | data_reg <= 'd0 ; 158 | cs_n <= 1'b1 ; 159 | data_reg <= 'd0 ; 160 | finish <= 1'b1 ; 161 | end 162 | default : begin 163 | clk_cnt_en <= 1'b0 ; 164 | data_reg <= 'd0 ; 165 | cs_n <= 1'b1 ; 166 | data_reg <= 'd0 ; 167 | finish <= 1'b0 ; 168 | end 169 | endcase 170 | end 171 | end 172 | //mosi output MSB first 173 | assign mosi = data_reg[DATA_WIDTH-1]; 174 | //sample data from the miso line 175 | always @(posedge clk or negedge rst_n) begin 176 | if (!rst_n) 177 | data_out <= 'd0; 178 | else if (sampl_en) 179 | data_out <= {data_out[DATA_WIDTH-1:0],miso}; 180 | else 181 | data_out <= data_out; 182 | end 183 | //the function to get the width of data 184 | function integer log2(input integer v); 185 | begin 186 | log2=0; 187 | while(v>>log2) 188 | log2=log2+1; 189 | end 190 | endfunction 191 | 192 | endmodule 193 | -------------------------------------------------------------------------------- /I2C and SPI Protocols/SPI/Master_tb.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns/1ps 2 | 3 | module SPI_Master_tb(); 4 | 5 | parameter CLK_FREQUENCE = 50_000_000 , 6 | SPI_FREQUENCE = 5_000_000 , 7 | DATA_WIDTH = 8 , 8 | CPOL = 1 , 9 | CPHA = 1 ; 10 | 11 | reg clk ; 12 | reg rst_n ; 13 | reg [DATA_WIDTH-1:0] data_in ; 14 | reg start ; 15 | reg miso ; 16 | wire sclk ; 17 | wire cs_n ; 18 | wire mosi ; 19 | wire finish ; 20 | wire [DATA_WIDTH-1:0] data_out ; 21 | //the clk generation 22 | initial begin 23 | clk = 1; 24 | forever #10 clk = ~clk; 25 | end 26 | //the rst_n generation 27 | initial begin 28 | rst_n = 1'b0; 29 | #22 rst_n = 1'b1; 30 | end 31 | //the main block 32 | initial fork 33 | data_in_generate; 34 | start_change; 35 | debug_information; 36 | join 37 | //to generate data_in 38 | task data_in_generate; 39 | begin 40 | data_in = 'd0; 41 | @(posedge rst_n) 42 | data_in <= 8'b10100101; 43 | @(posedge finish) 44 | data_in <= 8'b10011010; 45 | @(negedge finish) 46 | ; 47 | @(negedge finish) 48 | #20 $finish; 49 | end 50 | endtask 51 | //to generate the start signal 52 | task start_change; 53 | begin 54 | start = 1'b0; 55 | @(posedge rst_n) 56 | #20 start <= 1'b1; 57 | #20 start = 1'b0; 58 | @(negedge finish) 59 | #20 start = 1'b1; 60 | #20 start = 1'b0; 61 | end 62 | endtask 63 | //to display the debug information 64 | task debug_information; 65 | begin 66 | $display("----------------------------------------------"); 67 | $display("------------------ -----------------------"); 68 | $display("----------- SIMULATION RESULT ----------------"); 69 | $display("-------------- -------------------"); 70 | $display("---------------- ---------------------"); 71 | $display("----------------------------------------------"); 72 | $monitor("TIME = %d, mosi = %b, miso = %b, data_in = %b",$time, mosi, miso, data_in); 73 | end 74 | endtask 75 | //the generate block to generate the miso 76 | generate 77 | if(CPHA == 0) 78 | always @(negedge sclk) begin 79 | miso = $random; 80 | end 81 | else 82 | always @(posedge sclk) begin 83 | miso = $random; 84 | end 85 | endgenerate 86 | //to generate uart_frame_tx_tb.vcd 87 | initial begin 88 | 89 | end 90 | //DUT 91 | spi_master 92 | #( 93 | .CLK_FREQUENCE (CLK_FREQUENCE ), 94 | .SPI_FREQUENCE (SPI_FREQUENCE ), 95 | .DATA_WIDTH (DATA_WIDTH ), 96 | .CPOL (CPOL ), 97 | .CPHA (CPHA ) 98 | ) 99 | u_spi_master( 100 | .clk (clk ), 101 | .rst_n (rst_n ), 102 | .data_in (data_in ), 103 | .start (start ), 104 | .miso (miso ), 105 | .sclk (sclk ), 106 | .cs_n (cs_n ), 107 | .mosi (mosi ), 108 | .finish (finish ), 109 | .data_out (data_out ) 110 | ); 111 | 112 | endmodule 113 | -------------------------------------------------------------------------------- /I2C and SPI Protocols/SPI/Slave.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns/1ps 2 | 3 | module SPI_Slave 4 | #( 5 | parameter CLK_FREQUENCE = 50_000_000 , //system clk frequence 6 | SPI_FREQUENCE = 5_000_000 , //spi clk frequence 7 | DATA_WIDTH = 8 , //serial word length 8 | CPOL = 1 , //SPI mode selection (mode 0 default) 9 | CPHA = 1 //CPOL = clock polarity, CPHA = clock phase 10 | ) 11 | ( 12 | input clk , //system clk 13 | input rst_n , //system reset 14 | input [DATA_WIDTH-1:0] data_in , //the data sent by miso 15 | input sclk , //spi bus sclk 16 | input cs_n , //spi bus slave select line 17 | input mosi , //spi bus mosi input 18 | output miso , //spi bus miso output 19 | output data_valid , //the data received by mosi valid 20 | output reg [DATA_WIDTH-1:0] data_out //the data received by mosi,valid when data_valid is high 21 | ); 22 | 23 | localparam SFIFT_NUM = log2(DATA_WIDTH); 24 | 25 | reg [DATA_WIDTH-1:0] data_reg ; //the register to latch the data_in,also the shift register 26 | reg [ SFIFT_NUM-1:0] sampl_num ; //the counter to count the number of sample 27 | reg sclk_a ; //sclk register to capture the edge of sclk 28 | reg sclk_b ; //sclk register to capture the edge of sclk 29 | wire sclk_posedge; //posedge of sclk 30 | wire sclk_negedge; //negedge of sclk 31 | reg cs_n_a ; //cs_n register to capture the edge of cs_n 32 | reg cs_n_b ; //cs_n register to capture the edge of cs_n 33 | wire cs_n_negedge; //negedge of cs_n to latch the data 34 | wire shift_en ; //the signal to enable shift register to generate mosi 35 | wire sampl_en ; //the signal to sample the data from miso 36 | 37 | //to capture the edge of sclk 38 | always @(posedge clk or negedge rst_n) begin 39 | if (!rst_n) begin 40 | sclk_a <= CPOL; 41 | sclk_b <= CPOL; 42 | end else if (!cs_n) begin 43 | sclk_a <= sclk; 44 | sclk_b <= sclk_a; 45 | end 46 | end 47 | 48 | assign sclk_posedge = ~sclk_b & sclk_a; 49 | assign sclk_negedge = ~sclk_a & sclk_b; 50 | 51 | //to capture the edge of sclk 52 | always @(posedge clk or negedge rst_n) begin 53 | if (!rst_n) begin 54 | cs_n_a <= 1'b1; 55 | cs_n_b <= 1'b1; 56 | end else begin 57 | cs_n_a <= cs_n ; 58 | cs_n_b <= cs_n_a ; 59 | end 60 | end 61 | 62 | assign cs_n_negedge = ~cs_n_a & cs_n_b; 63 | 64 | //==============GENERATE BLOCKS================= 65 | generate 66 | case (CPHA) 67 | 0: assign sampl_en = sclk_posedge; 68 | 1: assign sampl_en = sclk_negedge; 69 | default: assign sampl_en = sclk_posedge; 70 | endcase 71 | endgenerate 72 | 73 | generate 74 | case (CPHA) 75 | 0: assign shift_en = sclk_negedge; 76 | 1: assign shift_en = sclk_posedge; 77 | default: assign shift_en = sclk_posedge; 78 | endcase 79 | endgenerate 80 | 81 | //the register to latch the data_in 82 | //also the shift register to generate the miso 83 | always @(posedge clk or negedge rst_n) begin 84 | if (!rst_n) 85 | data_reg <= 'd0; 86 | else if(cs_n_negedge) 87 | data_reg <= data_in; 88 | else if (!cs_n & shift_en) 89 | data_reg <= {data_reg[DATA_WIDTH-2:0],1'b0}; 90 | else 91 | data_reg <= data_reg; 92 | end 93 | //miso output MSB first 94 | assign miso = !cs_n ? data_reg[DATA_WIDTH-1] : 1'd0; 95 | 96 | //sample data from the mosi line 97 | always @(posedge clk or negedge rst_n) begin 98 | if (!rst_n) 99 | data_out <= 'd0; 100 | else if (!cs_n & sampl_en) 101 | data_out <= {data_out[DATA_WIDTH-2:0],mosi}; 102 | else 103 | data_out <= data_out; 104 | end 105 | //the counter to count the number of sampled data bit 106 | always @(posedge clk or negedge rst_n) begin 107 | if (!rst_n) 108 | sampl_num <= 'd0; 109 | else if (cs_n) 110 | sampl_num <= 'd0; 111 | else if (!cs_n & sampl_en) 112 | if (sampl_num == DATA_WIDTH) 113 | sampl_num <= 'd1; 114 | else 115 | sampl_num <= sampl_num + 1'b1; 116 | else 117 | sampl_num <= sampl_num; 118 | end 119 | //the received data valid 120 | assign data_valid = sampl_num == DATA_WIDTH; 121 | //the function to get the width of data 122 | function integer log2(input integer v); 123 | begin 124 | log2=0; 125 | while(v>>log2) 126 | log2=log2+1; 127 | end 128 | endfunction 129 | 130 | endmodule 131 | -------------------------------------------------------------------------------- /I2C and SPI Protocols/SPI/images.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Test134n/32-Verilog-Mini-Projects/f6458719db15c2b348ec63d70c5ab7572b771341/I2C and SPI Protocols/SPI/images.png -------------------------------------------------------------------------------- /LFSR and CFSR/CFSR/cfsr.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Test134n/32-Verilog-Mini-Projects/f6458719db15c2b348ec63d70c5ab7572b771341/LFSR and CFSR/CFSR/cfsr.jpg -------------------------------------------------------------------------------- /LFSR and CFSR/CFSR/cfsr.v: -------------------------------------------------------------------------------- 1 | module cfsr (); 2 | reg clk, rst; 3 | reg[7:0] x_q; 4 | reg[7:0] x_d; 5 | reg[4:0] q_cnt; 6 | 7 | integer i; 8 | integer out; 9 | //clock 10 | initial 11 | begin 12 | clk = 0; 13 | forever #10 clk = ~clk; 14 | end 15 | //reset 16 | initial begin 17 | rst = 0; 18 | # 50 rst = 1; 19 | end 20 | // Use positive edge of clock to shift the register value 21 | // Implement cyclic shift right 22 | always @(posedge clk or 23 | negedge rst) 24 | begin 25 | if (!rst) 26 | begin 27 | x_q <= 'hed; 28 | q_cnt <= 0; 29 | out = $fopen("cfsr.vec","w"); 30 | end 31 | else 32 | begin 33 | x_q <= x_d; 34 | q_cnt <= q_cnt + 1; 35 | $fdisplay(out, "Pass %d Shift value in hex %b", q_cnt, x_q); 36 | end 37 | end 38 | //shift logic 39 | always @(*) 40 | begin 41 | x_d = x_q; 42 | x_d[7] = x_q[0]; 43 | for (i=0; i<7; i=i+1) 44 | begin 45 | x_d[i] = x_q[i+1]; 46 | end 47 | end 48 | endmodule 49 | -------------------------------------------------------------------------------- /LFSR and CFSR/CFSR/cfsr.vec: -------------------------------------------------------------------------------- 1 | Pass 0 Shift value in hex 11101101 2 | Pass 1 Shift value in hex 11110110 3 | Pass 2 Shift value in hex 01111011 4 | Pass 3 Shift value in hex 10111101 5 | Pass 4 Shift value in hex 11011110 6 | Pass 5 Shift value in hex 01101111 7 | Pass 6 Shift value in hex 10110111 8 | Pass 7 Shift value in hex 11011011 9 | Pass 8 Shift value in hex 11101101 10 | Pass 9 Shift value in hex 11110110 11 | Pass 10 Shift value in hex 01111011 12 | Pass 11 Shift value in hex 10111101 13 | Pass 12 Shift value in hex 11011110 14 | Pass 13 Shift value in hex 01101111 15 | Pass 14 Shift value in hex 10110111 16 | Pass 15 Shift value in hex 11011011 17 | Pass 16 Shift value in hex 11101101 18 | Pass 17 Shift value in hex 11110110 19 | Pass 18 Shift value in hex 01111011 20 | Pass 19 Shift value in hex 10111101 21 | Pass 20 Shift value in hex 11011110 22 | Pass 21 Shift value in hex 01101111 23 | Pass 22 Shift value in hex 10110111 24 | Pass 23 Shift value in hex 11011011 25 | Pass 24 Shift value in hex 11101101 26 | Pass 25 Shift value in hex 11110110 27 | Pass 26 Shift value in hex 01111011 28 | Pass 27 Shift value in hex 10111101 29 | Pass 28 Shift value in hex 11011110 30 | Pass 29 Shift value in hex 01101111 31 | Pass 30 Shift value in hex 10110111 32 | Pass 31 Shift value in hex 11011011 33 | Pass 0 Shift value in hex 11101101 34 | Pass 1 Shift value in hex 11110110 35 | Pass 2 Shift value in hex 01111011 36 | Pass 3 Shift value in hex 10111101 37 | Pass 4 Shift value in hex 11011110 38 | Pass 5 Shift value in hex 01101111 39 | Pass 6 Shift value in hex 10110111 40 | Pass 7 Shift value in hex 11011011 41 | Pass 8 Shift value in hex 11101101 42 | Pass 9 Shift value in hex 11110110 43 | Pass 10 Shift value in hex 01111011 44 | Pass 11 Shift value in hex 10111101 45 | Pass 12 Shift value in hex 11011110 46 | Pass 13 Shift value in hex 01101111 47 | Pass 14 Shift value in hex 10110111 48 | Pass 15 Shift value in hex 11011011 49 | -------------------------------------------------------------------------------- /LFSR and CFSR/LFSR/lfsr.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Test134n/32-Verilog-Mini-Projects/f6458719db15c2b348ec63d70c5ab7572b771341/LFSR and CFSR/LFSR/lfsr.jpg -------------------------------------------------------------------------------- /LFSR and CFSR/LFSR/lfsr.v: -------------------------------------------------------------------------------- 1 | module lfsr (out, clk, rst); 2 | 3 | output reg [3:0] out; 4 | input clk, rst; 5 | 6 | wire feedback; 7 | 8 | assign feedback = ~(out[3] ^ out[2]); 9 | 10 | always @(posedge clk, posedge rst) 11 | begin 12 | if (rst) 13 | out = 4'b0; 14 | else 15 | out = {out[2:0],feedback}; 16 | end 17 | endmodule 18 | -------------------------------------------------------------------------------- /LFSR and CFSR/LFSR/lfsr_tb.v: -------------------------------------------------------------------------------- 1 | module lfsr_tb(); 2 | reg clk_tb; 3 | reg rst_tb; 4 | wire [3:0] out_tb; 5 | 6 | initial 7 | begin 8 | clk_tb = 0; 9 | rst_tb = 1; 10 | #15; 11 | 12 | rst_tb = 0; 13 | #200; 14 | end 15 | 16 | always 17 | begin 18 | #5; 19 | clk_tb = ~ clk_tb; 20 | end 21 | 22 | lfsr DUT(out_tb,clk_tb,rst_tb); 23 | endmodule 24 | -------------------------------------------------------------------------------- /LICENCE.txt: -------------------------------------------------------------------------------- 1 | CERN Open Hardware Licence Version 2 - Weakly Reciprocal 2 | 3 | 4 | Preamble 5 | 6 | CERN has developed this licence to promote collaboration among hardware 7 | designers and to provide a legal tool which supports the freedom to use, 8 | study, modify, share and distribute hardware designs and products based on 9 | those designs. Version 2 of the CERN Open Hardware Licence comes in three 10 | variants: CERN-OHL-P (permissive); and two reciprocal licences: this licence, 11 | CERN-OHL-W (weakly reciprocal) and CERN-OHL-S (strongly reciprocal). 12 | 13 | The CERN-OHL-W is copyright CERN 2020. Anyone is welcome to use it, in 14 | unmodified form only. 15 | 16 | Use of this Licence does not imply any endorsement by CERN of any Licensor or 17 | their designs nor does it imply any involvement by CERN in their development. 18 | 19 | 20 | 1 Definitions 21 | 22 | 1.1 'Licence' means this CERN-OHL-W. 23 | 24 | 1.2 'Compatible Licence' means 25 | 26 | a) any earlier version of the CERN Open Hardware licence, or 27 | 28 | b) any version of the CERN-OHL-S or the CERN-OHL-W, or 29 | 30 | c) any licence which permits You to treat the Source to which it 31 | applies as licensed under CERN-OHL-S or CERN-OHL-W provided that on 32 | Conveyance of any such Source, or any associated Product You treat 33 | the Source in question as being licensed under CERN-OHL-S or 34 | CERN-OHL-W as appropriate. 35 | 36 | 1.3 'Source' means information such as design materials or digital code 37 | which can be applied to Make or test a Product or to prepare a Product 38 | for use, Conveyance or sale, regardless of its medium or how it is 39 | expressed. It may include Notices. 40 | 41 | 1.4 'Covered Source' means Source that is explicitly made available under 42 | this Licence. 43 | 44 | 1.5 'Product' means any device, component, work or physical object, whether 45 | in finished or intermediate form, arising from the use, application or 46 | processing of Covered Source. 47 | 48 | 1.6 'Make' means to create or configure something, whether by manufacture, 49 | assembly, compiling, loading or applying Covered Source or another 50 | Product or otherwise. 51 | 52 | 1.7 'Available Component' means any part, sub-assembly, library or code 53 | which: 54 | 55 | a) is licensed to You as Complete Source under a Compatible Licence; or 56 | 57 | b) is available, at the time a Product or the Source containing it is 58 | first Conveyed, to You and any other prospective licensees 59 | 60 | i) with sufficient rights and information (including any 61 | configuration and programming files and information about its 62 | characteristics and interfaces) to enable it either to be Made 63 | itself, or to be sourced and used to Make the Product; or 64 | ii) as part of the normal distribution of a tool used to design or 65 | Make the Product. 66 | 67 | 1.8 'External Material' means anything (including Source) which: 68 | 69 | a) is only combined with Covered Source in such a way that it 70 | interfaces with the Covered Source using a documented interface 71 | which is described in the Covered Source; and 72 | 73 | b) is not a derivative of or contains Covered Source, or, if it is, it 74 | is solely to the extent necessary to facilitate such interfacing. 75 | 76 | 1.9 'Complete Source' means the set of all Source necessary to Make a 77 | Product, in the preferred form for making modifications, including 78 | necessary installation and interfacing information both for the Product, 79 | and for any included Available Components. If the format is 80 | proprietary, it must also be made available in a format (if the 81 | proprietary tool can create it) which is viewable with a tool available 82 | to potential licensees and licensed under a licence approved by the Free 83 | Software Foundation or the Open Source Initiative. Complete Source need 84 | not include the Source of any Available Component, provided that You 85 | include in the Complete Source sufficient information to enable a 86 | recipient to Make or source and use the Available Component to Make the 87 | Product. 88 | 89 | 1.10 'Source Location' means a location where a Licensor has placed Covered 90 | Source, and which that Licensor reasonably believes will remain easily 91 | accessible for at least three years for anyone to obtain a digital copy. 92 | 93 | 1.11 'Notice' means copyright, acknowledgement and trademark notices, Source 94 | Location references, modification notices (subsection 3.3(b)) and all 95 | notices that refer to this Licence and to the disclaimer of warranties 96 | that are included in the Covered Source. 97 | 98 | 1.12 'Licensee' or 'You' means any person exercising rights under this 99 | Licence. 100 | 101 | 1.13 'Licensor' means a natural or legal person who creates or modifies 102 | Covered Source. A person may be a Licensee and a Licensor at the same 103 | time. 104 | 105 | 1.14 'Convey' means to communicate to the public or distribute. 106 | 107 | 108 | 2 Applicability 109 | 110 | 2.1 This Licence governs the use, copying, modification, Conveying of 111 | Covered Source and Products, and the Making of Products. By exercising 112 | any right granted under this Licence, You irrevocably accept these terms 113 | and conditions. 114 | 115 | 2.2 This Licence is granted by the Licensor directly to You, and shall apply 116 | worldwide and without limitation in time. 117 | 118 | 2.3 You shall not attempt to restrict by contract or otherwise the rights 119 | granted under this Licence to other Licensees. 120 | 121 | 2.4 This Licence is not intended to restrict fair use, fair dealing, or any 122 | other similar right. 123 | 124 | 125 | 3 Copying, Modifying and Conveying Covered Source 126 | 127 | 3.1 You may copy and Convey verbatim copies of Covered Source, in any 128 | medium, provided You retain all Notices. 129 | 130 | 3.2 You may modify Covered Source, other than Notices, provided that You 131 | irrevocably undertake to make that modified Covered Source available 132 | from a Source Location should You Convey a Product in circumstances 133 | where the recipient does not otherwise receive a copy of the modified 134 | Covered Source. In each case subsection 3.3 shall apply. 135 | 136 | You may only delete Notices if they are no longer applicable to the 137 | corresponding Covered Source as modified by You and You may add 138 | additional Notices applicable to Your modifications. 139 | 140 | 3.3 You may Convey modified Covered Source (with the effect that You shall 141 | also become a Licensor) provided that You: 142 | 143 | a) retain Notices as required in subsection 3.2; 144 | 145 | b) add a Notice to the modified Covered Source stating that You have 146 | modified it, with the date and brief description of how You have 147 | modified it; 148 | 149 | c) add a Source Location Notice for the modified Covered Source if You 150 | Convey in circumstances where the recipient does not otherwise 151 | receive a copy of the modified Covered Source; and 152 | 153 | d) license the modified Covered Source under the terms and conditions 154 | of this Licence (or, as set out in subsection 8.3, a later version, 155 | if permitted by the licence of the original Covered Source). Such 156 | modified Covered Source must be licensed as a whole, but excluding 157 | Available Components contained in it or External Material to which 158 | it is interfaced, which remain licensed under their own applicable 159 | licences. 160 | 161 | 162 | 4 Making and Conveying Products 163 | 164 | 4.1 You may Make Products, and/or Convey them, provided that You either 165 | provide each recipient with a copy of the Complete Source or ensure that 166 | each recipient is notified of the Source Location of the Complete 167 | Source. That Complete Source includes Covered Source and You must 168 | accordingly satisfy Your obligations set out in subsection 3.3. If 169 | specified in a Notice, the Product must visibly and securely display the 170 | Source Location on it or its packaging or documentation in the manner 171 | specified in that Notice. 172 | 173 | 4.2 Where You Convey a Product which incorporates External Material, the 174 | Complete Source for that Product which You are required to provide under 175 | subsection 4.1 need not include any Source for the External Material. 176 | 177 | 4.3 You may license Products under terms of Your choice, provided that such 178 | terms do not restrict or attempt to restrict any recipients' rights 179 | under this Licence to the Covered Source. 180 | 181 | 182 | 5 Research and Development 183 | 184 | You may Convey Covered Source, modified Covered Source or Products to a legal 185 | entity carrying out development, testing or quality assurance work on Your 186 | behalf provided that the work is performed on terms which prevent the entity 187 | from both using the Source or Products for its own internal purposes and 188 | Conveying the Source or Products or any modifications to them to any person 189 | other than You. Any modifications made by the entity shall be deemed to be 190 | made by You pursuant to subsection 3.2. 191 | 192 | 193 | 6 DISCLAIMER AND LIABILITY 194 | 195 | 6.1 DISCLAIMER OF WARRANTY -- The Covered Source and any Products are 196 | provided 'as is' and any express or implied warranties, including, but 197 | not limited to, implied warranties of merchantability, of satisfactory 198 | quality, non-infringement of third party rights, and fitness for a 199 | particular purpose or use are disclaimed in respect of any Source or 200 | Product to the maximum extent permitted by law. The Licensor makes no 201 | representation that any Source or Product does not or will not infringe 202 | any patent, copyright, trade secret or other proprietary right. The 203 | entire risk as to the use, quality, and performance of any Source or 204 | Product shall be with You and not the Licensor. This disclaimer of 205 | warranty is an essential part of this Licence and a condition for the 206 | grant of any rights granted under this Licence. 207 | 208 | 6.2 EXCLUSION AND LIMITATION OF LIABILITY -- The Licensor shall, to the 209 | maximum extent permitted by law, have no liability for direct, indirect, 210 | special, incidental, consequential, exemplary, punitive or other damages 211 | of any character including, without limitation, procurement of 212 | substitute goods or services, loss of use, data or profits, or business 213 | interruption, however caused and on any theory of contract, warranty, 214 | tort (including negligence), product liability or otherwise, arising in 215 | any way in relation to the Covered Source, modified Covered Source 216 | and/or the Making or Conveyance of a Product, even if advised of the 217 | possibility of such damages, and You shall hold the Licensor(s) free and 218 | harmless from any liability, costs, damages, fees and expenses, 219 | including claims by third parties, in relation to such use. 220 | 221 | 222 | 7 Patents 223 | 224 | 7.1 Subject to the terms and conditions of this Licence, each Licensor 225 | hereby grants to You a perpetual, worldwide, non-exclusive, no-charge, 226 | royalty-free, irrevocable (except as stated in subsections 7.2 and 8.4) 227 | patent licence to Make, have Made, use, offer to sell, sell, import, and 228 | otherwise transfer the Covered Source and Products, where such licence 229 | applies only to those patent claims licensable by such Licensor that are 230 | necessarily infringed by exercising rights under the Covered Source as 231 | Conveyed by that Licensor. 232 | 233 | 7.2 If You institute patent litigation against any entity (including a 234 | cross-claim or counterclaim in a lawsuit) alleging that the Covered 235 | Source or a Product constitutes direct or contributory patent 236 | infringement, or You seek any declaration that a patent licensed to You 237 | under this Licence is invalid or unenforceable then any rights granted 238 | to You under this Licence shall terminate as of the date such process is 239 | initiated. 240 | 241 | 242 | 8 General 243 | 244 | 8.1 If any provisions of this Licence are or subsequently become invalid or 245 | unenforceable for any reason, the remaining provisions shall remain 246 | effective. 247 | 248 | 8.2 You shall not use any of the name (including acronyms and 249 | abbreviations), image, or logo by which the Licensor or CERN is known, 250 | except where needed to comply with section 3, or where the use is 251 | otherwise allowed by law. Any such permitted use shall be factual and 252 | shall not be made so as to suggest any kind of endorsement or 253 | implication of involvement by the Licensor or its personnel. 254 | 255 | 8.3 CERN may publish updated versions and variants of this Licence which it 256 | considers to be in the spirit of this version, but may differ in detail 257 | to address new problems or concerns. New versions will be published with 258 | a unique version number and a variant identifier specifying the variant. 259 | If the Licensor has specified that a given variant applies to the 260 | Covered Source without specifying a version, You may treat that Covered 261 | Source as being released under any version of the CERN-OHL with that 262 | variant. If no variant is specified, the Covered Source shall be treated 263 | as being released under CERN-OHL-S. The Licensor may also specify that 264 | the Covered Source is subject to a specific version of the CERN-OHL or 265 | any later version in which case You may apply this or any later version 266 | of CERN-OHL with the same variant identifier published by CERN. 267 | 268 | You may treat Covered Source licensed under CERN-OHL-W as licensed under 269 | CERN-OHL-S if and only if all Available Components referenced in the 270 | Covered Source comply with the corresponding definition of Available 271 | Component for CERN-OHL-S. 272 | 273 | 8.4 This Licence shall terminate with immediate effect if You fail to comply 274 | with any of its terms and conditions. 275 | 276 | 8.5 However, if You cease all breaches of this Licence, then Your Licence 277 | from any Licensor is reinstated unless such Licensor has terminated this 278 | Licence by giving You, while You remain in breach, a notice specifying 279 | the breach and requiring You to cure it within 30 days, and You have 280 | failed to come into compliance in all material respects by the end of 281 | the 30 day period. Should You repeat the breach after receipt of a cure 282 | notice and subsequent reinstatement, this Licence will terminate 283 | immediately and permanently. Section 6 shall continue to apply after any 284 | termination. 285 | 286 | 8.6 This Licence shall not be enforceable except by a Licensor acting as 287 | such, and third party beneficiary rights are specifically excluded. 288 | -------------------------------------------------------------------------------- /Logarithm Implementation/log.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Test134n/32-Verilog-Mini-Projects/f6458719db15c2b348ec63d70c5ab7572b771341/Logarithm Implementation/log.jpg -------------------------------------------------------------------------------- /Logarithm Implementation/log.v: -------------------------------------------------------------------------------- 1 | module logarithm(input [31:0] a,b,output [127:0] a_out, b_out); 2 | assign a_out = 1000000000 * $ln(a); 3 | assign b_out = 1000000000 * $log10(b); 4 | endmodule 5 | 6 | module logarithm_tb; 7 | reg [31:0] a; 8 | reg [31:0] b; 9 | wire [127:0] a_out; 10 | wire [127:0] b_out; 11 | logarithm uut(a,b,a_out,b_out); 12 | initial begin 13 | a=0;b=0; 14 | #20 a= 123;b=123; 15 | #20 a =4;b=4; 16 | #20 a=234;b=34; 17 | end 18 | 19 | initial 20 | $monitor(" a = %d, b = %d, ln(a) = %d, log10(b) = %d",a,b,a_out,b_out); 21 | 22 | endmodule 23 | -------------------------------------------------------------------------------- /Mealy and Moore State Machine Implementation of Sequence Detector/mealy.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Test134n/32-Verilog-Mini-Projects/f6458719db15c2b348ec63d70c5ab7572b771341/Mealy and Moore State Machine Implementation of Sequence Detector/mealy.jpg -------------------------------------------------------------------------------- /Mealy and Moore State Machine Implementation of Sequence Detector/mealy.v: -------------------------------------------------------------------------------- 1 | module state_machine_mealy(clk, reset, in, out); 2 | parameter zero=0, one1=1, two1s=2; 3 | output out; input clk, reset, in; 4 | reg out; reg [1:0] state, next_state; 5 | // Implement the state register 6 | always @(posedge clk or posedge reset) begin 7 | if (reset) 8 | state <= zero; 9 | else 10 | state <= next_state; 11 | end 12 | always @(state or in) begin 13 | case (state) 14 | zero: begin //last input was a zero out = 0; 15 | if (in) 16 | next_state=one1; 17 | else 18 | next_state=zero; 19 | end 20 | one1: begin //we've seen one 1 out = 0; 21 | if (in) 22 | next_state=two1s; 23 | else 24 | next_state=zero; 25 | end 26 | two1s: begin //we've seen at least 2 ones out = 1; 27 | if (in) 28 | next_state=two1s; 29 | else 30 | next_state=zero; 31 | end 32 | default: //in case we reach a bad state out = 0; 33 | next_state=zero; 34 | endcase 35 | end 36 | // output logic 37 | always @(state) begin 38 | case (state) 39 | zero: out <= 0; 40 | one1: out <= 0; 41 | two1s: out <= 1; 42 | default : out <= 0; 43 | endcase 44 | end 45 | endmodule 46 | 47 | module state_machine_mealy_tb(); 48 | reg clk, reset, in; 49 | wire out; 50 | integer i; 51 | 52 | state_machine_mealy dut(clk, reset, in, out); 53 | initial 54 | forever #5 clk = ~clk; 55 | 56 | initial begin 57 | reset = 1'b1; 58 | clk = 1'b0; 59 | in = 0 ; 60 | #6; 61 | reset = 1'b0; 62 | 63 | for (i = 0; i<10 ; i = i+1) 64 | begin 65 | @(negedge clk); #1; 66 | in = $random; 67 | if (out == 1'b1) 68 | $display("PASS: Sequence 11 detected i = %d\n", i); 69 | end 70 | #50; 71 | $finish; 72 | end 73 | endmodule 74 | -------------------------------------------------------------------------------- /Mealy and Moore State Machine Implementation of Sequence Detector/moore.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Test134n/32-Verilog-Mini-Projects/f6458719db15c2b348ec63d70c5ab7572b771341/Mealy and Moore State Machine Implementation of Sequence Detector/moore.jpg -------------------------------------------------------------------------------- /Mealy and Moore State Machine Implementation of Sequence Detector/moore.v: -------------------------------------------------------------------------------- 1 | module state_machine_moore(clk, reset, in, out); 2 | parameter zero=0, one1=1, two1s=2; 3 | output out; input clk, reset, in; 4 | reg out; reg [1:0] state, next_state; 5 | // Implement the state register 6 | always @(posedge clk or posedge reset) begin 7 | if (reset) 8 | state <= zero; 9 | else 10 | state <= next_state; 11 | end 12 | always @(state or in) begin 13 | case (state) 14 | zero: begin //last input was a zero out = 0; 15 | if (in) 16 | next_state=one1; 17 | else 18 | next_state=zero; 19 | end 20 | one1: begin //we've seen one 1 out = 0; 21 | if (in) 22 | next_state=two1s; 23 | else 24 | next_state=zero; 25 | end 26 | two1s: begin //we've seen at least 2 ones out = 1; 27 | if (in) 28 | next_state=two1s; 29 | else 30 | next_state=zero; 31 | end 32 | default: //in case we reach a bad state out = 0; 33 | next_state=zero; 34 | endcase 35 | end 36 | // output logic 37 | always @(state) begin 38 | case (state) 39 | zero: out <= 0; 40 | one1: out <= 0; 41 | two1s: out <= 1; 42 | default : out <= 0; 43 | endcase 44 | end 45 | endmodule 46 | 47 | module state_machine_moore_tb(); 48 | reg clk, reset, in; 49 | wire out; 50 | integer i; 51 | 52 | state_machine_moore dut(clk, reset, in, out); 53 | initial 54 | forever #5 clk = ~clk; 55 | 56 | initial begin 57 | reset = 1'b1; 58 | clk = 1'b0; 59 | in = 0 ; 60 | #6; 61 | reset = 1'b0; 62 | 63 | for (i = 0; i<10 ; i = i+1) 64 | begin 65 | @(negedge clk); #1; 66 | in = $random; 67 | if (out == 1'b1) 68 | $display("PASS: Sequence 11 detected i = %d\n", i); 69 | end 70 | #50; 71 | $finish; 72 | end 73 | endmodule 74 | -------------------------------------------------------------------------------- /Modified Booth Algorithm/modified_booth.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Test134n/32-Verilog-Mini-Projects/f6458719db15c2b348ec63d70c5ab7572b771341/Modified Booth Algorithm/modified_booth.jpg -------------------------------------------------------------------------------- /Modified Booth Algorithm/modified_booth.v: -------------------------------------------------------------------------------- 1 | module MBA_module(p,a,b,clock); 2 | output [15:0] p; 3 | input [7:0] a, b; 4 | input clock; 5 | reg [15:0] p,ans; 6 | 7 | integer i, lookup_tbl; 8 | integer operate; 9 | 10 | initial 11 | begin 12 | p=16'b0; 13 | ans=16'b0; 14 | end 15 | 16 | always @(negedge clock) 17 | begin 18 | p=16'b0; 19 | for(i=1;i<=7;i=i+2) 20 | begin 21 | if(i==1) 22 | lookup_tbl = 0; 23 | else 24 | lookup_tbl = b[i-2]; 25 | 26 | lookup_tbl = lookup_tbl + 4*b[i] + 2*b[i-1]; 27 | 28 | if(lookup_tbl == 0 || lookup_tbl == 7) 29 | operate = 0; 30 | else if(lookup_tbl == 3 || lookup_tbl == 4) 31 | operate = 2; 32 | else 33 | operate = 1; 34 | if(b[i] == 1) 35 | operate = -1*operate; 36 | 37 | case(operate) 38 | 1: 39 | begin 40 | ans=a; 41 | ans=ans<<(i-1); 42 | p=p+ans; 43 | end 44 | 2: 45 | begin 46 | ans=a<<1; 47 | ans=ans<<(i-1); 48 | p=p+ans; 49 | end 50 | -1: 51 | begin 52 | ans=~a+1; 53 | ans=ans<<(i-1); 54 | p=p+ans; 55 | end 56 | -2: 57 | begin 58 | ans=a<<1; 59 | ans=~ans+1; 60 | ans=ans<<(i-1); 61 | p=p+ans; 62 | end 63 | endcase 64 | end 65 | end 66 | endmodule 67 | 68 | -------------------------------------------------------------------------------- /Modified Booth Algorithm/modified_booth_tb.v: -------------------------------------------------------------------------------- 1 | module MBA_mod_tb; 2 | 3 | // Inputs 4 | reg [7:0] a; 5 | reg [7:0] b; 6 | reg clock; 7 | 8 | // Outputs 9 | wire [15:0] p; 10 | 11 | // Variables 12 | integer j,k; 13 | 14 | // Instantiate the Unit Under Test (UUT) 15 | MBA_module uut ( 16 | .p(p), 17 | .a(a), 18 | .b(b), 19 | .clock(clock) 20 | ); 21 | 22 | initial clock = 0; 23 | always #5 clock = ~clock; 24 | 25 | initial 26 | begin 27 | a=0; 28 | b=0; 29 | for (j=1; j<10; j=j+1) 30 | for (k=1; k<11; k=k+1) 31 | begin 32 | a=j; 33 | b=k; 34 | #20 $display("a * b = %d * %d = p = %d", a, b, p); 35 | end 36 | end 37 | endmodule 38 | -------------------------------------------------------------------------------- /Pipelined Multiplier/pipelined multiplier.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Test134n/32-Verilog-Mini-Projects/f6458719db15c2b348ec63d70c5ab7572b771341/Pipelined Multiplier/pipelined multiplier.jpg -------------------------------------------------------------------------------- /Pipelined Multiplier/pipelined_multiplier.v: -------------------------------------------------------------------------------- 1 | module MULTI_32bit(clk, rst,A, B, F); 2 | `define BIAS 8'b01111111 3 | input clk, rst; 4 | input [31:0]A; 5 | input [31:0]B; 6 | 7 | output [31:0]F; 8 | reg [31:0]F; 9 | 10 | 11 | // reg [1:0]sign; 12 | // reg [49:0]mantissa; 13 | 14 | 15 | //////////////// PIPE-LINE REGISTERS ///////////////// 16 | reg [62:0] P1; 17 | reg [66:0] P2; 18 | reg [31:0] P3; 19 | ////////////////////////////////////////////////////// 20 | 21 | initial 22 | begin 23 | P1 = 0; 24 | P2 = 0; 25 | P3 = 0; 26 | end 27 | 28 | 29 | wire [1:0]sign; 30 | wire [49:0]mantissa; 31 | 32 | assign sign = A[31]+B[31]; 33 | 34 | //always @ ( F or A or B ) 35 | always @ ( posedge clk ) 36 | begin 37 | //solve for the sign bit part 38 | ///////////////////////////////////////////////////////// 39 | P1[0] <= (sign == 1'b1) ? 1'b1 : 1'b0; 40 | P1[31:1] <= A[30:0]; 41 | P1[62:32] <= B[30:0]; 42 | 43 | /////////////////////////////////////////////////////////// 44 | P2[0] <= P1[0]; 45 | P2[50:1] <= P1[23:1] * P1[54:32]; 46 | 47 | P2[58:51] <= P1[31:24]; 48 | P2[66:59] <= P1[62:55]; 49 | 50 | /////////////////////////////////////////////////////////// 51 | P3[0] <= P2[0]; 52 | 53 | if(P2[50:24] == 0) begin 54 | P3[23:1] = P2[23:1]; 55 | P3[31:24] = P2[58:51] + P2[66:59] - `BIAS + 8'h00; 56 | end 57 | else if(P2[50] == 1) begin 58 | P3[23:1] = P2[49:27]; 59 | P3[31:24] = P2[58:51] + P2[66:59] - `BIAS + 8'h1a; 60 | end 61 | else if(P2[49] == 1) begin 62 | P3[23:1] = P2[48:26]; 63 | P3[31:24] = P2[58:51] + P2[66:59] - `BIAS + 8'h19; 64 | end 65 | else if(P2[48] == 1) begin 66 | P3[23:1] = P2[47:25]; 67 | P3[31:24] = P2[58:51] + P2[66:59] - `BIAS + 8'h18; 68 | end 69 | else if(P2[47] == 1) begin 70 | P3[23:1] = P2[46:24]; 71 | P3[31:24] = P2[58:51] + P2[66:59] - `BIAS + 8'h17; 72 | end 73 | else if(P2[46] == 1) begin 74 | P3[23:1] = P2[45:23]; 75 | P3[31:24] = P2[58:51] + P2[66:59] - `BIAS + 8'h16; 76 | end 77 | else if(P2[45] == 1) begin 78 | P3[23:1] = P2[44:22]; 79 | P3[31:24] = P2[58:51] + P2[66:59] - `BIAS + 8'h15; 80 | end 81 | else if(P2[44] == 1) begin 82 | P3[23:1] = P2[43:21]; 83 | P3[31:24] = P2[58:51] + P2[66:59] - `BIAS + 8'h14; 84 | end 85 | else if(P2[43] == 1) begin 86 | P3[23:1] = P2[42:20]; 87 | P3[31:24] = P2[58:51] + P2[66:59] - `BIAS + 8'h13; 88 | end 89 | else if(P2[42] == 1) begin 90 | P3[23:1] = P2[41:19]; 91 | P3[31:24] = P2[58:51] + P2[66:59] - `BIAS + 8'h12; 92 | end 93 | else if(P2[41] == 1) begin 94 | P3[23:1] = P2[40:18]; 95 | P3[31:24] = P2[58:51] + P2[66:59] - `BIAS + 8'h11; 96 | end 97 | else if(P2[40] == 1) begin 98 | P3[23:1] = P2[39:17]; 99 | P3[31:24] = P2[58:51] + P2[66:59] - `BIAS + 8'h10; 100 | end 101 | else if(P2[39] == 1) begin 102 | P3[23:1] = P2[38:16]; 103 | P3[31:24] = P2[58:51] + P2[66:59] - `BIAS + 8'h0f; 104 | end 105 | else if(P2[38] == 1) begin 106 | P3[23:1] = P2[37:15]; 107 | P3[31:24] = P2[58:51] + P2[66:59] - `BIAS + 8'h0e; 108 | end 109 | else if(P2[37] == 1) begin 110 | P3[23:1] = P2[36:14]; 111 | P3[31:24] = P2[58:51] + P2[66:59] - `BIAS + 8'h0d; 112 | end 113 | else if(P2[36] == 1) begin 114 | P3[23:1] = P2[35:13]; 115 | P3[31:24] = P2[58:51] + P2[66:59] - `BIAS + 8'h0c; 116 | end 117 | else if(P2[35] == 1) begin 118 | P3[23:1] = P2[34:12]; 119 | P3[31:24] = P2[58:51] + P2[66:59] - `BIAS + 8'h0b; 120 | end 121 | else if(P2[34] == 1) begin 122 | P3[23:1] = P2[33:11]; 123 | P3[31:24] = P2[58:51] + P2[66:59] - `BIAS + 8'h0a; 124 | end 125 | else if(P2[33] == 1) begin 126 | P3[23:1] = P2[32:10]; 127 | P3[31:24] = P2[58:51] + P2[66:59] - `BIAS + 8'h09; 128 | end 129 | else if(P2[32] == 1) begin 130 | P3[23:1] = P2[31:09]; 131 | P3[31:24] = P2[58:51] + P2[66:59] - `BIAS + 8'h08; 132 | end 133 | else if(P2[31] == 1) begin 134 | P3[23:1] = P2[30:08]; 135 | P3[31:24] = P2[58:51] + P2[66:59] - `BIAS + 8'h07; 136 | end 137 | else if(P2[30] == 1) begin 138 | P3[23:1] = P2[29:07]; 139 | P3[31:24] = P2[58:51] + P2[66:59] - `BIAS + 8'h06; 140 | end 141 | else if(P2[29] == 1) begin 142 | P3[23:1] = P2[28:06]; 143 | P3[31:24] = P2[58:51] + P2[66:59] - `BIAS + 8'h05; 144 | end 145 | else if(P2[28] == 1) begin 146 | P3[23:1] = P2[27:05]; 147 | P3[31:24] = P2[58:51] + P2[66:59] - `BIAS + 8'h04; 148 | end 149 | else if(P2[27] == 1) begin 150 | P3[23:1] = P2[26:04]; 151 | P3[31:24] = P2[58:51] + P2[66:59] - `BIAS + 8'h03; 152 | end 153 | else if(P2[26] == 1) begin 154 | P3[23:1] = P2[25:03]; 155 | P3[31:24] = P2[58:51] + P2[66:59] - `BIAS + 8'h02; 156 | end 157 | else begin 158 | P3[23:1] = P2[24:02]; 159 | P3[31:24] = P2[58:51] + P2[66:59] - `BIAS + 8'h01; 160 | end 161 | 162 | /////////////////////////////////////////////////////////// 163 | F[31] <= P3[0]; 164 | F[30:0] <= P3[31:1]; 165 | 166 | //////////////////////////////////////////////////////////// 167 | end 168 | 169 | endmodule 170 | 171 | 172 | 173 | -------------------------------------------------------------------------------- /Pipelined Multiplier/pipelined_multiplier_tb.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Test Bench 4 | ////////////////////////////////////////////////////////////////////////////////// 5 | 6 | module MULTI_32bit_tb; 7 | 8 | reg clk; 9 | reg rst; 10 | reg [31:0] A; 11 | reg [31:0] B; 12 | wire [31:0] F; 13 | 14 | 15 | MULTI_32bit uut ( .clk(clk), .rst(rst), .A(A), .B(B), .F(F)); 16 | 17 | initial begin 18 | A = 0; 19 | B = 0; 20 | clk <= 1'b0; 21 | rst <= 1'b1; 22 | 23 | 24 | #10 clk <= ~clk; 25 | 26 | A = 32'h0000; B = 32'h0001; 27 | 28 | #10 clk <= ~clk; 29 | #10 clk <= ~clk; 30 | 31 | A = 32'h0010; B = 32'h0001; 32 | 33 | #10 clk <= ~clk; 34 | #10 clk <= ~clk; 35 | 36 | A = 32'h00F0; B = 32'h0040; 37 | 38 | #10 clk <= ~clk; 39 | #10 clk <= ~clk; 40 | 41 | A = 32'hC000; B = 32'h1000; 42 | 43 | #10 clk <= ~clk; 44 | #10 clk <= ~clk; 45 | 46 | A = 32'hAA00; B = 32'h0100; 47 | 48 | #10 clk <= ~clk; 49 | #10 clk <= ~clk; 50 | 51 | A = 32'h0A01; B = 32'h0020; 52 | 53 | #10 clk <= ~clk; 54 | #10 clk <= ~clk; 55 | 56 | A = 32'h0030; B = 32'h0009; 57 | 58 | #10 clk <= ~clk; 59 | #10 clk <= ~clk; 60 | 61 | A = 32'h0020; B = 32'h00010; 62 | 63 | #10 clk <= ~clk; 64 | #10 clk <= ~clk; 65 | 66 | A = 32'h9000; B = 32'h8000; 67 | 68 | #10 clk <= ~clk; 69 | #10 clk <= ~clk; 70 | 71 | A = 32'h0003; B = 32'h0001; 72 | 73 | #10 clk <= ~clk; 74 | #10 clk <= ~clk; 75 | 76 | #10 clk <= ~clk; 77 | #10 clk <= ~clk; 78 | 79 | #10 clk <= ~clk; 80 | #10 clk <= ~clk; 81 | 82 | end 83 | 84 | 85 | endmodule 86 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # 32 Verilog Mini Projects 2 | Implementing 32 Verilog Mini Projects. 3 | 4 | [I2C and SPI Protocols](I2C%20and%20SPI%20Protocols)
5 | [I2C Protocol](I2C%20and%20SPI%20Protocols/I2C) 6 | ![](I2C%20and%20SPI%20Protocols/I2C/I2C.jpg) 7 | [SPI Protocol](I2C%20and%20SPI%20Protocols/SPI)
8 | [SPI_Master](I2C%20and%20SPI%20Protocols/SPI/Master.jpg) 9 | ![](I2C%20and%20SPI%20Protocols/SPI/Master.jpg) 10 | [SPI_Loopback](I2C%20and%20SPI%20Protocols/SPI/Loopback.jpg) 11 | ![](I2C%20and%20SPI%20Protocols/SPI/Loopback.jpg) 12 | [IEEE 754 Division](Floating%20Point%20IEEE%20754%20Division/division.v) 13 | ![](Floating%20Point%20IEEE%20754%20Division/IEEE_754_Division.jpg) 14 | [IEEE 754 Addition Subtraction](Floating%20Point%20IEEE%20754%20Addition%20Subtraction/Addition_Subtraction.v) 15 | ![](Floating%20Point%20IEEE%20754%20Addition%20Subtraction/IEEE_754_Addition_Substraction.jpg) 16 | [IEEE 754 Multiplication](Floating%20Point%20IEEE%20754%20Multiplication) 17 | ![](Floating%20Point%20IEEE%20754%20Multiplication/IEEE_754_Multiplication.jpg) 18 | CRC Coding 19 | [CRC_16_parallel](CRC%20Coding/CRC_16_parallel) 20 | ![](CRC%20Coding/CRC_16_parallel/CRC_16_parallel.jpg) 21 | [CRC_16_serial](CRC%20Coding/CRC_16_serial) 22 | ![](CRC%20Coding/CRC_16_serial/CRC_16_serial.jpg) 23 | [CRC_32_parallel](CRC%20Coding/CRC_32_parallel) 24 | ![](CRC%20Coding/CRC_32_parallel/CRC_32_parallel.jpg) 25 | [CRC_32_serial](CRC%20Coding/CRC_32_serial) 26 | ![](CRC%20Coding/CRC_32_serial/CRC_32_serial.jpg) 27 | [BCD Adder](/bcd_adder) 28 | ![](bcd_adder/bcd_adder.jpg) 29 | [Dual Address ROM](/dual_address_rom) 30 | ![](dual_address_rom/dual_address_rom.jpg) 31 | [Dual Address RAM](/dual_address_ram) 32 | ![](dual_address_ram/dual_address_ram1.jpg) 33 | ![](dual_address_ram/dual_address_ram2.jpg) 34 | ![](dual_address_ram/dual_address_ram3.jpg) 35 | [Restoring and Non Restoring Division](/Restoring%20and%20Non%20Restoring%20Division) 36 | ![](Restoring%20and%20Non%20Restoring%20Division/Non%20Restoring%20Division%20Radix%202.jpg) 37 | ![](Restoring%20and%20Non%20Restoring%20Division/Restoring%20Division%20Radix%202.jpg) 38 | ![](Restoring%20and%20Non%20Restoring%20Division/Restoring%20Division%20Radix%204.jpg) 39 | [Universal Shift Register](/Universal_Shift_Register) 40 | ![](Universal_Shift_Register/Universal_shift_reg.jpg) 41 | [Barrel Shifter 8bit](/Barrel%20Shifter) 42 | ![](Barrel%20Shifter/barrel_shifter_8bit.jpg) 43 | [Booth Multiplier](/Booth%20Multiplication) 44 | ![](Booth%20Multiplication/booth_multiplication.jpg) 45 | [32 Bit Adder](32%20bit%20adder) 46 | ![](32%20bit%20adder/32%20bit%20adder.jpg) 47 | [Mealy State Machine for sequence detection](Mealy%20and%20Moore%20State%20Machine%20Implementation%20of%20Sequence%20Detector) 48 | ![](Mealy%20and%20Moore%20State%20Machine%20Implementation%20of%20Sequence%20Detector/mealy.jpg) 49 | [Moore State Machine for sequence detection](Mealy%20and%20Moore%20State%20Machine%20Implementation%20of%20Sequence%20Detector) 50 | ![](Mealy%20and%20Moore%20State%20Machine%20Implementation%20of%20Sequence%20Detector/moore.jpg) 51 | [Array Multiplier](Array%20Multiplier) 52 | ![](Array%20Multiplier/array_multiplier.jpg) 53 | [Carry Skip Adder](Carry%20Skip%20and%20Carry%20Save%20Adder) 54 | ![](Carry%20Skip%20and%20Carry%20Save%20Adder/carry_skip_adder.jpg) 55 | [Carry Select Adder](Carry%20Select%20and%20Carry%20Look%20Ahead%20Adder) 56 | ![](Carry%20Select%20and%20Carry%20Look%20Ahead%20Adder/carry_select_adder.jpg) 57 | [Carry Look Ahead Adder](Carry%20Select%20and%20Carry%20Look%20Ahead%20Adder) 58 | ![](Carry%20Select%20and%20Carry%20Look%20Ahead%20Adder/carry_look_ahead_adder.jpg) 59 | [Carry Save Adder](Carry%20Skip%20and%20Carry%20Save%20Adder) 60 | ![](Carry%20Skip%20and%20Carry%20Save%20Adder/carry_save_adder.jpg) 61 | [Complex Multiplier](Complex%20Multiplier) 62 | ![](Complex%20Multiplier/complex_multiplication.jpg) 63 | [Logarithm Implementation](Logarithm%20Implementation) 64 | ![](Logarithm%20Implementation/log.jpg) 65 | [Traffic_Light_Controller](Traffic%20Light%20Controller) 66 | ![](Traffic%20Light%20Controller/traffic_light.jpg) 67 | [Shift and Add Binary Multiplier](Shift%20and%20Add%20Binary%20Multiplier) 68 | ![](Shift%20and%20Add%20Binary%20Multiplier/shift%20and%20add%20multiplier.jpg) 69 | [Sequential Multiplier](Sequential%20Multiplier) 70 | ![](Sequential%20Multiplier/sequential_multiplication1.jpg) 71 | ![](Sequential%20Multiplier/sequential_multiplication2.jpg) 72 | [Fixed Point Adder](Fixed%20Point%20Adder%20and%20Subtractor) 73 | ![](Fixed%20Point%20Adder%20and%20Subtractor/fixed_point_adder1.jpg) 74 | ![](Fixed%20Point%20Adder%20and%20Subtractor/fixed_point_adder2.jpg) 75 | [Fixed Point Subtractor](Fixed%20Point%20Adder%20and%20Subtractor) 76 | ![](Fixed%20Point%20Adder%20and%20Subtractor/fixed_point_subtractor1.jpg) 77 | ![](Fixed%20Point%20Adder%20and%20Subtractor/fixed_point_subtractor2.jpg) 78 | [Fixed Point Multiplier](Fixed%20Point%20Multiplier%20and%20Divider) 79 | ![](Fixed%20Point%20Multiplier%20and%20Divider/fixed_point_multiplier1.jpg) 80 | ![](Fixed%20Point%20Multiplier%20and%20Divider/fixed_point_multiplier2.jpg) 81 | [Fixed Point Divider](Fixed%20Point%20Multiplier%20and%20Divider) 82 | ![](Fixed%20Point%20Multiplier%20and%20Divider/fixed_point_divider1.jpg) 83 | ![](Fixed%20Point%20Multiplier%20and%20Divider/fixed_point_divider2.jpg) 84 | [Fraction_Multiplier](Fraction%20Multiplier) 85 | ![](Fraction%20Multiplier/fraction_multiplication.jpg) 86 | [FIFO](FIFO) 87 | ![](FIFO/fifo.jpg) 88 | [LFSR and CFSR](LFSR%20and%20CFSR)
89 | [LFSR](LFSR%20and%20CFSR/LFSR) 90 | ![](LFSR%20and%20CFSR/LFSR/lfsr.jpg) 91 | [CFSR](LFSR%20and%20CFSR/CFSR) 92 | ![](LFSR%20and%20CFSR/CFSR/cfsr.jpg) 93 | [Modified Booth Multiplication](Modified%20Booth%20Algorithm) 94 | ![](Modified%20Booth%20Algorithm/modified_booth.jpg) 95 | [Pipelined Multiplier](Pipelined%20Multiplier) 96 | ![](Pipelined%20Multiplier/pipelined%20multiplier.jpg) 97 | [High Radix Multiplication](High%20Radix%20Multiplier) 98 | ![](High%20Radix%20Multiplier/multiplier.jpg) 99 | -------------------------------------------------------------------------------- /Restoring and Non Restoring Division/Non Restoring Division Radix 2.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Test134n/32-Verilog-Mini-Projects/f6458719db15c2b348ec63d70c5ab7572b771341/Restoring and Non Restoring Division/Non Restoring Division Radix 2.jpg -------------------------------------------------------------------------------- /Restoring and Non Restoring Division/Restoring Division Radix 2.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Test134n/32-Verilog-Mini-Projects/f6458719db15c2b348ec63d70c5ab7572b771341/Restoring and Non Restoring Division/Restoring Division Radix 2.jpg -------------------------------------------------------------------------------- /Restoring and Non Restoring Division/Restoring Division Radix 4.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Test134n/32-Verilog-Mini-Projects/f6458719db15c2b348ec63d70c5ab7572b771341/Restoring and Non Restoring Division/Restoring Division Radix 4.jpg -------------------------------------------------------------------------------- /Restoring and Non Restoring Division/non_restoring_div_R2.v: -------------------------------------------------------------------------------- 1 | module non_restoring_div(clk, reset, Dividend, Divisor, Quotient, Remainder); 2 | input clk, reset; 3 | input [63:0] Dividend, Divisor; 4 | output [63:0] Quotient, Remainder; 5 | reg [63:0] Quotient, Remainder; 6 | reg [63:0] p, a, temp; 7 | integer i; 8 | 9 | always @(posedge clk, negedge reset) 10 | begin 11 | if( !reset ) 12 | begin 13 | Quotient <= 0; 14 | Remainder <= 0; 15 | end 16 | else 17 | begin 18 | Quotient <= a; 19 | Remainder <= p; 20 | end 21 | end 22 | 23 | always @(*) 24 | begin 25 | a = Dividend; 26 | p = 0; 27 | 28 | for(i = 0; i < 64; i = i+1) 29 | begin 30 | //Shift Left carrying a's MSB into p's LSB 31 | p = (p << 1) | a[63]; 32 | a = a << 1; 33 | 34 | //Check the old value of p 35 | if( p[63] ) //if p is negative 36 | temp = Divisor; //add divisor 37 | else 38 | temp = ~Divisor+1; //subtract divisor 39 | 40 | //this will do the appropriate add or subtract 41 | //depending on the value of temp 42 | p = p + temp; 43 | 44 | //Check the new value of p 45 | if( p[63] ) // if p is negative 46 | a = a | 0; //no change to quotient 47 | else 48 | a = a | 1; 49 | end 50 | 51 | //Correction is needed if remainder is negative 52 | if( p[63] ) //if p is negative 53 | p = p + Divisor; 54 | end 55 | 56 | endmodule 57 | 58 | module non_restoring_div_tb; 59 | reg clk, reset; 60 | reg [63:0] dividend, divisor; 61 | wire [63:0] quotient, remainder; 62 | 63 | non_restoring_div divider(clk, reset, dividend, divisor, quotient, remainder); 64 | 65 | initial 66 | forever #1 clk = ~clk; 67 | 68 | initial 69 | $monitor("%0d / %0d: q = %0d, r = %0d", dividend, divisor, quotient, remainder); 70 | 71 | initial 72 | begin 73 | clk = 0; 74 | reset = 0; 75 | 76 | #1; 77 | reset = 1; 78 | dividend = 87; 79 | divisor = 5; 80 | 81 | #5; 82 | dividend = 59; 83 | divisor = 20; 84 | 85 | #5; 86 | dividend = 64'hFFFF_FFFF_FFFF_FFFF; 87 | divisor = 2; 88 | 89 | #5; 90 | dividend = 32'h1234_5678; 91 | divisor = 1; 92 | 93 | #5; 94 | divisor = dividend; 95 | 96 | #5; 97 | $finish; 98 | end 99 | 100 | endmodule 101 | -------------------------------------------------------------------------------- /Restoring and Non Restoring Division/restoring_div_R2.v: -------------------------------------------------------------------------------- 1 | module restoring_div_R2(clk, reset, Dividend, Divisor, Quotient, Remainder); 2 | input clk, reset; 3 | input [63:0] Dividend, Divisor; 4 | 5 | output [63:0] Quotient, Remainder; 6 | reg [63:0] Quotient, Remainder; 7 | 8 | reg [63:0] p, a, temp; 9 | integer i; 10 | 11 | always @(posedge clk, negedge reset) 12 | begin 13 | if( !reset ) 14 | begin 15 | Quotient <= 0; 16 | Remainder <= 0; 17 | end 18 | else 19 | begin 20 | Quotient <= a; 21 | Remainder <= p; 22 | end 23 | end 24 | 25 | always @(*) 26 | begin 27 | a = Dividend; 28 | p = 0; 29 | 30 | for(i = 0; i < 64; i = i+1) 31 | begin 32 | //Shift Left carrying a's MSB into p's LSB 33 | p = (p << 1) | a[63]; 34 | a = a << 1; 35 | 36 | //store value in case we have to restore 37 | temp = p; 38 | 39 | //Subtract 40 | p = p - Divisor; 41 | 42 | if( p[63] ) // if p < 0 43 | p = temp; //restore value 44 | else 45 | a = a | 1; 46 | end 47 | end 48 | 49 | endmodule 50 | 51 | module restoring_div_R2_tb; 52 | reg clk, reset; 53 | reg [63:0] dividend, divisor; 54 | wire [63:0] quotient, remainder; 55 | 56 | restoring_div_R2 divider(clk, reset, dividend, divisor, quotient, remainder); 57 | 58 | initial 59 | forever #1 clk = ~clk; 60 | 61 | initial 62 | $monitor("%0d / %0d: q = %0d, r = %0d", dividend, divisor, quotient, remainder); 63 | 64 | initial 65 | begin 66 | clk = 0; 67 | reset = 0; 68 | 69 | #1; 70 | reset = 1; 71 | dividend = 87; 72 | divisor = 5; 73 | 74 | #5; 75 | dividend = 59; 76 | divisor = 20; 77 | 78 | #5; 79 | dividend = 64'hFFFF_FFFF_FFFF_FFFF; 80 | divisor = 2; 81 | 82 | #5; 83 | dividend = 32'h1234_5678; 84 | divisor = 1; 85 | 86 | #5; 87 | divisor = dividend; 88 | 89 | #5; 90 | $finish; 91 | end 92 | 93 | endmodule 94 | -------------------------------------------------------------------------------- /Restoring and Non Restoring Division/restoring_div_R4.v: -------------------------------------------------------------------------------- 1 | module restoring_div_R4(clk, reset, Dividend, Divisor, Quotient, Remainder); 2 | input clk, reset; 3 | input [63:0] Dividend, Divisor; 4 | 5 | output [63:0] Quotient, Remainder; 6 | reg [63:0] Quotient, Remainder; 7 | reg [63:0] p, a; 8 | reg [63:0] Result1, Result2, Result3; 9 | reg [63:0] DivisorX2, DivisorX3; 10 | integer i; 11 | 12 | always @(posedge clk, negedge reset) 13 | begin 14 | if( !reset ) 15 | begin 16 | Quotient <= 0; 17 | Remainder <= 0; 18 | end 19 | else 20 | begin 21 | Quotient <= a; 22 | Remainder <= p; 23 | end 24 | end 25 | 26 | always @(*) 27 | begin 28 | a = Dividend; 29 | p = 0; 30 | DivisorX2 = Divisor << 1; //Divisor*2 31 | DivisorX3 = (Divisor << 1) + Divisor; //Divisor*3 32 | 33 | for(i = 0; i < 32; i = i+1) 34 | begin 35 | //Shift Left carrying a's MSB into p's LSB 36 | p = (p << 2) | a[63:62]; 37 | a = a << 2; 38 | 39 | //Subtract 40 | Result1 = p - Divisor; 41 | Result2 = p - DivisorX2; 42 | Result3 = p - DivisorX3; 43 | 44 | if( Result1[63] ) //Divisor is too big 45 | begin 46 | a = a | 0; 47 | end 48 | else if( Result2[63] )//Divisor*2 is too big, but Divisor*1 is OK 49 | begin 50 | p = Result1; 51 | a = a | 1; 52 | end 53 | else if( Result3[63] ) //Divisor*3 is too big, but Divisor*2 is OK 54 | begin 55 | p = Result2; 56 | a = a | 2; 57 | end 58 | else 59 | begin //Divisor*3 is OK 60 | p = Result3; 61 | a = a | 3; 62 | end 63 | end 64 | end 65 | 66 | endmodule 67 | 68 | module restoring_div_R4_tb; 69 | reg clk, reset; 70 | reg [63:0] dividend, divisor; 71 | wire [63:0] quotient, remainder; 72 | 73 | restoring_div_R4 divider(clk, reset, dividend, divisor, quotient, remainder); 74 | 75 | initial 76 | forever #1 clk = ~clk; 77 | 78 | initial 79 | $monitor("%0d / %0d: q = %0d, r = %0d", dividend, divisor, quotient, remainder); 80 | 81 | initial 82 | begin 83 | clk = 0; 84 | reset = 0; 85 | 86 | #1; 87 | reset = 1; 88 | dividend = 87; 89 | divisor = 5; 90 | 91 | #5; 92 | dividend = 59; 93 | divisor = 20; 94 | 95 | #5; 96 | dividend = 64'hFFFF_FFFF_FFFF_FFFF; 97 | divisor = 2; 98 | 99 | #5; 100 | dividend = 32'h1234_5678; 101 | divisor = 1; 102 | 103 | #5; 104 | divisor = dividend; 105 | 106 | #5; 107 | $finish; 108 | end 109 | 110 | endmodule 111 | -------------------------------------------------------------------------------- /Sequential Multiplier/SR1.v: -------------------------------------------------------------------------------- 1 | //SR 2 | 3 | module s2(rst,l_s,clk,q1,d); 4 | 5 | input l_s,clk,rst; 6 | input [7:0] d; 7 | output reg [7:0] q1; 8 | 9 | always @(posedge clk) 10 | begin 11 | if(rst) 12 | q1=0; 13 | else if(l_s) 14 | q1=d; 15 | else 16 | q1=q1>>1; 17 | end 18 | endmodule 19 | -------------------------------------------------------------------------------- /Sequential Multiplier/SR2.v: -------------------------------------------------------------------------------- 1 | //SR 2 | 3 | module s3(clk,rst,d,l,q2); 4 | 5 | input clk,rst,l; 6 | input [7:0] d; 7 | output reg [7:0] q2; 8 | 9 | always @(posedge clk) 10 | begin 11 | if(rst) 12 | q2=0; 13 | else if(l) 14 | q2=q2; 15 | else 16 | q2=d; 17 | end 18 | endmodule 19 | -------------------------------------------------------------------------------- /Sequential Multiplier/adder.v: -------------------------------------------------------------------------------- 1 | //Adder 2 | 3 | module adder(a,b,c,s); 4 | input [7:0] a,b; 5 | output [7:0] s; 6 | output c; 7 | assign {c,s}=a+b; 8 | endmodule 9 | -------------------------------------------------------------------------------- /Sequential Multiplier/counter.v: -------------------------------------------------------------------------------- 1 | //Counter 2 | 3 | module counter(reset,l,clk); 4 | 5 | input reset,clk; 6 | output reg l; 7 | integer i; 8 | 9 | always @(posedge clk) 10 | begin 11 | if(reset) 12 | begin 13 | i=0; 14 | l=0; 15 | end 16 | else 17 | begin 18 | if(i==7) 19 | l=1; 20 | else 21 | begin 22 | i=i+1; 23 | l=0; 24 | end 25 | end 26 | end 27 | endmodule 28 | -------------------------------------------------------------------------------- /Sequential Multiplier/pipo.v: -------------------------------------------------------------------------------- 1 | //PIPO 2 | module s1(rst,d,clk,q,l); 3 | 4 | input clk,l,rst; 5 | input [7:0] d; 6 | output reg [7:0] q; 7 | 8 | always @(posedge clk) 9 | begin 10 | if(rst) 11 | q=0; 12 | else if(l) 13 | q=d; 14 | end 15 | endmodule 16 | -------------------------------------------------------------------------------- /Sequential Multiplier/prod1.v: -------------------------------------------------------------------------------- 1 | //Prod1 2 | module s4(clk,rst,d,l,q3); 3 | 4 | input clk,rst,l,d; 5 | output reg [7:0] q3; 6 | 7 | always @(negedge clk) 8 | begin 9 | if(rst) 10 | q3<=7'd0; 11 | else if(l) 12 | q3<=q3; 13 | else 14 | begin 15 | q3[0]<=q3[1]; 16 | q3[1]<=q3[2]; 17 | q3[2]<=q3[3]; 18 | q3[3]<=q3[4]; 19 | q3[4]<=q3[5]; 20 | q3[5]<=q3[6]; 21 | q3[6]<=q3[7]; 22 | q3[7]<=d; 23 | end 24 | end 25 | endmodule 26 | -------------------------------------------------------------------------------- /Sequential Multiplier/sequential_multiplication.v: -------------------------------------------------------------------------------- 1 | 2 | module final12 (a,b,op,load,reset,clk,valid); 3 | input [7:0] a,b; 4 | output [15:0] op; 5 | output valid; 6 | input clk,reset,load; 7 | wire [7:0] x,y,z,s,po,lo; 8 | wire c,v1,l,t; 9 | 10 | s1 u1 (reset,a,clk,x,load); 11 | s2 u2 (reset,load,clk,z,b); 12 | assign y=x & {8{z[0]}}; 13 | counter u5 (t,l,clk); 14 | assign valid=l; 15 | adder u3 (y,po,c,s); 16 | s3 u4 (clk,v1,{c,s[7:1]},l,po); 17 | s4 e1 (clk,v1,s[0],l,lo); 18 | assign op={po,lo}; 19 | assign v1= reset|load; 20 | assign t=reset|load; 21 | 22 | always @(l) 23 | begin 24 | if(op==a*b) 25 | $display("the product of a=%d ,b=%d is p=%d",a,b,op); 26 | else 27 | $display("Incorrect operation"); 28 | end 29 | endmodule 30 | -------------------------------------------------------------------------------- /Sequential Multiplier/sequential_multiplication1.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Test134n/32-Verilog-Mini-Projects/f6458719db15c2b348ec63d70c5ab7572b771341/Sequential Multiplier/sequential_multiplication1.jpg -------------------------------------------------------------------------------- /Sequential Multiplier/sequential_multiplication2.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Test134n/32-Verilog-Mini-Projects/f6458719db15c2b348ec63d70c5ab7572b771341/Sequential Multiplier/sequential_multiplication2.jpg -------------------------------------------------------------------------------- /Sequential Multiplier/sequential_multiplication_tb.v: -------------------------------------------------------------------------------- 1 | module test; 2 | 3 | reg [7:0] a,b; 4 | wire [15:0] p; 5 | reg clk,rst,load; 6 | wire valid; 7 | final12 x1 (a,b,p,load,rst,clk,valid); 8 | 9 | initial 10 | begin 11 | clk=1; 12 | forever #5 clk=~clk; 13 | end 14 | 15 | initial 16 | begin 17 | rst=1; 18 | #20; 19 | 20 | rst=0; 21 | load=1; 22 | a=255; 23 | b=255; 24 | #10 25 | load=0; 26 | #100 27 | 28 | rst=1; 29 | #20 30 | 31 | rst=0; 32 | load=1; 33 | a=128; 34 | b=128; 35 | #10 36 | load=0; 37 | #100 38 | 39 | load=1; 40 | a=128; 41 | b=0; 42 | #10 43 | load=0; 44 | #100 45 | 46 | load=1; 47 | a=128; 48 | b=1; 49 | #10 50 | load=0; 51 | #100 52 | 53 | load=1; 54 | a=25; 55 | b=5; 56 | #10 57 | load=0; 58 | #100 59 | 60 | load=1; 61 | a=64; 62 | b=64; 63 | #10 64 | load=0; 65 | #100 66 | 67 | load=1; 68 | a=36; 69 | b=36; 70 | #10 71 | load=0; 72 | #100 73 | 74 | load=1; 75 | a=11; 76 | b=33; 77 | #10 78 | load=0; 79 | #100 80 | 81 | load=1; 82 | a=80; 83 | b=10; 84 | #10 85 | load=0; 86 | #100; 87 | end 88 | endmodule 89 | -------------------------------------------------------------------------------- /Shift and Add Binary Multiplier/shift and add multiplier.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Test134n/32-Verilog-Mini-Projects/f6458719db15c2b348ec63d70c5ab7572b771341/Shift and Add Binary Multiplier/shift and add multiplier.jpg -------------------------------------------------------------------------------- /Shift and Add Binary Multiplier/shift and add.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Test134n/32-Verilog-Mini-Projects/f6458719db15c2b348ec63d70c5ab7572b771341/Shift and Add Binary Multiplier/shift and add.png -------------------------------------------------------------------------------- /Shift and Add Binary Multiplier/shift_add_multiplication.v: -------------------------------------------------------------------------------- 1 | module adder( 2 | D,A,add_out,c_out 3 | ); 4 | parameter m=8,n=8; 5 | input [m-1:0] D,A; 6 | output [m-1:0] add_out; 7 | output c_out; 8 | wire [m:0] add_result, data1, data2; 9 | assign data1 = {1'b0,D}; 10 | assign data2 = {1'b0,A}; 11 | assign add_result = data1+data2; 12 | assign add_out = add_result[m-1:0]; 13 | assign c_out = add_result[m]; 14 | endmodule 15 | 16 | module controller(clk,rst,lsb,load_cmd,add_cmd,shift_cmd,out_cmd); 17 | input clk, rst,lsb; 18 | output load_cmd,add_cmd,shift_cmd,out_cmd; 19 | reg load_cmd,add_cmd,shift_cmd, out_cmd; 20 | reg [2:0] state; 21 | reg start; 22 | integer count; 23 | parameter m=8; 24 | parameter n=8; 25 | parameter idle=3'b000, init=3'b001, test=3'b010, add=3'b011, shift=3'b100; 26 | always@(posedge clk or posedge rst) 27 | if (rst) 28 | begin 29 | state<=idle; 30 | count<=0; 31 | start<=1; 32 | out_cmd<=0; 33 | end 34 | else 35 | case (state) 36 | idle: begin 37 | load_cmd<=0; 38 | add_cmd<=0; 39 | shift_cmd<=0; 40 | if (start) begin 41 | state<=init; 42 | out_cmd<=0; 43 | end 44 | else begin 45 | state<=idle; 46 | out_cmd<=1; 47 | end 48 | end 49 | init: begin 50 | load_cmd<=1; 51 | add_cmd<=0; 52 | shift_cmd<=0; 53 | out_cmd<=0; 54 | state<=test; 55 | end 56 | test: begin 57 | load_cmd<=0; 58 | add_cmd<=0; 59 | shift_cmd<=0; 60 | out_cmd<=0; 61 | if (lsb) begin 62 | state<=add; 63 | end 64 | else state<=shift; 65 | end 66 | add: begin 67 | load_cmd<=0; 68 | add_cmd<=1; 69 | shift_cmd<=0; 70 | out_cmd<=0; 71 | state<=shift; 72 | end 73 | shift: begin 74 | load_cmd<=0; 75 | add_cmd<=0; 76 | shift_cmd<=1; 77 | out_cmd<=0; 78 | if (count 9) 14 | begin 15 | temp = temp+6; //add 6, if result is more than 9. 16 | cout = 1; //set the carry output 17 | sum = temp[3:0]; 18 | end 19 | else 20 | begin 21 | cout = 0; 22 | sum = temp[3:0]; 23 | end 24 | end 25 | 26 | endmodule 27 | 28 | 29 | module tb_bcdadder; 30 | 31 | reg [3:0] a; 32 | reg [3:0] b; 33 | reg cin; 34 | 35 | wire [3:0] sum; 36 | wire cout; 37 | 38 | bcd_adder uut ( 39 | .a(a), 40 | .b(b), 41 | .cin(cin), 42 | .sum(sum), 43 | .cout(cout) 44 | ); 45 | 46 | initial begin 47 | a = 0; b = 0; cin = 0; #100; 48 | a = 6; b = 9; cin = 0; #100; 49 | a = 3; b = 3; cin = 1; #100; 50 | a = 4; b = 5; cin = 0; #100; 51 | a = 8; b = 2; cin = 0; #100; 52 | a = 9; b = 9; cin = 1; #100; 53 | end 54 | 55 | endmodule 56 | -------------------------------------------------------------------------------- /dual_address_ram/dual_address_ram.v: -------------------------------------------------------------------------------- 1 | module dual_port_ram 2 | ( input clk, //clock 3 | input wr_en, //write enable for port 0 4 | input [7:0] data_in, //Input data to port 0. 5 | input [3:0] addr_in_0, //address for port 0 6 | input [3:0] addr_in_1, //address for port 1 7 | input port_en_0, //enable port 0. 8 | input port_en_1, //enable port 1. 9 | output [7:0] data_out_0, //output data from port 0. 10 | output [7:0] data_out_1 //output data from port 1. 11 | ); 12 | 13 | //memory declaration. 14 | reg [7:0] ram[0:15]; 15 | 16 | //writing to the RAM 17 | always@(posedge clk) 18 | begin 19 | if(port_en_0 == 1 && wr_en == 1) // check enable signal and if write enable is ON 20 | ram[addr_in_0] <= data_in; 21 | end 22 | 23 | //always reading from the ram, irrespective of clock. 24 | assign data_out_0 = port_en_0 ? ram[addr_in_0] : 'dZ; 25 | assign data_out_1 = port_en_1 ? ram[addr_in_1] : 'dZ; 26 | 27 | endmodule 28 | 29 | 30 | module dual_port_ram_tb; 31 | 32 | // Inputs 33 | reg clk; 34 | reg wr_en; 35 | reg [7:0] data_in; 36 | reg [3:0] addr_in_0; 37 | reg [3:0] addr_in_1; 38 | reg port_en_0; 39 | reg port_en_1; 40 | 41 | // Outputs 42 | wire [7:0] data_out_0; 43 | wire [7:0] data_out_1; 44 | 45 | integer i; 46 | 47 | // Instantiate the Unit Under Test (UUT) 48 | dual_port_ram uut ( 49 | .clk(clk), 50 | .wr_en(wr_en), 51 | .data_in(data_in), 52 | .addr_in_0(addr_in_0), 53 | .addr_in_1(addr_in_1), 54 | .port_en_0(port_en_0), 55 | .port_en_1(port_en_1), 56 | .data_out_0(data_out_0), 57 | .data_out_1(data_out_1) 58 | ); 59 | 60 | always 61 | #5 clk = ~clk; 62 | 63 | initial begin 64 | // Initialize Inputs 65 | clk = 1; 66 | addr_in_1 = 0; 67 | port_en_0 = 0; 68 | port_en_1 = 0; 69 | wr_en = 0; 70 | data_in = 0; 71 | addr_in_0 = 0; 72 | #20; 73 | //Write all the locations of RAM 74 | port_en_0 = 1; 75 | wr_en = 1; 76 | for(i=1; i <= 16; i = i + 1) begin 77 | data_in = i; 78 | addr_in_0 = i-1; 79 | #10; 80 | end 81 | wr_en = 0; 82 | port_en_0 = 0; 83 | //Read from port 1, all the locations of RAM. 84 | port_en_1 = 1; 85 | for(i=1; i <= 16; i = i + 1) begin 86 | addr_in_1 = i-1; 87 | #10; 88 | end 89 | port_en_1 = 0; 90 | end 91 | 92 | endmodule 93 | -------------------------------------------------------------------------------- /dual_address_ram/dual_address_ram0.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Test134n/32-Verilog-Mini-Projects/f6458719db15c2b348ec63d70c5ab7572b771341/dual_address_ram/dual_address_ram0.jpg -------------------------------------------------------------------------------- /dual_address_ram/dual_address_ram1.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Test134n/32-Verilog-Mini-Projects/f6458719db15c2b348ec63d70c5ab7572b771341/dual_address_ram/dual_address_ram1.jpg -------------------------------------------------------------------------------- /dual_address_ram/dual_address_ram2.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Test134n/32-Verilog-Mini-Projects/f6458719db15c2b348ec63d70c5ab7572b771341/dual_address_ram/dual_address_ram2.jpg -------------------------------------------------------------------------------- /dual_address_ram/dual_address_ram3.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Test134n/32-Verilog-Mini-Projects/f6458719db15c2b348ec63d70c5ab7572b771341/dual_address_ram/dual_address_ram3.jpg -------------------------------------------------------------------------------- /dual_address_rom/dual_address_rom.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Test134n/32-Verilog-Mini-Projects/f6458719db15c2b348ec63d70c5ab7572b771341/dual_address_rom/dual_address_rom.jpg -------------------------------------------------------------------------------- /dual_address_rom/dual_address_rom.v: -------------------------------------------------------------------------------- 1 | module dual_port_rom 2 | (input clk, 3 | input wr_en, 4 | input [3:0] addr_in_0, 5 | input [3:0] addr_in_1, 6 | input port_en_0, 7 | input port_en_1, 8 | output [7:0] data_out_0, 9 | output [7:0] data_out_1); 10 | 11 | reg [4:0] raddr; 12 | reg[7:0] rom [7:0]; 13 | 14 | always @(posedge clk) 15 | begin 16 | if (port_en_0 == 1 && wr_en == 1) 17 | raddr <= addr_in_0; 18 | end 19 | 20 | always @(raddr) 21 | begin 22 | if (port_en_0 == 1 && wr_en == 1) 23 | case(raddr) 24 | 4'b0000: rom[raddr] = 8'b00100100; 25 | 4'b0001: rom[raddr] = 8'b00100011; 26 | 4'b0010: rom[raddr] = 8'b11100010; 27 | 4'b0011: rom[raddr] = 8'b00100001; 28 | 4'b0100: rom[raddr] = 8'b01000101; 29 | 4'b0101: rom[raddr] = 8'b10101110; 30 | 4'b0110: rom[raddr] = 8'b11001011; 31 | 4'b0111: rom[raddr] = 8'b00000000; 32 | 4'b1000: rom[raddr] = 8'b10100011; 33 | 4'b1001: rom[raddr] = 8'b00101010; 34 | 4'b1010: rom[raddr] = 8'b11101100; 35 | 4'b1011: rom[raddr] = 8'b00100010; 36 | 4'b1100: rom[raddr] = 8'b01000000; 37 | 4'b1101: rom[raddr] = 8'b10100000; 38 | 4'b1110: rom[raddr] = 8'b00001100; 39 | 4'b1111: rom[raddr] = 8'b00000000; 40 | default: rom[raddr] = 8'bXXXXXXXX; 41 | endcase 42 | end 43 | assign data_out_0 = port_en_0 ? rom[addr_in_0] : 'dZ; 44 | assign data_out_1 = port_en_1 ? rom[addr_in_1] : 'dZ; 45 | endmodule 46 | 47 | module dual_port_rom_tb; 48 | 49 | // Inputs 50 | reg clk; 51 | reg wr_en; 52 | reg [3:0] addr_in_0; 53 | reg [3:0] addr_in_1; 54 | reg port_en_0; 55 | reg port_en_1; 56 | 57 | // Outputs 58 | wire [7:0] data_out_0; 59 | wire [7:0] data_out_1; 60 | 61 | integer i; 62 | 63 | // Instantiate the Unit Under Test (UUT) 64 | dual_port_rom uut ( 65 | .clk(clk), 66 | .wr_en(wr_en), 67 | .addr_in_0(addr_in_0), 68 | .addr_in_1(addr_in_1), 69 | .port_en_0(port_en_0), 70 | .port_en_1(port_en_1), 71 | .data_out_0(data_out_0), 72 | .data_out_1(data_out_1) 73 | ); 74 | 75 | always 76 | #5 clk = ~clk; 77 | 78 | initial begin 79 | // Initialize Inputs 80 | clk = 1; 81 | addr_in_1 = 0; 82 | port_en_0 = 0; 83 | port_en_1 = 0; 84 | wr_en = 0; 85 | addr_in_0 = 0; 86 | #20 87 | port_en_0 = 1; 88 | wr_en = 1; 89 | for(i=1; i <= 16; i = i + 1) begin 90 | addr_in_0 = i-1; 91 | #10; 92 | end 93 | wr_en = 0; 94 | port_en_0 = 0; 95 | //Read from port 1, all the locations of ROM. 96 | port_en_1 = 1; 97 | for(i=1; i <= 16; i = i + 1) begin 98 | addr_in_1 = i-1; 99 | #10; 100 | end 101 | port_en_1 = 0; 102 | end 103 | 104 | endmodule 105 | --------------------------------------------------------------------------------