├── .gitmodules ├── LICENSE ├── README.md ├── RISC-V-demonstrator--docs.pdf ├── chisel.sh ├── git.sh ├── thales-risc-v-controller ├── Makefile ├── risc-v-ctrl.c └── risc-v-ft.h ├── thales-risc-v-recovery-app ├── Makefile ├── bootzephyr.h ├── linker.ld ├── recovery.S ├── recovery.rv32.elf ├── recovery.rv32.img └── recovery.rv64.img ├── thales-risc-v-vivado └── git │ ├── .gitignore │ ├── ip_repo │ ├── bus_monitor_1.0 │ │ ├── bd │ │ │ └── bd.tcl │ │ ├── component.xml │ │ ├── hdl │ │ │ ├── bus_monitor_v1_0.v │ │ │ └── bus_monitor_v1_0_S00_AXI.v │ │ └── xgui │ │ │ └── bus_monitor_v1_0.tcl │ ├── clk_control_1.0 │ │ ├── bd │ │ │ └── bd.tcl │ │ ├── component.xml │ │ ├── hdl │ │ │ ├── clk_control_v1_0.v │ │ │ └── clk_control_v1_0_S00_AXI.v │ │ ├── src │ │ │ └── clk_control.v │ │ └── xgui │ │ │ └── clk_control_v1_0.tcl │ ├── fault_detector_1.0 │ │ ├── bd │ │ │ └── bd.tcl │ │ ├── component.xml │ │ ├── src │ │ │ ├── FaultDetector.v │ │ │ └── fault_detector_v1_0.v │ │ └── xgui │ │ │ └── fault_detector_v1_0.tcl │ ├── interfaces │ │ ├── GPR.xml │ │ ├── GPR_rtl.xml │ │ ├── MStatus.xml │ │ └── MStatus_rtl.xml │ ├── jtag_simplelink_1.0 │ │ ├── bd │ │ │ └── bd.tcl │ │ ├── component.xml │ │ ├── hdl │ │ │ ├── jtag_simplelink_v1_0.vhd │ │ │ └── jtag_simplelink_v1_0_S00_AXI.vhd │ │ └── xgui │ │ │ └── jtag_simplelink_v1_0.tcl │ ├── regs_router_1.0 │ │ ├── component.xml │ │ ├── src │ │ │ └── RegsRouter.v │ │ └── xgui │ │ │ ├── Regs_Router_v1_0.tcl │ │ │ └── clk_control_v1_0.tcl │ ├── risc_v_CPU_1.0 │ │ ├── bd │ │ │ └── bd.tcl │ │ ├── component.xml │ │ ├── hdl │ │ │ ├── risc_v_CPU_v1_0.v │ │ │ └── risc_v_CPU_v1_0_M00_AXI.v │ │ ├── src │ │ │ ├── AsyncResetReg.v │ │ │ ├── ClockDivider2.v │ │ │ ├── ClockDivider3.v │ │ │ ├── SimDTM.v │ │ │ ├── TestDriver.v │ │ │ ├── antmicro_ft.FPGATop.AntmicroConfig.v │ │ │ ├── jtag_vpi.v │ │ │ └── plusarg_reader.v │ │ └── xgui │ │ │ └── risc_v_CPU_v1_0.tcl │ └── riscv_regs_reader_1.0 │ │ ├── bd │ │ └── bd.tcl │ │ ├── component.xml │ │ ├── hdl │ │ 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