├── .bazelversion ├── print_python_version.py ├── docker ├── bazelrc └── Dockerfile.dev ├── .bazelrc ├── io-boomtile.tcl ├── io-top.tcl ├── io.tcl ├── pytest.ini ├── io-sram.tcl ├── .gitignore ├── WORKSPACE.bazel ├── io-sram-bottom.tcl ├── report-kpi.tcl ├── rtl ├── GenericDigitalInIOCell.v ├── GenericDigitalOutIOCell.v ├── firrtl_black_box_resource_files.f ├── ClockSourceAtFreqMHz.v ├── EICG_wrapper.v ├── SimJTAG.cc ├── plusarg_reader.v ├── testchip_htif.h ├── Arbiter_8.sv ├── OptimizationBarrier_92.sv ├── BundleBridgeNexus_16.sv ├── IntSyncCrossingSource_4.sv ├── IntSyncSyncCrossingSink.sv ├── IntSyncAsyncCrossingSink.sv ├── SynchronizerShiftReg_w1_d3.sv ├── AsyncValidSync.sv ├── ClockCrossingReg_w4.sv ├── ClockCrossingReg_w15.sv ├── ClockCrossingReg_w43.sv ├── ClockCrossingReg_w55.sv ├── ResetSynchronizerShiftReg_w1_d3_i0.sv ├── AsyncResetSynchronizerShiftReg_w1_d3_i0.sv ├── AsyncResetSynchronizerShiftReg_w1_d3_i0_1.sv ├── IntXbar_1.sv ├── testchip_tsi.h ├── NonSyncResetSynchronizerPrimitiveShiftReg_d3.sv ├── extern_modules.sv ├── ResetCatchAndSync_d3.sv ├── FixedClockBroadcast.sv ├── FixedClockBroadcast_6.sv ├── Arbiter_19.sv ├── IntSyncCrossingSource_5.sv ├── ram_2x56.sv ├── ram_2x78.sv ├── ram_2x81.sv ├── ram_2x82.sv ├── ram_2x88.sv ├── ram_3x79.sv ├── ram_4x65.sv ├── ram_5x79.sv ├── ram_7x79.sv ├── ram_8x72.sv ├── ram_sink_2x2.sv ├── ram_16x46.sv ├── sdq_17x64.sv ├── ram_2x101.sv ├── ram_2x103.sv ├── ram_2x109.sv ├── ram_2x113.sv ├── ram_2x117.sv ├── ram_2x120.sv ├── ram_2x121.sv ├── ram_2x127.sv ├── ram_2x128.sv ├── ram_2x412.sv ├── lb_32x128.sv ├── RecFNToRecFN_1.sv ├── Arbiter_14.sv ├── ClockGroupResetSynchronizer.sv ├── RoundAnyRawFNToRecFN_5.sv ├── ghist_40x72.sv ├── ebtb_128x40.sv ├── dataArrayB_256x64.sv ├── meta_40x240.sv ├── l2_tlb_ram_0_512x46.sv ├── Repeater_7.sv ├── remote_bitbang.h ├── AsyncResetRegVec_w1_i1.sv ├── AsyncResetRegVec_w2_i0.sv ├── testchip_htif.cc ├── OptimizationBarrier.sv ├── OptimizationBarrier_93.sv ├── RoundRawFNToRecFN.sv ├── RecFNToRecFN.sv ├── RoundRawFNToRecFN_1.sv ├── array_256x128.sv ├── FixedClockBroadcast_3.sv ├── BroadcastFilter.sv ├── RoundRawFNToRecFN_2.sv ├── UOPCodeFDivDecoder.sv ├── Mul54.sv ├── mem_128x4.sv ├── mem_256x4.sv ├── testchip_tsi.cc ├── JtagBypassChain.sv ├── FMADecoder.sv ├── data_2048x8.sv ├── btb_128x56.sv ├── table_128x44.sv ├── table_128x52.sv ├── table_256x48.sv ├── AsyncResetSynchronizerPrimitiveShiftReg_d3_i0.sv ├── RoundAnyRawFNToRecFN.sv ├── MaxPeriodFibonacciLFSR_2.sv ├── meta_128x120.sv ├── Arbiter_11.sv ├── RoundAnyRawFNToRecFN_1.sv ├── Arbiter_20.sv ├── AMOALU.sv ├── OptimizationBarrier_14.sv ├── SimTSI.cc ├── SimTSI.v ├── AsyncResetSynchronizerShiftReg_w4_d3_i0.sv ├── HellaCacheArbiter.sv ├── Queue_27.sv ├── CompareRecFN.sv ├── NLPrefetcher.sv ├── Arbiter_9.sv ├── Arbiter_13.sv ├── Queue_10.sv ├── tag_array_64x184.sv ├── DMIToTL.sv ├── Queue_28.sv ├── mem_268435456x64.sv ├── CaptureUpdateChain_2.sv ├── tag_array_64x168.sv └── RecFNToIN_1.sv ├── update.sh ├── write_macros.tcl ├── report-floorplan.tcl ├── write_binary.bzl ├── report-sram.tcl ├── etc ├── BuildMegaboom.sh └── DockerTag.sh ├── write_kept.tcl ├── .github └── workflows │ └── ci.yml ├── constraints-boomtile.sdc ├── mock ├── array_256x64.sv ├── dataArrayB_256x64.sv ├── l2_tlb_ram_0_512x45.sv ├── cc_dir_1024x16.sv ├── cc_banks_8192x64.sv ├── data_data_40x128.sv ├── ebtb_128x40.sv ├── ghist_40x64.sv ├── data_2048x2.sv ├── l2_tlb_ram_0_512x46.sv ├── ghist_40x72.sv ├── cc_banks_16384x64.sv ├── data_2048x8.sv └── array_256x128.sv ├── slack-positions.tcl ├── constraints.sdc ├── LICENSE ├── pdn.tcl ├── util.tcl ├── jenkins └── public_build.Jenkinsfile └── sram.py /.bazelversion: -------------------------------------------------------------------------------- 1 | 8.3.1 2 | -------------------------------------------------------------------------------- /print_python_version.py: -------------------------------------------------------------------------------- 1 | import sys 2 | print(sys.version) 3 | 4 | -------------------------------------------------------------------------------- /docker/bazelrc: -------------------------------------------------------------------------------- 1 | startup --output_user_root=/home/boomer/bazel-cache 2 | -------------------------------------------------------------------------------- /.bazelrc: -------------------------------------------------------------------------------- 1 | build --incompatible_strict_action_env 2 | try-import %workspace%/user.bazelrc 3 | -------------------------------------------------------------------------------- /io-boomtile.tcl: -------------------------------------------------------------------------------- 1 | source util.tcl 2 | 3 | set_io_pin_constraint -region bottom:* -pin_names [match_pins .*] 4 | -------------------------------------------------------------------------------- /io-top.tcl: -------------------------------------------------------------------------------- 1 | source util.tcl 2 | 3 | set_io_pin_constraint -region top:* -pin_names [match_pins (io|auto)_.*] 4 | -------------------------------------------------------------------------------- /io.tcl: -------------------------------------------------------------------------------- 1 | source util.tcl 2 | 3 | set_io_pin_constraint -region left:* -pin_names [match_pins (io|auto)_.*] 4 | -------------------------------------------------------------------------------- /pytest.ini: -------------------------------------------------------------------------------- 1 | [pytest] 2 | norecursedirs = bazel-bin/ bazel-megaboom/ bazel-out/ bazel-testlogs/ build/ 3 | 4 | -------------------------------------------------------------------------------- /io-sram.tcl: -------------------------------------------------------------------------------- 1 | source util.tcl 2 | 3 | set_io_pin_constraint -region left:* -pin_names [match_pins {(R|W)[0-9]+_.*}] 4 | -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | bazel-bin 2 | bazel-megaboom 3 | bazel-megaboom2 4 | bazel-out 5 | bazel-testlogs 6 | .vscode/ 7 | user.bazelrc 8 | -------------------------------------------------------------------------------- /WORKSPACE.bazel: -------------------------------------------------------------------------------- 1 | # This file marks the root of the Bazel workspace. 2 | # See MODULE.bazel for external dependencies setup. 3 | -------------------------------------------------------------------------------- /io-sram-bottom.tcl: -------------------------------------------------------------------------------- 1 | source util.tcl 2 | 3 | set_io_pin_constraint -region bottom:* -pin_names [match_pins {(R|W)[0-9]+_.*}] 4 | -------------------------------------------------------------------------------- /report-kpi.tcl: -------------------------------------------------------------------------------- 1 | source $::env(SCRIPTS_DIR)/load.tcl 2 | load_design 4_cts.odb 4_cts.sdc 3 | 4 | set fp [open $::env(OUTPUT) w] 5 | puts $fp "some: value" 6 | close $fp 7 | -------------------------------------------------------------------------------- /rtl/GenericDigitalInIOCell.v: -------------------------------------------------------------------------------- 1 | 2 | `timescale 1ns/1ps 3 | module GenericDigitalInIOCell( 4 | input pad, 5 | output i, 6 | input ie 7 | ); 8 | 9 | assign i = ie ? pad : 1'b0; 10 | 11 | endmodule 12 | -------------------------------------------------------------------------------- /rtl/GenericDigitalOutIOCell.v: -------------------------------------------------------------------------------- 1 | 2 | `timescale 1ns/1ps 3 | module GenericDigitalOutIOCell( 4 | output pad, 5 | input o, 6 | input oe 7 | ); 8 | 9 | assign pad = oe ? o : 1'bz; 10 | 11 | endmodule 12 | -------------------------------------------------------------------------------- /update.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | # store in separate folder to avoid conflict 3 | # with label of generated file 4 | mkdir -p $BUILD_WORKSPACE_DIRECTORY/snapshots 5 | cp --no-preserve=all $@ $BUILD_WORKSPACE_DIRECTORY/snapshots/ 6 | -------------------------------------------------------------------------------- /rtl/firrtl_black_box_resource_files.f: -------------------------------------------------------------------------------- 1 | ClockSourceAtFreqMHz.v 2 | EICG_wrapper.v 3 | GenericDigitalInIOCell.v 4 | GenericDigitalOutIOCell.v 5 | SimJTAG.cc 6 | SimJTAG.v 7 | SimTSI.cc 8 | SimTSI.v 9 | plusarg_reader.v 10 | remote_bitbang.cc 11 | testchip_htif.cc 12 | testchip_tsi.cc 13 | -------------------------------------------------------------------------------- /rtl/ClockSourceAtFreqMHz.v: -------------------------------------------------------------------------------- 1 | 2 | module ClockSourceAtFreqMHz #(parameter PERIOD="") ( 3 | input power, 4 | input gate, 5 | output clk); 6 | timeunit 1ns/1ps; 7 | reg clk_i = 1'b0; 8 | always #(PERIOD/2.0) clk_i = ~clk_i & (power & ~gate); 9 | assign clk = clk_i; 10 | endmodule 11 | -------------------------------------------------------------------------------- /rtl/EICG_wrapper.v: -------------------------------------------------------------------------------- 1 | /* verilator lint_off UNOPTFLAT */ 2 | 3 | module EICG_wrapper( 4 | output out, 5 | input en, 6 | input test_en, 7 | input in 8 | ); 9 | 10 | reg en_latched /*verilator clock_enable*/; 11 | 12 | always @(*) begin 13 | if (!in) begin 14 | en_latched = en || test_en; 15 | end 16 | end 17 | 18 | assign out = en_latched && in; 19 | 20 | endmodule 21 | -------------------------------------------------------------------------------- /write_macros.tcl: -------------------------------------------------------------------------------- 1 | source $::env(SCRIPTS_DIR)/load.tcl 2 | 3 | set filename [file join $::env(WORK_HOME) "macro_placement.tcl"] 4 | puts "Macro placement written to $filename" 5 | 6 | load_design 2_floorplan.odb 2_floorplan.sdc 7 | 8 | write_macro_placement $filename.tmp 9 | set f [open $filename.tmp r] 10 | set content [read $f] 11 | set content [string map {"/" "."} $content] 12 | close $f 13 | 14 | set f [open $filename w] 15 | puts -nonewline $f $content 16 | close $f 17 | -------------------------------------------------------------------------------- /report-floorplan.tcl: -------------------------------------------------------------------------------- 1 | source $::env(SCRIPTS_DIR)/load.tcl 2 | load_design 2_floorplan.odb 2_floorplan.sdc 3 | 4 | set f [open "$::env(OUTFILE)" w] 5 | set db [::ord::get_db] 6 | set dbu_per_uu [expr double([[$db getTech] getDbUnitsPerMicron])] 7 | set block [[$db getChip] getBlock] 8 | set die_bbox [$block getDieArea] 9 | set scale [expr 1 / $dbu_per_uu] 10 | puts $f "width: [expr [$die_bbox xMax] * $scale]" 11 | puts $f "height: [expr [$die_bbox yMax] * $scale]" 12 | 13 | close $f 14 | -------------------------------------------------------------------------------- /write_binary.bzl: -------------------------------------------------------------------------------- 1 | """ 2 | This module contains a rule for writing binary files. 3 | """ 4 | 5 | def _write_binary_impl(ctx): 6 | out = ctx.actions.declare_file(ctx.label.name) 7 | ctx.actions.write( 8 | output = out, 9 | content = ctx.attr.data, 10 | ) 11 | return [DefaultInfo(files = depset([out]))] 12 | 13 | write_binary = rule( 14 | implementation = _write_binary_impl, 15 | attrs = { 16 | "data": attr.string(), 17 | }, 18 | ) 19 | -------------------------------------------------------------------------------- /report-sram.tcl: -------------------------------------------------------------------------------- 1 | source $::env(SCRIPTS_DIR)/load.tcl 2 | load_design $::env(STAGE).odb $::env(STAGE).sdc 3 | 4 | set f [open "$::env(OUTFILE)" w] 5 | foreach path_group {in2reg reg2out in2out reg2reg} { 6 | set paths [find_timing_paths -path_group $path_group -sort_by_slack] 7 | if {[llength $paths] == 0} { 8 | set worst "N/A" 9 | } else { 10 | set points [get_property [lindex $paths 0] points] 11 | set worst [get_property [lindex $points [expr [llength $points] - 1]] arrival] 12 | } 13 | puts $f "$path_group: $worst" 14 | } 15 | close $f 16 | -------------------------------------------------------------------------------- /etc/BuildMegaboom.sh: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env bash 2 | set -euox pipefail 3 | 4 | # Sets up logging to build.log file 5 | exec > >(tee -i build.log) 6 | exec 2>&1 7 | 8 | # Check GCP service account entitlements first 9 | test/cred_helper_test.py 10 | 11 | bazel build BoomTile_sweep_parallel --keep_going 12 | # If we're not sweeping grt, then we could have 13 | # started wns_report sooner, but at least we're not 14 | # running multiple grt builds in parallel, which makes 15 | # the server fall over. 16 | bazel build --jobs 1 BoomTile_wns_report BoomTile_grt --keep_going 17 | cat bazel-bin/BoomTile_wns_report.md 18 | -------------------------------------------------------------------------------- /rtl/SimJTAG.cc: -------------------------------------------------------------------------------- 1 | // See LICENSE.SiFive for license details. 2 | 3 | #include 4 | #include "remote_bitbang.h" 5 | 6 | remote_bitbang_t* jtag; 7 | extern "C" int jtag_tick 8 | ( 9 | unsigned char * jtag_TCK, 10 | unsigned char * jtag_TMS, 11 | unsigned char * jtag_TDI, 12 | unsigned char * jtag_TRSTn, 13 | unsigned char jtag_TDO 14 | ) 15 | { 16 | if (!jtag) { 17 | // TODO: Pass in real port number 18 | jtag = new remote_bitbang_t(0); 19 | } 20 | 21 | jtag->tick(jtag_TCK, jtag_TMS, jtag_TDI, jtag_TRSTn, jtag_TDO); 22 | 23 | return jtag->done() ? (jtag->exit_code() << 1 | 1) : 0; 24 | 25 | } 26 | -------------------------------------------------------------------------------- /etc/DockerTag.sh: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env bash 2 | # 3 | # Creates and returns a SHA256 for the input files so that we can determine if a new Docker machine 4 | # image needs to be created and pushed to docker hub 5 | # 6 | 7 | cd $(dirname $(realpath $0))/../ 8 | 9 | if [[ "$@" == "-dev" ]]; then 10 | file_list=( 11 | "./docker/Dockerfile.dev" 12 | "./docker/bazelrc" 13 | "./etc/DockerHelper.sh" 14 | "./etc/DockerTag.sh" 15 | ) 16 | cat "${file_list[@]}" | sha256sum | awk '{print substr($1, 1, 6)}' 17 | elif [[ "$@" == "-main" ]]; then 18 | git describe 19 | else 20 | echo "Usage: $0 {-dev|-main}" 21 | exit 1 22 | fi 23 | -------------------------------------------------------------------------------- /write_kept.tcl: -------------------------------------------------------------------------------- 1 | yosys -import 2 | 3 | # stdcells are in .v file 4 | read_verilog $::env(RESULTS_DIR)/1_synth.v 5 | 6 | tee -q -o keep.txt -s kept ls A:keep_hierarchy=1 7 | 8 | set f [open keep.txt] 9 | set lines [split [read $f] \n] 10 | close $f 11 | 12 | set lines [lrange $lines 2 end-1] 13 | set lines [lmap line $lines {string trim $line}] 14 | lappend lines $::env(DESIGN_NAME) 15 | set lines [lsort $lines] 16 | 17 | set f [open [file join $::env(WORK_HOME) "kept.bzl"] "w"] 18 | puts $f "# buildifier: disable=module-docstring" 19 | puts $f "# asdfsafds" 20 | puts $f "KEPT_MODULES = \[" 21 | foreach master $lines { 22 | puts $f " \"$master\"," 23 | } 24 | puts $f "\]" 25 | close $f 26 | -------------------------------------------------------------------------------- /.github/workflows/ci.yml: -------------------------------------------------------------------------------- 1 | name: MegaBoom 2 | 3 | on: 4 | workflow_dispatch: 5 | push: 6 | pull_request: 7 | 8 | jobs: 9 | lint: 10 | name: Lint Bazel files 11 | runs-on: ubuntu-22.04 12 | env: 13 | DEBIAN_FRONTEND: "noninteractive" 14 | steps: 15 | - name: Download buildifier 16 | run: | 17 | wget https://github.com/bazelbuild/buildtools/releases/download/v6.4.0/buildifier-linux-amd64 -O /usr/local/bin/buildifier 18 | chmod +x /usr/local/bin/buildifier 19 | buildifier -version 20 | - name: Checkout megaboom 21 | uses: actions/checkout@v4 22 | - name: Check Bazel files 23 | run: | 24 | buildifier -lint warn -r . 25 | -------------------------------------------------------------------------------- /rtl/plusarg_reader.v: -------------------------------------------------------------------------------- 1 | // See LICENSE.SiFive for license details. 2 | 3 | //VCS coverage exclude_file 4 | 5 | // No default parameter values are intended, nor does IEEE 1800-2012 require them (clause A.2.4 param_assignment), 6 | // but Incisive demands them. These default values should never be used. 7 | module plusarg_reader #( 8 | parameter FORMAT="borked=%d", 9 | parameter WIDTH=1, 10 | parameter [WIDTH-1:0] DEFAULT=0 11 | ) ( 12 | output [WIDTH-1:0] out 13 | ); 14 | 15 | `ifdef SYNTHESIS 16 | assign out = DEFAULT; 17 | `else 18 | reg [WIDTH-1:0] myplus; 19 | assign out = myplus; 20 | 21 | initial begin 22 | if (!$value$plusargs(FORMAT, myplus)) myplus = DEFAULT; 23 | end 24 | `endif 25 | 26 | endmodule 27 | -------------------------------------------------------------------------------- /rtl/testchip_htif.h: -------------------------------------------------------------------------------- 1 | #ifndef __TESTCHIP_HTIF_H 2 | #define __TESTCHIP_HTIF_H 3 | 4 | #include 5 | #include 6 | #include 7 | #include 8 | #include 9 | 10 | struct init_access_t { 11 | uint64_t address; 12 | uint32_t stdata; 13 | bool store; 14 | }; 15 | 16 | class testchip_htif_t 17 | { 18 | public: 19 | virtual void write_chunk(addr_t taddr, size_t nbytes, const void* src) = 0; 20 | virtual void read_chunk(addr_t taddr, size_t nbytes, void* dst) = 0; 21 | virtual ~testchip_htif_t() {}; 22 | 23 | protected: 24 | void perform_init_accesses(); 25 | void parse_htif_args(std::vector &args); 26 | bool write_hart0_msip = true; 27 | std::vector init_accesses; 28 | }; 29 | #endif 30 | -------------------------------------------------------------------------------- /rtl/Arbiter_8.sv: -------------------------------------------------------------------------------- 1 | // Standard header to adapt well known macros for prints and assertions. 2 | 3 | // Users can define 'ASSERT_VERBOSE_COND' to add an extra gate to assert error printing. 4 | `ifndef ASSERT_VERBOSE_COND_ 5 | `ifdef ASSERT_VERBOSE_COND 6 | `define ASSERT_VERBOSE_COND_ (`ASSERT_VERBOSE_COND) 7 | `else // ASSERT_VERBOSE_COND 8 | `define ASSERT_VERBOSE_COND_ 1 9 | `endif // ASSERT_VERBOSE_COND 10 | `endif // not def ASSERT_VERBOSE_COND_ 11 | 12 | // Users can define 'STOP_COND' to add an extra gate to stop conditions. 13 | `ifndef STOP_COND_ 14 | `ifdef STOP_COND 15 | `define STOP_COND_ (`STOP_COND) 16 | `else // STOP_COND 17 | `define STOP_COND_ 1 18 | `endif // STOP_COND 19 | `endif // not def STOP_COND_ 20 | 21 | module Arbiter_8( 22 | output io_in_0_ready, 23 | input io_out_ready 24 | ); 25 | 26 | assign io_in_0_ready = io_out_ready; 27 | endmodule 28 | 29 | -------------------------------------------------------------------------------- /rtl/OptimizationBarrier_92.sv: -------------------------------------------------------------------------------- 1 | // Standard header to adapt well known macros for prints and assertions. 2 | 3 | // Users can define 'ASSERT_VERBOSE_COND' to add an extra gate to assert error printing. 4 | `ifndef ASSERT_VERBOSE_COND_ 5 | `ifdef ASSERT_VERBOSE_COND 6 | `define ASSERT_VERBOSE_COND_ (`ASSERT_VERBOSE_COND) 7 | `else // ASSERT_VERBOSE_COND 8 | `define ASSERT_VERBOSE_COND_ 1 9 | `endif // ASSERT_VERBOSE_COND 10 | `endif // not def ASSERT_VERBOSE_COND_ 11 | 12 | // Users can define 'STOP_COND' to add an extra gate to stop conditions. 13 | `ifndef STOP_COND_ 14 | `ifdef STOP_COND 15 | `define STOP_COND_ (`STOP_COND) 16 | `else // STOP_COND 17 | `define STOP_COND_ 1 18 | `endif // STOP_COND 19 | `endif // not def STOP_COND_ 20 | 21 | module OptimizationBarrier_92( 22 | input [2:0] io_x, 23 | output [2:0] io_y 24 | ); 25 | 26 | assign io_y = io_x; 27 | endmodule 28 | 29 | -------------------------------------------------------------------------------- /rtl/BundleBridgeNexus_16.sv: -------------------------------------------------------------------------------- 1 | // Standard header to adapt well known macros for prints and assertions. 2 | 3 | // Users can define 'ASSERT_VERBOSE_COND' to add an extra gate to assert error printing. 4 | `ifndef ASSERT_VERBOSE_COND_ 5 | `ifdef ASSERT_VERBOSE_COND 6 | `define ASSERT_VERBOSE_COND_ (`ASSERT_VERBOSE_COND) 7 | `else // ASSERT_VERBOSE_COND 8 | `define ASSERT_VERBOSE_COND_ 1 9 | `endif // ASSERT_VERBOSE_COND 10 | `endif // not def ASSERT_VERBOSE_COND_ 11 | 12 | // Users can define 'STOP_COND' to add an extra gate to stop conditions. 13 | `ifndef STOP_COND_ 14 | `ifdef STOP_COND 15 | `define STOP_COND_ (`STOP_COND) 16 | `else // STOP_COND 17 | `define STOP_COND_ 1 18 | `endif // STOP_COND 19 | `endif // not def STOP_COND_ 20 | 21 | module BundleBridgeNexus_16( 22 | output auto_out 23 | ); 24 | 25 | wire outputs_0 = 1'h0; 26 | assign auto_out = outputs_0; 27 | endmodule 28 | 29 | -------------------------------------------------------------------------------- /rtl/IntSyncCrossingSource_4.sv: -------------------------------------------------------------------------------- 1 | // Standard header to adapt well known macros for prints and assertions. 2 | 3 | // Users can define 'ASSERT_VERBOSE_COND' to add an extra gate to assert error printing. 4 | `ifndef ASSERT_VERBOSE_COND_ 5 | `ifdef ASSERT_VERBOSE_COND 6 | `define ASSERT_VERBOSE_COND_ (`ASSERT_VERBOSE_COND) 7 | `else // ASSERT_VERBOSE_COND 8 | `define ASSERT_VERBOSE_COND_ 1 9 | `endif // ASSERT_VERBOSE_COND 10 | `endif // not def ASSERT_VERBOSE_COND_ 11 | 12 | // Users can define 'STOP_COND' to add an extra gate to stop conditions. 13 | `ifndef STOP_COND_ 14 | `ifdef STOP_COND 15 | `define STOP_COND_ (`STOP_COND) 16 | `else // STOP_COND 17 | `define STOP_COND_ 1 18 | `endif // STOP_COND 19 | `endif // not def STOP_COND_ 20 | 21 | module IntSyncCrossingSource_4( 22 | input auto_in_0, 23 | output auto_out_sync_0 24 | ); 25 | 26 | assign auto_out_sync_0 = auto_in_0; 27 | endmodule 28 | 29 | -------------------------------------------------------------------------------- /rtl/IntSyncSyncCrossingSink.sv: -------------------------------------------------------------------------------- 1 | // Standard header to adapt well known macros for prints and assertions. 2 | 3 | // Users can define 'ASSERT_VERBOSE_COND' to add an extra gate to assert error printing. 4 | `ifndef ASSERT_VERBOSE_COND_ 5 | `ifdef ASSERT_VERBOSE_COND 6 | `define ASSERT_VERBOSE_COND_ (`ASSERT_VERBOSE_COND) 7 | `else // ASSERT_VERBOSE_COND 8 | `define ASSERT_VERBOSE_COND_ 1 9 | `endif // ASSERT_VERBOSE_COND 10 | `endif // not def ASSERT_VERBOSE_COND_ 11 | 12 | // Users can define 'STOP_COND' to add an extra gate to stop conditions. 13 | `ifndef STOP_COND_ 14 | `ifdef STOP_COND 15 | `define STOP_COND_ (`STOP_COND) 16 | `else // STOP_COND 17 | `define STOP_COND_ 1 18 | `endif // STOP_COND 19 | `endif // not def STOP_COND_ 20 | 21 | module IntSyncSyncCrossingSink( 22 | input auto_in_sync_0, 23 | auto_in_sync_1, 24 | output auto_out_0, 25 | auto_out_1 26 | ); 27 | 28 | assign auto_out_0 = auto_in_sync_0; 29 | assign auto_out_1 = auto_in_sync_1; 30 | endmodule 31 | 32 | -------------------------------------------------------------------------------- /rtl/IntSyncAsyncCrossingSink.sv: -------------------------------------------------------------------------------- 1 | // Standard header to adapt well known macros for prints and assertions. 2 | 3 | // Users can define 'ASSERT_VERBOSE_COND' to add an extra gate to assert error printing. 4 | `ifndef ASSERT_VERBOSE_COND_ 5 | `ifdef ASSERT_VERBOSE_COND 6 | `define ASSERT_VERBOSE_COND_ (`ASSERT_VERBOSE_COND) 7 | `else // ASSERT_VERBOSE_COND 8 | `define ASSERT_VERBOSE_COND_ 1 9 | `endif // ASSERT_VERBOSE_COND 10 | `endif // not def ASSERT_VERBOSE_COND_ 11 | 12 | // Users can define 'STOP_COND' to add an extra gate to stop conditions. 13 | `ifndef STOP_COND_ 14 | `ifdef STOP_COND 15 | `define STOP_COND_ (`STOP_COND) 16 | `else // STOP_COND 17 | `define STOP_COND_ 1 18 | `endif // STOP_COND 19 | `endif // not def STOP_COND_ 20 | 21 | module IntSyncAsyncCrossingSink( 22 | input clock, 23 | auto_in_sync_0, 24 | output auto_out_0 25 | ); 26 | 27 | SynchronizerShiftReg_w1_d3 chain ( 28 | .clock (clock), 29 | .io_d (auto_in_sync_0), 30 | .io_q (auto_out_0) 31 | ); 32 | endmodule 33 | 34 | -------------------------------------------------------------------------------- /rtl/SynchronizerShiftReg_w1_d3.sv: -------------------------------------------------------------------------------- 1 | // Standard header to adapt well known macros for prints and assertions. 2 | 3 | // Users can define 'ASSERT_VERBOSE_COND' to add an extra gate to assert error printing. 4 | `ifndef ASSERT_VERBOSE_COND_ 5 | `ifdef ASSERT_VERBOSE_COND 6 | `define ASSERT_VERBOSE_COND_ (`ASSERT_VERBOSE_COND) 7 | `else // ASSERT_VERBOSE_COND 8 | `define ASSERT_VERBOSE_COND_ 1 9 | `endif // ASSERT_VERBOSE_COND 10 | `endif // not def ASSERT_VERBOSE_COND_ 11 | 12 | // Users can define 'STOP_COND' to add an extra gate to stop conditions. 13 | `ifndef STOP_COND_ 14 | `ifdef STOP_COND 15 | `define STOP_COND_ (`STOP_COND) 16 | `else // STOP_COND 17 | `define STOP_COND_ 1 18 | `endif // STOP_COND 19 | `endif // not def STOP_COND_ 20 | 21 | module SynchronizerShiftReg_w1_d3( 22 | input clock, 23 | io_d, 24 | output io_q 25 | ); 26 | 27 | NonSyncResetSynchronizerPrimitiveShiftReg_d3 output_chain ( 28 | .clock (clock), 29 | .io_d (io_d), 30 | .io_q (io_q) 31 | ); 32 | endmodule 33 | 34 | -------------------------------------------------------------------------------- /rtl/AsyncValidSync.sv: -------------------------------------------------------------------------------- 1 | // Standard header to adapt well known macros for prints and assertions. 2 | 3 | // Users can define 'ASSERT_VERBOSE_COND' to add an extra gate to assert error printing. 4 | `ifndef ASSERT_VERBOSE_COND_ 5 | `ifdef ASSERT_VERBOSE_COND 6 | `define ASSERT_VERBOSE_COND_ (`ASSERT_VERBOSE_COND) 7 | `else // ASSERT_VERBOSE_COND 8 | `define ASSERT_VERBOSE_COND_ 1 9 | `endif // ASSERT_VERBOSE_COND 10 | `endif // not def ASSERT_VERBOSE_COND_ 11 | 12 | // Users can define 'STOP_COND' to add an extra gate to stop conditions. 13 | `ifndef STOP_COND_ 14 | `ifdef STOP_COND 15 | `define STOP_COND_ (`STOP_COND) 16 | `else // STOP_COND 17 | `define STOP_COND_ 1 18 | `endif // STOP_COND 19 | `endif // not def STOP_COND_ 20 | 21 | module AsyncValidSync( 22 | input io_in, 23 | output io_out, 24 | input clock, 25 | reset 26 | ); 27 | 28 | AsyncResetSynchronizerShiftReg_w1_d3_i0_1 io_out_source_valid_0 ( 29 | .clock (clock), 30 | .reset (reset), 31 | .io_d (io_in), 32 | .io_q (io_out) 33 | ); 34 | endmodule 35 | 36 | -------------------------------------------------------------------------------- /rtl/ClockCrossingReg_w4.sv: -------------------------------------------------------------------------------- 1 | // Standard header to adapt well known macros for prints and assertions. 2 | 3 | // Users can define 'ASSERT_VERBOSE_COND' to add an extra gate to assert error printing. 4 | `ifndef ASSERT_VERBOSE_COND_ 5 | `ifdef ASSERT_VERBOSE_COND 6 | `define ASSERT_VERBOSE_COND_ (`ASSERT_VERBOSE_COND) 7 | `else // ASSERT_VERBOSE_COND 8 | `define ASSERT_VERBOSE_COND_ 1 9 | `endif // ASSERT_VERBOSE_COND 10 | `endif // not def ASSERT_VERBOSE_COND_ 11 | 12 | // Users can define 'STOP_COND' to add an extra gate to stop conditions. 13 | `ifndef STOP_COND_ 14 | `ifdef STOP_COND 15 | `define STOP_COND_ (`STOP_COND) 16 | `else // STOP_COND 17 | `define STOP_COND_ 1 18 | `endif // STOP_COND 19 | `endif // not def STOP_COND_ 20 | 21 | module ClockCrossingReg_w4( 22 | input clock, 23 | input [3:0] io_d, 24 | output [3:0] io_q, 25 | input io_en 26 | ); 27 | 28 | reg [3:0] cdc_reg; 29 | always @(posedge clock) begin 30 | if (io_en) 31 | cdc_reg <= io_d; 32 | end // always @(posedge) 33 | assign io_q = cdc_reg; 34 | endmodule 35 | 36 | -------------------------------------------------------------------------------- /rtl/ClockCrossingReg_w15.sv: -------------------------------------------------------------------------------- 1 | // Standard header to adapt well known macros for prints and assertions. 2 | 3 | // Users can define 'ASSERT_VERBOSE_COND' to add an extra gate to assert error printing. 4 | `ifndef ASSERT_VERBOSE_COND_ 5 | `ifdef ASSERT_VERBOSE_COND 6 | `define ASSERT_VERBOSE_COND_ (`ASSERT_VERBOSE_COND) 7 | `else // ASSERT_VERBOSE_COND 8 | `define ASSERT_VERBOSE_COND_ 1 9 | `endif // ASSERT_VERBOSE_COND 10 | `endif // not def ASSERT_VERBOSE_COND_ 11 | 12 | // Users can define 'STOP_COND' to add an extra gate to stop conditions. 13 | `ifndef STOP_COND_ 14 | `ifdef STOP_COND 15 | `define STOP_COND_ (`STOP_COND) 16 | `else // STOP_COND 17 | `define STOP_COND_ 1 18 | `endif // STOP_COND 19 | `endif // not def STOP_COND_ 20 | 21 | module ClockCrossingReg_w15( 22 | input clock, 23 | input [14:0] io_d, 24 | output [14:0] io_q, 25 | input io_en 26 | ); 27 | 28 | reg [14:0] cdc_reg; 29 | always @(posedge clock) begin 30 | if (io_en) 31 | cdc_reg <= io_d; 32 | end // always @(posedge) 33 | assign io_q = cdc_reg; 34 | endmodule 35 | 36 | -------------------------------------------------------------------------------- /rtl/ClockCrossingReg_w43.sv: -------------------------------------------------------------------------------- 1 | // Standard header to adapt well known macros for prints and assertions. 2 | 3 | // Users can define 'ASSERT_VERBOSE_COND' to add an extra gate to assert error printing. 4 | `ifndef ASSERT_VERBOSE_COND_ 5 | `ifdef ASSERT_VERBOSE_COND 6 | `define ASSERT_VERBOSE_COND_ (`ASSERT_VERBOSE_COND) 7 | `else // ASSERT_VERBOSE_COND 8 | `define ASSERT_VERBOSE_COND_ 1 9 | `endif // ASSERT_VERBOSE_COND 10 | `endif // not def ASSERT_VERBOSE_COND_ 11 | 12 | // Users can define 'STOP_COND' to add an extra gate to stop conditions. 13 | `ifndef STOP_COND_ 14 | `ifdef STOP_COND 15 | `define STOP_COND_ (`STOP_COND) 16 | `else // STOP_COND 17 | `define STOP_COND_ 1 18 | `endif // STOP_COND 19 | `endif // not def STOP_COND_ 20 | 21 | module ClockCrossingReg_w43( 22 | input clock, 23 | input [42:0] io_d, 24 | output [42:0] io_q, 25 | input io_en 26 | ); 27 | 28 | reg [42:0] cdc_reg; 29 | always @(posedge clock) begin 30 | if (io_en) 31 | cdc_reg <= io_d; 32 | end // always @(posedge) 33 | assign io_q = cdc_reg; 34 | endmodule 35 | 36 | -------------------------------------------------------------------------------- /rtl/ClockCrossingReg_w55.sv: -------------------------------------------------------------------------------- 1 | // Standard header to adapt well known macros for prints and assertions. 2 | 3 | // Users can define 'ASSERT_VERBOSE_COND' to add an extra gate to assert error printing. 4 | `ifndef ASSERT_VERBOSE_COND_ 5 | `ifdef ASSERT_VERBOSE_COND 6 | `define ASSERT_VERBOSE_COND_ (`ASSERT_VERBOSE_COND) 7 | `else // ASSERT_VERBOSE_COND 8 | `define ASSERT_VERBOSE_COND_ 1 9 | `endif // ASSERT_VERBOSE_COND 10 | `endif // not def ASSERT_VERBOSE_COND_ 11 | 12 | // Users can define 'STOP_COND' to add an extra gate to stop conditions. 13 | `ifndef STOP_COND_ 14 | `ifdef STOP_COND 15 | `define STOP_COND_ (`STOP_COND) 16 | `else // STOP_COND 17 | `define STOP_COND_ 1 18 | `endif // STOP_COND 19 | `endif // not def STOP_COND_ 20 | 21 | module ClockCrossingReg_w55( 22 | input clock, 23 | input [54:0] io_d, 24 | output [54:0] io_q, 25 | input io_en 26 | ); 27 | 28 | reg [54:0] cdc_reg; 29 | always @(posedge clock) begin 30 | if (io_en) 31 | cdc_reg <= io_d; 32 | end // always @(posedge) 33 | assign io_q = cdc_reg; 34 | endmodule 35 | 36 | -------------------------------------------------------------------------------- /rtl/ResetSynchronizerShiftReg_w1_d3_i0.sv: -------------------------------------------------------------------------------- 1 | // Standard header to adapt well known macros for prints and assertions. 2 | 3 | // Users can define 'ASSERT_VERBOSE_COND' to add an extra gate to assert error printing. 4 | `ifndef ASSERT_VERBOSE_COND_ 5 | `ifdef ASSERT_VERBOSE_COND 6 | `define ASSERT_VERBOSE_COND_ (`ASSERT_VERBOSE_COND) 7 | `else // ASSERT_VERBOSE_COND 8 | `define ASSERT_VERBOSE_COND_ 1 9 | `endif // ASSERT_VERBOSE_COND 10 | `endif // not def ASSERT_VERBOSE_COND_ 11 | 12 | // Users can define 'STOP_COND' to add an extra gate to stop conditions. 13 | `ifndef STOP_COND_ 14 | `ifdef STOP_COND 15 | `define STOP_COND_ (`STOP_COND) 16 | `else // STOP_COND 17 | `define STOP_COND_ 1 18 | `endif // STOP_COND 19 | `endif // not def STOP_COND_ 20 | 21 | module ResetSynchronizerShiftReg_w1_d3_i0( 22 | input clock, 23 | reset, 24 | io_d, 25 | output io_q 26 | ); 27 | 28 | AsyncResetSynchronizerPrimitiveShiftReg_d3_i0 output_chain ( 29 | .clock (clock), 30 | .reset (reset), 31 | .io_d (io_d), 32 | .io_q (io_q) 33 | ); 34 | endmodule 35 | 36 | -------------------------------------------------------------------------------- /rtl/AsyncResetSynchronizerShiftReg_w1_d3_i0.sv: -------------------------------------------------------------------------------- 1 | // Standard header to adapt well known macros for prints and assertions. 2 | 3 | // Users can define 'ASSERT_VERBOSE_COND' to add an extra gate to assert error printing. 4 | `ifndef ASSERT_VERBOSE_COND_ 5 | `ifdef ASSERT_VERBOSE_COND 6 | `define ASSERT_VERBOSE_COND_ (`ASSERT_VERBOSE_COND) 7 | `else // ASSERT_VERBOSE_COND 8 | `define ASSERT_VERBOSE_COND_ 1 9 | `endif // ASSERT_VERBOSE_COND 10 | `endif // not def ASSERT_VERBOSE_COND_ 11 | 12 | // Users can define 'STOP_COND' to add an extra gate to stop conditions. 13 | `ifndef STOP_COND_ 14 | `ifdef STOP_COND 15 | `define STOP_COND_ (`STOP_COND) 16 | `else // STOP_COND 17 | `define STOP_COND_ 1 18 | `endif // STOP_COND 19 | `endif // not def STOP_COND_ 20 | 21 | module AsyncResetSynchronizerShiftReg_w1_d3_i0( 22 | input clock, 23 | reset, 24 | io_d, 25 | output io_q 26 | ); 27 | 28 | AsyncResetSynchronizerPrimitiveShiftReg_d3_i0 output_chain ( 29 | .clock (clock), 30 | .reset (reset), 31 | .io_d (io_d), 32 | .io_q (io_q) 33 | ); 34 | endmodule 35 | 36 | -------------------------------------------------------------------------------- /rtl/AsyncResetSynchronizerShiftReg_w1_d3_i0_1.sv: -------------------------------------------------------------------------------- 1 | // Standard header to adapt well known macros for prints and assertions. 2 | 3 | // Users can define 'ASSERT_VERBOSE_COND' to add an extra gate to assert error printing. 4 | `ifndef ASSERT_VERBOSE_COND_ 5 | `ifdef ASSERT_VERBOSE_COND 6 | `define ASSERT_VERBOSE_COND_ (`ASSERT_VERBOSE_COND) 7 | `else // ASSERT_VERBOSE_COND 8 | `define ASSERT_VERBOSE_COND_ 1 9 | `endif // ASSERT_VERBOSE_COND 10 | `endif // not def ASSERT_VERBOSE_COND_ 11 | 12 | // Users can define 'STOP_COND' to add an extra gate to stop conditions. 13 | `ifndef STOP_COND_ 14 | `ifdef STOP_COND 15 | `define STOP_COND_ (`STOP_COND) 16 | `else // STOP_COND 17 | `define STOP_COND_ 1 18 | `endif // STOP_COND 19 | `endif // not def STOP_COND_ 20 | 21 | module AsyncResetSynchronizerShiftReg_w1_d3_i0_1( 22 | input clock, 23 | reset, 24 | io_d, 25 | output io_q 26 | ); 27 | 28 | AsyncResetSynchronizerPrimitiveShiftReg_d3_i0 output_chain ( 29 | .clock (clock), 30 | .reset (reset), 31 | .io_d (io_d), 32 | .io_q (io_q) 33 | ); 34 | endmodule 35 | 36 | -------------------------------------------------------------------------------- /rtl/IntXbar_1.sv: -------------------------------------------------------------------------------- 1 | // Standard header to adapt well known macros for prints and assertions. 2 | 3 | // Users can define 'ASSERT_VERBOSE_COND' to add an extra gate to assert error printing. 4 | `ifndef ASSERT_VERBOSE_COND_ 5 | `ifdef ASSERT_VERBOSE_COND 6 | `define ASSERT_VERBOSE_COND_ (`ASSERT_VERBOSE_COND) 7 | `else // ASSERT_VERBOSE_COND 8 | `define ASSERT_VERBOSE_COND_ 1 9 | `endif // ASSERT_VERBOSE_COND 10 | `endif // not def ASSERT_VERBOSE_COND_ 11 | 12 | // Users can define 'STOP_COND' to add an extra gate to stop conditions. 13 | `ifndef STOP_COND_ 14 | `ifdef STOP_COND 15 | `define STOP_COND_ (`STOP_COND) 16 | `else // STOP_COND 17 | `define STOP_COND_ 1 18 | `endif // STOP_COND 19 | `endif // not def STOP_COND_ 20 | 21 | module IntXbar_1( 22 | input auto_int_in_1_0, 23 | auto_int_in_1_1, 24 | auto_int_in_0_0, 25 | output auto_int_out_0, 26 | auto_int_out_1, 27 | auto_int_out_2 28 | ); 29 | 30 | assign auto_int_out_0 = auto_int_in_0_0; 31 | assign auto_int_out_1 = auto_int_in_1_0; 32 | assign auto_int_out_2 = auto_int_in_1_1; 33 | endmodule 34 | 35 | -------------------------------------------------------------------------------- /rtl/testchip_tsi.h: -------------------------------------------------------------------------------- 1 | #ifndef __TESTCHIP_TSI_H 2 | #define __TESTCHIP_TSI_H 3 | 4 | #include 5 | 6 | #include 7 | #include 8 | #include "testchip_htif.h" 9 | 10 | class testchip_tsi_t : public tsi_t, public testchip_htif_t 11 | { 12 | public: 13 | testchip_tsi_t(int argc, char** argv, bool has_loadmem); 14 | virtual ~testchip_tsi_t() {}; 15 | 16 | void write_chunk(addr_t taddr, size_t nbytes, const void* src) override; 17 | void read_chunk(addr_t taddr, size_t nbytes, void* dst) override; 18 | void load_program() { 19 | switch_to_target(); 20 | is_loadmem = has_loadmem; 21 | tsi_t::load_program(); 22 | is_loadmem = false; 23 | } 24 | void idle() { switch_to_target(); } 25 | 26 | protected: 27 | virtual void load_mem_write(addr_t taddr, size_t nbytes, const void* src) { }; 28 | virtual void load_mem_read(addr_t taddr, size_t nbytes, void* dst) { }; 29 | void flush_cache_lines(addr_t taddr, size_t nbytes); 30 | void reset() override; 31 | bool has_loadmem; 32 | 33 | private: 34 | 35 | bool is_loadmem; 36 | addr_t cflush_addr; 37 | }; 38 | #endif 39 | -------------------------------------------------------------------------------- /constraints-boomtile.sdc: -------------------------------------------------------------------------------- 1 | set sdc_version 2.0 2 | 3 | # 4 | # SDC file used by BoomTile top level 5 | # 6 | 7 | set clk_period 1200 8 | set clk_name clock 9 | set clk_port_name clock 10 | 11 | # Ignore synchronous reset for now. 12 | set_false_path -from [get_ports reset] 13 | 14 | set clk_port [get_ports $clk_port_name] 15 | create_clock -period $clk_period -waveform [list 0 [expr $clk_period / 2]] -name $clk_name $clk_port 16 | 17 | set non_clk_inputs [all_inputs -no_clocks] 18 | 19 | if {[llength [all_registers]] > 0} { 20 | set_max_delay [expr {[info exists in2reg_max] ? $in2reg_max : 80}] -from $non_clk_inputs -to [all_registers] 21 | set_max_delay [expr {[info exists reg2out_max] ? $reg2out_max : 80}] -from [all_registers] -to [all_outputs] 22 | 23 | group_path -name in2reg -from $non_clk_inputs -to [all_registers] 24 | group_path -name reg2out -from [all_registers] -to [all_outputs] 25 | group_path -name reg2reg -from [all_registers] -to [all_registers] 26 | } 27 | 28 | set_max_delay [expr {[info exists in2out_max] ? $in2out_max : 80}] -from $non_clk_inputs -to [all_outputs] 29 | group_path -name in2out -from $non_clk_inputs -to [all_outputs] 30 | -------------------------------------------------------------------------------- /rtl/NonSyncResetSynchronizerPrimitiveShiftReg_d3.sv: -------------------------------------------------------------------------------- 1 | // Standard header to adapt well known macros for prints and assertions. 2 | 3 | // Users can define 'ASSERT_VERBOSE_COND' to add an extra gate to assert error printing. 4 | `ifndef ASSERT_VERBOSE_COND_ 5 | `ifdef ASSERT_VERBOSE_COND 6 | `define ASSERT_VERBOSE_COND_ (`ASSERT_VERBOSE_COND) 7 | `else // ASSERT_VERBOSE_COND 8 | `define ASSERT_VERBOSE_COND_ 1 9 | `endif // ASSERT_VERBOSE_COND 10 | `endif // not def ASSERT_VERBOSE_COND_ 11 | 12 | // Users can define 'STOP_COND' to add an extra gate to stop conditions. 13 | `ifndef STOP_COND_ 14 | `ifdef STOP_COND 15 | `define STOP_COND_ (`STOP_COND) 16 | `else // STOP_COND 17 | `define STOP_COND_ 1 18 | `endif // STOP_COND 19 | `endif // not def STOP_COND_ 20 | 21 | module NonSyncResetSynchronizerPrimitiveShiftReg_d3( 22 | input clock, 23 | io_d, 24 | output io_q 25 | ); 26 | 27 | reg sync_0; 28 | reg sync_1; 29 | reg sync_2; 30 | always @(posedge clock) begin 31 | sync_0 <= sync_1; 32 | sync_1 <= sync_2; 33 | sync_2 <= io_d; 34 | end // always @(posedge) 35 | assign io_q = sync_0; 36 | endmodule 37 | 38 | -------------------------------------------------------------------------------- /rtl/extern_modules.sv: -------------------------------------------------------------------------------- 1 | // Standard header to adapt well known macros for prints and assertions. 2 | 3 | // Users can define 'ASSERT_VERBOSE_COND' to add an extra gate to assert error printing. 4 | `ifndef ASSERT_VERBOSE_COND_ 5 | `ifdef ASSERT_VERBOSE_COND 6 | `define ASSERT_VERBOSE_COND_ (`ASSERT_VERBOSE_COND) 7 | `else // ASSERT_VERBOSE_COND 8 | `define ASSERT_VERBOSE_COND_ 1 9 | `endif // ASSERT_VERBOSE_COND 10 | `endif // not def ASSERT_VERBOSE_COND_ 11 | 12 | // Users can define 'STOP_COND' to add an extra gate to stop conditions. 13 | `ifndef STOP_COND_ 14 | `ifdef STOP_COND 15 | `define STOP_COND_ (`STOP_COND) 16 | `else // STOP_COND 17 | `define STOP_COND_ 1 18 | `endif // STOP_COND 19 | `endif // not def STOP_COND_ 20 | 21 | // external module plusarg_reader 22 | 23 | // external module GenericDigitalOutIOCell 24 | 25 | // external module GenericDigitalInIOCell 26 | 27 | // external module EICG_wrapper 28 | 29 | // external module SimTSI 30 | 31 | // external module SimJTAG 32 | 33 | // external module plusarg_reader 34 | 35 | // external module ClockSourceAtFreqMHz 36 | 37 | // external module ClockSourceAtFreqMHz 38 | 39 | -------------------------------------------------------------------------------- /rtl/ResetCatchAndSync_d3.sv: -------------------------------------------------------------------------------- 1 | // Standard header to adapt well known macros for prints and assertions. 2 | 3 | // Users can define 'ASSERT_VERBOSE_COND' to add an extra gate to assert error printing. 4 | `ifndef ASSERT_VERBOSE_COND_ 5 | `ifdef ASSERT_VERBOSE_COND 6 | `define ASSERT_VERBOSE_COND_ (`ASSERT_VERBOSE_COND) 7 | `else // ASSERT_VERBOSE_COND 8 | `define ASSERT_VERBOSE_COND_ 1 9 | `endif // ASSERT_VERBOSE_COND 10 | `endif // not def ASSERT_VERBOSE_COND_ 11 | 12 | // Users can define 'STOP_COND' to add an extra gate to stop conditions. 13 | `ifndef STOP_COND_ 14 | `ifdef STOP_COND 15 | `define STOP_COND_ (`STOP_COND) 16 | `else // STOP_COND 17 | `define STOP_COND_ 1 18 | `endif // STOP_COND 19 | `endif // not def STOP_COND_ 20 | 21 | module ResetCatchAndSync_d3( 22 | input clock, 23 | reset, 24 | output io_sync_reset 25 | ); 26 | 27 | wire _io_sync_reset_chain_io_q; 28 | AsyncResetSynchronizerShiftReg_w1_d3_i0 io_sync_reset_chain ( 29 | .clock (clock), 30 | .reset (reset), 31 | .io_d (1'h1), 32 | .io_q (_io_sync_reset_chain_io_q) 33 | ); 34 | assign io_sync_reset = ~_io_sync_reset_chain_io_q; 35 | endmodule 36 | 37 | -------------------------------------------------------------------------------- /rtl/FixedClockBroadcast.sv: -------------------------------------------------------------------------------- 1 | // Standard header to adapt well known macros for prints and assertions. 2 | 3 | // Users can define 'ASSERT_VERBOSE_COND' to add an extra gate to assert error printing. 4 | `ifndef ASSERT_VERBOSE_COND_ 5 | `ifdef ASSERT_VERBOSE_COND 6 | `define ASSERT_VERBOSE_COND_ (`ASSERT_VERBOSE_COND) 7 | `else // ASSERT_VERBOSE_COND 8 | `define ASSERT_VERBOSE_COND_ 1 9 | `endif // ASSERT_VERBOSE_COND 10 | `endif // not def ASSERT_VERBOSE_COND_ 11 | 12 | // Users can define 'STOP_COND' to add an extra gate to stop conditions. 13 | `ifndef STOP_COND_ 14 | `ifdef STOP_COND 15 | `define STOP_COND_ (`STOP_COND) 16 | `else // STOP_COND 17 | `define STOP_COND_ 1 18 | `endif // STOP_COND 19 | `endif // not def STOP_COND_ 20 | 21 | module FixedClockBroadcast( 22 | input auto_in_clock, 23 | auto_in_reset, 24 | output auto_out_2_clock, 25 | auto_out_2_reset, 26 | auto_out_0_clock, 27 | auto_out_0_reset 28 | ); 29 | 30 | assign auto_out_2_clock = auto_in_clock; 31 | assign auto_out_2_reset = auto_in_reset; 32 | assign auto_out_0_clock = auto_in_clock; 33 | assign auto_out_0_reset = auto_in_reset; 34 | endmodule 35 | 36 | -------------------------------------------------------------------------------- /rtl/FixedClockBroadcast_6.sv: -------------------------------------------------------------------------------- 1 | // Standard header to adapt well known macros for prints and assertions. 2 | 3 | // Users can define 'ASSERT_VERBOSE_COND' to add an extra gate to assert error printing. 4 | `ifndef ASSERT_VERBOSE_COND_ 5 | `ifdef ASSERT_VERBOSE_COND 6 | `define ASSERT_VERBOSE_COND_ (`ASSERT_VERBOSE_COND) 7 | `else // ASSERT_VERBOSE_COND 8 | `define ASSERT_VERBOSE_COND_ 1 9 | `endif // ASSERT_VERBOSE_COND 10 | `endif // not def ASSERT_VERBOSE_COND_ 11 | 12 | // Users can define 'STOP_COND' to add an extra gate to stop conditions. 13 | `ifndef STOP_COND_ 14 | `ifdef STOP_COND 15 | `define STOP_COND_ (`STOP_COND) 16 | `else // STOP_COND 17 | `define STOP_COND_ 1 18 | `endif // STOP_COND 19 | `endif // not def STOP_COND_ 20 | 21 | module FixedClockBroadcast_6( 22 | input auto_in_clock, 23 | auto_in_reset, 24 | output auto_out_1_clock, 25 | auto_out_1_reset, 26 | auto_out_0_clock, 27 | auto_out_0_reset 28 | ); 29 | 30 | assign auto_out_1_clock = auto_in_clock; 31 | assign auto_out_1_reset = auto_in_reset; 32 | assign auto_out_0_clock = auto_in_clock; 33 | assign auto_out_0_reset = auto_in_reset; 34 | endmodule 35 | 36 | -------------------------------------------------------------------------------- /rtl/Arbiter_19.sv: -------------------------------------------------------------------------------- 1 | // Standard header to adapt well known macros for prints and assertions. 2 | 3 | // Users can define 'ASSERT_VERBOSE_COND' to add an extra gate to assert error printing. 4 | `ifndef ASSERT_VERBOSE_COND_ 5 | `ifdef ASSERT_VERBOSE_COND 6 | `define ASSERT_VERBOSE_COND_ (`ASSERT_VERBOSE_COND) 7 | `else // ASSERT_VERBOSE_COND 8 | `define ASSERT_VERBOSE_COND_ 1 9 | `endif // ASSERT_VERBOSE_COND 10 | `endif // not def ASSERT_VERBOSE_COND_ 11 | 12 | // Users can define 'STOP_COND' to add an extra gate to stop conditions. 13 | `ifndef STOP_COND_ 14 | `ifdef STOP_COND 15 | `define STOP_COND_ (`STOP_COND) 16 | `else // STOP_COND 17 | `define STOP_COND_ 1 18 | `endif // STOP_COND 19 | `endif // not def STOP_COND_ 20 | 21 | module Arbiter_19( 22 | input io_in_0_valid, 23 | input [5:0] io_in_0_bits, 24 | input io_in_1_valid, 25 | input [5:0] io_in_1_bits, 26 | output io_in_2_ready, 27 | input [5:0] io_in_2_bits, 28 | output [5:0] io_out_bits 29 | ); 30 | 31 | assign io_in_2_ready = ~(io_in_0_valid | io_in_1_valid); 32 | assign io_out_bits = io_in_0_valid ? io_in_0_bits : io_in_1_valid ? io_in_1_bits : io_in_2_bits; 33 | endmodule 34 | 35 | -------------------------------------------------------------------------------- /mock/array_256x64.sv: -------------------------------------------------------------------------------- 1 | // Standard header to adapt well known macros to our needs. 2 | 3 | // Users can define 'PRINTF_COND' to add an extra gate to prints. 4 | `ifndef PRINTF_COND_ 5 | `ifdef PRINTF_COND 6 | `define PRINTF_COND_ (`PRINTF_COND) 7 | `else // PRINTF_COND 8 | `define PRINTF_COND_ 1 9 | `endif // PRINTF_COND 10 | `endif // not def PRINTF_COND_ 11 | 12 | // VCS coverage exclude_file 13 | module array_256x64( 14 | input [7:0] R0_addr, 15 | input R0_en, 16 | R0_clk, 17 | input [7:0] W0_addr, 18 | input W0_en, 19 | W0_clk, 20 | input [63:0] W0_data, 21 | output [63:0] R0_data 22 | ); 23 | 24 | reg [63:0] Memory[0:15]; 25 | reg _R0_en_d0; 26 | reg [3:0] _R0_addr_d0; // Reduced to 4 bits 27 | always @(posedge R0_clk) begin 28 | _R0_en_d0 <= R0_en; 29 | _R0_addr_d0 <= R0_addr[3:0] ^ R0_addr[7:4]; // XOR upper and lower bits 30 | end // always @(posedge) 31 | always @(posedge W0_clk) begin 32 | if (W0_en) 33 | Memory[W0_addr[3:0] ^ W0_addr[7:4]] <= W0_data; // XOR upper and lower bits 34 | end // always @(posedge) 35 | assign R0_data = _R0_en_d0 ? Memory[_R0_addr_d0] : 64'bx; 36 | endmodule 37 | 38 | -------------------------------------------------------------------------------- /mock/dataArrayB_256x64.sv: -------------------------------------------------------------------------------- 1 | // Standard header to adapt well known macros to our needs. 2 | 3 | // Users can define 'PRINTF_COND' to add an extra gate to prints. 4 | `ifndef PRINTF_COND_ 5 | `ifdef PRINTF_COND 6 | `define PRINTF_COND_ (`PRINTF_COND) 7 | `else // PRINTF_COND 8 | `define PRINTF_COND_ 1 9 | `endif // PRINTF_COND 10 | `endif // not def PRINTF_COND_ 11 | 12 | // VCS coverage exclude_file 13 | module dataArrayB_256x64( 14 | input [7:0] RW0_addr, 15 | input RW0_en, 16 | RW0_clk, 17 | RW0_wmode, 18 | input [63:0] RW0_wdata, 19 | output [63:0] RW0_rdata 20 | ); 21 | 22 | reg [63:0] Memory[0:15]; // Reduced to 16 rows 23 | reg [3:0] _RW0_raddr_d0; // Reduced to 4 bits 24 | reg _RW0_ren_d0; 25 | reg _RW0_rmode_d0; 26 | always @(posedge RW0_clk) begin 27 | _RW0_raddr_d0 <= RW0_addr[3:0] ^ RW0_addr[7:4]; // XOR upper and lower bits 28 | _RW0_ren_d0 <= RW0_en; 29 | _RW0_rmode_d0 <= RW0_wmode; 30 | if (RW0_en & RW0_wmode) 31 | Memory[_RW0_raddr_d0] <= RW0_wdata; // Use XORed address 32 | end // always @(posedge) 33 | assign RW0_rdata = _RW0_ren_d0 & ~_RW0_rmode_d0 ? Memory[_RW0_raddr_d0] : 64'bx; 34 | endmodule 35 | 36 | -------------------------------------------------------------------------------- /mock/l2_tlb_ram_0_512x45.sv: -------------------------------------------------------------------------------- 1 | // Standard header to adapt well known macros to our needs. 2 | 3 | // Users can define 'PRINTF_COND' to add an extra gate to prints. 4 | `ifndef PRINTF_COND_ 5 | `ifdef PRINTF_COND 6 | `define PRINTF_COND_ (`PRINTF_COND) 7 | `else // PRINTF_COND 8 | `define PRINTF_COND_ 1 9 | `endif // PRINTF_COND 10 | `endif // not def PRINTF_COND_ 11 | 12 | // VCS coverage exclude_file 13 | module l2_tlb_ram_0_512x45( 14 | input [8:0] RW0_addr, 15 | input RW0_en, 16 | RW0_clk, 17 | RW0_wmode, 18 | input [44:0] RW0_wdata, 19 | output [44:0] RW0_rdata 20 | ); 21 | 22 | reg [44:0] Memory[0:15]; // Reduced to 16 rows 23 | reg [3:0] _RW0_raddr_d0; // Reduced to 4 bits 24 | reg _RW0_ren_d0; 25 | reg _RW0_rmode_d0; 26 | always @(posedge RW0_clk) begin 27 | _RW0_raddr_d0 <= RW0_addr[3:0] ^ RW0_addr[7:4]; // XOR upper and lower bits 28 | _RW0_ren_d0 <= RW0_en; 29 | _RW0_rmode_d0 <= RW0_wmode; 30 | if (RW0_en & RW0_wmode) 31 | Memory[_RW0_raddr_d0] <= RW0_wdata; // Use XORed address 32 | end // always @(posedge) 33 | assign RW0_rdata = _RW0_ren_d0 & ~_RW0_rmode_d0 ? Memory[_RW0_raddr_d0] : 45'bx; 34 | endmodule 35 | 36 | -------------------------------------------------------------------------------- /mock/cc_dir_1024x16.sv: -------------------------------------------------------------------------------- 1 | // Standard header to adapt well known macros to our needs. 2 | 3 | // Users can define 'PRINTF_COND' to add an extra gate to prints. 4 | `ifndef PRINTF_COND_ 5 | `ifdef PRINTF_COND 6 | `define PRINTF_COND_ (`PRINTF_COND) 7 | `else // PRINTF_COND 8 | `define PRINTF_COND_ 1 9 | `endif // PRINTF_COND 10 | `endif // not def PRINTF_COND_ 11 | 12 | // VCS coverage exclude_file 13 | module cc_dir_1024x16( 14 | input [9:0] RW0_addr, 15 | input RW0_en, 16 | RW0_clk, 17 | RW0_wmode, 18 | input [15:0] RW0_wdata, 19 | output [15:0] RW0_rdata 20 | ); 21 | 22 | reg [15:0] Memory[0:15]; // Reduced to 16 rows 23 | reg [3:0] _RW0_raddr_d0; // Reduced to 4 bits 24 | reg _RW0_ren_d0; 25 | reg _RW0_rmode_d0; 26 | always @(posedge RW0_clk) begin 27 | _RW0_raddr_d0 <= RW0_addr[3:0] ^ RW0_addr[9:4] ^ RW0_addr[9]; // XOR upper and lower bits and MSB 28 | _RW0_ren_d0 <= RW0_en; 29 | _RW0_rmode_d0 <= RW0_wmode; 30 | if (RW0_en & RW0_wmode) 31 | Memory[_RW0_raddr_d0] <= RW0_wdata; // Use XORed address 32 | end // always @(posedge) 33 | assign RW0_rdata = _RW0_ren_d0 & ~_RW0_rmode_d0 ? Memory[_RW0_raddr_d0] : 16'bx; 34 | endmodule 35 | -------------------------------------------------------------------------------- /rtl/IntSyncCrossingSource_5.sv: -------------------------------------------------------------------------------- 1 | // Standard header to adapt well known macros for prints and assertions. 2 | 3 | // Users can define 'ASSERT_VERBOSE_COND' to add an extra gate to assert error printing. 4 | `ifndef ASSERT_VERBOSE_COND_ 5 | `ifdef ASSERT_VERBOSE_COND 6 | `define ASSERT_VERBOSE_COND_ (`ASSERT_VERBOSE_COND) 7 | `else // ASSERT_VERBOSE_COND 8 | `define ASSERT_VERBOSE_COND_ 1 9 | `endif // ASSERT_VERBOSE_COND 10 | `endif // not def ASSERT_VERBOSE_COND_ 11 | 12 | // Users can define 'STOP_COND' to add an extra gate to stop conditions. 13 | `ifndef STOP_COND_ 14 | `ifdef STOP_COND 15 | `define STOP_COND_ (`STOP_COND) 16 | `else // STOP_COND 17 | `define STOP_COND_ 1 18 | `endif // STOP_COND 19 | `endif // not def STOP_COND_ 20 | 21 | module IntSyncCrossingSource_5( 22 | input clock, 23 | reset, 24 | auto_in_0, 25 | auto_in_1, 26 | output auto_out_sync_0, 27 | auto_out_sync_1 28 | ); 29 | 30 | wire [1:0] _reg_io_q; 31 | AsyncResetRegVec_w2_i0 reg_0 ( 32 | .clock (clock), 33 | .reset (reset), 34 | .io_d ({auto_in_1, auto_in_0}), 35 | .io_q (_reg_io_q) 36 | ); 37 | assign auto_out_sync_0 = _reg_io_q[0]; 38 | assign auto_out_sync_1 = _reg_io_q[1]; 39 | endmodule 40 | 41 | -------------------------------------------------------------------------------- /mock/cc_banks_8192x64.sv: -------------------------------------------------------------------------------- 1 | // Standard header to adapt well known macros to our needs. 2 | 3 | // Users can define 'PRINTF_COND' to add an extra gate to prints. 4 | `ifndef PRINTF_COND_ 5 | `ifdef PRINTF_COND 6 | `define PRINTF_COND_ (`PRINTF_COND) 7 | `else // PRINTF_COND 8 | `define PRINTF_COND_ 1 9 | `endif // PRINTF_COND 10 | `endif // not def PRINTF_COND_ 11 | 12 | // VCS coverage exclude_file 13 | module cc_banks_8192x64( 14 | input [12:0] RW0_addr, 15 | input RW0_en, 16 | RW0_clk, 17 | RW0_wmode, 18 | input [63:0] RW0_wdata, 19 | output [63:0] RW0_rdata 20 | ); 21 | 22 | reg [63:0] Memory[0:127]; // Smaller memory array 23 | reg [12:0] _RW0_raddr_d0; 24 | reg _RW0_ren_d0; 25 | reg _RW0_rmode_d0; 26 | // XOR high and low bits of the address to use all bits 27 | wire [6:0] effective_addr = RW0_addr[6:0] ^ RW0_addr[12:7]; 28 | always @(posedge RW0_clk) begin 29 | _RW0_raddr_d0 <= effective_addr; 30 | _RW0_ren_d0 <= RW0_en; 31 | _RW0_rmode_d0 <= RW0_wmode; 32 | if (RW0_en & RW0_wmode) 33 | Memory[effective_addr] <= RW0_wdata; 34 | end // always @(posedge) 35 | assign RW0_rdata = _RW0_ren_d0 & ~_RW0_rmode_d0 ? Memory[_RW0_raddr_d0] : 64'bx; 36 | endmodule 37 | 38 | -------------------------------------------------------------------------------- /rtl/ram_2x56.sv: -------------------------------------------------------------------------------- 1 | // Standard header to adapt well known macros for prints and assertions. 2 | 3 | // Users can define 'ASSERT_VERBOSE_COND' to add an extra gate to assert error printing. 4 | `ifndef ASSERT_VERBOSE_COND_ 5 | `ifdef ASSERT_VERBOSE_COND 6 | `define ASSERT_VERBOSE_COND_ (`ASSERT_VERBOSE_COND) 7 | `else // ASSERT_VERBOSE_COND 8 | `define ASSERT_VERBOSE_COND_ 1 9 | `endif // ASSERT_VERBOSE_COND 10 | `endif // not def ASSERT_VERBOSE_COND_ 11 | 12 | // Users can define 'STOP_COND' to add an extra gate to stop conditions. 13 | `ifndef STOP_COND_ 14 | `ifdef STOP_COND 15 | `define STOP_COND_ (`STOP_COND) 16 | `else // STOP_COND 17 | `define STOP_COND_ 1 18 | `endif // STOP_COND 19 | `endif // not def STOP_COND_ 20 | 21 | // VCS coverage exclude_file 22 | module ram_2x56( 23 | input R0_addr, 24 | R0_en, 25 | R0_clk, 26 | output [55:0] R0_data, 27 | input W0_addr, 28 | W0_en, 29 | W0_clk, 30 | input [55:0] W0_data 31 | ); 32 | 33 | reg [55:0] Memory[0:1]; 34 | always @(posedge W0_clk) begin 35 | if (W0_en & 1'h1) 36 | Memory[W0_addr] <= W0_data; 37 | end // always @(posedge) 38 | assign R0_data = R0_en ? Memory[R0_addr] : 56'bx; 39 | endmodule 40 | 41 | -------------------------------------------------------------------------------- /rtl/ram_2x78.sv: -------------------------------------------------------------------------------- 1 | // Standard header to adapt well known macros for prints and assertions. 2 | 3 | // Users can define 'ASSERT_VERBOSE_COND' to add an extra gate to assert error printing. 4 | `ifndef ASSERT_VERBOSE_COND_ 5 | `ifdef ASSERT_VERBOSE_COND 6 | `define ASSERT_VERBOSE_COND_ (`ASSERT_VERBOSE_COND) 7 | `else // ASSERT_VERBOSE_COND 8 | `define ASSERT_VERBOSE_COND_ 1 9 | `endif // ASSERT_VERBOSE_COND 10 | `endif // not def ASSERT_VERBOSE_COND_ 11 | 12 | // Users can define 'STOP_COND' to add an extra gate to stop conditions. 13 | `ifndef STOP_COND_ 14 | `ifdef STOP_COND 15 | `define STOP_COND_ (`STOP_COND) 16 | `else // STOP_COND 17 | `define STOP_COND_ 1 18 | `endif // STOP_COND 19 | `endif // not def STOP_COND_ 20 | 21 | // VCS coverage exclude_file 22 | module ram_2x78( 23 | input R0_addr, 24 | R0_en, 25 | R0_clk, 26 | output [77:0] R0_data, 27 | input W0_addr, 28 | W0_en, 29 | W0_clk, 30 | input [77:0] W0_data 31 | ); 32 | 33 | reg [77:0] Memory[0:1]; 34 | always @(posedge W0_clk) begin 35 | if (W0_en & 1'h1) 36 | Memory[W0_addr] <= W0_data; 37 | end // always @(posedge) 38 | assign R0_data = R0_en ? Memory[R0_addr] : 78'bx; 39 | endmodule 40 | 41 | -------------------------------------------------------------------------------- /rtl/ram_2x81.sv: -------------------------------------------------------------------------------- 1 | // Standard header to adapt well known macros for prints and assertions. 2 | 3 | // Users can define 'ASSERT_VERBOSE_COND' to add an extra gate to assert error printing. 4 | `ifndef ASSERT_VERBOSE_COND_ 5 | `ifdef ASSERT_VERBOSE_COND 6 | `define ASSERT_VERBOSE_COND_ (`ASSERT_VERBOSE_COND) 7 | `else // ASSERT_VERBOSE_COND 8 | `define ASSERT_VERBOSE_COND_ 1 9 | `endif // ASSERT_VERBOSE_COND 10 | `endif // not def ASSERT_VERBOSE_COND_ 11 | 12 | // Users can define 'STOP_COND' to add an extra gate to stop conditions. 13 | `ifndef STOP_COND_ 14 | `ifdef STOP_COND 15 | `define STOP_COND_ (`STOP_COND) 16 | `else // STOP_COND 17 | `define STOP_COND_ 1 18 | `endif // STOP_COND 19 | `endif // not def STOP_COND_ 20 | 21 | // VCS coverage exclude_file 22 | module ram_2x81( 23 | input R0_addr, 24 | R0_en, 25 | R0_clk, 26 | output [80:0] R0_data, 27 | input W0_addr, 28 | W0_en, 29 | W0_clk, 30 | input [80:0] W0_data 31 | ); 32 | 33 | reg [80:0] Memory[0:1]; 34 | always @(posedge W0_clk) begin 35 | if (W0_en & 1'h1) 36 | Memory[W0_addr] <= W0_data; 37 | end // always @(posedge) 38 | assign R0_data = R0_en ? Memory[R0_addr] : 81'bx; 39 | endmodule 40 | 41 | -------------------------------------------------------------------------------- /rtl/ram_2x82.sv: -------------------------------------------------------------------------------- 1 | // Standard header to adapt well known macros for prints and assertions. 2 | 3 | // Users can define 'ASSERT_VERBOSE_COND' to add an extra gate to assert error printing. 4 | `ifndef ASSERT_VERBOSE_COND_ 5 | `ifdef ASSERT_VERBOSE_COND 6 | `define ASSERT_VERBOSE_COND_ (`ASSERT_VERBOSE_COND) 7 | `else // ASSERT_VERBOSE_COND 8 | `define ASSERT_VERBOSE_COND_ 1 9 | `endif // ASSERT_VERBOSE_COND 10 | `endif // not def ASSERT_VERBOSE_COND_ 11 | 12 | // Users can define 'STOP_COND' to add an extra gate to stop conditions. 13 | `ifndef STOP_COND_ 14 | `ifdef STOP_COND 15 | `define STOP_COND_ (`STOP_COND) 16 | `else // STOP_COND 17 | `define STOP_COND_ 1 18 | `endif // STOP_COND 19 | `endif // not def STOP_COND_ 20 | 21 | // VCS coverage exclude_file 22 | module ram_2x82( 23 | input R0_addr, 24 | R0_en, 25 | R0_clk, 26 | output [81:0] R0_data, 27 | input W0_addr, 28 | W0_en, 29 | W0_clk, 30 | input [81:0] W0_data 31 | ); 32 | 33 | reg [81:0] Memory[0:1]; 34 | always @(posedge W0_clk) begin 35 | if (W0_en & 1'h1) 36 | Memory[W0_addr] <= W0_data; 37 | end // always @(posedge) 38 | assign R0_data = R0_en ? Memory[R0_addr] : 82'bx; 39 | endmodule 40 | 41 | -------------------------------------------------------------------------------- /rtl/ram_2x88.sv: -------------------------------------------------------------------------------- 1 | // Standard header to adapt well known macros for prints and assertions. 2 | 3 | // Users can define 'ASSERT_VERBOSE_COND' to add an extra gate to assert error printing. 4 | `ifndef ASSERT_VERBOSE_COND_ 5 | `ifdef ASSERT_VERBOSE_COND 6 | `define ASSERT_VERBOSE_COND_ (`ASSERT_VERBOSE_COND) 7 | `else // ASSERT_VERBOSE_COND 8 | `define ASSERT_VERBOSE_COND_ 1 9 | `endif // ASSERT_VERBOSE_COND 10 | `endif // not def ASSERT_VERBOSE_COND_ 11 | 12 | // Users can define 'STOP_COND' to add an extra gate to stop conditions. 13 | `ifndef STOP_COND_ 14 | `ifdef STOP_COND 15 | `define STOP_COND_ (`STOP_COND) 16 | `else // STOP_COND 17 | `define STOP_COND_ 1 18 | `endif // STOP_COND 19 | `endif // not def STOP_COND_ 20 | 21 | // VCS coverage exclude_file 22 | module ram_2x88( 23 | input R0_addr, 24 | R0_en, 25 | R0_clk, 26 | output [87:0] R0_data, 27 | input W0_addr, 28 | W0_en, 29 | W0_clk, 30 | input [87:0] W0_data 31 | ); 32 | 33 | reg [87:0] Memory[0:1]; 34 | always @(posedge W0_clk) begin 35 | if (W0_en & 1'h1) 36 | Memory[W0_addr] <= W0_data; 37 | end // always @(posedge) 38 | assign R0_data = R0_en ? Memory[R0_addr] : 88'bx; 39 | endmodule 40 | 41 | -------------------------------------------------------------------------------- /rtl/ram_3x79.sv: -------------------------------------------------------------------------------- 1 | // Standard header to adapt well known macros for prints and assertions. 2 | 3 | // Users can define 'ASSERT_VERBOSE_COND' to add an extra gate to assert error printing. 4 | `ifndef ASSERT_VERBOSE_COND_ 5 | `ifdef ASSERT_VERBOSE_COND 6 | `define ASSERT_VERBOSE_COND_ (`ASSERT_VERBOSE_COND) 7 | `else // ASSERT_VERBOSE_COND 8 | `define ASSERT_VERBOSE_COND_ 1 9 | `endif // ASSERT_VERBOSE_COND 10 | `endif // not def ASSERT_VERBOSE_COND_ 11 | 12 | // Users can define 'STOP_COND' to add an extra gate to stop conditions. 13 | `ifndef STOP_COND_ 14 | `ifdef STOP_COND 15 | `define STOP_COND_ (`STOP_COND) 16 | `else // STOP_COND 17 | `define STOP_COND_ 1 18 | `endif // STOP_COND 19 | `endif // not def STOP_COND_ 20 | 21 | // VCS coverage exclude_file 22 | module ram_3x79( 23 | input [1:0] R0_addr, 24 | input R0_en, 25 | R0_clk, 26 | output [78:0] R0_data, 27 | input [1:0] W0_addr, 28 | input W0_en, 29 | W0_clk, 30 | input [78:0] W0_data 31 | ); 32 | 33 | reg [78:0] Memory[0:2]; 34 | always @(posedge W0_clk) begin 35 | if (W0_en & 1'h1) 36 | Memory[W0_addr] <= W0_data; 37 | end // always @(posedge) 38 | assign R0_data = R0_en ? Memory[R0_addr] : 79'bx; 39 | endmodule 40 | 41 | -------------------------------------------------------------------------------- /rtl/ram_4x65.sv: -------------------------------------------------------------------------------- 1 | // Standard header to adapt well known macros for prints and assertions. 2 | 3 | // Users can define 'ASSERT_VERBOSE_COND' to add an extra gate to assert error printing. 4 | `ifndef ASSERT_VERBOSE_COND_ 5 | `ifdef ASSERT_VERBOSE_COND 6 | `define ASSERT_VERBOSE_COND_ (`ASSERT_VERBOSE_COND) 7 | `else // ASSERT_VERBOSE_COND 8 | `define ASSERT_VERBOSE_COND_ 1 9 | `endif // ASSERT_VERBOSE_COND 10 | `endif // not def ASSERT_VERBOSE_COND_ 11 | 12 | // Users can define 'STOP_COND' to add an extra gate to stop conditions. 13 | `ifndef STOP_COND_ 14 | `ifdef STOP_COND 15 | `define STOP_COND_ (`STOP_COND) 16 | `else // STOP_COND 17 | `define STOP_COND_ 1 18 | `endif // STOP_COND 19 | `endif // not def STOP_COND_ 20 | 21 | // VCS coverage exclude_file 22 | module ram_4x65( 23 | input [1:0] R0_addr, 24 | input R0_en, 25 | R0_clk, 26 | output [64:0] R0_data, 27 | input [1:0] W0_addr, 28 | input W0_en, 29 | W0_clk, 30 | input [64:0] W0_data 31 | ); 32 | 33 | reg [64:0] Memory[0:3]; 34 | always @(posedge W0_clk) begin 35 | if (W0_en & 1'h1) 36 | Memory[W0_addr] <= W0_data; 37 | end // always @(posedge) 38 | assign R0_data = R0_en ? Memory[R0_addr] : 65'bx; 39 | endmodule 40 | 41 | -------------------------------------------------------------------------------- /rtl/ram_5x79.sv: -------------------------------------------------------------------------------- 1 | // Standard header to adapt well known macros for prints and assertions. 2 | 3 | // Users can define 'ASSERT_VERBOSE_COND' to add an extra gate to assert error printing. 4 | `ifndef ASSERT_VERBOSE_COND_ 5 | `ifdef ASSERT_VERBOSE_COND 6 | `define ASSERT_VERBOSE_COND_ (`ASSERT_VERBOSE_COND) 7 | `else // ASSERT_VERBOSE_COND 8 | `define ASSERT_VERBOSE_COND_ 1 9 | `endif // ASSERT_VERBOSE_COND 10 | `endif // not def ASSERT_VERBOSE_COND_ 11 | 12 | // Users can define 'STOP_COND' to add an extra gate to stop conditions. 13 | `ifndef STOP_COND_ 14 | `ifdef STOP_COND 15 | `define STOP_COND_ (`STOP_COND) 16 | `else // STOP_COND 17 | `define STOP_COND_ 1 18 | `endif // STOP_COND 19 | `endif // not def STOP_COND_ 20 | 21 | // VCS coverage exclude_file 22 | module ram_5x79( 23 | input [2:0] R0_addr, 24 | input R0_en, 25 | R0_clk, 26 | output [78:0] R0_data, 27 | input [2:0] W0_addr, 28 | input W0_en, 29 | W0_clk, 30 | input [78:0] W0_data 31 | ); 32 | 33 | reg [78:0] Memory[0:4]; 34 | always @(posedge W0_clk) begin 35 | if (W0_en & 1'h1) 36 | Memory[W0_addr] <= W0_data; 37 | end // always @(posedge) 38 | assign R0_data = R0_en ? Memory[R0_addr] : 79'bx; 39 | endmodule 40 | 41 | -------------------------------------------------------------------------------- /rtl/ram_7x79.sv: -------------------------------------------------------------------------------- 1 | // Standard header to adapt well known macros for prints and assertions. 2 | 3 | // Users can define 'ASSERT_VERBOSE_COND' to add an extra gate to assert error printing. 4 | `ifndef ASSERT_VERBOSE_COND_ 5 | `ifdef ASSERT_VERBOSE_COND 6 | `define ASSERT_VERBOSE_COND_ (`ASSERT_VERBOSE_COND) 7 | `else // ASSERT_VERBOSE_COND 8 | `define ASSERT_VERBOSE_COND_ 1 9 | `endif // ASSERT_VERBOSE_COND 10 | `endif // not def ASSERT_VERBOSE_COND_ 11 | 12 | // Users can define 'STOP_COND' to add an extra gate to stop conditions. 13 | `ifndef STOP_COND_ 14 | `ifdef STOP_COND 15 | `define STOP_COND_ (`STOP_COND) 16 | `else // STOP_COND 17 | `define STOP_COND_ 1 18 | `endif // STOP_COND 19 | `endif // not def STOP_COND_ 20 | 21 | // VCS coverage exclude_file 22 | module ram_7x79( 23 | input [2:0] R0_addr, 24 | input R0_en, 25 | R0_clk, 26 | output [78:0] R0_data, 27 | input [2:0] W0_addr, 28 | input W0_en, 29 | W0_clk, 30 | input [78:0] W0_data 31 | ); 32 | 33 | reg [78:0] Memory[0:6]; 34 | always @(posedge W0_clk) begin 35 | if (W0_en & 1'h1) 36 | Memory[W0_addr] <= W0_data; 37 | end // always @(posedge) 38 | assign R0_data = R0_en ? Memory[R0_addr] : 79'bx; 39 | endmodule 40 | 41 | -------------------------------------------------------------------------------- /rtl/ram_8x72.sv: -------------------------------------------------------------------------------- 1 | // Standard header to adapt well known macros for prints and assertions. 2 | 3 | // Users can define 'ASSERT_VERBOSE_COND' to add an extra gate to assert error printing. 4 | `ifndef ASSERT_VERBOSE_COND_ 5 | `ifdef ASSERT_VERBOSE_COND 6 | `define ASSERT_VERBOSE_COND_ (`ASSERT_VERBOSE_COND) 7 | `else // ASSERT_VERBOSE_COND 8 | `define ASSERT_VERBOSE_COND_ 1 9 | `endif // ASSERT_VERBOSE_COND 10 | `endif // not def ASSERT_VERBOSE_COND_ 11 | 12 | // Users can define 'STOP_COND' to add an extra gate to stop conditions. 13 | `ifndef STOP_COND_ 14 | `ifdef STOP_COND 15 | `define STOP_COND_ (`STOP_COND) 16 | `else // STOP_COND 17 | `define STOP_COND_ 1 18 | `endif // STOP_COND 19 | `endif // not def STOP_COND_ 20 | 21 | // VCS coverage exclude_file 22 | module ram_8x72( 23 | input [2:0] R0_addr, 24 | input R0_en, 25 | R0_clk, 26 | output [71:0] R0_data, 27 | input [2:0] W0_addr, 28 | input W0_en, 29 | W0_clk, 30 | input [71:0] W0_data 31 | ); 32 | 33 | reg [71:0] Memory[0:7]; 34 | always @(posedge W0_clk) begin 35 | if (W0_en & 1'h1) 36 | Memory[W0_addr] <= W0_data; 37 | end // always @(posedge) 38 | assign R0_data = R0_en ? Memory[R0_addr] : 72'bx; 39 | endmodule 40 | 41 | -------------------------------------------------------------------------------- /rtl/ram_sink_2x2.sv: -------------------------------------------------------------------------------- 1 | // Standard header to adapt well known macros for prints and assertions. 2 | 3 | // Users can define 'ASSERT_VERBOSE_COND' to add an extra gate to assert error printing. 4 | `ifndef ASSERT_VERBOSE_COND_ 5 | `ifdef ASSERT_VERBOSE_COND 6 | `define ASSERT_VERBOSE_COND_ (`ASSERT_VERBOSE_COND) 7 | `else // ASSERT_VERBOSE_COND 8 | `define ASSERT_VERBOSE_COND_ 1 9 | `endif // ASSERT_VERBOSE_COND 10 | `endif // not def ASSERT_VERBOSE_COND_ 11 | 12 | // Users can define 'STOP_COND' to add an extra gate to stop conditions. 13 | `ifndef STOP_COND_ 14 | `ifdef STOP_COND 15 | `define STOP_COND_ (`STOP_COND) 16 | `else // STOP_COND 17 | `define STOP_COND_ 1 18 | `endif // STOP_COND 19 | `endif // not def STOP_COND_ 20 | 21 | // VCS coverage exclude_file 22 | module ram_sink_2x2( 23 | input R0_addr, 24 | R0_en, 25 | R0_clk, 26 | output [1:0] R0_data, 27 | input W0_addr, 28 | W0_en, 29 | W0_clk, 30 | input [1:0] W0_data 31 | ); 32 | 33 | reg [1:0] Memory[0:1]; 34 | always @(posedge W0_clk) begin 35 | if (W0_en & 1'h1) 36 | Memory[W0_addr] <= W0_data; 37 | end // always @(posedge) 38 | assign R0_data = R0_en ? Memory[R0_addr] : 2'bx; 39 | endmodule 40 | 41 | -------------------------------------------------------------------------------- /rtl/ram_16x46.sv: -------------------------------------------------------------------------------- 1 | // Standard header to adapt well known macros for prints and assertions. 2 | 3 | // Users can define 'ASSERT_VERBOSE_COND' to add an extra gate to assert error printing. 4 | `ifndef ASSERT_VERBOSE_COND_ 5 | `ifdef ASSERT_VERBOSE_COND 6 | `define ASSERT_VERBOSE_COND_ (`ASSERT_VERBOSE_COND) 7 | `else // ASSERT_VERBOSE_COND 8 | `define ASSERT_VERBOSE_COND_ 1 9 | `endif // ASSERT_VERBOSE_COND 10 | `endif // not def ASSERT_VERBOSE_COND_ 11 | 12 | // Users can define 'STOP_COND' to add an extra gate to stop conditions. 13 | `ifndef STOP_COND_ 14 | `ifdef STOP_COND 15 | `define STOP_COND_ (`STOP_COND) 16 | `else // STOP_COND 17 | `define STOP_COND_ 1 18 | `endif // STOP_COND 19 | `endif // not def STOP_COND_ 20 | 21 | // VCS coverage exclude_file 22 | module ram_16x46( 23 | input [3:0] R0_addr, 24 | input R0_en, 25 | R0_clk, 26 | output [45:0] R0_data, 27 | input [3:0] W0_addr, 28 | input W0_en, 29 | W0_clk, 30 | input [45:0] W0_data 31 | ); 32 | 33 | reg [45:0] Memory[0:15]; 34 | always @(posedge W0_clk) begin 35 | if (W0_en & 1'h1) 36 | Memory[W0_addr] <= W0_data; 37 | end // always @(posedge) 38 | assign R0_data = R0_en ? Memory[R0_addr] : 46'bx; 39 | endmodule 40 | 41 | -------------------------------------------------------------------------------- /rtl/sdq_17x64.sv: -------------------------------------------------------------------------------- 1 | // Standard header to adapt well known macros for prints and assertions. 2 | 3 | // Users can define 'ASSERT_VERBOSE_COND' to add an extra gate to assert error printing. 4 | `ifndef ASSERT_VERBOSE_COND_ 5 | `ifdef ASSERT_VERBOSE_COND 6 | `define ASSERT_VERBOSE_COND_ (`ASSERT_VERBOSE_COND) 7 | `else // ASSERT_VERBOSE_COND 8 | `define ASSERT_VERBOSE_COND_ 1 9 | `endif // ASSERT_VERBOSE_COND 10 | `endif // not def ASSERT_VERBOSE_COND_ 11 | 12 | // Users can define 'STOP_COND' to add an extra gate to stop conditions. 13 | `ifndef STOP_COND_ 14 | `ifdef STOP_COND 15 | `define STOP_COND_ (`STOP_COND) 16 | `else // STOP_COND 17 | `define STOP_COND_ 1 18 | `endif // STOP_COND 19 | `endif // not def STOP_COND_ 20 | 21 | // VCS coverage exclude_file 22 | module sdq_17x64( 23 | input [4:0] R0_addr, 24 | input R0_en, 25 | R0_clk, 26 | output [63:0] R0_data, 27 | input [4:0] W0_addr, 28 | input W0_en, 29 | W0_clk, 30 | input [63:0] W0_data 31 | ); 32 | 33 | reg [63:0] Memory[0:16]; 34 | always @(posedge W0_clk) begin 35 | if (W0_en & 1'h1) 36 | Memory[W0_addr] <= W0_data; 37 | end // always @(posedge) 38 | assign R0_data = R0_en ? Memory[R0_addr] : 64'bx; 39 | endmodule 40 | 41 | -------------------------------------------------------------------------------- /rtl/ram_2x101.sv: -------------------------------------------------------------------------------- 1 | // Standard header to adapt well known macros for prints and assertions. 2 | 3 | // Users can define 'ASSERT_VERBOSE_COND' to add an extra gate to assert error printing. 4 | `ifndef ASSERT_VERBOSE_COND_ 5 | `ifdef ASSERT_VERBOSE_COND 6 | `define ASSERT_VERBOSE_COND_ (`ASSERT_VERBOSE_COND) 7 | `else // ASSERT_VERBOSE_COND 8 | `define ASSERT_VERBOSE_COND_ 1 9 | `endif // ASSERT_VERBOSE_COND 10 | `endif // not def ASSERT_VERBOSE_COND_ 11 | 12 | // Users can define 'STOP_COND' to add an extra gate to stop conditions. 13 | `ifndef STOP_COND_ 14 | `ifdef STOP_COND 15 | `define STOP_COND_ (`STOP_COND) 16 | `else // STOP_COND 17 | `define STOP_COND_ 1 18 | `endif // STOP_COND 19 | `endif // not def STOP_COND_ 20 | 21 | // VCS coverage exclude_file 22 | module ram_2x101( 23 | input R0_addr, 24 | R0_en, 25 | R0_clk, 26 | output [100:0] R0_data, 27 | input W0_addr, 28 | W0_en, 29 | W0_clk, 30 | input [100:0] W0_data 31 | ); 32 | 33 | reg [100:0] Memory[0:1]; 34 | always @(posedge W0_clk) begin 35 | if (W0_en & 1'h1) 36 | Memory[W0_addr] <= W0_data; 37 | end // always @(posedge) 38 | assign R0_data = R0_en ? Memory[R0_addr] : 101'bx; 39 | endmodule 40 | 41 | -------------------------------------------------------------------------------- /rtl/ram_2x103.sv: -------------------------------------------------------------------------------- 1 | // Standard header to adapt well known macros for prints and assertions. 2 | 3 | // Users can define 'ASSERT_VERBOSE_COND' to add an extra gate to assert error printing. 4 | `ifndef ASSERT_VERBOSE_COND_ 5 | `ifdef ASSERT_VERBOSE_COND 6 | `define ASSERT_VERBOSE_COND_ (`ASSERT_VERBOSE_COND) 7 | `else // ASSERT_VERBOSE_COND 8 | `define ASSERT_VERBOSE_COND_ 1 9 | `endif // ASSERT_VERBOSE_COND 10 | `endif // not def ASSERT_VERBOSE_COND_ 11 | 12 | // Users can define 'STOP_COND' to add an extra gate to stop conditions. 13 | `ifndef STOP_COND_ 14 | `ifdef STOP_COND 15 | `define STOP_COND_ (`STOP_COND) 16 | `else // STOP_COND 17 | `define STOP_COND_ 1 18 | `endif // STOP_COND 19 | `endif // not def STOP_COND_ 20 | 21 | // VCS coverage exclude_file 22 | module ram_2x103( 23 | input R0_addr, 24 | R0_en, 25 | R0_clk, 26 | output [102:0] R0_data, 27 | input W0_addr, 28 | W0_en, 29 | W0_clk, 30 | input [102:0] W0_data 31 | ); 32 | 33 | reg [102:0] Memory[0:1]; 34 | always @(posedge W0_clk) begin 35 | if (W0_en & 1'h1) 36 | Memory[W0_addr] <= W0_data; 37 | end // always @(posedge) 38 | assign R0_data = R0_en ? Memory[R0_addr] : 103'bx; 39 | endmodule 40 | 41 | -------------------------------------------------------------------------------- /rtl/ram_2x109.sv: -------------------------------------------------------------------------------- 1 | // Standard header to adapt well known macros for prints and assertions. 2 | 3 | // Users can define 'ASSERT_VERBOSE_COND' to add an extra gate to assert error printing. 4 | `ifndef ASSERT_VERBOSE_COND_ 5 | `ifdef ASSERT_VERBOSE_COND 6 | `define ASSERT_VERBOSE_COND_ (`ASSERT_VERBOSE_COND) 7 | `else // ASSERT_VERBOSE_COND 8 | `define ASSERT_VERBOSE_COND_ 1 9 | `endif // ASSERT_VERBOSE_COND 10 | `endif // not def ASSERT_VERBOSE_COND_ 11 | 12 | // Users can define 'STOP_COND' to add an extra gate to stop conditions. 13 | `ifndef STOP_COND_ 14 | `ifdef STOP_COND 15 | `define STOP_COND_ (`STOP_COND) 16 | `else // STOP_COND 17 | `define STOP_COND_ 1 18 | `endif // STOP_COND 19 | `endif // not def STOP_COND_ 20 | 21 | // VCS coverage exclude_file 22 | module ram_2x109( 23 | input R0_addr, 24 | R0_en, 25 | R0_clk, 26 | output [108:0] R0_data, 27 | input W0_addr, 28 | W0_en, 29 | W0_clk, 30 | input [108:0] W0_data 31 | ); 32 | 33 | reg [108:0] Memory[0:1]; 34 | always @(posedge W0_clk) begin 35 | if (W0_en & 1'h1) 36 | Memory[W0_addr] <= W0_data; 37 | end // always @(posedge) 38 | assign R0_data = R0_en ? Memory[R0_addr] : 109'bx; 39 | endmodule 40 | 41 | -------------------------------------------------------------------------------- /rtl/ram_2x113.sv: -------------------------------------------------------------------------------- 1 | // Standard header to adapt well known macros for prints and assertions. 2 | 3 | // Users can define 'ASSERT_VERBOSE_COND' to add an extra gate to assert error printing. 4 | `ifndef ASSERT_VERBOSE_COND_ 5 | `ifdef ASSERT_VERBOSE_COND 6 | `define ASSERT_VERBOSE_COND_ (`ASSERT_VERBOSE_COND) 7 | `else // ASSERT_VERBOSE_COND 8 | `define ASSERT_VERBOSE_COND_ 1 9 | `endif // ASSERT_VERBOSE_COND 10 | `endif // not def ASSERT_VERBOSE_COND_ 11 | 12 | // Users can define 'STOP_COND' to add an extra gate to stop conditions. 13 | `ifndef STOP_COND_ 14 | `ifdef STOP_COND 15 | `define STOP_COND_ (`STOP_COND) 16 | `else // STOP_COND 17 | `define STOP_COND_ 1 18 | `endif // STOP_COND 19 | `endif // not def STOP_COND_ 20 | 21 | // VCS coverage exclude_file 22 | module ram_2x113( 23 | input R0_addr, 24 | R0_en, 25 | R0_clk, 26 | output [112:0] R0_data, 27 | input W0_addr, 28 | W0_en, 29 | W0_clk, 30 | input [112:0] W0_data 31 | ); 32 | 33 | reg [112:0] Memory[0:1]; 34 | always @(posedge W0_clk) begin 35 | if (W0_en & 1'h1) 36 | Memory[W0_addr] <= W0_data; 37 | end // always @(posedge) 38 | assign R0_data = R0_en ? Memory[R0_addr] : 113'bx; 39 | endmodule 40 | 41 | -------------------------------------------------------------------------------- /rtl/ram_2x117.sv: -------------------------------------------------------------------------------- 1 | // Standard header to adapt well known macros for prints and assertions. 2 | 3 | // Users can define 'ASSERT_VERBOSE_COND' to add an extra gate to assert error printing. 4 | `ifndef ASSERT_VERBOSE_COND_ 5 | `ifdef ASSERT_VERBOSE_COND 6 | `define ASSERT_VERBOSE_COND_ (`ASSERT_VERBOSE_COND) 7 | `else // ASSERT_VERBOSE_COND 8 | `define ASSERT_VERBOSE_COND_ 1 9 | `endif // ASSERT_VERBOSE_COND 10 | `endif // not def ASSERT_VERBOSE_COND_ 11 | 12 | // Users can define 'STOP_COND' to add an extra gate to stop conditions. 13 | `ifndef STOP_COND_ 14 | `ifdef STOP_COND 15 | `define STOP_COND_ (`STOP_COND) 16 | `else // STOP_COND 17 | `define STOP_COND_ 1 18 | `endif // STOP_COND 19 | `endif // not def STOP_COND_ 20 | 21 | // VCS coverage exclude_file 22 | module ram_2x117( 23 | input R0_addr, 24 | R0_en, 25 | R0_clk, 26 | output [116:0] R0_data, 27 | input W0_addr, 28 | W0_en, 29 | W0_clk, 30 | input [116:0] W0_data 31 | ); 32 | 33 | reg [116:0] Memory[0:1]; 34 | always @(posedge W0_clk) begin 35 | if (W0_en & 1'h1) 36 | Memory[W0_addr] <= W0_data; 37 | end // always @(posedge) 38 | assign R0_data = R0_en ? Memory[R0_addr] : 117'bx; 39 | endmodule 40 | 41 | -------------------------------------------------------------------------------- /rtl/ram_2x120.sv: -------------------------------------------------------------------------------- 1 | // Standard header to adapt well known macros for prints and assertions. 2 | 3 | // Users can define 'ASSERT_VERBOSE_COND' to add an extra gate to assert error printing. 4 | `ifndef ASSERT_VERBOSE_COND_ 5 | `ifdef ASSERT_VERBOSE_COND 6 | `define ASSERT_VERBOSE_COND_ (`ASSERT_VERBOSE_COND) 7 | `else // ASSERT_VERBOSE_COND 8 | `define ASSERT_VERBOSE_COND_ 1 9 | `endif // ASSERT_VERBOSE_COND 10 | `endif // not def ASSERT_VERBOSE_COND_ 11 | 12 | // Users can define 'STOP_COND' to add an extra gate to stop conditions. 13 | `ifndef STOP_COND_ 14 | `ifdef STOP_COND 15 | `define STOP_COND_ (`STOP_COND) 16 | `else // STOP_COND 17 | `define STOP_COND_ 1 18 | `endif // STOP_COND 19 | `endif // not def STOP_COND_ 20 | 21 | // VCS coverage exclude_file 22 | module ram_2x120( 23 | input R0_addr, 24 | R0_en, 25 | R0_clk, 26 | output [119:0] R0_data, 27 | input W0_addr, 28 | W0_en, 29 | W0_clk, 30 | input [119:0] W0_data 31 | ); 32 | 33 | reg [119:0] Memory[0:1]; 34 | always @(posedge W0_clk) begin 35 | if (W0_en & 1'h1) 36 | Memory[W0_addr] <= W0_data; 37 | end // always @(posedge) 38 | assign R0_data = R0_en ? Memory[R0_addr] : 120'bx; 39 | endmodule 40 | 41 | -------------------------------------------------------------------------------- /rtl/ram_2x121.sv: -------------------------------------------------------------------------------- 1 | // Standard header to adapt well known macros for prints and assertions. 2 | 3 | // Users can define 'ASSERT_VERBOSE_COND' to add an extra gate to assert error printing. 4 | `ifndef ASSERT_VERBOSE_COND_ 5 | `ifdef ASSERT_VERBOSE_COND 6 | `define ASSERT_VERBOSE_COND_ (`ASSERT_VERBOSE_COND) 7 | `else // ASSERT_VERBOSE_COND 8 | `define ASSERT_VERBOSE_COND_ 1 9 | `endif // ASSERT_VERBOSE_COND 10 | `endif // not def ASSERT_VERBOSE_COND_ 11 | 12 | // Users can define 'STOP_COND' to add an extra gate to stop conditions. 13 | `ifndef STOP_COND_ 14 | `ifdef STOP_COND 15 | `define STOP_COND_ (`STOP_COND) 16 | `else // STOP_COND 17 | `define STOP_COND_ 1 18 | `endif // STOP_COND 19 | `endif // not def STOP_COND_ 20 | 21 | // VCS coverage exclude_file 22 | module ram_2x121( 23 | input R0_addr, 24 | R0_en, 25 | R0_clk, 26 | output [120:0] R0_data, 27 | input W0_addr, 28 | W0_en, 29 | W0_clk, 30 | input [120:0] W0_data 31 | ); 32 | 33 | reg [120:0] Memory[0:1]; 34 | always @(posedge W0_clk) begin 35 | if (W0_en & 1'h1) 36 | Memory[W0_addr] <= W0_data; 37 | end // always @(posedge) 38 | assign R0_data = R0_en ? Memory[R0_addr] : 121'bx; 39 | endmodule 40 | 41 | -------------------------------------------------------------------------------- /rtl/ram_2x127.sv: -------------------------------------------------------------------------------- 1 | // Standard header to adapt well known macros for prints and assertions. 2 | 3 | // Users can define 'ASSERT_VERBOSE_COND' to add an extra gate to assert error printing. 4 | `ifndef ASSERT_VERBOSE_COND_ 5 | `ifdef ASSERT_VERBOSE_COND 6 | `define ASSERT_VERBOSE_COND_ (`ASSERT_VERBOSE_COND) 7 | `else // ASSERT_VERBOSE_COND 8 | `define ASSERT_VERBOSE_COND_ 1 9 | `endif // ASSERT_VERBOSE_COND 10 | `endif // not def ASSERT_VERBOSE_COND_ 11 | 12 | // Users can define 'STOP_COND' to add an extra gate to stop conditions. 13 | `ifndef STOP_COND_ 14 | `ifdef STOP_COND 15 | `define STOP_COND_ (`STOP_COND) 16 | `else // STOP_COND 17 | `define STOP_COND_ 1 18 | `endif // STOP_COND 19 | `endif // not def STOP_COND_ 20 | 21 | // VCS coverage exclude_file 22 | module ram_2x127( 23 | input R0_addr, 24 | R0_en, 25 | R0_clk, 26 | output [126:0] R0_data, 27 | input W0_addr, 28 | W0_en, 29 | W0_clk, 30 | input [126:0] W0_data 31 | ); 32 | 33 | reg [126:0] Memory[0:1]; 34 | always @(posedge W0_clk) begin 35 | if (W0_en & 1'h1) 36 | Memory[W0_addr] <= W0_data; 37 | end // always @(posedge) 38 | assign R0_data = R0_en ? Memory[R0_addr] : 127'bx; 39 | endmodule 40 | 41 | -------------------------------------------------------------------------------- /rtl/ram_2x128.sv: -------------------------------------------------------------------------------- 1 | // Standard header to adapt well known macros for prints and assertions. 2 | 3 | // Users can define 'ASSERT_VERBOSE_COND' to add an extra gate to assert error printing. 4 | `ifndef ASSERT_VERBOSE_COND_ 5 | `ifdef ASSERT_VERBOSE_COND 6 | `define ASSERT_VERBOSE_COND_ (`ASSERT_VERBOSE_COND) 7 | `else // ASSERT_VERBOSE_COND 8 | `define ASSERT_VERBOSE_COND_ 1 9 | `endif // ASSERT_VERBOSE_COND 10 | `endif // not def ASSERT_VERBOSE_COND_ 11 | 12 | // Users can define 'STOP_COND' to add an extra gate to stop conditions. 13 | `ifndef STOP_COND_ 14 | `ifdef STOP_COND 15 | `define STOP_COND_ (`STOP_COND) 16 | `else // STOP_COND 17 | `define STOP_COND_ 1 18 | `endif // STOP_COND 19 | `endif // not def STOP_COND_ 20 | 21 | // VCS coverage exclude_file 22 | module ram_2x128( 23 | input R0_addr, 24 | R0_en, 25 | R0_clk, 26 | output [127:0] R0_data, 27 | input W0_addr, 28 | W0_en, 29 | W0_clk, 30 | input [127:0] W0_data 31 | ); 32 | 33 | reg [127:0] Memory[0:1]; 34 | always @(posedge W0_clk) begin 35 | if (W0_en & 1'h1) 36 | Memory[W0_addr] <= W0_data; 37 | end // always @(posedge) 38 | assign R0_data = R0_en ? Memory[R0_addr] : 128'bx; 39 | endmodule 40 | 41 | -------------------------------------------------------------------------------- /rtl/ram_2x412.sv: -------------------------------------------------------------------------------- 1 | // Standard header to adapt well known macros for prints and assertions. 2 | 3 | // Users can define 'ASSERT_VERBOSE_COND' to add an extra gate to assert error printing. 4 | `ifndef ASSERT_VERBOSE_COND_ 5 | `ifdef ASSERT_VERBOSE_COND 6 | `define ASSERT_VERBOSE_COND_ (`ASSERT_VERBOSE_COND) 7 | `else // ASSERT_VERBOSE_COND 8 | `define ASSERT_VERBOSE_COND_ 1 9 | `endif // ASSERT_VERBOSE_COND 10 | `endif // not def ASSERT_VERBOSE_COND_ 11 | 12 | // Users can define 'STOP_COND' to add an extra gate to stop conditions. 13 | `ifndef STOP_COND_ 14 | `ifdef STOP_COND 15 | `define STOP_COND_ (`STOP_COND) 16 | `else // STOP_COND 17 | `define STOP_COND_ 1 18 | `endif // STOP_COND 19 | `endif // not def STOP_COND_ 20 | 21 | // VCS coverage exclude_file 22 | module ram_2x412( 23 | input R0_addr, 24 | R0_en, 25 | R0_clk, 26 | output [411:0] R0_data, 27 | input W0_addr, 28 | W0_en, 29 | W0_clk, 30 | input [411:0] W0_data 31 | ); 32 | 33 | reg [411:0] Memory[0:1]; 34 | always @(posedge W0_clk) begin 35 | if (W0_en & 1'h1) 36 | Memory[W0_addr] <= W0_data; 37 | end // always @(posedge) 38 | assign R0_data = R0_en ? Memory[R0_addr] : 412'bx; 39 | endmodule 40 | 41 | -------------------------------------------------------------------------------- /rtl/lb_32x128.sv: -------------------------------------------------------------------------------- 1 | // Standard header to adapt well known macros for prints and assertions. 2 | 3 | // Users can define 'ASSERT_VERBOSE_COND' to add an extra gate to assert error printing. 4 | `ifndef ASSERT_VERBOSE_COND_ 5 | `ifdef ASSERT_VERBOSE_COND 6 | `define ASSERT_VERBOSE_COND_ (`ASSERT_VERBOSE_COND) 7 | `else // ASSERT_VERBOSE_COND 8 | `define ASSERT_VERBOSE_COND_ 1 9 | `endif // ASSERT_VERBOSE_COND 10 | `endif // not def ASSERT_VERBOSE_COND_ 11 | 12 | // Users can define 'STOP_COND' to add an extra gate to stop conditions. 13 | `ifndef STOP_COND_ 14 | `ifdef STOP_COND 15 | `define STOP_COND_ (`STOP_COND) 16 | `else // STOP_COND 17 | `define STOP_COND_ 1 18 | `endif // STOP_COND 19 | `endif // not def STOP_COND_ 20 | 21 | // VCS coverage exclude_file 22 | module lb_32x128( 23 | input [4:0] R0_addr, 24 | input R0_en, 25 | R0_clk, 26 | output [127:0] R0_data, 27 | input [4:0] W0_addr, 28 | input W0_en, 29 | W0_clk, 30 | input [127:0] W0_data 31 | ); 32 | 33 | reg [127:0] Memory[0:31]; 34 | always @(posedge W0_clk) begin 35 | if (W0_en & 1'h1) 36 | Memory[W0_addr] <= W0_data; 37 | end // always @(posedge) 38 | assign R0_data = R0_en ? Memory[R0_addr] : 128'bx; 39 | endmodule 40 | 41 | -------------------------------------------------------------------------------- /mock/data_data_40x128.sv: -------------------------------------------------------------------------------- 1 | // Standard header to adapt well known macros to our needs. 2 | 3 | // Users can define 'PRINTF_COND' to add an extra gate to prints. 4 | `ifndef PRINTF_COND_ 5 | `ifdef PRINTF_COND 6 | `define PRINTF_COND_ (`PRINTF_COND) 7 | `else // PRINTF_COND 8 | `define PRINTF_COND_ 1 9 | `endif // PRINTF_COND 10 | `endif // not def PRINTF_COND_ 11 | 12 | // VCS coverage exclude_file 13 | module data_data_40x128( 14 | input [5:0] R0_addr, 15 | input R0_en, 16 | R0_clk, 17 | input [5:0] W0_addr, 18 | input W0_en, 19 | W0_clk, 20 | input [127:0] W0_data, 21 | output [127:0] R0_data 22 | ); 23 | 24 | reg [127:0] Memory[0:15]; // Reduced to 16 rows 25 | reg [3:0] _R0_addr_d0; // Reduced to 4 bits 26 | reg [3:0] _W0_addr_d0; // Reduced to 4 bits 27 | always @(posedge R0_clk) begin 28 | _R0_addr_d0 <= R0_addr[3:0] ^ R0_addr[5:4]; // XOR upper and lower bits 29 | end // always @(posedge) 30 | always @(posedge W0_clk) begin 31 | _W0_addr_d0 <= W0_addr[3:0] ^ W0_addr[5:4]; // XOR upper and lower bits 32 | if (W0_en) 33 | Memory[_W0_addr_d0] <= W0_data; // Use XORed address 34 | end // always @(posedge) 35 | assign R0_data = R0_en ? Memory[_R0_addr_d0] : 128'bx; 36 | endmodule 37 | 38 | -------------------------------------------------------------------------------- /mock/ebtb_128x40.sv: -------------------------------------------------------------------------------- 1 | // Standard header to adapt well known macros to our needs. 2 | 3 | // Users can define 'PRINTF_COND' to add an extra gate to prints. 4 | `ifndef PRINTF_COND_ 5 | `ifdef PRINTF_COND 6 | `define PRINTF_COND_ (`PRINTF_COND) 7 | `else // PRINTF_COND 8 | `define PRINTF_COND_ 1 9 | `endif // PRINTF_COND 10 | `endif // not def PRINTF_COND_ 11 | 12 | // VCS coverage exclude_file 13 | module ebtb_128x40( 14 | input [6:0] R0_addr, 15 | input R0_en, 16 | R0_clk, 17 | input [6:0] W0_addr, 18 | input W0_en, 19 | W0_clk, 20 | input [39:0] W0_data, 21 | output [39:0] R0_data 22 | ); 23 | 24 | reg [39:0] Memory[0:15]; // Reduced to 16 rows 25 | reg _R0_en_d0; 26 | reg [3:0] _R0_addr_d0; // Reduced to 4 bits 27 | reg [3:0] _W0_addr_d0; // Reduced to 4 bits 28 | always @(posedge R0_clk) begin 29 | _R0_en_d0 <= R0_en; 30 | _R0_addr_d0 <= R0_addr[3:0] ^ R0_addr[6:4]; // XOR upper and lower bits 31 | end // always @(posedge) 32 | always @(posedge W0_clk) begin 33 | _W0_addr_d0 <= W0_addr[3:0] ^ W0_addr[6:4]; // XOR upper and lower bits 34 | if (W0_en) 35 | Memory[_W0_addr_d0] <= W0_data; // Use XORed address 36 | end // always @(posedge) 37 | assign R0_data = _R0_en_d0 ? Memory[_R0_addr_d0] : 40'bx; 38 | endmodule 39 | 40 | -------------------------------------------------------------------------------- /mock/ghist_40x64.sv: -------------------------------------------------------------------------------- 1 | // Standard header to adapt well known macros to our needs. 2 | 3 | // Users can define 'PRINTF_COND' to add an extra gate to prints. 4 | `ifndef PRINTF_COND_ 5 | `ifdef PRINTF_COND 6 | `define PRINTF_COND_ (`PRINTF_COND) 7 | `else // PRINTF_COND 8 | `define PRINTF_COND_ 1 9 | `endif // PRINTF_COND 10 | `endif // not def PRINTF_COND_ 11 | 12 | // VCS coverage exclude_file 13 | module ghist_40x64( 14 | input [5:0] R0_addr, 15 | input R0_en, 16 | R0_clk, 17 | input [5:0] W0_addr, 18 | input W0_en, 19 | W0_clk, 20 | input [63:0] W0_data, 21 | output [63:0] R0_data 22 | ); 23 | 24 | reg [63:0] Memory[0:15]; // Reduced to 16 rows 25 | reg _R0_en_d0; 26 | reg [3:0] _R0_addr_d0; // Reduced to 4 bits 27 | reg [3:0] _W0_addr_d0; // Reduced to 4 bits 28 | always @(posedge R0_clk) begin 29 | _R0_en_d0 <= R0_en; 30 | _R0_addr_d0 <= R0_addr[3:0] ^ R0_addr[5:4]; // XOR upper and lower bits 31 | end // always @(posedge) 32 | always @(posedge W0_clk) begin 33 | _W0_addr_d0 <= W0_addr[3:0] ^ W0_addr[5:4]; // XOR upper and lower bits 34 | if (W0_en) 35 | Memory[_W0_addr_d0] <= W0_data; // Use XORed address 36 | end // always @(posedge) 37 | assign R0_data = _R0_en_d0 ? Memory[_R0_addr_d0] : 64'bx; 38 | endmodule 39 | 40 | -------------------------------------------------------------------------------- /rtl/RecFNToRecFN_1.sv: -------------------------------------------------------------------------------- 1 | // Standard header to adapt well known macros for prints and assertions. 2 | 3 | // Users can define 'ASSERT_VERBOSE_COND' to add an extra gate to assert error printing. 4 | `ifndef ASSERT_VERBOSE_COND_ 5 | `ifdef ASSERT_VERBOSE_COND 6 | `define ASSERT_VERBOSE_COND_ (`ASSERT_VERBOSE_COND) 7 | `else // ASSERT_VERBOSE_COND 8 | `define ASSERT_VERBOSE_COND_ 1 9 | `endif // ASSERT_VERBOSE_COND 10 | `endif // not def ASSERT_VERBOSE_COND_ 11 | 12 | // Users can define 'STOP_COND' to add an extra gate to stop conditions. 13 | `ifndef STOP_COND_ 14 | `ifdef STOP_COND 15 | `define STOP_COND_ (`STOP_COND) 16 | `else // STOP_COND 17 | `define STOP_COND_ 1 18 | `endif // STOP_COND 19 | `endif // not def STOP_COND_ 20 | 21 | module RecFNToRecFN_1( 22 | input [32:0] io_in, 23 | output [64:0] io_out 24 | ); 25 | 26 | wire rawIn_isNaN = (&(io_in[31:30])) & io_in[29]; 27 | RoundAnyRawFNToRecFN_5 roundAnyRawFNToRecFN ( 28 | .io_invalidExc (rawIn_isNaN & ~(io_in[22])), 29 | .io_in_isNaN (rawIn_isNaN), 30 | .io_in_isInf ((&(io_in[31:30])) & ~(io_in[29])), 31 | .io_in_isZero (~(|(io_in[31:29]))), 32 | .io_in_sign (io_in[32]), 33 | .io_in_sExp ({1'h0, io_in[31:23]}), 34 | .io_in_sig ({1'h0, |(io_in[31:29]), io_in[22:0]}), 35 | .io_out (io_out) 36 | ); 37 | endmodule 38 | 39 | -------------------------------------------------------------------------------- /mock/data_2048x2.sv: -------------------------------------------------------------------------------- 1 | // Standard header to adapt well known macros to our needs. 2 | 3 | // Users can define 'PRINTF_COND' to add an extra gate to prints. 4 | `ifndef PRINTF_COND_ 5 | `ifdef PRINTF_COND 6 | `define PRINTF_COND_ (`PRINTF_COND) 7 | `else // PRINTF_COND 8 | `define PRINTF_COND_ 1 9 | `endif // PRINTF_COND 10 | `endif // not def PRINTF_COND_ 11 | 12 | // VCS coverage exclude_file 13 | module data_2048x2( 14 | input [10:0] R0_addr, 15 | input R0_en, 16 | R0_clk, 17 | input [10:0] W0_addr, 18 | input W0_en, 19 | W0_clk, 20 | input [1:0] W0_data, 21 | output [1:0] R0_data 22 | ); 23 | 24 | reg [1:0] Memory[0:15]; // Reduced to 16 rows 25 | reg _R0_en_d0; 26 | reg [3:0] _R0_addr_d0; // Reduced to 4 bits 27 | reg [3:0] _W0_addr_d0; // Reduced to 4 bits 28 | always @(posedge R0_clk) begin 29 | _R0_en_d0 <= R0_en; 30 | _R0_addr_d0 <= R0_addr[3:0] ^ R0_addr[7:4] ^ R0_addr[8:10]; // XOR upper and lower bits and MSB 31 | end // always @(posedge) 32 | always @(posedge W0_clk) begin 33 | _W0_addr_d0 <= W0_addr[3:0] ^ W0_addr[7:4] ^ W0_addr[8:10]; // XOR upper and lower bits and MSB 34 | if (W0_en) 35 | Memory[_W0_addr_d0] <= W0_data; // Use XORed address 36 | end // always @(posedge) 37 | assign R0_data = _R0_en_d0 ? Memory[_R0_addr_d0] : 2'bx; 38 | endmodule 39 | 40 | -------------------------------------------------------------------------------- /rtl/Arbiter_14.sv: -------------------------------------------------------------------------------- 1 | // Standard header to adapt well known macros for prints and assertions. 2 | 3 | // Users can define 'ASSERT_VERBOSE_COND' to add an extra gate to assert error printing. 4 | `ifndef ASSERT_VERBOSE_COND_ 5 | `ifdef ASSERT_VERBOSE_COND 6 | `define ASSERT_VERBOSE_COND_ (`ASSERT_VERBOSE_COND) 7 | `else // ASSERT_VERBOSE_COND 8 | `define ASSERT_VERBOSE_COND_ 1 9 | `endif // ASSERT_VERBOSE_COND 10 | `endif // not def ASSERT_VERBOSE_COND_ 11 | 12 | // Users can define 'STOP_COND' to add an extra gate to stop conditions. 13 | `ifndef STOP_COND_ 14 | `ifdef STOP_COND 15 | `define STOP_COND_ (`STOP_COND) 16 | `else // STOP_COND 17 | `define STOP_COND_ 1 18 | `endif // STOP_COND 19 | `endif // not def STOP_COND_ 20 | 21 | module Arbiter_14( 22 | output io_in_0_ready, 23 | input io_in_0_valid, 24 | input [32:0] io_in_0_bits_address, 25 | output io_in_1_ready, 26 | input io_in_1_valid, 27 | input [32:0] io_in_1_bits_address, 28 | input io_out_ready, 29 | output io_out_valid, 30 | output [32:0] io_out_bits_address 31 | ); 32 | 33 | assign io_in_0_ready = io_out_ready; 34 | assign io_in_1_ready = ~io_in_0_valid & io_out_ready; 35 | assign io_out_valid = io_in_0_valid | io_in_1_valid; 36 | assign io_out_bits_address = io_in_0_valid ? io_in_0_bits_address : io_in_1_bits_address; 37 | endmodule 38 | 39 | -------------------------------------------------------------------------------- /rtl/ClockGroupResetSynchronizer.sv: -------------------------------------------------------------------------------- 1 | // Standard header to adapt well known macros for prints and assertions. 2 | 3 | // Users can define 'ASSERT_VERBOSE_COND' to add an extra gate to assert error printing. 4 | `ifndef ASSERT_VERBOSE_COND_ 5 | `ifdef ASSERT_VERBOSE_COND 6 | `define ASSERT_VERBOSE_COND_ (`ASSERT_VERBOSE_COND) 7 | `else // ASSERT_VERBOSE_COND 8 | `define ASSERT_VERBOSE_COND_ 1 9 | `endif // ASSERT_VERBOSE_COND 10 | `endif // not def ASSERT_VERBOSE_COND_ 11 | 12 | // Users can define 'STOP_COND' to add an extra gate to stop conditions. 13 | `ifndef STOP_COND_ 14 | `ifdef STOP_COND 15 | `define STOP_COND_ (`STOP_COND) 16 | `else // STOP_COND 17 | `define STOP_COND_ 1 18 | `endif // STOP_COND 19 | `endif // not def STOP_COND_ 20 | 21 | module ClockGroupResetSynchronizer( 22 | input auto_in_member_allClocks_uncore_clock, 23 | auto_in_member_allClocks_uncore_reset, 24 | output auto_out_member_allClocks_uncore_clock, 25 | auto_out_member_allClocks_uncore_reset 26 | ); 27 | 28 | ResetCatchAndSync_d3 nodeOut_member_allClocks_uncore_reset_catcher ( 29 | .clock (auto_in_member_allClocks_uncore_clock), 30 | .reset (auto_in_member_allClocks_uncore_reset), 31 | .io_sync_reset (auto_out_member_allClocks_uncore_reset) 32 | ); 33 | assign auto_out_member_allClocks_uncore_clock = auto_in_member_allClocks_uncore_clock; 34 | endmodule 35 | 36 | -------------------------------------------------------------------------------- /rtl/RoundAnyRawFNToRecFN_5.sv: -------------------------------------------------------------------------------- 1 | // Standard header to adapt well known macros for prints and assertions. 2 | 3 | // Users can define 'ASSERT_VERBOSE_COND' to add an extra gate to assert error printing. 4 | `ifndef ASSERT_VERBOSE_COND_ 5 | `ifdef ASSERT_VERBOSE_COND 6 | `define ASSERT_VERBOSE_COND_ (`ASSERT_VERBOSE_COND) 7 | `else // ASSERT_VERBOSE_COND 8 | `define ASSERT_VERBOSE_COND_ 1 9 | `endif // ASSERT_VERBOSE_COND 10 | `endif // not def ASSERT_VERBOSE_COND_ 11 | 12 | // Users can define 'STOP_COND' to add an extra gate to stop conditions. 13 | `ifndef STOP_COND_ 14 | `ifdef STOP_COND 15 | `define STOP_COND_ (`STOP_COND) 16 | `else // STOP_COND 17 | `define STOP_COND_ 1 18 | `endif // STOP_COND 19 | `endif // not def STOP_COND_ 20 | 21 | module RoundAnyRawFNToRecFN_5( 22 | input io_invalidExc, 23 | io_in_isNaN, 24 | io_in_isInf, 25 | io_in_isZero, 26 | io_in_sign, 27 | input [9:0] io_in_sExp, 28 | input [24:0] io_in_sig, 29 | output [64:0] io_out 30 | ); 31 | 32 | wire isNaNOut = io_invalidExc | io_in_isNaN; 33 | assign io_out = {~isNaNOut & io_in_sign, {{2{io_in_sExp[9]}}, io_in_sExp} + 12'h700 & ~(io_in_isZero ? 12'hE00 : 12'h0) & {2'h3, ~io_in_isInf, 9'h1FF} | (io_in_isInf ? 12'hC00 : 12'h0) | (isNaNOut ? 12'hE00 : 12'h0), isNaNOut | io_in_isZero ? {isNaNOut, 51'h0} : {io_in_sig[22:0], 29'h0}}; 34 | endmodule 35 | 36 | -------------------------------------------------------------------------------- /slack-positions.tcl: -------------------------------------------------------------------------------- 1 | # To test from ~/OpenROAD-flow-scripts, run: 2 | # make RUN_SCRIPT=~/megaboom/slack-positions.tcl ODB_FILE=results/nangate45/gcd/base/4_cts.odb run OUTPUT=xxx.txt 3 | source $::env(SCRIPTS_DIR)/open.tcl 4 | 5 | set paths [find_timing_paths -path_group reg2reg -sort_by_slack -group_count 1000000] 6 | 7 | set db [::ord::get_db] 8 | set block [[$db getChip] getBlock] 9 | 10 | set fp [open $::env(OUTPUT) w] 11 | puts $fp "stats:" 12 | foreach path $paths { 13 | set endpoint [get_property $path endpoint] 14 | set instance [sta::sta_to_db_inst [$endpoint instance]] 15 | set port [sta::sta_to_db_port [$endpoint port]] 16 | set name [get_property $endpoint full_name] 17 | set obj {NULL} 18 | if {$port!={NULL}} { 19 | set obj $port 20 | } elseif {$instance!={NULL}} { 21 | set obj $instance 22 | } else { 23 | puts "Nothing found for $name" 24 | continue 25 | } 26 | set slack [get_property $path slack] 27 | set skew [$path clk_skew] 28 | set bbox [$obj getBBox] 29 | puts $fp " - $name $slack $skew [ord::dbu_to_microns [$bbox xMin]] [ord::dbu_to_microns [$bbox yMin]]" 30 | } 31 | 32 | puts $fp "masters:" 33 | foreach master [$block getInsts] { 34 | if {[$master isBlock]} { 35 | set bbox [$master getBBox] 36 | puts $fp " - [$master getName] [ord::dbu_to_microns [$bbox xMin]] [ord::dbu_to_microns [$bbox yMin]] [ord::dbu_to_microns [$bbox xMax]] [ord::dbu_to_microns [$bbox yMax]]" 37 | } 38 | } 39 | 40 | close $fp 41 | -------------------------------------------------------------------------------- /rtl/ghist_40x72.sv: -------------------------------------------------------------------------------- 1 | // Standard header to adapt well known macros for prints and assertions. 2 | 3 | // Users can define 'ASSERT_VERBOSE_COND' to add an extra gate to assert error printing. 4 | `ifndef ASSERT_VERBOSE_COND_ 5 | `ifdef ASSERT_VERBOSE_COND 6 | `define ASSERT_VERBOSE_COND_ (`ASSERT_VERBOSE_COND) 7 | `else // ASSERT_VERBOSE_COND 8 | `define ASSERT_VERBOSE_COND_ 1 9 | `endif // ASSERT_VERBOSE_COND 10 | `endif // not def ASSERT_VERBOSE_COND_ 11 | 12 | // Users can define 'STOP_COND' to add an extra gate to stop conditions. 13 | `ifndef STOP_COND_ 14 | `ifdef STOP_COND 15 | `define STOP_COND_ (`STOP_COND) 16 | `else // STOP_COND 17 | `define STOP_COND_ 1 18 | `endif // STOP_COND 19 | `endif // not def STOP_COND_ 20 | 21 | // VCS coverage exclude_file 22 | module ghist_40x72( 23 | input [5:0] R0_addr, 24 | input R0_en, 25 | R0_clk, 26 | output [71:0] R0_data, 27 | input [5:0] W0_addr, 28 | input W0_en, 29 | W0_clk, 30 | input [71:0] W0_data 31 | ); 32 | 33 | reg [71:0] Memory[0:39]; 34 | reg _R0_en_d0; 35 | reg [5:0] _R0_addr_d0; 36 | always @(posedge R0_clk) begin 37 | _R0_en_d0 <= R0_en; 38 | _R0_addr_d0 <= R0_addr; 39 | end // always @(posedge) 40 | always @(posedge W0_clk) begin 41 | if (W0_en & 1'h1) 42 | Memory[W0_addr] <= W0_data; 43 | end // always @(posedge) 44 | assign R0_data = _R0_en_d0 ? Memory[_R0_addr_d0] : 72'bx; 45 | endmodule 46 | 47 | -------------------------------------------------------------------------------- /rtl/ebtb_128x40.sv: -------------------------------------------------------------------------------- 1 | // Standard header to adapt well known macros for prints and assertions. 2 | 3 | // Users can define 'ASSERT_VERBOSE_COND' to add an extra gate to assert error printing. 4 | `ifndef ASSERT_VERBOSE_COND_ 5 | `ifdef ASSERT_VERBOSE_COND 6 | `define ASSERT_VERBOSE_COND_ (`ASSERT_VERBOSE_COND) 7 | `else // ASSERT_VERBOSE_COND 8 | `define ASSERT_VERBOSE_COND_ 1 9 | `endif // ASSERT_VERBOSE_COND 10 | `endif // not def ASSERT_VERBOSE_COND_ 11 | 12 | // Users can define 'STOP_COND' to add an extra gate to stop conditions. 13 | `ifndef STOP_COND_ 14 | `ifdef STOP_COND 15 | `define STOP_COND_ (`STOP_COND) 16 | `else // STOP_COND 17 | `define STOP_COND_ 1 18 | `endif // STOP_COND 19 | `endif // not def STOP_COND_ 20 | 21 | // VCS coverage exclude_file 22 | module ebtb_128x40( 23 | input [6:0] R0_addr, 24 | input R0_en, 25 | R0_clk, 26 | output [39:0] R0_data, 27 | input [6:0] W0_addr, 28 | input W0_en, 29 | W0_clk, 30 | input [39:0] W0_data 31 | ); 32 | 33 | reg [39:0] Memory[0:127]; 34 | reg _R0_en_d0; 35 | reg [6:0] _R0_addr_d0; 36 | always @(posedge R0_clk) begin 37 | _R0_en_d0 <= R0_en; 38 | _R0_addr_d0 <= R0_addr; 39 | end // always @(posedge) 40 | always @(posedge W0_clk) begin 41 | if (W0_en & 1'h1) 42 | Memory[W0_addr] <= W0_data; 43 | end // always @(posedge) 44 | assign R0_data = _R0_en_d0 ? Memory[_R0_addr_d0] : 40'bx; 45 | endmodule 46 | 47 | -------------------------------------------------------------------------------- /constraints.sdc: -------------------------------------------------------------------------------- 1 | set sdc_version 2.0 2 | 3 | # 4 | # SDC file used during SRAM abstract generation 5 | # 6 | 7 | # Run at 833 MHz 8 | set clk_period 1200 9 | 10 | # Covers all clock naming types in SRAMs and reg files 11 | set clock_ports [concat [get_ports -quiet *clk] [get_ports -quiet *clock]] 12 | 13 | if {[llength $clock_ports] == 0} { 14 | error "No clock ports found" 15 | } 16 | 17 | foreach clk_port $clock_ports { 18 | set clk_name [get_name $clk_port] 19 | create_clock -period $clk_period -name $clk_name $clk_port 20 | } 21 | 22 | set non_clk_inputs {} 23 | foreach input [all_inputs] { 24 | if {[lsearch -exact $clock_ports $input] == -1} { 25 | lappend non_clk_inputs $input 26 | } 27 | } 28 | 29 | set_max_delay [expr {[info exists in2out_max] ? $in2out_max : 80}] -from $non_clk_inputs -to [all_outputs] 30 | group_path -name in2out -from $non_clk_inputs -to [all_outputs] 31 | 32 | if {[llength [all_registers]] > 0} { 33 | set all_register_outputs [get_pins -of_objects [all_registers] -filter {direction == output}] 34 | set_max_delay [expr {[info exists in2reg_max] ? $in2reg_max : 80}] -from $non_clk_inputs -to [all_registers] 35 | set_max_delay [expr {[info exists reg2out_max] ? $reg2out_max : 80}] -from $all_register_outputs -to [all_outputs] 36 | 37 | group_path -name in2reg -from $non_clk_inputs -to [all_registers] 38 | group_path -name reg2out -from [all_registers] -to [all_outputs] 39 | group_path -name reg2reg -from [all_registers] -to [all_registers] 40 | } 41 | -------------------------------------------------------------------------------- /rtl/dataArrayB_256x64.sv: -------------------------------------------------------------------------------- 1 | // Standard header to adapt well known macros for prints and assertions. 2 | 3 | // Users can define 'ASSERT_VERBOSE_COND' to add an extra gate to assert error printing. 4 | `ifndef ASSERT_VERBOSE_COND_ 5 | `ifdef ASSERT_VERBOSE_COND 6 | `define ASSERT_VERBOSE_COND_ (`ASSERT_VERBOSE_COND) 7 | `else // ASSERT_VERBOSE_COND 8 | `define ASSERT_VERBOSE_COND_ 1 9 | `endif // ASSERT_VERBOSE_COND 10 | `endif // not def ASSERT_VERBOSE_COND_ 11 | 12 | // Users can define 'STOP_COND' to add an extra gate to stop conditions. 13 | `ifndef STOP_COND_ 14 | `ifdef STOP_COND 15 | `define STOP_COND_ (`STOP_COND) 16 | `else // STOP_COND 17 | `define STOP_COND_ 1 18 | `endif // STOP_COND 19 | `endif // not def STOP_COND_ 20 | 21 | // VCS coverage exclude_file 22 | module dataArrayB_256x64( 23 | input [7:0] RW0_addr, 24 | input RW0_en, 25 | RW0_clk, 26 | RW0_wmode, 27 | input [63:0] RW0_wdata, 28 | output [63:0] RW0_rdata 29 | ); 30 | 31 | reg [63:0] Memory[0:255]; 32 | reg [7:0] _RW0_raddr_d0; 33 | reg _RW0_ren_d0; 34 | reg _RW0_rmode_d0; 35 | always @(posedge RW0_clk) begin 36 | _RW0_raddr_d0 <= RW0_addr; 37 | _RW0_ren_d0 <= RW0_en; 38 | _RW0_rmode_d0 <= RW0_wmode; 39 | if (RW0_en & RW0_wmode & 1'h1) 40 | Memory[RW0_addr] <= RW0_wdata; 41 | end // always @(posedge) 42 | assign RW0_rdata = _RW0_ren_d0 & ~_RW0_rmode_d0 ? Memory[_RW0_raddr_d0] : 64'bx; 43 | endmodule 44 | 45 | -------------------------------------------------------------------------------- /rtl/meta_40x240.sv: -------------------------------------------------------------------------------- 1 | // Standard header to adapt well known macros for prints and assertions. 2 | 3 | // Users can define 'ASSERT_VERBOSE_COND' to add an extra gate to assert error printing. 4 | `ifndef ASSERT_VERBOSE_COND_ 5 | `ifdef ASSERT_VERBOSE_COND 6 | `define ASSERT_VERBOSE_COND_ (`ASSERT_VERBOSE_COND) 7 | `else // ASSERT_VERBOSE_COND 8 | `define ASSERT_VERBOSE_COND_ 1 9 | `endif // ASSERT_VERBOSE_COND 10 | `endif // not def ASSERT_VERBOSE_COND_ 11 | 12 | // Users can define 'STOP_COND' to add an extra gate to stop conditions. 13 | `ifndef STOP_COND_ 14 | `ifdef STOP_COND 15 | `define STOP_COND_ (`STOP_COND) 16 | `else // STOP_COND 17 | `define STOP_COND_ 1 18 | `endif // STOP_COND 19 | `endif // not def STOP_COND_ 20 | 21 | // VCS coverage exclude_file 22 | module meta_40x240( 23 | input [5:0] R0_addr, 24 | input R0_en, 25 | R0_clk, 26 | output [239:0] R0_data, 27 | input [5:0] W0_addr, 28 | input W0_en, 29 | W0_clk, 30 | input [239:0] W0_data 31 | ); 32 | 33 | reg [239:0] Memory[0:39]; 34 | reg _R0_en_d0; 35 | reg [5:0] _R0_addr_d0; 36 | always @(posedge R0_clk) begin 37 | _R0_en_d0 <= R0_en; 38 | _R0_addr_d0 <= R0_addr; 39 | end // always @(posedge) 40 | always @(posedge W0_clk) begin 41 | if (W0_en & 1'h1) 42 | Memory[W0_addr] <= W0_data; 43 | end // always @(posedge) 44 | assign R0_data = _R0_en_d0 ? Memory[_R0_addr_d0] : 240'bx; 45 | endmodule 46 | 47 | -------------------------------------------------------------------------------- /rtl/l2_tlb_ram_0_512x46.sv: -------------------------------------------------------------------------------- 1 | // Standard header to adapt well known macros for prints and assertions. 2 | 3 | // Users can define 'ASSERT_VERBOSE_COND' to add an extra gate to assert error printing. 4 | `ifndef ASSERT_VERBOSE_COND_ 5 | `ifdef ASSERT_VERBOSE_COND 6 | `define ASSERT_VERBOSE_COND_ (`ASSERT_VERBOSE_COND) 7 | `else // ASSERT_VERBOSE_COND 8 | `define ASSERT_VERBOSE_COND_ 1 9 | `endif // ASSERT_VERBOSE_COND 10 | `endif // not def ASSERT_VERBOSE_COND_ 11 | 12 | // Users can define 'STOP_COND' to add an extra gate to stop conditions. 13 | `ifndef STOP_COND_ 14 | `ifdef STOP_COND 15 | `define STOP_COND_ (`STOP_COND) 16 | `else // STOP_COND 17 | `define STOP_COND_ 1 18 | `endif // STOP_COND 19 | `endif // not def STOP_COND_ 20 | 21 | // VCS coverage exclude_file 22 | module l2_tlb_ram_0_512x46( 23 | input [8:0] RW0_addr, 24 | input RW0_en, 25 | RW0_clk, 26 | RW0_wmode, 27 | input [45:0] RW0_wdata, 28 | output [45:0] RW0_rdata 29 | ); 30 | 31 | reg [45:0] Memory[0:511]; 32 | reg [8:0] _RW0_raddr_d0; 33 | reg _RW0_ren_d0; 34 | reg _RW0_rmode_d0; 35 | always @(posedge RW0_clk) begin 36 | _RW0_raddr_d0 <= RW0_addr; 37 | _RW0_ren_d0 <= RW0_en; 38 | _RW0_rmode_d0 <= RW0_wmode; 39 | if (RW0_en & RW0_wmode & 1'h1) 40 | Memory[RW0_addr] <= RW0_wdata; 41 | end // always @(posedge) 42 | assign RW0_rdata = _RW0_ren_d0 & ~_RW0_rmode_d0 ? Memory[_RW0_raddr_d0] : 46'bx; 43 | endmodule 44 | 45 | -------------------------------------------------------------------------------- /rtl/Repeater_7.sv: -------------------------------------------------------------------------------- 1 | // Standard header to adapt well known macros for prints and assertions. 2 | 3 | // Users can define 'ASSERT_VERBOSE_COND' to add an extra gate to assert error printing. 4 | `ifndef ASSERT_VERBOSE_COND_ 5 | `ifdef ASSERT_VERBOSE_COND 6 | `define ASSERT_VERBOSE_COND_ (`ASSERT_VERBOSE_COND) 7 | `else // ASSERT_VERBOSE_COND 8 | `define ASSERT_VERBOSE_COND_ 1 9 | `endif // ASSERT_VERBOSE_COND 10 | `endif // not def ASSERT_VERBOSE_COND_ 11 | 12 | // Users can define 'STOP_COND' to add an extra gate to stop conditions. 13 | `ifndef STOP_COND_ 14 | `ifdef STOP_COND 15 | `define STOP_COND_ (`STOP_COND) 16 | `else // STOP_COND 17 | `define STOP_COND_ 1 18 | `endif // STOP_COND 19 | `endif // not def STOP_COND_ 20 | 21 | module Repeater_7( 22 | input clock, 23 | reset, 24 | output io_enq_ready, 25 | input io_enq_valid, 26 | input [32:0] io_enq_bits_address, 27 | input io_deq_ready, 28 | output io_deq_valid, 29 | output [32:0] io_deq_bits_address 30 | ); 31 | 32 | reg full; 33 | wire _io_deq_valid_output = io_enq_valid | full; 34 | always @(posedge clock) begin 35 | if (reset) 36 | full <= 1'h0; 37 | else 38 | full <= ~(io_deq_ready & _io_deq_valid_output) & full; 39 | end // always @(posedge) 40 | assign io_enq_ready = io_deq_ready & ~full; 41 | assign io_deq_valid = _io_deq_valid_output; 42 | assign io_deq_bits_address = full ? 33'h0 : io_enq_bits_address; 43 | endmodule 44 | 45 | -------------------------------------------------------------------------------- /rtl/remote_bitbang.h: -------------------------------------------------------------------------------- 1 | // See LICENSE.Berkeley for license details. 2 | 3 | #ifndef REMOTE_BITBANG_H 4 | #define REMOTE_BITBANG_H 5 | 6 | #include 7 | #include 8 | 9 | class remote_bitbang_t 10 | { 11 | public: 12 | // Create a new server, listening for connections from localhost on the given 13 | // port. 14 | remote_bitbang_t(uint16_t port); 15 | 16 | // Do a bit of work. 17 | void tick(unsigned char * jtag_tck, 18 | unsigned char * jtag_tms, 19 | unsigned char * jtag_tdi, 20 | unsigned char * jtag_trstn, 21 | unsigned char jtag_tdo); 22 | 23 | unsigned char done() {return quit;} 24 | 25 | int exit_code() {return err;} 26 | 27 | private: 28 | 29 | int err; 30 | 31 | unsigned char tck; 32 | unsigned char tms; 33 | unsigned char tdi; 34 | unsigned char trstn; 35 | unsigned char tdo; 36 | unsigned char quit; 37 | 38 | int socket_fd; 39 | int client_fd; 40 | 41 | static const ssize_t buf_size = 64 * 1024; 42 | char recv_buf[buf_size]; 43 | ssize_t recv_start, recv_end; 44 | 45 | // Check for a client connecting, and accept if there is one. 46 | void accept(); 47 | // Execute any commands the client has for us. 48 | // But we only execute 1 because we need time for the 49 | // simulation to run. 50 | void execute_command(); 51 | 52 | // Reset. Currently does nothing. 53 | void reset(); 54 | 55 | void set_pins(char _tck, char _tms, char _tdi); 56 | 57 | }; 58 | 59 | #endif 60 | -------------------------------------------------------------------------------- /rtl/AsyncResetRegVec_w1_i1.sv: -------------------------------------------------------------------------------- 1 | // Standard header to adapt well known macros for prints and assertions. 2 | 3 | // Users can define 'ASSERT_VERBOSE_COND' to add an extra gate to assert error printing. 4 | `ifndef ASSERT_VERBOSE_COND_ 5 | `ifdef ASSERT_VERBOSE_COND 6 | `define ASSERT_VERBOSE_COND_ (`ASSERT_VERBOSE_COND) 7 | `else // ASSERT_VERBOSE_COND 8 | `define ASSERT_VERBOSE_COND_ 1 9 | `endif // ASSERT_VERBOSE_COND 10 | `endif // not def ASSERT_VERBOSE_COND_ 11 | 12 | // Users can define 'STOP_COND' to add an extra gate to stop conditions. 13 | `ifndef STOP_COND_ 14 | `ifdef STOP_COND 15 | `define STOP_COND_ (`STOP_COND) 16 | `else // STOP_COND 17 | `define STOP_COND_ 1 18 | `endif // STOP_COND 19 | `endif // not def STOP_COND_ 20 | 21 | module AsyncResetRegVec_w1_i1( 22 | input clock, 23 | reset, 24 | io_d, 25 | output io_q, 26 | input io_en 27 | ); 28 | 29 | reg reg_0; 30 | always @(posedge clock or posedge reset) begin 31 | if (reset) 32 | reg_0 <= 1'h1; 33 | else if (io_en) 34 | reg_0 <= io_d; 35 | end // always @(posedge, posedge) 36 | `ifdef ENABLE_INITIAL_REG_ 37 | `ifdef FIRRTL_BEFORE_INITIAL 38 | `FIRRTL_BEFORE_INITIAL 39 | `endif // FIRRTL_BEFORE_INITIAL 40 | initial begin 41 | if (reset) 42 | reg_0 = 1'h1; 43 | end // initial 44 | `ifdef FIRRTL_AFTER_INITIAL 45 | `FIRRTL_AFTER_INITIAL 46 | `endif // FIRRTL_AFTER_INITIAL 47 | `endif // ENABLE_INITIAL_REG_ 48 | assign io_q = reg_0; 49 | endmodule 50 | 51 | -------------------------------------------------------------------------------- /rtl/AsyncResetRegVec_w2_i0.sv: -------------------------------------------------------------------------------- 1 | // Standard header to adapt well known macros for prints and assertions. 2 | 3 | // Users can define 'ASSERT_VERBOSE_COND' to add an extra gate to assert error printing. 4 | `ifndef ASSERT_VERBOSE_COND_ 5 | `ifdef ASSERT_VERBOSE_COND 6 | `define ASSERT_VERBOSE_COND_ (`ASSERT_VERBOSE_COND) 7 | `else // ASSERT_VERBOSE_COND 8 | `define ASSERT_VERBOSE_COND_ 1 9 | `endif // ASSERT_VERBOSE_COND 10 | `endif // not def ASSERT_VERBOSE_COND_ 11 | 12 | // Users can define 'STOP_COND' to add an extra gate to stop conditions. 13 | `ifndef STOP_COND_ 14 | `ifdef STOP_COND 15 | `define STOP_COND_ (`STOP_COND) 16 | `else // STOP_COND 17 | `define STOP_COND_ 1 18 | `endif // STOP_COND 19 | `endif // not def STOP_COND_ 20 | 21 | module AsyncResetRegVec_w2_i0( 22 | input clock, 23 | reset, 24 | input [1:0] io_d, 25 | output [1:0] io_q 26 | ); 27 | 28 | reg [1:0] reg_0; 29 | always @(posedge clock or posedge reset) begin 30 | if (reset) 31 | reg_0 <= 2'h0; 32 | else 33 | reg_0 <= io_d; 34 | end // always @(posedge, posedge) 35 | `ifdef ENABLE_INITIAL_REG_ 36 | `ifdef FIRRTL_BEFORE_INITIAL 37 | `FIRRTL_BEFORE_INITIAL 38 | `endif // FIRRTL_BEFORE_INITIAL 39 | initial begin 40 | if (reset) 41 | reg_0 = 2'h0; 42 | end // initial 43 | `ifdef FIRRTL_AFTER_INITIAL 44 | `FIRRTL_AFTER_INITIAL 45 | `endif // FIRRTL_AFTER_INITIAL 46 | `endif // ENABLE_INITIAL_REG_ 47 | assign io_q = reg_0; 48 | endmodule 49 | 50 | -------------------------------------------------------------------------------- /rtl/testchip_htif.cc: -------------------------------------------------------------------------------- 1 | #include "testchip_htif.h" 2 | 3 | void testchip_htif_t::parse_htif_args(std::vector &args) { 4 | for (auto& arg : args) { 5 | if (arg.find("+init_write=0x") == 0) { 6 | auto d = arg.find(":0x"); 7 | if (d == std::string::npos) { 8 | throw std::invalid_argument("Improperly formatted +init_write argument"); 9 | } 10 | uint64_t addr = strtoull(arg.substr(14, d - 14).c_str(), 0, 16); 11 | uint32_t val = strtoull(arg.substr(d + 3).c_str(), 0, 16); 12 | init_access_t access = { .address=addr, .stdata=val, .store=true }; 13 | init_accesses.push_back(access); 14 | } 15 | if (arg.find("+init_read=0x") == 0) { 16 | uint64_t addr = strtoull(arg.substr(13).c_str(), 0, 16); 17 | init_access_t access = { .address=addr, .stdata=0, .store=false }; 18 | init_accesses.push_back(access); 19 | } 20 | if (arg.find("+no_hart0_msip") == 0) 21 | write_hart0_msip = false; 22 | } 23 | } 24 | 25 | void testchip_htif_t::perform_init_accesses() { 26 | for (auto p : init_accesses) { 27 | if (p.store) { 28 | fprintf(stderr, "Writing %lx with %x\n", p.address, p.stdata); 29 | write_chunk(p.address, sizeof(uint32_t), &p.stdata); 30 | fprintf(stderr, "Done writing %lx with %x\n", p.address, p.stdata); 31 | } else { 32 | fprintf(stderr, "Reading %lx ...", p.address); 33 | uint32_t rdata = 0; 34 | read_chunk(p.address, sizeof(uint32_t), &rdata); 35 | fprintf(stderr, " got %x\n", rdata); 36 | } 37 | } 38 | } 39 | -------------------------------------------------------------------------------- /rtl/OptimizationBarrier.sv: -------------------------------------------------------------------------------- 1 | // Standard header to adapt well known macros for prints and assertions. 2 | 3 | // Users can define 'ASSERT_VERBOSE_COND' to add an extra gate to assert error printing. 4 | `ifndef ASSERT_VERBOSE_COND_ 5 | `ifdef ASSERT_VERBOSE_COND 6 | `define ASSERT_VERBOSE_COND_ (`ASSERT_VERBOSE_COND) 7 | `else // ASSERT_VERBOSE_COND 8 | `define ASSERT_VERBOSE_COND_ 1 9 | `endif // ASSERT_VERBOSE_COND 10 | `endif // not def ASSERT_VERBOSE_COND_ 11 | 12 | // Users can define 'STOP_COND' to add an extra gate to stop conditions. 13 | `ifndef STOP_COND_ 14 | `ifdef STOP_COND 15 | `define STOP_COND_ (`STOP_COND) 16 | `else // STOP_COND 17 | `define STOP_COND_ 1 18 | `endif // STOP_COND 19 | `endif // not def STOP_COND_ 20 | 21 | module OptimizationBarrier( 22 | input [20:0] io_x_ppn, 23 | input io_x_u, 24 | io_x_ae_ptw, 25 | io_x_ae_final, 26 | io_x_pf, 27 | io_x_gf, 28 | io_x_sx, 29 | io_x_px, 30 | output [20:0] io_y_ppn, 31 | output io_y_u, 32 | io_y_ae_ptw, 33 | io_y_ae_final, 34 | io_y_pf, 35 | io_y_gf, 36 | io_y_sx, 37 | io_y_px 38 | ); 39 | 40 | assign io_y_ppn = io_x_ppn; 41 | assign io_y_u = io_x_u; 42 | assign io_y_ae_ptw = io_x_ae_ptw; 43 | assign io_y_ae_final = io_x_ae_final; 44 | assign io_y_pf = io_x_pf; 45 | assign io_y_gf = io_x_gf; 46 | assign io_y_sx = io_x_sx; 47 | assign io_y_px = io_x_px; 48 | endmodule 49 | 50 | -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | BSD 3-Clause License 2 | 3 | Copyright (c) 2023, The OpenROAD Project 4 | 5 | Redistribution and use in source and binary forms, with or without 6 | modification, are permitted provided that the following conditions are met: 7 | 8 | 1. Redistributions of source code must retain the above copyright notice, this 9 | list of conditions and the following disclaimer. 10 | 11 | 2. Redistributions in binary form must reproduce the above copyright notice, 12 | this list of conditions and the following disclaimer in the documentation 13 | and/or other materials provided with the distribution. 14 | 15 | 3. Neither the name of the copyright holder nor the names of its 16 | contributors may be used to endorse or promote products derived from 17 | this software without specific prior written permission. 18 | 19 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 22 | DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 23 | FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 | DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 25 | SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 26 | CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 27 | OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 28 | OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 | -------------------------------------------------------------------------------- /pdn.tcl: -------------------------------------------------------------------------------- 1 | # based on ORFS/platforms/asap7/openRoad/pdn/BLOCK_grid_strategy.tcl, 2 | # but added power higher up 3 | 4 | #################################### 5 | # global connections 6 | #################################### 7 | add_global_connection -net {VDD} -inst_pattern {.*} -pin_pattern {^VDD$} -power 8 | add_global_connection -net {VSS} -inst_pattern {.*} -pin_pattern {^VSS$} -ground 9 | 10 | #################################### 11 | # voltage domains 12 | #################################### 13 | set_voltage_domain -name {CORE} -power {VDD} -ground {VSS} 14 | 15 | #################################### 16 | # standard cell grid 17 | # M1 M2 are for follow pin, width derived from PG rail in standard cell 18 | # M5 stripe width rerived from one of width allowed in LEF, offset and pitch 19 | # put stripe on M5 track 20 | # M4 M5 ring follow stripe width 21 | #################################### 22 | define_pdn_grid -name {top} -voltage_domains {CORE} 23 | 24 | add_pdn_ring -grid {top} -layers {M5 M4} -widths {0.12 0.12} -spacings {0.072} -core_offset {0.084} 25 | 26 | add_pdn_stripe -grid {top} -layer {M1} -width {0.018} -pitch {0.54} -offset {0} -followpins 27 | add_pdn_stripe -grid {top} -layer {M2} -width {0.018} -pitch {0.54} -offset {0} -followpins 28 | 29 | add_pdn_stripe -grid {top} -layer {M5} -width {0.12} -spacing {0.072} -pitch {2.976} -offset {1.5} -extend_to_core_ring 30 | 31 | add_pdn_connect -grid {top} -layers {M1 M2} 32 | add_pdn_connect -grid {top} -layers {M2 M5} 33 | add_pdn_connect -grid {top} -layers {M4 M5} 34 | # allow routing at all metal levels 35 | add_pdn_connect -grid {top} -layers {M5 M9} 36 | -------------------------------------------------------------------------------- /rtl/OptimizationBarrier_93.sv: -------------------------------------------------------------------------------- 1 | // Standard header to adapt well known macros for prints and assertions. 2 | 3 | // Users can define 'ASSERT_VERBOSE_COND' to add an extra gate to assert error printing. 4 | `ifndef ASSERT_VERBOSE_COND_ 5 | `ifdef ASSERT_VERBOSE_COND 6 | `define ASSERT_VERBOSE_COND_ (`ASSERT_VERBOSE_COND) 7 | `else // ASSERT_VERBOSE_COND 8 | `define ASSERT_VERBOSE_COND_ 1 9 | `endif // ASSERT_VERBOSE_COND 10 | `endif // not def ASSERT_VERBOSE_COND_ 11 | 12 | // Users can define 'STOP_COND' to add an extra gate to stop conditions. 13 | `ifndef STOP_COND_ 14 | `ifdef STOP_COND 15 | `define STOP_COND_ (`STOP_COND) 16 | `else // STOP_COND 17 | `define STOP_COND_ 1 18 | `endif // STOP_COND 19 | `endif // not def STOP_COND_ 20 | 21 | module OptimizationBarrier_93( 22 | input [43:0] io_x_ppn, 23 | input io_x_d, 24 | io_x_a, 25 | io_x_g, 26 | io_x_u, 27 | io_x_x, 28 | io_x_w, 29 | io_x_r, 30 | io_x_v, 31 | output [43:0] io_y_ppn, 32 | output io_y_d, 33 | io_y_a, 34 | io_y_g, 35 | io_y_u, 36 | io_y_x, 37 | io_y_w, 38 | io_y_r, 39 | io_y_v 40 | ); 41 | 42 | assign io_y_ppn = io_x_ppn; 43 | assign io_y_d = io_x_d; 44 | assign io_y_a = io_x_a; 45 | assign io_y_g = io_x_g; 46 | assign io_y_u = io_x_u; 47 | assign io_y_x = io_x_x; 48 | assign io_y_w = io_x_w; 49 | assign io_y_r = io_x_r; 50 | assign io_y_v = io_x_v; 51 | endmodule 52 | 53 | -------------------------------------------------------------------------------- /rtl/RoundRawFNToRecFN.sv: -------------------------------------------------------------------------------- 1 | // Standard header to adapt well known macros for prints and assertions. 2 | 3 | // Users can define 'ASSERT_VERBOSE_COND' to add an extra gate to assert error printing. 4 | `ifndef ASSERT_VERBOSE_COND_ 5 | `ifdef ASSERT_VERBOSE_COND 6 | `define ASSERT_VERBOSE_COND_ (`ASSERT_VERBOSE_COND) 7 | `else // ASSERT_VERBOSE_COND 8 | `define ASSERT_VERBOSE_COND_ 1 9 | `endif // ASSERT_VERBOSE_COND 10 | `endif // not def ASSERT_VERBOSE_COND_ 11 | 12 | // Users can define 'STOP_COND' to add an extra gate to stop conditions. 13 | `ifndef STOP_COND_ 14 | `ifdef STOP_COND 15 | `define STOP_COND_ (`STOP_COND) 16 | `else // STOP_COND 17 | `define STOP_COND_ 1 18 | `endif // STOP_COND 19 | `endif // not def STOP_COND_ 20 | 21 | module RoundRawFNToRecFN( 22 | input io_invalidExc, 23 | io_in_isNaN, 24 | io_in_isInf, 25 | io_in_isZero, 26 | io_in_sign, 27 | input [12:0] io_in_sExp, 28 | input [55:0] io_in_sig, 29 | input [2:0] io_roundingMode, 30 | output [64:0] io_out, 31 | output [4:0] io_exceptionFlags 32 | ); 33 | 34 | RoundAnyRawFNToRecFN_2 roundAnyRawFNToRecFN ( 35 | .io_invalidExc (io_invalidExc), 36 | .io_in_isNaN (io_in_isNaN), 37 | .io_in_isInf (io_in_isInf), 38 | .io_in_isZero (io_in_isZero), 39 | .io_in_sign (io_in_sign), 40 | .io_in_sExp (io_in_sExp), 41 | .io_in_sig (io_in_sig), 42 | .io_roundingMode (io_roundingMode), 43 | .io_out (io_out), 44 | .io_exceptionFlags (io_exceptionFlags) 45 | ); 46 | endmodule 47 | 48 | -------------------------------------------------------------------------------- /rtl/RecFNToRecFN.sv: -------------------------------------------------------------------------------- 1 | // Standard header to adapt well known macros for prints and assertions. 2 | 3 | // Users can define 'ASSERT_VERBOSE_COND' to add an extra gate to assert error printing. 4 | `ifndef ASSERT_VERBOSE_COND_ 5 | `ifdef ASSERT_VERBOSE_COND 6 | `define ASSERT_VERBOSE_COND_ (`ASSERT_VERBOSE_COND) 7 | `else // ASSERT_VERBOSE_COND 8 | `define ASSERT_VERBOSE_COND_ 1 9 | `endif // ASSERT_VERBOSE_COND 10 | `endif // not def ASSERT_VERBOSE_COND_ 11 | 12 | // Users can define 'STOP_COND' to add an extra gate to stop conditions. 13 | `ifndef STOP_COND_ 14 | `ifdef STOP_COND 15 | `define STOP_COND_ (`STOP_COND) 16 | `else // STOP_COND 17 | `define STOP_COND_ 1 18 | `endif // STOP_COND 19 | `endif // not def STOP_COND_ 20 | 21 | module RecFNToRecFN( 22 | input [64:0] io_in, 23 | input [2:0] io_roundingMode, 24 | input io_detectTininess, 25 | output [32:0] io_out, 26 | output [4:0] io_exceptionFlags 27 | ); 28 | 29 | wire rawIn_isNaN = (&(io_in[63:62])) & io_in[61]; 30 | RoundAnyRawFNToRecFN_4 roundAnyRawFNToRecFN ( 31 | .io_invalidExc (rawIn_isNaN & ~(io_in[51])), 32 | .io_in_isNaN (rawIn_isNaN), 33 | .io_in_isInf ((&(io_in[63:62])) & ~(io_in[61])), 34 | .io_in_isZero (~(|(io_in[63:61]))), 35 | .io_in_sign (io_in[64]), 36 | .io_in_sExp ({1'h0, io_in[63:52]}), 37 | .io_in_sig ({1'h0, |(io_in[63:61]), io_in[51:0]}), 38 | .io_roundingMode (io_roundingMode), 39 | .io_detectTininess (io_detectTininess), 40 | .io_out (io_out), 41 | .io_exceptionFlags (io_exceptionFlags) 42 | ); 43 | endmodule 44 | 45 | -------------------------------------------------------------------------------- /rtl/RoundRawFNToRecFN_1.sv: -------------------------------------------------------------------------------- 1 | // Standard header to adapt well known macros for prints and assertions. 2 | 3 | // Users can define 'ASSERT_VERBOSE_COND' to add an extra gate to assert error printing. 4 | `ifndef ASSERT_VERBOSE_COND_ 5 | `ifdef ASSERT_VERBOSE_COND 6 | `define ASSERT_VERBOSE_COND_ (`ASSERT_VERBOSE_COND) 7 | `else // ASSERT_VERBOSE_COND 8 | `define ASSERT_VERBOSE_COND_ 1 9 | `endif // ASSERT_VERBOSE_COND 10 | `endif // not def ASSERT_VERBOSE_COND_ 11 | 12 | // Users can define 'STOP_COND' to add an extra gate to stop conditions. 13 | `ifndef STOP_COND_ 14 | `ifdef STOP_COND 15 | `define STOP_COND_ (`STOP_COND) 16 | `else // STOP_COND 17 | `define STOP_COND_ 1 18 | `endif // STOP_COND 19 | `endif // not def STOP_COND_ 20 | 21 | module RoundRawFNToRecFN_1( 22 | input io_invalidExc, 23 | io_in_isNaN, 24 | io_in_isInf, 25 | io_in_isZero, 26 | io_in_sign, 27 | input [9:0] io_in_sExp, 28 | input [26:0] io_in_sig, 29 | input [2:0] io_roundingMode, 30 | output [32:0] io_out, 31 | output [4:0] io_exceptionFlags 32 | ); 33 | 34 | RoundAnyRawFNToRecFN_3 roundAnyRawFNToRecFN ( 35 | .io_invalidExc (io_invalidExc), 36 | .io_in_isNaN (io_in_isNaN), 37 | .io_in_isInf (io_in_isInf), 38 | .io_in_isZero (io_in_isZero), 39 | .io_in_sign (io_in_sign), 40 | .io_in_sExp (io_in_sExp), 41 | .io_in_sig (io_in_sig), 42 | .io_roundingMode (io_roundingMode), 43 | .io_out (io_out), 44 | .io_exceptionFlags (io_exceptionFlags) 45 | ); 46 | endmodule 47 | 48 | -------------------------------------------------------------------------------- /rtl/array_256x128.sv: -------------------------------------------------------------------------------- 1 | // Standard header to adapt well known macros for prints and assertions. 2 | 3 | // Users can define 'ASSERT_VERBOSE_COND' to add an extra gate to assert error printing. 4 | `ifndef ASSERT_VERBOSE_COND_ 5 | `ifdef ASSERT_VERBOSE_COND 6 | `define ASSERT_VERBOSE_COND_ (`ASSERT_VERBOSE_COND) 7 | `else // ASSERT_VERBOSE_COND 8 | `define ASSERT_VERBOSE_COND_ 1 9 | `endif // ASSERT_VERBOSE_COND 10 | `endif // not def ASSERT_VERBOSE_COND_ 11 | 12 | // Users can define 'STOP_COND' to add an extra gate to stop conditions. 13 | `ifndef STOP_COND_ 14 | `ifdef STOP_COND 15 | `define STOP_COND_ (`STOP_COND) 16 | `else // STOP_COND 17 | `define STOP_COND_ 1 18 | `endif // STOP_COND 19 | `endif // not def STOP_COND_ 20 | 21 | // VCS coverage exclude_file 22 | module array_256x128( 23 | input [7:0] R0_addr, 24 | input R0_en, 25 | R0_clk, 26 | output [127:0] R0_data, 27 | input [7:0] W0_addr, 28 | input W0_en, 29 | W0_clk, 30 | input [127:0] W0_data, 31 | input [1:0] W0_mask 32 | ); 33 | 34 | reg [127:0] Memory[0:255]; 35 | reg _R0_en_d0; 36 | reg [7:0] _R0_addr_d0; 37 | always @(posedge R0_clk) begin 38 | _R0_en_d0 <= R0_en; 39 | _R0_addr_d0 <= R0_addr; 40 | end // always @(posedge) 41 | always @(posedge W0_clk) begin 42 | if (W0_en & W0_mask[0]) 43 | Memory[W0_addr][32'h0 +: 64] <= W0_data[63:0]; 44 | if (W0_en & W0_mask[1]) 45 | Memory[W0_addr][32'h40 +: 64] <= W0_data[127:64]; 46 | end // always @(posedge) 47 | assign R0_data = _R0_en_d0 ? Memory[_R0_addr_d0] : 128'bx; 48 | endmodule 49 | 50 | -------------------------------------------------------------------------------- /rtl/FixedClockBroadcast_3.sv: -------------------------------------------------------------------------------- 1 | // Standard header to adapt well known macros for prints and assertions. 2 | 3 | // Users can define 'ASSERT_VERBOSE_COND' to add an extra gate to assert error printing. 4 | `ifndef ASSERT_VERBOSE_COND_ 5 | `ifdef ASSERT_VERBOSE_COND 6 | `define ASSERT_VERBOSE_COND_ (`ASSERT_VERBOSE_COND) 7 | `else // ASSERT_VERBOSE_COND 8 | `define ASSERT_VERBOSE_COND_ 1 9 | `endif // ASSERT_VERBOSE_COND 10 | `endif // not def ASSERT_VERBOSE_COND_ 11 | 12 | // Users can define 'STOP_COND' to add an extra gate to stop conditions. 13 | `ifndef STOP_COND_ 14 | `ifdef STOP_COND 15 | `define STOP_COND_ (`STOP_COND) 16 | `else // STOP_COND 17 | `define STOP_COND_ 1 18 | `endif // STOP_COND 19 | `endif // not def STOP_COND_ 20 | 21 | module FixedClockBroadcast_3( 22 | input auto_in_clock, 23 | auto_in_reset, 24 | output auto_out_5_clock, 25 | auto_out_5_reset, 26 | auto_out_4_clock, 27 | auto_out_4_reset, 28 | auto_out_3_clock, 29 | auto_out_3_reset, 30 | auto_out_1_clock, 31 | auto_out_1_reset, 32 | auto_out_0_clock, 33 | auto_out_0_reset 34 | ); 35 | 36 | assign auto_out_5_clock = auto_in_clock; 37 | assign auto_out_5_reset = auto_in_reset; 38 | assign auto_out_4_clock = auto_in_clock; 39 | assign auto_out_4_reset = auto_in_reset; 40 | assign auto_out_3_clock = auto_in_clock; 41 | assign auto_out_3_reset = auto_in_reset; 42 | assign auto_out_1_clock = auto_in_clock; 43 | assign auto_out_1_reset = auto_in_reset; 44 | assign auto_out_0_clock = auto_in_clock; 45 | assign auto_out_0_reset = auto_in_reset; 46 | endmodule 47 | 48 | -------------------------------------------------------------------------------- /docker/Dockerfile.dev: -------------------------------------------------------------------------------- 1 | # syntax=docker/dockerfile:1 2 | 3 | FROM ubuntu:22.04 4 | 5 | # Install packages as root 6 | # Install bazel 7 | RUN apt update && apt upgrade -y 8 | RUN apt install apt-transport-https curl gnupg -y 9 | RUN curl -fsSL https://bazel.build/bazel-release.pub.gpg | gpg --dearmor > bazel-archive-keyring.gpg 10 | RUN mv bazel-archive-keyring.gpg /usr/share/keyrings 11 | RUN echo "deb [arch=amd64 signed-by=/usr/share/keyrings/bazel-archive-keyring.gpg] https://storage.googleapis.com/bazel-apt stable jdk1.8" | tee /etc/apt/sources.list.d/bazel.list 12 | RUN apt update 13 | RUN curl -L https://github.com/bazelbuild/bazelisk/releases/download/v1.22.0/bazelisk-linux-amd64 -o /usr/bin/bazelisk && chmod +x /usr/bin/bazelisk 14 | RUN ln -s /usr/bin/bazelisk /usr/bin/bazel 15 | 16 | # install gcloud 17 | RUN curl https://packages.cloud.google.com/apt/doc/apt-key.gpg | gpg --dearmor -o /usr/share/keyrings/cloud.google.gpg 18 | RUN echo "deb [signed-by=/usr/share/keyrings/cloud.google.gpg] https://packages.cloud.google.com/apt cloud-sdk main" | tee -a /etc/apt/sources.list.d/google-cloud-sdk.list 19 | RUN apt update 20 | RUN apt install google-cloud-cli -y 21 | 22 | RUN apt install time podman-docker git python3 python3-pip -y 23 | RUN pip3 install tabulate 24 | 25 | # Create gcloud config directories in /tmp 26 | RUN mkdir -p /tmp/.config/gcloud 27 | RUN chmod -R 777 /tmp/.config 28 | 29 | # copy .bazelrc into root's home dir 30 | COPY docker/bazelrc /tmp/.bazelrc 31 | 32 | # set up builduser UID of 1016:1017 33 | # name is required for bazel to run the build 34 | RUN groupadd --gid 1017 buildgroup 35 | RUN useradd --gid buildgroup --uid 1016 -ms /bin/bash builduser 36 | -------------------------------------------------------------------------------- /rtl/BroadcastFilter.sv: -------------------------------------------------------------------------------- 1 | // Standard header to adapt well known macros for prints and assertions. 2 | 3 | // Users can define 'ASSERT_VERBOSE_COND' to add an extra gate to assert error printing. 4 | `ifndef ASSERT_VERBOSE_COND_ 5 | `ifdef ASSERT_VERBOSE_COND 6 | `define ASSERT_VERBOSE_COND_ (`ASSERT_VERBOSE_COND) 7 | `else // ASSERT_VERBOSE_COND 8 | `define ASSERT_VERBOSE_COND_ 1 9 | `endif // ASSERT_VERBOSE_COND 10 | `endif // not def ASSERT_VERBOSE_COND_ 11 | 12 | // Users can define 'STOP_COND' to add an extra gate to stop conditions. 13 | `ifndef STOP_COND_ 14 | `ifdef STOP_COND 15 | `define STOP_COND_ (`STOP_COND) 16 | `else // STOP_COND 17 | `define STOP_COND_ 1 18 | `endif // STOP_COND 19 | `endif // not def STOP_COND_ 20 | 21 | module BroadcastFilter( 22 | output io_request_ready, 23 | input io_request_valid, 24 | input [1:0] io_request_bits_mshr, 25 | input [32:0] io_request_bits_address, 26 | input io_request_bits_allocOH, 27 | io_request_bits_needT, 28 | io_response_ready, 29 | output io_response_valid, 30 | output [1:0] io_response_bits_mshr, 31 | output [32:0] io_response_bits_address, 32 | output io_response_bits_allocOH, 33 | io_response_bits_needT 34 | ); 35 | 36 | assign io_request_ready = io_response_ready; 37 | assign io_response_valid = io_request_valid; 38 | assign io_response_bits_mshr = io_request_bits_mshr; 39 | assign io_response_bits_address = io_request_bits_address; 40 | assign io_response_bits_allocOH = io_request_bits_allocOH; 41 | assign io_response_bits_needT = io_request_bits_needT; 42 | endmodule 43 | 44 | -------------------------------------------------------------------------------- /rtl/RoundRawFNToRecFN_2.sv: -------------------------------------------------------------------------------- 1 | // Standard header to adapt well known macros for prints and assertions. 2 | 3 | // Users can define 'ASSERT_VERBOSE_COND' to add an extra gate to assert error printing. 4 | `ifndef ASSERT_VERBOSE_COND_ 5 | `ifdef ASSERT_VERBOSE_COND 6 | `define ASSERT_VERBOSE_COND_ (`ASSERT_VERBOSE_COND) 7 | `else // ASSERT_VERBOSE_COND 8 | `define ASSERT_VERBOSE_COND_ 1 9 | `endif // ASSERT_VERBOSE_COND 10 | `endif // not def ASSERT_VERBOSE_COND_ 11 | 12 | // Users can define 'STOP_COND' to add an extra gate to stop conditions. 13 | `ifndef STOP_COND_ 14 | `ifdef STOP_COND 15 | `define STOP_COND_ (`STOP_COND) 16 | `else // STOP_COND 17 | `define STOP_COND_ 1 18 | `endif // STOP_COND 19 | `endif // not def STOP_COND_ 20 | 21 | module RoundRawFNToRecFN_2( 22 | input io_invalidExc, 23 | io_infiniteExc, 24 | io_in_isNaN, 25 | io_in_isInf, 26 | io_in_isZero, 27 | io_in_sign, 28 | input [12:0] io_in_sExp, 29 | input [55:0] io_in_sig, 30 | input [2:0] io_roundingMode, 31 | output [64:0] io_out, 32 | output [4:0] io_exceptionFlags 33 | ); 34 | 35 | RoundAnyRawFNToRecFN_7 roundAnyRawFNToRecFN ( 36 | .io_invalidExc (io_invalidExc), 37 | .io_infiniteExc (io_infiniteExc), 38 | .io_in_isNaN (io_in_isNaN), 39 | .io_in_isInf (io_in_isInf), 40 | .io_in_isZero (io_in_isZero), 41 | .io_in_sign (io_in_sign), 42 | .io_in_sExp (io_in_sExp), 43 | .io_in_sig (io_in_sig), 44 | .io_roundingMode (io_roundingMode), 45 | .io_out (io_out), 46 | .io_exceptionFlags (io_exceptionFlags) 47 | ); 48 | endmodule 49 | 50 | -------------------------------------------------------------------------------- /rtl/UOPCodeFDivDecoder.sv: -------------------------------------------------------------------------------- 1 | // Standard header to adapt well known macros for prints and assertions. 2 | 3 | // Users can define 'ASSERT_VERBOSE_COND' to add an extra gate to assert error printing. 4 | `ifndef ASSERT_VERBOSE_COND_ 5 | `ifdef ASSERT_VERBOSE_COND 6 | `define ASSERT_VERBOSE_COND_ (`ASSERT_VERBOSE_COND) 7 | `else // ASSERT_VERBOSE_COND 8 | `define ASSERT_VERBOSE_COND_ 1 9 | `endif // ASSERT_VERBOSE_COND 10 | `endif // not def ASSERT_VERBOSE_COND_ 11 | 12 | // Users can define 'STOP_COND' to add an extra gate to stop conditions. 13 | `ifndef STOP_COND_ 14 | `ifdef STOP_COND 15 | `define STOP_COND_ (`STOP_COND) 16 | `else // STOP_COND 17 | `define STOP_COND_ 1 18 | `endif // STOP_COND 19 | `endif // not def STOP_COND_ 20 | 21 | module UOPCodeFDivDecoder( 22 | input [6:0] io_uopc, 23 | output [1:0] io_sigs_typeTagIn, 24 | output io_sigs_div, 25 | io_sigs_sqrt 26 | ); 27 | 28 | wire [4:0] decoder_decoded_invInputs = ~(io_uopc[4:0]); 29 | wire [6:0] _decoder_decoded_T_2 = {decoder_decoded_invInputs[0], io_uopc[1], io_uopc[2], decoder_decoded_invInputs[3], decoder_decoded_invInputs[4], io_uopc[5], io_uopc[6]}; 30 | wire [3:0] _decoder_decoded_T_6 = {io_uopc[3], decoder_decoded_invInputs[4], io_uopc[5], io_uopc[6]}; 31 | assign io_sigs_typeTagIn = {1'h0, |{&_decoder_decoded_T_2, &_decoder_decoded_T_6}}; 32 | assign io_sigs_div = |{&{decoder_decoded_invInputs[1], io_uopc[2], decoder_decoded_invInputs[3], decoder_decoded_invInputs[4], io_uopc[5], io_uopc[6]}, &_decoder_decoded_T_2}; 33 | assign io_sigs_sqrt = |{&{io_uopc[0], io_uopc[1], io_uopc[2], decoder_decoded_invInputs[3], decoder_decoded_invInputs[4], io_uopc[5], io_uopc[6]}, &_decoder_decoded_T_6}; 34 | endmodule 35 | 36 | -------------------------------------------------------------------------------- /rtl/Mul54.sv: -------------------------------------------------------------------------------- 1 | // Standard header to adapt well known macros for prints and assertions. 2 | 3 | // Users can define 'ASSERT_VERBOSE_COND' to add an extra gate to assert error printing. 4 | `ifndef ASSERT_VERBOSE_COND_ 5 | `ifdef ASSERT_VERBOSE_COND 6 | `define ASSERT_VERBOSE_COND_ (`ASSERT_VERBOSE_COND) 7 | `else // ASSERT_VERBOSE_COND 8 | `define ASSERT_VERBOSE_COND_ 1 9 | `endif // ASSERT_VERBOSE_COND 10 | `endif // not def ASSERT_VERBOSE_COND_ 11 | 12 | // Users can define 'STOP_COND' to add an extra gate to stop conditions. 13 | `ifndef STOP_COND_ 14 | `ifdef STOP_COND 15 | `define STOP_COND_ (`STOP_COND) 16 | `else // STOP_COND 17 | `define STOP_COND_ 1 18 | `endif // STOP_COND 19 | `endif // not def STOP_COND_ 20 | 21 | module Mul54( 22 | input clock, 23 | io_val_s0, 24 | io_latch_a_s0, 25 | input [53:0] io_a_s0, 26 | input io_latch_b_s0, 27 | input [53:0] io_b_s0, 28 | input [104:0] io_c_s2, 29 | output [104:0] io_result_s3 30 | ); 31 | 32 | reg val_s1; 33 | reg val_s2; 34 | reg [53:0] reg_a_s1; 35 | reg [53:0] reg_b_s1; 36 | reg [53:0] reg_a_s2; 37 | reg [53:0] reg_b_s2; 38 | reg [104:0] reg_result_s3; 39 | always @(posedge clock) begin 40 | val_s1 <= io_val_s0; 41 | val_s2 <= val_s1; 42 | if (io_val_s0 & io_latch_a_s0) 43 | reg_a_s1 <= io_a_s0; 44 | if (io_val_s0 & io_latch_b_s0) 45 | reg_b_s1 <= io_b_s0; 46 | if (val_s1) begin 47 | reg_a_s2 <= reg_a_s1; 48 | reg_b_s2 <= reg_b_s1; 49 | end 50 | if (val_s2) 51 | reg_result_s3 <= {51'h0, reg_a_s2} * {51'h0, reg_b_s2} + io_c_s2; 52 | end // always @(posedge) 53 | assign io_result_s3 = reg_result_s3; 54 | endmodule 55 | 56 | -------------------------------------------------------------------------------- /rtl/mem_128x4.sv: -------------------------------------------------------------------------------- 1 | // Standard header to adapt well known macros for prints and assertions. 2 | 3 | // Users can define 'ASSERT_VERBOSE_COND' to add an extra gate to assert error printing. 4 | `ifndef ASSERT_VERBOSE_COND_ 5 | `ifdef ASSERT_VERBOSE_COND 6 | `define ASSERT_VERBOSE_COND_ (`ASSERT_VERBOSE_COND) 7 | `else // ASSERT_VERBOSE_COND 8 | `define ASSERT_VERBOSE_COND_ 1 9 | `endif // ASSERT_VERBOSE_COND 10 | `endif // not def ASSERT_VERBOSE_COND_ 11 | 12 | // Users can define 'STOP_COND' to add an extra gate to stop conditions. 13 | `ifndef STOP_COND_ 14 | `ifdef STOP_COND 15 | `define STOP_COND_ (`STOP_COND) 16 | `else // STOP_COND 17 | `define STOP_COND_ 1 18 | `endif // STOP_COND 19 | `endif // not def STOP_COND_ 20 | 21 | // VCS coverage exclude_file 22 | module mem_128x4( 23 | input [6:0] R0_addr, 24 | input R0_en, 25 | R0_clk, 26 | output [3:0] R0_data, 27 | input [6:0] W0_addr, 28 | input W0_en, 29 | W0_clk, 30 | input [3:0] W0_data, 31 | W0_mask 32 | ); 33 | 34 | reg [3:0] Memory[0:127]; 35 | reg _R0_en_d0; 36 | reg [6:0] _R0_addr_d0; 37 | always @(posedge R0_clk) begin 38 | _R0_en_d0 <= R0_en; 39 | _R0_addr_d0 <= R0_addr; 40 | end // always @(posedge) 41 | always @(posedge W0_clk) begin 42 | if (W0_en & W0_mask[0]) 43 | Memory[W0_addr][32'h0 +: 1] <= W0_data[0]; 44 | if (W0_en & W0_mask[1]) 45 | Memory[W0_addr][32'h1 +: 1] <= W0_data[1]; 46 | if (W0_en & W0_mask[2]) 47 | Memory[W0_addr][32'h2 +: 1] <= W0_data[2]; 48 | if (W0_en & W0_mask[3]) 49 | Memory[W0_addr][32'h3 +: 1] <= W0_data[3]; 50 | end // always @(posedge) 51 | assign R0_data = _R0_en_d0 ? Memory[_R0_addr_d0] : 4'bx; 52 | endmodule 53 | 54 | -------------------------------------------------------------------------------- /rtl/mem_256x4.sv: -------------------------------------------------------------------------------- 1 | // Standard header to adapt well known macros for prints and assertions. 2 | 3 | // Users can define 'ASSERT_VERBOSE_COND' to add an extra gate to assert error printing. 4 | `ifndef ASSERT_VERBOSE_COND_ 5 | `ifdef ASSERT_VERBOSE_COND 6 | `define ASSERT_VERBOSE_COND_ (`ASSERT_VERBOSE_COND) 7 | `else // ASSERT_VERBOSE_COND 8 | `define ASSERT_VERBOSE_COND_ 1 9 | `endif // ASSERT_VERBOSE_COND 10 | `endif // not def ASSERT_VERBOSE_COND_ 11 | 12 | // Users can define 'STOP_COND' to add an extra gate to stop conditions. 13 | `ifndef STOP_COND_ 14 | `ifdef STOP_COND 15 | `define STOP_COND_ (`STOP_COND) 16 | `else // STOP_COND 17 | `define STOP_COND_ 1 18 | `endif // STOP_COND 19 | `endif // not def STOP_COND_ 20 | 21 | // VCS coverage exclude_file 22 | module mem_256x4( 23 | input [7:0] R0_addr, 24 | input R0_en, 25 | R0_clk, 26 | output [3:0] R0_data, 27 | input [7:0] W0_addr, 28 | input W0_en, 29 | W0_clk, 30 | input [3:0] W0_data, 31 | W0_mask 32 | ); 33 | 34 | reg [3:0] Memory[0:255]; 35 | reg _R0_en_d0; 36 | reg [7:0] _R0_addr_d0; 37 | always @(posedge R0_clk) begin 38 | _R0_en_d0 <= R0_en; 39 | _R0_addr_d0 <= R0_addr; 40 | end // always @(posedge) 41 | always @(posedge W0_clk) begin 42 | if (W0_en & W0_mask[0]) 43 | Memory[W0_addr][32'h0 +: 1] <= W0_data[0]; 44 | if (W0_en & W0_mask[1]) 45 | Memory[W0_addr][32'h1 +: 1] <= W0_data[1]; 46 | if (W0_en & W0_mask[2]) 47 | Memory[W0_addr][32'h2 +: 1] <= W0_data[2]; 48 | if (W0_en & W0_mask[3]) 49 | Memory[W0_addr][32'h3 +: 1] <= W0_data[3]; 50 | end // always @(posedge) 51 | assign R0_data = _R0_en_d0 ? Memory[_R0_addr_d0] : 4'bx; 52 | endmodule 53 | 54 | -------------------------------------------------------------------------------- /rtl/testchip_tsi.cc: -------------------------------------------------------------------------------- 1 | #include "testchip_tsi.h" 2 | #include 3 | 4 | testchip_tsi_t::testchip_tsi_t(int argc, char** argv, bool can_have_loadmem) : tsi_t(argc, argv) 5 | { 6 | has_loadmem = false; 7 | init_accesses = std::vector(); 8 | write_hart0_msip = true; 9 | is_loadmem = false; 10 | cflush_addr = 0; 11 | std::vector args(argv + 1, argv + argc); 12 | for (auto& arg : args) { 13 | if (arg.find("+loadmem=") == 0) 14 | has_loadmem = can_have_loadmem; 15 | if (arg.find("+cflush_addr=0x") == 0) 16 | cflush_addr = strtoull(arg.substr(15).c_str(), 0, 16); 17 | } 18 | 19 | testchip_htif_t::parse_htif_args(args); 20 | } 21 | 22 | void testchip_tsi_t::flush_cache_lines(addr_t taddr, size_t nbytes) { 23 | if (!cflush_addr) return; 24 | static size_t cblock_bytes = 64; 25 | size_t base = taddr & ~(cblock_bytes-1); 26 | while (base < taddr + nbytes) { 27 | uint32_t data[2] { base, base >> 32 }; 28 | tsi_t::write_chunk(cflush_addr, 8, data); 29 | base += cblock_bytes; 30 | } 31 | } 32 | 33 | void testchip_tsi_t::write_chunk(addr_t taddr, size_t nbytes, const void* src) 34 | { 35 | if (is_loadmem) { 36 | load_mem_write(taddr, nbytes, src); 37 | } else { 38 | flush_cache_lines(taddr, nbytes); 39 | tsi_t::write_chunk(taddr, nbytes, src); 40 | } 41 | } 42 | 43 | void testchip_tsi_t::read_chunk(addr_t taddr, size_t nbytes, void* dst) 44 | { 45 | if (is_loadmem) { 46 | load_mem_read(taddr, nbytes, dst); 47 | } else { 48 | flush_cache_lines(taddr, nbytes); 49 | tsi_t::read_chunk(taddr, nbytes, dst); 50 | } 51 | } 52 | 53 | void testchip_tsi_t::reset() 54 | { 55 | testchip_htif_t::perform_init_accesses(); 56 | if (write_hart0_msip) 57 | tsi_t::reset(); 58 | } 59 | -------------------------------------------------------------------------------- /rtl/JtagBypassChain.sv: -------------------------------------------------------------------------------- 1 | // Standard header to adapt well known macros for prints and assertions. 2 | 3 | // Users can define 'ASSERT_VERBOSE_COND' to add an extra gate to assert error printing. 4 | `ifndef ASSERT_VERBOSE_COND_ 5 | `ifdef ASSERT_VERBOSE_COND 6 | `define ASSERT_VERBOSE_COND_ (`ASSERT_VERBOSE_COND) 7 | `else // ASSERT_VERBOSE_COND 8 | `define ASSERT_VERBOSE_COND_ 1 9 | `endif // ASSERT_VERBOSE_COND 10 | `endif // not def ASSERT_VERBOSE_COND_ 11 | 12 | // Users can define 'STOP_COND' to add an extra gate to stop conditions. 13 | `ifndef STOP_COND_ 14 | `ifdef STOP_COND 15 | `define STOP_COND_ (`STOP_COND) 16 | `else // STOP_COND 17 | `define STOP_COND_ 1 18 | `endif // STOP_COND 19 | `endif // not def STOP_COND_ 20 | 21 | module JtagBypassChain( 22 | input clock, 23 | reset, 24 | io_chainIn_shift, 25 | io_chainIn_data, 26 | io_chainIn_capture, 27 | io_chainIn_update, 28 | output io_chainOut_data 29 | ); 30 | 31 | reg reg_0; 32 | `ifndef SYNTHESIS 33 | always @(posedge clock) begin 34 | if (~reset & ~(~(io_chainIn_capture & io_chainIn_update) & ~(io_chainIn_capture & io_chainIn_shift) & ~(io_chainIn_update & io_chainIn_shift))) begin 35 | if (`ASSERT_VERBOSE_COND_) 36 | $error("Assertion failed\n at JtagShifter.scala:72 assert(!(io.chainIn.capture && io.chainIn.update)\n"); 37 | if (`STOP_COND_) 38 | $fatal; 39 | end 40 | end // always @(posedge) 41 | `endif // not def SYNTHESIS 42 | always @(posedge clock) begin 43 | if (io_chainIn_capture) 44 | reg_0 <= 1'h0; 45 | else if (io_chainIn_shift) 46 | reg_0 <= io_chainIn_data; 47 | end // always @(posedge) 48 | assign io_chainOut_data = reg_0; 49 | endmodule 50 | 51 | -------------------------------------------------------------------------------- /util.tcl: -------------------------------------------------------------------------------- 1 | # Helper function to split a string into a list of strings and numbers 2 | proc split_strings_and_numbers {str} { 3 | set result {} 4 | foreach {all letters numbers} [regexp -all -inline {(\D*)(\d*)} $str] { 5 | if {$letters ne ""} { 6 | lappend result $letters 7 | } 8 | if {$numbers ne ""} { 9 | lappend result [expr {$numbers + 0}] ;# Convert to integer 10 | } 11 | } 12 | return $result 13 | } 14 | 15 | # Custom comparison function 16 | proc natural_compare {str1 str2} { 17 | set list1 [split_strings_and_numbers $str1] 18 | set list2 [split_strings_and_numbers $str2] 19 | set len [expr {min([llength $list1], [llength $list2])}] 20 | for {set i 0} {$i < $len} {incr i} { 21 | set part1 [lindex $list1 $i] 22 | set part2 [lindex $list2 $i] 23 | if {$part1 ne $part2} { 24 | if {[string is integer -strict $part1] && [string is integer -strict $part2]} { 25 | return [expr {$part1 - $part2}] 26 | } else { 27 | return [string compare $part1 $part2] 28 | } 29 | } 30 | } 31 | return [expr {[llength $list1] - [llength $list2]}] ;# If all parts are equal, compare by length 32 | } 33 | 34 | proc natural_sort {list} { 35 | return [lsort -command natural_compare $list] 36 | } 37 | 38 | proc match_pins { regex } { 39 | set pins {} 40 | # The regex for get_ports is not the tcl regex 41 | foreach pin [get_ports -regex .*] { 42 | set input [get_property $pin name] 43 | # We want the Tcl regex 44 | if {![regexp $regex $input]} { 45 | continue 46 | } 47 | lappend pins [get_property $pin name] 48 | } 49 | return [natural_sort $pins] 50 | } 51 | -------------------------------------------------------------------------------- /rtl/FMADecoder.sv: -------------------------------------------------------------------------------- 1 | // Standard header to adapt well known macros for prints and assertions. 2 | 3 | // Users can define 'ASSERT_VERBOSE_COND' to add an extra gate to assert error printing. 4 | `ifndef ASSERT_VERBOSE_COND_ 5 | `ifdef ASSERT_VERBOSE_COND 6 | `define ASSERT_VERBOSE_COND_ (`ASSERT_VERBOSE_COND) 7 | `else // ASSERT_VERBOSE_COND 8 | `define ASSERT_VERBOSE_COND_ 1 9 | `endif // ASSERT_VERBOSE_COND 10 | `endif // not def ASSERT_VERBOSE_COND_ 11 | 12 | // Users can define 'STOP_COND' to add an extra gate to stop conditions. 13 | `ifndef STOP_COND_ 14 | `ifdef STOP_COND 15 | `define STOP_COND_ (`STOP_COND) 16 | `else // STOP_COND 17 | `define STOP_COND_ 1 18 | `endif // STOP_COND 19 | `endif // not def STOP_COND_ 20 | 21 | module FMADecoder( 22 | input [6:0] io_uopc, 23 | output [1:0] io_cmd 24 | ); 25 | 26 | wire [5:0] decoder_decoded_invInputs = ~(io_uopc[5:0]); 27 | assign io_cmd = {|{&{io_uopc[0], io_uopc[1], io_uopc[2], io_uopc[3], io_uopc[4], decoder_decoded_invInputs[5], io_uopc[6]}, &{decoder_decoded_invInputs[0], decoder_decoded_invInputs[1], decoder_decoded_invInputs[3], decoder_decoded_invInputs[4], io_uopc[5], io_uopc[6]}, &{io_uopc[0], io_uopc[1], decoder_decoded_invInputs[2], decoder_decoded_invInputs[3], decoder_decoded_invInputs[4], io_uopc[5], io_uopc[6]}}, |{&{decoder_decoded_invInputs[0], decoder_decoded_invInputs[1], decoder_decoded_invInputs[2], io_uopc[3], io_uopc[4], decoder_decoded_invInputs[5], io_uopc[6]}, &{io_uopc[0], io_uopc[1], io_uopc[3], io_uopc[4], decoder_decoded_invInputs[5], io_uopc[6]}, &{io_uopc[1], io_uopc[2], io_uopc[3], io_uopc[4], decoder_decoded_invInputs[5], io_uopc[6]}, &{io_uopc[1], decoder_decoded_invInputs[2], decoder_decoded_invInputs[3], decoder_decoded_invInputs[4], io_uopc[5], io_uopc[6]}}}; 28 | endmodule 29 | 30 | -------------------------------------------------------------------------------- /rtl/data_2048x8.sv: -------------------------------------------------------------------------------- 1 | // Standard header to adapt well known macros for prints and assertions. 2 | 3 | // Users can define 'ASSERT_VERBOSE_COND' to add an extra gate to assert error printing. 4 | `ifndef ASSERT_VERBOSE_COND_ 5 | `ifdef ASSERT_VERBOSE_COND 6 | `define ASSERT_VERBOSE_COND_ (`ASSERT_VERBOSE_COND) 7 | `else // ASSERT_VERBOSE_COND 8 | `define ASSERT_VERBOSE_COND_ 1 9 | `endif // ASSERT_VERBOSE_COND 10 | `endif // not def ASSERT_VERBOSE_COND_ 11 | 12 | // Users can define 'STOP_COND' to add an extra gate to stop conditions. 13 | `ifndef STOP_COND_ 14 | `ifdef STOP_COND 15 | `define STOP_COND_ (`STOP_COND) 16 | `else // STOP_COND 17 | `define STOP_COND_ 1 18 | `endif // STOP_COND 19 | `endif // not def STOP_COND_ 20 | 21 | // VCS coverage exclude_file 22 | module data_2048x8( 23 | input [10:0] R0_addr, 24 | input R0_en, 25 | R0_clk, 26 | output [7:0] R0_data, 27 | input [10:0] W0_addr, 28 | input W0_en, 29 | W0_clk, 30 | input [7:0] W0_data, 31 | input [3:0] W0_mask 32 | ); 33 | 34 | reg [7:0] Memory[0:2047]; 35 | reg _R0_en_d0; 36 | reg [10:0] _R0_addr_d0; 37 | always @(posedge R0_clk) begin 38 | _R0_en_d0 <= R0_en; 39 | _R0_addr_d0 <= R0_addr; 40 | end // always @(posedge) 41 | always @(posedge W0_clk) begin 42 | if (W0_en & W0_mask[0]) 43 | Memory[W0_addr][32'h0 +: 2] <= W0_data[1:0]; 44 | if (W0_en & W0_mask[1]) 45 | Memory[W0_addr][32'h2 +: 2] <= W0_data[3:2]; 46 | if (W0_en & W0_mask[2]) 47 | Memory[W0_addr][32'h4 +: 2] <= W0_data[5:4]; 48 | if (W0_en & W0_mask[3]) 49 | Memory[W0_addr][32'h6 +: 2] <= W0_data[7:6]; 50 | end // always @(posedge) 51 | assign R0_data = _R0_en_d0 ? Memory[_R0_addr_d0] : 8'bx; 52 | endmodule 53 | 54 | -------------------------------------------------------------------------------- /rtl/btb_128x56.sv: -------------------------------------------------------------------------------- 1 | // Standard header to adapt well known macros for prints and assertions. 2 | 3 | // Users can define 'ASSERT_VERBOSE_COND' to add an extra gate to assert error printing. 4 | `ifndef ASSERT_VERBOSE_COND_ 5 | `ifdef ASSERT_VERBOSE_COND 6 | `define ASSERT_VERBOSE_COND_ (`ASSERT_VERBOSE_COND) 7 | `else // ASSERT_VERBOSE_COND 8 | `define ASSERT_VERBOSE_COND_ 1 9 | `endif // ASSERT_VERBOSE_COND 10 | `endif // not def ASSERT_VERBOSE_COND_ 11 | 12 | // Users can define 'STOP_COND' to add an extra gate to stop conditions. 13 | `ifndef STOP_COND_ 14 | `ifdef STOP_COND 15 | `define STOP_COND_ (`STOP_COND) 16 | `else // STOP_COND 17 | `define STOP_COND_ 1 18 | `endif // STOP_COND 19 | `endif // not def STOP_COND_ 20 | 21 | // VCS coverage exclude_file 22 | module btb_128x56( 23 | input [6:0] R0_addr, 24 | input R0_en, 25 | R0_clk, 26 | output [55:0] R0_data, 27 | input [6:0] W0_addr, 28 | input W0_en, 29 | W0_clk, 30 | input [55:0] W0_data, 31 | input [3:0] W0_mask 32 | ); 33 | 34 | reg [55:0] Memory[0:127]; 35 | reg _R0_en_d0; 36 | reg [6:0] _R0_addr_d0; 37 | always @(posedge R0_clk) begin 38 | _R0_en_d0 <= R0_en; 39 | _R0_addr_d0 <= R0_addr; 40 | end // always @(posedge) 41 | always @(posedge W0_clk) begin 42 | if (W0_en & W0_mask[0]) 43 | Memory[W0_addr][32'h0 +: 14] <= W0_data[13:0]; 44 | if (W0_en & W0_mask[1]) 45 | Memory[W0_addr][32'hE +: 14] <= W0_data[27:14]; 46 | if (W0_en & W0_mask[2]) 47 | Memory[W0_addr][32'h1C +: 14] <= W0_data[41:28]; 48 | if (W0_en & W0_mask[3]) 49 | Memory[W0_addr][32'h2A +: 14] <= W0_data[55:42]; 50 | end // always @(posedge) 51 | assign R0_data = _R0_en_d0 ? Memory[_R0_addr_d0] : 56'bx; 52 | endmodule 53 | 54 | -------------------------------------------------------------------------------- /rtl/table_128x44.sv: -------------------------------------------------------------------------------- 1 | // Standard header to adapt well known macros for prints and assertions. 2 | 3 | // Users can define 'ASSERT_VERBOSE_COND' to add an extra gate to assert error printing. 4 | `ifndef ASSERT_VERBOSE_COND_ 5 | `ifdef ASSERT_VERBOSE_COND 6 | `define ASSERT_VERBOSE_COND_ (`ASSERT_VERBOSE_COND) 7 | `else // ASSERT_VERBOSE_COND 8 | `define ASSERT_VERBOSE_COND_ 1 9 | `endif // ASSERT_VERBOSE_COND 10 | `endif // not def ASSERT_VERBOSE_COND_ 11 | 12 | // Users can define 'STOP_COND' to add an extra gate to stop conditions. 13 | `ifndef STOP_COND_ 14 | `ifdef STOP_COND 15 | `define STOP_COND_ (`STOP_COND) 16 | `else // STOP_COND 17 | `define STOP_COND_ 1 18 | `endif // STOP_COND 19 | `endif // not def STOP_COND_ 20 | 21 | // VCS coverage exclude_file 22 | module table_128x44( 23 | input [6:0] R0_addr, 24 | input R0_en, 25 | R0_clk, 26 | output [43:0] R0_data, 27 | input [6:0] W0_addr, 28 | input W0_en, 29 | W0_clk, 30 | input [43:0] W0_data, 31 | input [3:0] W0_mask 32 | ); 33 | 34 | reg [43:0] Memory[0:127]; 35 | reg _R0_en_d0; 36 | reg [6:0] _R0_addr_d0; 37 | always @(posedge R0_clk) begin 38 | _R0_en_d0 <= R0_en; 39 | _R0_addr_d0 <= R0_addr; 40 | end // always @(posedge) 41 | always @(posedge W0_clk) begin 42 | if (W0_en & W0_mask[0]) 43 | Memory[W0_addr][32'h0 +: 11] <= W0_data[10:0]; 44 | if (W0_en & W0_mask[1]) 45 | Memory[W0_addr][32'hB +: 11] <= W0_data[21:11]; 46 | if (W0_en & W0_mask[2]) 47 | Memory[W0_addr][32'h16 +: 11] <= W0_data[32:22]; 48 | if (W0_en & W0_mask[3]) 49 | Memory[W0_addr][32'h21 +: 11] <= W0_data[43:33]; 50 | end // always @(posedge) 51 | assign R0_data = _R0_en_d0 ? Memory[_R0_addr_d0] : 44'bx; 52 | endmodule 53 | 54 | -------------------------------------------------------------------------------- /rtl/table_128x52.sv: -------------------------------------------------------------------------------- 1 | // Standard header to adapt well known macros for prints and assertions. 2 | 3 | // Users can define 'ASSERT_VERBOSE_COND' to add an extra gate to assert error printing. 4 | `ifndef ASSERT_VERBOSE_COND_ 5 | `ifdef ASSERT_VERBOSE_COND 6 | `define ASSERT_VERBOSE_COND_ (`ASSERT_VERBOSE_COND) 7 | `else // ASSERT_VERBOSE_COND 8 | `define ASSERT_VERBOSE_COND_ 1 9 | `endif // ASSERT_VERBOSE_COND 10 | `endif // not def ASSERT_VERBOSE_COND_ 11 | 12 | // Users can define 'STOP_COND' to add an extra gate to stop conditions. 13 | `ifndef STOP_COND_ 14 | `ifdef STOP_COND 15 | `define STOP_COND_ (`STOP_COND) 16 | `else // STOP_COND 17 | `define STOP_COND_ 1 18 | `endif // STOP_COND 19 | `endif // not def STOP_COND_ 20 | 21 | // VCS coverage exclude_file 22 | module table_128x52( 23 | input [6:0] R0_addr, 24 | input R0_en, 25 | R0_clk, 26 | output [51:0] R0_data, 27 | input [6:0] W0_addr, 28 | input W0_en, 29 | W0_clk, 30 | input [51:0] W0_data, 31 | input [3:0] W0_mask 32 | ); 33 | 34 | reg [51:0] Memory[0:127]; 35 | reg _R0_en_d0; 36 | reg [6:0] _R0_addr_d0; 37 | always @(posedge R0_clk) begin 38 | _R0_en_d0 <= R0_en; 39 | _R0_addr_d0 <= R0_addr; 40 | end // always @(posedge) 41 | always @(posedge W0_clk) begin 42 | if (W0_en & W0_mask[0]) 43 | Memory[W0_addr][32'h0 +: 13] <= W0_data[12:0]; 44 | if (W0_en & W0_mask[1]) 45 | Memory[W0_addr][32'hD +: 13] <= W0_data[25:13]; 46 | if (W0_en & W0_mask[2]) 47 | Memory[W0_addr][32'h1A +: 13] <= W0_data[38:26]; 48 | if (W0_en & W0_mask[3]) 49 | Memory[W0_addr][32'h27 +: 13] <= W0_data[51:39]; 50 | end // always @(posedge) 51 | assign R0_data = _R0_en_d0 ? Memory[_R0_addr_d0] : 52'bx; 52 | endmodule 53 | 54 | -------------------------------------------------------------------------------- /rtl/table_256x48.sv: -------------------------------------------------------------------------------- 1 | // Standard header to adapt well known macros for prints and assertions. 2 | 3 | // Users can define 'ASSERT_VERBOSE_COND' to add an extra gate to assert error printing. 4 | `ifndef ASSERT_VERBOSE_COND_ 5 | `ifdef ASSERT_VERBOSE_COND 6 | `define ASSERT_VERBOSE_COND_ (`ASSERT_VERBOSE_COND) 7 | `else // ASSERT_VERBOSE_COND 8 | `define ASSERT_VERBOSE_COND_ 1 9 | `endif // ASSERT_VERBOSE_COND 10 | `endif // not def ASSERT_VERBOSE_COND_ 11 | 12 | // Users can define 'STOP_COND' to add an extra gate to stop conditions. 13 | `ifndef STOP_COND_ 14 | `ifdef STOP_COND 15 | `define STOP_COND_ (`STOP_COND) 16 | `else // STOP_COND 17 | `define STOP_COND_ 1 18 | `endif // STOP_COND 19 | `endif // not def STOP_COND_ 20 | 21 | // VCS coverage exclude_file 22 | module table_256x48( 23 | input [7:0] R0_addr, 24 | input R0_en, 25 | R0_clk, 26 | output [47:0] R0_data, 27 | input [7:0] W0_addr, 28 | input W0_en, 29 | W0_clk, 30 | input [47:0] W0_data, 31 | input [3:0] W0_mask 32 | ); 33 | 34 | reg [47:0] Memory[0:255]; 35 | reg _R0_en_d0; 36 | reg [7:0] _R0_addr_d0; 37 | always @(posedge R0_clk) begin 38 | _R0_en_d0 <= R0_en; 39 | _R0_addr_d0 <= R0_addr; 40 | end // always @(posedge) 41 | always @(posedge W0_clk) begin 42 | if (W0_en & W0_mask[0]) 43 | Memory[W0_addr][32'h0 +: 12] <= W0_data[11:0]; 44 | if (W0_en & W0_mask[1]) 45 | Memory[W0_addr][32'hC +: 12] <= W0_data[23:12]; 46 | if (W0_en & W0_mask[2]) 47 | Memory[W0_addr][32'h18 +: 12] <= W0_data[35:24]; 48 | if (W0_en & W0_mask[3]) 49 | Memory[W0_addr][32'h24 +: 12] <= W0_data[47:36]; 50 | end // always @(posedge) 51 | assign R0_data = _R0_en_d0 ? Memory[_R0_addr_d0] : 48'bx; 52 | endmodule 53 | 54 | -------------------------------------------------------------------------------- /jenkins/public_build.Jenkinsfile: -------------------------------------------------------------------------------- 1 | @Library('utils@orfs-v2.2.2') _ 2 | 3 | // kick off worker using megaboom cloud definition 4 | // Prevent builds stomping on each other and set a timeout to avoid runaways 5 | timeout(time: 72, unit: 'HOURS') { 6 | node('gce-megaboom-central1') { 7 | properties([copyArtifactPermission('${JOB_NAME},'+env.BRANCH_NAME), 8 | disableConcurrentBuilds(abortPrevious: true)]); 9 | 10 | // checkout megaboom and apply PR 11 | stage('Checkout Megaboom') { 12 | checkout([ 13 | $class: 'GitSCM', 14 | branches: [[name: scm.branches[0].name]], 15 | extensions: [ 16 | [$class: 'CloneOption', noTags: false], 17 | ], 18 | userRemoteConfigs: scm.userRemoteConfigs 19 | ]); 20 | def description = sh(script: "git log -1 --pretty=%B", returnStdout: true).trim(); 21 | if (description.contains('ci') && description.contains('skip')) { 22 | currentBuild.result = 'SKIPPED'; // 'SUCCESS', 'SKIPPED' 23 | return; 24 | } 25 | } 26 | 27 | def DOCKER_IMAGE; 28 | 29 | // Run docker build for machine image 30 | stage('Build and Push Docker Machine Image') { 31 | DOCKER_IMAGE = dockerPush('ubuntu22.04', 'megaboom'); 32 | echo "Docker image is $DOCKER_IMAGE"; 33 | } 34 | 35 | // execute bazel to build BoomTile through grt stage 36 | stage('Build Megaboom') { 37 | buildMegaboom(DOCKER_IMAGE); 38 | } 39 | 40 | // TODO Add some smoke tests 41 | 42 | stage ('Cleanup and Reporting') { 43 | finalReport(DOCKER_IMAGE, "megaboom"); 44 | } 45 | } 46 | } 47 | -------------------------------------------------------------------------------- /rtl/AsyncResetSynchronizerPrimitiveShiftReg_d3_i0.sv: -------------------------------------------------------------------------------- 1 | // Standard header to adapt well known macros for prints and assertions. 2 | 3 | // Users can define 'ASSERT_VERBOSE_COND' to add an extra gate to assert error printing. 4 | `ifndef ASSERT_VERBOSE_COND_ 5 | `ifdef ASSERT_VERBOSE_COND 6 | `define ASSERT_VERBOSE_COND_ (`ASSERT_VERBOSE_COND) 7 | `else // ASSERT_VERBOSE_COND 8 | `define ASSERT_VERBOSE_COND_ 1 9 | `endif // ASSERT_VERBOSE_COND 10 | `endif // not def ASSERT_VERBOSE_COND_ 11 | 12 | // Users can define 'STOP_COND' to add an extra gate to stop conditions. 13 | `ifndef STOP_COND_ 14 | `ifdef STOP_COND 15 | `define STOP_COND_ (`STOP_COND) 16 | `else // STOP_COND 17 | `define STOP_COND_ 1 18 | `endif // STOP_COND 19 | `endif // not def STOP_COND_ 20 | 21 | module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0( 22 | input clock, 23 | reset, 24 | io_d, 25 | output io_q 26 | ); 27 | 28 | reg sync_0; 29 | reg sync_1; 30 | reg sync_2; 31 | always @(posedge clock or posedge reset) begin 32 | if (reset) begin 33 | sync_0 <= 1'h0; 34 | sync_1 <= 1'h0; 35 | sync_2 <= 1'h0; 36 | end 37 | else begin 38 | sync_0 <= sync_1; 39 | sync_1 <= sync_2; 40 | sync_2 <= io_d; 41 | end 42 | end // always @(posedge, posedge) 43 | `ifdef ENABLE_INITIAL_REG_ 44 | `ifdef FIRRTL_BEFORE_INITIAL 45 | `FIRRTL_BEFORE_INITIAL 46 | `endif // FIRRTL_BEFORE_INITIAL 47 | initial begin 48 | if (reset) begin 49 | sync_0 = 1'h0; 50 | sync_1 = 1'h0; 51 | sync_2 = 1'h0; 52 | end 53 | end // initial 54 | `ifdef FIRRTL_AFTER_INITIAL 55 | `FIRRTL_AFTER_INITIAL 56 | `endif // FIRRTL_AFTER_INITIAL 57 | `endif // ENABLE_INITIAL_REG_ 58 | assign io_q = sync_0; 59 | endmodule 60 | 61 | -------------------------------------------------------------------------------- /rtl/RoundAnyRawFNToRecFN.sv: -------------------------------------------------------------------------------- 1 | // Standard header to adapt well known macros for prints and assertions. 2 | 3 | // Users can define 'ASSERT_VERBOSE_COND' to add an extra gate to assert error printing. 4 | `ifndef ASSERT_VERBOSE_COND_ 5 | `ifdef ASSERT_VERBOSE_COND 6 | `define ASSERT_VERBOSE_COND_ (`ASSERT_VERBOSE_COND) 7 | `else // ASSERT_VERBOSE_COND 8 | `define ASSERT_VERBOSE_COND_ 1 9 | `endif // ASSERT_VERBOSE_COND 10 | `endif // not def ASSERT_VERBOSE_COND_ 11 | 12 | // Users can define 'STOP_COND' to add an extra gate to stop conditions. 13 | `ifndef STOP_COND_ 14 | `ifdef STOP_COND 15 | `define STOP_COND_ (`STOP_COND) 16 | `else // STOP_COND 17 | `define STOP_COND_ 1 18 | `endif // STOP_COND 19 | `endif // not def STOP_COND_ 20 | 21 | module RoundAnyRawFNToRecFN( 22 | input io_in_isZero, 23 | io_in_sign, 24 | input [8:0] io_in_sExp, 25 | input [64:0] io_in_sig, 26 | input [2:0] io_roundingMode, 27 | output [32:0] io_out, 28 | output [4:0] io_exceptionFlags 29 | ); 30 | 31 | wire roundingMode_near_even = io_roundingMode == 3'h0; 32 | wire common_inexact = io_in_sig[39] | (|(io_in_sig[38:0])); 33 | wire [25:0] roundedSig = (roundingMode_near_even | io_roundingMode == 3'h4) & io_in_sig[39] | (io_roundingMode == 3'h2 & io_in_sign | io_roundingMode == 3'h3 & ~io_in_sign) & common_inexact ? {1'h0, io_in_sig[64:40]} + 26'h1 & {25'h1FFFFFF, ~(roundingMode_near_even & io_in_sig[39] & ~(|(io_in_sig[38:0])))} : {1'h0, io_in_sig[64:41], io_in_sig[40] | io_roundingMode == 3'h6 & common_inexact}; 34 | assign io_out = {io_in_sign, io_in_sExp + {7'h0, roundedSig[25:24]} + 9'h80 & ~(io_in_isZero ? 9'h1C0 : 9'h0), io_in_isZero ? 23'h0 : roundedSig[22:0]}; 35 | assign io_exceptionFlags = {4'h0, ~io_in_isZero & common_inexact}; 36 | endmodule 37 | 38 | -------------------------------------------------------------------------------- /rtl/MaxPeriodFibonacciLFSR_2.sv: -------------------------------------------------------------------------------- 1 | // Standard header to adapt well known macros for prints and assertions. 2 | 3 | // Users can define 'ASSERT_VERBOSE_COND' to add an extra gate to assert error printing. 4 | `ifndef ASSERT_VERBOSE_COND_ 5 | `ifdef ASSERT_VERBOSE_COND 6 | `define ASSERT_VERBOSE_COND_ (`ASSERT_VERBOSE_COND) 7 | `else // ASSERT_VERBOSE_COND 8 | `define ASSERT_VERBOSE_COND_ 1 9 | `endif // ASSERT_VERBOSE_COND 10 | `endif // not def ASSERT_VERBOSE_COND_ 11 | 12 | // Users can define 'STOP_COND' to add an extra gate to stop conditions. 13 | `ifndef STOP_COND_ 14 | `ifdef STOP_COND 15 | `define STOP_COND_ (`STOP_COND) 16 | `else // STOP_COND 17 | `define STOP_COND_ 1 18 | `endif // STOP_COND 19 | `endif // not def STOP_COND_ 20 | 21 | module MaxPeriodFibonacciLFSR_2( 22 | input clock, 23 | reset, 24 | output io_out_0, 25 | io_out_1, 26 | io_out_2, 27 | io_out_3, 28 | io_out_4, 29 | io_out_5 30 | ); 31 | 32 | reg state_0; 33 | reg state_1; 34 | reg state_2; 35 | reg state_3; 36 | reg state_4; 37 | reg state_5; 38 | always @(posedge clock) begin 39 | if (reset) begin 40 | state_0 <= 1'h1; 41 | state_1 <= 1'h0; 42 | state_2 <= 1'h0; 43 | state_3 <= 1'h0; 44 | state_4 <= 1'h0; 45 | state_5 <= 1'h0; 46 | end 47 | else begin 48 | state_0 <= state_5 ^ state_4; 49 | state_1 <= state_0; 50 | state_2 <= state_1; 51 | state_3 <= state_2; 52 | state_4 <= state_3; 53 | state_5 <= state_4; 54 | end 55 | end // always @(posedge) 56 | assign io_out_0 = state_0; 57 | assign io_out_1 = state_1; 58 | assign io_out_2 = state_2; 59 | assign io_out_3 = state_3; 60 | assign io_out_4 = state_4; 61 | assign io_out_5 = state_5; 62 | endmodule 63 | 64 | -------------------------------------------------------------------------------- /rtl/meta_128x120.sv: -------------------------------------------------------------------------------- 1 | // Standard header to adapt well known macros for prints and assertions. 2 | 3 | // Users can define 'ASSERT_VERBOSE_COND' to add an extra gate to assert error printing. 4 | `ifndef ASSERT_VERBOSE_COND_ 5 | `ifdef ASSERT_VERBOSE_COND 6 | `define ASSERT_VERBOSE_COND_ (`ASSERT_VERBOSE_COND) 7 | `else // ASSERT_VERBOSE_COND 8 | `define ASSERT_VERBOSE_COND_ 1 9 | `endif // ASSERT_VERBOSE_COND 10 | `endif // not def ASSERT_VERBOSE_COND_ 11 | 12 | // Users can define 'STOP_COND' to add an extra gate to stop conditions. 13 | `ifndef STOP_COND_ 14 | `ifdef STOP_COND 15 | `define STOP_COND_ (`STOP_COND) 16 | `else // STOP_COND 17 | `define STOP_COND_ 1 18 | `endif // STOP_COND 19 | `endif // not def STOP_COND_ 20 | 21 | // VCS coverage exclude_file 22 | module meta_128x120( 23 | input [6:0] R0_addr, 24 | input R0_en, 25 | R0_clk, 26 | output [119:0] R0_data, 27 | input [6:0] W0_addr, 28 | input W0_en, 29 | W0_clk, 30 | input [119:0] W0_data, 31 | input [3:0] W0_mask 32 | ); 33 | 34 | reg [119:0] Memory[0:127]; 35 | reg _R0_en_d0; 36 | reg [6:0] _R0_addr_d0; 37 | always @(posedge R0_clk) begin 38 | _R0_en_d0 <= R0_en; 39 | _R0_addr_d0 <= R0_addr; 40 | end // always @(posedge) 41 | always @(posedge W0_clk) begin 42 | if (W0_en & W0_mask[0]) 43 | Memory[W0_addr][32'h0 +: 30] <= W0_data[29:0]; 44 | if (W0_en & W0_mask[1]) 45 | Memory[W0_addr][32'h1E +: 30] <= W0_data[59:30]; 46 | if (W0_en & W0_mask[2]) 47 | Memory[W0_addr][32'h3C +: 30] <= W0_data[89:60]; 48 | if (W0_en & W0_mask[3]) 49 | Memory[W0_addr][32'h5A +: 30] <= W0_data[119:90]; 50 | end // always @(posedge) 51 | assign R0_data = _R0_en_d0 ? Memory[_R0_addr_d0] : 120'bx; 52 | endmodule 53 | 54 | -------------------------------------------------------------------------------- /rtl/Arbiter_11.sv: -------------------------------------------------------------------------------- 1 | // Standard header to adapt well known macros for prints and assertions. 2 | 3 | // Users can define 'ASSERT_VERBOSE_COND' to add an extra gate to assert error printing. 4 | `ifndef ASSERT_VERBOSE_COND_ 5 | `ifdef ASSERT_VERBOSE_COND 6 | `define ASSERT_VERBOSE_COND_ (`ASSERT_VERBOSE_COND) 7 | `else // ASSERT_VERBOSE_COND 8 | `define ASSERT_VERBOSE_COND_ 1 9 | `endif // ASSERT_VERBOSE_COND 10 | `endif // not def ASSERT_VERBOSE_COND_ 11 | 12 | // Users can define 'STOP_COND' to add an extra gate to stop conditions. 13 | `ifndef STOP_COND_ 14 | `ifdef STOP_COND 15 | `define STOP_COND_ (`STOP_COND) 16 | `else // STOP_COND 17 | `define STOP_COND_ 1 18 | `endif // STOP_COND 19 | `endif // not def STOP_COND_ 20 | 21 | module Arbiter_11( 22 | input io_in_0_valid, 23 | input [7:0] io_in_0_bits_way_en, 24 | input [11:0] io_in_0_bits_addr, 25 | input [1:0] io_in_0_bits_wmask, 26 | input [127:0] io_in_0_bits_data, 27 | output io_in_1_ready, 28 | input io_in_1_valid, 29 | input [7:0] io_in_1_bits_way_en, 30 | input [11:0] io_in_1_bits_addr, 31 | input [127:0] io_in_1_bits_data, 32 | output io_out_valid, 33 | output [7:0] io_out_bits_way_en, 34 | output [11:0] io_out_bits_addr, 35 | output [1:0] io_out_bits_wmask, 36 | output [127:0] io_out_bits_data 37 | ); 38 | 39 | assign io_in_1_ready = ~io_in_0_valid; 40 | assign io_out_valid = io_in_0_valid | io_in_1_valid; 41 | assign io_out_bits_way_en = io_in_0_valid ? io_in_0_bits_way_en : io_in_1_bits_way_en; 42 | assign io_out_bits_addr = io_in_0_valid ? io_in_0_bits_addr : io_in_1_bits_addr; 43 | assign io_out_bits_wmask = io_in_0_valid ? io_in_0_bits_wmask : 2'h3; 44 | assign io_out_bits_data = io_in_0_valid ? io_in_0_bits_data : io_in_1_bits_data; 45 | endmodule 46 | 47 | -------------------------------------------------------------------------------- /rtl/RoundAnyRawFNToRecFN_1.sv: -------------------------------------------------------------------------------- 1 | // Standard header to adapt well known macros for prints and assertions. 2 | 3 | // Users can define 'ASSERT_VERBOSE_COND' to add an extra gate to assert error printing. 4 | `ifndef ASSERT_VERBOSE_COND_ 5 | `ifdef ASSERT_VERBOSE_COND 6 | `define ASSERT_VERBOSE_COND_ (`ASSERT_VERBOSE_COND) 7 | `else // ASSERT_VERBOSE_COND 8 | `define ASSERT_VERBOSE_COND_ 1 9 | `endif // ASSERT_VERBOSE_COND 10 | `endif // not def ASSERT_VERBOSE_COND_ 11 | 12 | // Users can define 'STOP_COND' to add an extra gate to stop conditions. 13 | `ifndef STOP_COND_ 14 | `ifdef STOP_COND 15 | `define STOP_COND_ (`STOP_COND) 16 | `else // STOP_COND 17 | `define STOP_COND_ 1 18 | `endif // STOP_COND 19 | `endif // not def STOP_COND_ 20 | 21 | module RoundAnyRawFNToRecFN_1( 22 | input io_in_isZero, 23 | io_in_sign, 24 | input [8:0] io_in_sExp, 25 | input [64:0] io_in_sig, 26 | input [2:0] io_roundingMode, 27 | output [64:0] io_out, 28 | output [4:0] io_exceptionFlags 29 | ); 30 | 31 | wire roundingMode_near_even = io_roundingMode == 3'h0; 32 | wire common_inexact = io_in_sig[10] | (|(io_in_sig[9:0])); 33 | wire [54:0] roundedSig = (roundingMode_near_even | io_roundingMode == 3'h4) & io_in_sig[10] | (io_roundingMode == 3'h2 & io_in_sign | io_roundingMode == 3'h3 & ~io_in_sign) & common_inexact ? {1'h0, io_in_sig[64:11]} + 55'h1 & {54'h3FFFFFFFFFFFFF, ~(roundingMode_near_even & io_in_sig[10] & ~(|(io_in_sig[9:0])))} : {1'h0, io_in_sig[64:12], io_in_sig[11] | io_roundingMode == 3'h6 & common_inexact}; 34 | assign io_out = {io_in_sign, {{3{io_in_sExp[8]}}, io_in_sExp} + {10'h0, roundedSig[54:53]} + 12'h780 & ~(io_in_isZero ? 12'hE00 : 12'h0), io_in_isZero ? 52'h0 : roundedSig[51:0]}; 35 | assign io_exceptionFlags = {4'h0, ~io_in_isZero & common_inexact}; 36 | endmodule 37 | 38 | -------------------------------------------------------------------------------- /rtl/Arbiter_20.sv: -------------------------------------------------------------------------------- 1 | // Standard header to adapt well known macros for prints and assertions. 2 | 3 | // Users can define 'ASSERT_VERBOSE_COND' to add an extra gate to assert error printing. 4 | `ifndef ASSERT_VERBOSE_COND_ 5 | `ifdef ASSERT_VERBOSE_COND 6 | `define ASSERT_VERBOSE_COND_ (`ASSERT_VERBOSE_COND) 7 | `else // ASSERT_VERBOSE_COND 8 | `define ASSERT_VERBOSE_COND_ 1 9 | `endif // ASSERT_VERBOSE_COND 10 | `endif // not def ASSERT_VERBOSE_COND_ 11 | 12 | // Users can define 'STOP_COND' to add an extra gate to stop conditions. 13 | `ifndef STOP_COND_ 14 | `ifdef STOP_COND 15 | `define STOP_COND_ (`STOP_COND) 16 | `else // STOP_COND 17 | `define STOP_COND_ 1 18 | `endif // STOP_COND 19 | `endif // not def STOP_COND_ 20 | 21 | module Arbiter_20( 22 | output io_in_0_ready, 23 | input io_in_0_valid, 24 | io_in_0_bits_valid, 25 | input [26:0] io_in_0_bits_bits_addr, 26 | output io_in_1_ready, 27 | input io_in_1_valid, 28 | input [26:0] io_in_1_bits_bits_addr, 29 | input io_in_1_bits_bits_need_gpa, 30 | io_out_ready, 31 | output io_out_valid, 32 | io_out_bits_valid, 33 | output [26:0] io_out_bits_bits_addr, 34 | output io_out_bits_bits_need_gpa, 35 | output [1:0] io_chosen 36 | ); 37 | 38 | assign io_in_0_ready = io_out_ready; 39 | assign io_in_1_ready = ~io_in_0_valid & io_out_ready; 40 | assign io_out_valid = io_in_0_valid | io_in_1_valid; 41 | assign io_out_bits_valid = io_in_0_valid ? io_in_0_bits_valid : io_in_1_valid; 42 | assign io_out_bits_bits_addr = io_in_0_valid ? io_in_0_bits_bits_addr : io_in_1_valid ? io_in_1_bits_bits_addr : 27'h0; 43 | assign io_out_bits_bits_need_gpa = ~io_in_0_valid & io_in_1_valid & io_in_1_bits_bits_need_gpa; 44 | assign io_chosen = io_in_0_valid ? 2'h0 : io_in_1_valid ? 2'h1 : 2'h2; 45 | endmodule 46 | 47 | -------------------------------------------------------------------------------- /mock/l2_tlb_ram_0_512x46.sv: -------------------------------------------------------------------------------- 1 | // Standard header to adapt well known macros for prints and assertions. 2 | 3 | // Users can define 'PRINTF_COND' to add an extra gate to prints. 4 | `ifndef PRINTF_COND_ 5 | `ifdef PRINTF_COND 6 | `define PRINTF_COND_ (`PRINTF_COND) 7 | `else // PRINTF_COND 8 | `define PRINTF_COND_ 1 9 | `endif // PRINTF_COND 10 | `endif // not def PRINTF_COND_ 11 | 12 | // Users can define 'ASSERT_VERBOSE_COND' to add an extra gate to assert error printing. 13 | `ifndef ASSERT_VERBOSE_COND_ 14 | `ifdef ASSERT_VERBOSE_COND 15 | `define ASSERT_VERBOSE_COND_ (`ASSERT_VERBOSE_COND) 16 | `else // ASSERT_VERBOSE_COND 17 | `define ASSERT_VERBOSE_COND_ 1 18 | `endif // ASSERT_VERBOSE_COND 19 | `endif // not def ASSERT_VERBOSE_COND_ 20 | 21 | // Users can define 'STOP_COND' to add an extra gate to stop conditions. 22 | `ifndef STOP_COND_ 23 | `ifdef STOP_COND 24 | `define STOP_COND_ (`STOP_COND) 25 | `else // STOP_COND 26 | `define STOP_COND_ 1 27 | `endif // STOP_COND 28 | `endif // not def STOP_COND_ 29 | 30 | // VCS coverage exclude_file 31 | module l2_tlb_ram_0_512x46( 32 | input [8:0] RW0_addr, 33 | input RW0_en, 34 | RW0_clk, 35 | RW0_wmode, 36 | input [45:0] RW0_wdata, 37 | output [45:0] RW0_rdata 38 | ); 39 | 40 | reg [45:0] Memory[0:15]; // Reduced to 16 rows 41 | reg [3:0] _RW0_raddr_d0; // Reduced to 4 bits 42 | reg _RW0_ren_d0; 43 | reg _RW0_rmode_d0; 44 | always @(posedge RW0_clk) begin 45 | _RW0_raddr_d0 <= RW0_addr[3:0] ^ RW0_addr[7:4]; // XOR upper and lower bits 46 | _RW0_ren_d0 <= RW0_en; 47 | _RW0_rmode_d0 <= RW0_wmode; 48 | if (RW0_en & RW0_wmode) 49 | Memory[_RW0_raddr_d0] <= RW0_wdata; // Use XORed address 50 | end // always @(posedge) 51 | assign RW0_rdata = _RW0_ren_d0 & ~_RW0_rmode_d0 ? Memory[_RW0_raddr_d0] : 46'bx; 52 | endmodule 53 | 54 | -------------------------------------------------------------------------------- /sram.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python3 2 | import os 3 | import yaml 4 | import json 5 | import sys 6 | from tabulate import tabulate 7 | 8 | 9 | def main(): 10 | if len(sys.argv) == 1: 11 | print("Usage: {} ".format(sys.argv[0])) 12 | sys.exit(1) 13 | 14 | with open(sys.argv[1], "r") as f: 15 | build_bazel = json.load(f) 16 | 17 | srams = {} 18 | for filename in sys.argv[2:]: 19 | with open(filename, "r") as f: 20 | key = os.path.splitext(os.path.basename(filename))[0].replace( 21 | "_floorplan", "" 22 | ) 23 | srams[key] = ( 24 | srams.get(key, {}) 25 | | yaml.load(f, Loader=yaml.FullLoader) 26 | | build_bazel[key] 27 | ) 28 | 29 | list_of_list_of_all_columns = [list(sram.keys()) for sram in srams.values()] 30 | all_columns = sorted( 31 | list(set([item for sublist in list_of_list_of_all_columns for item in sublist])) 32 | ) 33 | order = ["aspect_ratio", "width", "height"] 34 | all_columns = order + [col for col in all_columns if col not in order] 35 | 36 | table_data = [] 37 | 38 | table_data.append(["Name"] + all_columns) 39 | 40 | for sram, values in srams.items(): 41 | basename_without_ext = os.path.splitext(os.path.basename(sram))[0] 42 | row = [basename_without_ext] + [ 43 | ( 44 | f"{float(values.get(col, '')):>10.2f}" 45 | if isinstance(values.get(col, ""), (int, float)) 46 | or values.get(col, "").replace(".", "", 1).isdigit() 47 | else str(values.get(col, "")) 48 | ) 49 | for col in all_columns 50 | ] 51 | table_data.append(row) 52 | 53 | print(tabulate(table_data, headers="firstrow", tablefmt="pipe")) 54 | 55 | 56 | if __name__ == "__main__": 57 | main() 58 | -------------------------------------------------------------------------------- /rtl/AMOALU.sv: -------------------------------------------------------------------------------- 1 | // Standard header to adapt well known macros for prints and assertions. 2 | 3 | // Users can define 'ASSERT_VERBOSE_COND' to add an extra gate to assert error printing. 4 | `ifndef ASSERT_VERBOSE_COND_ 5 | `ifdef ASSERT_VERBOSE_COND 6 | `define ASSERT_VERBOSE_COND_ (`ASSERT_VERBOSE_COND) 7 | `else // ASSERT_VERBOSE_COND 8 | `define ASSERT_VERBOSE_COND_ 1 9 | `endif // ASSERT_VERBOSE_COND 10 | `endif // not def ASSERT_VERBOSE_COND_ 11 | 12 | // Users can define 'STOP_COND' to add an extra gate to stop conditions. 13 | `ifndef STOP_COND_ 14 | `ifdef STOP_COND 15 | `define STOP_COND_ (`STOP_COND) 16 | `else // STOP_COND 17 | `define STOP_COND_ 1 18 | `endif // STOP_COND 19 | `endif // not def STOP_COND_ 20 | 21 | module AMOALU( 22 | input [7:0] io_mask, 23 | input [4:0] io_cmd, 24 | input [63:0] io_lhs, 25 | io_rhs, 26 | output [63:0] io_out 27 | ); 28 | 29 | wire _logic_xor_T_1 = io_cmd == 5'hA; 30 | wire logic_and = _logic_xor_T_1 | io_cmd == 5'hB; 31 | wire logic_xor = io_cmd == 5'h9 | _logic_xor_T_1; 32 | wire [63:0] adder_out_mask = {32'hFFFFFFFF, io_mask[3], 31'h7FFFFFFF}; 33 | wire [63:0] wmask = {{8{io_mask[7]}}, {8{io_mask[6]}}, {8{io_mask[5]}}, {8{io_mask[4]}}, {8{io_mask[3]}}, {8{io_mask[2]}}, {8{io_mask[1]}}, {8{io_mask[0]}}}; 34 | assign io_out = wmask & (io_cmd == 5'h8 ? (io_lhs & adder_out_mask) + (io_rhs & adder_out_mask) : logic_and | logic_xor ? (logic_and ? io_lhs & io_rhs : 64'h0) | (logic_xor ? io_lhs ^ io_rhs : 64'h0) : ((io_mask[4] ? (io_lhs[63] == io_rhs[63] ? io_lhs[63:32] < io_rhs[63:32] | io_lhs[63:32] == io_rhs[63:32] & io_lhs[31:0] < io_rhs[31:0] : io_cmd[1] ? io_rhs[63] : io_lhs[63]) : io_lhs[31] == io_rhs[31] ? io_lhs[31:0] < io_rhs[31:0] : io_cmd[1] ? io_rhs[31] : io_lhs[31]) ? io_cmd == 5'hC | io_cmd == 5'hE : io_cmd == 5'hD | io_cmd == 5'hF) ? io_lhs : io_rhs) | ~wmask & io_lhs; 35 | endmodule 36 | 37 | -------------------------------------------------------------------------------- /rtl/OptimizationBarrier_14.sv: -------------------------------------------------------------------------------- 1 | // Standard header to adapt well known macros for prints and assertions. 2 | 3 | // Users can define 'ASSERT_VERBOSE_COND' to add an extra gate to assert error printing. 4 | `ifndef ASSERT_VERBOSE_COND_ 5 | `ifdef ASSERT_VERBOSE_COND 6 | `define ASSERT_VERBOSE_COND_ (`ASSERT_VERBOSE_COND) 7 | `else // ASSERT_VERBOSE_COND 8 | `define ASSERT_VERBOSE_COND_ 1 9 | `endif // ASSERT_VERBOSE_COND 10 | `endif // not def ASSERT_VERBOSE_COND_ 11 | 12 | // Users can define 'STOP_COND' to add an extra gate to stop conditions. 13 | `ifndef STOP_COND_ 14 | `ifdef STOP_COND 15 | `define STOP_COND_ (`STOP_COND) 16 | `else // STOP_COND 17 | `define STOP_COND_ 1 18 | `endif // STOP_COND 19 | `endif // not def STOP_COND_ 20 | 21 | module OptimizationBarrier_14( 22 | input [20:0] io_x_ppn, 23 | input io_x_u, 24 | io_x_ae, 25 | io_x_sw, 26 | io_x_sx, 27 | io_x_sr, 28 | io_x_pw, 29 | io_x_pr, 30 | io_x_pal, 31 | io_x_paa, 32 | io_x_eff, 33 | io_x_c, 34 | output [20:0] io_y_ppn, 35 | output io_y_u, 36 | io_y_ae, 37 | io_y_sw, 38 | io_y_sx, 39 | io_y_sr, 40 | io_y_pw, 41 | io_y_pr, 42 | io_y_pal, 43 | io_y_paa, 44 | io_y_eff, 45 | io_y_c 46 | ); 47 | 48 | assign io_y_ppn = io_x_ppn; 49 | assign io_y_u = io_x_u; 50 | assign io_y_ae = io_x_ae; 51 | assign io_y_sw = io_x_sw; 52 | assign io_y_sx = io_x_sx; 53 | assign io_y_sr = io_x_sr; 54 | assign io_y_pw = io_x_pw; 55 | assign io_y_pr = io_x_pr; 56 | assign io_y_pal = io_x_pal; 57 | assign io_y_paa = io_x_paa; 58 | assign io_y_eff = io_x_eff; 59 | assign io_y_c = io_x_c; 60 | endmodule 61 | 62 | -------------------------------------------------------------------------------- /rtl/SimTSI.cc: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | #include 4 | #include 5 | #include "testchip_tsi.h" 6 | 7 | testchip_tsi_t *tsi = NULL; 8 | 9 | // Remove VCS simv option from argv if it match pattern -X???= 10 | void remove_vcs_simv_opt(int & argc, char **& argv){ 11 | int idx = 0; 12 | while(idx < argc){ 13 | std::string str = std::string(argv[idx]); 14 | if(str.length() > 1 && str[0] == '-' && str[1] != '-' && str.find('=') != std::string::npos){ 15 | // Found -????=???? as VCS simv option 16 | for(int i = idx; i < argc - 1; i++){ 17 | // Remove the current option 18 | argv[i] = argv[i + 1]; 19 | } 20 | argc--; 21 | }else{ 22 | idx++; 23 | } 24 | } 25 | } 26 | 27 | extern "C" int tsi_tick( 28 | unsigned char out_valid, 29 | unsigned char *out_ready, 30 | int out_bits, 31 | 32 | unsigned char *in_valid, 33 | unsigned char in_ready, 34 | int *in_bits) 35 | { 36 | bool out_fire = *out_ready && out_valid; 37 | bool in_fire = *in_valid && in_ready; 38 | bool in_free = !(*in_valid); 39 | 40 | if (!tsi) { 41 | s_vpi_vlog_info info; 42 | if (!vpi_get_vlog_info(&info)) 43 | abort(); 44 | 45 | // Prevent simv option enter htif 46 | remove_vcs_simv_opt(info.argc, info.argv); 47 | 48 | // TODO: We should somehow inspect whether or not our backing memory supports loadmem, instead of unconditionally setting it to true 49 | tsi = new testchip_tsi_t(info.argc, info.argv, true); 50 | } 51 | 52 | tsi->tick(out_valid, out_bits, in_ready); 53 | tsi->switch_to_host(); 54 | 55 | *in_valid = tsi->in_valid(); 56 | *in_bits = tsi->in_bits(); 57 | *out_ready = tsi->out_ready(); 58 | 59 | return tsi->done() ? (tsi->exit_code() << 1 | 1) : 0; 60 | } 61 | -------------------------------------------------------------------------------- /rtl/SimTSI.v: -------------------------------------------------------------------------------- 1 | import "DPI-C" function int tsi_tick 2 | ( 3 | input bit tsi_out_valid, 4 | output bit tsi_out_ready, 5 | input int tsi_out_bits, 6 | 7 | output bit tsi_in_valid, 8 | input bit tsi_in_ready, 9 | output int tsi_in_bits 10 | ); 11 | 12 | module SimTSI ( 13 | input clock, 14 | input reset, 15 | input tsi_out_valid, 16 | output tsi_out_ready, 17 | input [31:0] tsi_out_bits, 18 | 19 | output tsi_in_valid, 20 | input tsi_in_ready, 21 | output [31:0] tsi_in_bits, 22 | 23 | output [31:0] exit 24 | ); 25 | 26 | bit __in_valid; 27 | bit __out_ready; 28 | int __in_bits; 29 | int __exit; 30 | 31 | reg __in_valid_reg; 32 | reg __out_ready_reg; 33 | reg [31:0] __in_bits_reg; 34 | reg [31:0] __exit_reg; 35 | 36 | assign tsi_in_valid = __in_valid_reg; 37 | assign tsi_in_bits = __in_bits_reg; 38 | assign tsi_out_ready = __out_ready_reg; 39 | assign exit = __exit_reg; 40 | 41 | // Evaluate the signals on the positive edge 42 | always @(posedge clock) begin 43 | if (reset) begin 44 | __in_valid = 0; 45 | __out_ready = 0; 46 | __exit = 0; 47 | 48 | __in_valid_reg <= 0; 49 | __in_bits_reg <= 0; 50 | __out_ready_reg <= 0; 51 | __exit_reg <= 0; 52 | end else begin 53 | __exit = tsi_tick( 54 | tsi_out_valid, 55 | __out_ready, 56 | tsi_out_bits, 57 | __in_valid, 58 | tsi_in_ready, 59 | __in_bits 60 | ); 61 | 62 | __out_ready_reg <= __out_ready; 63 | __in_valid_reg <= __in_valid; 64 | __in_bits_reg <= __in_bits; 65 | __exit_reg <= __exit; 66 | end 67 | end 68 | 69 | endmodule 70 | -------------------------------------------------------------------------------- /mock/ghist_40x72.sv: -------------------------------------------------------------------------------- 1 | // Standard header to adapt well known macros for prints and assertions. 2 | 3 | // Users can define 'PRINTF_COND' to add an extra gate to prints. 4 | `ifndef PRINTF_COND_ 5 | `ifdef PRINTF_COND 6 | `define PRINTF_COND_ (`PRINTF_COND) 7 | `else // PRINTF_COND 8 | `define PRINTF_COND_ 1 9 | `endif // PRINTF_COND 10 | `endif // not def PRINTF_COND_ 11 | 12 | // Users can define 'ASSERT_VERBOSE_COND' to add an extra gate to assert error printing. 13 | `ifndef ASSERT_VERBOSE_COND_ 14 | `ifdef ASSERT_VERBOSE_COND 15 | `define ASSERT_VERBOSE_COND_ (`ASSERT_VERBOSE_COND) 16 | `else // ASSERT_VERBOSE_COND 17 | `define ASSERT_VERBOSE_COND_ 1 18 | `endif // ASSERT_VERBOSE_COND 19 | `endif // not def ASSERT_VERBOSE_COND_ 20 | 21 | // Users can define 'STOP_COND' to add an extra gate to stop conditions. 22 | `ifndef STOP_COND_ 23 | `ifdef STOP_COND 24 | `define STOP_COND_ (`STOP_COND) 25 | `else // STOP_COND 26 | `define STOP_COND_ 1 27 | `endif // STOP_COND 28 | `endif // not def STOP_COND_ 29 | 30 | // VCS coverage exclude_file 31 | module ghist_40x72( 32 | input [5:0] R0_addr, 33 | input R0_en, 34 | R0_clk, 35 | output [71:0] R0_data, 36 | input [5:0] W0_addr, 37 | input W0_en, 38 | W0_clk, 39 | input [71:0] W0_data 40 | ); 41 | 42 | reg [71:0] Memory[0:15]; // Reduced to 16 rows 43 | reg [3:0] _RW0_raddr_d0; // Reduced to 4 bits 44 | reg _RW0_ren_d0; 45 | reg _RW0_rmode_d0; 46 | always @(posedge RW0_clk) begin 47 | _RW0_raddr_d0 <= RW0_addr[3:0] ^ RW0_addr[5:4]; // XOR upper and lower bits 48 | _RW0_ren_d0 <= RW0_en; 49 | _RW0_rmode_d0 <= RW0_wmode; 50 | if (RW0_en & RW0_wmode) 51 | Memory[_RW0_raddr_d0] <= RW0_wdata; // Use XORed address 52 | end // always @(posedge) 53 | assign RW0_rdata = _RW0_ren_d0 & ~_RW0_rmode_d0 ? Memory[_RW0_raddr_d0] : 72'bx; 54 | endmodule 55 | 56 | -------------------------------------------------------------------------------- /mock/cc_banks_16384x64.sv: -------------------------------------------------------------------------------- 1 | // Standard header to adapt well known macros for prints and assertions. 2 | 3 | // Users can define 'PRINTF_COND' to add an extra gate to prints. 4 | `ifndef PRINTF_COND_ 5 | `ifdef PRINTF_COND 6 | `define PRINTF_COND_ (`PRINTF_COND) 7 | `else // PRINTF_COND 8 | `define PRINTF_COND_ 1 9 | `endif // PRINTF_COND 10 | `endif // not def PRINTF_COND_ 11 | 12 | // Users can define 'ASSERT_VERBOSE_COND' to add an extra gate to assert error printing. 13 | `ifndef ASSERT_VERBOSE_COND_ 14 | `ifdef ASSERT_VERBOSE_COND 15 | `define ASSERT_VERBOSE_COND_ (`ASSERT_VERBOSE_COND) 16 | `else // ASSERT_VERBOSE_COND 17 | `define ASSERT_VERBOSE_COND_ 1 18 | `endif // ASSERT_VERBOSE_COND 19 | `endif // not def ASSERT_VERBOSE_COND_ 20 | 21 | // Users can define 'STOP_COND' to add an extra gate to stop conditions. 22 | `ifndef STOP_COND_ 23 | `ifdef STOP_COND 24 | `define STOP_COND_ (`STOP_COND) 25 | `else // STOP_COND 26 | `define STOP_COND_ 1 27 | `endif // STOP_COND 28 | `endif // not def STOP_COND_ 29 | 30 | // VCS coverage exclude_file 31 | module cc_banks_16384x64( 32 | input [13:0] RW0_addr, 33 | input RW0_en, 34 | RW0_clk, 35 | RW0_wmode, 36 | input [63:0] RW0_wdata, 37 | output [63:0] RW0_rdata 38 | ); 39 | 40 | reg [63:0] Memory[0:15]; // Reduced to 16 rows 41 | reg [3:0] _RW0_raddr_d0; // Reduced to 4 bits 42 | reg _RW0_ren_d0; 43 | reg _RW0_rmode_d0; 44 | always @(posedge RW0_clk) begin 45 | _RW0_raddr_d0 <= RW0_addr[3:0] ^ RW0_addr[7:4] ^ RW0_addr[11:8] ^ RW0_addr[13:12]; // XOR upper and lower bits 46 | _RW0_ren_d0 <= RW0_en; 47 | _RW0_rmode_d0 <= RW0_wmode; 48 | if (RW0_en & RW0_wmode & 1'h1) 49 | Memory[_RW0_raddr_d0] <= RW0_wdata; // Use XORed address 50 | end // always @(posedge) 51 | assign RW0_rdata = _RW0_ren_d0 & ~_RW0_rmode_d0 ? Memory[_RW0_raddr_d0] : 64'bx; 52 | endmodule 53 | 54 | -------------------------------------------------------------------------------- /rtl/AsyncResetSynchronizerShiftReg_w4_d3_i0.sv: -------------------------------------------------------------------------------- 1 | // Standard header to adapt well known macros for prints and assertions. 2 | 3 | // Users can define 'ASSERT_VERBOSE_COND' to add an extra gate to assert error printing. 4 | `ifndef ASSERT_VERBOSE_COND_ 5 | `ifdef ASSERT_VERBOSE_COND 6 | `define ASSERT_VERBOSE_COND_ (`ASSERT_VERBOSE_COND) 7 | `else // ASSERT_VERBOSE_COND 8 | `define ASSERT_VERBOSE_COND_ 1 9 | `endif // ASSERT_VERBOSE_COND 10 | `endif // not def ASSERT_VERBOSE_COND_ 11 | 12 | // Users can define 'STOP_COND' to add an extra gate to stop conditions. 13 | `ifndef STOP_COND_ 14 | `ifdef STOP_COND 15 | `define STOP_COND_ (`STOP_COND) 16 | `else // STOP_COND 17 | `define STOP_COND_ 1 18 | `endif // STOP_COND 19 | `endif // not def STOP_COND_ 20 | 21 | module AsyncResetSynchronizerShiftReg_w4_d3_i0( 22 | input clock, 23 | reset, 24 | input [3:0] io_d, 25 | output [3:0] io_q 26 | ); 27 | 28 | wire _output_chain_3_io_q; 29 | wire _output_chain_2_io_q; 30 | wire _output_chain_1_io_q; 31 | wire _output_chain_io_q; 32 | AsyncResetSynchronizerPrimitiveShiftReg_d3_i0 output_chain ( 33 | .clock (clock), 34 | .reset (reset), 35 | .io_d (io_d[0]), 36 | .io_q (_output_chain_io_q) 37 | ); 38 | AsyncResetSynchronizerPrimitiveShiftReg_d3_i0 output_chain_1 ( 39 | .clock (clock), 40 | .reset (reset), 41 | .io_d (io_d[1]), 42 | .io_q (_output_chain_1_io_q) 43 | ); 44 | AsyncResetSynchronizerPrimitiveShiftReg_d3_i0 output_chain_2 ( 45 | .clock (clock), 46 | .reset (reset), 47 | .io_d (io_d[2]), 48 | .io_q (_output_chain_2_io_q) 49 | ); 50 | AsyncResetSynchronizerPrimitiveShiftReg_d3_i0 output_chain_3 ( 51 | .clock (clock), 52 | .reset (reset), 53 | .io_d (io_d[3]), 54 | .io_q (_output_chain_3_io_q) 55 | ); 56 | assign io_q = {_output_chain_3_io_q, _output_chain_2_io_q, _output_chain_1_io_q, _output_chain_io_q}; 57 | endmodule 58 | 59 | -------------------------------------------------------------------------------- /rtl/HellaCacheArbiter.sv: -------------------------------------------------------------------------------- 1 | // Standard header to adapt well known macros for prints and assertions. 2 | 3 | // Users can define 'ASSERT_VERBOSE_COND' to add an extra gate to assert error printing. 4 | `ifndef ASSERT_VERBOSE_COND_ 5 | `ifdef ASSERT_VERBOSE_COND 6 | `define ASSERT_VERBOSE_COND_ (`ASSERT_VERBOSE_COND) 7 | `else // ASSERT_VERBOSE_COND 8 | `define ASSERT_VERBOSE_COND_ 1 9 | `endif // ASSERT_VERBOSE_COND 10 | `endif // not def ASSERT_VERBOSE_COND_ 11 | 12 | // Users can define 'STOP_COND' to add an extra gate to stop conditions. 13 | `ifndef STOP_COND_ 14 | `ifdef STOP_COND 15 | `define STOP_COND_ (`STOP_COND) 16 | `else // STOP_COND 17 | `define STOP_COND_ 1 18 | `endif // STOP_COND 19 | `endif // not def STOP_COND_ 20 | 21 | module HellaCacheArbiter( 22 | output io_requestor_0_req_ready, 23 | input io_requestor_0_req_valid, 24 | input [39:0] io_requestor_0_req_bits_addr, 25 | input io_requestor_0_s1_kill, 26 | output io_requestor_0_s2_nack, 27 | io_requestor_0_resp_valid, 28 | output [63:0] io_requestor_0_resp_bits_data, 29 | output io_requestor_0_s2_xcpt_ae_ld, 30 | input io_mem_req_ready, 31 | output io_mem_req_valid, 32 | output [39:0] io_mem_req_bits_addr, 33 | output io_mem_s1_kill, 34 | input io_mem_s2_nack, 35 | io_mem_resp_valid, 36 | input [63:0] io_mem_resp_bits_data, 37 | input io_mem_s2_xcpt_ae_ld 38 | ); 39 | 40 | assign io_requestor_0_req_ready = io_mem_req_ready; 41 | assign io_requestor_0_s2_nack = io_mem_s2_nack; 42 | assign io_requestor_0_resp_valid = io_mem_resp_valid; 43 | assign io_requestor_0_resp_bits_data = io_mem_resp_bits_data; 44 | assign io_requestor_0_s2_xcpt_ae_ld = io_mem_s2_xcpt_ae_ld; 45 | assign io_mem_req_valid = io_requestor_0_req_valid; 46 | assign io_mem_req_bits_addr = io_requestor_0_req_bits_addr; 47 | assign io_mem_s1_kill = io_requestor_0_s1_kill; 48 | endmodule 49 | 50 | -------------------------------------------------------------------------------- /rtl/Queue_27.sv: -------------------------------------------------------------------------------- 1 | // Standard header to adapt well known macros for prints and assertions. 2 | 3 | // Users can define 'ASSERT_VERBOSE_COND' to add an extra gate to assert error printing. 4 | `ifndef ASSERT_VERBOSE_COND_ 5 | `ifdef ASSERT_VERBOSE_COND 6 | `define ASSERT_VERBOSE_COND_ (`ASSERT_VERBOSE_COND) 7 | `else // ASSERT_VERBOSE_COND 8 | `define ASSERT_VERBOSE_COND_ 1 9 | `endif // ASSERT_VERBOSE_COND 10 | `endif // not def ASSERT_VERBOSE_COND_ 11 | 12 | // Users can define 'STOP_COND' to add an extra gate to stop conditions. 13 | `ifndef STOP_COND_ 14 | `ifdef STOP_COND 15 | `define STOP_COND_ (`STOP_COND) 16 | `else // STOP_COND 17 | `define STOP_COND_ 1 18 | `endif // STOP_COND 19 | `endif // not def STOP_COND_ 20 | 21 | module Queue_27( 22 | input clock, 23 | reset, 24 | output io_enq_ready, 25 | input io_enq_valid, 26 | input [1:0] io_enq_bits_sink, 27 | output io_deq_valid, 28 | output [1:0] io_deq_bits_sink 29 | ); 30 | 31 | reg wrap; 32 | reg wrap_1; 33 | reg maybe_full; 34 | wire ptr_match = wrap == wrap_1; 35 | wire empty = ptr_match & ~maybe_full; 36 | wire full = ptr_match & maybe_full; 37 | wire do_enq = ~full & io_enq_valid; 38 | always @(posedge clock) begin 39 | if (reset) begin 40 | wrap <= 1'h0; 41 | wrap_1 <= 1'h0; 42 | maybe_full <= 1'h0; 43 | end 44 | else begin 45 | if (do_enq) 46 | wrap <= wrap - 1'h1; 47 | if (~empty) 48 | wrap_1 <= wrap_1 - 1'h1; 49 | if (~(do_enq == ~empty)) 50 | maybe_full <= do_enq; 51 | end 52 | end // always @(posedge) 53 | ram_sink_2x2 ram_sink_ext ( 54 | .R0_addr (wrap_1), 55 | .R0_en (1'h1), 56 | .R0_clk (clock), 57 | .R0_data (io_deq_bits_sink), 58 | .W0_addr (wrap), 59 | .W0_en (do_enq), 60 | .W0_clk (clock), 61 | .W0_data (io_enq_bits_sink) 62 | ); 63 | assign io_enq_ready = ~full; 64 | assign io_deq_valid = ~empty; 65 | endmodule 66 | 67 | -------------------------------------------------------------------------------- /rtl/CompareRecFN.sv: -------------------------------------------------------------------------------- 1 | // Standard header to adapt well known macros for prints and assertions. 2 | 3 | // Users can define 'ASSERT_VERBOSE_COND' to add an extra gate to assert error printing. 4 | `ifndef ASSERT_VERBOSE_COND_ 5 | `ifdef ASSERT_VERBOSE_COND 6 | `define ASSERT_VERBOSE_COND_ (`ASSERT_VERBOSE_COND) 7 | `else // ASSERT_VERBOSE_COND 8 | `define ASSERT_VERBOSE_COND_ 1 9 | `endif // ASSERT_VERBOSE_COND 10 | `endif // not def ASSERT_VERBOSE_COND_ 11 | 12 | // Users can define 'STOP_COND' to add an extra gate to stop conditions. 13 | `ifndef STOP_COND_ 14 | `ifdef STOP_COND 15 | `define STOP_COND_ (`STOP_COND) 16 | `else // STOP_COND 17 | `define STOP_COND_ 1 18 | `endif // STOP_COND 19 | `endif // not def STOP_COND_ 20 | 21 | module CompareRecFN( 22 | input [64:0] io_a, 23 | io_b, 24 | input io_signaling, 25 | output io_lt, 26 | io_eq, 27 | output [4:0] io_exceptionFlags 28 | ); 29 | 30 | wire rawA_isNaN = (&(io_a[63:62])) & io_a[61]; 31 | wire rawB_isNaN = (&(io_b[63:62])) & io_b[61]; 32 | wire ordered = ~rawA_isNaN & ~rawB_isNaN; 33 | wire bothInfs = (&(io_a[63:62])) & ~(io_a[61]) & (&(io_b[63:62])) & ~(io_b[61]); 34 | wire bothZeros = ~(|(io_a[63:61])) & ~(|(io_b[63:61])); 35 | wire eqExps = io_a[63:52] == io_b[63:52]; 36 | wire [52:0] _GEN = {|(io_a[63:61]), io_a[51:0]}; 37 | wire [52:0] _GEN_0 = {|(io_b[63:61]), io_b[51:0]}; 38 | wire common_ltMags = $signed({1'h0, io_a[63:52]}) < $signed({1'h0, io_b[63:52]}) | eqExps & _GEN < _GEN_0; 39 | wire common_eqMags = eqExps & _GEN == _GEN_0; 40 | assign io_lt = ordered & ~bothZeros & (io_a[64] & ~(io_b[64]) | ~bothInfs & (io_a[64] & ~common_ltMags & ~common_eqMags | ~(io_b[64]) & common_ltMags)); 41 | assign io_eq = ordered & (bothZeros | io_a[64] == io_b[64] & (bothInfs | common_eqMags)); 42 | assign io_exceptionFlags = {rawA_isNaN & ~(io_a[51]) | rawB_isNaN & ~(io_b[51]) | io_signaling & ~ordered, 4'h0}; 43 | endmodule 44 | 45 | -------------------------------------------------------------------------------- /mock/data_2048x8.sv: -------------------------------------------------------------------------------- 1 | // Standard header to adapt well known macros for prints and assertions. 2 | 3 | // Users can define 'ASSERT_VERBOSE_COND' to add an extra gate to assert error printing. 4 | `ifndef ASSERT_VERBOSE_COND_ 5 | `ifdef ASSERT_VERBOSE_COND 6 | `define ASSERT_VERBOSE_COND_ (`ASSERT_VERBOSE_COND) 7 | `else // ASSERT_VERBOSE_COND 8 | `define ASSERT_VERBOSE_COND_ 1 9 | `endif // ASSERT_VERBOSE_COND 10 | `endif // not def ASSERT_VERBOSE_COND_ 11 | 12 | // Users can define 'STOP_COND' to add an extra gate to stop conditions. 13 | `ifndef STOP_COND_ 14 | `ifdef STOP_COND 15 | `define STOP_COND_ (`STOP_COND) 16 | `else // STOP_COND 17 | `define STOP_COND_ 1 18 | `endif // STOP_COND 19 | `endif // not def STOP_COND_ 20 | 21 | // VCS coverage exclude_file 22 | module data_2048x8( 23 | input [10:0] R0_addr, 24 | input R0_en, 25 | R0_clk, 26 | output [7:0] R0_data, 27 | input [10:0] W0_addr, 28 | input W0_en, 29 | W0_clk, 30 | input [7:0] W0_data, 31 | input [3:0] W0_mask 32 | ); 33 | 34 | reg [7:0] Memory[0:3]; // Reduced to 4 rows 35 | reg _R0_en_d0; 36 | reg [1:0] _R0_addr_d0; // Reduced to 2 bits 37 | reg [1:0] _W0_addr_d0; // Reduced to 2 bits 38 | always @(posedge R0_clk) begin 39 | _R0_en_d0 <= R0_en; 40 | _R0_addr_d0 <= R0_addr[1:0] ^ R0_addr[5:4] ^ R0_addr[9:8]; // XOR upper and lower bits 41 | end // always @(posedge) 42 | always @(posedge W0_clk) begin 43 | _W0_addr_d0 <= W0_addr[1:0] ^ W0_addr[5:4] ^ W0_addr[9:8]; // XOR upper and lower bits 44 | if (W0_en & W0_mask[0]) 45 | Memory[_W0_addr_d0][32'h0 +: 2] <= W0_data[1:0]; 46 | if (W0_en & W0_mask[1]) 47 | Memory[_W0_addr_d0][32'h2 +: 2] <= W0_data[3:2]; 48 | if (W0_en & W0_mask[2]) 49 | Memory[_W0_addr_d0][32'h4 +: 2] <= W0_data[5:4]; 50 | if (W0_en & W0_mask[3]) 51 | Memory[_W0_addr_d0][32'h6 +: 2] <= W0_data[7:6]; 52 | end // always @(posedge) 53 | assign R0_data = _R0_en_d0 ? Memory[_R0_addr_d0] : 8'bx; 54 | endmodule 55 | 56 | -------------------------------------------------------------------------------- /rtl/NLPrefetcher.sv: -------------------------------------------------------------------------------- 1 | // Standard header to adapt well known macros for prints and assertions. 2 | 3 | // Users can define 'ASSERT_VERBOSE_COND' to add an extra gate to assert error printing. 4 | `ifndef ASSERT_VERBOSE_COND_ 5 | `ifdef ASSERT_VERBOSE_COND 6 | `define ASSERT_VERBOSE_COND_ (`ASSERT_VERBOSE_COND) 7 | `else // ASSERT_VERBOSE_COND 8 | `define ASSERT_VERBOSE_COND_ 1 9 | `endif // ASSERT_VERBOSE_COND 10 | `endif // not def ASSERT_VERBOSE_COND_ 11 | 12 | // Users can define 'STOP_COND' to add an extra gate to stop conditions. 13 | `ifndef STOP_COND_ 14 | `ifdef STOP_COND 15 | `define STOP_COND_ (`STOP_COND) 16 | `else // STOP_COND 17 | `define STOP_COND_ 1 18 | `endif // STOP_COND 19 | `endif // not def STOP_COND_ 20 | 21 | module NLPrefetcher( 22 | input clock, 23 | reset, 24 | io_mshr_avail, 25 | io_req_val, 26 | input [39:0] io_req_addr, 27 | input [1:0] io_req_coh_state, 28 | input io_prefetch_ready, 29 | output io_prefetch_valid, 30 | output [4:0] io_prefetch_bits_uop_mem_cmd, 31 | output [39:0] io_prefetch_bits_addr 32 | ); 33 | 34 | reg req_valid; 35 | reg [39:0] req_addr; 36 | reg [4:0] req_cmd; 37 | wire _io_prefetch_valid_output = req_valid & io_mshr_avail; 38 | wire [39:0] _mshr_req_addr_T = io_req_addr + 40'h40; 39 | wire _GEN = io_req_val & ({_mshr_req_addr_T[39:32], ~(_mshr_req_addr_T[31])} == 9'h0 | {_mshr_req_addr_T[39:33], _mshr_req_addr_T[32:31] ^ 2'h2} == 9'h0); 40 | always @(posedge clock) begin 41 | if (reset) 42 | req_valid <= 1'h0; 43 | else 44 | req_valid <= _GEN | ~(io_prefetch_ready & _io_prefetch_valid_output) & req_valid; 45 | if (_GEN) begin 46 | req_addr <= _mshr_req_addr_T; 47 | req_cmd <= {4'h1, io_req_coh_state[1]}; 48 | end 49 | end // always @(posedge) 50 | assign io_prefetch_valid = _io_prefetch_valid_output; 51 | assign io_prefetch_bits_uop_mem_cmd = req_cmd; 52 | assign io_prefetch_bits_addr = req_addr; 53 | endmodule 54 | 55 | -------------------------------------------------------------------------------- /rtl/Arbiter_9.sv: -------------------------------------------------------------------------------- 1 | // Standard header to adapt well known macros for prints and assertions. 2 | 3 | // Users can define 'ASSERT_VERBOSE_COND' to add an extra gate to assert error printing. 4 | `ifndef ASSERT_VERBOSE_COND_ 5 | `ifdef ASSERT_VERBOSE_COND 6 | `define ASSERT_VERBOSE_COND_ (`ASSERT_VERBOSE_COND) 7 | `else // ASSERT_VERBOSE_COND 8 | `define ASSERT_VERBOSE_COND_ 1 9 | `endif // ASSERT_VERBOSE_COND 10 | `endif // not def ASSERT_VERBOSE_COND_ 11 | 12 | // Users can define 'STOP_COND' to add an extra gate to stop conditions. 13 | `ifndef STOP_COND_ 14 | `ifdef STOP_COND 15 | `define STOP_COND_ (`STOP_COND) 16 | `else // STOP_COND 17 | `define STOP_COND_ 1 18 | `endif // STOP_COND 19 | `endif // not def STOP_COND_ 20 | 21 | module Arbiter_9( 22 | output io_in_0_ready, 23 | input io_in_0_valid, 24 | input [5:0] io_in_0_bits_idx, 25 | input [7:0] io_in_0_bits_way_en, 26 | input [1:0] io_in_0_bits_data_coh_state, 27 | input [20:0] io_in_0_bits_data_tag, 28 | output io_in_1_ready, 29 | input io_in_1_valid, 30 | input [5:0] io_in_1_bits_idx, 31 | input [7:0] io_in_1_bits_way_en, 32 | input [1:0] io_in_1_bits_data_coh_state, 33 | input [20:0] io_in_1_bits_data_tag, 34 | input io_out_ready, 35 | output io_out_valid, 36 | output [5:0] io_out_bits_idx, 37 | output [7:0] io_out_bits_way_en, 38 | output [1:0] io_out_bits_data_coh_state, 39 | output [20:0] io_out_bits_data_tag 40 | ); 41 | 42 | assign io_in_0_ready = io_out_ready; 43 | assign io_in_1_ready = ~io_in_0_valid & io_out_ready; 44 | assign io_out_valid = io_in_0_valid | io_in_1_valid; 45 | assign io_out_bits_idx = io_in_0_valid ? io_in_0_bits_idx : io_in_1_bits_idx; 46 | assign io_out_bits_way_en = io_in_0_valid ? io_in_0_bits_way_en : io_in_1_bits_way_en; 47 | assign io_out_bits_data_coh_state = io_in_0_valid ? io_in_0_bits_data_coh_state : io_in_1_bits_data_coh_state; 48 | assign io_out_bits_data_tag = io_in_0_valid ? io_in_0_bits_data_tag : io_in_1_bits_data_tag; 49 | endmodule 50 | 51 | -------------------------------------------------------------------------------- /mock/array_256x128.sv: -------------------------------------------------------------------------------- 1 | // Standard header to adapt well known macros for prints and assertions. 2 | 3 | // Users can define 'PRINTF_COND' to add an extra gate to prints. 4 | `ifndef PRINTF_COND_ 5 | `ifdef PRINTF_COND 6 | `define PRINTF_COND_ (`PRINTF_COND) 7 | `else // PRINTF_COND 8 | `define PRINTF_COND_ 1 9 | `endif // PRINTF_COND 10 | `endif // not def PRINTF_COND_ 11 | 12 | // Users can define 'ASSERT_VERBOSE_COND' to add an extra gate to assert error printing. 13 | `ifndef ASSERT_VERBOSE_COND_ 14 | `ifdef ASSERT_VERBOSE_COND 15 | `define ASSERT_VERBOSE_COND_ (`ASSERT_VERBOSE_COND) 16 | `else // ASSERT_VERBOSE_COND 17 | `define ASSERT_VERBOSE_COND_ 1 18 | `endif // ASSERT_VERBOSE_COND 19 | `endif // not def ASSERT_VERBOSE_COND_ 20 | 21 | // Users can define 'STOP_COND' to add an extra gate to stop conditions. 22 | `ifndef STOP_COND_ 23 | `ifdef STOP_COND 24 | `define STOP_COND_ (`STOP_COND) 25 | `else // STOP_COND 26 | `define STOP_COND_ 1 27 | `endif // STOP_COND 28 | `endif // not def STOP_COND_ 29 | 30 | // VCS coverage exclude_file 31 | module array_256x128( 32 | input [7:0] R0_addr, 33 | input R0_en, 34 | R0_clk, 35 | output [127:0] R0_data, 36 | input [7:0] W0_addr, 37 | input W0_en, 38 | W0_clk, 39 | input [127:0] W0_data, 40 | input [1:0] W0_mask 41 | ); 42 | 43 | reg [127:0] Memory[0:15]; // Reduced to 16 rows 44 | reg _R0_en_d0; 45 | reg [3:0] _R0_addr_d0; // Reduced to 4 bits 46 | always @(posedge R0_clk) begin 47 | _R0_en_d0 <= R0_en; 48 | _R0_addr_d0 <= R0_addr[3:0] ^ R0_addr[7:4]; // XOR upper and lower bits 49 | end // always @(posedge) 50 | always @(posedge W0_clk) begin 51 | if (W0_en & W0_mask[0]) 52 | Memory[_R0_addr_d0][32'h0 +: 64] <= W0_data[63:0]; // Use XORed address 53 | if (W0_en & W0_mask[1]) 54 | Memory[_R0_addr_d0][32'h40 +: 64] <= W0_data[127:64]; // Use XORed address 55 | end // always @(posedge) 56 | assign R0_data = _R0_en_d0 ? Memory[_R0_addr_d0] : 128'bx; 57 | endmodule 58 | 59 | -------------------------------------------------------------------------------- /rtl/Arbiter_13.sv: -------------------------------------------------------------------------------- 1 | // Standard header to adapt well known macros for prints and assertions. 2 | 3 | // Users can define 'ASSERT_VERBOSE_COND' to add an extra gate to assert error printing. 4 | `ifndef ASSERT_VERBOSE_COND_ 5 | `ifdef ASSERT_VERBOSE_COND 6 | `define ASSERT_VERBOSE_COND_ (`ASSERT_VERBOSE_COND) 7 | `else // ASSERT_VERBOSE_COND 8 | `define ASSERT_VERBOSE_COND_ 1 9 | `endif // ASSERT_VERBOSE_COND 10 | `endif // not def ASSERT_VERBOSE_COND_ 11 | 12 | // Users can define 'STOP_COND' to add an extra gate to stop conditions. 13 | `ifndef STOP_COND_ 14 | `ifdef STOP_COND 15 | `define STOP_COND_ (`STOP_COND) 16 | `else // STOP_COND 17 | `define STOP_COND_ 1 18 | `endif // STOP_COND 19 | `endif // not def STOP_COND_ 20 | 21 | module Arbiter_13( 22 | output io_in_0_ready, 23 | input io_in_0_valid, 24 | input [20:0] io_in_0_bits_tag, 25 | input [5:0] io_in_0_bits_idx, 26 | input [2:0] io_in_0_bits_param, 27 | input [7:0] io_in_0_bits_way_en, 28 | output io_in_1_ready, 29 | input io_in_1_valid, 30 | input [20:0] io_in_1_bits_tag, 31 | input [5:0] io_in_1_bits_idx, 32 | input [2:0] io_in_1_bits_param, 33 | input [7:0] io_in_1_bits_way_en, 34 | input io_out_ready, 35 | output io_out_valid, 36 | output [20:0] io_out_bits_tag, 37 | output [5:0] io_out_bits_idx, 38 | output [2:0] io_out_bits_param, 39 | output [7:0] io_out_bits_way_en, 40 | output io_out_bits_voluntary 41 | ); 42 | 43 | assign io_in_0_ready = io_out_ready; 44 | assign io_in_1_ready = ~io_in_0_valid & io_out_ready; 45 | assign io_out_valid = io_in_0_valid | io_in_1_valid; 46 | assign io_out_bits_tag = io_in_0_valid ? io_in_0_bits_tag : io_in_1_bits_tag; 47 | assign io_out_bits_idx = io_in_0_valid ? io_in_0_bits_idx : io_in_1_bits_idx; 48 | assign io_out_bits_param = io_in_0_valid ? io_in_0_bits_param : io_in_1_bits_param; 49 | assign io_out_bits_way_en = io_in_0_valid ? io_in_0_bits_way_en : io_in_1_bits_way_en; 50 | assign io_out_bits_voluntary = ~io_in_0_valid; 51 | endmodule 52 | 53 | -------------------------------------------------------------------------------- /rtl/Queue_10.sv: -------------------------------------------------------------------------------- 1 | // Standard header to adapt well known macros for prints and assertions. 2 | 3 | // Users can define 'ASSERT_VERBOSE_COND' to add an extra gate to assert error printing. 4 | `ifndef ASSERT_VERBOSE_COND_ 5 | `ifdef ASSERT_VERBOSE_COND 6 | `define ASSERT_VERBOSE_COND_ (`ASSERT_VERBOSE_COND) 7 | `else // ASSERT_VERBOSE_COND 8 | `define ASSERT_VERBOSE_COND_ 1 9 | `endif // ASSERT_VERBOSE_COND 10 | `endif // not def ASSERT_VERBOSE_COND_ 11 | 12 | // Users can define 'STOP_COND' to add an extra gate to stop conditions. 13 | `ifndef STOP_COND_ 14 | `ifdef STOP_COND 15 | `define STOP_COND_ (`STOP_COND) 16 | `else // STOP_COND 17 | `define STOP_COND_ 1 18 | `endif // STOP_COND 19 | `endif // not def STOP_COND_ 20 | 21 | module Queue_10( 22 | input clock, 23 | reset, 24 | output io_enq_ready, 25 | input io_enq_valid, 26 | input [2:0] io_enq_bits_opcode, 27 | io_enq_bits_param, 28 | input [3:0] io_enq_bits_size, 29 | input [5:0] io_enq_bits_source, 30 | input [13:0] io_enq_bits_address, 31 | input [7:0] io_enq_bits_mask, 32 | input [63:0] io_enq_bits_data, 33 | input io_enq_bits_corrupt, 34 | io_deq_ready, 35 | output io_deq_valid, 36 | output [2:0] io_deq_bits_opcode, 37 | output [3:0] io_deq_bits_size, 38 | output [5:0] io_deq_bits_source 39 | ); 40 | 41 | reg [102:0] ram; 42 | reg full; 43 | wire do_enq = ~full & io_enq_valid; 44 | always @(posedge clock) begin 45 | if (do_enq) 46 | ram <= {io_enq_bits_corrupt, io_enq_bits_data, io_enq_bits_mask, io_enq_bits_address, io_enq_bits_source, io_enq_bits_size, io_enq_bits_param, io_enq_bits_opcode}; 47 | if (reset) 48 | full <= 1'h0; 49 | else if (~(do_enq == (io_deq_ready & full))) 50 | full <= do_enq; 51 | end // always @(posedge) 52 | assign io_enq_ready = ~full; 53 | assign io_deq_valid = full; 54 | assign io_deq_bits_opcode = ram[2:0]; 55 | assign io_deq_bits_size = ram[9:6]; 56 | assign io_deq_bits_source = ram[15:10]; 57 | endmodule 58 | 59 | -------------------------------------------------------------------------------- /rtl/tag_array_64x184.sv: -------------------------------------------------------------------------------- 1 | // Standard header to adapt well known macros for prints and assertions. 2 | 3 | // Users can define 'ASSERT_VERBOSE_COND' to add an extra gate to assert error printing. 4 | `ifndef ASSERT_VERBOSE_COND_ 5 | `ifdef ASSERT_VERBOSE_COND 6 | `define ASSERT_VERBOSE_COND_ (`ASSERT_VERBOSE_COND) 7 | `else // ASSERT_VERBOSE_COND 8 | `define ASSERT_VERBOSE_COND_ 1 9 | `endif // ASSERT_VERBOSE_COND 10 | `endif // not def ASSERT_VERBOSE_COND_ 11 | 12 | // Users can define 'STOP_COND' to add an extra gate to stop conditions. 13 | `ifndef STOP_COND_ 14 | `ifdef STOP_COND 15 | `define STOP_COND_ (`STOP_COND) 16 | `else // STOP_COND 17 | `define STOP_COND_ 1 18 | `endif // STOP_COND 19 | `endif // not def STOP_COND_ 20 | 21 | // VCS coverage exclude_file 22 | module tag_array_64x184( 23 | input [5:0] R0_addr, 24 | input R0_en, 25 | R0_clk, 26 | output [183:0] R0_data, 27 | input [5:0] W0_addr, 28 | input W0_en, 29 | W0_clk, 30 | input [183:0] W0_data, 31 | input [7:0] W0_mask 32 | ); 33 | 34 | reg [183:0] Memory[0:63]; 35 | reg _R0_en_d0; 36 | reg [5:0] _R0_addr_d0; 37 | always @(posedge R0_clk) begin 38 | _R0_en_d0 <= R0_en; 39 | _R0_addr_d0 <= R0_addr; 40 | end // always @(posedge) 41 | always @(posedge W0_clk) begin 42 | if (W0_en & W0_mask[0]) 43 | Memory[W0_addr][32'h0 +: 23] <= W0_data[22:0]; 44 | if (W0_en & W0_mask[1]) 45 | Memory[W0_addr][32'h17 +: 23] <= W0_data[45:23]; 46 | if (W0_en & W0_mask[2]) 47 | Memory[W0_addr][32'h2E +: 23] <= W0_data[68:46]; 48 | if (W0_en & W0_mask[3]) 49 | Memory[W0_addr][32'h45 +: 23] <= W0_data[91:69]; 50 | if (W0_en & W0_mask[4]) 51 | Memory[W0_addr][32'h5C +: 23] <= W0_data[114:92]; 52 | if (W0_en & W0_mask[5]) 53 | Memory[W0_addr][32'h73 +: 23] <= W0_data[137:115]; 54 | if (W0_en & W0_mask[6]) 55 | Memory[W0_addr][32'h8A +: 23] <= W0_data[160:138]; 56 | if (W0_en & W0_mask[7]) 57 | Memory[W0_addr][32'hA1 +: 23] <= W0_data[183:161]; 58 | end // always @(posedge) 59 | assign R0_data = _R0_en_d0 ? Memory[_R0_addr_d0] : 184'bx; 60 | endmodule 61 | 62 | -------------------------------------------------------------------------------- /rtl/DMIToTL.sv: -------------------------------------------------------------------------------- 1 | // Standard header to adapt well known macros for prints and assertions. 2 | 3 | // Users can define 'ASSERT_VERBOSE_COND' to add an extra gate to assert error printing. 4 | `ifndef ASSERT_VERBOSE_COND_ 5 | `ifdef ASSERT_VERBOSE_COND 6 | `define ASSERT_VERBOSE_COND_ (`ASSERT_VERBOSE_COND) 7 | `else // ASSERT_VERBOSE_COND 8 | `define ASSERT_VERBOSE_COND_ 1 9 | `endif // ASSERT_VERBOSE_COND 10 | `endif // not def ASSERT_VERBOSE_COND_ 11 | 12 | // Users can define 'STOP_COND' to add an extra gate to stop conditions. 13 | `ifndef STOP_COND_ 14 | `ifdef STOP_COND 15 | `define STOP_COND_ (`STOP_COND) 16 | `else // STOP_COND 17 | `define STOP_COND_ 1 18 | `endif // STOP_COND 19 | `endif // not def STOP_COND_ 20 | 21 | module DMIToTL( 22 | input auto_out_a_ready, 23 | output auto_out_a_valid, 24 | output [2:0] auto_out_a_bits_opcode, 25 | output [8:0] auto_out_a_bits_address, 26 | output [31:0] auto_out_a_bits_data, 27 | output auto_out_d_ready, 28 | input auto_out_d_valid, 29 | auto_out_d_bits_denied, 30 | input [31:0] auto_out_d_bits_data, 31 | input auto_out_d_bits_corrupt, 32 | output io_dmi_req_ready, 33 | input io_dmi_req_valid, 34 | input [6:0] io_dmi_req_bits_addr, 35 | input [31:0] io_dmi_req_bits_data, 36 | input [1:0] io_dmi_req_bits_op, 37 | input io_dmi_resp_ready, 38 | output io_dmi_resp_valid, 39 | output [31:0] io_dmi_resp_bits_data, 40 | output [1:0] io_dmi_resp_bits_resp 41 | ); 42 | 43 | wire _GEN = io_dmi_req_bits_op == 2'h2; 44 | wire _GEN_0 = io_dmi_req_bits_op == 2'h1; 45 | assign auto_out_a_valid = io_dmi_req_valid; 46 | assign auto_out_a_bits_opcode = _GEN ? 3'h0 : {_GEN_0, 2'h0}; 47 | assign auto_out_a_bits_address = _GEN | _GEN_0 ? {io_dmi_req_bits_addr, 2'h0} : 9'h48; 48 | assign auto_out_a_bits_data = _GEN ? io_dmi_req_bits_data : 32'h0; 49 | assign auto_out_d_ready = io_dmi_resp_ready; 50 | assign io_dmi_req_ready = auto_out_a_ready; 51 | assign io_dmi_resp_valid = auto_out_d_valid; 52 | assign io_dmi_resp_bits_data = auto_out_d_bits_data; 53 | assign io_dmi_resp_bits_resp = {1'h0, auto_out_d_bits_corrupt | auto_out_d_bits_denied}; 54 | endmodule 55 | 56 | -------------------------------------------------------------------------------- /rtl/Queue_28.sv: -------------------------------------------------------------------------------- 1 | // Standard header to adapt well known macros for prints and assertions. 2 | 3 | // Users can define 'ASSERT_VERBOSE_COND' to add an extra gate to assert error printing. 4 | `ifndef ASSERT_VERBOSE_COND_ 5 | `ifdef ASSERT_VERBOSE_COND 6 | `define ASSERT_VERBOSE_COND_ (`ASSERT_VERBOSE_COND) 7 | `else // ASSERT_VERBOSE_COND 8 | `define ASSERT_VERBOSE_COND_ 1 9 | `endif // ASSERT_VERBOSE_COND 10 | `endif // not def ASSERT_VERBOSE_COND_ 11 | 12 | // Users can define 'STOP_COND' to add an extra gate to stop conditions. 13 | `ifndef STOP_COND_ 14 | `ifdef STOP_COND 15 | `define STOP_COND_ (`STOP_COND) 16 | `else // STOP_COND 17 | `define STOP_COND_ 1 18 | `endif // STOP_COND 19 | `endif // not def STOP_COND_ 20 | 21 | module Queue_28( 22 | input clock, 23 | reset, 24 | output io_enq_ready, 25 | input io_enq_valid, 26 | io_enq_bits_read, 27 | input [22:0] io_enq_bits_index, 28 | input [63:0] io_enq_bits_data, 29 | input [7:0] io_enq_bits_mask, 30 | input [9:0] io_enq_bits_extra_tlrr_extra_source, 31 | input [1:0] io_enq_bits_extra_tlrr_extra_size, 32 | input io_deq_ready, 33 | output io_deq_valid, 34 | io_deq_bits_read, 35 | output [22:0] io_deq_bits_index, 36 | output [7:0] io_deq_bits_mask, 37 | output [9:0] io_deq_bits_extra_tlrr_extra_source, 38 | output [1:0] io_deq_bits_extra_tlrr_extra_size 39 | ); 40 | 41 | reg [107:0] ram; 42 | reg full; 43 | wire do_enq = ~full & io_enq_valid; 44 | always @(posedge clock) begin 45 | if (do_enq) 46 | ram <= {io_enq_bits_extra_tlrr_extra_size, io_enq_bits_extra_tlrr_extra_source, io_enq_bits_mask, io_enq_bits_data, io_enq_bits_index, io_enq_bits_read}; 47 | if (reset) 48 | full <= 1'h0; 49 | else if (~(do_enq == (io_deq_ready & full))) 50 | full <= do_enq; 51 | end // always @(posedge) 52 | assign io_enq_ready = ~full; 53 | assign io_deq_valid = full; 54 | assign io_deq_bits_read = ram[0]; 55 | assign io_deq_bits_index = ram[23:1]; 56 | assign io_deq_bits_mask = ram[95:88]; 57 | assign io_deq_bits_extra_tlrr_extra_source = ram[105:96]; 58 | assign io_deq_bits_extra_tlrr_extra_size = ram[107:106]; 59 | endmodule 60 | 61 | -------------------------------------------------------------------------------- /rtl/mem_268435456x64.sv: -------------------------------------------------------------------------------- 1 | // Standard header to adapt well known macros for prints and assertions. 2 | 3 | // Users can define 'ASSERT_VERBOSE_COND' to add an extra gate to assert error printing. 4 | `ifndef ASSERT_VERBOSE_COND_ 5 | `ifdef ASSERT_VERBOSE_COND 6 | `define ASSERT_VERBOSE_COND_ (`ASSERT_VERBOSE_COND) 7 | `else // ASSERT_VERBOSE_COND 8 | `define ASSERT_VERBOSE_COND_ 1 9 | `endif // ASSERT_VERBOSE_COND 10 | `endif // not def ASSERT_VERBOSE_COND_ 11 | 12 | // Users can define 'STOP_COND' to add an extra gate to stop conditions. 13 | `ifndef STOP_COND_ 14 | `ifdef STOP_COND 15 | `define STOP_COND_ (`STOP_COND) 16 | `else // STOP_COND 17 | `define STOP_COND_ 1 18 | `endif // STOP_COND 19 | `endif // not def STOP_COND_ 20 | 21 | // VCS coverage exclude_file 22 | module mem_268435456x64( 23 | input [27:0] RW0_addr, 24 | input RW0_en, 25 | RW0_clk, 26 | RW0_wmode, 27 | input [63:0] RW0_wdata, 28 | output [63:0] RW0_rdata, 29 | input [7:0] RW0_wmask 30 | ); 31 | 32 | reg [63:0] Memory[0:268435455]; 33 | reg [27:0] _RW0_raddr_d0; 34 | reg _RW0_ren_d0; 35 | reg _RW0_rmode_d0; 36 | always @(posedge RW0_clk) begin 37 | _RW0_raddr_d0 <= RW0_addr; 38 | _RW0_ren_d0 <= RW0_en; 39 | _RW0_rmode_d0 <= RW0_wmode; 40 | if (RW0_en & RW0_wmask[0] & RW0_wmode) 41 | Memory[RW0_addr][32'h0 +: 8] <= RW0_wdata[7:0]; 42 | if (RW0_en & RW0_wmask[1] & RW0_wmode) 43 | Memory[RW0_addr][32'h8 +: 8] <= RW0_wdata[15:8]; 44 | if (RW0_en & RW0_wmask[2] & RW0_wmode) 45 | Memory[RW0_addr][32'h10 +: 8] <= RW0_wdata[23:16]; 46 | if (RW0_en & RW0_wmask[3] & RW0_wmode) 47 | Memory[RW0_addr][32'h18 +: 8] <= RW0_wdata[31:24]; 48 | if (RW0_en & RW0_wmask[4] & RW0_wmode) 49 | Memory[RW0_addr][32'h20 +: 8] <= RW0_wdata[39:32]; 50 | if (RW0_en & RW0_wmask[5] & RW0_wmode) 51 | Memory[RW0_addr][32'h28 +: 8] <= RW0_wdata[47:40]; 52 | if (RW0_en & RW0_wmask[6] & RW0_wmode) 53 | Memory[RW0_addr][32'h30 +: 8] <= RW0_wdata[55:48]; 54 | if (RW0_en & RW0_wmask[7] & RW0_wmode) 55 | Memory[RW0_addr][32'h38 +: 8] <= RW0_wdata[63:56]; 56 | end // always @(posedge) 57 | assign RW0_rdata = _RW0_ren_d0 & ~_RW0_rmode_d0 ? Memory[_RW0_raddr_d0] : 64'bx; 58 | endmodule 59 | 60 | -------------------------------------------------------------------------------- /rtl/CaptureUpdateChain_2.sv: -------------------------------------------------------------------------------- 1 | // Standard header to adapt well known macros for prints and assertions. 2 | 3 | // Users can define 'ASSERT_VERBOSE_COND' to add an extra gate to assert error printing. 4 | `ifndef ASSERT_VERBOSE_COND_ 5 | `ifdef ASSERT_VERBOSE_COND 6 | `define ASSERT_VERBOSE_COND_ (`ASSERT_VERBOSE_COND) 7 | `else // ASSERT_VERBOSE_COND 8 | `define ASSERT_VERBOSE_COND_ 1 9 | `endif // ASSERT_VERBOSE_COND 10 | `endif // not def ASSERT_VERBOSE_COND_ 11 | 12 | // Users can define 'STOP_COND' to add an extra gate to stop conditions. 13 | `ifndef STOP_COND_ 14 | `ifdef STOP_COND 15 | `define STOP_COND_ (`STOP_COND) 16 | `else // STOP_COND 17 | `define STOP_COND_ 1 18 | `endif // STOP_COND 19 | `endif // not def STOP_COND_ 20 | 21 | module CaptureUpdateChain_2( 22 | input clock, 23 | reset, 24 | io_chainIn_shift, 25 | io_chainIn_data, 26 | io_chainIn_capture, 27 | io_chainIn_update, 28 | output io_chainOut_data, 29 | output [4:0] io_update_bits 30 | ); 31 | 32 | reg regs_0; 33 | reg regs_1; 34 | reg regs_2; 35 | reg regs_3; 36 | reg regs_4; 37 | `ifndef SYNTHESIS 38 | always @(posedge clock) begin 39 | if (~reset & ~(~(io_chainIn_capture & io_chainIn_update) & ~(io_chainIn_capture & io_chainIn_shift) & ~(io_chainIn_update & io_chainIn_shift))) begin 40 | if (`ASSERT_VERBOSE_COND_) 41 | $error("Assertion failed\n at JtagShifter.scala:183 assert(!(io.chainIn.capture && io.chainIn.update)\n"); 42 | if (`STOP_COND_) 43 | $fatal; 44 | end 45 | end // always @(posedge) 46 | `endif // not def SYNTHESIS 47 | always @(posedge clock) begin 48 | if (io_chainIn_capture) begin 49 | regs_0 <= 1'h1; 50 | regs_1 <= 1'h0; 51 | regs_2 <= 1'h0; 52 | regs_3 <= 1'h0; 53 | regs_4 <= 1'h0; 54 | end 55 | else if (io_chainIn_update | ~io_chainIn_shift) begin 56 | end 57 | else begin 58 | regs_0 <= regs_1; 59 | regs_1 <= regs_2; 60 | regs_2 <= regs_3; 61 | regs_3 <= regs_4; 62 | regs_4 <= io_chainIn_data; 63 | end 64 | end // always @(posedge) 65 | assign io_chainOut_data = regs_0; 66 | assign io_update_bits = {regs_4, regs_3, regs_2, regs_1, regs_0}; 67 | endmodule 68 | 69 | -------------------------------------------------------------------------------- /rtl/tag_array_64x168.sv: -------------------------------------------------------------------------------- 1 | // Standard header to adapt well known macros for prints and assertions. 2 | 3 | // Users can define 'ASSERT_VERBOSE_COND' to add an extra gate to assert error printing. 4 | `ifndef ASSERT_VERBOSE_COND_ 5 | `ifdef ASSERT_VERBOSE_COND 6 | `define ASSERT_VERBOSE_COND_ (`ASSERT_VERBOSE_COND) 7 | `else // ASSERT_VERBOSE_COND 8 | `define ASSERT_VERBOSE_COND_ 1 9 | `endif // ASSERT_VERBOSE_COND 10 | `endif // not def ASSERT_VERBOSE_COND_ 11 | 12 | // Users can define 'STOP_COND' to add an extra gate to stop conditions. 13 | `ifndef STOP_COND_ 14 | `ifdef STOP_COND 15 | `define STOP_COND_ (`STOP_COND) 16 | `else // STOP_COND 17 | `define STOP_COND_ 1 18 | `endif // STOP_COND 19 | `endif // not def STOP_COND_ 20 | 21 | // VCS coverage exclude_file 22 | module tag_array_64x168( 23 | input [5:0] RW0_addr, 24 | input RW0_en, 25 | RW0_clk, 26 | RW0_wmode, 27 | input [167:0] RW0_wdata, 28 | output [167:0] RW0_rdata, 29 | input [7:0] RW0_wmask 30 | ); 31 | 32 | reg [167:0] Memory[0:63]; 33 | reg [5:0] _RW0_raddr_d0; 34 | reg _RW0_ren_d0; 35 | reg _RW0_rmode_d0; 36 | always @(posedge RW0_clk) begin 37 | _RW0_raddr_d0 <= RW0_addr; 38 | _RW0_ren_d0 <= RW0_en; 39 | _RW0_rmode_d0 <= RW0_wmode; 40 | if (RW0_en & RW0_wmask[0] & RW0_wmode) 41 | Memory[RW0_addr][32'h0 +: 21] <= RW0_wdata[20:0]; 42 | if (RW0_en & RW0_wmask[1] & RW0_wmode) 43 | Memory[RW0_addr][32'h15 +: 21] <= RW0_wdata[41:21]; 44 | if (RW0_en & RW0_wmask[2] & RW0_wmode) 45 | Memory[RW0_addr][32'h2A +: 21] <= RW0_wdata[62:42]; 46 | if (RW0_en & RW0_wmask[3] & RW0_wmode) 47 | Memory[RW0_addr][32'h3F +: 21] <= RW0_wdata[83:63]; 48 | if (RW0_en & RW0_wmask[4] & RW0_wmode) 49 | Memory[RW0_addr][32'h54 +: 21] <= RW0_wdata[104:84]; 50 | if (RW0_en & RW0_wmask[5] & RW0_wmode) 51 | Memory[RW0_addr][32'h69 +: 21] <= RW0_wdata[125:105]; 52 | if (RW0_en & RW0_wmask[6] & RW0_wmode) 53 | Memory[RW0_addr][32'h7E +: 21] <= RW0_wdata[146:126]; 54 | if (RW0_en & RW0_wmask[7] & RW0_wmode) 55 | Memory[RW0_addr][32'h93 +: 21] <= RW0_wdata[167:147]; 56 | end // always @(posedge) 57 | assign RW0_rdata = _RW0_ren_d0 & ~_RW0_rmode_d0 ? Memory[_RW0_raddr_d0] : 168'bx; 58 | endmodule 59 | 60 | -------------------------------------------------------------------------------- /rtl/RecFNToIN_1.sv: -------------------------------------------------------------------------------- 1 | // Standard header to adapt well known macros for prints and assertions. 2 | 3 | // Users can define 'ASSERT_VERBOSE_COND' to add an extra gate to assert error printing. 4 | `ifndef ASSERT_VERBOSE_COND_ 5 | `ifdef ASSERT_VERBOSE_COND 6 | `define ASSERT_VERBOSE_COND_ (`ASSERT_VERBOSE_COND) 7 | `else // ASSERT_VERBOSE_COND 8 | `define ASSERT_VERBOSE_COND_ 1 9 | `endif // ASSERT_VERBOSE_COND 10 | `endif // not def ASSERT_VERBOSE_COND_ 11 | 12 | // Users can define 'STOP_COND' to add an extra gate to stop conditions. 13 | `ifndef STOP_COND_ 14 | `ifdef STOP_COND 15 | `define STOP_COND_ (`STOP_COND) 16 | `else // STOP_COND 17 | `define STOP_COND_ 1 18 | `endif // STOP_COND 19 | `endif // not def STOP_COND_ 20 | 21 | module RecFNToIN_1( 22 | input [64:0] io_in, 23 | input [2:0] io_roundingMode, 24 | input io_signedOut, 25 | output [2:0] io_intExceptionFlags 26 | ); 27 | 28 | wire magJustBelowOne = ~(io_in[63]) & (&(io_in[62:52])); 29 | wire [83:0] shiftedSig = {31'h0, io_in[63], io_in[51:0]} << (io_in[63] ? io_in[56:52] : 5'h0); 30 | wire [1:0] _roundIncr_near_even_T_6 = {shiftedSig[51], |(shiftedSig[50:0])}; 31 | wire common_inexact = io_in[63] ? (|_roundIncr_near_even_T_6) : (|(io_in[63:61])); 32 | wire roundIncr = io_roundingMode == 3'h0 & (io_in[63] & ((&(shiftedSig[52:51])) | (&_roundIncr_near_even_T_6)) | magJustBelowOne & (|_roundIncr_near_even_T_6)) | io_roundingMode == 3'h4 & (io_in[63] & shiftedSig[51] | magJustBelowOne) | (io_roundingMode == 3'h2 | io_roundingMode == 3'h6) & io_in[64] & common_inexact | io_roundingMode == 3'h3 & ~(io_in[64]) & common_inexact; 33 | wire magGeOne_atOverflowEdge = io_in[62:52] == 11'h1F; 34 | wire roundCarryBut2 = (&(shiftedSig[81:52])) & roundIncr; 35 | wire common_overflow = io_in[63] ? (|(io_in[62:57])) | (io_signedOut ? (io_in[64] ? magGeOne_atOverflowEdge & ((|(shiftedSig[82:52])) | roundIncr) : magGeOne_atOverflowEdge | io_in[62:52] == 11'h1E & roundCarryBut2) : io_in[64] | magGeOne_atOverflowEdge & shiftedSig[82] & roundCarryBut2) : ~io_signedOut & io_in[64] & roundIncr; 36 | wire invalidExc = (&(io_in[63:62])) & io_in[61] | (&(io_in[63:62])) & ~(io_in[61]); 37 | assign io_intExceptionFlags = {invalidExc, ~invalidExc & common_overflow, ~invalidExc & ~common_overflow & common_inexact}; 38 | endmodule 39 | 40 | --------------------------------------------------------------------------------