├── .gitmodules ├── LICENSE ├── README.md ├── applyPatch.sh ├── exercise1 ├── config.mk └── solution │ └── config.mk ├── exercise2 ├── alu.v ├── config.mk ├── constraint.sdc └── solution │ └── config.mk ├── exercise3 ├── alu.v ├── config.mk ├── constraint.sdc └── solution │ └── data.csv ├── exercise4 ├── alu.v ├── config.mk ├── constraint.sdc └── solution │ └── data.csv ├── exercise5 ├── config.mk ├── constraint.sdc ├── counter.v └── solution │ ├── config.mk │ └── constraint.sdc └── patchfile.patch /.gitmodules: -------------------------------------------------------------------------------- 1 | [submodule "OpenROAD-flow-scripts"] 2 | path = OpenROAD-flow-scripts 3 | url = ../OpenROAD-flow-scripts.git 4 | -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | BSD 3-Clause License 2 | 3 | Copyright (c) 2022, Austin Rovinski 4 | All rights reserved. 5 | 6 | Redistribution and use in source and binary forms, with or without 7 | modification, are permitted provided that the following conditions are met: 8 | 9 | 1. Redistributions of source code must retain the above copyright notice, this 10 | list of conditions and the following disclaimer. 11 | 12 | 2. Redistributions in binary form must reproduce the above copyright notice, 13 | this list of conditions and the following disclaimer in the documentation 14 | and/or other materials provided with the distribution. 15 | 16 | 3. Neither the name of the copyright holder nor the names of its 17 | contributors may be used to endorse or promote products derived from 18 | this software without specific prior written permission. 19 | 20 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 23 | DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 24 | FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 | DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 26 | SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 27 | CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 28 | OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 29 | OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # OpenROAD: Open-Source ASIC Design for Computer Architects 2 | 3 | This repository contains all material needed to participate in the tutorial hosted at MICRO 2022. 4 | Please see the [tutorial website](https://the-openroad-project.github.io/micro2022tutorial) for more information. 5 | 6 | ## Tutorial Info 7 | **Date**: Saturday, October 1, 2022 8 | 9 | **Time**: 1 PM - 5 PM CST (afternoon session) 10 | 11 | **Location**: [The Westin Chicago River North Hotel](https://www.marriott.com/en-us/hotels/chino-the-westin-chicago-river-north/), 12 | Chicago, IL, USA. Room TBD. 13 | 14 | ## Preparation and Installation 15 | See [Tutorial Preparation](https://the-openroad-project.github.io/micro2022tutorial/content/0-prep.html). 16 | 17 | 18 | # Demos and Exercises 19 | :exclamation: All demos and exercises must be performed with your current directory as 20 | `micro2022tutorial/OpenROAD-flow-scripts/flow`. 21 | 22 | ## Demo 1: Running the Flow 23 | 24 | Follow along as the presenter explains each step / sub-step of the flow (click to expand each section). 25 | 26 |
27 |

Synthesis

 28 | 29 | Run `make synth` and examine the output: 30 | 31 | 1. Perform file preprocessing (mainly for yosys) 32 | ``` 33 | ./util/markDontUse.py 34 | Marked 4 cells as dont_use 35 | Commented 0 lines containing "original_pin" 36 | Replaced malformed functions 0 37 | Writing replaced file: objects/nangate45/gcd/base/lib/NangateOpenCellLibrary_typical.lib 38 | ``` 39 | 2. Parse input files 40 | ``` 41 | 1. Executing Verilog-2005 frontend: ./designs/src/gcd/gcd.v 42 | 2. Executing Liberty frontend. 43 | 3. Executing Verilog-2005 frontend: ./platforms/nangate45/cells_clkgate.v 44 | ``` 45 | 3. Elaborate the design 46 | ``` 47 | 4.1 Executing HIERARCHY pass (managing design hierarchy). 48 | 4.2 Executing AST frontend in derive mose using pre-parses AST for module `\gcd'. 49 | # ... 50 | 4.3. Executing PROC pass (convert processes to netlists) 51 | # ... 52 | ``` 53 | 4. Optimize the netlist 54 | ``` 55 | 4.4. Executing FLATTEN pass (flatten design). 56 | 4.5. Executing OPT_EXPR pass (perform const folding). 57 | 4.6. Executing OPT_CLEAN pass (remove unused cells and wires). 58 | 4.7. Executing CHECK pass (checking for obvious problems). 59 | 4.8. Executing OPT pass (perform simple optimizations). 60 | # ... 61 | ``` 62 | 5. Map the generic netlist cells to technology specific cells 63 | ``` 64 | 4.22. Executing TECHMAP pass (map to technology primitives). 65 | # ... 66 | 6. Executing TECHMAP pass (map to technology primitives). 67 | # ... 68 | 9. Executing ABC pass (technology mapping using ABC). 69 | ``` 70 | 6. Generate Verilog netlist 71 | ``` 72 | 17. Executing Verilog backend. 73 | ``` 74 |
75 | 76 |
77 |

Floorplanning

 78 | 79 | Run `make floorplan` and examine the output: 80 | 81 | 1. Initialize chip area 82 | ``` 83 | [INFO IFP-0001] Added 35 rows of 263 sites. 84 | ``` 85 | 2. I/O pin placement 86 | ``` 87 | Using 1u default distance from corners. 88 | Using 2 tracks default min distance between IO pins. 89 | [INFO PPL-0007] Random pin placement. 90 | ``` 91 | 3. Insert tapcells and endcaps 92 | ``` 93 | [INFO TAP-0004] Inserted 70 endcaps. 94 | [INFO TAP-0005] Inserted 0 tapcells. 95 | ``` 96 | 4. Generate power grid 97 | ``` 98 | [INFO PDN-0001] Inserting grid: grid 99 | ``` 100 | See this step in the GUI: 101 | ``` 102 | $ make gui_floorplan 103 | ``` 104 |
105 | 106 |
107 |

Global Placement

 108 | 109 | Run `make place` and examine the output: 110 | 111 | 1. Initial place 112 | ``` 113 | [InitialPlace] Iter: 1 CG residual: 0.00000008 HPWL: 7481451 114 | [InitialPlace] Iter: 2 CG residual: 0.00000006 HPWL: 6842787 115 | [InitialPlace] Iter: 3 CG residual: 0.00000009 HPWL: 6812234 116 | [InitialPlace] Iter: 4 CG residual: 0.00000007 HPWL: 6797416 117 | [InitialPlace] Iter: 5 CG residual: 0.00000009 HPWL: 6771698 118 | ``` 119 | 2. Nesterov gradient descent (with timing-driven weighting) 120 | ``` 121 | [NesterovSolve] Iter: 10 overflow: 0.408459 HPWL: 5518685 122 | [NesterovSolve] Iter: 20 overflow: 0.369914 HPWL: 5301283 123 | [NesterovSolve] Iter: 30 overflow: 0.356915 HPWL: 5274819 124 | [NesterovSolve] Iter: 40 overflow: 0.355273 HPWL: 5251818 125 | [NesterovSolve] Iter: 50 overflow: 0.357892 HPWL: 5262578 126 | # ... 127 | [INFO GPL-0100] worst slack -6.41e-11 128 | [INFO GPL-0103] Weighted 38 nets. 129 | # ... 130 | [NesterovSolve] Iter: 350 overflow: 0.105841 HPWL: 5296714 131 | [NesterovSolve] Finished with Overflow: 0.098895 132 | ``` 133 | 3. Timing optimization and electrical rule fixing 134 | ``` 135 | Perform port buffering... 136 | [INFO RSZ-0027] Inserted 35 input buffers. 137 | [INFO RSZ-0028] Inserted 18 output buffers. 138 | Perform buffer insertion... 139 | [INFO RSZ-0058] Using max wire length 661um. 140 | [INFO RSZ-0039] Resized 39 instances. 141 | Repair tie lo fanout... 142 | Repair tie hi fanout... 143 | ``` 144 |
145 | 146 |
147 |

Detailed Placement

 148 | 149 | 1. Optimize and legaliize placement 150 | ``` 151 | Detailed placement improvement. 152 | Importing netlist into detailed improver. 153 | [INFO DPO-0100] Creating network with 470 cells, 54 terminals, 471 edges and 1293 pins. 154 | [INFO DPO-0109] Network stats: inst 524, edges 471, pins 1293 155 | [INFO DPO-0110] Number of regions is 1 156 | [INFO DPO-0401] Setting random seed to 1. 157 | # ... 158 | Detailed Improvement Results 159 | ------------------------------------------ 160 | Original HPWL 2915.0 u 161 | Final HPWL 2703.4 u 162 | Delta HPWL -7.3 % 163 | 164 | 2. Cell mirroring 165 | ``` 166 | INFO DPL-0020] Mirrored 20 instances 167 | [INFO DPL-0021] HPWL before 2703.4 u 168 | [INFO DPL-0022] HPWL after 2700.8 u 169 | [INFO DPL-0023] HPWL delta -0.1 % 170 | ``` 171 | See this step in the GUI: 172 | ``` 173 | $ make gui_place 174 | ``` 175 |
176 | 177 |
178 |

Clock Tree Synthesis

 179 | 180 | Run `make cts` and examine the output: 181 | 182 | 1. Buffer characterization 183 | ``` 184 | [INFO CTS-0049] Characterization buffer is: BUF_X4. 185 | [INFO CTS-0039] Number of created patterns = 11880. 186 | [INFO CTS-0084] Compiling LUT. 187 | Min. len Max. len Min. cap Max. cap Min. slew Max. slew 188 | 2 8 1 34 1 14 189 | ``` 190 | 2. Generate clock tree 191 | ``` 192 | [INFO CTS-0007] Net "clk" found for clock "core_clock". 193 | [INFO CTS-0010] Clock net "clk" has 35 sinks. 194 | [INFO CTS-0008] TritonCTS found 1 clock nets. 195 | [INFO CTS-0097] Characterization used 1 buffer(s) types. 196 | [INFO CTS-0027] Generating H-Tree topology for net clk. 197 | [INFO CTS-0028] Total number of sinks: 35. 198 | ``` 199 | 3. Resize / repair clock tree 200 | ``` 201 | [INFO RSZ-0058] Using max wire length 661um. 202 | ``` 203 | 4. Legalize buffers 204 | ``` 205 | Placement Analysis 206 | --------------------------------- 207 | total displacement 12.1 u 208 | average displacement 0.0 u 209 | max displacement 2.2 u 210 | original HPWL 2814.9 u 211 | legalized HPWL 2884.6 u 212 | delta HPWL 2 % 213 | ``` 214 | 5. Repair timing 215 | ``` 216 | Repair setup and hold violations... 217 | [INFO RSZ-0040] Inserted 3 buffers. 218 | [INFO RSZ-0041] Resized 29 instances. 219 | [WARNING RSZ-0062] Unable to repair all setup violations. 220 | [INFO RSZ-0033] No hold violations found. 221 | ``` 222 | 6. Legalize buffers again 223 | ``` 224 | Placement Analysis 225 | --------------------------------- 226 | total displacement 21.5 u 227 | average displacement 0.0 u 228 | max displacement 2.2 u 229 | original HPWL 2896.4 u 230 | legalized HPWL 2917.9 u 231 | delta HPWL 1 % 232 | ``` 233 | 7. Insert filler cells 234 | ``` 235 | [INFO DPL-0001] Placed 704 filler instances. 236 | ``` 237 | See this step in the GUI: 238 | ``` 239 | $ make gui_cts 240 | ``` 241 |
242 | 243 |
244 |

Global Routing

 245 | 246 | Run `make route` and examine the output: 247 | 248 | 1. Generate routing grid 249 | ``` 250 | [INFO GRT-0053] Routing resources analysis: 251 | Routing Original Derated Resource 252 | Layer Direction Resources Resources Reduction (%) 253 | --------------------------------------------------------------- 254 | metal1 Horizontal 0 0 0.00% 255 | metal2 Vertical 11979 2464 79.43% 256 | metal3 Horizontal 16335 4704 71.20% 257 | metal4 Vertical 7623 5394 29.24% 258 | metal5 Horizontal 7623 5408 29.06% 259 | metal6 Vertical 7623 5440 28.64% 260 | metal7 Horizontal 2178 1120 48.58% 261 | metal8 Vertical 2178 1120 48.58% 262 | metal9 Horizontal 1089 32 97.06% 263 | metal10 Vertical 1089 32 97.06% 264 | --------------------------------------------------------------- 265 | ``` 266 | 2. Perform global routing 267 | ``` 268 | [INFO GRT-0096] Final congestion report: 269 | Layer Resource Demand Usage (%) Max H / Max V / Total Overflow 270 | --------------------------------------------------------------------------------------- 271 | metal1 0 0 0.00% 0 / 0 / 0 272 | metal2 2464 489 19.85% 0 / 0 / 0 273 | metal3 4704 677 14.39% 0 / 0 / 0 274 | metal4 5394 317 5.88% 0 / 0 / 0 275 | metal5 5408 87 1.61% 0 / 0 / 0 276 | metal6 5440 4 0.07% 0 / 0 / 0 277 | metal7 1120 0 0.00% 0 / 0 / 0 278 | metal8 1120 0 0.00% 0 / 0 / 0 279 | metal9 32 0 0.00% 0 / 0 / 0 280 | metal10 32 0 0.00% 0 / 0 / 0 281 | --------------------------------------------------------------------------------------- 282 | Total 25714 1574 6.12% 0 / 0 / 0 283 | ``` 284 | 3. Check for antenna violations 285 | ``` 286 | [INFO ANT-0002] Found 0 net violations. 287 | [INFO ANT-0001] Found 0 pin violations. 288 | ``` 289 |
290 | 291 |
292 |

Detailed Routing

 293 | 294 | 1. Region query 295 | ``` 296 | [INFO DRT-0168] Init region query. 297 | [INFO DRT-0024] Complete active. 298 | [INFO DRT-0024] Complete Fr_VIA. 299 | [INFO DRT-0024] Complete metal1. 300 | [INFO DRT-0024] Complete via1. 301 | # ... 302 | ``` 303 | 2. Pin access 304 | ``` 305 | [INFO DRT-0165] Start pin access. 306 | [INFO DRT-0076] Complete 100 pins. 307 | [INFO DRT-0078] Complete 176 pins. 308 | [INFO DRT-0081] Complete 53 unique inst patterns. 309 | [INFO DRT-0084] Complete 251 groups. 310 | ``` 311 | 3. Post-process guides 312 | ``` 313 | [INFO DRT-0169] Post process guides. 314 | [INFO DRT-0176] GCELLGRID X 0 DO 33 STEP 4200 ; 315 | [INFO DRT-0177] GCELLGRID Y 0 DO 33 STEP 4200 ; 316 | [INFO DRT-0028] Complete active. 317 | [INFO DRT-0028] Complete Fr_VIA. 318 | [INFO DRT-0028] Complete metal1. 319 | [INFO DRT-0028] Complete via1. 320 | ``` 321 | 4. Track assignment 322 | ``` 323 | [INFO DRT-0181] Start track assignment. 324 | [INFO DRT-0184] Done with 906 vertical wires in 1 frboxes and 1498 horizontal wires in 1 frboxes. 325 | [INFO DRT-0186] Done with 181 vertical wires in 1 frboxes and 287 horizontal wires in 1 frboxes. 326 | [INFO DRT-0182] Complete track assignment. 327 | ``` 328 | 5. Detailed routing 329 | ``` 330 | [INFO DRT-0194] Start detail routing. 331 | [INFO DRT-0195] Start 0th optimization iteration. 332 | Completing 10% with 0 violations. 333 | elapsed time = 00:00:00, memory = 96.41 (MB). 334 | Completing 20% with 0 violations. 335 | elapsed time = 00:00:00, memory = 96.70 (MB). 336 | Completing 30% with 0 violations. 337 | # ... 338 | Completing 100% with 10 violations. 339 | elapsed time = 00:00:01, memory = 129.02 (MB). 340 | [INFO DRT-0199] Number of violations = 88. 341 | Viol/Layer metal1 metal2 metal3 via3 metal4 metal5 342 | Cut Spacing 0 0 0 2 0 0 343 | Metal Spacing 1 1 0 0 0 0 344 | NS Metal 0 0 1 0 0 0 345 | Recheck 0 32 31 0 12 3 346 | Short 0 4 0 0 1 0 347 | # ... 348 | [INFO DRT-0199] Number of violations = 0. 349 | # ... 350 | [INFO DRT-0198] Complete detail routing. 351 | Total wire length = 3573 um. 352 | ``` 353 | See this step in the GUI: 354 | ``` 355 | $ make gui_route 356 | ``` 357 |
358 | 359 |
360 |

Parasitic Extraction

 361 | 362 | Run `make finish` and examine the output: 363 | 364 | Extract parasitic capacitances and resistances 365 | ``` 366 | [INFO RCX-0008] extracting parasitics of gcd ... 367 | [INFO RCX-0435] Reading extraction model file ./platforms/nangate45/rcx_patterns.rules ... 368 | [INFO RCX-0436] RC segment generation gcd (max_merge_res 50.0) ... 369 | [INFO RCX-0040] Final 1266 rc segments 370 | [INFO RCX-0439] Coupling Cap extraction gcd ... 371 | # ... 372 | [INFO RCX-0017] Finished writing SPEF ... 373 | ``` 374 |
375 | 376 |
377 |

Timing Signoff

 378 | 379 | 1. Report final timing 380 | ``` 381 | ========================================================================== 382 | finish report_tns 383 | -------------------------------------------------------------------------- 384 | tns -1.57 385 | 386 | ========================================================================== 387 | finish report_wns 388 | -------------------------------------------------------------------------- 389 | wns -0.08 390 | 391 | ========================================================================== 392 | finish report_worst_slack 393 | -------------------------------------------------------------------------- 394 | worst slack -0.08 395 | 396 | ========================================================================== 397 | finish report_clock_skew 398 | -------------------------------------------------------------------------- 399 | Clock core_clock 400 | Latency CRPR Skew 401 | _699_/CK ^ 402 | 0.05 403 | _679_/CK ^ 404 | 0.05 0.00 0.00 405 | ``` 406 | 2. Report final electrical violations 407 | ``` 408 | finish max_slew_violation_count 409 | -------------------------------------------------------------------------- 410 | max slew violation count 0 411 | 412 | ========================================================================== 413 | finish max_fanout_violation_count 414 | -------------------------------------------------------------------------- 415 | max fanout violation count 0 416 | 417 | ========================================================================== 418 | finish max_cap_violation_count 419 | -------------------------------------------------------------------------- 420 | max cap violation count 0 421 | 422 | ========================================================================== 423 | finish setup_violation_count 424 | -------------------------------------------------------------------------- 425 | setup violation count 0 426 | 427 | ========================================================================== 428 | finish hold_violation_count 429 | -------------------------------------------------------------------------- 430 | hold violation count 1 431 | ``` 432 | See this step in the GUI: 433 | ``` 434 | $ make gui_finish 435 | ``` 436 |
437 | 438 |
439 |

GDS Export

 440 | 441 | Export DEF file to GDS file 442 | ``` 443 | [INFO] Reading DEF ... 444 | [INFO] Clearing cells... 445 | [INFO] Merging GDS/OAS files... 446 | ./platforms/nangate45/gds/NangateOpenCellLibrary.gds 447 | [INFO] Copying toplevel cell 'gcd' 448 | WARNING: no fill config file specified 449 | [INFO] Checking for missing cell from GDS/OAS... 450 | [INFO] Found GDS_ALLOW_EMPTY variable. 451 | [INFO] All LEF cells have matching GDS/OAS cells 452 | [INFO] Checking for orphan cell in the final layout... 453 | [INFO] No orphan cells 454 | [INFO] Writing out GDS/OAS 'results/nangate45/gcd/base/6_1_merged.gds' 455 | ``` 456 | 457 | See this step in the GUI: 458 | ``` 459 | $ make klayout_6_final.gds 460 | ``` 461 |
462 | 463 | ## Exercise 1: Debugging a Design #1 464 | Find the problem with the provided design. 465 | 466 | [`../../exercise1/config.mk`](exercise1/config.mk) provides a faulty design 467 | config for the design `dynamic_node`, which is a mesh router node. Find the 468 | error by running: 469 | ``` 470 | $ make DESIGN_CONFIG=../../exercise1/config.mk 471 | ``` 472 | 473 | Once the error is spotted, open `../../exercise1/config.mk` in a text editor and 474 | fix the problematic line(s). You can test your solution by cleaning and 475 | rerunning the design: 476 | ``` 477 | # Save time by only cleaning the floorplan step to avoid rerunning synthesis 478 | make DESIGN_CONFIG=../../exercise1/config.mk clean_floorplan 479 | make DESIGN_CONFIG=../../exercise1/config.mk 480 | ``` 481 | 482 | Compare your solution to the reference solution at 483 | [`../../exercise1/solution/config.mk`](exercise1/solution/config.mk). 484 | 485 | ## Exercise 2: Debugging a Design #2 486 | Find the problem with the provided design. 487 | 488 | [`../../exercise2/config.mk`](exercise2/config.mk) provides a faulty design config. 489 | Find the error by running: 490 | ``` 491 | make DESIGN_CONFIG=../../exercise2/config.mk 492 | ``` 493 | 494 | Once the error is spotted, open `../../exercise2/config.mk` in a text editor and fix 495 | the problematic line. You can test your solution by cleaning and rerunning the design: 496 | ``` 497 | # Save time by only cleaning the floorplan step to avoid rerunning synthesis 498 | make DESIGN_CONFIG=../../exercise2/config.mk clean_floorplan 499 | make DESIGN_CONFIG=../../exercise2/config.mk 500 | ``` 501 | 502 | Compare your solution to the reference solution at 503 | [`../../exercise2/solution/config.mk`](exercise2/solution/config.mk). 504 | 505 | 506 | 507 | ## Demo 2: Analyzing Your Design Using OpenROAD 508 | Follow along as the presenter demonstrates how to observe design metrics. 509 | 510 | This demo will look at the metrics reported for `nangate45/gcd`. If you haven't already, run the 511 | design by running `make`. 512 | 513 | Once complete, observe the final report by navigating to `logs/nangate45/gcd/base/6_report.json` 514 | for a simple JSON-based report or `logs/nangate45/gcd/base/6_report.log` for a textual report. 515 | 516 | ### Modeling Power 517 | To observe the modeled power, look at `finish__power__total` or `finish report_power`. Note that 518 | OpenROAD models power using default activity factors on inputs and propagates these activity factors 519 | through the design. This method provides a solid first-order approximation of power and is useful 520 | for design space exploration. You can increase the accuracy of the model by applying accurate 521 | activity factors on the inputs (see OpenSTA documentation). Static activity-based power modeling 522 | (SAIF) and vector-based (VPD) power modeling are even more accurate methods, however they are not 523 | currently supported in OpenROAD. 524 | 525 | OpenROAD power report: 526 | ``` 527 | ========================================================================== 528 | finish report_power 529 | -------------------------------------------------------------------------- 530 | Group Internal Switching Leakage Total 531 | Power Power Power Power (Watts) 532 | ---------------------------------------------------------------- 533 | Sequential 4.49e-04 6.01e-05 3.13e-06 5.12e-04 38.6% 534 | Combinational 4.08e-04 3.96e-04 9.84e-06 8.14e-04 61.4% 535 | Macro 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0% 536 | Pad 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0% 537 | ---------------------------------------------------------------- 538 | Total 8.57e-04 4.56e-04 1.30e-05 1.33e-03 100.0% 539 | 64.7% 34.4% 1.0% 540 | ``` 541 | Total power is the most important metric, however you can read more about the other components 542 | [here](https://blogs.cuit.columbia.edu/zp2130/modeling_power_terminology). The power report is 543 | broken down by group, where `Sequential` represents flip-flops, `Combinational` represents logic 544 | gates, `Macro` represents macros such as SRAM, and `Pad` represents I/O cells (if any). 545 | 546 | ### Calculating Max Frequency 547 | To determine maximum frequency, look at `finish__timing__setup__ws` or `finish report_worst_slack` 548 | value. "Slack" is the difference between the constraint (0.46ns) and the actual signal propagation time. 549 | Positive slack means the constraint is met ("there is extra slack"). Negative slack means the 550 | constraint is violated. 551 | 552 | ``` 553 | ========================================================================== 554 | finish report_worst_slack 555 | -------------------------------------------------------------------------- 556 | worst slack -0.08 557 | ``` 558 | 559 | Using the slack, the frequency is calculated as: 560 | $$\mathrm{Frequency_max} = \frac{1}{\mathrm{constraint} - \mathrm{slack}}$$ 561 | Be mindful of the sign and units of the slack. Greater slack should mean greater frequency. 562 | Be sure that you also calculate frequency using *setup* slack not *hold* slack. 563 | 564 | In this case, the max frequency is: 565 | $$\mathrm{Frequency_max} = \frac{1}{\mathrm{constraint} - \mathrm{slack}} = \frac{1}{0.46\mathrm{ns} - (-0.08\mathrm{ns})} \approx 1.85 \mathrm{GHz} $$ 566 | 567 | ### Measuring Area 568 | To measure the design area, you must be aware of the different types of reported area. 569 | 1. Synthesized area 570 | 2. Place-and-route area 571 | 3. Core area / die area 572 | 573 | #### Synthesized Area 574 | Synthesized area is obtained after synthesis and is a good first-order model for design space exploration. 575 | You can find the design area in `logs/nangate45/gcd/base/synth_stat.txt`. Units are $\mathrm{\mu m}^2$. 576 | 577 | ``` 578 | Chip area for module '\gcd': 519.764000 579 | ``` 580 | 581 | #### Place-and-Route Area 582 | Place-and-route area is the area obtained after cell placement and routing. If reporting this number, it 583 | is implied that the design does not have any violations which make the chip unmanufacturable (e.g. 584 | routing or hold time violations). You can find the area from `finish__design__instance__area` or 585 | `finish report_design_area`. 586 | 587 | ``` 588 | ========================================================================== 589 | finish report_design_area 590 | -------------------------------------------------------------------------- 591 | Design area 581 u^2 24% utilization. 592 | ``` 593 | 594 | #### Core Area / Die Area 595 | Core / Die areas are the most accurate numbers, as they specify the exact area of silicon that will be 596 | used for fabrication. However, these numbers are not often reported for computer architecture works. 597 | Core area is the area of silicon which cells can occupy. It can effectively be calculated as: 598 | $$\mathrm{Area_{core}} = \frac{\mathrm{Area_design}}{\mathrm{utilization}}$$ 599 | 600 | Die area includes all silicon area needed to fabricate the chip, including any I/O and untilized space. 601 | 602 | In the case of `nangate45/gcd`, the easiest location to find this information is from the design config, 603 | which specifies the die area as a set of $(x_1, y_1, x_2, y_2)$ coordinates: 604 | 605 | [`flow/designs/nangate45/gcd/config.mk`](https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/blob/96a7fc08e8404bec49f9a874589a5d95638707ee/flow/designs/nangate45/gcd/config.mk): 606 | ``` 607 | export DIE_AREA = 0 0 70.11 70 608 | export CORE_AREA = 10.07 11.2 60.04 60.2 609 | ``` 610 | yielding a die area of: 611 | $$\mathrm{Area_{die}} = (70.11 \mathrm{\mu m} - 0 \mathrm{\mu m})\times(70 \mathrm{\mu m} - 0 \mathrm{\mu m}) = 4907.7 \mathrm{\mu m}^2$$ 612 | 613 | and core area of: 614 | $$\mathrm{Area_{core}} = (60.04 \mathrm{\mu m} - 10.07 \mathrm{\mu m})\times(60.2 \mathrm{\mu m} - 11.2 \mathrm{\mu m}) = 2448.53 \mathrm{\mu m}^2$$ 615 | 616 | which can also be obtained from the previous formula: 617 | $$\mathrm{Area_{core}} = \frac{\mathrm{Area_design}}{\mathrm{utilization}} = \frac{581 \mathrm{\mu m}^2}{0.24} \approx 2420.83 \mathrm{\mu m}^2$$ 618 | 619 | ## Exercise 3: Creating a Pareto Curve 620 | Adjust the constraints on a design to observe the impact on power, performance, and area (PPA). 621 | 622 | `../../exercise3/` provides a simple integer arithmetic logic unit (ALU). The default bitwidth is 12 623 | and the default clock constraint is 7ns (~143 MHz). These parameters allow for RTL-to-GDS in 624 | under 1 minute. Run the design with: 625 | ``` 626 | make DESIGN_CONFIG=../../exercise3/config.mk 627 | ``` 628 | 629 | Once complete, observe the final report at `logs/nangate45/alu/base/6_report.json` or 630 | `logs/nangate45/alu/base/6_report.log`. 631 | 632 | Record the power, frequency, and area. Then, open the constraint file 633 | ([`../../exercise3/constraint.sdc`](exercise3/constraint.sdc)) with your 634 | favorite editor and adjust the clock period to 6ns. 635 | 636 | Clean the design and rerun using the new constraint: 637 | ``` 638 | make DESIGN_CONFIG=../../exercise3/config.mk clean_all 639 | make DESIGN_CONFIG=../../exercise3/config.mk 640 | ``` 641 | 642 | Record the power, frequency, and area, then repeat for 5ns, 4ns, and 3ns. 643 | 644 | Once complete, you can plot this data using your favorite software (Google 645 | Sheets, Microsoft Excel, matplotlib, etc.). Use max frequency as the independent 646 | variable. Confirm that your data matches the reference data at 647 | [`../../exercise3/solution/data.csv`](exercise3/solution/data.csv) 648 | 649 | ## Exercise 4: Scaling a Design Across Technologies 650 | Observe the differences when a design is implemented in different technologies. 651 | 652 | OpenROAD-flow-scripts provides 3 open-source PDKs to implement designs in: 653 | SkyWater 130nm, Nangate 45nm, and ASAP 7nm. RTL is easily portable across 654 | technologies if it does not contain technology-specific cells (such as I/O pads, 655 | SRAM, clock-gate cells, etc.). 656 | 657 | The `../../exercise4/` directory contains the same ALU design from Exercise 3. 658 | However, this time you will change the config to alter the target technology. 659 | Adjust the `PLATFORM` variable in [`../../exercise4/config.mk`](exercise4/config.mk) 660 | to to one of the technologies (`sky130hd`, `nangate45`, `asap7`). Keep in mind 661 | that: 662 | 663 | * You may need to clean the design data from Exercise 3, because the platform and 664 | design name (`nangate45/alu`) are reused: 665 | ``` 666 | make DESIGN_CONFIG=../exercise3/config.mk clean_all 667 | ``` 668 | * The time units for `sky130hd` and `nangate45` are both in ns, but the units 669 | for `asap7` are in ps. In order to maintain parity, you will need to adjust 670 | [`../../exercise4/constraint.sdc`](exercise4/constraint.sdc). 671 | 672 | Then, run the design using: 673 | 674 | ``` 675 | make DESIGN_CONFIG=../exercise4/config.mk 676 | ``` 677 | 678 | Record the power, frequency, and area for each technology. You need not clean 679 | the design between runs because changing the platform changes the output 680 | directory. You can again graph the data using your favorite graphing software 681 | and compare the data to the reference data at 682 | [`../../exercise4/solution/data.csv`](exercise4/solution/data.csv). 683 | 684 | ## Demo 3: Building Complex Designs 685 | Follow along as the presenter explains how to incorporate macros into your design. 686 | 687 | For designs to scale to larger sizes, additional layers of abstraction are required. **Macros** 688 | are special cells which are not logic gates and aren't automatically generated from synthesis. 689 | Macros are often much larger than standard cells and therefore require special handling. Macros 690 | are often used for several reasons: 691 | 692 | 1. Using SRAM or register files for large memories 693 | 2. Encapsulating a module which is instantiated multiple times 694 | 3. I/O pad cells for off-chip power and communication 695 | 4. Fiducial cells required by the manufacturer for fabrication 696 | 5. Intellectual property (IP) provided by a third-party vendor 697 | 6. And more! 698 | 699 | ### How can I generate macros? 700 | * [OpenRAM](https://github.com/VLSIDA/OpenRAM) is an open-source SRAM generator 701 | * Requires bitcells and sense amplifiers; creates implementations suitable for fabrication 702 | * [bsg_fakeram](https://github.com/bespoke-silicon-group/bsg_fakeram) is a blackbox SRAM generator 703 | * Creates a blackbox implementation which is useful for modeling; cannot be used for fabrication 704 | * Generate a block using OpenROAD 705 | * Use OpenROAD to create a hardened macro, then instantiate the block in a parent module 706 | * Acquire third-party IP 707 | * Many commerical vendors provide RAM generators, I/O pad cells, analog macros, and more 708 | 709 | `nangate45/tinyRocket` is a CPU core which incorporates SRAM macros generated by bsg_fakeram. 710 | While OpenROAD-flow-scipts already includes platform files necessary for standard cells, designers 711 | must specify macro files in the design config. 712 | 713 | [`flow/designs/nangate45/tinyRocket/config.mk`](https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/blob/96a7fc08e8404bec49f9a874589a5d95638707ee/flow/designs/nangate45/tinyRocket/config.mk): 714 | ``` 715 | export ADDITIONAL_LEFS = $(sort $(wildcard ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/*.lef)) 716 | export ADDITIONAL_LIBS = $(sort $(wildcard ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/*.lib)) 717 | ``` 718 | The config file uses the variable `ADDITIONAL_LEFS` and `ADDITIONAL_LIBS` to reference the abstract 719 | physical views (`.lef`) and timing models (`.lib`) for the macros. The wildcard commands above are 720 | shorthand for: 721 | ``` 722 | export ADDITIONAL_LEFS = ./designs/nangate45/tinyRocket/fakeram45_1024x32.lef ./designs/nangate45/tinyRocket/fakeram45_64x32.lef 723 | export ADDITIONAL_LIBS = ./designs/nangate45/tinyRocket/fakeram45_1024x32.lib ./designs/nangate45/tinyRocket/fakeram45_64x32.lib 724 | ``` 725 | Notice however that these RAMs are generated by bsg_fakeram and do not have physical implementation 726 | files (`.gds`). Normally, this would create an error during the GDS merge step, however the [platform 727 | configuration for nangate45](https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/blob/96a7fc08e8404bec49f9a874589a5d95638707ee/flow/platforms/nangate45/config.mk#L101) 728 | downgrades this to a warning by setting `GDS_ALLOW_EMPTY` on these instances: 729 | ``` 730 | # Allow empty GDS cell 731 | export GDS_ALLOW_EMPTY = fakeram.* 732 | ``` 733 | If the macro does have a physical implementation (`.gds`), it can be added to the design config with: 734 | ``` 735 | export ADDITIONAL_GDS = /path/to/macro1.gds /path/to/macro2.gds ... 736 | ``` 737 | 738 | Now, build tinyRocket with: 739 | ``` 740 | # Build takes several minutes 741 | make DESIGN_CONFIG=./designs/nangate45/tinyRocket/config.mk 742 | ``` 743 | 744 | Once done, you can see that new steps in the flow were used: 745 | 1. `2_3_tdms_place.log`: timing-driven mixed-size place 746 | 2. `2_4_mplace.log`: macro place 747 | 748 | `tdms_place` performs a rough initial placement of both macros and standard cells. This is used as a 749 | seed for the macro placer. `mplace` performs macro placement. The placer tries to ensure that 750 | macros block as little design area as possible while still allowing connectivity to the macro. 751 | 752 | Common problems when introducing macros: 753 | * "Channels" between macros need to be wide enough to not overcongest the router 754 | * Slight changes to the design area can cause large changes in the macro placements 755 | * Macros can block regions of the core area and make standard cell placement difficult 756 | * Malformed macros can cause difficult-to-diagnose design problems 757 | 758 | ## Exercise 5: Setting Up a New Design with OpenROAD-flow-Scripts 759 | If you have your own RTL, now's the time to use it! 760 | 761 | The directory `../../exercise5/` contains a blank [`config.mk`](exercise5/config.mk) 762 | template and blank [`constraint.sdc`](exercise5/constraint.sdc) template. 763 | 764 | * If you have Verilog RTL file(s), place it (them) in `../../exercise5/`. 765 | * If you don't have your own RTL, you can use the provided `counter.v` file instead. 766 | 767 | Feel free to use other designs as a reference! Use any platform you want. 768 | 769 | ## Demo 4: Using OpenLane for the Free Skywater 130nm Open MPW Shuttle 770 | Follow along as the presenter explains [OpenLane](https://github.com/The-OpenROAD-Project/OpenLane), 771 | the [Efabless OpenMPW Program](https://efabless.com/open_shuttle_program), and a [design which was 772 | just submitted](https://platform.efabless.com/projects/1165). 773 | -------------------------------------------------------------------------------- /applyPatch.sh: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env bash 2 | patch OpenROAD-flow-scripts/flow/scripts/report_metrics.tcl patchfile.patch 3 | -------------------------------------------------------------------------------- /exercise1/config.mk: -------------------------------------------------------------------------------- 1 | export DESIGN_NICKNAME = dynamic_node 2 | export DESIGN_NAME = dynamic_node_top_wrap 3 | export PLATFORM = nangate45 4 | 5 | export VERILOG_FILES = ./designs/src/$(DESIGN_NICKNAME)/dynamic_node.pickle.v 6 | export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc 7 | 8 | # One or more of the below lines are causing a problem! 9 | export CORE_UTILIZATION = 99 10 | export PLACE_DENSITY = 0.99 11 | export CORE_ASPECT_RATIO = 1 12 | export CORE_MARGIN = 5 13 | 14 | -------------------------------------------------------------------------------- /exercise1/solution/config.mk: -------------------------------------------------------------------------------- 1 | export DESIGN_NICKNAME = dynamic_node 2 | export DESIGN_NAME = dynamic_node_top_wrap 3 | export PLATFORM = nangate45 4 | 5 | export VERILOG_FILES = ./designs/src/$(DESIGN_NICKNAME)/dynamic_node.pickle.v 6 | export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc 7 | 8 | # The utilization and place density were too high. After buffering for timing, 9 | # the utilization was over 100%. This causes detailed placement failures. 10 | # Adjusting the utilization / place density lower (but not low enough) causes 11 | # other problems, such as global routing failure (design is too congested) 12 | # A value of 60% resolves the issues. 13 | export CORE_UTILIZATION = 60 14 | export PLACE_DENSITY = 0.60 15 | export CORE_ASPECT_RATIO = 1 16 | export CORE_MARGIN = 5 17 | 18 | -------------------------------------------------------------------------------- /exercise2/alu.v: -------------------------------------------------------------------------------- 1 | module alu #( 2 | parameter WIDTH = 12 3 | )( 4 | input wire clk, // Clock 5 | input wire rst, // Active-high reset 6 | input wire [WIDTH-1:0] a, b, // ALU operands 7 | input wire [ 3:0] sel, // ALU function select 8 | output reg [WIDTH-1:0] out // ALU output 9 | ); 10 | 11 | // Define functions 12 | localparam ADD = 4'h0; // Addition 13 | localparam SUB = 4'h1; // Subtraction 14 | localparam MULT = 4'h2; // Multiplication 15 | localparam DIV = 4'h3; // Division 16 | localparam LSL = 4'h4; // Logical shift left 17 | localparam LSR = 4'h5; // Logical shift right 18 | localparam RL = 4'h6; // Rotate left 19 | localparam RR = 4'h7; // Rotate right 20 | localparam AND = 4'h8; // Bitwise AND 21 | localparam OR = 4'h9; // Bitwise OR 22 | localparam XOR = 4'ha; // Bitwise XOR 23 | localparam NOR = 4'hb; // Bitwise NOR 24 | localparam NAND = 4'hc; // Bitwise NAND 25 | localparam XNOR = 4'hd; // Bitwise XNOR 26 | localparam GT = 4'he; // Signed greater than 27 | localparam EQ = 4'hf; // Equal 28 | 29 | always @(posedge clk) begin 30 | if(rst) begin 31 | out <= WIDTH'b0; 32 | end else begin 33 | case(sel) 34 | ADD : out <= a + b; 35 | SUB : out <= a - b; 36 | MULT: out <= a * b; 37 | DIV : out <= a / b; 38 | LSL : out <= a << 1; 39 | LSR : out <= a >> 1; 40 | RL : out <= {a[WIDTH-2:0],a[WIDTH-1]}; 41 | RR : out <= {a[0],a[WIDTH-1:1]}; 42 | AND : out <= a & b; 43 | OR : out <= a | b; 44 | XOR : out <= a ^ b; 45 | NOR : out <= ~(a | b); 46 | NAND: out <= ~(a & b); 47 | XNOR: out <= ~(a ^ b); 48 | GT : out <= $signed(a) > $signed(b); 49 | EQ : out <= a == b; 50 | endcase 51 | end 52 | end 53 | 54 | endmodule 55 | -------------------------------------------------------------------------------- /exercise2/config.mk: -------------------------------------------------------------------------------- 1 | export DESIGN_NAME = alu 2 | export PLATFORM = nangate45 3 | 4 | export VERILOG_FILES = ../../exercise2/$(DESIGN_NAME).v 5 | export SDC_FILE = ../../exercise2/constraint.sdc 6 | export ABC_AREA = 1 7 | 8 | # One or more of the below lines are causing a problem! 9 | export CORE_UTILIZATION = 55 10 | export PLACE_DENSITY = 0.50 11 | export CORE_ASPECT_RATIO = 1 12 | export CORE_MARGIN = 1.0 13 | -------------------------------------------------------------------------------- /exercise2/constraint.sdc: -------------------------------------------------------------------------------- 1 | set clk_period 7 2 | 3 | # Don't change below here 4 | current_design alu 5 | set clk_name core_clock 6 | set clk_port_name clk 7 | set clk_io_pct 0.2 8 | 9 | set clk_port [get_ports $clk_port_name] 10 | 11 | create_clock -name $clk_name -period $clk_period $clk_port 12 | 13 | set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] 14 | 15 | set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs 16 | set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] 17 | -------------------------------------------------------------------------------- /exercise2/solution/config.mk: -------------------------------------------------------------------------------- 1 | export DESIGN_NAME = alu 2 | export PLATFORM = nangate45 3 | 4 | export VERILOG_FILES = ../../exercise2/$(DESIGN_NAME).v 5 | export SDC_FILE = ../../exercise2/constraint.sdc 6 | export ABC_AREA = 1 7 | 8 | # Core utilization cannot be higher than placement density 9 | export CORE_UTILIZATION = 55 10 | export PLACE_DENSITY = 0.60 11 | export CORE_ASPECT_RATIO = 1 12 | export CORE_MARGIN = 1.0 13 | -------------------------------------------------------------------------------- /exercise3/alu.v: -------------------------------------------------------------------------------- 1 | module alu #( 2 | parameter WIDTH = 12 3 | )( 4 | input wire clk, // Clock 5 | input wire rst, // Active-high reset 6 | input wire [WIDTH-1:0] a, b, // ALU operands 7 | input wire [ 3:0] sel, // ALU function select 8 | output reg [WIDTH-1:0] out // ALU output 9 | ); 10 | 11 | // Define functions 12 | localparam ADD = 4'h0; // Addition 13 | localparam SUB = 4'h1; // Subtraction 14 | localparam MULT = 4'h2; // Multiplication 15 | localparam DIV = 4'h3; // Division 16 | localparam LSL = 4'h4; // Logical shift left 17 | localparam LSR = 4'h5; // Logical shift right 18 | localparam RL = 4'h6; // Rotate left 19 | localparam RR = 4'h7; // Rotate right 20 | localparam AND = 4'h8; // Bitwise AND 21 | localparam OR = 4'h9; // Bitwise OR 22 | localparam XOR = 4'ha; // Bitwise XOR 23 | localparam NOR = 4'hb; // Bitwise NOR 24 | localparam NAND = 4'hc; // Bitwise NAND 25 | localparam XNOR = 4'hd; // Bitwise XNOR 26 | localparam GT = 4'he; // Signed greater than 27 | localparam EQ = 4'hf; // Equal 28 | 29 | always @(posedge clk) begin 30 | if(rst) begin 31 | out <= WIDTH'b0; 32 | end else begin 33 | case(sel) 34 | ADD : out <= a + b; 35 | SUB : out <= a - b; 36 | MULT: out <= a * b; 37 | DIV : out <= a / b; 38 | LSL : out <= a << 1; 39 | LSR : out <= a >> 1; 40 | RL : out <= {a[WIDTH-2:0],a[WIDTH-1]}; 41 | RR : out <= {a[0],a[WIDTH-1:1]}; 42 | AND : out <= a & b; 43 | OR : out <= a | b; 44 | XOR : out <= a ^ b; 45 | NOR : out <= ~(a | b); 46 | NAND: out <= ~(a & b); 47 | XNOR: out <= ~(a ^ b); 48 | GT : out <= $signed(a) > $signed(b); 49 | EQ : out <= a == b; 50 | endcase 51 | end 52 | end 53 | 54 | endmodule 55 | -------------------------------------------------------------------------------- /exercise3/config.mk: -------------------------------------------------------------------------------- 1 | export DESIGN_NAME = alu 2 | export PLATFORM = nangate45 3 | 4 | export VERILOG_FILES = ../../exercise3/$(DESIGN_NAME).v 5 | export SDC_FILE = ../../exercise3/constraint.sdc 6 | export ABC_AREA = 1 7 | 8 | export CORE_UTILIZATION = 45 9 | export PLACE_DENSITY = 0.50 10 | export CORE_ASPECT_RATIO = 1 11 | export CORE_MARGIN = 1.0 12 | -------------------------------------------------------------------------------- /exercise3/constraint.sdc: -------------------------------------------------------------------------------- 1 | # Try setting clock period to 7, 6, 5, 4, 3 2 | set clk_period 7 3 | 4 | # Don't change below here 5 | current_design alu 6 | set clk_name core_clock 7 | set clk_port_name clk 8 | set clk_io_pct 0.2 9 | 10 | set clk_port [get_ports $clk_port_name] 11 | 12 | create_clock -name $clk_name -period $clk_period $clk_port 13 | 14 | set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] 15 | 16 | set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs 17 | set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] 18 | -------------------------------------------------------------------------------- /exercise3/solution/data.csv: -------------------------------------------------------------------------------- 1 | clock period (ns),max frequency (MHz),area (um^2),total power (W) 2 | 7,185,2034,1.65e-04 3 | 6,191,2037,1.84e-04 4 | 5,202,2033,2.09e-04 5 | 4,229,2202,2.72e-04 6 | 3,240,2264,3.53e-04 7 | -------------------------------------------------------------------------------- /exercise4/alu.v: -------------------------------------------------------------------------------- 1 | module alu #( 2 | parameter WIDTH = 12 3 | )( 4 | input wire clk, // Clock 5 | input wire rst, // Active-high reset 6 | input wire [WIDTH-1:0] a, b, // ALU operands 7 | input wire [ 3:0] sel, // ALU function select 8 | output reg [WIDTH-1:0] out // ALU output 9 | ); 10 | 11 | // Define functions 12 | localparam ADD = 4'h0; // Addition 13 | localparam SUB = 4'h1; // Subtraction 14 | localparam MULT = 4'h2; // Multiplication 15 | localparam DIV = 4'h3; // Division 16 | localparam LSL = 4'h4; // Logical shift left 17 | localparam LSR = 4'h5; // Logical shift right 18 | localparam RL = 4'h6; // Rotate left 19 | localparam RR = 4'h7; // Rotate right 20 | localparam AND = 4'h8; // Bitwise AND 21 | localparam OR = 4'h9; // Bitwise OR 22 | localparam XOR = 4'ha; // Bitwise XOR 23 | localparam NOR = 4'hb; // Bitwise NOR 24 | localparam NAND = 4'hc; // Bitwise NAND 25 | localparam XNOR = 4'hd; // Bitwise XNOR 26 | localparam GT = 4'he; // Signed greater than 27 | localparam EQ = 4'hf; // Equal 28 | 29 | always @(posedge clk) begin 30 | if(rst) begin 31 | out <= WIDTH'b0; 32 | end else begin 33 | case(sel) 34 | ADD : out <= a + b; 35 | SUB : out <= a - b; 36 | MULT: out <= a * b; 37 | DIV : out <= a / b; 38 | LSL : out <= a << 1; 39 | LSR : out <= a >> 1; 40 | RL : out <= {a[WIDTH-2:0],a[WIDTH-1]}; 41 | RR : out <= {a[0],a[WIDTH-1:1]}; 42 | AND : out <= a & b; 43 | OR : out <= a | b; 44 | XOR : out <= a ^ b; 45 | NOR : out <= ~(a | b); 46 | NAND: out <= ~(a & b); 47 | XNOR: out <= ~(a ^ b); 48 | GT : out <= $signed(a) > $signed(b); 49 | EQ : out <= a == b; 50 | endcase 51 | end 52 | end 53 | 54 | endmodule 55 | -------------------------------------------------------------------------------- /exercise4/config.mk: -------------------------------------------------------------------------------- 1 | # Try setting platform to sky130hd, nangate45, asap7 2 | # Be aware that the time units for asap7 are in ps, not ns! 3 | # You may want to change your constraint.sdc 4 | export PLATFORM = 5 | 6 | export DESIGN_NAME = alu 7 | export VERILOG_FILES = ../../exercise4/alu.v 8 | export SDC_FILE = ../../exercise4/constraint.sdc 9 | 10 | export CORE_UTILIZATION = 35 11 | export PLACE_DENSITY = 0.60 12 | export CORE_ASPECT_RATIO = 1 13 | export CORE_MARGIN = 1.0 14 | -------------------------------------------------------------------------------- /exercise4/constraint.sdc: -------------------------------------------------------------------------------- 1 | # sky130hd and nangate45 are ns, but asap7 is ps 2 | set clk_period 7 3 | 4 | # Don't change below here 5 | current_design alu 6 | set clk_name core_clock 7 | set clk_port_name clk 8 | set clk_io_pct 0.2 9 | 10 | set clk_port [get_ports $clk_port_name] 11 | 12 | create_clock -name $clk_name -period $clk_period $clk_port 13 | 14 | set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] 15 | 16 | set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs 17 | set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] 18 | -------------------------------------------------------------------------------- /exercise4/solution/data.csv: -------------------------------------------------------------------------------- 1 | platform,clock period (ns),max frequency (MHz),area (um^2),total power (W) 2 | sky130hd,7,55,11811,1.06e-03 3 | nangate45,7,173,2122,1.83e-04 4 | asap7,7,278,156,4.51e-05 5 | -------------------------------------------------------------------------------- /exercise5/config.mk: -------------------------------------------------------------------------------- 1 | export DESIGN_NAME = 2 | export PLATFORM = 3 | 4 | export VERILOG_FILES = 5 | export SDC_FILE = 6 | 7 | export CORE_UTILIZATION = 8 | export PLACE_DENSITY = 9 | export CORE_ASPECT_RATIO = 10 | export CORE_MARGIN = 11 | -------------------------------------------------------------------------------- /exercise5/constraint.sdc: -------------------------------------------------------------------------------- 1 | current_design 2 | set clk_period 3 | set clk_port_name 4 | 5 | # No need to change below here 6 | set clk_name core_clock 7 | set clk_io_pct 0.2 8 | 9 | set clk_port [get_ports $clk_port_name] 10 | 11 | create_clock -name $clk_name -period $clk_period $clk_port 12 | 13 | set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] 14 | 15 | set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs 16 | set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] 17 | -------------------------------------------------------------------------------- /exercise5/counter.v: -------------------------------------------------------------------------------- 1 | module counter #( 2 | parameter WIDTH = 64 3 | )( 4 | input wire clk, 5 | input wire rst, 6 | output reg count 7 | ); 8 | 9 | always @(posedge clk) begin 10 | if(rst) begin 11 | count <= WIDTH'b0; 12 | end else begin 13 | count <= count + WIDTH'b1; 14 | end 15 | end 16 | 17 | endmodule 18 | -------------------------------------------------------------------------------- /exercise5/solution/config.mk: -------------------------------------------------------------------------------- 1 | export DESIGN_NAME = counter 2 | export PLATFORM = asap7 3 | 4 | export VERILOG_FILES = ../../exercise5/${DESIGN_NAME}.v 5 | export SDC_FILE = ../../exercise5/solution/constraint.sdc 6 | 7 | export CORE_UTILIZATION = 20 8 | export PLACE_DENSITY = 0.55 9 | export CORE_ASPECT_RATIO = 1 10 | export CORE_MARGIN = 1.0 11 | -------------------------------------------------------------------------------- /exercise5/solution/constraint.sdc: -------------------------------------------------------------------------------- 1 | current_design counter 2 | set clk_period 1000 3 | set clk_port_name clk 4 | 5 | # No need to change below here 6 | set clk_name core_clock 7 | set clk_io_pct 0.2 8 | 9 | set clk_port [get_ports $clk_port_name] 10 | 11 | create_clock -name $clk_name -period $clk_period $clk_port 12 | 13 | set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] 14 | 15 | set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs 16 | set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] 17 | -------------------------------------------------------------------------------- /patchfile.patch: -------------------------------------------------------------------------------- 1 | diff --git a/flow/scripts/report_metrics.tcl b/flow/scripts/report_metrics.tcl 2 | index b885d9f3..b051112f 100644 3 | --- a/flow/scripts/report_metrics.tcl 4 | +++ b/flow/scripts/report_metrics.tcl 5 | @@ -21,8 +21,8 @@ proc report_metrics { when {include_erc true} {include_clock_skew true} } { 6 | puts "$when report_clock_skew" 7 | puts "--------------------------------------------------------------------------" 8 | report_clock_skew 9 | - report_clock_skew_metric 10 | - report_clock_skew_metric -hold 11 | + #report_clock_skew_metric 12 | + #report_clock_skew_metric -hold 13 | } 14 | 15 | puts "\n==========================================================================" 16 | --------------------------------------------------------------------------------