├── ALU.v ├── ALU.v.bak ├── Control_E.v ├── Control_E.v.bak ├── EXT.v ├── EXT.v.bak ├── HazardUnit.v ├── HazardUnit.v.bak ├── PC.v ├── PC.v.bak ├── README.md ├── Reg.v ├── Reg.v.bak ├── RegP.v ├── RegP.v.bak ├── Verilog5.v.bak ├── Waveform.vwf ├── c5_pin_model_dump.txt ├── db ├── .cmp.kpt ├── prev_cmp_riscv_top.qmsg ├── riscv_top.(0).cnf.cdb ├── riscv_top.(0).cnf.hdb ├── riscv_top.(1).cnf.cdb ├── riscv_top.(1).cnf.hdb ├── riscv_top.(10).cnf.cdb ├── riscv_top.(10).cnf.hdb ├── riscv_top.(11).cnf.cdb ├── riscv_top.(11).cnf.hdb ├── riscv_top.(12).cnf.cdb ├── riscv_top.(12).cnf.hdb ├── riscv_top.(13).cnf.cdb ├── riscv_top.(13).cnf.hdb ├── riscv_top.(14).cnf.cdb ├── riscv_top.(14).cnf.hdb ├── riscv_top.(15).cnf.cdb ├── riscv_top.(15).cnf.hdb ├── riscv_top.(16).cnf.cdb ├── riscv_top.(16).cnf.hdb ├── riscv_top.(17).cnf.cdb ├── riscv_top.(17).cnf.hdb ├── riscv_top.(2).cnf.cdb ├── riscv_top.(2).cnf.hdb ├── riscv_top.(3).cnf.cdb ├── riscv_top.(3).cnf.hdb ├── riscv_top.(4).cnf.cdb ├── riscv_top.(4).cnf.hdb ├── riscv_top.(5).cnf.cdb ├── riscv_top.(5).cnf.hdb ├── riscv_top.(6).cnf.cdb ├── riscv_top.(6).cnf.hdb ├── riscv_top.(7).cnf.cdb ├── riscv_top.(7).cnf.hdb ├── riscv_top.(8).cnf.cdb ├── riscv_top.(8).cnf.hdb ├── riscv_top.(9).cnf.cdb ├── riscv_top.(9).cnf.hdb ├── riscv_top.asm.qmsg ├── riscv_top.asm.rdb ├── riscv_top.cbx.xml ├── riscv_top.cmp.idb ├── riscv_top.cmp.rdb ├── riscv_top.cmp_merge.kpt ├── riscv_top.cyclonev_io_sim_cache.ff_0c_fast.hsd ├── riscv_top.cyclonev_io_sim_cache.ss_85c_slow.hsd ├── riscv_top.db_info ├── riscv_top.drc.qmsg ├── riscv_top.eco.cdb ├── riscv_top.eda.qmsg ├── riscv_top.fit.qmsg ├── riscv_top.hier_info ├── riscv_top.hif ├── riscv_top.lpc.html ├── riscv_top.lpc.rdb ├── riscv_top.lpc.txt ├── riscv_top.map.ammdb ├── riscv_top.map.bpm ├── riscv_top.map.cdb ├── riscv_top.map.hdb ├── riscv_top.map.kpt ├── riscv_top.map.logdb ├── riscv_top.map.qmsg ├── riscv_top.map.rdb ├── riscv_top.map_bb.cdb ├── riscv_top.map_bb.hdb ├── riscv_top.map_bb.logdb ├── riscv_top.npp.qmsg ├── riscv_top.pplq.rdb ├── riscv_top.pre_map.hdb ├── riscv_top.ram0_rom_1d582.hdl.mif ├── riscv_top.root_partition.map.reg_db.cdb ├── riscv_top.routing.rdb ├── riscv_top.rtlv.hdb ├── riscv_top.rtlv_sg.cdb ├── riscv_top.rtlv_sg_swap.cdb ├── riscv_top.sgate.nvd ├── riscv_top.sgate_sm.nvd ├── riscv_top.sld_design_entry.sci ├── riscv_top.sld_design_entry_dsc.sci ├── riscv_top.smart_action.txt ├── riscv_top.tis_db_list.ddb ├── riscv_top.tiscmp.fastest_slow_1100mv_85c.ddb ├── riscv_top.tmw_info ├── riscv_top.vpr.ammdb └── riscv_top_partition_pins.json ├── defination.v ├── defination.v.bak ├── imemrom.txt ├── incremental_db ├── README └── compiled_partitions │ ├── riscv_top.db_info │ ├── riscv_top.root_partition.cmp.ammdb │ ├── riscv_top.root_partition.cmp.cdb │ ├── riscv_top.root_partition.cmp.dfp │ ├── riscv_top.root_partition.cmp.hbdb.cdb │ ├── riscv_top.root_partition.cmp.hbdb.hdb │ ├── riscv_top.root_partition.cmp.hbdb.sig │ ├── riscv_top.root_partition.cmp.hdb │ ├── riscv_top.root_partition.cmp.logdb │ ├── riscv_top.root_partition.cmp.rcfdb │ ├── riscv_top.root_partition.map.cdb │ ├── riscv_top.root_partition.map.dpi │ ├── riscv_top.root_partition.map.hbdb.cdb │ ├── riscv_top.root_partition.map.hbdb.hb_info │ ├── riscv_top.root_partition.map.hbdb.hdb │ ├── riscv_top.root_partition.map.hbdb.sig │ ├── riscv_top.root_partition.map.hdb │ ├── riscv_top.root_partition.map.kpt │ ├── riscv_top.rrp.hdb │ └── riscv_top.rrs.cdb ├── insmem.txt ├── memfile.txt ├── mux4.v ├── output_files ├── riscv_top.asm.rpt ├── riscv_top.done ├── riscv_top.drc.rpt ├── riscv_top.eda.rpt ├── riscv_top.fit.rpt ├── riscv_top.fit.smsg ├── riscv_top.fit.summary ├── riscv_top.flow.rpt ├── riscv_top.jdi ├── riscv_top.map.rpt ├── riscv_top.map.smsg ├── riscv_top.map.summary ├── riscv_top.pin ├── riscv_top.sld └── riscv_top.sof ├── ram.v ├── ram.v.bak ├── regfile.v ├── regfile.v.bak ├── riscv_top.qpf ├── riscv_top.qsf ├── riscv_top.qws ├── riscv_top.v ├── riscv_top.v.bak ├── riscv_top_nativelink_simulation.rpt ├── riscvtest.v ├── riscvtest.v.bak ├── rom.v ├── rom.v.bak └── simulation ├── modelsim ├── modelsim.ini ├── msim_transcript ├── riscv_top_run_msim_rtl_verilog.do ├── riscv_top_run_msim_rtl_verilog.do.bak ├── riscv_top_run_msim_rtl_verilog.do.bak1 ├── riscv_top_run_msim_rtl_verilog.do.bak10 ├── riscv_top_run_msim_rtl_verilog.do.bak11 ├── riscv_top_run_msim_rtl_verilog.do.bak2 ├── riscv_top_run_msim_rtl_verilog.do.bak3 ├── riscv_top_run_msim_rtl_verilog.do.bak4 ├── riscv_top_run_msim_rtl_verilog.do.bak5 ├── riscv_top_run_msim_rtl_verilog.do.bak6 ├── riscv_top_run_msim_rtl_verilog.do.bak7 ├── riscv_top_run_msim_rtl_verilog.do.bak8 ├── riscv_top_run_msim_rtl_verilog.do.bak9 ├── rtl_work │ ├── _info │ ├── _lib.qdb │ ├── _lib1_0.qdb │ ├── _lib1_0.qpg │ ├── _lib1_0.qtl │ └── _vmake ├── tbriscv.v ├── tbriscv.v.bak ├── vish_stacktrace.vstf ├── vsim.wlf ├── wlft02d5q4 ├── wlft1ibe54 ├── wlft2sb3i8 ├── wlft3ca0t9 ├── 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