├── .gitignore ├── README.md ├── doc ├── design.pdf ├── rate记录.xlsx └── 重庆大学.pptx ├── sim ├── basic_pipeline │ ├── mipstest.asm │ ├── mipstest.coe │ ├── testbench_behav.wcfg │ └── top_tb.v ├── pipelineMIPS.wcfg └── pipelineMIPS_sram.wcfg ├── src ├── PipelineMIPS-sram │ ├── EX │ │ ├── alu.v │ │ ├── branch_judge.v │ │ ├── div_radix2.v │ │ └── my_mul.v │ ├── ID │ │ ├── branch_predict.v │ │ ├── imm_ext.v │ │ ├── jump_predict.v │ │ └── regfile.v │ ├── IF │ │ ├── pc_ctrl.v │ │ └── pc_reg.v │ ├── MEM │ │ ├── cp0_reg.v │ │ ├── exception.v │ │ ├── hilo_reg.v │ │ └── mem_ctrl.v │ ├── PIPE │ │ ├── ex_mem.v │ │ ├── id_ex.v │ │ ├── if_id.v │ │ └── mem_wb.v │ ├── alu_decoder.v │ ├── datapath.v │ ├── defines │ │ ├── aludefines.vh │ │ └── defines.vh │ ├── hazard.v │ ├── main_decoder.v │ ├── mmu.v │ ├── mycpu_top.v │ └── utils │ │ ├── inst_ascii_decoder.v │ │ ├── mux2.v │ │ ├── mux4.v │ │ └── mux8.v ├── PipelineMIPS-sram_like │ ├── bridge_1x2.v │ ├── bridge_2x1.v │ ├── cache │ │ ├── d_cache.v │ │ └── i_cache.v │ ├── core │ │ ├── d_sram_to_sram_like.v │ │ ├── datapath │ │ │ ├── EX │ │ │ │ ├── alu.v │ │ │ │ ├── branch_judge.v │ │ │ │ └── div_radix2.v │ │ │ ├── ID │ │ │ │ ├── branch_predict.v │ │ │ │ ├── imm_ext.v │ │ │ │ ├── jump_predict.v │ │ │ │ └── regfile.v │ │ │ ├── IF │ │ │ │ ├── pc_ctrl.v │ │ │ │ └── pc_reg.v │ │ │ ├── MEM │ │ │ │ ├── cp0_reg.v │ │ │ │ ├── exception.v │ │ │ │ ├── hilo_reg.v │ │ │ │ └── mem_ctrl.v │ │ │ ├── PIPE │ │ │ │ ├── ex_mem.v │ │ │ │ ├── id_ex.v │ │ │ │ ├── if_id.v │ │ │ │ └── mem_wb.v │ │ │ ├── alu_decoder.v │ │ │ ├── datapath.v │ │ │ ├── defines │ │ │ │ ├── aludefines.vh │ │ │ │ └── defines.vh │ │ │ ├── hazard.v │ │ │ ├── main_decoder.v │ │ │ ├── readme.md │ │ │ ├── utils │ │ │ │ ├── inst_ascii_decoder.v │ │ │ │ ├── mux4.v │ │ │ │ └── mux8.v │ │ │ └── xilinx_ip │ │ │ │ ├── signed_mult │ │ │ │ └── signed_mult.xci │ │ │ │ └── unsigned_mult │ │ │ │ └── unsigned_mult.xci │ │ ├── i_sram_to_sram_like.v │ │ ├── mips_core.v │ │ └── readme.md │ ├── cpu_axi_interface.v │ ├── mmu.v │ └── mycpu_top.v ├── PipelineMIPS │ ├── EX │ │ ├── alu.v │ │ ├── branch_judge.v │ │ ├── div_radix2.v │ │ ├── div_self_align.v │ │ └── my_mul.v │ ├── ID │ │ ├── LLbit.v │ │ ├── branch_predict.v │ │ ├── imm_ext.v │ │ ├── jump_predict.v │ │ └── regfile.v │ ├── IF │ │ ├── int.v │ │ ├── pc_ctrl.v │ │ └── pc_reg.v │ ├── MEM │ │ ├── cp0_reg.v │ │ ├── exception.v │ │ ├── hilo_reg.v │ │ └── mem_ctrl.v │ ├── PIPE │ │ ├── ex_mem.v │ │ ├── id_ex.v │ │ ├── if_id.v │ │ └── mem_wb.v │ ├── alu_decoder.v │ ├── arbitrater.v │ ├── d_cache.v │ ├── datapath.v │ ├── defines │ │ ├── aludefines.vh │ │ └── defines.vh │ ├── hazard.v │ ├── i_cache.v │ ├── main_decoder.v │ ├── mycpu_top.v │ ├── tlb.v │ ├── utils │ │ ├── decoder2x4.v │ │ ├── decoder3x8.v │ │ ├── encoder4x2.v │ │ ├── inst_ascii_decoder.v │ │ ├── mux2.v │ │ ├── mux4.v │ │ └── mux8.v │ └── xilinx_ip │ │ ├── d_data_bank │ │ └── d_data_bank.xci │ │ ├── d_tag_ram │ │ └── d_tag_ram.xci │ │ ├── i_data_bank │ │ └── i_data_bank.xci │ │ ├── i_tag_ram │ │ └── i_tag_ram.xci │ │ ├── signed_mult │ │ └── signed_mult.xci │ │ └── unsigned_mult │ │ └── unsigned_mult.xci ├── PipelineMIPS_only_axi │ ├── EX │ │ ├── alu.v │ │ ├── branch_judge.v │ │ └── div_radix2.v │ ├── ID │ │ ├── branch_predict.v │ │ ├── imm_ext.v │ │ ├── jump_predict.v │ │ └── regfile.v │ ├── IF │ │ ├── pc_ctrl.v │ │ └── pc_reg.v │ ├── MEM │ │ ├── cp0_reg.v │ │ ├── exception.v │ │ ├── hilo_reg.v │ │ └── mem_ctrl.v │ ├── PIPE │ │ ├── ex_mem.v │ │ ├── id_ex.v │ │ ├── if_id.v │ │ └── mem_wb.v │ ├── alu_decoder.v │ ├── cpu_axi_interface.v │ ├── d_sram_to_sram_like.v │ ├── datapath.v │ ├── hazard.v │ ├── i_sram_to_sram_like.v │ ├── images │ │ └── readme │ │ │ └── image-20201014174459695.png │ ├── main_decoder.v │ ├── mips_core.v │ ├── mmu.v │ ├── mycpu_top.v │ ├── utils │ │ ├── aludefines.vh │ │ ├── defines.vh │ │ ├── inst_ascii_decoder.v │ │ ├── mux4.v │ │ └── mux8.v │ └── xilinx_ip │ │ ├── signed_mult │ │ └── signed_mult.xci │ │ └── unsigned_mult │ │ └── unsigned_mult.xci ├── basic_pipeline │ ├── EX │ │ └── alu.v │ ├── ID │ │ ├── branch_predict.v │ │ ├── imm_ext.v │ │ └── regfile.v │ ├── IF │ │ ├── pc_ctrl.v │ │ └── pc_reg.v │ ├── PIPE │ │ ├── ex_mem.v │ │ ├── id_ex.v │ │ ├── if_id.v │ │ └── mem_wb.v │ ├── alu_decoder.v │ ├── d_cache.v │ ├── datapath.v │ ├── hazard.v │ ├── i_cache.v │ ├── main_decoder.v │ ├── mycpu_top.v │ ├── simulation │ │ ├── mipstest.asm │ │ ├── mipstest.coe │ │ ├── testbench_behav.wcfg │ │ └── top_tb.v │ ├── soc_top.v │ └── utils │ │ ├── aludefines.vh │ │ ├── defines.vh │ │ ├── inst_ascii_decoder.v │ │ ├── mux2.v │ │ └── mux4.v └── pipelineMIPS-cache_lab │ ├── Analysis.v │ ├── EX │ ├── alu.v │ ├── branch_judge.v │ └── div_radix2.v │ ├── ID │ ├── branch_predict.v │ ├── imm_ext.v │ ├── jump_predict.v │ └── regfile.v │ ├── IF │ ├── pc_ctrl.v │ └── pc_reg.v │ ├── MEM │ ├── cp0_reg.v │ ├── exception.v │ ├── hilo_reg.v │ └── mem_ctrl.v │ ├── PIPE │ ├── ex_mem.v │ ├── id_ex.v │ ├── if_id.v │ └── mem_wb.v │ ├── alu_decoder.v │ ├── bridge_1x2.v │ ├── bridge_2x1.v │ ├── cache.v │ ├── cpu_axi_interface.v │ ├── d_cache-4_way.v │ ├── d_cache-4_way_random.v │ ├── d_cache-write_back.v │ ├── d_cache-write_through.v │ ├── d_cache.v │ ├── d_sram_to_sram_like.v │ ├── datapath.v │ ├── hazard.v │ ├── i_cache-4_way.v │ ├── i_cache-direct_map.v │ ├── i_cache.v │ ├── i_sram_to_sram_like.v │ ├── main_decoder.v │ ├── mips_core.v │ ├── mmu.v │ ├── mycpu_top.v │ ├── readme.txt │ ├── utils │ ├── aludefines.vh │ ├── defines.vh │ ├── inst_ascii_decoder.v │ ├── mux4.v │ └── mux8.v │ └── xilinx_ip │ ├── signed_mult │ └── signed_mult.xci │ └── unsigned_mult │ └── unsigned_mult.xci └── utils ├── copy_ip_xci.py └── copy_proj.py /.gitignore: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/TheRainstorm/PiplineMIPS/HEAD/.gitignore -------------------------------------------------------------------------------- /README.md: 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