├── README.md ├── bit └── top.bit ├── code ├── Divider.v ├── display7.v ├── mp3.v ├── top.v ├── vga_ctrl.v └── vga_display.v ├── test_bench └── mp3_tb.v └── xdc └── top_xdc.xdc /README.md: -------------------------------------------------------------------------------- 1 | # Animation_Projector 2 | ## 同济大学数字逻辑大作业 3 | *** 4 | 本次大作业是利用VGA和mp3实现的一个图片、音频播放器（本来想做动画演示的但是最后没时间研究了~_~）。 5 | *** 6 | VGA部分实现过程可以参考别人写的很不错的代码（原理什么的我好像没搞清楚，但是确实可以正常显示），因此可以正常实现。 7 | *** 8 | mp3比较容易出问题，我个人在上面翻过好几次车了/(ㄒoㄒ)/（所以这个也有专门的test_bench，VGA我都没测试）。 9 | 10 | 主要是coe文件的实现，由于不同的音频文件coe的开头是不一样的，我这里使用的是mid的格式，如果coe的开头和mid的开头不一样的话，那肯定是无法识别出来，因此也就无法正常播放音乐。 11 | 12 | 生成coe的方式，可以将音频文件转成16进制文件，然后这个16进制文件就是我们需要的coe了 13 | 14 | 生成方式有很多，网上有工具，转换文件的格式的也有（甚至可以自己写脚本（。＾▽＾））。 15 | 16 | 然后如果coe没问题的话，接下来可以看是不是硬件连接有故障，我在这上面也栽了好几次了┭┮﹏┭┮。只需要将mp3“人工”好好地连接在FPGA板上面，他就能开始播放，如果不按着的话就可能播放不成功...... 17 | *** 18 | 总之，确定自己代码没什么问题的话，那就考虑硬件的问题，换别人的同模块可能就成功了（甚至可以换板子）（确信）。 19 | *** 20 | 新增了xdc文件和bit文件，大家可以拿来对照参考。xdc文件对应的那些管脚应该是没问题的OwO，bit文件（好像有些bug），如果在自己板子上没跑起来的话也不要太怀疑(x_x)。 21 | -------------------------------------------------------------------------------- /bit/top.bit: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/TheTry16/Animation_Projector/ff52649796da6cb23fca0293e32130134b83fffe/bit/top.bit -------------------------------------------------------------------------------- /code/Divider.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 2023/11/21 17:11:35 7 | // Design Name: 8 | // Module Name: Divider 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | module Divider( 24 | input I_CLK, 25 | input rst, 26 | output O_CLK 27 | ); 28 | parameter N = 20; 29 | 30 | reg [4:0] count = 0; 31 | reg out = 0; 32 | always @(posedge I_CLK) 33 | if(rst) 34 | begin 35 | out <= 0; 36 | count <= 0; 37 | end 38 | else 39 | if(count < N / 2 - 1) 40 | begin 41 | count <= count + 1; 42 | out <= out; 43 | end 44 | else 45 | begin 46 | count <= 0; 47 | out <= ~out; 48 | end 49 | assign O_CLK = out; 50 | endmodule 51 | -------------------------------------------------------------------------------- /code/display7.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 2023/10/26 22:31:26 7 | // Design Name: 8 | // Module Name: display7 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | 24 | module display7( 25 | input clk, 26 | output reg [7:0] enable, 27 | output reg [6:0] oData 28 | ); 29 | 30 | reg [17:0] cnt = 0; 31 | reg [3:0] num_current; 32 | 33 | always @(posedge clk) 34 | begin 35 | cnt = cnt + 1; 36 | case(cnt[17:15]) 37 | 3'b000: 38 | begin 39 | enable <= 8'b1111_1111; 40 | num_current <= 4'd0; 41 | end 42 | 3'b001: 43 | begin 44 | enable <= 8'b1011_1111; 45 | num_current <= 4'd4; 46 | end 47 | 3'b010: 48 | begin 49 | enable <= 8'b1101_1111; 50 | num_current <=4'd3; 51 | end 52 | 3'b011: 53 | begin 54 | enable <= 8'b1110_1111; 55 | num_current <= 4'd6; 56 | end 57 | 3'b100: 58 | begin 59 | enable <= 8'b1111_0111; 60 | num_current <= 4'd6; 61 | end 62 | 3'b101: 63 | begin 64 | enable <= 8'b1111_1011; 65 | num_current <= 4'd7; 66 | end 67 | 3'b110: 68 | begin 69 | enable <= 8'b1111_1101; 70 | num_current <= 4'd7; 71 | end 72 | 3'b111: 73 | begin 74 | enable <= 8'b1111_1110; 75 | num_current <= 4'd6; 76 | end 77 | endcase 78 | end 79 | 80 | always @(*) 81 | begin 82 | case(num_current) 83 | 4'd0 : oData <= 7'b1000000; 84 | 4'd1 : oData <= 7'b1111001; 85 | 4'd2 : oData <= 7'b0100100; 86 | 4'd3 : oData <= 7'b0110000; 87 | 4'd4 : oData <= 7'b0011001; 88 | 4'd5 : oData <= 7'b0010010; 89 | 4'd6 : oData <= 7'b0000010; 90 | 4'd7 : oData <= 7'b1111000; 91 | 4'd8 : oData <= 7'b0000000; 92 | 4'd9 : oData <= 7'b0010000; 93 | default : oData <= 7'b1111111; 94 | endcase 95 | end 96 | 97 | endmodule -------------------------------------------------------------------------------- /code/mp3.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 2024/01/12 15:30:43 7 | // Design Name: 8 | // Module Name: my_mp3 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | module mp3( 24 | input clk, 25 | input rst, 26 | input DREQ, 27 | 28 | output reg xRSET, 29 | output reg XCS, 30 | output reg XDCS, 31 | output reg SI, 32 | output reg SCLK 33 | ); 34 | 35 | parameter PRE = 0; 36 | parameter CMD_START = 1; 37 | parameter CMD_WRITE = 2; 38 | parameter DATA_START = 3; 39 | parameter DATA_WRITE = 4; 40 | reg [2:0] state; 41 | 42 | parameter PRE_TIME = 0; 43 | 44 | parameter CMD_NUM = 2; 45 | reg [2:0] cmd_cnt = 0; 46 | 47 | wire mp3_clk; 48 | Divider #(100) mp3clk(.I_CLK(clk),.rst(0), .O_CLK(mp3_clk)); 49 | 50 | parameter WIDTH = 32; 51 | parameter DEPTH = 3340; 52 | wire [WIDTH - 1:0] Data; 53 | reg [WIDTH - 1:0] IData; 54 | reg [13:0] addr; 55 | blk_mem_gen_1 music(.clka(mp3_clk), .ena(1), .addra(addr), .douta(Data)); 56 | 57 | reg [32:0] cmd_mode = 32'h02000804; 58 | reg [32:0] cmd_vol = 32'h020B0000; 59 | 60 | integer cnt = 0; 61 | integer pre_cnt = 0; 62 | 63 | //FSM 64 | always @(posedge mp3_clk) 65 | begin 66 | if(!rst) 67 | begin 68 | xRSET <= 0; 69 | XCS <= 1; 70 | XDCS <= 1; 71 | SCLK <= 0; 72 | pre_cnt <= 0; 73 | cmd_cnt <= 0; 74 | cnt <= 0; 75 | addr <= 0; 76 | state <= PRE; 77 | end 78 | else 79 | begin 80 | case(state) 81 | //pre 82 | PRE: 83 | begin 84 | if(pre_cnt == PRE_TIME) 85 | begin 86 | pre_cnt <= 0; 87 | xRSET <= 1; 88 | state <= CMD_START; 89 | end 90 | else 91 | pre_cnt <= pre_cnt + 1; 92 | end 93 | //cmd_start 94 | CMD_START: 95 | begin 96 | SCLK <= 0; 97 | if(cmd_cnt == CMD_NUM) 98 | begin 99 | cmd_cnt <= 0; 100 | state <= DATA_START; 101 | end 102 | else if(DREQ) 103 | begin 104 | cnt <= 0; 105 | state <= CMD_WRITE; 106 | end 107 | end 108 | //cmd_write 109 | CMD_WRITE: 110 | begin 111 | if(DREQ) 112 | begin 113 | if(mp3_clk) 114 | begin 115 | if(cnt == 32) 116 | begin 117 | cmd_cnt <= cmd_cnt + 1; 118 | XCS <= 1; 119 | cnt <= 0; 120 | state <= CMD_START; 121 | end 122 | else 123 | begin 124 | XCS <= 0; 125 | if(cmd_cnt == 0) 126 | begin 127 | SI <= cmd_mode[31]; 128 | cmd_mode <= {cmd_mode[30:0], cmd_mode[31]}; 129 | end 130 | else if(cmd_cnt == 1) 131 | begin 132 | SI <= cmd_vol[31]; 133 | cmd_vol <= {cmd_vol[30:0], cmd_vol[31]}; 134 | end 135 | cnt <= cnt + 1; 136 | end 137 | end 138 | SCLK <= ~SCLK; 139 | end 140 | end 141 | //data_start 142 | DATA_START: 143 | begin 144 | if(DREQ) 145 | begin 146 | SCLK <= 0; 147 | IData <= Data; 148 | cnt <= 0; 149 | state <= DATA_WRITE; 150 | end 151 | end 152 | //data_write 153 | DATA_WRITE: 154 | begin 155 | if(SCLK) 156 | begin 157 | if(cnt == WIDTH) 158 | begin 159 | XDCS <= 1; 160 | addr <= addr + 1; 161 | cnt <= 0; 162 | state <= DATA_START; 163 | end 164 | else 165 | begin 166 | XDCS <= 0; 167 | SI <= IData[WIDTH - 1]; 168 | IData <= {IData[WIDTH - 2:0], IData[WIDTH - 1]}; 169 | cnt <= cnt + 1; 170 | end 171 | end 172 | SCLK <= ~SCLK; 173 | end 174 | 175 | default: ; 176 | endcase 177 | end 178 | end 179 | endmodule 180 | -------------------------------------------------------------------------------- /code/top.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 2024/01/14 19:47:43 7 | // Design Name: 8 | // Module Name: top 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | module top( 24 | input clk, 25 | input rst, 26 | 27 | //mp3 28 | input DREQ, 29 | output xRSET, 30 | output XCS, 31 | output XDCS, 32 | output SI, 33 | output SCLK, 34 | 35 | //vga 36 | output hsync, 37 | output vsync, 38 | output [11:0] pic_data, 39 | 40 | //display7 41 | output [7:0] enable, 42 | output [6:0] oData 43 | ); 44 | 45 | //vga 46 | wire [9:0] pix_x; 47 | wire [9:0] pix_y; 48 | wire vga_clk; 49 | 50 | Divider #(4) ( 51 | .I_CLK(clk), 52 | .rst(0), 53 | .O_CLK(vga_clk) 54 | ); 55 | 56 | //mp3 57 | mp3 my_mp3( 58 | .clk(clk), 59 | .rst(rst), 60 | .DREQ(DREQ), 61 | .xRSET(xRSET), 62 | .XCS(XCS), 63 | .XDCS(XDCS), 64 | .SI(SI), 65 | .SCLK(SCLK) 66 | ); 67 | 68 | //vga_ctrl 69 | vga_ctrl my_ctrl( 70 | .vga_clk(vga_clk), 71 | .rst(rst), 72 | .pix_x(pix_x), 73 | .pix_y(pix_y), 74 | .hsync(hsync), 75 | .vsync(vsync) 76 | ); 77 | 78 | //vga_display 79 | vga_display my_display( 80 | .vga_clk(vga_clk), 81 | .rst(rst), 82 | .pix_x(pix_x), 83 | .pix_y(pix_y), 84 | .data_out(pic_data) 85 | ); 86 | 87 | //display7 88 | display7 my_7( 89 | .clk(clk), 90 | .enable(enable), 91 | .oData(oData) 92 | ); 93 | endmodule 94 | -------------------------------------------------------------------------------- /code/vga_ctrl.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 2024/01/14 19:19:41 7 | // Design Name: 8 | // Module Name: vga_ctrl 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | module vga_ctrl( 24 | input wire vga_clk , 25 | input wire rst , 26 | 27 | output wire [9:0] pix_x , 28 | output wire [9:0] pix_y , 29 | output wire hsync , 30 | output wire vsync 31 | ); 32 | parameter H_SYNC = 10'd96 , 33 | H_BACK_PORCH=10'd48, 34 | H_VALID = 10'd640 , 35 | H_FRONT_PORCH = 10'd16 , 36 | H_TOTAL = 10'd800 ; 37 | parameter V_SYNC = 10'd2, 38 | V_BACK_PORCH =10'd33, 39 | V_VALID = 10'd480 , 40 | V_FRONT_PORCH =10'd10, 41 | V_TOTAL = 10'd525 ; 42 | 43 | wire pix_data_req ; 44 | 45 | reg [9:0] cnt_h ; 46 | reg [9:0] cnt_v ; 47 | 48 | always@(posedge vga_clk or negedge rst) 49 | if(!rst) 50 | cnt_h <= 10'd0 ; 51 | else if(cnt_h == H_TOTAL - 1'd1) 52 | cnt_h <= 10'd0 ; 53 | else 54 | cnt_h <= cnt_h + 1'd1 ; 55 | 56 | //hsync 57 | assign hsync = (cnt_h <= H_SYNC - 1'd1) ? 1'b1 : 1'b0 ; 58 | 59 | always@(posedge vga_clk or negedge rst) 60 | if(!rst) 61 | cnt_v <= 10'd0 ; 62 | else if((cnt_v == V_TOTAL - 1'd1) && (cnt_h == H_TOTAL-1'd1)) 63 | cnt_v <= 10'd0 ; 64 | else if(cnt_h == H_TOTAL - 1'd1) 65 | cnt_v <= cnt_v + 1'd1 ; 66 | else 67 | cnt_v <= cnt_v ; 68 | 69 | //vsync 70 | assign vsync = (cnt_v <= V_SYNC - 1'd1) ? 1'b1 : 1'b0 ; 71 | 72 | 73 | assign pix_data_req = (((cnt_h >= H_SYNC + H_BACK_PORCH - 1'b1) 74 | && (cnt_h= V_SYNC + V_BACK_PORCH) 76 | && (cnt_v < V_SYNC + V_BACK_PORCH + V_VALID))) 77 | ? 1'b1 : 1'b0; 78 | 79 | //pix_x,pix_y 80 | assign pix_x = (pix_data_req == 1'b1) 81 | ? (cnt_h - (H_SYNC + H_BACK_PORCH - 1'b1)) : 10'h3ff; 82 | assign pix_y = (pix_data_req == 1'b1) 83 | ? (cnt_v - (V_SYNC + V_BACK_PORCH)) : 10'h3ff; 84 | 85 | endmodule 86 | 87 | -------------------------------------------------------------------------------- /code/vga_display.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 2024/01/14 19:20:30 7 | // Design Name: 8 | // Module Name: vga_display 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | module vga_display( 24 | input vga_clk, 25 | input rst, 26 | input [9:0] pix_x, 27 | input [9:0] pix_y, 28 | 29 | output [11:0] data_out 30 | ); 31 | parameter H_VALID = 10'd640; 32 | parameter V_VALID = 10'd480; 33 | 34 | parameter H_PIC = 10'd500; 35 | parameter W_PIC = 10'd312; 36 | parameter PIC_SIZE = 18'd156000; 37 | 38 | parameter RED = 16'hF800 , 39 | ORANGE = 16'hFC00 , 40 | YELLOW = 16'hFFE0 , 41 | GREEN = 16'h07E0 , 42 | CYAN = 16'h07FF , 43 | BLUE = 16'h001F , 44 | PURPPLE = 16'hF81F , 45 | BLACK = 16'h0000 , 46 | WHITE = 16'hFFFF , 47 | GRAY = 16'hD69A ; 48 | 49 | wire ena; 50 | wire [15:0] pic_data; 51 | reg [17:0] addr; 52 | 53 | reg pic_valid ; 54 | reg [15:0] pix_data; 55 | 56 | assign ena = (((pix_x >= (((H_VALID - H_PIC)/2) - 1'b1)) 57 | && (pix_x < (((H_VALID - H_PIC)/2) + H_PIC - 1'b1))) 58 | &&((pix_y >= ((V_VALID - W_PIC)/2)) 59 | && ((pix_y < (((V_VALID - W_PIC)/2) + W_PIC))))); 60 | 61 | always@(posedge vga_clk or negedge rst) 62 | if(rst == 1'b0) 63 | addr <= 17'd0; 64 | else if(addr == (PIC_SIZE - 1'b1)) 65 | addr <= 17'd0; 66 | else if(ena == 1'b1) 67 | addr <= addr + 1'b1; 68 | 69 | always@(posedge vga_clk or negedge rst) 70 | if(rst == 1'b0) 71 | pic_valid <= 1'b1; 72 | else 73 | pic_valid <= ena; 74 | 75 | assign data_out = (pic_valid == 1'b1) ? {pic_data[15:12],pic_data[10:7],pic_data[4:1]} 76 | : {pix_data[15:12],pix_data[10:7],pix_data[4:1]}; 77 | blk_mem_gen_0 tuanzi 78 | ( 79 | .addra(addr), 80 | .clka(vga_clk), 81 | .ena(ena), 82 | .douta (pic_data) 83 | ); 84 | 85 | endmodule 86 | 87 | -------------------------------------------------------------------------------- /test_bench/mp3_tb.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 2024/01/12 22:21:24 7 | // Design Name: 8 | // Module Name: mp3_tb 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | module mp3_tb(); 24 | reg clk; 25 | reg rst; 26 | reg DREQ; 27 | 28 | wire xRSET; 29 | wire XCS; 30 | wire XDCS; 31 | wire SI; 32 | wire SCLK; 33 | 34 | my_mp3 mp3(.clk(clk), .rst(rst), .DREQ(DREQ), .xRSET(xRSET), .XCS(XCS), .XDCS(XDCS), .SI(SI), .SCLK(SCLK)); 35 | 36 | initial 37 | begin 38 | clk = 0; rst = 0; DREQ = 0; 39 | #25 rst = 1; 40 | DREQ = 1; 41 | end 42 | always #2 clk = ~clk; 43 | endmodule 44 | -------------------------------------------------------------------------------- /xdc/top_xdc.xdc: -------------------------------------------------------------------------------- 1 | set_property PACKAGE_PIN U13 [get_ports {enable[7]}] 2 | set_property PACKAGE_PIN K2 [get_ports {enable[6]}] 3 | set_property PACKAGE_PIN T14 [get_ports {enable[5]}] 4 | set_property PACKAGE_PIN P14 [get_ports {enable[4]}] 5 | set_property PACKAGE_PIN J14 [get_ports {enable[3]}] 6 | set_property PACKAGE_PIN T9 [get_ports {enable[2]}] 7 | set_property PACKAGE_PIN J18 [get_ports {enable[1]}] 8 | set_property PACKAGE_PIN J17 [get_ports {enable[0]}] 9 | set_property IOSTANDARD LVCMOS33 [get_ports {enable[7]}] 10 | set_property IOSTANDARD LVCMOS33 [get_ports {enable[6]}] 11 | set_property IOSTANDARD LVCMOS33 [get_ports {enable[5]}] 12 | set_property IOSTANDARD LVCMOS33 [get_ports {enable[4]}] 13 | set_property IOSTANDARD LVCMOS33 [get_ports {enable[3]}] 14 | set_property IOSTANDARD LVCMOS33 [get_ports {enable[2]}] 15 | set_property IOSTANDARD LVCMOS33 [get_ports {enable[1]}] 16 | set_property IOSTANDARD LVCMOS33 [get_ports {enable[0]}] 17 | set_property PACKAGE_PIN E3 [get_ports clk] 18 | set_property PACKAGE_PIN T10 [get_ports {oData[0]}] 19 | set_property PACKAGE_PIN R10 [get_ports {oData[1]}] 20 | set_property PACKAGE_PIN K16 [get_ports {oData[2]}] 21 | set_property PACKAGE_PIN K13 [get_ports {oData[3]}] 22 | set_property PACKAGE_PIN P15 [get_ports {oData[4]}] 23 | set_property PACKAGE_PIN T11 [get_ports {oData[5]}] 24 | set_property PACKAGE_PIN L18 [get_ports {oData[6]}] 25 | set_property IOSTANDARD LVCMOS33 [get_ports {oData[6]}] 26 | set_property IOSTANDARD LVCMOS33 [get_ports {oData[5]}] 27 | set_property IOSTANDARD LVCMOS33 [get_ports {oData[4]}] 28 | set_property IOSTANDARD LVCMOS33 [get_ports {oData[3]}] 29 | set_property IOSTANDARD LVCMOS33 [get_ports {oData[2]}] 30 | set_property IOSTANDARD LVCMOS33 [get_ports {oData[1]}] 31 | set_property IOSTANDARD LVCMOS33 [get_ports {oData[0]}] 32 | set_property PACKAGE_PIN J2 [get_ports DREQ] 33 | set_property PACKAGE_PIN J3 [get_ports SCLK] 34 | set_property PACKAGE_PIN J4 [get_ports SI] 35 | set_property PACKAGE_PIN E7 [get_ports XCS] 36 | set_property PACKAGE_PIN K1 [get_ports XDCS] 37 | set_property PACKAGE_PIN F6 [get_ports xRSET] 38 | 39 | set_property IOSTANDARD LVCMOS33 [get_ports {pic_data[11]}] 40 | set_property IOSTANDARD LVCMOS33 [get_ports {pic_data[10]}] 41 | set_property IOSTANDARD LVCMOS33 [get_ports {pic_data[9]}] 42 | set_property IOSTANDARD LVCMOS33 [get_ports {pic_data[8]}] 43 | set_property IOSTANDARD LVCMOS33 [get_ports {pic_data[7]}] 44 | set_property IOSTANDARD LVCMOS33 [get_ports {pic_data[6]}] 45 | set_property IOSTANDARD LVCMOS33 [get_ports {pic_data[5]}] 46 | set_property IOSTANDARD LVCMOS33 [get_ports {pic_data[4]}] 47 | set_property IOSTANDARD LVCMOS33 [get_ports {pic_data[3]}] 48 | set_property IOSTANDARD LVCMOS33 [get_ports {pic_data[2]}] 49 | set_property IOSTANDARD LVCMOS33 [get_ports {pic_data[1]}] 50 | set_property IOSTANDARD LVCMOS33 [get_ports {pic_data[0]}] 51 | set_property PACKAGE_PIN B7 [get_ports {pic_data[0]}] 52 | set_property PACKAGE_PIN C7 [get_ports {pic_data[1]}] 53 | set_property PACKAGE_PIN D7 [get_ports {pic_data[2]}] 54 | set_property PACKAGE_PIN D8 [get_ports {pic_data[3]}] 55 | set_property PACKAGE_PIN C6 [get_ports {pic_data[4]}] 56 | set_property PACKAGE_PIN A5 [get_ports {pic_data[5]}] 57 | set_property PACKAGE_PIN B6 [get_ports {pic_data[6]}] 58 | set_property PACKAGE_PIN A6 [get_ports {pic_data[7]}] 59 | set_property PACKAGE_PIN A3 [get_ports {pic_data[8]}] 60 | set_property PACKAGE_PIN B4 [get_ports {pic_data[9]}] 61 | set_property PACKAGE_PIN C5 [get_ports {pic_data[10]}] 62 | set_property PACKAGE_PIN A4 [get_ports {pic_data[11]}] 63 | set_property PACKAGE_PIN J15 [get_ports rst] 64 | set_property PACKAGE_PIN B11 [get_ports hsync] 65 | set_property PACKAGE_PIN B12 [get_ports vsync] 66 | set_property IOSTANDARD LVCMOS33 [get_ports clk] 67 | set_property IOSTANDARD LVCMOS33 [get_ports DREQ] 68 | set_property IOSTANDARD LVCMOS33 [get_ports hsync] 69 | set_property IOSTANDARD LVCMOS33 [get_ports rst] 70 | set_property IOSTANDARD LVCMOS33 [get_ports SCLK] 71 | set_property IOSTANDARD LVCMOS33 [get_ports SI] 72 | set_property IOSTANDARD LVCMOS33 [get_ports vsync] 73 | set_property IOSTANDARD LVCMOS33 [get_ports XCS] 74 | set_property IOSTANDARD LVCMOS33 [get_ports XDCS] 75 | set_property IOSTANDARD LVCMOS33 [get_ports xRSET] 76 | 77 | 78 | 79 | 80 | --------------------------------------------------------------------------------