├── pin.png ├── example-vivado-readfile.zip ├── example-vivado-readsector.zip ├── SIM ├── tb_sd_file_reader_run_iverilog.bat ├── tb_sd_file_reader.v └── sd_fake.v ├── RTL ├── sdcmd_ctrl.v ├── sd_reader.v └── sd_file_reader.v ├── README.md └── LICENSE /pin.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ThinkCodeStudio/FPGA-SDcard-Reader/main/pin.png -------------------------------------------------------------------------------- /example-vivado-readfile.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ThinkCodeStudio/FPGA-SDcard-Reader/main/example-vivado-readfile.zip -------------------------------------------------------------------------------- /example-vivado-readsector.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ThinkCodeStudio/FPGA-SDcard-Reader/main/example-vivado-readsector.zip -------------------------------------------------------------------------------- /SIM/tb_sd_file_reader_run_iverilog.bat: -------------------------------------------------------------------------------- 1 | del sim.out dump.vcd 2 | iverilog -g2001 -o sim.out tb_sd_file_reader.v sd_fake.v ../RTL/sd_file_reader.v ../RTL/sd_reader.v ../RTL/sdcmd_ctrl.v 3 | vvp -n sim.out 4 | del sim.out 5 | pause -------------------------------------------------------------------------------- /RTL/sdcmd_ctrl.v: -------------------------------------------------------------------------------- 1 | 2 | //-------------------------------------------------------------------------------------------------------- 3 | // Module : sdcmd_ctrl 4 | // Type : synthesizable, IP's sub module 5 | // Standard: Verilog 2001 (IEEE1364-2001) 6 | // Function: sdcmd signal control, 7 | // instantiated by sd_reader 8 | //-------------------------------------------------------------------------------------------------------- 9 | 10 | module sdcmd_ctrl ( 11 | input wire rstn, 12 | input wire clk, 13 | // SDcard signals (sdclk and sdcmd) 14 | output reg sdclk, 15 | inout sdcmd, 16 | // config clk freq 17 | input wire [15:0] clkdiv, 18 | // user input signal 19 | input wire start, 20 | input wire [15:0] precnt, 21 | input wire [ 5:0] cmd, 22 | input wire [31:0] arg, 23 | // user output signal 24 | output reg busy, 25 | output reg done, 26 | output reg timeout, 27 | output reg syntaxe, 28 | output wire [31:0] resparg 29 | ); 30 | 31 | 32 | initial {busy, done, timeout, syntaxe} = 0; 33 | initial sdclk = 1'b0; 34 | 35 | localparam [7:0] TIMEOUT = 8'd250; 36 | 37 | reg sdcmdoe = 1'b0; 38 | reg sdcmdout = 1'b1; 39 | 40 | // sdcmd tri-state driver 41 | assign sdcmd = sdcmdoe ? sdcmdout : 1'bz; 42 | wire sdcmdin = sdcmdoe ? 1'b1 : sdcmd; 43 | 44 | function [6:0] CalcCrc7; 45 | input [6:0] crc; 46 | input [0:0] inbit; 47 | //function automatic logic [6:0] CalcCrc7(input logic [6:0] crc, input logic inbit); 48 | begin 49 | CalcCrc7 = ( {crc[5:0],crc[6]^inbit} ^ {3'b0,crc[6]^inbit,3'b0} ); 50 | end 51 | endfunction 52 | 53 | reg [ 5:0] req_cmd = 6'd0; // request[45:40] 54 | reg [31:0] req_arg = 0; // request[39: 8] 55 | reg [ 6:0] req_crc = 7'd0; // request[ 7: 1] 56 | wire [51:0] request = {6'b111101, req_cmd, req_arg, req_crc, 1'b1}; 57 | 58 | //struct packed { 59 | reg resp_st; 60 | reg [ 5:0] resp_cmd; 61 | reg [31:0] resp_arg; 62 | //} response = 0; 63 | 64 | assign resparg = resp_arg; 65 | 66 | reg [17:0] clkdivr = 18'h3FFFF; 67 | reg [17:0] clkcnt = 0; 68 | reg [15:0] cnt1 = 0; 69 | reg [ 5:0] cnt2 = 6'h3F; 70 | reg [ 7:0] cnt3 = 0; 71 | reg [ 7:0] cnt4 = 8'hFF; 72 | 73 | 74 | always @ (posedge clk or negedge rstn) 75 | if(~rstn) begin 76 | {busy, done, timeout, syntaxe} <= 0; 77 | sdclk <= 1'b0; 78 | {sdcmdoe, sdcmdout} <= 2'b01; 79 | {req_cmd, req_arg, req_crc} <= 0; 80 | {resp_st, resp_cmd, resp_arg} <= 0; 81 | clkdivr <= 18'h3FFFF; 82 | clkcnt <= 0; 83 | cnt1 <= 0; 84 | cnt2 <= 6'h3F; 85 | cnt3 <= 0; 86 | cnt4 <= 8'hFF; 87 | end else begin 88 | {done, timeout, syntaxe} <= 0; 89 | 90 | clkcnt <= ( clkcnt < {clkdivr[16:0],1'b1} ) ? (clkcnt+18'd1) : 18'd0; 91 | 92 | if (clkcnt == 18'd0) 93 | clkdivr <= {2'h0, clkdiv} + 18'd1; 94 | 95 | if (clkcnt == clkdivr) 96 | sdclk <= 1'b0; 97 | else if (clkcnt == {clkdivr[16:0],1'b1} ) 98 | sdclk <= 1'b1; 99 | 100 | if(~busy) begin 101 | if(start) busy <= 1'b1; 102 | req_cmd <= cmd; 103 | req_arg <= arg; 104 | req_crc <= 0; 105 | cnt1 <= precnt; 106 | cnt2 <= 6'd51; 107 | cnt3 <= TIMEOUT; 108 | cnt4 <= 8'd134; 109 | end else if(done) begin 110 | busy <= 1'b0; 111 | end else if( clkcnt == clkdivr) begin 112 | {sdcmdoe, sdcmdout} <= 2'b01; 113 | if (cnt1 != 16'd0) begin 114 | cnt1 <= cnt1 - 16'd1; 115 | end else if(cnt2 != 6'h3F) begin 116 | cnt2 <= cnt2 - 6'd1; 117 | {sdcmdoe, sdcmdout} <= {1'b1, request[cnt2]}; 118 | if(cnt2>=8 && cnt2<48) req_crc <= CalcCrc7(req_crc, request[cnt2]); 119 | end 120 | end else if( clkcnt == {clkdivr[16:0],1'b1} && cnt1==16'd0 && cnt2==6'h3F ) begin 121 | if(cnt3 != 8'd0) begin 122 | cnt3 <= cnt3 - 8'd1; 123 | if(~sdcmdin) 124 | cnt3 <= 8'd0; 125 | else if(cnt3 == 8'd1) 126 | {done, timeout, syntaxe} <= 3'b110; 127 | end else if(cnt4 != 8'hFF) begin 128 | cnt4 <= cnt4 - 8'd1; 129 | if(cnt4 >= 8'd96) 130 | {resp_st, resp_cmd, resp_arg} <= {resp_cmd, resp_arg, sdcmdin}; 131 | if(cnt4 == 8'd0) begin 132 | {done, timeout} <= 2'b10; 133 | syntaxe <= resp_st || ((resp_cmd!=req_cmd) && (resp_cmd!=6'h3F) && (resp_cmd!=6'd0)); 134 | end 135 | end 136 | end 137 | end 138 | 139 | endmodule 140 | -------------------------------------------------------------------------------- /RTL/sd_reader.v: -------------------------------------------------------------------------------- 1 | 2 | //-------------------------------------------------------------------------------------------------------- 3 | // Module : sd_reader 4 | // Type : synthesizable, IP's top 5 | // Standard: Verilog 2001 (IEEE1364-2001) 6 | // Function: A SD-host to initialize SD-card and read sector 7 | // Support CardType : SDv1.1 , SDv2 or SDHCv2 8 | //-------------------------------------------------------------------------------------------------------- 9 | 10 | module sd_reader # ( 11 | parameter [2:0] CLK_DIV = 3'd2, // when clk = 0~ 25MHz , set CLK_DIV = 3'd1, 12 | // when clk = 25~ 50MHz , set CLK_DIV = 3'd2, 13 | // when clk = 50~100MHz , set CLK_DIV = 3'd3, 14 | // when clk = 100~200MHz , set CLK_DIV = 3'd4, 15 | // ...... 16 | parameter SIMULATE = 0 17 | ) ( 18 | // rstn active-low, 1:working, 0:reset 19 | input wire rstn, 20 | // clock 21 | input wire clk, 22 | // SDcard signals (connect to SDcard), this design do not use sddat1~sddat3. 23 | output wire sdclk, 24 | inout sdcmd, 25 | input wire sddat0, // FPGA only read SDDAT signal but never drive it 26 | // show card status 27 | output wire [ 3:0] card_stat, // show the sdcard initialize status 28 | output reg [ 1:0] card_type, // 0=UNKNOWN , 1=SDv1 , 2=SDv2 , 3=SDHCv2 29 | // user read sector command interface (sync with clk) 30 | input wire rstart, 31 | input wire [31:0] rsector, 32 | output wire rbusy, 33 | output wire rdone, 34 | // sector data output interface (sync with clk) 35 | output reg outen, // when outen=1, a byte of sector content is read out from outbyte 36 | output reg [ 8:0] outaddr, // outaddr from 0 to 511, because the sector size is 512 37 | output reg [ 7:0] outbyte // a byte of sector content 38 | ); 39 | 40 | 41 | initial {outen, outaddr, outbyte} = 0; 42 | 43 | localparam [1:0] UNKNOWN = 2'd0, // SD card type 44 | SDv1 = 2'd1, 45 | SDv2 = 2'd2, 46 | SDHCv2 = 2'd3; 47 | 48 | localparam [15:0] FASTCLKDIV = (16'd1 << CLK_DIV) ; 49 | localparam [15:0] SLOWCLKDIV = FASTCLKDIV * (SIMULATE ? 16'd5 : 16'd48); 50 | 51 | reg start = 1'b0; 52 | reg [15:0] precnt = 0; 53 | reg [ 5:0] cmd = 0; 54 | reg [31:0] arg = 0; 55 | reg [15:0] clkdiv = SLOWCLKDIV; 56 | reg [31:0] rsectoraddr = 0; 57 | 58 | wire busy, done, timeout, syntaxe; 59 | wire[31:0] resparg; 60 | 61 | reg sdv1_maybe = 1'b0; 62 | reg [ 2:0] cmd8_cnt = 0; 63 | reg [15:0] rca = 0; 64 | 65 | localparam [3:0] CMD0 = 4'd0, 66 | CMD8 = 4'd1, 67 | CMD55_41 = 4'd2, 68 | ACMD41 = 4'd3, 69 | CMD2 = 4'd4, 70 | CMD3 = 4'd5, 71 | CMD7 = 4'd6, 72 | CMD16 = 4'd7, 73 | CMD17 = 4'd8, 74 | READING = 4'd9, 75 | READING2 = 4'd10; 76 | 77 | reg [3:0] sdcmd_stat = CMD0; 78 | //enum logic [3:0] {CMD0, CMD8, CMD55_41, ACMD41, CMD2, CMD3, CMD7, CMD16, CMD17, READING, READING2} sdcmd_stat = CMD0; 79 | 80 | reg sdclkl = 1'b0; 81 | 82 | localparam [2:0] RWAIT = 3'd0, 83 | RDURING = 3'd1, 84 | RTAIL = 3'd2, 85 | RDONE = 3'd3, 86 | RTIMEOUT = 3'd4; 87 | 88 | reg [2:0] sddat_stat = RWAIT; 89 | 90 | //enum logic [2:0] {RWAIT, RDURING, RTAIL, RDONE, RTIMEOUT} sddat_stat = RWAIT; 91 | 92 | reg [31:0] ridx = 0; 93 | 94 | assign rbusy = (sdcmd_stat != CMD17) ; 95 | assign rdone = (sdcmd_stat == READING2) && (sddat_stat==RDONE); 96 | 97 | assign card_stat = sdcmd_stat; 98 | 99 | 100 | sdcmd_ctrl u_sdcmd_ctrl ( 101 | .rstn ( rstn ), 102 | .clk ( clk ), 103 | .sdclk ( sdclk ), 104 | .sdcmd ( sdcmd ), 105 | .clkdiv ( clkdiv ), 106 | .start ( start ), 107 | .precnt ( precnt ), 108 | .cmd ( cmd ), 109 | .arg ( arg ), 110 | .busy ( busy ), 111 | .done ( done ), 112 | .timeout ( timeout ), 113 | .syntaxe ( syntaxe ), 114 | .resparg ( resparg ) 115 | ); 116 | 117 | 118 | task set_cmd; 119 | input [ 0:0] _start; 120 | input [15:0] _precnt; 121 | input [ 5:0] _cmd; 122 | input [31:0] _arg; 123 | //task automatic set_cmd(input _start, input[15:0] _precnt='0, input[5:0] _cmd='0, input[31:0] _arg='0 ); 124 | begin 125 | start <= _start; 126 | precnt <= _precnt; 127 | cmd <= _cmd; 128 | arg <= _arg; 129 | end 130 | endtask 131 | 132 | 133 | 134 | 135 | always @ (posedge clk or negedge rstn) 136 | if(~rstn) begin 137 | set_cmd(0,0,0,0); 138 | clkdiv <= SLOWCLKDIV; 139 | rsectoraddr <= 0; 140 | rca <= 0; 141 | sdv1_maybe <= 1'b0; 142 | card_type <= UNKNOWN; 143 | sdcmd_stat <= CMD0; 144 | cmd8_cnt <= 0; 145 | end else begin 146 | set_cmd(0,0,0,0); 147 | if(sdcmd_stat == READING2) begin 148 | if(sddat_stat==RTIMEOUT) begin 149 | set_cmd(1, 96, 17, rsectoraddr); 150 | sdcmd_stat <= READING; 151 | end else if(sddat_stat==RDONE) 152 | sdcmd_stat <= CMD17; 153 | end else if(~busy) begin 154 | case(sdcmd_stat) 155 | CMD0 : set_cmd(1, (SIMULATE?512:64000), 0, 'h00000000); 156 | CMD8 : set_cmd(1, 512 , 8, 'h000001aa); 157 | CMD55_41: set_cmd(1, 512 , 55, 'h00000000); 158 | ACMD41 : set_cmd(1, 256 , 41, 'h40100000); 159 | CMD2 : set_cmd(1, 256 , 2, 'h00000000); 160 | CMD3 : set_cmd(1, 256 , 3, 'h00000000); 161 | CMD7 : set_cmd(1, 256 , 7, {rca,16'h0}); 162 | CMD16 : set_cmd(1, (SIMULATE?512:64000), 16, 'h00000200); 163 | CMD17 : if(rstart) begin 164 | set_cmd(1, 96, 17, (card_type==SDHCv2) ? rsector : (rsector<<9) ); 165 | rsectoraddr <= (card_type==SDHCv2) ? rsector : (rsector<<9); 166 | sdcmd_stat <= READING; 167 | end 168 | endcase 169 | end else if(done) begin 170 | case(sdcmd_stat) 171 | CMD0 : sdcmd_stat <= CMD8; 172 | CMD8 : if(~timeout && ~syntaxe && resparg[7:0]==8'haa) begin 173 | sdcmd_stat <= CMD55_41; 174 | end else if(timeout) begin 175 | cmd8_cnt <= cmd8_cnt + 3'd1; 176 | if (cmd8_cnt == 3'b111) begin 177 | sdv1_maybe <= 1'b1; 178 | sdcmd_stat <= CMD55_41; 179 | end 180 | end 181 | CMD55_41: if(~timeout && ~syntaxe) 182 | sdcmd_stat <= ACMD41; 183 | ACMD41 : if(~timeout && ~syntaxe && resparg[31]) begin 184 | card_type <= sdv1_maybe ? SDv1 : (resparg[30] ? SDHCv2 : SDv2); 185 | sdcmd_stat <= CMD2; 186 | end else begin 187 | sdcmd_stat <= CMD55_41; 188 | end 189 | CMD2 : if(~timeout && ~syntaxe) 190 | sdcmd_stat <= CMD3; 191 | CMD3 : if(~timeout && ~syntaxe) begin 192 | rca <= resparg[31:16]; 193 | sdcmd_stat <= CMD7; 194 | end 195 | CMD7 : if(~timeout && ~syntaxe) begin 196 | clkdiv <= FASTCLKDIV; 197 | sdcmd_stat <= CMD16; 198 | end 199 | CMD16 : if(~timeout && ~syntaxe) 200 | sdcmd_stat <= CMD17; 201 | default : //READING : 202 | if(~timeout && ~syntaxe) 203 | sdcmd_stat <= READING2; 204 | else 205 | set_cmd(1, 128, 17, rsectoraddr); 206 | endcase 207 | end 208 | end 209 | 210 | 211 | always @ (posedge clk or negedge rstn) 212 | if(~rstn) begin 213 | outen <= 1'b0; 214 | outaddr <= 0; 215 | outbyte <= 0; 216 | sdclkl <= 1'b0; 217 | sddat_stat <= RWAIT; 218 | ridx <= 0; 219 | end else begin 220 | outen <= 1'b0; 221 | outaddr <= 0; 222 | sdclkl <= sdclk; 223 | if(sdcmd_stat!=READING && sdcmd_stat!=READING2) begin 224 | sddat_stat <= RWAIT; 225 | ridx <= 0; 226 | end else if(~sdclkl & sdclk) begin 227 | case(sddat_stat) 228 | RWAIT : begin 229 | if(~sddat0) begin 230 | sddat_stat <= RDURING; 231 | ridx <= 0; 232 | end else begin 233 | if(ridx > 1000000) // according to SD datasheet, 1ms is enough to wait for DAT result, here, we set timeout to 1000000 clock cycles = 80ms (when SDCLK=12.5MHz) 234 | sddat_stat <= RTIMEOUT; 235 | ridx <= ridx + 1; 236 | end 237 | end 238 | RDURING : begin 239 | outbyte[3'd7 - ridx[2:0]] <= sddat0; 240 | if(ridx[2:0] == 3'd7) begin 241 | outen <= 1'b1; 242 | outaddr<= ridx[11:3]; 243 | end 244 | if(ridx >= 512*8-1) begin 245 | sddat_stat <= RTAIL; 246 | ridx <= 0; 247 | end else begin 248 | ridx <= ridx + 1; 249 | end 250 | end 251 | RTAIL : begin 252 | if (ridx >= 8*8-1) 253 | sddat_stat <= RDONE; 254 | ridx <= ridx + 1; 255 | end 256 | endcase 257 | end 258 | end 259 | 260 | 261 | endmodule 262 | 263 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | ![语言](https://img.shields.io/badge/语言-verilog_(IEEE1364_2001)-9A90FD.svg) ![仿真](https://img.shields.io/badge/仿真-iverilog-green.svg) ![部署](https://img.shields.io/badge/部署-quartus-blue.svg) ![部署](https://img.shields.io/badge/部署-vivado-FF1010.svg) 2 | 3 | [English](#en) | [中文](#cn) 4 | 5 | 　 6 | 7 | FPGA SDcard File Reader 8 | =========================== 9 | 10 | FPGA-based SDcard file reader 11 | 12 | * **Function**: FPGA acts as **SD-host**, specifying the file name to read the file content; or specifying the sector number to read the sector content. 13 | * **Performance**: Use SD bus instead of SPI bus. Read faster. 14 | * **Strong compatibility**: automatically adapt to **SDcard version**, automatically adapt to **FAT16/FAT32 file system**. 15 | * pure Verilog implement, easy to simulate and transplant. 16 | 17 | | | SDv1.1 card | SDv2 card | SDHCv2 card | 18 | | :-------------------- | :----------------: | :----------------: | :----------------: | 19 | | **Read Sector** | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | 20 | | **Read File (FAT16)** | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | 21 | | **Read File (FAT32)** | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | 22 | 23 | 　 24 | 25 | # Background 26 | 27 | ## SD bus 28 | 29 | The SDcard is connected to the SD-host (such as a card adaptor) using the SD bus. The signals of the SD bus include: 30 | 31 | | Signal name | Direction | 32 | | ------------------------------ | ------------------------------------------------------------ | 33 | | sdclk | host→card | 34 | | sdcmd | host→card when request command, card→host when respond command | 35 | | sddat0, sddat1, sddat2, sddat3 | host→card, when write data, card→host when read data | 36 | 37 | The pin definitions of these signals on SDcard and microSDcard are as follows (SDcard and microSDcard have no difference in function except for the shape and appearance). 38 | 39 | | ![pin](./pin.png) | 40 | | :----------------------------------------------------------: | 41 | | Figure : pin defination of SDcard (left) and microSDcard (right) | 42 | 43 | ## File System 44 | 45 | The SDcard is just a large linear data storage space, divided into multiple sectors, each sector contains 512 bytes, the address range of sector 0 is 0x00000000\~0x000001FF, and the address range of sector 1 is 0x00000200\~0x000003FF, and so on…. The underlying read and write operations are performed in unit of sectors. In order to organize disk partitions and files in this linear storage space, people stipulate complex data structures: file system. The most commonly used file systems for SDcard are FAT16 and FAT32. 46 | 47 | In order to read file data from SDcard, this library is divided into two functional modules: 48 | 49 | - Manipulate the SD bus according to the SD bus standard, specify the sector number and read the sector. 50 | - On the basis of being able to read sectors, parse the file system, that is, given the file name, to find the location and length of the file. In fact, the file may not be stored contiguously (that is, split into multiple blocks in different sectors), my code will handle this case correctly. 51 | 52 | 　 53 | 54 | 55 | # How to use this module 56 | 57 | sd_file_reader.v in the [RTL](./RTL) folder is the top-level module of the SD card file reader, and it is defined as follows: 58 | 59 | ```verilog 60 | module sd_file_reader #( 61 | parameter FILE_NAME_LEN = 11 , // valid length of FILE_NAME (in bytes) 62 | parameter [52*8-1:0] FILE_NAME = "example.txt", // file to read, ignore Upper and Lower Case 63 | // For example, if you want to read a file named HeLLo123.txt in the SD card, 64 | // this parameter can be hello123.TXT, HELLO123.txt or HEllo123.Txt 65 | parameter [2:0] CLK_DIV = 3'd2, // when clk = 0~ 25MHz , set CLK_DIV = 3'd1, 66 | // when clk = 25~ 50MHz , set CLK_DIV = 3'd2, 67 | // when clk = 50~100MHz , set CLK_DIV = 3'd3, 68 | // when clk = 100~200MHz , set CLK_DIV = 3'd4, 69 | // ...... 70 | parameter SIMULATE = 0 71 | ) ( 72 | // rstn active-low, 1:working, 0:reset 73 | input wire rstn, 74 | // clock 75 | input wire clk, 76 | // SDcard signals (connect to SDcard), this design do not use sddat1~sddat3. 77 | output wire sdclk, 78 | inout sdcmd, 79 | input wire sddat0, // FPGA only read SDDAT signal but never drive it 80 | // status output (optional for user) 81 | output wire [3:0] card_stat, // show the sdcard initialize status 82 | output wire [1:0] card_type, // 0=UNKNOWN , 1=SDv1 , 2=SDv2 , 3=SDHCv2 83 | output wire [1:0] filesystem_type, // 0=UNASSIGNED , 1=UNKNOWN , 2=FAT16 , 3=FAT32 84 | output reg file_found, // 0=file not found, 1=file found 85 | // file content data output (sync with clk) 86 | output reg outen, // when outen=1, a byte of file content is read out from outbyte 87 | output reg [7:0] outbyte // a byte of file content 88 | ); 89 | ``` 90 | 91 | where: 92 | 93 | - `FILE_NAME` specifies the name of the target file to read. 94 | - `FILE_NAME_LEN` specifies the file name's length (in bytes). E.g., length of "example.txt" is 11. 95 | - `CLK_DIV` is the clock frequency division factor, its value needs to be determined according to the `clk` frequency you provide (see code comments for details). 96 | - `SIMULATE` is the simulation speed-up option. **Usually set to `0`**. It can be set to `1` only during simulation to speed up the SD card initialization progress and prevent the simulation from taking too much time. 97 | - `clk` is the module driving clock. 98 | - `rstn` is the reset signal, you need to set `rstn=0` before starting to work, and then set `rstn=1` to release it. 99 | - `sdclk` , `sdcmd` , `sddat0` are SD bus signals, should connect to SDcard. 100 | - Note that this module only uses `sddat0` and does not use `sddat1~sddat3`, because the SDcard will run in 1bit narrow data bus mode by default when powered on, and can be switched to 4bit wide data bus mode with the command, I did not switch it, always use only `sddat0`. And `sddat1~sddat3` can be left unconnected. 101 | - `card_type` will output the detected SDcard type: 0 corresponds to unknown, 1 corresponds to SDv1, 2 corresponds to SDv2, 3 corresponds to SDHCv2. 102 | - `file_system_type` will output the detected file system of SDcard: 1 corresponds to unknown, 2 corresponds to FAT16, 3 corresponds to FAT32. 103 | - `file_found` will output whether the target file was found: 0 means not found, 1 means found. 104 | - If the target file is found, the module will output all the bytes in the file. For each output byte, a high-level pulse will be generated on `outen`, and the byte will appear on `outbyte`. 105 | 106 | > :warning: This repo only uses sddat0 (i.e. SD 1-bit bus mode) instead of sddat1\~3. When working, you need to continuously pull sddat1\~3 high (you can write `assign sddat[3:1] = 3'b111;` in the FPGA code, or use pull-up resistors on the PCB). This is to ensure that the SD card can enter SD bus mode normally, otherwise it will enter SPI bus mode. 107 | 108 | 　 109 | 110 | # RTL Simulation 111 | 112 | Simulation related files are in the [SIM](./SIM) folder, where: 113 | 114 | - sd_fake.v is the code for FPGA to imitate an SDcard. It comes from another repo of mine: [FPGA-SDfake](https://github.com/WangXuan95/FPGA-SDfake) . In this simulation, it imitates an SDcard with FAT32 system with a file "example.txt" inside. And it will be readed by the design under test (sd_file_reader.v). 115 | - tb_sd_file_reader.v is the top level of the simulation, it will call sd_file_reader.v to read the file in sd_fake.v . 116 | - tb_sd_file_reader_run_iverilog.bat is a command script to run iverilog simulations. 117 | 118 | Before simulate using iverilog, you need to install iverilog , see: [iverilog_usage](https://github.com/WangXuan95/WangXuan95/blob/main/iverilog_usage/iverilog_usage.md) 119 | 120 | Then double-click tb_sd_file_reader_run_iverilog.bat to run simulation, which will run for several minutes. 121 | 122 | After the simulation runs, you can open the generated dump.vcd file to view the waveform. 123 | 124 | 　 125 | 126 | FPGA Demo: Read File 127 | =========================== 128 | 129 | example-vivado-readfile.zip contains a vivado project, which runs on the [Nexys4 development board](http://www.digilent.com.cn/products/product-nexys-4-ddr-artix-7-fpga- trainer-board.html) (it has a microSDcard slot). It will search the file example.txt from the root directory of the SDcard and read its entire content, and then send it to PC via **UART**. 130 | 131 | Run the demo as follows: 132 | 133 | 1. Prepare a **microSDcard** of **FAT16** or **FAT32**. If it is not **FAT16** or **FAT32**, you need to format it. 134 | 2. Create **example.txt** in the root directory (the file name is not limited in case), and write some content in the file. 135 | 3. Insert the SDcard into the card slot of Nexys4. 136 | 4. Plug the USB port of Nexys4 into PC, and open the corresponding serial port with software such as **Serial Assistant**, **Putty**, **HyperTerminal** or **minicom**. 137 | 5. Unzip example-vivado-readfile.zip . Then open the project in it with vivado, synthesize and program it. 138 | 6. Observe that the serial port prints the contents of the file. 139 | 7. Simutinously, you can see that the LEDs on the Nexys4 change, they indicate the type and status of the SDcard, see the code for the specific meaning. 140 | 8. Press the red CPU\_RESET button on Nexys4 to re-read and print out the file content again. 141 | 142 | 　 143 | 144 | FPGA Demo: Read Sector 145 | =========================== 146 | 147 | example-vivado-readsector.zip contains a vivado project, which runs on the [Nexys4 development board](http://www.digilent.com.cn/products/product-nexys-4-ddr-artix-7-fpga- trainer-board.html), it will read sector 0 from the SD card (it is often called the MBR sector in file systems) and send it to PC via **UART**. 148 | 149 | Run the demo as follows: 150 | 151 | 1. Prepare a **microSDcard**. Plug it into the card slot of Nexys4. 152 | 2. Plug the USB port of Nexys4 into PC, use **Serial Assistant** to open the corresponding serial port, please select "HEX Receive Mode", print each byte in hexadecimal form, so that we can see those ASCII non-printable characters. 153 | 3. Unzip example-vivado-readsector.zip . Then use vivado to open the project in it, synthesize and program it. 154 | 4. Observe that the serial port prints the contents of sector 0. 155 | 5. At the same time, you can also see that the LEDs on the Nexys4 change, they indicate the type and status of the SDcard, see the code comments for the specific meaning. 156 | 6. Press the red CPU\_RESET button on Nexys4 to re-read and print out the sector content again. 157 | 158 | 　 159 | 160 | 　 161 | 162 | 　 163 | 164 | 　 165 | 166 | 　 167 | 168 | 169 | FPGA SDcard File Reader 170 | =========================== 171 | 172 | 基于 FPGA 的 SD卡文件读取器 173 | 174 | * **功能** ：FPGA作为 **SD-host** ， 指定文件名读取文件内容；或指定扇区号读取扇区内容。 175 | * **性能** ：使用 SD总线，而不是 SPI总线。读取速度更快。 176 | * **兼容性强** ：自动适配 **SD卡版本** ，自动适配 **FAT16/FAT32文件系统**。 177 | * 纯 Verilog 实现，便于移植和仿真。 178 | 179 | | | SDv1.1 card | SDv2 card | SDHCv2 card | 180 | | :----- | :------------: | :------------: | :------------: | 181 | | **读取扇区** | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | 182 | | **读取文件 (FAT16)** | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | 183 | | **读取文件 (FAT32)** | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | 184 | 185 | 　 186 | 187 | # 背景知识 188 | 189 | ## SD总线 190 | 191 | SD卡使用 SD 总线与 SD-host （比如读卡器）连接，SD总线的信号包括： 192 | 193 | | 信号名 | 输入输出方向 | 194 | | ------------------------------ | ------------------------------------------------ | 195 | | sdclk | host→ card | 196 | | sdcmd | 当发起命令时 host→ card ，当响应命令时 card→host | 197 | | sddat0、sddat1、sddat2、sddat3 | 当写数据时 host→card ，当读数据时 card→host | 198 | 199 | 这些信号在 SD 卡和 microSD 卡上的引脚定义如下图（SD卡和microSD卡除了外形尺寸外，功能上没有差别） 200 | 201 | | ![pin](./pin.png) | 202 | | :------------------------------------------: | 203 | | 图：SD 卡（左）与 microSD 卡（右）的引脚定义 | 204 | 205 | 　 206 | 207 | ## 文件系统 208 | 209 | SD卡本身只是一大块线性的数据存储空间，分为多个扇区 (sector)，每个扇区 512 字节，扇区0的地址范围为 0x00000000\~0x000001FF，扇区1的地址范围为 0x00000200\~0x000003FF，以此类推……。底层的读取和写入操作都以扇区为单位。为了在这片线性的存储空间中组织磁盘分区和文件，人们规定了复杂的数据结构——文件系统，SD卡最常用的文件系统是 FAT16 和 FAT32 。 210 | 211 | 为了从 SD 卡中读取文件数据，本库分为两个功能模块： 212 | 213 | - 按照 SD 总线标准操控 SD 总线，指定扇区号，读取扇区。 214 | - 在能够读取扇区的基础上，解析文件系统，也就是给定文件名，找到文件所在的位置和长度。实际上，文件可能不是连续存储的（被拆成多块放在不同扇区），本库会正确地处理这种情况。 215 | 216 | 　 217 | 218 | 219 | # 如何调用本模块 220 | 221 | RTL 文件夹中的 sd_file_reader.v 是 SD卡文件读取器的顶层模块，它的定义如下： 222 | 223 | ```verilog 224 | module sd_file_reader #( 225 | parameter FILE_NAME_LEN = 11 , // valid length of FILE_NAME (in bytes) 226 | parameter [52*8-1:0] FILE_NAME = "example.txt", // file to read, ignore Upper and Lower Case 227 | // For example, if you want to read a file named HeLLo123.txt in the SD card, 228 | // this parameter can be hello123.TXT, HELLO123.txt or HEllo123.Txt 229 | parameter [2:0] CLK_DIV = 3'd2, // when clk = 0~ 25MHz , set CLK_DIV = 3'd1, 230 | // when clk = 25~ 50MHz , set CLK_DIV = 3'd2, 231 | // when clk = 50~100MHz , set CLK_DIV = 3'd3, 232 | // when clk = 100~200MHz , set CLK_DIV = 3'd4, 233 | // ...... 234 | parameter SIMULATE = 0 235 | ) ( 236 | // rstn active-low, 1:working, 0:reset 237 | input wire rstn, 238 | // clock 239 | input wire clk, 240 | // SDcard signals (connect to SDcard), this design do not use sddat1~sddat3. 241 | output wire sdclk, 242 | inout sdcmd, 243 | input wire sddat0, // FPGA only read SDDAT signal but never drive it 244 | // status output (optional for user) 245 | output wire [3:0] card_stat, // show the sdcard initialize status 246 | output wire [1:0] card_type, // 0=UNKNOWN , 1=SDv1 , 2=SDv2 , 3=SDHCv2 247 | output wire [1:0] filesystem_type, // 0=UNASSIGNED , 1=UNKNOWN , 2=FAT16 , 3=FAT32 248 | output reg file_found, // 0=file not found, 1=file found 249 | // file content data output (sync with clk) 250 | output reg outen, // when outen=1, a byte of file content is read out from outbyte 251 | output reg [7:0] outbyte // a byte of file content 252 | ); 253 | ``` 254 | 255 | 其中： 256 | 257 | - `FILE_NAME` 指定要读的目标文件名。 258 | - 需要在 `FILE_NAME_LEN` 指定文件名的长度 (字节数量) ，例如 "example.txt" 的长度为 11。 259 | - `CLK_DIV` 是时钟分频系数，它的取值需要根据你提供的 clk 时钟频率来决定（详见代码注释）。 260 | - `SIMULATE` 是仿真加速选项。**平常要设为 `0` **。只有仿真时才可以设 为 `1` 来加速 SD 卡初始化进度，防止仿真占用过多时间。 261 | - `clk` 是模块驱动时钟。 262 | - `rstn` 是复位信号，在开始工作前需要令 `rstn=0` 复位一下，然后令 `rstn=1` 释放。 263 | - `sdclk` 、 `sdcmd` 、 `sddat0` 是 SD 总线信号，需要连接到 SD 卡。 264 | - 注意到本模块只用到了 `sddat0` 而没用到 `sddat1~sddat3` ，因为 SD 卡上电会默认运行在 1bit 窄数据总线模式，可以用命令切换到 4bit 宽数据总线模式，我没有做切换，一直只用 `sddat0` 。而 `sddat1~sddat3` 需要弱上拉或强上拉到高电平（避免 SD 卡进入 SPI 总线模式）。 265 | - `card_type` 指示检测到的 SD 卡的类型：0对应未知、1对应SDv1、2对应SDv2、3对应SDHCv2。 266 | - `file_system_type` 指示检测到的 SD 卡的文件系统：1对应未知、2对应FAT16、3对应FAT32。 267 | - `file_found` 指示是否找到目标文件：0代表未找到，1代表找到。 268 | - 如果找到目标文件，模块会逐个输出目标文件中的所有字节，每输出一个字节，`outen` 上就产生一个高电平脉冲，同时该字节出现在 `outbyte` 上。 269 | 270 | > :warning: 本库只使用了 sddat0 ，而不使用 sddat1\~3 （也即SD 1-bit总线模式）。在工作时需要将 sddat1\~3 持续拉高（可以在 FPGA 代码里 `assign sddat[3:1] = 3'b111;` ，或者在PCB板上使用上拉电阻），这样 SD 卡才能正常进入 SD 总线模式，否则会进入 SPI 总线模式。 271 | 272 | 　 273 | 274 | # 仿真 275 | 276 | 仿真相关的文件都在 SIM 文件夹中，其中： 277 | 278 | - sd_fake.v ：是一个 FPGA 模拟 SD 卡的代码。它来自我的另一个库：[FPGA-SDfake](https://github.com/WangXuan95/FPGA-SDfake) 。在本仿真中，我们把它当作 SD 卡仿真模型，我们用它模拟了一个具有 FAT32 系统，里面有一个 example.txt 文件的 SD 卡。它会被我们的 SD 读取器 (sd_file_reader.v) 读取。 279 | - tb_sd_file_reader.v 是仿真顶层，它会调用 sd_file_reader 读取 sd_fake 中的 example.txt 。 280 | - tb_sd_file_reader_run_iverilog.bat 是运行 iverilog 仿真的脚本。 281 | 282 | 使用 iverilog 进行仿真前，需要安装 iverilog ，见：[iverilog_usage](https://github.com/WangXuan95/WangXuan95/blob/main/iverilog_usage/iverilog_usage.md) 283 | 284 | 然后双击 tb_sd_file_reader_run_iverilog.bat 运行仿真，会运行大约几分钟。 285 | 286 | 仿真运行完后，可以打开生成的 dump.vcd 文件查看波形。 287 | 288 | 　 289 | 290 | 读取文件示例 291 | =========================== 292 | 293 | example-vivado-readfile.zip 中包含一个 vivado 工程，它运行在 [Nexys4开发板](http://www.digilent.com.cn/products/product-nexys-4-ddr-artix-7-fpga-trainer-board.html) 上（Nexys4 开发板有 microSD 卡槽，比较方便）。它会从 SD卡根目录中找到文件 example.txt 并读取其全部内容，然后用 **UART** 发送出给PC机。 294 | 295 | 按以下步骤运行该示例： 296 | 297 | 1. 准备一张 **microSD卡** 。如果是标准尺寸的SD卡（大SD卡），可以用大卡转 microSD 卡的转接板转接一下。 298 | 1. 确保卡中的文件系统是 **FAT16** 或 **FAT32** 。如果不是，则需要格式化一下。 299 | 2. 在根目录下创建 **example.txt** (文件名大小写不限) ， 在文件中随便写入一些内容。 300 | 3. 将卡插入 Nexys4 的卡槽。 301 | 4. 将 Nexys4 的USB口插在PC机上，用 **串口助手** 或 **Putty** 等软件打开对应的串口。 302 | 5. 解压 example-vivado-readfile.zip ，然后用 vivado 打开目录 example-vivado-readfile 中的工程，综合并烧录。 303 | 6. 观察到串口打印出文件内容。 304 | 7. 同时，还能看到 Nexys4 上的 LED 灯发生变化，它们指示了SD卡的类型和状态，具体含义见代码。 305 | 8. 按下 Nexys4 上的红色 CPU_RESET 按钮可以重新读取，再次打印出文件内容。 306 | 307 | 　 308 | 309 | 读取扇区示例 310 | =========================== 311 | 312 | example-vivado-readsector.zip 中包含一个 vivado 工程，它运行在 [Nexys4开发板](http://www.digilent.com.cn/products/product-nexys-4-ddr-artix-7-fpga-trainer-board.html) 上。它会从 SD卡中读取扇区0（它在文件系统中往往叫 MBR 扇区），然后用 **UART** 发送出给PC机。 313 | 314 | 按以下步骤运行该示例： 315 | 316 | 1. 准备一张 **microSD卡** 。如果是标准尺寸的SD卡（大SD卡），可以用大卡转 microSD 卡的转接板转接一下。 317 | 2. 将 Nexys4 的USB口插在PC机上，用 **串口助手** 打开对应的串口，请选择 “HEX接收” ，以十六进制的形式打印每个字节，这样我们才能看到那些 ASCII 不可打印字符。 318 | 3. 解压 example-vivado-readsector.zip ，然后用 vivado 打开目录 example-vivado-readsector 中的工程，综合并烧录。 319 | 4. 观察到串口打印出扇区0的内容。 320 | 5. 同时，还能看到 Nexys4 上的 LED 灯发生变化，它们指示了SD卡的类型和状态，具体含义见代码注释。 321 | 6. 按下 Nexys4 上的红色 CPU_RESET 按钮可以重新读取，再次打印出扇区内容。 322 | 323 | -------------------------------------------------------------------------------- /SIM/tb_sd_file_reader.v: -------------------------------------------------------------------------------- 1 | 2 | //-------------------------------------------------------------------------------------------------------- 3 | // Module : tb_sd_file_reader 4 | // Type : simulation, top 5 | // Standard: Verilog 2001 (IEEE1364-2001) 6 | // Function: testbench for sd_file_reader 7 | // connect sd_file_reader (SD-host) to sd_fake (SD-card) 8 | // sd_file_reader will read sd_fake's content 9 | //-------------------------------------------------------------------------------------------------------- 10 | 11 | `timescale 1ps/1ps 12 | 13 | module tb_sd_file_reader (); 14 | 15 | initial $dumpvars(0, tb_sd_file_reader); 16 | 17 | 18 | //-------------------------------------------------------------------------------------------------------- 19 | // clock and reset 20 | //-------------------------------------------------------------------------------------------------------- 21 | reg rstn = 1'b0; 22 | reg clk = 1'b1; 23 | always #20000 clk = ~clk; // 25MHz 24 | initial begin repeat(4) @ (posedge clk); rstn<=1'b1; end 25 | 26 | 27 | //-------------------------------------------------------------------------------------------------------- 28 | // SDIO bus 29 | //-------------------------------------------------------------------------------------------------------- 30 | wire sdclk; 31 | tri sdcmd; 32 | wire [ 3:0] sddat; 33 | 34 | 35 | //-------------------------------------------------------------------------------------------------------- 36 | // sd_file_reader data out signals 37 | //-------------------------------------------------------------------------------------------------------- 38 | wire outen; 39 | wire [ 7:0] outbyte; 40 | always @ (posedge clk) if(outen) $display("readout byte: %c", outbyte); 41 | 42 | 43 | //-------------------------------------------------------------------------------------------------------- 44 | // sd_file_reader 45 | //-------------------------------------------------------------------------------------------------------- 46 | sd_file_reader #( 47 | .FILE_NAME ( "example.txt" ), 48 | .CLK_DIV ( 1 ), 49 | .SIMULATE ( 1 ) 50 | ) sd_file_reader_i ( 51 | .rstn ( rstn ), 52 | .clk ( clk ), 53 | .sdclk ( sdclk ), 54 | .sdcmd ( sdcmd ), 55 | .sddat0 ( sddat[0] ), 56 | .card_stat ( ), 57 | .card_type ( ), 58 | .filesystem_type ( ), 59 | .file_found ( ), 60 | .outen ( outen ), 61 | .outbyte ( outbyte ) 62 | ); 63 | 64 | 65 | //-------------------------------------------------------------------------------------------------------- 66 | // sd_fake's memory interface, connect to a ROM which contains SD-card's data 67 | //-------------------------------------------------------------------------------------------------------- 68 | wire rom_req; 69 | wire [39:0] rom_addr; 70 | reg [15:0] rom_data; 71 | 72 | 73 | //-------------------------------------------------------------------------------------------------------- 74 | // monitor parsed request command on sdcmd 75 | //-------------------------------------------------------------------------------------------------------- 76 | wire show_sdcmd_en; 77 | wire [ 5:0] show_sdcmd_cmd; 78 | wire [31:0] show_sdcmd_arg; 79 | always @ (posedge sdclk) if(show_sdcmd_en) $display("sdcmd request: %2d %08x", show_sdcmd_cmd, show_sdcmd_arg); 80 | initial $display("wait for SD-card power up..."); 81 | 82 | 83 | //-------------------------------------------------------------------------------------------------------- 84 | // sd_fake 85 | //-------------------------------------------------------------------------------------------------------- 86 | sd_fake sd_fake_i ( 87 | .rstn_async ( rstn ), 88 | .sdclk ( sdclk ), 89 | .sdcmd ( sdcmd ), 90 | .sddat ( sddat ), 91 | .rdreq ( rom_req ), 92 | .rdaddr ( rom_addr ), 93 | .rddata ( rom_data ), 94 | .show_status_bits ( ), 95 | .show_sdcmd_en ( show_sdcmd_en ), 96 | .show_sdcmd_cmd ( show_sdcmd_cmd ), 97 | .show_sdcmd_arg ( show_sdcmd_arg ) 98 | ); 99 | 100 | 101 | //-------------------------------------------------------------------------------------------------------- 102 | // A ROM, contains a complete FAT32 partition data mirror 103 | //-------------------------------------------------------------------------------------------------------- 104 | always @ (posedge sdclk) 105 | if (rom_req) 106 | case (rom_addr) 107 | 40'h00000000df: rom_data <= 16'h8200; 108 | 40'h00000000e0: rom_data <= 16'h0003; 109 | 40'h00000000e1: rom_data <= 16'hd50b; 110 | 40'h00000000e2: rom_data <= 16'hade8; 111 | 40'h00000000e3: rom_data <= 16'h2000; 112 | 40'h00000000e5: rom_data <= 16'hc000; 113 | 40'h00000000e6: rom_data <= 16'h00e6; 114 | 40'h00000000ff: rom_data <= 16'haa55; 115 | 40'h0000200000: rom_data <= 16'h00eb; 116 | 40'h0000200001: rom_data <= 16'h2090; 117 | 40'h0000200002: rom_data <= 16'h2020; 118 | 40'h0000200003: rom_data <= 16'h2020; 119 | 40'h0000200004: rom_data <= 16'h2020; 120 | 40'h0000200005: rom_data <= 16'h0020; 121 | 40'h0000200006: rom_data <= 16'h4002; 122 | 40'h0000200007: rom_data <= 16'h1194; 123 | 40'h0000200008: rom_data <= 16'h0002; 124 | 40'h000020000a: rom_data <= 16'hf800; 125 | 40'h000020000c: rom_data <= 16'h003f; 126 | 40'h000020000d: rom_data <= 16'h00ff; 127 | 40'h000020000e: rom_data <= 16'h2000; 128 | 40'h0000200010: rom_data <= 16'hc000; 129 | 40'h0000200011: rom_data <= 16'h00e6; 130 | 40'h0000200012: rom_data <= 16'h0736; 131 | 40'h0000200016: rom_data <= 16'h0002; 132 | 40'h0000200018: rom_data <= 16'h0001; 133 | 40'h0000200019: rom_data <= 16'h0006; 134 | 40'h0000200020: rom_data <= 16'h0080; 135 | 40'h0000200021: rom_data <= 16'h5929; 136 | 40'h0000200022: rom_data <= 16'he22a; 137 | 40'h0000200023: rom_data <= 16'h4e19; 138 | 40'h0000200024: rom_data <= 16'h204f; 139 | 40'h0000200025: rom_data <= 16'h414e; 140 | 40'h0000200026: rom_data <= 16'h454d; 141 | 40'h0000200027: rom_data <= 16'h2020; 142 | 40'h0000200028: rom_data <= 16'h2020; 143 | 40'h0000200029: rom_data <= 16'h4146; 144 | 40'h000020002a: rom_data <= 16'h3354; 145 | 40'h000020002b: rom_data <= 16'h2032; 146 | 40'h000020002c: rom_data <= 16'h2020; 147 | 40'h00002000ff: rom_data <= 16'haa55; 148 | 40'h0000200100: rom_data <= 16'h5252; 149 | 40'h0000200101: rom_data <= 16'h4161; 150 | 40'h00002001f2: rom_data <= 16'h7272; 151 | 40'h00002001f3: rom_data <= 16'h6141; 152 | 40'h00002001f4: rom_data <= 16'h9a7b; 153 | 40'h00002001f5: rom_data <= 16'h0003; 154 | 40'h00002001f6: rom_data <= 16'h0007; 155 | 40'h00002001ff: rom_data <= 16'haa55; 156 | 40'h00002002ff: rom_data <= 16'haa55; 157 | 40'h0000200600: rom_data <= 16'h00eb; 158 | 40'h0000200601: rom_data <= 16'h2090; 159 | 40'h0000200602: rom_data <= 16'h2020; 160 | 40'h0000200603: rom_data <= 16'h2020; 161 | 40'h0000200604: rom_data <= 16'h2020; 162 | 40'h0000200605: rom_data <= 16'h0020; 163 | 40'h0000200606: rom_data <= 16'h4002; 164 | 40'h0000200607: rom_data <= 16'h1194; 165 | 40'h0000200608: rom_data <= 16'h0002; 166 | 40'h000020060a: rom_data <= 16'hf800; 167 | 40'h000020060c: rom_data <= 16'h003f; 168 | 40'h000020060d: rom_data <= 16'h00ff; 169 | 40'h000020060e: rom_data <= 16'h2000; 170 | 40'h0000200610: rom_data <= 16'hc000; 171 | 40'h0000200611: rom_data <= 16'h00e6; 172 | 40'h0000200612: rom_data <= 16'h0736; 173 | 40'h0000200616: rom_data <= 16'h0002; 174 | 40'h0000200618: rom_data <= 16'h0001; 175 | 40'h0000200619: rom_data <= 16'h0006; 176 | 40'h0000200620: rom_data <= 16'h0080; 177 | 40'h0000200621: rom_data <= 16'h5929; 178 | 40'h0000200622: rom_data <= 16'he22a; 179 | 40'h0000200623: rom_data <= 16'h4e19; 180 | 40'h0000200624: rom_data <= 16'h204f; 181 | 40'h0000200625: rom_data <= 16'h414e; 182 | 40'h0000200626: rom_data <= 16'h454d; 183 | 40'h0000200627: rom_data <= 16'h2020; 184 | 40'h0000200628: rom_data <= 16'h2020; 185 | 40'h0000200629: rom_data <= 16'h4146; 186 | 40'h000020062a: rom_data <= 16'h3354; 187 | 40'h000020062b: rom_data <= 16'h2032; 188 | 40'h000020062c: rom_data <= 16'h2020; 189 | 40'h00002006ff: rom_data <= 16'haa55; 190 | 40'h0000200700: rom_data <= 16'h5252; 191 | 40'h0000200701: rom_data <= 16'h4161; 192 | 40'h00002007f2: rom_data <= 16'h7272; 193 | 40'h00002007f3: rom_data <= 16'h6141; 194 | 40'h00002007f4: rom_data <= 16'hffff; 195 | 40'h00002007f5: rom_data <= 16'hffff; 196 | 40'h00002007f6: rom_data <= 16'hffff; 197 | 40'h00002007f7: rom_data <= 16'hffff; 198 | 40'h00002007ff: rom_data <= 16'haa55; 199 | 40'h00002008ff: rom_data <= 16'haa55; 200 | 40'h0000319400: rom_data <= 16'hfff8; 201 | 40'h0000319401: rom_data <= 16'h0fff; 202 | 40'h0000319402: rom_data <= 16'hffff; 203 | 40'h0000319403: rom_data <= 16'hffff; 204 | 40'h0000319404: rom_data <= 16'hffff; 205 | 40'h0000319405: rom_data <= 16'h0fff; 206 | 40'h0000319406: rom_data <= 16'hffff; 207 | 40'h0000319407: rom_data <= 16'h0fff; 208 | 40'h0000319408: rom_data <= 16'hffff; 209 | 40'h0000319409: rom_data <= 16'h0fff; 210 | 40'h000031940a: rom_data <= 16'hffff; 211 | 40'h000031940b: rom_data <= 16'h0fff; 212 | 40'h000031940c: rom_data <= 16'hffff; 213 | 40'h000031940d: rom_data <= 16'h0fff; 214 | 40'h000038ca00: rom_data <= 16'hfff8; 215 | 40'h000038ca01: rom_data <= 16'h0fff; 216 | 40'h000038ca02: rom_data <= 16'hffff; 217 | 40'h000038ca03: rom_data <= 16'hffff; 218 | 40'h000038ca04: rom_data <= 16'hffff; 219 | 40'h000038ca05: rom_data <= 16'h0fff; 220 | 40'h000038ca06: rom_data <= 16'hffff; 221 | 40'h000038ca07: rom_data <= 16'h0fff; 222 | 40'h000038ca08: rom_data <= 16'hffff; 223 | 40'h000038ca09: rom_data <= 16'h0fff; 224 | 40'h000038ca0a: rom_data <= 16'hffff; 225 | 40'h000038ca0b: rom_data <= 16'h0fff; 226 | 40'h000038ca0c: rom_data <= 16'hffff; 227 | 40'h000038ca0d: rom_data <= 16'h0fff; 228 | 40'h0000400000: rom_data <= 16'h2042; 229 | 40'h0000400001: rom_data <= 16'h4900; 230 | 40'h0000400002: rom_data <= 16'h6e00; 231 | 40'h0000400003: rom_data <= 16'h6600; 232 | 40'h0000400004: rom_data <= 16'h6f00; 233 | 40'h0000400005: rom_data <= 16'h0f00; 234 | 40'h0000400006: rom_data <= 16'h7200; 235 | 40'h0000400007: rom_data <= 16'h0072; 236 | 40'h0000400008: rom_data <= 16'h006d; 237 | 40'h0000400009: rom_data <= 16'h0061; 238 | 40'h000040000a: rom_data <= 16'h0074; 239 | 40'h000040000b: rom_data <= 16'h0069; 240 | 40'h000040000c: rom_data <= 16'h006f; 241 | 40'h000040000e: rom_data <= 16'h006e; 242 | 40'h0000400010: rom_data <= 16'h5301; 243 | 40'h0000400011: rom_data <= 16'h7900; 244 | 40'h0000400012: rom_data <= 16'h7300; 245 | 40'h0000400013: rom_data <= 16'h7400; 246 | 40'h0000400014: rom_data <= 16'h6500; 247 | 40'h0000400015: rom_data <= 16'h0f00; 248 | 40'h0000400016: rom_data <= 16'h7200; 249 | 40'h0000400017: rom_data <= 16'h006d; 250 | 40'h0000400018: rom_data <= 16'h0020; 251 | 40'h0000400019: rom_data <= 16'h0056; 252 | 40'h000040001a: rom_data <= 16'h006f; 253 | 40'h000040001b: rom_data <= 16'h006c; 254 | 40'h000040001c: rom_data <= 16'h0075; 255 | 40'h000040001e: rom_data <= 16'h006d; 256 | 40'h000040001f: rom_data <= 16'h0065; 257 | 40'h0000400020: rom_data <= 16'h5953; 258 | 40'h0000400021: rom_data <= 16'h5453; 259 | 40'h0000400022: rom_data <= 16'h4d45; 260 | 40'h0000400023: rom_data <= 16'h317e; 261 | 40'h0000400024: rom_data <= 16'h2020; 262 | 40'h0000400025: rom_data <= 16'h1620; 263 | 40'h0000400026: rom_data <= 16'h9200; 264 | 40'h0000400027: rom_data <= 16'h91a7; 265 | 40'h0000400028: rom_data <= 16'h4f2a; 266 | 40'h0000400029: rom_data <= 16'h4f2a; 267 | 40'h000040002b: rom_data <= 16'h91a8; 268 | 40'h000040002c: rom_data <= 16'h4f2a; 269 | 40'h000040002d: rom_data <= 16'h0003; 270 | 40'h0000400030: rom_data <= 16'h5845; 271 | 40'h0000400031: rom_data <= 16'h4d41; 272 | 40'h0000400032: rom_data <= 16'h4c50; 273 | 40'h0000400033: rom_data <= 16'h2045; 274 | 40'h0000400034: rom_data <= 16'h5854; 275 | 40'h0000400035: rom_data <= 16'h2054; 276 | 40'h0000400036: rom_data <= 16'h9418; 277 | 40'h0000400037: rom_data <= 16'h91c7; 278 | 40'h0000400038: rom_data <= 16'h4f2a; 279 | 40'h0000400039: rom_data <= 16'h4f2a; 280 | 40'h000040003b: rom_data <= 16'h91ba; 281 | 40'h000040003c: rom_data <= 16'h4f2a; 282 | 40'h000040003d: rom_data <= 16'h0006; 283 | 40'h000040003e: rom_data <= 16'h0019; 284 | 40'h0000404000: rom_data <= 16'h202e; 285 | 40'h0000404001: rom_data <= 16'h2020; 286 | 40'h0000404002: rom_data <= 16'h2020; 287 | 40'h0000404003: rom_data <= 16'h2020; 288 | 40'h0000404004: rom_data <= 16'h2020; 289 | 40'h0000404005: rom_data <= 16'h1020; 290 | 40'h0000404006: rom_data <= 16'h9200; 291 | 40'h0000404007: rom_data <= 16'h91a7; 292 | 40'h0000404008: rom_data <= 16'h4f2a; 293 | 40'h0000404009: rom_data <= 16'h4f2a; 294 | 40'h000040400b: rom_data <= 16'h91a8; 295 | 40'h000040400c: rom_data <= 16'h4f2a; 296 | 40'h000040400d: rom_data <= 16'h0003; 297 | 40'h0000404010: rom_data <= 16'h2e2e; 298 | 40'h0000404011: rom_data <= 16'h2020; 299 | 40'h0000404012: rom_data <= 16'h2020; 300 | 40'h0000404013: rom_data <= 16'h2020; 301 | 40'h0000404014: rom_data <= 16'h2020; 302 | 40'h0000404015: rom_data <= 16'h1020; 303 | 40'h0000404016: rom_data <= 16'h9200; 304 | 40'h0000404017: rom_data <= 16'h91a7; 305 | 40'h0000404018: rom_data <= 16'h4f2a; 306 | 40'h0000404019: rom_data <= 16'h4f2a; 307 | 40'h000040401b: rom_data <= 16'h91a8; 308 | 40'h000040401c: rom_data <= 16'h4f2a; 309 | 40'h0000404020: rom_data <= 16'h7442; 310 | 40'h0000404022: rom_data <= 16'hff00; 311 | 40'h0000404023: rom_data <= 16'hffff; 312 | 40'h0000404024: rom_data <= 16'hffff; 313 | 40'h0000404025: rom_data <= 16'h0fff; 314 | 40'h0000404026: rom_data <= 16'hce00; 315 | 40'h0000404027: rom_data <= 16'hffff; 316 | 40'h0000404028: rom_data <= 16'hffff; 317 | 40'h0000404029: rom_data <= 16'hffff; 318 | 40'h000040402a: rom_data <= 16'hffff; 319 | 40'h000040402b: rom_data <= 16'hffff; 320 | 40'h000040402c: rom_data <= 16'hffff; 321 | 40'h000040402e: rom_data <= 16'hffff; 322 | 40'h000040402f: rom_data <= 16'hffff; 323 | 40'h0000404030: rom_data <= 16'h5701; 324 | 40'h0000404031: rom_data <= 16'h5000; 325 | 40'h0000404032: rom_data <= 16'h5300; 326 | 40'h0000404033: rom_data <= 16'h6500; 327 | 40'h0000404034: rom_data <= 16'h7400; 328 | 40'h0000404035: rom_data <= 16'h0f00; 329 | 40'h0000404036: rom_data <= 16'hce00; 330 | 40'h0000404037: rom_data <= 16'h0074; 331 | 40'h0000404038: rom_data <= 16'h0069; 332 | 40'h0000404039: rom_data <= 16'h006e; 333 | 40'h000040403a: rom_data <= 16'h0067; 334 | 40'h000040403b: rom_data <= 16'h0073; 335 | 40'h000040403c: rom_data <= 16'h002e; 336 | 40'h000040403e: rom_data <= 16'h0064; 337 | 40'h000040403f: rom_data <= 16'h0061; 338 | 40'h0000404040: rom_data <= 16'h5057; 339 | 40'h0000404041: rom_data <= 16'h4553; 340 | 40'h0000404042: rom_data <= 16'h5454; 341 | 40'h0000404043: rom_data <= 16'h317e; 342 | 40'h0000404044: rom_data <= 16'h4144; 343 | 40'h0000404045: rom_data <= 16'h2054; 344 | 40'h0000404046: rom_data <= 16'h9500; 345 | 40'h0000404047: rom_data <= 16'h91a7; 346 | 40'h0000404048: rom_data <= 16'h4f2a; 347 | 40'h0000404049: rom_data <= 16'h4f2a; 348 | 40'h000040404b: rom_data <= 16'h91a8; 349 | 40'h000040404c: rom_data <= 16'h4f2a; 350 | 40'h000040404d: rom_data <= 16'h0004; 351 | 40'h000040404e: rom_data <= 16'h000c; 352 | 40'h0000404050: rom_data <= 16'h4742; 353 | 40'h0000404051: rom_data <= 16'h7500; 354 | 40'h0000404052: rom_data <= 16'h6900; 355 | 40'h0000404053: rom_data <= 16'h6400; 356 | 40'h0000404055: rom_data <= 16'h0f00; 357 | 40'h0000404056: rom_data <= 16'hff00; 358 | 40'h0000404057: rom_data <= 16'hffff; 359 | 40'h0000404058: rom_data <= 16'hffff; 360 | 40'h0000404059: rom_data <= 16'hffff; 361 | 40'h000040405a: rom_data <= 16'hffff; 362 | 40'h000040405b: rom_data <= 16'hffff; 363 | 40'h000040405c: rom_data <= 16'hffff; 364 | 40'h000040405e: rom_data <= 16'hffff; 365 | 40'h000040405f: rom_data <= 16'hffff; 366 | 40'h0000404060: rom_data <= 16'h4901; 367 | 40'h0000404061: rom_data <= 16'h6e00; 368 | 40'h0000404062: rom_data <= 16'h6400; 369 | 40'h0000404063: rom_data <= 16'h6500; 370 | 40'h0000404064: rom_data <= 16'h7800; 371 | 40'h0000404065: rom_data <= 16'h0f00; 372 | 40'h0000404066: rom_data <= 16'hff00; 373 | 40'h0000404067: rom_data <= 16'h0065; 374 | 40'h0000404068: rom_data <= 16'h0072; 375 | 40'h0000404069: rom_data <= 16'h0056; 376 | 40'h000040406a: rom_data <= 16'h006f; 377 | 40'h000040406b: rom_data <= 16'h006c; 378 | 40'h000040406c: rom_data <= 16'h0075; 379 | 40'h000040406e: rom_data <= 16'h006d; 380 | 40'h000040406f: rom_data <= 16'h0065; 381 | 40'h0000404070: rom_data <= 16'h4e49; 382 | 40'h0000404071: rom_data <= 16'h4544; 383 | 40'h0000404072: rom_data <= 16'h4558; 384 | 40'h0000404073: rom_data <= 16'h317e; 385 | 40'h0000404074: rom_data <= 16'h2020; 386 | 40'h0000404075: rom_data <= 16'h2020; 387 | 40'h0000404076: rom_data <= 16'h6600; 388 | 40'h0000404077: rom_data <= 16'h91a8; 389 | 40'h0000404078: rom_data <= 16'h4f2a; 390 | 40'h0000404079: rom_data <= 16'h4f2a; 391 | 40'h000040407b: rom_data <= 16'h91a9; 392 | 40'h000040407c: rom_data <= 16'h4f2a; 393 | 40'h000040407d: rom_data <= 16'h0005; 394 | 40'h000040407e: rom_data <= 16'h004c; 395 | 40'h0000408000: rom_data <= 16'h000c; 396 | 40'h0000408002: rom_data <= 16'h19b9; 397 | 40'h0000408003: rom_data <= 16'h2cb8; 398 | 40'h0000408004: rom_data <= 16'ha4d9; 399 | 40'h0000408005: rom_data <= 16'h8fea; 400 | 40'h000040c000: rom_data <= 16'h007b; 401 | 40'h000040c001: rom_data <= 16'h0038; 402 | 40'h000040c002: rom_data <= 16'h0036; 403 | 40'h000040c003: rom_data <= 16'h0037; 404 | 40'h000040c004: rom_data <= 16'h0044; 405 | 40'h000040c005: rom_data <= 16'h0033; 406 | 40'h000040c006: rom_data <= 16'h0033; 407 | 40'h000040c007: rom_data <= 16'h0031; 408 | 40'h000040c008: rom_data <= 16'h0046; 409 | 40'h000040c009: rom_data <= 16'h002d; 410 | 40'h000040c00a: rom_data <= 16'h0034; 411 | 40'h000040c00b: rom_data <= 16'h0031; 412 | 40'h000040c00c: rom_data <= 16'h0031; 413 | 40'h000040c00d: rom_data <= 16'h0036; 414 | 40'h000040c00e: rom_data <= 16'h002d; 415 | 40'h000040c00f: rom_data <= 16'h0034; 416 | 40'h000040c010: rom_data <= 16'h0038; 417 | 40'h000040c011: rom_data <= 16'h0035; 418 | 40'h000040c012: rom_data <= 16'h0039; 419 | 40'h000040c013: rom_data <= 16'h002d; 420 | 40'h000040c014: rom_data <= 16'h0039; 421 | 40'h000040c015: rom_data <= 16'h0034; 422 | 40'h000040c016: rom_data <= 16'h0046; 423 | 40'h000040c017: rom_data <= 16'h0031; 424 | 40'h000040c018: rom_data <= 16'h002d; 425 | 40'h000040c019: rom_data <= 16'h0045; 426 | 40'h000040c01a: rom_data <= 16'h0036; 427 | 40'h000040c01b: rom_data <= 16'h0032; 428 | 40'h000040c01c: rom_data <= 16'h0037; 429 | 40'h000040c01d: rom_data <= 16'h0034; 430 | 40'h000040c01e: rom_data <= 16'h0046; 431 | 40'h000040c01f: rom_data <= 16'h0032; 432 | 40'h000040c020: rom_data <= 16'h0034; 433 | 40'h000040c021: rom_data <= 16'h0030; 434 | 40'h000040c022: rom_data <= 16'h0035; 435 | 40'h000040c023: rom_data <= 16'h0043; 436 | 40'h000040c024: rom_data <= 16'h0032; 437 | 40'h000040c025: rom_data <= 16'h007d; 438 | 40'h0000410000: rom_data <= 16'h6548; 439 | 40'h0000410001: rom_data <= 16'h6c6c; 440 | 40'h0000410002: rom_data <= 16'h206f; 441 | 40'h0000410003: rom_data <= 16'h6f77; 442 | 40'h0000410004: rom_data <= 16'h6c72; 443 | 40'h0000410005: rom_data <= 16'h2164; 444 | 40'h0000410006: rom_data <= 16'h0a0d; 445 | 40'h0000410007: rom_data <= 16'h7449; 446 | 40'h0000410008: rom_data <= 16'h7720; 447 | 40'h0000410009: rom_data <= 16'h726f; 448 | 40'h000041000a: rom_data <= 16'h736b; 449 | 40'h000041000b: rom_data <= 16'h0d21; 450 | 40'h000041000c: rom_data <= 16'h000a; 451 | default: rom_data <= 16'h0000; 452 | endcase 453 | 454 | 455 | endmodule 456 | -------------------------------------------------------------------------------- /RTL/sd_file_reader.v: -------------------------------------------------------------------------------- 1 | 2 | //-------------------------------------------------------------------------------------------------------- 3 | // Module : sd_file_reader 4 | // Type : synthesizable, IP's top 5 | // Standard: Verilog 2001 (IEEE1364-2001) 6 | // Function: A SD-card host to initialize SD-card and read files 7 | // Specify a filename, sd_file_reader will read out file content 8 | // Support CardType : SDv1.1 , SDv2 or SDHCv2 9 | // Support FileSystem : FAT16 or FAT32 10 | //-------------------------------------------------------------------------------------------------------- 11 | 12 | module sd_file_reader #( 13 | parameter FILE_NAME_LEN = 11 , // length of FILE_NAME (in bytes). Since the length of "example.txt" is 11, so here is 11. 14 | parameter [52*8-1:0] FILE_NAME = "example.txt", // file name to read, ignore upper and lower case 15 | // For example, if you want to read a file named "HeLLo123.txt", this parameter can be "hello123.TXT", "HELLO123.txt" or "HEllo123.Txt" 16 | parameter [2:0] CLK_DIV = 3'd2, // when clk = 0~ 25MHz , set CLK_DIV = 3'd1, 17 | // when clk = 25~ 50MHz , set CLK_DIV = 3'd2, 18 | // when clk = 50~100MHz , set CLK_DIV = 3'd3, 19 | // when clk = 100~200MHz , set CLK_DIV = 3'd4, 20 | // ...... 21 | parameter SIMULATE = 0 // 0:normal use. 1:only for simulation 22 | ) ( 23 | // rstn active-low, 1:working, 0:reset 24 | input wire rstn, 25 | // clock 26 | input wire clk, 27 | // SDcard signals (connect to SDcard), this design do not use sddat1~sddat3. 28 | output wire sdclk, 29 | inout sdcmd, 30 | input wire sddat0, // FPGA only read SDDAT signal but never drive it 31 | // status output (optional for user) 32 | output wire [3:0] card_stat, // show the sdcard initialize status 33 | output wire [1:0] card_type, // 0=UNKNOWN , 1=SDv1 , 2=SDv2 , 3=SDHCv2 34 | output wire [1:0] filesystem_type, // 0=UNASSIGNED , 1=UNKNOWN , 2=FAT16 , 3=FAT32 35 | output reg file_found, // 0=file not found, 1=file found 36 | // file content data output (sync with clk) 37 | output reg outen, // when outen=1, a byte of file content is read out from outbyte 38 | output reg [7:0] outbyte // a byte of file content 39 | ); 40 | 41 | 42 | 43 | function [7:0] toUpperCase; 44 | input [7:0] in; 45 | begin 46 | toUpperCase = (in>=8'h61 && in<=8'h7A) ? (in & 8'b11011111) : in; 47 | end 48 | endfunction 49 | 50 | 51 | 52 | wire [52*8-1:0] FILE_NAME_UPPER; 53 | 54 | generate genvar k; 55 | for (k=0; k<52; k=k+1) begin : convert_fname_to_upper 56 | assign FILE_NAME_UPPER[k*8 +: 8] = toUpperCase( FILE_NAME[k*8 +: 8] ); 57 | end 58 | endgenerate 59 | 60 | 61 | 62 | initial file_found = 1'b0; 63 | initial {outen,outbyte} = 0; 64 | 65 | 66 | reg read_start = 1'b0; 67 | reg [31:0] read_sector_no = 0; 68 | wire read_done; 69 | 70 | wire rvalid; 71 | wire [ 8:0] raddr; 72 | wire [ 7:0] rdata; 73 | 74 | reg [31:0] rootdir_sector = 0 , rootdir_sector_t; // rootdir sector number (FAT16 only) 75 | reg [15:0] rootdir_sectorcount = 0 , rootdir_sectorcount_t; // (FAT16 only) 76 | 77 | reg [31:0] curr_cluster = 0 , curr_cluster_t; // current reading cluster number 78 | 79 | wire [ 6:0] curr_cluster_fat_offset; 80 | wire [24:0] curr_cluster_fat_no; 81 | assign {curr_cluster_fat_no,curr_cluster_fat_offset} = curr_cluster; 82 | 83 | wire [ 7:0] curr_cluster_fat_offset_fat16; 84 | wire [23:0] curr_cluster_fat_no_fat16; 85 | assign {curr_cluster_fat_no_fat16,curr_cluster_fat_offset_fat16} = curr_cluster; 86 | 87 | reg [31:0] target_cluster = 0; // target cluster number item in FAT32 table 88 | reg [15:0] target_cluster_fat16 = 16'h0; // target cluster number item in FAT16 table 89 | reg [ 7:0] cluster_sector_offset=8'h0 , cluster_sector_offset_t; // current sector number in cluster 90 | 91 | reg [31:0] file_cluster = 0; 92 | reg [31:0] file_size = 0; 93 | 94 | reg [ 7:0] cluster_size = 0 , cluster_size_t; 95 | reg [31:0] first_fat_sector_no = 0 , first_fat_sector_no_t; 96 | reg [31:0] first_data_sector_no= 0 , first_data_sector_no_t; 97 | 98 | reg search_fat = 1'b0; 99 | 100 | localparam [2:0] RESET = 3'd0, 101 | SEARCH_MBR = 3'd1, 102 | SEARCH_DBR = 3'd2, 103 | LS_ROOT_FAT16 = 3'd3, 104 | LS_ROOT_FAT32 = 3'd4, 105 | READ_A_FILE = 3'd5, 106 | DONE = 3'd6; 107 | 108 | reg [2:0] filesystem_state = RESET; 109 | 110 | localparam [1:0] UNASSIGNED = 2'd0, 111 | UNKNOWN = 2'd1, 112 | FAT16 = 2'd2, 113 | FAT32 = 2'd3; 114 | 115 | reg [1:0] filesystem = UNASSIGNED, 116 | filesystem_parsed; 117 | 118 | //enum logic [2:0] {RESET, SEARCH_MBR, SEARCH_DBR, LS_ROOT_FAT16, LS_ROOT_FAT32, READ_A_FILE, DONE} filesystem_state = RESET; 119 | //enum logic [1:0] {UNASSIGNED, UNKNOWN, FAT16, FAT32} filesystem=UNASSIGNED, filesystem_parsed; 120 | 121 | assign filesystem_type = filesystem; 122 | 123 | 124 | 125 | //---------------------------------------------------------------------------------------------------------------------- 126 | // loop variables 127 | integer ii, i; 128 | 129 | 130 | //---------------------------------------------------------------------------------------------------------------------- 131 | // store MBR or DBR fields 132 | //---------------------------------------------------------------------------------------------------------------------- 133 | reg [ 7:0] sector_content [0:511]; 134 | initial for (ii=0; ii<512; ii=ii+1) sector_content[ii] = 0; 135 | 136 | always @ (posedge clk) 137 | if (rvalid) 138 | sector_content[raddr] <= rdata; 139 | 140 | 141 | 142 | //---------------------------------------------------------------------------------------------------------------------- 143 | // parse MBR or DBR fields 144 | //---------------------------------------------------------------------------------------------------------------------- 145 | wire is_boot_sector = ( {sector_content['h1FE],sector_content['h1FF]}==16'h55AA ); 146 | wire is_dbr = sector_content[0]==8'hEB || sector_content[0]==8'hE9; 147 | wire [31:0] dbr_sector_no = {sector_content['h1C9],sector_content['h1C8],sector_content['h1C7],sector_content['h1C6]}; 148 | wire [15:0] bytes_per_sector = {sector_content['hC],sector_content['hB]}; 149 | wire [ 7:0] sector_per_cluster = sector_content['hD]; 150 | wire [15:0] resv_sectors = {sector_content['hF],sector_content['hE]}; 151 | wire [ 7:0] number_of_fat = sector_content['h10]; 152 | wire [15:0] rootdir_itemcount = {sector_content['h12],sector_content['h11]}; // root dir item count (FAT16 Only) 153 | 154 | reg [31:0] sectors_per_fat = 0; 155 | reg [31:0] root_cluster = 0; 156 | 157 | always @ (*) begin 158 | sectors_per_fat = {16'h0, sector_content['h17], sector_content['h16]}; 159 | root_cluster = 0; 160 | if(sectors_per_fat>0) begin // FAT16 case 161 | filesystem_parsed = FAT16; 162 | end else if(sector_content['h56]==8'h32) begin // FAT32 case 163 | filesystem_parsed = FAT32; 164 | sectors_per_fat = {sector_content['h27],sector_content['h26],sector_content['h25],sector_content['h24]}; 165 | root_cluster = {sector_content['h2F],sector_content['h2E],sector_content['h2D],sector_content['h2C]}; 166 | end else begin // Unknown FileSystem 167 | filesystem_parsed = UNKNOWN; 168 | end 169 | end 170 | 171 | 172 | 173 | //---------------------------------------------------------------------------------------------------------------------- 174 | // main FSM 175 | //---------------------------------------------------------------------------------------------------------------------- 176 | always @ (posedge clk or negedge rstn) 177 | if(~rstn) begin 178 | read_start <= 1'b0; 179 | read_sector_no <= 0; 180 | filesystem_state <= RESET; 181 | filesystem <= UNASSIGNED; 182 | search_fat <= 1'b0; 183 | cluster_size <= 8'h0; 184 | first_fat_sector_no <= 0; 185 | first_data_sector_no <= 0; 186 | curr_cluster <= 0; 187 | cluster_sector_offset <= 8'h0; 188 | rootdir_sector <= 0; 189 | rootdir_sectorcount <= 16'h0; 190 | end else begin 191 | cluster_size_t = cluster_size; 192 | first_fat_sector_no_t = first_fat_sector_no; 193 | first_data_sector_no_t = first_data_sector_no; 194 | curr_cluster_t = curr_cluster; 195 | cluster_sector_offset_t = cluster_sector_offset; 196 | rootdir_sector_t = rootdir_sector; 197 | rootdir_sectorcount_t = rootdir_sectorcount; 198 | 199 | read_start <= 1'b0; 200 | 201 | if (read_done) begin 202 | case(filesystem_state) 203 | SEARCH_MBR : if(is_boot_sector) begin 204 | filesystem_state <= SEARCH_DBR; 205 | if(~is_dbr) read_sector_no <= dbr_sector_no; 206 | end else begin 207 | read_sector_no <= read_sector_no + 1; 208 | end 209 | SEARCH_DBR : if(is_boot_sector && is_dbr ) begin 210 | if(bytes_per_sector!=16'd512) begin 211 | filesystem_state <= DONE; 212 | end else begin 213 | filesystem <= filesystem_parsed; 214 | if(filesystem_parsed==FAT16) begin 215 | cluster_size_t = sector_per_cluster; 216 | first_fat_sector_no_t = read_sector_no + resv_sectors; 217 | 218 | rootdir_sectorcount_t = rootdir_itemcount / (16'd512/16'd32); 219 | rootdir_sector_t = first_fat_sector_no_t + sectors_per_fat * number_of_fat; 220 | first_data_sector_no_t= rootdir_sector_t + rootdir_sectorcount_t - cluster_size_t*2; 221 | 222 | cluster_sector_offset_t = 8'h0; 223 | read_sector_no <= rootdir_sector_t + cluster_sector_offset_t; 224 | filesystem_state <= LS_ROOT_FAT16; 225 | end else if(filesystem_parsed==FAT32) begin 226 | cluster_size_t = sector_per_cluster; 227 | first_fat_sector_no_t = read_sector_no + resv_sectors; 228 | 229 | first_data_sector_no_t= first_fat_sector_no_t + sectors_per_fat * number_of_fat - cluster_size_t * 2; 230 | 231 | curr_cluster_t = root_cluster; 232 | cluster_sector_offset_t = 8'h0; 233 | read_sector_no <= first_data_sector_no_t + cluster_size_t * curr_cluster_t + cluster_sector_offset_t; 234 | filesystem_state <= LS_ROOT_FAT32; 235 | end else begin 236 | filesystem_state <= DONE; 237 | end 238 | end 239 | end 240 | LS_ROOT_FAT16 : if(file_found) begin 241 | curr_cluster_t = file_cluster; 242 | cluster_sector_offset_t = 8'h0; 243 | read_sector_no <= first_data_sector_no_t + cluster_size_t * curr_cluster_t + cluster_sector_offset_t; 244 | filesystem_state <= READ_A_FILE; 245 | end else if(cluster_sector_offset_t=16'hFFF0 || target_cluster_fat16<16'h2) begin 290 | filesystem_state <= DONE; // read to the end of file, done 291 | end else begin 292 | curr_cluster_t = {16'h0,target_cluster_fat16}; 293 | read_sector_no <= first_data_sector_no_t + cluster_size_t * curr_cluster_t + cluster_sector_offset_t; 294 | end 295 | end else begin 296 | if(target_cluster=='h0FFF_FFFF || target_cluster=='h0FFF_FFF8 || target_cluster=='hFFFF_FFFF || target_cluster<2) begin 297 | filesystem_state <= DONE; // read to the end of file, done 298 | end else begin 299 | curr_cluster_t = target_cluster; 300 | read_sector_no <= first_data_sector_no_t + cluster_size_t * curr_cluster_t + cluster_sector_offset_t; 301 | end 302 | end 303 | end 304 | endcase 305 | end else begin 306 | case (filesystem_state) 307 | RESET : filesystem_state <= SEARCH_MBR; 308 | SEARCH_MBR : read_start <= 1'b1; 309 | SEARCH_DBR : read_start <= 1'b1; 310 | LS_ROOT_FAT16 : read_start <= 1'b1; 311 | LS_ROOT_FAT32 : read_start <= 1'b1; 312 | READ_A_FILE : read_start <= 1'b1; 313 | //DONE : $finish; 314 | endcase 315 | end 316 | 317 | cluster_size <= cluster_size_t; 318 | first_fat_sector_no <= first_fat_sector_no_t; 319 | first_data_sector_no <= first_data_sector_no_t; 320 | curr_cluster <= curr_cluster_t; 321 | cluster_sector_offset <= cluster_sector_offset_t; 322 | rootdir_sector <= rootdir_sector_t; 323 | rootdir_sectorcount <= rootdir_sectorcount_t; 324 | end 325 | 326 | 327 | generate if (SIMULATE) begin 328 | always @ (posedge clk) 329 | if (read_done) begin 330 | end else begin 331 | if (filesystem_state == DONE) $finish; // only for finish simulation, will be ignore when synthesize 332 | end 333 | end endgenerate 334 | 335 | 336 | 337 | 338 | //---------------------------------------------------------------------------------------------------------------------- 339 | // capture data in FAT table 340 | //---------------------------------------------------------------------------------------------------------------------- 341 | always @ (posedge clk or negedge rstn) begin 342 | if(~rstn) begin 343 | target_cluster <= 0; 344 | target_cluster_fat16 <= 16'h0; 345 | end else begin 346 | if(search_fat && rvalid) begin 347 | if(filesystem==FAT16) begin 348 | if(raddr[8:1]==curr_cluster_fat_offset_fat16) 349 | target_cluster_fat16[8*raddr[0] +: 8] <= rdata; 350 | end else if(filesystem==FAT32) begin 351 | if(raddr[8:2]==curr_cluster_fat_offset) 352 | target_cluster[8*raddr[1:0] +: 8] <= rdata; 353 | end 354 | end 355 | end 356 | end 357 | 358 | 359 | sd_reader #( 360 | .CLK_DIV ( CLK_DIV ), 361 | .SIMULATE ( SIMULATE ) 362 | ) u_sd_reader ( 363 | .rstn ( rstn ), 364 | .clk ( clk ), 365 | .sdclk ( sdclk ), 366 | .sdcmd ( sdcmd ), 367 | .sddat0 ( sddat0 ), 368 | .card_type ( card_type ), 369 | .card_stat ( card_stat ), 370 | .rstart ( read_start ), 371 | .rsector ( read_sector_no ), 372 | .rbusy ( ), 373 | .rdone ( read_done ), 374 | .outen ( rvalid ), 375 | .outaddr ( raddr ), 376 | .outbyte ( rdata ) 377 | ); 378 | 379 | 380 | 381 | //---------------------------------------------------------------------------------------------------------------------- 382 | // parse root dir 383 | //---------------------------------------------------------------------------------------------------------------------- 384 | reg fready = 1'b0; // a file is find when fready = 1 385 | reg [ 7:0] fnamelen = 0; 386 | reg [15:0] fcluster = 0; 387 | reg [31:0] fsize = 0; 388 | reg [ 7:0] fname [0:51]; 389 | reg [ 7:0] file_name [0:51]; 390 | reg isshort=1'b0, islongok=1'b0, islong=1'b0, longvalid=1'b0; 391 | reg isshort_t , islongok_t , islong_t , longvalid_t ; 392 | reg [ 5:0] longno = 6'h0 , longno_t; 393 | reg [ 7:0] lastchar = 8'h0; 394 | reg [ 7:0] fdtnamelen = 8'h0 , fdtnamelen_t; 395 | reg [ 7:0] sdtnamelen = 8'h0 , sdtnamelen_t; 396 | reg [ 7:0] file_namelen = 8'h0; 397 | reg [15:0] file_1st_cluster = 16'h0 , file_1st_cluster_t; 398 | reg [31:0] file_1st_size = 0 , file_1st_size_t; 399 | 400 | initial for(i=0;i<52;i=i+1) begin file_name[i]=8'h0; fname[i]=8'h0; end 401 | 402 | always @ (posedge clk or negedge rstn) begin 403 | if(~rstn) begin 404 | fready<=1'b0; fnamelen<=8'h0; file_namelen<=8'h0; 405 | fcluster<=16'h0; fsize<=0; 406 | for(i=0;i<52;i=i+1) begin file_name[i]<=8'h0; fname[i]<=8'h0; end 407 | 408 | {isshort, islongok, islong, longvalid} <= 4'b0000; 409 | 410 | longno <= 6'h0; 411 | lastchar <= 8'h0; 412 | fdtnamelen <= 8'h0; 413 | sdtnamelen <= 8'h0; 414 | file_1st_cluster <= 16'h0; 415 | file_1st_size <= 0; 416 | end else begin 417 | {isshort_t, islongok_t, islong_t, longvalid_t} = {isshort, islongok, islong, longvalid}; 418 | longno_t = longno; 419 | fdtnamelen_t = fdtnamelen; 420 | sdtnamelen_t = sdtnamelen; 421 | file_1st_cluster_t = file_1st_cluster; 422 | file_1st_size_t = file_1st_size; 423 | 424 | fready<=1'b0; fnamelen<=8'h0; 425 | for(i=0;i<52;i=i+1) fname[i]<=8'h0; 426 | fcluster<=16'h0; fsize<=0; 427 | 428 | if( rvalid && (filesystem_state==LS_ROOT_FAT16||filesystem_state==LS_ROOT_FAT32) && ~search_fat ) begin 429 | case (raddr[4:0]) 430 | 5'h1A : file_1st_cluster_t[ 0+:8] = rdata; 431 | 5'h1B : file_1st_cluster_t[ 8+:8] = rdata; 432 | 5'h1C : file_1st_size_t[ 0+:8] = rdata; 433 | 5'h1D : file_1st_size_t[ 8+:8] = rdata; 434 | 5'h1E : file_1st_size_t[16+:8] = rdata; 435 | 5'h1F : file_1st_size_t[24+:8] = rdata; 436 | endcase 437 | 438 | if(raddr[4:0]==5'h0) begin 439 | {islongok_t, isshort_t} = 2'b00; 440 | fdtnamelen_t = 8'h0; sdtnamelen_t=8'h0; 441 | 442 | if(rdata!=8'hE5 && rdata!=8'h2E && rdata!=8'h00) begin 443 | if(islong_t && longno_t==6'h1) 444 | islongok_t = 1'b1; 445 | else 446 | isshort_t = 1'b1; 447 | end 448 | 449 | if(rdata[7]==1'b0 && ~islongok_t) begin 450 | if(rdata[6]) begin 451 | {islong_t,longvalid_t} = 2'b11; 452 | longno_t = rdata[5:0]; 453 | end else if(islong_t) begin 454 | if(longno_t>6'h1 && (rdata[5:0]+6'h1==longno_t) ) begin 455 | islong_t = 1'b1; 456 | longno_t = rdata[5:0]; 457 | end else begin 458 | islong_t = 1'b0; 459 | end 460 | end else 461 | islong_t = 1'b0; 462 | end else 463 | islong_t = 1'b0; 464 | end else if(raddr[4:0]==5'hB) begin 465 | if(rdata!=8'h0F) 466 | islong_t = 1'b0; 467 | if(rdata!=8'h20) 468 | {isshort_t, islongok_t} = 2'b00; 469 | end else if(raddr[4:0]==5'h1F) begin 470 | if(islongok_t && longvalid_t || isshort_t) begin 471 | fready <= 1'b1; 472 | fnamelen <= file_namelen; 473 | for(i=0;i<52;i=i+1) fname[i] <= (i5'h0&&raddr[4:0]<5'hB || raddr[4:0]>=5'hE&&raddr[4:0]<5'h1A || raddr[4:0]>=5'h1C)begin 481 | if(raddr[4:0]<5'hB ? raddr[0] : ~raddr[0]) begin 482 | lastchar <= rdata; 483 | fdtnamelen_t = fdtnamelen_t + 8'd1; 484 | end else begin 485 | //automatic logic [15:0] unicode = {rdata,lastchar}; 486 | if({rdata,lastchar} == 16'h0000) begin 487 | file_namelen <= fdtnamelen_t-8'd1 + (longno_t-8'd1)*8'd13; 488 | end else if({rdata,lastchar} != 16'hFFFF) begin 489 | if(rdata == 8'h0) begin 490 | file_name[fdtnamelen_t-8'd1+(longno_t-8'd1)*8'd13] <= (lastchar>=8'h61 && lastchar<=8'h7A) ? lastchar&8'b11011111 : lastchar; 491 | end else begin 492 | longvalid_t = 1'b0; 493 | end 494 | end 495 | end 496 | end 497 | end 498 | 499 | if(isshort_t) begin 500 | if(raddr[4:0]<5'h8) begin 501 | if(rdata!=8'h20) begin 502 | file_name[sdtnamelen_t] <= rdata; 503 | sdtnamelen_t = sdtnamelen_t + 8'd1; 504 | end 505 | end else if(raddr[4:0]<5'hB) begin 506 | if(raddr[4:0]==5'h8) begin 507 | file_name[sdtnamelen_t] <= 8'h2E; 508 | sdtnamelen_t = sdtnamelen_t + 8'd1; 509 | end 510 | if(rdata!=8'h20) begin 511 | file_name[sdtnamelen_t] <= rdata; 512 | sdtnamelen_t = sdtnamelen_t + 8'd1; 513 | end 514 | end else if(raddr[4:0]==5'hB) begin 515 | file_namelen <= sdtnamelen_t; 516 | end 517 | end 518 | 519 | end 520 | 521 | {isshort, islongok, islong, longvalid} <= {isshort_t, islongok_t, islong_t, longvalid_t}; 522 | longno <= longno_t; 523 | fdtnamelen <= fdtnamelen_t; 524 | sdtnamelen <= sdtnamelen_t; 525 | file_1st_cluster <= file_1st_cluster_t; 526 | file_1st_size <= file_1st_size_t; 527 | end 528 | end 529 | 530 | 531 | 532 | //---------------------------------------------------------------------------------------------------------------------- 533 | // compare Target filename with Parsed filename 534 | //---------------------------------------------------------------------------------------------------------------------- 535 | always @ (posedge clk or negedge rstn) 536 | if(~rstn) begin 537 | file_found <= 1'b0; 538 | file_cluster <= 0; 539 | file_size <= 0; 540 | end else begin 541 | if (fready && fnamelen==FILE_NAME_LEN) begin 542 | file_found <= 1'b1; 543 | file_cluster <= fcluster; 544 | file_size <= fsize; 545 | for (ii=0; ii0; i=i-1) cmdcrcval = CalcCrcCMD(cmdcrcval, request[i]); 468 | end 469 | 470 | 471 | always @ (posedge sdclk or negedge rstn_sdclk_p) 472 | if(~rstn_sdclk_p) begin 473 | respstate <= WAITINGCMD; 474 | request <= 50'h3ffffffffffff; 475 | end else begin 476 | case(respstate) 477 | WAITINGCMD: 478 | if (request_pre_st==4'b1101 && request_stop) begin 479 | if(cmdcrcval==7'd0) 480 | respstate <= LOADRESP; 481 | else 482 | request <= 50'h3ffffffffffff; 483 | end else begin 484 | request <= {request[48:0], sdcmd}; 485 | end 486 | LOADRESP : 487 | respstate <= RESPING; 488 | default : //RESPING : 489 | if (response_end) begin 490 | respstate <= WAITINGCMD; 491 | request <= 50'h3ffffffffffff; 492 | end 493 | endcase 494 | end 495 | 496 | 497 | 498 | always @ (negedge sdclk or negedge rstn_sdclk_n) 499 | if(~rstn_sdclk_n) begin 500 | response_init( 0, 0, 0, 0, 0 ); 501 | data_response_stop; 502 | response_yield; 503 | data_response_yield; 504 | last_is_acmd <= 1'b0; 505 | {cardstatus_out_of_range, cardstatus_address_error, cardstatus_block_len_error, cardstatus_erase_seq_error, cardstatus_erase_param, cardstatus_wp_violation, cardstatus_card_is_locked, cardstatus_lock_unlock_failed, cardstatus_com_crc_error, cardstatus_illegal_command, cardstatus_card_ecc_failed, cardstatus_cc_error, cardstatus_error, cardstatus_rsvd1, cardstatus_csd_overwrite, cardstatus_wp_erase_skip, cardstatus_card_ecc_disabled, cardstatus_erase_reset, cardstatus_current_state, cardstatus_ready_for_data, cardstatus_rsvd2, cardstatus_app_cmd, cardstatus_rsvd3, cardstatus_ake_seq_error, cardstatus_rsvd4} = 0; 506 | widebus = 0; 507 | cmd6_invalid <= 6'h0; 508 | end else begin 509 | if(respstate==LOADRESP) begin 510 | last_is_acmd <= 1'b0; 511 | cardstatus_app_cmd = 1'b0; 512 | cardstatus_block_len_error = 1'b0; 513 | case (request_cmd) 514 | 0 : begin // GO_IDLE_STATE 515 | response_init( 0, 0 , 0 , 0 , 0 ); // there is NO RESPONSE for CMD0 516 | data_response_stop; 517 | response_yield; 518 | data_response_yield; 519 | last_is_acmd <= 1'b0; 520 | {cardstatus_out_of_range, cardstatus_address_error, cardstatus_block_len_error, cardstatus_erase_seq_error, cardstatus_erase_param, cardstatus_wp_violation, cardstatus_card_is_locked, cardstatus_lock_unlock_failed, cardstatus_com_crc_error, cardstatus_illegal_command, cardstatus_card_ecc_failed, cardstatus_cc_error, cardstatus_error, cardstatus_rsvd1, cardstatus_csd_overwrite, cardstatus_wp_erase_skip, cardstatus_card_ecc_disabled, cardstatus_erase_reset, cardstatus_current_state, cardstatus_ready_for_data, cardstatus_rsvd2, cardstatus_app_cmd, cardstatus_rsvd3, cardstatus_ake_seq_error, cardstatus_rsvd4} = 0; 521 | cardstatus_ready_for_data = 1'b1; 522 | widebus = 0; 523 | cmd6_invalid <= 6'h0; 524 | end 525 | 2 : begin // ALL_SEND_CID 526 | response_init( 1, 0 , 6'b000000 , 120 , CID_REG ); // R2 TODO: why cmd=000000 instead of 111111 ??? 527 | cardstatus_current_state = IDENT; 528 | cardstatus_illegal_command = 1'b0; 529 | end 530 | 3 : begin // SEND_RELATIVE_ADDR(send RCA) 531 | response_init( 1, 0 , request_cmd , 32 , {RCA_REG,cardstatus_short} ); // R6 532 | cardstatus_current_state = STBY; 533 | cardstatus_illegal_command = 1'b0; 534 | end 535 | 4 : if(request_arg[15:0] == 16'h0) begin // SET_DSR 536 | response_init( 0, 0 , 0 , 0 , 0 ); // there is NO RESPONSE for CMD4 537 | cardstatus_illegal_command = 1'b0; 538 | end 539 | 6 : if(last_is_acmd && cardstatus_current_state==TRAN) begin // SET_BUS_WIDTH 540 | cardstatus_app_cmd = 1'b1; 541 | response_init( 1, 0 , request_cmd , 32 , cardstatus ); 542 | widebus = request_arg[1]; 543 | cardstatus_illegal_command = 1'b0; 544 | end else if(cardstatus_current_state==TRAN) begin // SWITCH_FUNC 545 | response_init( 1, 0 , request_cmd , 32 , cardstatus ); 546 | cmd6_invalid[0] <= ( request_arg[0*4+:4]!=4'h0 && request_arg[0*4+:4]!=4'hf ); 547 | cmd6_invalid[1] <= ( request_arg[1*4+:4]!=4'h0 && request_arg[1*4+:4]!=4'hf ); 548 | cmd6_invalid[2] <= ( request_arg[2*4+:4]!=4'h0 && request_arg[2*4+:4]!=4'hf ); 549 | cmd6_invalid[3] <= ( request_arg[3*4+:4]!=4'h0 && request_arg[3*4+:4]!=4'hf ); 550 | cmd6_invalid[4] <= ( request_arg[4*4+:4]!=4'h0 && request_arg[4*4+:4]!=4'hf ); 551 | cmd6_invalid[5] <= ( request_arg[5*4+:4]!=4'h0 && request_arg[5*4+:4]!=4'hf ); 552 | data_response_cmd6stat_init; 553 | cardstatus_illegal_command = 1'b0; 554 | end 555 | 7 : if(request_arg[31:16] == RCA_REG) begin // SELECT_CARD 556 | response_init( 1, 0 , request_cmd , 32 , cardstatus ); 557 | cardstatus_current_state = TRAN; 558 | cardstatus_illegal_command = 1'b0; 559 | end else begin // DESELECT_CARD 560 | cardstatus_current_state = STBY; 561 | cardstatus_illegal_command = 1'b0; 562 | end 563 | 8 : begin // SEND_IF_COND 564 | response_init( 1, 0 , request_cmd , 32 , {24'd1,request_arg[7:0]} ); 565 | cardstatus_illegal_command = 1'b0; 566 | end 567 | 9 : if(request_arg[31:16]==RCA_REG) begin // SEND_CSD 568 | response_init( 1, 0 , 6'b000000 , 120 , CSD_REG ); 569 | cardstatus_illegal_command = 1'b0; 570 | end 571 | 10 : if(request_arg[31:16]==RCA_REG) begin // SEND_CID 572 | response_init( 1, 0 , 6'b000000 , 120 , CID_REG ); 573 | cardstatus_illegal_command = 1'b0; 574 | end 575 | 12 : if(cardstatus_current_state==DATA) begin // STOP_TRANSMISSION 576 | response_init( 1, 0 , request_cmd , 32 , cardstatus ); 577 | data_response_stop; 578 | cardstatus_illegal_command = 1'b0; 579 | end 580 | 13 : if(last_is_acmd) begin // SEND_SD_STATUS 581 | if(cardstatus_current_state==TRAN) begin 582 | cardstatus_app_cmd = 1'b1; 583 | response_init( 1, 0 , request_cmd , 32 , cardstatus ); 584 | data_response_sdstat_init; 585 | cardstatus_illegal_command = 1'b0; 586 | end 587 | end else if(request_arg[31:16]==RCA_REG) begin // SEND_STATUS 588 | response_init( 1, 0 , request_cmd , 32 , cardstatus ); 589 | cardstatus_illegal_command = 1'b0; 590 | end 591 | 15 : if(request_arg[31:16]==RCA_REG) begin // GO_INACTIVE_STATE 592 | response_init( 0, 0 , 0 , 0 , 0 ); 593 | cardstatus_current_state = IDLE; 594 | cardstatus_illegal_command = 1'b0; 595 | end 596 | 16 : if(cardstatus_current_state==TRAN) begin // SET_BLOCKLEN 597 | if(request_arg > 512) cardstatus_block_len_error = 1'b1; 598 | response_init( 1, 0 , request_cmd , 32 , cardstatus ); 599 | cardstatus_illegal_command = 1'b0; 600 | end 601 | 17 : if(cardstatus_current_state==TRAN) begin // READ_SINGLE_BLOCK 602 | response_init( 1, 0 , request_cmd , 32 , cardstatus ); 603 | data_response_init(request_arg, 0); 604 | cardstatus_illegal_command = 1'b0; 605 | end 606 | 18 : if(cardstatus_current_state==TRAN) begin // READ_MULTIPLE_BLOCK 607 | response_init( 1, 0 , request_cmd , 32 , cardstatus ); 608 | data_response_init(request_arg, 1); 609 | cardstatus_illegal_command = 1'b0; 610 | end 611 | 55 : if(request_arg[31:16]==16'd0 || request_arg[31:16]==RCA_REG) begin // APP_CMD 612 | last_is_acmd <= 1'b1; 613 | cardstatus_app_cmd = 1'b1; 614 | response_init( 1, 0 , request_cmd , 32 , cardstatus ); 615 | cardstatus_illegal_command = 1'b0; 616 | end 617 | 41 : if(last_is_acmd) begin // SD_SEND_OP_COND 618 | cardstatus_app_cmd = 1'b1; 619 | response_init( 1, 1 , 6'b111111 , 32 , OCR_REG ); 620 | cardstatus_illegal_command = 1'b0; 621 | end 622 | 42 : if(last_is_acmd) begin // SET_CLR_CARD_DETECT 623 | cardstatus_app_cmd = 1'b1; 624 | response_init( 1, 0 , request_cmd , 32 , cardstatus ); 625 | cardstatus_illegal_command = 1'b0; 626 | end 627 | 51 : if(last_is_acmd && cardstatus_current_state==TRAN) begin // SEND_SCR 628 | cardstatus_app_cmd = 1'b1; 629 | response_init( 1, 0 , request_cmd , 32 , cardstatus ); 630 | data_response_scr_init; 631 | cardstatus_illegal_command = 1'b0; 632 | end 633 | default : begin // undefined CMD 634 | response_init( 0, 0 , 0 , 0 , 0 ); 635 | cardstatus_illegal_command = 1'b1; 636 | end 637 | endcase 638 | end 639 | response_yield; 640 | data_response_yield; 641 | end 642 | 643 | 644 | always @ (posedge sdclk or negedge rstn_sdclk_p) 645 | if(~rstn_sdclk_p) begin 646 | show_sdcmd_en <= 1'b0; 647 | show_sdcmd_cmd <= 0; 648 | show_sdcmd_arg <= 0; 649 | end else begin 650 | show_sdcmd_en <= 1'b0; 651 | if (respstate == LOADRESP) begin 652 | show_sdcmd_en <= 1'b1; 653 | show_sdcmd_cmd <= request_cmd; 654 | show_sdcmd_arg <= request_arg; 655 | end 656 | end 657 | 658 | endmodule 659 | -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | GNU GENERAL PUBLIC LICENSE 2 | Version 3, 29 June 2007 3 | 4 | Copyright (C) 2007 Free Software Foundation, Inc. 5 | Everyone is permitted to copy and distribute verbatim copies 6 | of this license document, but changing it is not allowed. 7 | 8 | Preamble 9 | 10 | The GNU General Public License is a free, copyleft license for 11 | software and other kinds of works. 12 | 13 | The licenses for most software and other practical works are designed 14 | to take away your freedom to share and change the works. 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Interpretation of Sections 15 and 16. 613 | 614 | If the disclaimer of warranty and limitation of liability provided 615 | above cannot be given local legal effect according to their terms, 616 | reviewing courts shall apply local law that most closely approximates 617 | an absolute waiver of all civil liability in connection with the 618 | Program, unless a warranty or assumption of liability accompanies a 619 | copy of the Program in return for a fee. 620 | 621 | END OF TERMS AND CONDITIONS 622 | 623 | How to Apply These Terms to Your New Programs 624 | 625 | If you develop a new program, and you want it to be of the greatest 626 | possible use to the public, the best way to achieve this is to make it 627 | free software which everyone can redistribute and change under these terms. 628 | 629 | To do so, attach the following notices to the program. It is safest 630 | to attach them to the start of each source file to most effectively 631 | state the exclusion of warranty; and each file should have at least 632 | the "copyright" line and a pointer to where the full notice is found. 633 | 634 | 635 | Copyright (C) 636 | 637 | This program is free software: you can redistribute it and/or modify 638 | it under the terms of the GNU General Public License as published by 639 | the Free Software Foundation, either version 3 of the License, or 640 | (at your option) any later version. 641 | 642 | This program is distributed in the hope that it will be useful, 643 | but WITHOUT ANY WARRANTY; without even the implied warranty of 644 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 645 | GNU General Public License for more details. 646 | 647 | You should have received a copy of the GNU General Public License 648 | along with this program. If not, see . 649 | 650 | Also add information on how to contact you by electronic and paper mail. 651 | 652 | If the program does terminal interaction, make it output a short 653 | notice like this when it starts in an interactive mode: 654 | 655 | Copyright (C) 656 | This program comes with ABSOLUTELY NO WARRANTY; for details type `show w'. 657 | This is free software, and you are welcome to redistribute it 658 | under certain conditions; type `show c' for details. 659 | 660 | The hypothetical commands `show w' and `show c' should show the appropriate 661 | parts of the General Public License. Of course, your program's commands 662 | might be different; for a GUI interface, you would use an "about box". 663 | 664 | You should also get your employer (if you work as a programmer) or school, 665 | if any, to sign a "copyright disclaimer" for the program, if necessary. 666 | For more information on this, and how to apply and follow the GNU GPL, see 667 | . 668 | 669 | The GNU General Public License does not permit incorporating your program 670 | into proprietary programs. If your program is a subroutine library, you 671 | may consider it more useful to permit linking proprietary applications with 672 | the library. If this is what you want to do, use the GNU Lesser General 673 | Public License instead of this License. But first, please read 674 | . --------------------------------------------------------------------------------