├── .github └── workflows │ ├── docs.yaml │ ├── fpga.yaml │ ├── gds.yaml │ └── test.yaml ├── .gitignore ├── LICENSE ├── README.md ├── docs └── info.md ├── info.yaml ├── src ├── config.tcl └── project.v └── test ├── Makefile ├── README.md ├── requirements.txt ├── tb.gtkw ├── tb.v └── test.py /.github/workflows/docs.yaml: -------------------------------------------------------------------------------- 1 | name: docs 2 | 3 | on: 4 | push: 5 | workflow_dispatch: 6 | 7 | jobs: 8 | docs: 9 | runs-on: ubuntu-latest 10 | steps: 11 | - name: Checkout repo 12 | uses: actions/checkout@v4 13 | with: 14 | submodules: recursive 15 | 16 | - name: Build docs 17 | uses: TinyTapeout/tt-gds-action/docs@tt07 18 | -------------------------------------------------------------------------------- /.github/workflows/fpga.yaml: -------------------------------------------------------------------------------- 1 | name: fpga 2 | 3 | on: 4 | push: 5 | workflow_dispatch: 6 | 7 | jobs: 8 | fpga: 9 | runs-on: ubuntu-latest 10 | steps: 11 | - name: checkout repo 12 | uses: actions/checkout@v4 13 | with: 14 | submodules: recursive 15 | 16 | - name: FPGA bitstream for TT ASIC Sim (ICE40UP5K) 17 | uses: TinyTapeout/tt-gds-action/fpga/ice40up5k@tt07 18 | -------------------------------------------------------------------------------- /.github/workflows/gds.yaml: -------------------------------------------------------------------------------- 1 | name: gds 2 | 3 | on: 4 | push: 5 | workflow_dispatch: 6 | 7 | jobs: 8 | gds: 9 | runs-on: ubuntu-latest 10 | steps: 11 | - name: checkout repo 12 | uses: actions/checkout@v4 13 | with: 14 | submodules: recursive 15 | 16 | - name: Build GDS 17 | uses: TinyTapeout/tt-gds-action@tt07 18 | 19 | precheck: 20 | needs: gds 21 | runs-on: ubuntu-latest 22 | steps: 23 | - name: Run Tiny Tapeout Precheck 24 | uses: TinyTapeout/tt-gds-action/precheck@tt07 25 | 26 | gl_test: 27 | needs: gds 28 | runs-on: ubuntu-latest 29 | steps: 30 | - name: checkout repo 31 | uses: actions/checkout@v4 32 | with: 33 | submodules: recursive 34 | 35 | - name: GL test 36 | uses: TinyTapeout/tt-gds-action/gl_test@tt07 37 | 38 | viewer: 39 | needs: gds 40 | runs-on: ubuntu-latest 41 | permissions: 42 | pages: write # to deploy to Pages 43 | id-token: write # to verify the deployment originates from an appropriate source 44 | steps: 45 | - uses: TinyTapeout/tt-gds-action/viewer@tt07 46 | -------------------------------------------------------------------------------- /.github/workflows/test.yaml: -------------------------------------------------------------------------------- 1 | name: test 2 | on: [push, workflow_dispatch] 3 | jobs: 4 | test: 5 | runs-on: ubuntu-latest 6 | steps: 7 | - name: Checkout repo 8 | uses: actions/checkout@v4 9 | with: 10 | submodules: recursive 11 | 12 | - name: Install iverilog 13 | shell: bash 14 | run: sudo apt-get update && sudo apt-get install -y iverilog 15 | 16 | # Set Python up and install cocotb 17 | - name: Setup python 18 | uses: actions/setup-python@v5 19 | with: 20 | python-version: '3.11' 21 | 22 | - name: Install Python packages 23 | shell: bash 24 | run: pip install -r test/requirements.txt 25 | 26 | - name: Run tests 27 | run: | 28 | cd test 29 | make clean 30 | make 31 | # make will return success even if the test fails, so check for failure in the results.xml 32 | ! grep failure results.xml 33 | 34 | - name: Test Summary 35 | uses: test-summary/action@v2.3 36 | with: 37 | paths: "test/results.xml" 38 | if: always() 39 | 40 | - name: upload vcd 41 | if: success() || failure() 42 | uses: actions/upload-artifact@v4 43 | with: 44 | name: test-vcd 45 | path: | 46 | test/tb.vcd 47 | test/result.xml 48 | -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | .DS_Store 2 | .idea 3 | .vscode 4 | *.vcd 5 | runs 6 | tt_submission 7 | src/user_config.tcl 8 | test/sim_build 9 | test/__pycache__/ 10 | test/results.xml 11 | test/gate_level_netlist.v 12 | -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | Apache License 2 | Version 2.0, January 2004 3 | http://www.apache.org/licenses/ 4 | 5 | TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION 6 | 7 | 1. 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We also recommend that a 185 | file or class name and description of purpose be included on the 186 | same "printed page" as the copyright notice for easier 187 | identification within third-party archives. 188 | 189 | Copyright [yyyy] [name of copyright owner] 190 | 191 | Licensed under the Apache License, Version 2.0 (the "License"); 192 | you may not use this file except in compliance with the License. 193 | You may obtain a copy of the License at 194 | 195 | http://www.apache.org/licenses/LICENSE-2.0 196 | 197 | Unless required by applicable law or agreed to in writing, software 198 | distributed under the License is distributed on an "AS IS" BASIS, 199 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 200 | See the License for the specific language governing permissions and 201 | limitations under the License. 202 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | ![](../../workflows/gds/badge.svg) ![](../../workflows/docs/badge.svg) ![](../../workflows/test/badge.svg) ![](../../workflows/fpga/badge.svg) 2 | 3 | # Tiny Tapeout Verilog Project Template 4 | 5 | - [Read the documentation for project](docs/info.md) 6 | 7 | ## What is Tiny Tapeout? 8 | 9 | Tiny Tapeout is an educational project that aims to make it easier and cheaper than ever to get your digital and analog designs manufactured on a real chip. 10 | 11 | To learn more and get started, visit https://tinytapeout.com. 12 | 13 | ## Set up your Verilog project 14 | 15 | 1. Add your Verilog files to the `src` folder. 16 | 2. Edit the [info.yaml](info.yaml) and update information about your project, paying special attention to the `source_files` and `top_module` properties. If you are upgrading an existing Tiny Tapeout project, check out our [online info.yaml migration tool](https://tinytapeout.github.io/tt-yaml-upgrade-tool/). 17 | 3. Edit [docs/info.md](docs/info.md) and add a description of your project. 18 | 4. Adapt the testbench to your design. See [test/README.md](test/README.md) for more information. 19 | 20 | The GitHub action will automatically build the ASIC files using [OpenLane](https://www.zerotoasiccourse.com/terminology/openlane/). 21 | 22 | ## Enable GitHub actions to build the results page 23 | 24 | - [Enabling GitHub Pages](https://tinytapeout.com/faq/#my-github-action-is-failing-on-the-pages-part) 25 | 26 | ## Resources 27 | 28 | - [FAQ](https://tinytapeout.com/faq/) 29 | - [Digital design lessons](https://tinytapeout.com/digital_design/) 30 | - [Learn how semiconductors work](https://tinytapeout.com/siliwiz/) 31 | - [Join the community](https://tinytapeout.com/discord) 32 | - [Build your design locally](https://docs.google.com/document/d/1aUUZ1jthRpg4QURIIyzlOaPWlmQzr-jBn3wZipVUPt4) 33 | 34 | ## What next? 35 | 36 | - [Submit your design to the next shuttle](https://app.tinytapeout.com/). 37 | - Edit [this README](README.md) and explain your design, how it works, and how to test it. 38 | - Share your project on your social network of choice: 39 | - LinkedIn [#tinytapeout](https://www.linkedin.com/search/results/content/?keywords=%23tinytapeout) [@TinyTapeout](https://www.linkedin.com/company/100708654/) 40 | - Mastodon [#tinytapeout](https://chaos.social/tags/tinytapeout) [@matthewvenn](https://chaos.social/@matthewvenn) 41 | - X (formerly Twitter) [#tinytapeout](https://twitter.com/hashtag/tinytapeout) [@tinytapeout](https://twitter.com/tinytapeout) 42 | -------------------------------------------------------------------------------- /docs/info.md: -------------------------------------------------------------------------------- 1 | 9 | 10 | ## How it works 11 | 12 | Explain how your project works 13 | 14 | ## How to test 15 | 16 | Explain how to use your project 17 | 18 | ## External hardware 19 | 20 | List external hardware used in your project (e.g. PMOD, LED display, etc), if any 21 | -------------------------------------------------------------------------------- /info.yaml: -------------------------------------------------------------------------------- 1 | # Tiny Tapeout project information 2 | project: 3 | title: "" # Project title 4 | author: "" # Your name 5 | discord: "" # Your discord username, for communication and automatically assigning you a Tapeout role (optional) 6 | description: "" # One line description of what your project does 7 | language: "Verilog" # other examples include SystemVerilog, Amaranth, VHDL, etc 8 | clock_hz: 0 # Clock frequency in Hz (or 0 if not applicable) 9 | 10 | # How many tiles your design occupies? A single tile is about 167x108 uM. 11 | tiles: "1x1" # Valid values: 1x1, 1x2, 2x2, 3x2, 4x2, 6x2 or 8x2 12 | 13 | # Your top module name must start with "tt_um_". Make it unique by including your github username: 14 | top_module: "tt_um_example" 15 | 16 | # List your project's source files here. Source files must be in ./src and you must list each source file separately, one per line: 17 | source_files: 18 | - "project.v" 19 | 20 | # The pinout of your project. Leave unused pins blank. DO NOT delete or add any pins. 21 | pinout: 22 | # Inputs 23 | ui[0]: "" 24 | ui[1]: "" 25 | ui[2]: "" 26 | ui[3]: "" 27 | ui[4]: "" 28 | ui[5]: "" 29 | ui[6]: "" 30 | ui[7]: "" 31 | 32 | # Outputs 33 | uo[0]: "" 34 | uo[1]: "" 35 | uo[2]: "" 36 | uo[3]: "" 37 | uo[4]: "" 38 | uo[5]: "" 39 | uo[6]: "" 40 | uo[7]: "" 41 | 42 | # Bidirectional pins 43 | uio[0]: "" 44 | uio[1]: "" 45 | uio[2]: "" 46 | uio[3]: "" 47 | uio[4]: "" 48 | uio[5]: "" 49 | uio[6]: "" 50 | uio[7]: "" 51 | 52 | # Do not change! 53 | yaml_version: 6 54 | -------------------------------------------------------------------------------- /src/config.tcl: -------------------------------------------------------------------------------- 1 | # DO NOT EDIT THIS FILE before reading the comments below: 2 | 3 | # This is the default configuration for Tiny Tapeout projects. It should fit most designs. 4 | # If you change it, please make sure you understand what you are doing. We are not responsible 5 | # if your project fails because of a bad configuration. 6 | 7 | # !!! DO NOT EDIT THIS FILE unless you know what you are doing !!! 8 | 9 | # If you get stuck with this config, please open an issue or get in touch via the discord. 10 | 11 | # Here are some of the variables you may want to change: 12 | 13 | # PL_TARGET_DENSITY - You can increase this if Global Placement fails with error GPL-0302. 14 | # Users have reported that values up to 0.8 worked well for them. 15 | set ::env(PL_TARGET_DENSITY) 0.6 16 | 17 | # CLOCK_PERIOD - Increase this in case you are getting setup time violations. 18 | # The value is in nanoseconds, so 20ns == 50MHz. 19 | set ::env(CLOCK_PERIOD) "20" 20 | 21 | # Hold slack margin - Increase them in case you are getting hold violations. 22 | set ::env(PL_RESIZER_HOLD_SLACK_MARGIN) 0.1 23 | set ::env(GLB_RESIZER_HOLD_SLACK_MARGIN) 0.05 24 | 25 | # RUN_LINTER, LINTER_INCLUDE_PDK_MODELS - Disabling the linter is not recommended! 26 | set ::env(RUN_LINTER) 1 27 | set ::env(LINTER_INCLUDE_PDK_MODELS) 1 28 | 29 | # If you need a custom clock configuration, read the following documentation first: 30 | # https://tinytapeout.com/faq/#how-can-i-map-an-additional-external-clock-to-one-of-the-gpios 31 | set ::env(CLOCK_PORT) {clk} 32 | 33 | # Configuration docs: https://openlane.readthedocs.io/en/latest/reference/configuration.html 34 | 35 | # !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! 36 | # !!! DO NOT CHANGE ANYTHING BELOW THIS POINT !!! 37 | # !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! 38 | 39 | # Load configuration auto-generated by tt-support-tools 40 | set script_dir [file dirname [file normalize [info script]]] 41 | source $::env(DESIGN_DIR)/user_config.tcl 42 | 43 | # Save some time 44 | set ::env(RUN_KLAYOUT_XOR) 0 45 | set ::env(RUN_KLAYOUT_DRC) 0 46 | 47 | # Don't put clock buffers on the outputs 48 | set ::env(PL_RESIZER_BUFFER_OUTPUT_PORTS) 0 49 | 50 | # Allow use of specific sky130 cells 51 | set ::env(SYNTH_READ_BLACKBOX_LIB) 1 52 | 53 | # Reduce wasted space 54 | set ::env(TOP_MARGIN_MULT) 1 55 | set ::env(BOTTOM_MARGIN_MULT) 1 56 | set ::env(LEFT_MARGIN_MULT) 6 57 | set ::env(RIGHT_MARGIN_MULT) 6 58 | 59 | # Absolute die size 60 | set ::env(FP_SIZING) absolute 61 | 62 | set ::env(PL_BASIC_PLACEMENT) {0} 63 | set ::env(GRT_ALLOW_CONGESTION) "1" 64 | 65 | set ::env(FP_IO_HLENGTH) 2 66 | set ::env(FP_IO_VLENGTH) 2 67 | 68 | # Use alternative efabless decap cells to solve LI density issue 69 | set ::env(DECAP_CELL) "\ 70 | sky130_fd_sc_hd__decap_3 \ 71 | sky130_fd_sc_hd__decap_4 \ 72 | sky130_fd_sc_hd__decap_6 \ 73 | sky130_fd_sc_hd__decap_8 \ 74 | sky130_ef_sc_hd__decap_12" 75 | 76 | # Clock 77 | set ::env(RUN_CTS) 1 78 | 79 | # Don't use power rings or met5 layer 80 | set ::env(DESIGN_IS_CORE) 0 81 | set ::env(RT_MAX_LAYER) {met4} 82 | 83 | # MAGIC_DEF_LABELS may cause issues with LVS 84 | set ::env(MAGIC_DEF_LABELS) 0 85 | -------------------------------------------------------------------------------- /src/project.v: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2024 Your Name 3 | * SPDX-License-Identifier: Apache-2.0 4 | */ 5 | 6 | `default_nettype none 7 | 8 | module tt_um_example ( 9 | input wire [7:0] ui_in, // Dedicated inputs 10 | output wire [7:0] uo_out, // Dedicated outputs 11 | input wire [7:0] uio_in, // IOs: Input path 12 | output wire [7:0] uio_out, // IOs: Output path 13 | output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output) 14 | input wire ena, // always 1 when the design is powered, so you can ignore it 15 | input wire clk, // clock 16 | input wire rst_n // reset_n - low to reset 17 | ); 18 | 19 | // All output pins must be assigned. If not used, assign to 0. 20 | assign uo_out = ui_in + uio_in; // Example: ou_out is the sum of ui_in and uio_in 21 | assign uio_out = 0; 22 | assign uio_oe = 0; 23 | 24 | // List all unused inputs to prevent warnings 25 | wire _unused = &{ena, clk, rst_n, 1'b0}; 26 | 27 | endmodule 28 | -------------------------------------------------------------------------------- /test/Makefile: -------------------------------------------------------------------------------- 1 | # Makefile 2 | # See https://docs.cocotb.org/en/stable/quickstart.html for more info 3 | 4 | # defaults 5 | SIM ?= icarus 6 | TOPLEVEL_LANG ?= verilog 7 | SRC_DIR = $(PWD)/../src 8 | PROJECT_SOURCES = project.v 9 | 10 | ifneq ($(GATES),yes) 11 | 12 | # RTL simulation: 13 | SIM_BUILD = sim_build/rtl 14 | VERILOG_SOURCES += $(addprefix $(SRC_DIR)/,$(PROJECT_SOURCES)) 15 | COMPILE_ARGS += -I$(SRC_DIR) 16 | 17 | else 18 | 19 | # Gate level simulation: 20 | SIM_BUILD = sim_build/gl 21 | COMPILE_ARGS += -DGL_TEST 22 | COMPILE_ARGS += -DFUNCTIONAL 23 | COMPILE_ARGS += -DUSE_POWER_PINS 24 | COMPILE_ARGS += -DSIM 25 | COMPILE_ARGS += -DUNIT_DELAY=\#1 26 | VERILOG_SOURCES += $(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/verilog/primitives.v 27 | VERILOG_SOURCES += $(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v 28 | 29 | # this gets copied in by the GDS action workflow 30 | VERILOG_SOURCES += $(PWD)/gate_level_netlist.v 31 | 32 | endif 33 | 34 | # Include the testbench sources: 35 | VERILOG_SOURCES += $(PWD)/tb.v 36 | TOPLEVEL = tb 37 | 38 | # MODULE is the basename of the Python test file 39 | MODULE = test 40 | 41 | # include cocotb's make rules to take care of the simulator setup 42 | include $(shell cocotb-config --makefiles)/Makefile.sim 43 | -------------------------------------------------------------------------------- /test/README.md: -------------------------------------------------------------------------------- 1 | # Sample testbench for a Tiny Tapeout project 2 | 3 | This is a sample testbench for a Tiny Tapeout project. It uses [cocotb](https://docs.cocotb.org/en/stable/) to drive the DUT and check the outputs. 4 | See below to get started or for more information, check the [website](https://tinytapeout.com/hdl/testing/). 5 | 6 | ## Setting up 7 | 8 | 1. Edit [Makefile](Makefile) and modify `PROJECT_SOURCES` to point to your Verilog files. 9 | 2. Edit [tb.v](tb.v) and replace `tt_um_example` with your module name. 10 | 11 | ## How to run 12 | 13 | To run the RTL simulation: 14 | 15 | ```sh 16 | make -B 17 | ``` 18 | 19 | To run gatelevel simulation, first harden your project and copy `../runs/wokwi/results/final/verilog/gl/{your_module_name}.v` to `gate_level_netlist.v`. 20 | 21 | Then run: 22 | 23 | ```sh 24 | make -B GATES=yes 25 | ``` 26 | 27 | ## How to view the VCD file 28 | 29 | ```sh 30 | gtkwave tb.vcd tb.gtkw 31 | ``` 32 | -------------------------------------------------------------------------------- /test/requirements.txt: -------------------------------------------------------------------------------- 1 | pytest==8.1.1 2 | cocotb==1.8.1 3 | -------------------------------------------------------------------------------- /test/tb.gtkw: -------------------------------------------------------------------------------- 1 | [*] 2 | [*] GTKWave Analyzer v3.4.0 (w)1999-2022 BSI 3 | [*] Mon Nov 20 16:00:28 2023 4 | [*] 5 | [dumpfile] "/home/uri/p/tt-new-template-proto/test/tb.vcd" 6 | [dumpfile_mtime] "Mon Nov 20 15:58:34 2023" 7 | [dumpfile_size] 1110 8 | [savefile] "/home/uri/p/tt-new-template-proto/test/tb.gtkw" 9 | [timestart] 0 10 | [size] 1376 600 11 | [pos] -1 -1 12 | *-24.534533 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 13 | [treeopen] tb. 14 | [sst_width] 297 15 | [signals_width] 230 16 | [sst_expanded] 1 17 | [sst_vpaned_height] 158 18 | @28 19 | tb.user_project.ena 20 | @29 21 | tb.user_project.clk 22 | @28 23 | tb.user_project.rst_n 24 | @200 25 | -Inputs 26 | @22 27 | tb.user_project.ui_in[7:0] 28 | @200 29 | -Bidirectional Pins 30 | @22 31 | tb.user_project.uio_in[7:0] 32 | tb.user_project.uio_oe[7:0] 33 | tb.user_project.uio_out[7:0] 34 | @200 35 | -Output Pins 36 | @22 37 | tb.user_project.uo_out[7:0] 38 | [pattern_trace] 1 39 | [pattern_trace] 0 40 | -------------------------------------------------------------------------------- /test/tb.v: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | `timescale 1ns / 1ps 3 | 4 | /* This testbench just instantiates the module and makes some convenient wires 5 | that can be driven / tested by the cocotb test.py. 6 | */ 7 | module tb (); 8 | 9 | // Dump the signals to a VCD file. You can view it with gtkwave. 10 | initial begin 11 | $dumpfile("tb.vcd"); 12 | $dumpvars(0, tb); 13 | #1; 14 | end 15 | 16 | // Wire up the inputs and outputs: 17 | reg clk; 18 | reg rst_n; 19 | reg ena; 20 | reg [7:0] ui_in; 21 | reg [7:0] uio_in; 22 | wire [7:0] uo_out; 23 | wire [7:0] uio_out; 24 | wire [7:0] uio_oe; 25 | 26 | // Replace tt_um_example with your module name: 27 | tt_um_example user_project ( 28 | 29 | // Include power ports for the Gate Level test: 30 | `ifdef GL_TEST 31 | .VPWR(1'b1), 32 | .VGND(1'b0), 33 | `endif 34 | 35 | .ui_in (ui_in), // Dedicated inputs 36 | .uo_out (uo_out), // Dedicated outputs 37 | .uio_in (uio_in), // IOs: Input path 38 | .uio_out(uio_out), // IOs: Output path 39 | .uio_oe (uio_oe), // IOs: Enable path (active high: 0=input, 1=output) 40 | .ena (ena), // enable - goes high when design is selected 41 | .clk (clk), // clock 42 | .rst_n (rst_n) // not reset 43 | ); 44 | 45 | endmodule 46 | -------------------------------------------------------------------------------- /test/test.py: -------------------------------------------------------------------------------- 1 | # SPDX-FileCopyrightText: © 2024 Tiny Tapeout 2 | # SPDX-License-Identifier: Apache-2.0 3 | 4 | import cocotb 5 | from cocotb.clock import Clock 6 | from cocotb.triggers import ClockCycles 7 | 8 | 9 | @cocotb.test() 10 | async def test_project(dut): 11 | dut._log.info("Start") 12 | 13 | # Set the clock period to 10 us (100 KHz) 14 | clock = Clock(dut.clk, 10, units="us") 15 | cocotb.start_soon(clock.start()) 16 | 17 | # Reset 18 | dut._log.info("Reset") 19 | dut.ena.value = 1 20 | dut.ui_in.value = 0 21 | dut.uio_in.value = 0 22 | dut.rst_n.value = 0 23 | await ClockCycles(dut.clk, 10) 24 | dut.rst_n.value = 1 25 | 26 | dut._log.info("Test project behavior") 27 | 28 | # Set the input values you want to test 29 | dut.ui_in.value = 20 30 | dut.uio_in.value = 30 31 | 32 | # Wait for one clock cycle to see the output values 33 | await ClockCycles(dut.clk, 1) 34 | 35 | # The following assersion is just an example of how to check the output values. 36 | # Change it to match the actual expected output of your module: 37 | assert dut.uo_out.value == 50 38 | 39 | # Keep testing the module by changing the input values, waiting for 40 | # one or more clock cycles, and asserting the expected output values. 41 | --------------------------------------------------------------------------------