├── cifar10 ├── .gitignore ├── ARMCM4_debug │ └── arm_nnexample_cifar10.sct ├── DebugConfig │ ├── ARMCM4_FP_STM32F407VGTx.dbgconf │ └── STM32F407DISCO_STM32F407VGTx.dbgconf ├── EventRecorderStub.scvd ├── RTE │ ├── Compiler │ │ └── EventRecorderConf.h │ ├── Device │ │ ├── ARMCM0 │ │ │ ├── startup_ARMCM0.s │ │ │ └── system_ARMCM0.c │ │ ├── ARMCM3 │ │ │ ├── startup_ARMCM3.s │ │ │ └── system_ARMCM3.c │ │ ├── ARMCM4_FP │ │ │ ├── startup_ARMCM4.s │ │ │ └── system_ARMCM4.c │ │ ├── ARMCM7_SP │ │ │ ├── gcc_arm.ld │ │ │ ├── startup_ARMCM7.c │ │ │ ├── startup_ARMCM7.s │ │ │ └── system_ARMCM7.c │ │ └── STM32F407VGTx │ │ │ ├── startup_stm32f407xx.s │ │ │ ├── system_stm32f4xx-backup.c │ │ │ └── system_stm32f4xx.c │ ├── _ARMCM0 │ │ └── RTE_Components.h │ ├── _ARMCM3 │ │ └── RTE_Components.h │ ├── _ARMCM4_FP │ │ └── RTE_Components.h │ ├── _ARMCM7_SP │ │ └── RTE_Components.h │ └── _STM32F407DISCO │ │ └── RTE_Components.h ├── arm_nnexamples_cifar10.cpp ├── arm_nnexamples_cifar10.uvprojx ├── arm_nnexamples_cifar10_inputs.h ├── arm_nnexamples_cifar10_parameter.h ├── arm_nnexamples_cifar10_weights.h └── readme.txt ├── readme.md └── scripts ├── .gitignore ├── README.md ├── cifar-10-IMG_DATA.ipynb ├── model.png └── requirements.txt /cifar10/.gitignore: -------------------------------------------------------------------------------- 1 | # A .gitignore for Keil projects. 2 | # Taken mostly from http://www.keil.com/support/man/docs/uv4/uv4_b_filetypes.htm 3 | 4 | # User-specific uVision files 5 | *.opt 6 | *.uvopt 7 | *.uvoptx 8 | *.uvgui 9 | *.uvgui.* 10 | *.uvguix.* 11 | 12 | # Listing files 13 | *.cod 14 | *.htm 15 | *.i 16 | *.lst 17 | *.map 18 | *.m51 19 | *.m66 20 | *.scr # define exception below if needed 21 | 22 | # Object and HEX files 23 | *.axf 24 | *.b[0-3][0-9] 25 | *.hex 26 | *.d 27 | *.crf 28 | *.elf 29 | *.hex 30 | *.h86 31 | *.lib 32 | *.obj 33 | *.o 34 | *.sbr 35 | 36 | # Build files 37 | *.bat # define exception below if needed 38 | *._ia 39 | *.__i 40 | *._ii 41 | 42 | # Generated output files 43 | /Listings/* 44 | /Objects/* 45 | 46 | # Debugger files 47 | *.ini # define exception below if needed 48 | 49 | # Other files 50 | *.build_log.htm 51 | *.cdb 52 | *.dep 53 | *.ic 54 | *.lin 55 | *.lnp 56 | *.orc 57 | *.pack # define exception below if needed 58 | *.pdsc # define exception below if needed 59 | *.plg 60 | *.sct # define exception below if needed 61 | *.sfd 62 | *.sfr 63 | 64 | # Miscellaneous 65 | *.tra 66 | *.bin 67 | *.fed 68 | *.l1p 69 | *.l2p 70 | *.iex 71 | 72 | # To explicitly override the above, define any exceptions here; e.g.: 73 | # !my_customized_scatter_file.sct -------------------------------------------------------------------------------- /cifar10/ARMCM4_debug/arm_nnexample_cifar10.sct: -------------------------------------------------------------------------------- 1 | ; ************************************************************* 2 | ; *** Scatter-Loading Description File generated by uVision *** 3 | ; ************************************************************* 4 | 5 | LR_IROM1 0x08000000 0x00100000 { ; load region size_region 6 | ER_IROM1 0x08000000 0x00100000 { ; load address = execution address 7 | *.o (RESET, +First) 8 | *(InRoot$$Sections) 9 | .ANY (+RO) 10 | } 11 | RW_IRAM1 0x20000000 0x00020000 { ; RW data 12 | .ANY (+RW +ZI) 13 | } 14 | } 15 | 16 | -------------------------------------------------------------------------------- /cifar10/DebugConfig/ARMCM4_FP_STM32F407VGTx.dbgconf: -------------------------------------------------------------------------------- 1 | // File: STM32F405_415_407_417_427_437_429_439.dbgconf 2 | // Version: 1.0.0 3 | // Note: refer to STM32F405/415 STM32F407/417 STM32F427/437 STM32F429/439 reference manual (RM0090) 4 | // refer to STM32F40x STM32F41x datasheets 5 | // refer to STM32F42x STM32F43x datasheets 6 | 7 | // <<< Use Configuration Wizard in Context Menu >>> 8 | 9 | // Debug MCU configuration register (DBGMCU_CR) 10 | // DBG_STANDBY Debug Standby Mode 11 | // DBG_STOP Debug Stop Mode 12 | // DBG_SLEEP Debug Sleep Mode 13 | // 14 | DbgMCU_CR = 0x00000007; 15 | 16 | // Debug MCU APB1 freeze register (DBGMCU_APB1_FZ) 17 | // Reserved bits must be kept at reset value 18 | // DBG_CAN2_STOP CAN2 stopped when core is halted 19 | // DBG_CAN1_STOP CAN2 stopped when core is halted 20 | // DBG_I2C3_SMBUS_TIMEOUT I2C3 SMBUS timeout mode stopped when core is halted 21 | // DBG_I2C2_SMBUS_TIMEOUT I2C2 SMBUS timeout mode stopped when core is halted 22 | // DBG_I2C1_SMBUS_TIMEOUT I2C1 SMBUS timeout mode stopped when core is halted 23 | // DBG_IWDG_STOP Independent watchdog stopped when core is halted 24 | // DBG_WWDG_STOP Window watchdog stopped when core is halted 25 | // DBG_RTC_STOP RTC stopped when core is halted 26 | // DBG_TIM14_STOP TIM14 counter stopped when core is halted 27 | // DBG_TIM13_STOP TIM13 counter stopped when core is halted 28 | // DBG_TIM12_STOP TIM12 counter stopped when core is halted 29 | // DBG_TIM7_STOP TIM7 counter stopped when core is halted 30 | // DBG_TIM6_STOP TIM6 counter stopped when core is halted 31 | // DBG_TIM5_STOP TIM5 counter stopped when core is halted 32 | // DBG_TIM4_STOP TIM4 counter stopped when core is halted 33 | // DBG_TIM3_STOP TIM3 counter stopped when core is halted 34 | // DBG_TIM2_STOP TIM2 counter stopped when core is halted 35 | // 36 | DbgMCU_APB1_Fz = 0x00000000; 37 | 38 | // Debug MCU APB2 freeze register (DBGMCU_APB2_FZ) 39 | // Reserved bits must be kept at reset value 40 | // DBG_TIM11_STOP TIM11 counter stopped when core is halted 41 | // DBG_TIM10_STOP TIM10 counter stopped when core is halted 42 | // DBG_TIM9_STOP TIM9 counter stopped when core is halted 43 | // DBG_TIM8_STOP TIM8 counter stopped when core is halted 44 | // DBG_TIM1_STOP TIM1 counter stopped when core is halted 45 | // 46 | DbgMCU_APB2_Fz = 0x00000000; 47 | 48 | // <<< end of configuration section >>> -------------------------------------------------------------------------------- /cifar10/DebugConfig/STM32F407DISCO_STM32F407VGTx.dbgconf: -------------------------------------------------------------------------------- 1 | // File: STM32F405_415_407_417_427_437_429_439.dbgconf 2 | // Version: 1.0.0 3 | // Note: refer to STM32F405/415 STM32F407/417 STM32F427/437 STM32F429/439 reference manual (RM0090) 4 | // refer to STM32F40x STM32F41x datasheets 5 | // refer to STM32F42x STM32F43x datasheets 6 | 7 | // <<< Use Configuration Wizard in Context Menu >>> 8 | 9 | // Debug MCU configuration register (DBGMCU_CR) 10 | // DBG_STANDBY Debug Standby Mode 11 | // DBG_STOP Debug Stop Mode 12 | // DBG_SLEEP Debug Sleep Mode 13 | // 14 | DbgMCU_CR = 0x00000007; 15 | 16 | // Debug MCU APB1 freeze register (DBGMCU_APB1_FZ) 17 | // Reserved bits must be kept at reset value 18 | // DBG_CAN2_STOP CAN2 stopped when core is halted 19 | // DBG_CAN1_STOP CAN2 stopped when core is halted 20 | // DBG_I2C3_SMBUS_TIMEOUT I2C3 SMBUS timeout mode stopped when core is halted 21 | // DBG_I2C2_SMBUS_TIMEOUT I2C2 SMBUS timeout mode stopped when core is halted 22 | // DBG_I2C1_SMBUS_TIMEOUT I2C1 SMBUS timeout mode stopped when core is halted 23 | // DBG_IWDG_STOP Independent watchdog stopped when core is halted 24 | // DBG_WWDG_STOP Window watchdog stopped when core is halted 25 | // DBG_RTC_STOP RTC stopped when core is halted 26 | // DBG_TIM14_STOP TIM14 counter stopped when core is halted 27 | // DBG_TIM13_STOP TIM13 counter stopped when core is halted 28 | // DBG_TIM12_STOP TIM12 counter stopped when core is halted 29 | // DBG_TIM7_STOP TIM7 counter stopped when core is halted 30 | // DBG_TIM6_STOP TIM6 counter stopped when core is halted 31 | // DBG_TIM5_STOP TIM5 counter stopped when core is halted 32 | // DBG_TIM4_STOP TIM4 counter stopped when core is halted 33 | // DBG_TIM3_STOP TIM3 counter stopped when core is halted 34 | // DBG_TIM2_STOP TIM2 counter stopped when core is halted 35 | // 36 | DbgMCU_APB1_Fz = 0x00000000; 37 | 38 | // Debug MCU APB2 freeze register (DBGMCU_APB2_FZ) 39 | // Reserved bits must be kept at reset value 40 | // DBG_TIM11_STOP TIM11 counter stopped when core is halted 41 | // DBG_TIM10_STOP TIM10 counter stopped when core is halted 42 | // DBG_TIM9_STOP TIM9 counter stopped when core is halted 43 | // DBG_TIM8_STOP TIM8 counter stopped when core is halted 44 | // DBG_TIM1_STOP TIM1 counter stopped when core is halted 45 | // 46 | DbgMCU_APB2_Fz = 0x00000000; 47 | 48 | // <<< end of configuration section >>> -------------------------------------------------------------------------------- /cifar10/EventRecorderStub.scvd: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | -------------------------------------------------------------------------------- /cifar10/RTE/Compiler/EventRecorderConf.h: -------------------------------------------------------------------------------- 1 | /*------------------------------------------------------------------------------ 2 | * MDK - Component ::Event Recorder 3 | * Copyright (c) 2016 ARM Germany GmbH. All rights reserved. 4 | *------------------------------------------------------------------------------ 5 | * Name: EventRecorderConf.h 6 | * Purpose: Event Recorder Configuration 7 | * Rev.: V1.0.0 8 | *----------------------------------------------------------------------------*/ 9 | 10 | //-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- 11 | 12 | // Event Recorder 13 | 14 | // Number of Records 15 | // <8=>8 <16=>16 <32=>32 <64=>64 <128=>128 <256=>256 <512=>512 <1024=>1024 16 | // <2048=>2048 <4096=>4096 <8192=>8192 <16384=>16384 <32768=>32768 17 | // <65536=>65536 <131072=>131072 <262144=>262144 <524288=>524288 18 | // <1048576=>1048576 19 | // Configure size of Event Record Buffer (each record is 16 bytes) 20 | // Must be 2^n (min=8, max=1048576) 21 | #define EVENT_RECORD_COUNT 64U 22 | 23 | // Time Stamp Source 24 | // <0=> DWT Cycle Counter <1=> SysTick 25 | // <3=> User Timer (Normal Reset) <4=> User Timer (Power-On Reset) 26 | // Selects source for 32-bit time stamp 27 | #define EVENT_TIMESTAMP_SOURCE 1 28 | 29 | // SysTick Configuration 30 | // Configure values when Time Stamp Source is set to SysTick 31 | 32 | // SysTick Input Clock Frequency [Hz] <1-1000000000> 33 | // Defines SysTick input clock (typical identical with processor clock) 34 | #define SYSTICK_CLOCK 100000000U 35 | 36 | // SysTick Interrupt Period [us] <1-1000000000> 37 | // Defines time period of the SysTick timer interrupt 38 | #define SYSTICK_PERIOD_US 1000U 39 | 40 | // 41 | 42 | // 43 | 44 | //------------- <<< end of configuration section >>> --------------------------- 45 | -------------------------------------------------------------------------------- /cifar10/RTE/Device/ARMCM0/startup_ARMCM0.s: -------------------------------------------------------------------------------- 1 | ;/**************************************************************************//** 2 | ; * @file startup_ARMCM0.s 3 | ; * @brief CMSIS Core Device Startup File for 4 | ; * ARMCM0 Device Series 5 | ; * @version V5.00 6 | ; * @date 02. March 2016 7 | ; ******************************************************************************/ 8 | ;/* 9 | ; * Copyright (c) 2009-2016 ARM Limited. All rights reserved. 10 | ; * 11 | ; * SPDX-License-Identifier: Apache-2.0 12 | ; * 13 | ; * Licensed under the Apache License, Version 2.0 (the License); you may 14 | ; * not use this file except in compliance with the License. 15 | ; * You may obtain a copy of the License at 16 | ; * 17 | ; * www.apache.org/licenses/LICENSE-2.0 18 | ; * 19 | ; * Unless required by applicable law or agreed to in writing, software 20 | ; * distributed under the License is distributed on an AS IS BASIS, WITHOUT 21 | ; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 | ; * See the License for the specific language governing permissions and 23 | ; * limitations under the License. 24 | ; */ 25 | 26 | ;/* 27 | ;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ 28 | ;*/ 29 | 30 | 31 | ; Stack Configuration 32 | ; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> 33 | ; 34 | 35 | Stack_Size EQU 0x00000400 36 | 37 | AREA STACK, NOINIT, READWRITE, ALIGN=3 38 | Stack_Mem SPACE Stack_Size 39 | __initial_sp 40 | 41 | 42 | ; Heap Configuration 43 | ; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> 44 | ; 45 | 46 | Heap_Size EQU 0x00000C00 47 | 48 | AREA HEAP, NOINIT, READWRITE, ALIGN=3 49 | __heap_base 50 | Heap_Mem SPACE Heap_Size 51 | __heap_limit 52 | 53 | 54 | PRESERVE8 55 | THUMB 56 | 57 | 58 | ; Vector Table Mapped to Address 0 at Reset 59 | 60 | AREA RESET, DATA, READONLY 61 | EXPORT __Vectors 62 | EXPORT __Vectors_End 63 | EXPORT __Vectors_Size 64 | 65 | __Vectors DCD __initial_sp ; Top of Stack 66 | DCD Reset_Handler ; Reset Handler 67 | DCD NMI_Handler ; NMI Handler 68 | DCD HardFault_Handler ; Hard Fault Handler 69 | DCD 0 ; Reserved 70 | DCD 0 ; Reserved 71 | DCD 0 ; Reserved 72 | DCD 0 ; Reserved 73 | DCD 0 ; Reserved 74 | DCD 0 ; Reserved 75 | DCD 0 ; Reserved 76 | DCD SVC_Handler ; SVCall Handler 77 | DCD 0 ; Reserved 78 | DCD 0 ; Reserved 79 | DCD PendSV_Handler ; PendSV Handler 80 | DCD SysTick_Handler ; SysTick Handler 81 | 82 | ; External Interrupts 83 | DCD WDT_IRQHandler ; 0: Watchdog Timer 84 | DCD RTC_IRQHandler ; 1: Real Time Clock 85 | DCD TIM0_IRQHandler ; 2: Timer0 / Timer1 86 | DCD TIM2_IRQHandler ; 3: Timer2 / Timer3 87 | DCD MCIA_IRQHandler ; 4: MCIa 88 | DCD MCIB_IRQHandler ; 5: MCIb 89 | DCD UART0_IRQHandler ; 6: UART0 - DUT FPGA 90 | DCD UART1_IRQHandler ; 7: UART1 - DUT FPGA 91 | DCD UART2_IRQHandler ; 8: UART2 - DUT FPGA 92 | DCD UART4_IRQHandler ; 9: UART4 - not connected 93 | DCD AACI_IRQHandler ; 10: AACI / AC97 94 | DCD CLCD_IRQHandler ; 11: CLCD Combined Interrupt 95 | DCD ENET_IRQHandler ; 12: Ethernet 96 | DCD USBDC_IRQHandler ; 13: USB Device 97 | DCD USBHC_IRQHandler ; 14: USB Host Controller 98 | DCD CHLCD_IRQHandler ; 15: Character LCD 99 | DCD FLEXRAY_IRQHandler ; 16: Flexray 100 | DCD CAN_IRQHandler ; 17: CAN 101 | DCD LIN_IRQHandler ; 18: LIN 102 | DCD I2C_IRQHandler ; 19: I2C ADC/DAC 103 | DCD 0 ; 20: Reserved 104 | DCD 0 ; 21: Reserved 105 | DCD 0 ; 22: Reserved 106 | DCD 0 ; 23: Reserved 107 | DCD 0 ; 24: Reserved 108 | DCD 0 ; 25: Reserved 109 | DCD 0 ; 26: Reserved 110 | DCD 0 ; 27: Reserved 111 | DCD CPU_CLCD_IRQHandler ; 28: Reserved - CPU FPGA CLCD 112 | DCD 0 ; 29: Reserved - CPU FPGA 113 | DCD UART3_IRQHandler ; 30: UART3 - CPU FPGA 114 | DCD SPI_IRQHandler ; 31: SPI Touchscreen - CPU FPGA 115 | __Vectors_End 116 | 117 | __Vectors_Size EQU __Vectors_End - __Vectors 118 | 119 | AREA |.text|, CODE, READONLY 120 | 121 | 122 | ; Reset Handler 123 | 124 | Reset_Handler PROC 125 | EXPORT Reset_Handler [WEAK] 126 | IMPORT SystemInit 127 | IMPORT __main 128 | LDR R0, =SystemInit 129 | BLX R0 130 | LDR R0, =__main 131 | BX R0 132 | ENDP 133 | 134 | 135 | ; Dummy Exception Handlers (infinite loops which can be modified) 136 | 137 | NMI_Handler PROC 138 | EXPORT NMI_Handler [WEAK] 139 | B . 140 | ENDP 141 | HardFault_Handler\ 142 | PROC 143 | EXPORT HardFault_Handler [WEAK] 144 | B . 145 | ENDP 146 | SVC_Handler PROC 147 | EXPORT SVC_Handler [WEAK] 148 | B . 149 | ENDP 150 | PendSV_Handler PROC 151 | EXPORT PendSV_Handler [WEAK] 152 | B . 153 | ENDP 154 | SysTick_Handler PROC 155 | EXPORT SysTick_Handler [WEAK] 156 | B . 157 | ENDP 158 | 159 | Default_Handler PROC 160 | 161 | EXPORT WDT_IRQHandler [WEAK] 162 | EXPORT RTC_IRQHandler [WEAK] 163 | EXPORT TIM0_IRQHandler [WEAK] 164 | EXPORT TIM2_IRQHandler [WEAK] 165 | EXPORT MCIA_IRQHandler [WEAK] 166 | EXPORT MCIB_IRQHandler [WEAK] 167 | EXPORT UART0_IRQHandler [WEAK] 168 | EXPORT UART1_IRQHandler [WEAK] 169 | EXPORT UART2_IRQHandler [WEAK] 170 | EXPORT UART3_IRQHandler [WEAK] 171 | EXPORT UART4_IRQHandler [WEAK] 172 | EXPORT AACI_IRQHandler [WEAK] 173 | EXPORT CLCD_IRQHandler [WEAK] 174 | EXPORT ENET_IRQHandler [WEAK] 175 | EXPORT USBDC_IRQHandler [WEAK] 176 | EXPORT USBHC_IRQHandler [WEAK] 177 | EXPORT CHLCD_IRQHandler [WEAK] 178 | EXPORT FLEXRAY_IRQHandler [WEAK] 179 | EXPORT CAN_IRQHandler [WEAK] 180 | EXPORT LIN_IRQHandler [WEAK] 181 | EXPORT I2C_IRQHandler [WEAK] 182 | EXPORT CPU_CLCD_IRQHandler [WEAK] 183 | EXPORT SPI_IRQHandler [WEAK] 184 | 185 | WDT_IRQHandler 186 | RTC_IRQHandler 187 | TIM0_IRQHandler 188 | TIM2_IRQHandler 189 | MCIA_IRQHandler 190 | MCIB_IRQHandler 191 | UART0_IRQHandler 192 | UART1_IRQHandler 193 | UART2_IRQHandler 194 | UART3_IRQHandler 195 | UART4_IRQHandler 196 | AACI_IRQHandler 197 | CLCD_IRQHandler 198 | ENET_IRQHandler 199 | USBDC_IRQHandler 200 | USBHC_IRQHandler 201 | CHLCD_IRQHandler 202 | FLEXRAY_IRQHandler 203 | CAN_IRQHandler 204 | LIN_IRQHandler 205 | I2C_IRQHandler 206 | CPU_CLCD_IRQHandler 207 | SPI_IRQHandler 208 | B . 209 | 210 | ENDP 211 | 212 | 213 | ALIGN 214 | 215 | 216 | ; User Initial Stack & Heap 217 | 218 | IF :DEF:__MICROLIB 219 | 220 | EXPORT __initial_sp 221 | EXPORT __heap_base 222 | EXPORT __heap_limit 223 | 224 | ELSE 225 | 226 | IMPORT __use_two_region_memory 227 | EXPORT __user_initial_stackheap 228 | 229 | __user_initial_stackheap PROC 230 | LDR R0, = Heap_Mem 231 | LDR R1, =(Stack_Mem + Stack_Size) 232 | LDR R2, = (Heap_Mem + Heap_Size) 233 | LDR R3, = Stack_Mem 234 | BX LR 235 | ENDP 236 | 237 | ALIGN 238 | 239 | ENDIF 240 | 241 | 242 | END 243 | -------------------------------------------------------------------------------- /cifar10/RTE/Device/ARMCM0/system_ARMCM0.c: -------------------------------------------------------------------------------- 1 | /**************************************************************************//** 2 | * @file system_ARMCM0.c 3 | * @brief CMSIS Device System Source File for 4 | * ARMCM0 Device Series 5 | * @version V5.00 6 | * @date 08. April 2016 7 | ******************************************************************************/ 8 | /* 9 | * Copyright (c) 2009-2016 ARM Limited. All rights reserved. 10 | * 11 | * SPDX-License-Identifier: Apache-2.0 12 | * 13 | * Licensed under the Apache License, Version 2.0 (the License); you may 14 | * not use this file except in compliance with the License. 15 | * You may obtain a copy of the License at 16 | * 17 | * www.apache.org/licenses/LICENSE-2.0 18 | * 19 | * Unless required by applicable law or agreed to in writing, software 20 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 21 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 | * See the License for the specific language governing permissions and 23 | * limitations under the License. 24 | */ 25 | 26 | #include "ARMCM0.h" 27 | 28 | /*---------------------------------------------------------------------------- 29 | Define clocks 30 | *----------------------------------------------------------------------------*/ 31 | #define XTAL ( 5000000U) /* Oscillator frequency */ 32 | 33 | #define SYSTEM_CLOCK (5 * XTAL) 34 | 35 | 36 | /*---------------------------------------------------------------------------- 37 | System Core Clock Variable 38 | *----------------------------------------------------------------------------*/ 39 | uint32_t SystemCoreClock = SYSTEM_CLOCK; 40 | 41 | 42 | /*---------------------------------------------------------------------------- 43 | System Core Clock update function 44 | *----------------------------------------------------------------------------*/ 45 | void SystemCoreClockUpdate (void) 46 | { 47 | SystemCoreClock = SYSTEM_CLOCK; 48 | } 49 | 50 | /*---------------------------------------------------------------------------- 51 | System initialization function 52 | *----------------------------------------------------------------------------*/ 53 | void SystemInit (void) 54 | { 55 | SystemCoreClock = SYSTEM_CLOCK; 56 | } 57 | -------------------------------------------------------------------------------- /cifar10/RTE/Device/ARMCM3/startup_ARMCM3.s: -------------------------------------------------------------------------------- 1 | ;/**************************************************************************//** 2 | ; * @file startup_ARMCM3.s 3 | ; * @brief CMSIS Core Device Startup File for 4 | ; * ARMCM3 Device Series 5 | ; * @version V5.00 6 | ; * @date 02. March 2016 7 | ; ******************************************************************************/ 8 | ;/* 9 | ; * Copyright (c) 2009-2016 ARM Limited. All rights reserved. 10 | ; * 11 | ; * SPDX-License-Identifier: Apache-2.0 12 | ; * 13 | ; * Licensed under the Apache License, Version 2.0 (the License); you may 14 | ; * not use this file except in compliance with the License. 15 | ; * You may obtain a copy of the License at 16 | ; * 17 | ; * www.apache.org/licenses/LICENSE-2.0 18 | ; * 19 | ; * Unless required by applicable law or agreed to in writing, software 20 | ; * distributed under the License is distributed on an AS IS BASIS, WITHOUT 21 | ; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 | ; * See the License for the specific language governing permissions and 23 | ; * limitations under the License. 24 | ; */ 25 | 26 | ;/* 27 | ;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ 28 | ;*/ 29 | 30 | 31 | ; Stack Configuration 32 | ; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> 33 | ; 34 | 35 | Stack_Size EQU 0x00000400 36 | 37 | AREA STACK, NOINIT, READWRITE, ALIGN=3 38 | Stack_Mem SPACE Stack_Size 39 | __initial_sp 40 | 41 | 42 | ; Heap Configuration 43 | ; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> 44 | ; 45 | 46 | Heap_Size EQU 0x00000C00 47 | 48 | AREA HEAP, NOINIT, READWRITE, ALIGN=3 49 | __heap_base 50 | Heap_Mem SPACE Heap_Size 51 | __heap_limit 52 | 53 | 54 | PRESERVE8 55 | THUMB 56 | 57 | 58 | ; Vector Table Mapped to Address 0 at Reset 59 | 60 | AREA RESET, DATA, READONLY 61 | EXPORT __Vectors 62 | EXPORT __Vectors_End 63 | EXPORT __Vectors_Size 64 | 65 | __Vectors DCD __initial_sp ; Top of Stack 66 | DCD Reset_Handler ; Reset Handler 67 | DCD NMI_Handler ; NMI Handler 68 | DCD HardFault_Handler ; Hard Fault Handler 69 | DCD MemManage_Handler ; MPU Fault Handler 70 | DCD BusFault_Handler ; Bus Fault Handler 71 | DCD UsageFault_Handler ; Usage Fault Handler 72 | DCD 0 ; Reserved 73 | DCD 0 ; Reserved 74 | DCD 0 ; Reserved 75 | DCD 0 ; Reserved 76 | DCD SVC_Handler ; SVCall Handler 77 | DCD DebugMon_Handler ; Debug Monitor Handler 78 | DCD 0 ; Reserved 79 | DCD PendSV_Handler ; PendSV Handler 80 | DCD SysTick_Handler ; SysTick Handler 81 | 82 | ; External Interrupts 83 | DCD WDT_IRQHandler ; 0: Watchdog Timer 84 | DCD RTC_IRQHandler ; 1: Real Time Clock 85 | DCD TIM0_IRQHandler ; 2: Timer0 / Timer1 86 | DCD TIM2_IRQHandler ; 3: Timer2 / Timer3 87 | DCD MCIA_IRQHandler ; 4: MCIa 88 | DCD MCIB_IRQHandler ; 5: MCIb 89 | DCD UART0_IRQHandler ; 6: UART0 - DUT FPGA 90 | DCD UART1_IRQHandler ; 7: UART1 - DUT FPGA 91 | DCD UART2_IRQHandler ; 8: UART2 - DUT FPGA 92 | DCD UART4_IRQHandler ; 9: UART4 - not connected 93 | DCD AACI_IRQHandler ; 10: AACI / AC97 94 | DCD CLCD_IRQHandler ; 11: CLCD Combined Interrupt 95 | DCD ENET_IRQHandler ; 12: Ethernet 96 | DCD USBDC_IRQHandler ; 13: USB Device 97 | DCD USBHC_IRQHandler ; 14: USB Host Controller 98 | DCD CHLCD_IRQHandler ; 15: Character LCD 99 | DCD FLEXRAY_IRQHandler ; 16: Flexray 100 | DCD CAN_IRQHandler ; 17: CAN 101 | DCD LIN_IRQHandler ; 18: LIN 102 | DCD I2C_IRQHandler ; 19: I2C ADC/DAC 103 | DCD 0 ; 20: Reserved 104 | DCD 0 ; 21: Reserved 105 | DCD 0 ; 22: Reserved 106 | DCD 0 ; 23: Reserved 107 | DCD 0 ; 24: Reserved 108 | DCD 0 ; 25: Reserved 109 | DCD 0 ; 26: Reserved 110 | DCD 0 ; 27: Reserved 111 | DCD CPU_CLCD_IRQHandler ; 28: Reserved - CPU FPGA CLCD 112 | DCD 0 ; 29: Reserved - CPU FPGA 113 | DCD UART3_IRQHandler ; 30: UART3 - CPU FPGA 114 | DCD SPI_IRQHandler ; 31: SPI Touchscreen - CPU FPGA 115 | __Vectors_End 116 | 117 | __Vectors_Size EQU __Vectors_End - __Vectors 118 | 119 | AREA |.text|, CODE, READONLY 120 | 121 | 122 | ; Reset Handler 123 | 124 | Reset_Handler PROC 125 | EXPORT Reset_Handler [WEAK] 126 | IMPORT SystemInit 127 | IMPORT __main 128 | LDR R0, =SystemInit 129 | BLX R0 130 | LDR R0, =__main 131 | BX R0 132 | ENDP 133 | 134 | 135 | ; Dummy Exception Handlers (infinite loops which can be modified) 136 | 137 | NMI_Handler PROC 138 | EXPORT NMI_Handler [WEAK] 139 | B . 140 | ENDP 141 | HardFault_Handler\ 142 | PROC 143 | EXPORT HardFault_Handler [WEAK] 144 | B . 145 | ENDP 146 | MemManage_Handler\ 147 | PROC 148 | EXPORT MemManage_Handler [WEAK] 149 | B . 150 | ENDP 151 | BusFault_Handler\ 152 | PROC 153 | EXPORT BusFault_Handler [WEAK] 154 | B . 155 | ENDP 156 | UsageFault_Handler\ 157 | PROC 158 | EXPORT UsageFault_Handler [WEAK] 159 | B . 160 | ENDP 161 | SVC_Handler PROC 162 | EXPORT SVC_Handler [WEAK] 163 | B . 164 | ENDP 165 | DebugMon_Handler\ 166 | PROC 167 | EXPORT DebugMon_Handler [WEAK] 168 | B . 169 | ENDP 170 | PendSV_Handler PROC 171 | EXPORT PendSV_Handler [WEAK] 172 | B . 173 | ENDP 174 | SysTick_Handler PROC 175 | EXPORT SysTick_Handler [WEAK] 176 | B . 177 | ENDP 178 | 179 | Default_Handler PROC 180 | 181 | EXPORT WDT_IRQHandler [WEAK] 182 | EXPORT RTC_IRQHandler [WEAK] 183 | EXPORT TIM0_IRQHandler [WEAK] 184 | EXPORT TIM2_IRQHandler [WEAK] 185 | EXPORT MCIA_IRQHandler [WEAK] 186 | EXPORT MCIB_IRQHandler [WEAK] 187 | EXPORT UART0_IRQHandler [WEAK] 188 | EXPORT UART1_IRQHandler [WEAK] 189 | EXPORT UART2_IRQHandler [WEAK] 190 | EXPORT UART3_IRQHandler [WEAK] 191 | EXPORT UART4_IRQHandler [WEAK] 192 | EXPORT AACI_IRQHandler [WEAK] 193 | EXPORT CLCD_IRQHandler [WEAK] 194 | EXPORT ENET_IRQHandler [WEAK] 195 | EXPORT USBDC_IRQHandler [WEAK] 196 | EXPORT USBHC_IRQHandler [WEAK] 197 | EXPORT CHLCD_IRQHandler [WEAK] 198 | EXPORT FLEXRAY_IRQHandler [WEAK] 199 | EXPORT CAN_IRQHandler [WEAK] 200 | EXPORT LIN_IRQHandler [WEAK] 201 | EXPORT I2C_IRQHandler [WEAK] 202 | EXPORT CPU_CLCD_IRQHandler [WEAK] 203 | EXPORT SPI_IRQHandler [WEAK] 204 | 205 | WDT_IRQHandler 206 | RTC_IRQHandler 207 | TIM0_IRQHandler 208 | TIM2_IRQHandler 209 | MCIA_IRQHandler 210 | MCIB_IRQHandler 211 | UART0_IRQHandler 212 | UART1_IRQHandler 213 | UART2_IRQHandler 214 | UART3_IRQHandler 215 | UART4_IRQHandler 216 | AACI_IRQHandler 217 | CLCD_IRQHandler 218 | ENET_IRQHandler 219 | USBDC_IRQHandler 220 | USBHC_IRQHandler 221 | CHLCD_IRQHandler 222 | FLEXRAY_IRQHandler 223 | CAN_IRQHandler 224 | LIN_IRQHandler 225 | I2C_IRQHandler 226 | CPU_CLCD_IRQHandler 227 | SPI_IRQHandler 228 | B . 229 | 230 | ENDP 231 | 232 | 233 | ALIGN 234 | 235 | 236 | ; User Initial Stack & Heap 237 | 238 | IF :DEF:__MICROLIB 239 | 240 | EXPORT __initial_sp 241 | EXPORT __heap_base 242 | EXPORT __heap_limit 243 | 244 | ELSE 245 | 246 | IMPORT __use_two_region_memory 247 | EXPORT __user_initial_stackheap 248 | 249 | __user_initial_stackheap PROC 250 | LDR R0, = Heap_Mem 251 | LDR R1, =(Stack_Mem + Stack_Size) 252 | LDR R2, = (Heap_Mem + Heap_Size) 253 | LDR R3, = Stack_Mem 254 | BX LR 255 | ENDP 256 | 257 | ALIGN 258 | 259 | ENDIF 260 | 261 | 262 | END 263 | -------------------------------------------------------------------------------- /cifar10/RTE/Device/ARMCM3/system_ARMCM3.c: -------------------------------------------------------------------------------- 1 | /**************************************************************************//** 2 | * @file system_ARMCM3.c 3 | * @brief CMSIS Device System Source File for 4 | * ARMCM3 Device Series 5 | * @version V5.00 6 | * @date 08. April 2016 7 | ******************************************************************************/ 8 | /* 9 | * Copyright (c) 2009-2016 ARM Limited. All rights reserved. 10 | * 11 | * SPDX-License-Identifier: Apache-2.0 12 | * 13 | * Licensed under the Apache License, Version 2.0 (the License); you may 14 | * not use this file except in compliance with the License. 15 | * You may obtain a copy of the License at 16 | * 17 | * www.apache.org/licenses/LICENSE-2.0 18 | * 19 | * Unless required by applicable law or agreed to in writing, software 20 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 21 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 | * See the License for the specific language governing permissions and 23 | * limitations under the License. 24 | */ 25 | 26 | #include "ARMCM3.h" 27 | 28 | /*---------------------------------------------------------------------------- 29 | Define clocks 30 | *----------------------------------------------------------------------------*/ 31 | #define XTAL ( 5000000U) /* Oscillator frequency */ 32 | 33 | #define SYSTEM_CLOCK (5 * XTAL) 34 | 35 | 36 | /*---------------------------------------------------------------------------- 37 | Externals 38 | *----------------------------------------------------------------------------*/ 39 | #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1) 40 | extern uint32_t __Vectors; 41 | #endif 42 | 43 | /*---------------------------------------------------------------------------- 44 | System Core Clock Variable 45 | *----------------------------------------------------------------------------*/ 46 | uint32_t SystemCoreClock = SYSTEM_CLOCK; 47 | 48 | 49 | /*---------------------------------------------------------------------------- 50 | System Core Clock update function 51 | *----------------------------------------------------------------------------*/ 52 | void SystemCoreClockUpdate (void) 53 | { 54 | SystemCoreClock = SYSTEM_CLOCK; 55 | } 56 | 57 | /*---------------------------------------------------------------------------- 58 | System initialization function 59 | *----------------------------------------------------------------------------*/ 60 | void SystemInit (void) 61 | { 62 | 63 | #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1) 64 | SCB->VTOR = (uint32_t) &__Vectors; 65 | #endif 66 | 67 | SystemCoreClock = SYSTEM_CLOCK; 68 | } 69 | -------------------------------------------------------------------------------- /cifar10/RTE/Device/ARMCM4_FP/startup_ARMCM4.s: -------------------------------------------------------------------------------- 1 | ;/**************************************************************************//** 2 | ; * @file startup_ARMCM4.s 3 | ; * @brief CMSIS Core Device Startup File for 4 | ; * ARMCM4 Device Series 5 | ; * @version V5.00 6 | ; * @date 02. March 2016 7 | ; ******************************************************************************/ 8 | ;/* 9 | ; * Copyright (c) 2009-2016 ARM Limited. All rights reserved. 10 | ; * 11 | ; * SPDX-License-Identifier: Apache-2.0 12 | ; * 13 | ; * Licensed under the Apache License, Version 2.0 (the License); you may 14 | ; * not use this file except in compliance with the License. 15 | ; * You may obtain a copy of the License at 16 | ; * 17 | ; * www.apache.org/licenses/LICENSE-2.0 18 | ; * 19 | ; * Unless required by applicable law or agreed to in writing, software 20 | ; * distributed under the License is distributed on an AS IS BASIS, WITHOUT 21 | ; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 | ; * See the License for the specific language governing permissions and 23 | ; * limitations under the License. 24 | ; */ 25 | 26 | ;/* 27 | ;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ 28 | ;*/ 29 | 30 | 31 | ; Stack Configuration 32 | ; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> 33 | ; 34 | 35 | Stack_Size EQU 0x00000800 36 | 37 | AREA STACK, NOINIT, READWRITE, ALIGN=3 38 | Stack_Mem SPACE Stack_Size 39 | __initial_sp 40 | 41 | 42 | ; Heap Configuration 43 | ; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> 44 | ; 45 | 46 | Heap_Size EQU 0x00080000 47 | 48 | AREA HEAP, NOINIT, READWRITE, ALIGN=3 49 | __heap_base 50 | Heap_Mem SPACE Heap_Size 51 | __heap_limit 52 | 53 | 54 | PRESERVE8 55 | THUMB 56 | 57 | 58 | ; Vector Table Mapped to Address 0 at Reset 59 | 60 | AREA RESET, DATA, READONLY 61 | EXPORT __Vectors 62 | EXPORT __Vectors_End 63 | EXPORT __Vectors_Size 64 | 65 | __Vectors DCD __initial_sp ; Top of Stack 66 | DCD Reset_Handler ; Reset Handler 67 | DCD NMI_Handler ; NMI Handler 68 | DCD HardFault_Handler ; Hard Fault Handler 69 | DCD MemManage_Handler ; MPU Fault Handler 70 | DCD BusFault_Handler ; Bus Fault Handler 71 | DCD UsageFault_Handler ; Usage Fault Handler 72 | DCD 0 ; Reserved 73 | DCD 0 ; Reserved 74 | DCD 0 ; Reserved 75 | DCD 0 ; Reserved 76 | DCD SVC_Handler ; SVCall Handler 77 | DCD DebugMon_Handler ; Debug Monitor Handler 78 | DCD 0 ; Reserved 79 | DCD PendSV_Handler ; PendSV Handler 80 | DCD SysTick_Handler ; SysTick Handler 81 | 82 | ; External Interrupts 83 | DCD WDT_IRQHandler ; 0: Watchdog Timer 84 | DCD RTC_IRQHandler ; 1: Real Time Clock 85 | DCD TIM0_IRQHandler ; 2: Timer0 / Timer1 86 | DCD TIM2_IRQHandler ; 3: Timer2 / Timer3 87 | DCD MCIA_IRQHandler ; 4: MCIa 88 | DCD MCIB_IRQHandler ; 5: MCIb 89 | DCD UART0_IRQHandler ; 6: UART0 - DUT FPGA 90 | DCD UART1_IRQHandler ; 7: UART1 - DUT FPGA 91 | DCD UART2_IRQHandler ; 8: UART2 - DUT FPGA 92 | DCD UART4_IRQHandler ; 9: UART4 - not connected 93 | DCD AACI_IRQHandler ; 10: AACI / AC97 94 | DCD CLCD_IRQHandler ; 11: CLCD Combined Interrupt 95 | DCD ENET_IRQHandler ; 12: Ethernet 96 | DCD USBDC_IRQHandler ; 13: USB Device 97 | DCD USBHC_IRQHandler ; 14: USB Host Controller 98 | DCD CHLCD_IRQHandler ; 15: Character LCD 99 | DCD FLEXRAY_IRQHandler ; 16: Flexray 100 | DCD CAN_IRQHandler ; 17: CAN 101 | DCD LIN_IRQHandler ; 18: LIN 102 | DCD I2C_IRQHandler ; 19: I2C ADC/DAC 103 | DCD 0 ; 20: Reserved 104 | DCD 0 ; 21: Reserved 105 | DCD 0 ; 22: Reserved 106 | DCD 0 ; 23: Reserved 107 | DCD 0 ; 24: Reserved 108 | DCD 0 ; 25: Reserved 109 | DCD 0 ; 26: Reserved 110 | DCD 0 ; 27: Reserved 111 | DCD CPU_CLCD_IRQHandler ; 28: Reserved - CPU FPGA CLCD 112 | DCD 0 ; 29: Reserved - CPU FPGA 113 | DCD UART3_IRQHandler ; 30: UART3 - CPU FPGA 114 | DCD SPI_IRQHandler ; 31: SPI Touchscreen - CPU FPGA 115 | __Vectors_End 116 | 117 | __Vectors_Size EQU __Vectors_End - __Vectors 118 | 119 | AREA |.text|, CODE, READONLY 120 | 121 | 122 | ; Reset Handler 123 | 124 | Reset_Handler PROC 125 | EXPORT Reset_Handler [WEAK] 126 | IMPORT SystemInit 127 | IMPORT __main 128 | LDR R0, =SystemInit 129 | BLX R0 130 | LDR R0, =__main 131 | BX R0 132 | ENDP 133 | 134 | 135 | ; Dummy Exception Handlers (infinite loops which can be modified) 136 | 137 | NMI_Handler PROC 138 | EXPORT NMI_Handler [WEAK] 139 | B . 140 | ENDP 141 | HardFault_Handler\ 142 | PROC 143 | EXPORT HardFault_Handler [WEAK] 144 | B . 145 | ENDP 146 | MemManage_Handler\ 147 | PROC 148 | EXPORT MemManage_Handler [WEAK] 149 | B . 150 | ENDP 151 | BusFault_Handler\ 152 | PROC 153 | EXPORT BusFault_Handler [WEAK] 154 | B . 155 | ENDP 156 | UsageFault_Handler\ 157 | PROC 158 | EXPORT UsageFault_Handler [WEAK] 159 | B . 160 | ENDP 161 | SVC_Handler PROC 162 | EXPORT SVC_Handler [WEAK] 163 | B . 164 | ENDP 165 | DebugMon_Handler\ 166 | PROC 167 | EXPORT DebugMon_Handler [WEAK] 168 | B . 169 | ENDP 170 | PendSV_Handler PROC 171 | EXPORT PendSV_Handler [WEAK] 172 | B . 173 | ENDP 174 | SysTick_Handler PROC 175 | EXPORT SysTick_Handler [WEAK] 176 | B . 177 | ENDP 178 | 179 | Default_Handler PROC 180 | 181 | EXPORT WDT_IRQHandler [WEAK] 182 | EXPORT RTC_IRQHandler [WEAK] 183 | EXPORT TIM0_IRQHandler [WEAK] 184 | EXPORT TIM2_IRQHandler [WEAK] 185 | EXPORT MCIA_IRQHandler [WEAK] 186 | EXPORT MCIB_IRQHandler [WEAK] 187 | EXPORT UART0_IRQHandler [WEAK] 188 | EXPORT UART1_IRQHandler [WEAK] 189 | EXPORT UART2_IRQHandler [WEAK] 190 | EXPORT UART3_IRQHandler [WEAK] 191 | EXPORT UART4_IRQHandler [WEAK] 192 | EXPORT AACI_IRQHandler [WEAK] 193 | EXPORT CLCD_IRQHandler [WEAK] 194 | EXPORT ENET_IRQHandler [WEAK] 195 | EXPORT USBDC_IRQHandler [WEAK] 196 | EXPORT USBHC_IRQHandler [WEAK] 197 | EXPORT CHLCD_IRQHandler [WEAK] 198 | EXPORT FLEXRAY_IRQHandler [WEAK] 199 | EXPORT CAN_IRQHandler [WEAK] 200 | EXPORT LIN_IRQHandler [WEAK] 201 | EXPORT I2C_IRQHandler [WEAK] 202 | EXPORT CPU_CLCD_IRQHandler [WEAK] 203 | EXPORT SPI_IRQHandler [WEAK] 204 | 205 | WDT_IRQHandler 206 | RTC_IRQHandler 207 | TIM0_IRQHandler 208 | TIM2_IRQHandler 209 | MCIA_IRQHandler 210 | MCIB_IRQHandler 211 | UART0_IRQHandler 212 | UART1_IRQHandler 213 | UART2_IRQHandler 214 | UART3_IRQHandler 215 | UART4_IRQHandler 216 | AACI_IRQHandler 217 | CLCD_IRQHandler 218 | ENET_IRQHandler 219 | USBDC_IRQHandler 220 | USBHC_IRQHandler 221 | CHLCD_IRQHandler 222 | FLEXRAY_IRQHandler 223 | CAN_IRQHandler 224 | LIN_IRQHandler 225 | I2C_IRQHandler 226 | CPU_CLCD_IRQHandler 227 | SPI_IRQHandler 228 | B . 229 | 230 | ENDP 231 | 232 | 233 | ALIGN 234 | 235 | 236 | ; User Initial Stack & Heap 237 | 238 | IF :DEF:__MICROLIB 239 | 240 | EXPORT __initial_sp 241 | EXPORT __heap_base 242 | EXPORT __heap_limit 243 | 244 | ELSE 245 | 246 | IMPORT __use_two_region_memory 247 | EXPORT __user_initial_stackheap 248 | 249 | __user_initial_stackheap PROC 250 | LDR R0, = Heap_Mem 251 | LDR R1, =(Stack_Mem + Stack_Size) 252 | LDR R2, = (Heap_Mem + Heap_Size) 253 | LDR R3, = Stack_Mem 254 | BX LR 255 | ENDP 256 | 257 | ALIGN 258 | 259 | ENDIF 260 | 261 | 262 | END 263 | -------------------------------------------------------------------------------- /cifar10/RTE/Device/ARMCM4_FP/system_ARMCM4.c: -------------------------------------------------------------------------------- 1 | /**************************************************************************//** 2 | * @file system_ARMCM4.c 3 | * @brief CMSIS Device System Source File for 4 | * ARMCM4 Device Series 5 | * @version V5.00 6 | * @date 08. April 2016 7 | ******************************************************************************/ 8 | /* 9 | * Copyright (c) 2009-2016 ARM Limited. All rights reserved. 10 | * 11 | * SPDX-License-Identifier: Apache-2.0 12 | * 13 | * Licensed under the Apache License, Version 2.0 (the License); you may 14 | * not use this file except in compliance with the License. 15 | * You may obtain a copy of the License at 16 | * 17 | * www.apache.org/licenses/LICENSE-2.0 18 | * 19 | * Unless required by applicable law or agreed to in writing, software 20 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 21 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 | * See the License for the specific language governing permissions and 23 | * limitations under the License. 24 | */ 25 | 26 | #if defined (ARMCM4) 27 | #include "ARMCM4.h" 28 | #elif defined (ARMCM4_FP) 29 | #include "ARMCM4_FP.h" 30 | #else 31 | #error device not specified! 32 | #endif 33 | 34 | /*---------------------------------------------------------------------------- 35 | Define clocks 36 | *----------------------------------------------------------------------------*/ 37 | #define XTAL ( 5000000U) /* Oscillator frequency */ 38 | 39 | #define SYSTEM_CLOCK (5 * XTAL) 40 | 41 | 42 | /*---------------------------------------------------------------------------- 43 | Externals 44 | *----------------------------------------------------------------------------*/ 45 | #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1) 46 | extern uint32_t __Vectors; 47 | #endif 48 | 49 | /*---------------------------------------------------------------------------- 50 | System Core Clock Variable 51 | *----------------------------------------------------------------------------*/ 52 | uint32_t SystemCoreClock = SYSTEM_CLOCK; 53 | 54 | 55 | /*---------------------------------------------------------------------------- 56 | System Core Clock update function 57 | *----------------------------------------------------------------------------*/ 58 | void SystemCoreClockUpdate (void) 59 | { 60 | SystemCoreClock = SYSTEM_CLOCK; 61 | } 62 | 63 | /*---------------------------------------------------------------------------- 64 | System initialization function 65 | *----------------------------------------------------------------------------*/ 66 | void SystemInit (void) 67 | { 68 | 69 | #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1) 70 | SCB->VTOR = (uint32_t) &__Vectors; 71 | #endif 72 | 73 | #if defined (__FPU_USED) && (__FPU_USED == 1) 74 | SCB->CPACR |= ((3U << 10*2) | /* set CP10 Full Access */ 75 | (3U << 11*2) ); /* set CP11 Full Access */ 76 | #endif 77 | 78 | #ifdef UNALIGNED_SUPPORT_DISABLE 79 | SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; 80 | #endif 81 | 82 | SystemCoreClock = SYSTEM_CLOCK; 83 | } 84 | -------------------------------------------------------------------------------- /cifar10/RTE/Device/ARMCM7_SP/gcc_arm.ld: -------------------------------------------------------------------------------- 1 | /* Linker script to configure memory regions. */ 2 | MEMORY 3 | { 4 | FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 512K 5 | RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 256K 6 | } 7 | 8 | /* Library configurations */ 9 | GROUP(libgcc.a libc.a libm.a libnosys.a) 10 | 11 | /* Linker script to place sections and symbol values. Should be used together 12 | * with other linker script that defines memory regions FLASH and RAM. 13 | * It references following symbols, which must be defined in code: 14 | * Reset_Handler : Entry of reset handler 15 | * 16 | * It defines following symbols, which code can use without definition: 17 | * __exidx_start 18 | * __exidx_end 19 | * __copy_table_start__ 20 | * __copy_table_end__ 21 | * __zero_table_start__ 22 | * __zero_table_end__ 23 | * __etext 24 | * __data_start__ 25 | * __preinit_array_start 26 | * __preinit_array_end 27 | * __init_array_start 28 | * __init_array_end 29 | * __fini_array_start 30 | * __fini_array_end 31 | * __data_end__ 32 | * __bss_start__ 33 | * __bss_end__ 34 | * __end__ 35 | * end 36 | * __HeapBase 37 | * __HeapLimit 38 | * __StackLimit 39 | * __StackTop 40 | * __stack 41 | * __Vectors_End 42 | * __Vectors_Size 43 | */ 44 | ENTRY(Reset_Handler) 45 | 46 | SECTIONS 47 | { 48 | .text : 49 | { 50 | KEEP(*(.vectors)) 51 | __Vectors_End = .; 52 | __Vectors_Size = __Vectors_End - __Vectors; 53 | __end__ = .; 54 | 55 | *(.text*) 56 | 57 | KEEP(*(.init)) 58 | KEEP(*(.fini)) 59 | 60 | /* .ctors */ 61 | *crtbegin.o(.ctors) 62 | *crtbegin?.o(.ctors) 63 | *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) 64 | *(SORT(.ctors.*)) 65 | *(.ctors) 66 | 67 | /* .dtors */ 68 | *crtbegin.o(.dtors) 69 | *crtbegin?.o(.dtors) 70 | *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) 71 | *(SORT(.dtors.*)) 72 | *(.dtors) 73 | 74 | *(.rodata*) 75 | 76 | KEEP(*(.eh_frame*)) 77 | } > FLASH 78 | 79 | .ARM.extab : 80 | { 81 | *(.ARM.extab* .gnu.linkonce.armextab.*) 82 | } > FLASH 83 | 84 | __exidx_start = .; 85 | .ARM.exidx : 86 | { 87 | *(.ARM.exidx* .gnu.linkonce.armexidx.*) 88 | } > FLASH 89 | __exidx_end = .; 90 | 91 | /* To copy multiple ROM to RAM sections, 92 | * uncomment .copy.table section and, 93 | * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */ 94 | /* 95 | .copy.table : 96 | { 97 | . = ALIGN(4); 98 | __copy_table_start__ = .; 99 | LONG (__etext) 100 | LONG (__data_start__) 101 | LONG (__data_end__ - __data_start__) 102 | LONG (__etext2) 103 | LONG (__data2_start__) 104 | LONG (__data2_end__ - __data2_start__) 105 | __copy_table_end__ = .; 106 | } > FLASH 107 | */ 108 | 109 | /* To clear multiple BSS sections, 110 | * uncomment .zero.table section and, 111 | * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */ 112 | /* 113 | .zero.table : 114 | { 115 | . = ALIGN(4); 116 | __zero_table_start__ = .; 117 | LONG (__bss_start__) 118 | LONG (__bss_end__ - __bss_start__) 119 | LONG (__bss2_start__) 120 | LONG (__bss2_end__ - __bss2_start__) 121 | __zero_table_end__ = .; 122 | } > FLASH 123 | */ 124 | 125 | __etext = .; 126 | 127 | .data : AT (__etext) 128 | { 129 | __data_start__ = .; 130 | *(vtable) 131 | *(.data*) 132 | 133 | . = ALIGN(4); 134 | /* preinit data */ 135 | PROVIDE_HIDDEN (__preinit_array_start = .); 136 | KEEP(*(.preinit_array)) 137 | PROVIDE_HIDDEN (__preinit_array_end = .); 138 | 139 | . = ALIGN(4); 140 | /* init data */ 141 | PROVIDE_HIDDEN (__init_array_start = .); 142 | KEEP(*(SORT(.init_array.*))) 143 | KEEP(*(.init_array)) 144 | PROVIDE_HIDDEN (__init_array_end = .); 145 | 146 | 147 | . = ALIGN(4); 148 | /* finit data */ 149 | PROVIDE_HIDDEN (__fini_array_start = .); 150 | KEEP(*(SORT(.fini_array.*))) 151 | KEEP(*(.fini_array)) 152 | PROVIDE_HIDDEN (__fini_array_end = .); 153 | 154 | KEEP(*(.jcr*)) 155 | . = ALIGN(4); 156 | /* All data end */ 157 | __data_end__ = .; 158 | 159 | } > RAM 160 | 161 | .bss : 162 | { 163 | . = ALIGN(4); 164 | __bss_start__ = .; 165 | *(.bss*) 166 | *(COMMON) 167 | . = ALIGN(4); 168 | __bss_end__ = .; 169 | } > RAM 170 | 171 | .heap (COPY): 172 | { 173 | __HeapBase = .; 174 | __end__ = .; 175 | end = __end__; 176 | KEEP(*(.heap*)) 177 | __HeapLimit = .; 178 | } > RAM 179 | 180 | /* .stack_dummy section doesn't contains any symbols. It is only 181 | * used for linker to calculate size of stack sections, and assign 182 | * values to stack symbols later */ 183 | .stack_dummy (COPY): 184 | { 185 | KEEP(*(.stack*)) 186 | } > RAM 187 | 188 | /* Set stack top to end of RAM, and stack limit move down by 189 | * size of stack_dummy section */ 190 | __StackTop = ORIGIN(RAM) + LENGTH(RAM); 191 | __StackLimit = __StackTop - SIZEOF(.stack_dummy); 192 | PROVIDE(__stack = __StackTop); 193 | 194 | /* Check if data + heap + stack exceeds RAM limit */ 195 | ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") 196 | } 197 | -------------------------------------------------------------------------------- /cifar10/RTE/Device/ARMCM7_SP/startup_ARMCM7.c: -------------------------------------------------------------------------------- 1 | /**************************************************************************//** 2 | * @file startup_ARMCM7.s 3 | * @brief CMSIS Core Device Startup File for 4 | * ARMCM7 Device Series 5 | * @version V5.00 6 | * @date 26. April 2016 7 | ******************************************************************************/ 8 | /* 9 | * Copyright (c) 2009-2016 ARM Limited. All rights reserved. 10 | * 11 | * SPDX-License-Identifier: Apache-2.0 12 | * 13 | * Licensed under the Apache License, Version 2.0 (the License); you may 14 | * not use this file except in compliance with the License. 15 | * You may obtain a copy of the License at 16 | * 17 | * www.apache.org/licenses/LICENSE-2.0 18 | * 19 | * Unless required by applicable law or agreed to in writing, software 20 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 21 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 | * See the License for the specific language governing permissions and 23 | * limitations under the License. 24 | */ 25 | 26 | #include 27 | 28 | 29 | /*---------------------------------------------------------------------------- 30 | Linker generated Symbols 31 | *----------------------------------------------------------------------------*/ 32 | extern uint32_t __etext; 33 | extern uint32_t __data_start__; 34 | extern uint32_t __data_end__; 35 | extern uint32_t __copy_table_start__; 36 | extern uint32_t __copy_table_end__; 37 | extern uint32_t __zero_table_start__; 38 | extern uint32_t __zero_table_end__; 39 | extern uint32_t __bss_start__; 40 | extern uint32_t __bss_end__; 41 | extern uint32_t __StackTop; 42 | 43 | /*---------------------------------------------------------------------------- 44 | Exception / Interrupt Handler Function Prototype 45 | *----------------------------------------------------------------------------*/ 46 | typedef void( *pFunc )( void ); 47 | 48 | 49 | /*---------------------------------------------------------------------------- 50 | External References 51 | *----------------------------------------------------------------------------*/ 52 | #ifndef __START 53 | extern void _start(void) __attribute__((noreturn)); /* PreeMain (C library entry point) */ 54 | #else 55 | extern int __START(void) __attribute__((noreturn)); /* main entry point */ 56 | #endif 57 | 58 | #ifndef __NO_SYSTEM_INIT 59 | extern void SystemInit (void); /* CMSIS System Initialization */ 60 | #endif 61 | 62 | 63 | /*---------------------------------------------------------------------------- 64 | Internal References 65 | *----------------------------------------------------------------------------*/ 66 | void Default_Handler(void); /* Default empty handler */ 67 | void Reset_Handler(void); /* Reset Handler */ 68 | 69 | 70 | /*---------------------------------------------------------------------------- 71 | User Initial Stack & Heap 72 | *----------------------------------------------------------------------------*/ 73 | #ifndef __STACK_SIZE 74 | #define __STACK_SIZE 0x00000400 75 | #endif 76 | static uint8_t stack[__STACK_SIZE] __attribute__ ((aligned(8), used, section(".stack"))); 77 | 78 | #ifndef __HEAP_SIZE 79 | #define __HEAP_SIZE 0x00000C00 80 | #endif 81 | #if __HEAP_SIZE > 0 82 | static uint8_t heap[__HEAP_SIZE] __attribute__ ((aligned(8), used, section(".heap"))); 83 | #endif 84 | 85 | 86 | /*---------------------------------------------------------------------------- 87 | Exception / Interrupt Handler 88 | *----------------------------------------------------------------------------*/ 89 | /* Cortex-M7 Processor Exceptions */ 90 | void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); 91 | void HardFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); 92 | void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); 93 | void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); 94 | void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); 95 | void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); 96 | void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); 97 | void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); 98 | void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); 99 | 100 | /* ARMCM7 Specific Interrupts */ 101 | void WDT_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); 102 | void RTC_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); 103 | void TIM0_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); 104 | void TIM2_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); 105 | void MCIA_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); 106 | void MCIB_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); 107 | void UART0_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); 108 | void UART1_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); 109 | void UART2_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); 110 | void UART4_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); 111 | void AACI_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); 112 | void CLCD_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); 113 | void ENET_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); 114 | void USBDC_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); 115 | void USBHC_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); 116 | void CHLCD_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); 117 | void FLEXRAY_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); 118 | void CAN_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); 119 | void LIN_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); 120 | void I2C_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); 121 | void CPU_CLCD_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); 122 | void UART3_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); 123 | void SPI_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); 124 | 125 | 126 | /*---------------------------------------------------------------------------- 127 | Exception / Interrupt Vector table 128 | *----------------------------------------------------------------------------*/ 129 | const pFunc __Vectors[] __attribute__ ((section(".vectors"))) = { 130 | /* Cortex-M7 Exceptions Handler */ 131 | (pFunc)((uint32_t)&__StackTop), /* Initial Stack Pointer */ 132 | Reset_Handler, /* Reset Handler */ 133 | NMI_Handler, /* NMI Handler */ 134 | HardFault_Handler, /* Hard Fault Handler */ 135 | MemManage_Handler, /* MPU Fault Handler */ 136 | BusFault_Handler, /* Bus Fault Handler */ 137 | UsageFault_Handler, /* Usage Fault Handler */ 138 | 0, /* Reserved */ 139 | 0, /* Reserved */ 140 | 0, /* Reserved */ 141 | 0, /* Reserved */ 142 | SVC_Handler, /* SVCall Handler */ 143 | DebugMon_Handler, /* Debug Monitor Handler */ 144 | 0, /* Reserved */ 145 | PendSV_Handler, /* PendSV Handler */ 146 | SysTick_Handler, /* SysTick Handler */ 147 | 148 | /* External interrupts */ 149 | WDT_IRQHandler, /* 0: Watchdog Timer */ 150 | RTC_IRQHandler, /* 1: Real Time Clock */ 151 | TIM0_IRQHandler, /* 2: Timer0 / Timer1 */ 152 | TIM2_IRQHandler, /* 3: Timer2 / Timer3 */ 153 | MCIA_IRQHandler, /* 4: MCIa */ 154 | MCIB_IRQHandler, /* 5: MCIb */ 155 | UART0_IRQHandler, /* 6: UART0 - DUT FPGA */ 156 | UART1_IRQHandler, /* 7: UART1 - DUT FPGA */ 157 | UART2_IRQHandler, /* 8: UART2 - DUT FPGA */ 158 | UART4_IRQHandler, /* 9: UART4 - not connected */ 159 | AACI_IRQHandler, /* 10: AACI / AC97 */ 160 | CLCD_IRQHandler, /* 11: CLCD Combined Interrupt */ 161 | ENET_IRQHandler, /* 12: Ethernet */ 162 | USBDC_IRQHandler, /* 13: USB Device */ 163 | USBHC_IRQHandler, /* 14: USB Host Controller */ 164 | CHLCD_IRQHandler, /* 15: Character LCD */ 165 | FLEXRAY_IRQHandler, /* 16: Flexray */ 166 | CAN_IRQHandler, /* 17: CAN */ 167 | LIN_IRQHandler, /* 18: LIN */ 168 | I2C_IRQHandler, /* 19: I2C ADC/DAC */ 169 | 0, /* 20: Reserved */ 170 | 0, /* 21: Reserved */ 171 | 0, /* 22: Reserved */ 172 | 0, /* 23: Reserved */ 173 | 0, /* 24: Reserved */ 174 | 0, /* 25: Reserved */ 175 | 0, /* 26: Reserved */ 176 | 0, /* 27: Reserved */ 177 | CPU_CLCD_IRQHandler, /* 28: Reserved - CPU FPGA CLCD */ 178 | 0, /* 29: Reserved - CPU FPGA */ 179 | UART3_IRQHandler, /* 30: UART3 - CPU FPGA */ 180 | SPI_IRQHandler /* 31: SPI Touchscreen - CPU FPGA */ 181 | }; 182 | 183 | 184 | /*---------------------------------------------------------------------------- 185 | Reset Handler called on controller reset 186 | *----------------------------------------------------------------------------*/ 187 | void Reset_Handler(void) { 188 | uint32_t *pSrc, *pDest; 189 | uint32_t *pTable __attribute__((unused)); 190 | 191 | /* Firstly it copies data from read only memory to RAM. There are two schemes 192 | * to copy. One can copy more than one sections. Another can only copy 193 | * one section. The former scheme needs more instructions and read-only 194 | * data to implement than the latter. 195 | * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */ 196 | 197 | #ifdef __STARTUP_COPY_MULTIPLE 198 | /* Multiple sections scheme. 199 | * 200 | * Between symbol address __copy_table_start__ and __copy_table_end__, 201 | * there are array of triplets, each of which specify: 202 | * offset 0: LMA of start of a section to copy from 203 | * offset 4: VMA of start of a section to copy to 204 | * offset 8: size of the section to copy. Must be multiply of 4 205 | * 206 | * All addresses must be aligned to 4 bytes boundary. 207 | */ 208 | pTable = &__copy_table_start__; 209 | 210 | for (; pTable < &__copy_table_end__; pTable = pTable + 3) { 211 | pSrc = (uint32_t*)*(pTable + 0); 212 | pDest = (uint32_t*)*(pTable + 1); 213 | for (; pDest < (uint32_t*)(*(pTable + 1) + *(pTable + 2)) ; ) { 214 | *pDest++ = *pSrc++; 215 | } 216 | } 217 | #else 218 | /* Single section scheme. 219 | * 220 | * The ranges of copy from/to are specified by following symbols 221 | * __etext: LMA of start of the section to copy from. Usually end of text 222 | * __data_start__: VMA of start of the section to copy to 223 | * __data_end__: VMA of end of the section to copy to 224 | * 225 | * All addresses must be aligned to 4 bytes boundary. 226 | */ 227 | pSrc = &__etext; 228 | pDest = &__data_start__; 229 | 230 | for ( ; pDest < &__data_end__ ; ) { 231 | *pDest++ = *pSrc++; 232 | } 233 | #endif /*__STARTUP_COPY_MULTIPLE */ 234 | 235 | /* This part of work usually is done in C library startup code. Otherwise, 236 | * define this macro to enable it in this startup. 237 | * 238 | * There are two schemes too. One can clear multiple BSS sections. Another 239 | * can only clear one section. The former is more size expensive than the 240 | * latter. 241 | * 242 | * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former. 243 | * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later. 244 | */ 245 | #ifdef __STARTUP_CLEAR_BSS_MULTIPLE 246 | /* Multiple sections scheme. 247 | * 248 | * Between symbol address __copy_table_start__ and __copy_table_end__, 249 | * there are array of tuples specifying: 250 | * offset 0: Start of a BSS section 251 | * offset 4: Size of this BSS section. Must be multiply of 4 252 | */ 253 | pTable = &__zero_table_start__; 254 | 255 | for (; pTable < &__zero_table_end__; pTable = pTable + 2) { 256 | pDest = (uint32_t*)*(pTable + 0); 257 | for (; pDest < (uint32_t*)(*(pTable + 0) + *(pTable + 1)) ; ) { 258 | *pDest++ = 0; 259 | } 260 | } 261 | #elif defined (__STARTUP_CLEAR_BSS) 262 | /* Single BSS section scheme. 263 | * 264 | * The BSS section is specified by following symbols 265 | * __bss_start__: start of the BSS section. 266 | * __bss_end__: end of the BSS section. 267 | * 268 | * Both addresses must be aligned to 4 bytes boundary. 269 | */ 270 | pDest = &__bss_start__; 271 | 272 | for ( ; pDest < &__bss_end__ ; ) { 273 | *pDest++ = 0UL; 274 | } 275 | #endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */ 276 | 277 | #ifndef __NO_SYSTEM_INIT 278 | SystemInit(); 279 | #endif 280 | 281 | #ifndef __START 282 | #define __START _start 283 | #endif 284 | __START(); 285 | 286 | } 287 | 288 | 289 | /*---------------------------------------------------------------------------- 290 | Default Handler for Exceptions / Interrupts 291 | *----------------------------------------------------------------------------*/ 292 | void Default_Handler(void) { 293 | 294 | while(1); 295 | } 296 | -------------------------------------------------------------------------------- /cifar10/RTE/Device/ARMCM7_SP/startup_ARMCM7.s: -------------------------------------------------------------------------------- 1 | ;/**************************************************************************//** 2 | ; * @file startup_ARMCM7.s 3 | ; * @brief CMSIS Core Device Startup File for 4 | ; * ARMCM7 Device Series 5 | ; * @version V5.00 6 | ; * @date 02. March 2016 7 | ; ******************************************************************************/ 8 | ;/* 9 | ; * Copyright (c) 2009-2016 ARM Limited. All rights reserved. 10 | ; * 11 | ; * SPDX-License-Identifier: Apache-2.0 12 | ; * 13 | ; * Licensed under the Apache License, Version 2.0 (the License); you may 14 | ; * not use this file except in compliance with the License. 15 | ; * You may obtain a copy of the License at 16 | ; * 17 | ; * www.apache.org/licenses/LICENSE-2.0 18 | ; * 19 | ; * Unless required by applicable law or agreed to in writing, software 20 | ; * distributed under the License is distributed on an AS IS BASIS, WITHOUT 21 | ; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 | ; * See the License for the specific language governing permissions and 23 | ; * limitations under the License. 24 | ; */ 25 | 26 | ;/* 27 | ;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ 28 | ;*/ 29 | 30 | 31 | ; Stack Configuration 32 | ; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> 33 | ; 34 | 35 | Stack_Size EQU 0x00000400 36 | 37 | AREA STACK, NOINIT, READWRITE, ALIGN=3 38 | Stack_Mem SPACE Stack_Size 39 | __initial_sp 40 | 41 | 42 | ; Heap Configuration 43 | ; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> 44 | ; 45 | 46 | Heap_Size EQU 0x00000C00 47 | 48 | AREA HEAP, NOINIT, READWRITE, ALIGN=3 49 | __heap_base 50 | Heap_Mem SPACE Heap_Size 51 | __heap_limit 52 | 53 | 54 | PRESERVE8 55 | THUMB 56 | 57 | 58 | ; Vector Table Mapped to Address 0 at Reset 59 | 60 | AREA RESET, DATA, READONLY 61 | EXPORT __Vectors 62 | EXPORT __Vectors_End 63 | EXPORT __Vectors_Size 64 | 65 | __Vectors DCD __initial_sp ; Top of Stack 66 | DCD Reset_Handler ; Reset Handler 67 | DCD NMI_Handler ; NMI Handler 68 | DCD HardFault_Handler ; Hard Fault Handler 69 | DCD MemManage_Handler ; MPU Fault Handler 70 | DCD BusFault_Handler ; Bus Fault Handler 71 | DCD UsageFault_Handler ; Usage Fault Handler 72 | DCD 0 ; Reserved 73 | DCD 0 ; Reserved 74 | DCD 0 ; Reserved 75 | DCD 0 ; Reserved 76 | DCD SVC_Handler ; SVCall Handler 77 | DCD DebugMon_Handler ; Debug Monitor Handler 78 | DCD 0 ; Reserved 79 | DCD PendSV_Handler ; PendSV Handler 80 | DCD SysTick_Handler ; SysTick Handler 81 | 82 | ; External Interrupts 83 | DCD WDT_IRQHandler ; 0: Watchdog Timer 84 | DCD RTC_IRQHandler ; 1: Real Time Clock 85 | DCD TIM0_IRQHandler ; 2: Timer0 / Timer1 86 | DCD TIM2_IRQHandler ; 3: Timer2 / Timer3 87 | DCD MCIA_IRQHandler ; 4: MCIa 88 | DCD MCIB_IRQHandler ; 5: MCIb 89 | DCD UART0_IRQHandler ; 6: UART0 - DUT FPGA 90 | DCD UART1_IRQHandler ; 7: UART1 - DUT FPGA 91 | DCD UART2_IRQHandler ; 8: UART2 - DUT FPGA 92 | DCD UART4_IRQHandler ; 9: UART4 - not connected 93 | DCD AACI_IRQHandler ; 10: AACI / AC97 94 | DCD CLCD_IRQHandler ; 11: CLCD Combined Interrupt 95 | DCD ENET_IRQHandler ; 12: Ethernet 96 | DCD USBDC_IRQHandler ; 13: USB Device 97 | DCD USBHC_IRQHandler ; 14: USB Host Controller 98 | DCD CHLCD_IRQHandler ; 15: Character LCD 99 | DCD FLEXRAY_IRQHandler ; 16: Flexray 100 | DCD CAN_IRQHandler ; 17: CAN 101 | DCD LIN_IRQHandler ; 18: LIN 102 | DCD I2C_IRQHandler ; 19: I2C ADC/DAC 103 | DCD 0 ; 20: Reserved 104 | DCD 0 ; 21: Reserved 105 | DCD 0 ; 22: Reserved 106 | DCD 0 ; 23: Reserved 107 | DCD 0 ; 24: Reserved 108 | DCD 0 ; 25: Reserved 109 | DCD 0 ; 26: Reserved 110 | DCD 0 ; 27: Reserved 111 | DCD CPU_CLCD_IRQHandler ; 28: Reserved - CPU FPGA CLCD 112 | DCD 0 ; 29: Reserved - CPU FPGA 113 | DCD UART3_IRQHandler ; 30: UART3 - CPU FPGA 114 | DCD SPI_IRQHandler ; 31: SPI Touchscreen - CPU FPGA 115 | __Vectors_End 116 | 117 | __Vectors_Size EQU __Vectors_End - __Vectors 118 | 119 | AREA |.text|, CODE, READONLY 120 | 121 | 122 | ; Reset Handler 123 | 124 | Reset_Handler PROC 125 | EXPORT Reset_Handler [WEAK] 126 | IMPORT SystemInit 127 | IMPORT __main 128 | LDR R0, =SystemInit 129 | BLX R0 130 | LDR R0, =__main 131 | BX R0 132 | ENDP 133 | 134 | 135 | ; Dummy Exception Handlers (infinite loops which can be modified) 136 | 137 | NMI_Handler PROC 138 | EXPORT NMI_Handler [WEAK] 139 | B . 140 | ENDP 141 | HardFault_Handler\ 142 | PROC 143 | EXPORT HardFault_Handler [WEAK] 144 | B . 145 | ENDP 146 | MemManage_Handler\ 147 | PROC 148 | EXPORT MemManage_Handler [WEAK] 149 | B . 150 | ENDP 151 | BusFault_Handler\ 152 | PROC 153 | EXPORT BusFault_Handler [WEAK] 154 | B . 155 | ENDP 156 | UsageFault_Handler\ 157 | PROC 158 | EXPORT UsageFault_Handler [WEAK] 159 | B . 160 | ENDP 161 | SVC_Handler PROC 162 | EXPORT SVC_Handler [WEAK] 163 | B . 164 | ENDP 165 | DebugMon_Handler\ 166 | PROC 167 | EXPORT DebugMon_Handler [WEAK] 168 | B . 169 | ENDP 170 | PendSV_Handler PROC 171 | EXPORT PendSV_Handler [WEAK] 172 | B . 173 | ENDP 174 | SysTick_Handler PROC 175 | EXPORT SysTick_Handler [WEAK] 176 | B . 177 | ENDP 178 | 179 | Default_Handler PROC 180 | 181 | EXPORT WDT_IRQHandler [WEAK] 182 | EXPORT RTC_IRQHandler [WEAK] 183 | EXPORT TIM0_IRQHandler [WEAK] 184 | EXPORT TIM2_IRQHandler [WEAK] 185 | EXPORT MCIA_IRQHandler [WEAK] 186 | EXPORT MCIB_IRQHandler [WEAK] 187 | EXPORT UART0_IRQHandler [WEAK] 188 | EXPORT UART1_IRQHandler [WEAK] 189 | EXPORT UART2_IRQHandler [WEAK] 190 | EXPORT UART3_IRQHandler [WEAK] 191 | EXPORT UART4_IRQHandler [WEAK] 192 | EXPORT AACI_IRQHandler [WEAK] 193 | EXPORT CLCD_IRQHandler [WEAK] 194 | EXPORT ENET_IRQHandler [WEAK] 195 | EXPORT USBDC_IRQHandler [WEAK] 196 | EXPORT USBHC_IRQHandler [WEAK] 197 | EXPORT CHLCD_IRQHandler [WEAK] 198 | EXPORT FLEXRAY_IRQHandler [WEAK] 199 | EXPORT CAN_IRQHandler [WEAK] 200 | EXPORT LIN_IRQHandler [WEAK] 201 | EXPORT I2C_IRQHandler [WEAK] 202 | EXPORT CPU_CLCD_IRQHandler [WEAK] 203 | EXPORT SPI_IRQHandler [WEAK] 204 | 205 | WDT_IRQHandler 206 | RTC_IRQHandler 207 | TIM0_IRQHandler 208 | TIM2_IRQHandler 209 | MCIA_IRQHandler 210 | MCIB_IRQHandler 211 | UART0_IRQHandler 212 | UART1_IRQHandler 213 | UART2_IRQHandler 214 | UART3_IRQHandler 215 | UART4_IRQHandler 216 | AACI_IRQHandler 217 | CLCD_IRQHandler 218 | ENET_IRQHandler 219 | USBDC_IRQHandler 220 | USBHC_IRQHandler 221 | CHLCD_IRQHandler 222 | FLEXRAY_IRQHandler 223 | CAN_IRQHandler 224 | LIN_IRQHandler 225 | I2C_IRQHandler 226 | CPU_CLCD_IRQHandler 227 | SPI_IRQHandler 228 | B . 229 | 230 | ENDP 231 | 232 | 233 | ALIGN 234 | 235 | 236 | ; User Initial Stack & Heap 237 | 238 | IF :DEF:__MICROLIB 239 | 240 | EXPORT __initial_sp 241 | EXPORT __heap_base 242 | EXPORT __heap_limit 243 | 244 | ELSE 245 | 246 | IMPORT __use_two_region_memory 247 | EXPORT __user_initial_stackheap 248 | 249 | __user_initial_stackheap PROC 250 | LDR R0, = Heap_Mem 251 | LDR R1, =(Stack_Mem + Stack_Size) 252 | LDR R2, = (Heap_Mem + Heap_Size) 253 | LDR R3, = Stack_Mem 254 | BX LR 255 | ENDP 256 | 257 | ALIGN 258 | 259 | ENDIF 260 | 261 | 262 | END 263 | -------------------------------------------------------------------------------- /cifar10/RTE/Device/ARMCM7_SP/system_ARMCM7.c: -------------------------------------------------------------------------------- 1 | /**************************************************************************//** 2 | * @file system_ARMCM7.c 3 | * @brief CMSIS Device System Source File for 4 | * ARMCM7 Device Series 5 | * @version V5.00 6 | * @date 08. April 2016 7 | ******************************************************************************/ 8 | /* 9 | * Copyright (c) 2009-2016 ARM Limited. All rights reserved. 10 | * 11 | * SPDX-License-Identifier: Apache-2.0 12 | * 13 | * Licensed under the Apache License, Version 2.0 (the License); you may 14 | * not use this file except in compliance with the License. 15 | * You may obtain a copy of the License at 16 | * 17 | * www.apache.org/licenses/LICENSE-2.0 18 | * 19 | * Unless required by applicable law or agreed to in writing, software 20 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 21 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 | * See the License for the specific language governing permissions and 23 | * limitations under the License. 24 | */ 25 | 26 | #if defined (ARMCM7) 27 | #include "ARMCM7.h" 28 | #elif defined (ARMCM7_SP) 29 | #include "ARMCM7_SP.h" 30 | #elif defined (ARMCM7_DP) 31 | #include "ARMCM7_DP.h" 32 | #else 33 | #error device not specified! 34 | #endif 35 | 36 | /*---------------------------------------------------------------------------- 37 | Define clocks 38 | *----------------------------------------------------------------------------*/ 39 | #define XTAL ( 5000000U) /* Oscillator frequency */ 40 | 41 | #define SYSTEM_CLOCK (5 * XTAL) 42 | 43 | 44 | /*---------------------------------------------------------------------------- 45 | Externals 46 | *----------------------------------------------------------------------------*/ 47 | #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1) 48 | extern uint32_t __Vectors; 49 | #endif 50 | 51 | /*---------------------------------------------------------------------------- 52 | System Core Clock Variable 53 | *----------------------------------------------------------------------------*/ 54 | uint32_t SystemCoreClock = SYSTEM_CLOCK; 55 | 56 | 57 | /*---------------------------------------------------------------------------- 58 | System Core Clock update function 59 | *----------------------------------------------------------------------------*/ 60 | void SystemCoreClockUpdate (void) 61 | { 62 | SystemCoreClock = SYSTEM_CLOCK; 63 | } 64 | 65 | /*---------------------------------------------------------------------------- 66 | System initialization function 67 | *----------------------------------------------------------------------------*/ 68 | void SystemInit (void) 69 | { 70 | 71 | #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1) 72 | SCB->VTOR = (uint32_t) &__Vectors; 73 | #endif 74 | 75 | #if defined (__FPU_USED) && (__FPU_USED == 1) 76 | SCB->CPACR |= ((3U << 10*2) | /* set CP10 Full Access */ 77 | (3U << 11*2) ); /* set CP11 Full Access */ 78 | #endif 79 | 80 | #ifdef UNALIGNED_SUPPORT_DISABLE 81 | SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; 82 | #endif 83 | 84 | SystemCoreClock = SYSTEM_CLOCK; 85 | } 86 | -------------------------------------------------------------------------------- /cifar10/RTE/Device/STM32F407VGTx/startup_stm32f407xx.s: -------------------------------------------------------------------------------- 1 | ;******************** (C) COPYRIGHT 2017 STMicroelectronics ******************** 2 | ;* File Name : startup_stm32f407xx.s 3 | ;* Author : MCD Application Team 4 | ;* Description : STM32F407xx devices vector table for MDK-ARM toolchain. 5 | ;* This module performs: 6 | ;* - Set the initial SP 7 | ;* - Set the initial PC == Reset_Handler 8 | ;* - Set the vector table entries with the exceptions ISR address 9 | ;* - Branches to __main in the C library (which eventually 10 | ;* calls main()). 11 | ;* After Reset the CortexM4 processor is in Thread mode, 12 | ;* priority is Privileged, and the Stack is set to Main. 13 | ;* <<< Use Configuration Wizard in Context Menu >>> 14 | ;******************************************************************************* 15 | ; 16 | ;* Redistribution and use in source and binary forms, with or without modification, 17 | ;* are permitted provided that the following conditions are met: 18 | ;* 1. Redistributions of source code must retain the above copyright notice, 19 | ;* this list of conditions and the following disclaimer. 20 | ;* 2. Redistributions in binary form must reproduce the above copyright notice, 21 | ;* this list of conditions and the following disclaimer in the documentation 22 | ;* and/or other materials provided with the distribution. 23 | ;* 3. Neither the name of STMicroelectronics nor the names of its contributors 24 | ;* may be used to endorse or promote products derived from this software 25 | ;* without specific prior written permission. 26 | ;* 27 | ;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 28 | ;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 29 | ;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 30 | ;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 31 | ;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 32 | ;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 33 | ;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 34 | ;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 35 | ;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 36 | ;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 37 | ; 38 | ;******************************************************************************* 39 | 40 | ; Amount of memory (in bytes) allocated for Stack 41 | ; Tailor this value to your application needs 42 | ; Stack Configuration 43 | ; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> 44 | ; 45 | 46 | Stack_Size EQU 0x00000400 47 | 48 | AREA STACK, NOINIT, READWRITE, ALIGN=3 49 | Stack_Mem SPACE Stack_Size 50 | __initial_sp 51 | 52 | 53 | ; Heap Configuration 54 | ; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> 55 | ; 56 | 57 | Heap_Size EQU 0x00000200 58 | 59 | AREA HEAP, NOINIT, READWRITE, ALIGN=3 60 | __heap_base 61 | Heap_Mem SPACE Heap_Size 62 | __heap_limit 63 | 64 | PRESERVE8 65 | THUMB 66 | 67 | 68 | ; Vector Table Mapped to Address 0 at Reset 69 | AREA RESET, DATA, READONLY 70 | EXPORT __Vectors 71 | EXPORT __Vectors_End 72 | EXPORT __Vectors_Size 73 | 74 | __Vectors DCD __initial_sp ; Top of Stack 75 | DCD Reset_Handler ; Reset Handler 76 | DCD NMI_Handler ; NMI Handler 77 | DCD HardFault_Handler ; Hard Fault Handler 78 | DCD MemManage_Handler ; MPU Fault Handler 79 | DCD BusFault_Handler ; Bus Fault Handler 80 | DCD UsageFault_Handler ; Usage Fault Handler 81 | DCD 0 ; Reserved 82 | DCD 0 ; Reserved 83 | DCD 0 ; Reserved 84 | DCD 0 ; Reserved 85 | DCD SVC_Handler ; SVCall Handler 86 | DCD DebugMon_Handler ; Debug Monitor Handler 87 | DCD 0 ; Reserved 88 | DCD PendSV_Handler ; PendSV Handler 89 | DCD SysTick_Handler ; SysTick Handler 90 | 91 | ; External Interrupts 92 | DCD WWDG_IRQHandler ; Window WatchDog 93 | DCD PVD_IRQHandler ; PVD through EXTI Line detection 94 | DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line 95 | DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line 96 | DCD FLASH_IRQHandler ; FLASH 97 | DCD RCC_IRQHandler ; RCC 98 | DCD EXTI0_IRQHandler ; EXTI Line0 99 | DCD EXTI1_IRQHandler ; EXTI Line1 100 | DCD EXTI2_IRQHandler ; EXTI Line2 101 | DCD EXTI3_IRQHandler ; EXTI Line3 102 | DCD EXTI4_IRQHandler ; EXTI Line4 103 | DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 104 | DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 105 | DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 106 | DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 107 | DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 108 | DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 109 | DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 110 | DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s 111 | DCD CAN1_TX_IRQHandler ; CAN1 TX 112 | DCD CAN1_RX0_IRQHandler ; CAN1 RX0 113 | DCD CAN1_RX1_IRQHandler ; CAN1 RX1 114 | DCD CAN1_SCE_IRQHandler ; CAN1 SCE 115 | DCD EXTI9_5_IRQHandler ; External Line[9:5]s 116 | DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 117 | DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 118 | DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 119 | DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare 120 | DCD TIM2_IRQHandler ; TIM2 121 | DCD TIM3_IRQHandler ; TIM3 122 | DCD TIM4_IRQHandler ; TIM4 123 | DCD I2C1_EV_IRQHandler ; I2C1 Event 124 | DCD I2C1_ER_IRQHandler ; I2C1 Error 125 | DCD I2C2_EV_IRQHandler ; I2C2 Event 126 | DCD I2C2_ER_IRQHandler ; I2C2 Error 127 | DCD SPI1_IRQHandler ; SPI1 128 | DCD SPI2_IRQHandler ; SPI2 129 | DCD USART1_IRQHandler ; USART1 130 | DCD USART2_IRQHandler ; USART2 131 | DCD USART3_IRQHandler ; USART3 132 | DCD EXTI15_10_IRQHandler ; External Line[15:10]s 133 | DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line 134 | DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line 135 | DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 136 | DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 137 | DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 138 | DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare 139 | DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 140 | DCD FMC_IRQHandler ; FMC 141 | DCD SDIO_IRQHandler ; SDIO 142 | DCD TIM5_IRQHandler ; TIM5 143 | DCD SPI3_IRQHandler ; SPI3 144 | DCD UART4_IRQHandler ; UART4 145 | DCD UART5_IRQHandler ; UART5 146 | DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors 147 | DCD TIM7_IRQHandler ; TIM7 148 | DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 149 | DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 150 | DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 151 | DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 152 | DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 153 | DCD ETH_IRQHandler ; Ethernet 154 | DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line 155 | DCD CAN2_TX_IRQHandler ; CAN2 TX 156 | DCD CAN2_RX0_IRQHandler ; CAN2 RX0 157 | DCD CAN2_RX1_IRQHandler ; CAN2 RX1 158 | DCD CAN2_SCE_IRQHandler ; CAN2 SCE 159 | DCD OTG_FS_IRQHandler ; USB OTG FS 160 | DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 161 | DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 162 | DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 163 | DCD USART6_IRQHandler ; USART6 164 | DCD I2C3_EV_IRQHandler ; I2C3 event 165 | DCD I2C3_ER_IRQHandler ; I2C3 error 166 | DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out 167 | DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In 168 | DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI 169 | DCD OTG_HS_IRQHandler ; USB OTG HS 170 | DCD DCMI_IRQHandler ; DCMI 171 | DCD 0 ; Reserved 172 | DCD HASH_RNG_IRQHandler ; Hash and Rng 173 | DCD FPU_IRQHandler ; FPU 174 | 175 | 176 | __Vectors_End 177 | 178 | __Vectors_Size EQU __Vectors_End - __Vectors 179 | 180 | AREA |.text|, CODE, READONLY 181 | 182 | ; Reset handler 183 | Reset_Handler PROC 184 | EXPORT Reset_Handler [WEAK] 185 | IMPORT SystemInit 186 | IMPORT __main 187 | 188 | LDR R0, =SystemInit 189 | BLX R0 190 | LDR R0, =__main 191 | BX R0 192 | ENDP 193 | 194 | ; Dummy Exception Handlers (infinite loops which can be modified) 195 | 196 | NMI_Handler PROC 197 | EXPORT NMI_Handler [WEAK] 198 | B . 199 | ENDP 200 | HardFault_Handler\ 201 | PROC 202 | EXPORT HardFault_Handler [WEAK] 203 | B . 204 | ENDP 205 | MemManage_Handler\ 206 | PROC 207 | EXPORT MemManage_Handler [WEAK] 208 | B . 209 | ENDP 210 | BusFault_Handler\ 211 | PROC 212 | EXPORT BusFault_Handler [WEAK] 213 | B . 214 | ENDP 215 | UsageFault_Handler\ 216 | PROC 217 | EXPORT UsageFault_Handler [WEAK] 218 | B . 219 | ENDP 220 | SVC_Handler PROC 221 | EXPORT SVC_Handler [WEAK] 222 | B . 223 | ENDP 224 | DebugMon_Handler\ 225 | PROC 226 | EXPORT DebugMon_Handler [WEAK] 227 | B . 228 | ENDP 229 | PendSV_Handler PROC 230 | EXPORT PendSV_Handler [WEAK] 231 | B . 232 | ENDP 233 | SysTick_Handler PROC 234 | EXPORT SysTick_Handler [WEAK] 235 | B . 236 | ENDP 237 | 238 | Default_Handler PROC 239 | 240 | EXPORT WWDG_IRQHandler [WEAK] 241 | EXPORT PVD_IRQHandler [WEAK] 242 | EXPORT TAMP_STAMP_IRQHandler [WEAK] 243 | EXPORT RTC_WKUP_IRQHandler [WEAK] 244 | EXPORT FLASH_IRQHandler [WEAK] 245 | EXPORT RCC_IRQHandler [WEAK] 246 | EXPORT EXTI0_IRQHandler [WEAK] 247 | EXPORT EXTI1_IRQHandler [WEAK] 248 | EXPORT EXTI2_IRQHandler [WEAK] 249 | EXPORT EXTI3_IRQHandler [WEAK] 250 | EXPORT EXTI4_IRQHandler [WEAK] 251 | EXPORT DMA1_Stream0_IRQHandler [WEAK] 252 | EXPORT DMA1_Stream1_IRQHandler [WEAK] 253 | EXPORT DMA1_Stream2_IRQHandler [WEAK] 254 | EXPORT DMA1_Stream3_IRQHandler [WEAK] 255 | EXPORT DMA1_Stream4_IRQHandler [WEAK] 256 | EXPORT DMA1_Stream5_IRQHandler [WEAK] 257 | EXPORT DMA1_Stream6_IRQHandler [WEAK] 258 | EXPORT ADC_IRQHandler [WEAK] 259 | EXPORT CAN1_TX_IRQHandler [WEAK] 260 | EXPORT CAN1_RX0_IRQHandler [WEAK] 261 | EXPORT CAN1_RX1_IRQHandler [WEAK] 262 | EXPORT CAN1_SCE_IRQHandler [WEAK] 263 | EXPORT EXTI9_5_IRQHandler [WEAK] 264 | EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK] 265 | EXPORT TIM1_UP_TIM10_IRQHandler [WEAK] 266 | EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK] 267 | EXPORT TIM1_CC_IRQHandler [WEAK] 268 | EXPORT TIM2_IRQHandler [WEAK] 269 | EXPORT TIM3_IRQHandler [WEAK] 270 | EXPORT TIM4_IRQHandler [WEAK] 271 | EXPORT I2C1_EV_IRQHandler [WEAK] 272 | EXPORT I2C1_ER_IRQHandler [WEAK] 273 | EXPORT I2C2_EV_IRQHandler [WEAK] 274 | EXPORT I2C2_ER_IRQHandler [WEAK] 275 | EXPORT SPI1_IRQHandler [WEAK] 276 | EXPORT SPI2_IRQHandler [WEAK] 277 | EXPORT USART1_IRQHandler [WEAK] 278 | EXPORT USART2_IRQHandler [WEAK] 279 | EXPORT USART3_IRQHandler [WEAK] 280 | EXPORT EXTI15_10_IRQHandler [WEAK] 281 | EXPORT RTC_Alarm_IRQHandler [WEAK] 282 | EXPORT OTG_FS_WKUP_IRQHandler [WEAK] 283 | EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK] 284 | EXPORT TIM8_UP_TIM13_IRQHandler [WEAK] 285 | EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK] 286 | EXPORT TIM8_CC_IRQHandler [WEAK] 287 | EXPORT DMA1_Stream7_IRQHandler [WEAK] 288 | EXPORT FMC_IRQHandler [WEAK] 289 | EXPORT SDIO_IRQHandler [WEAK] 290 | EXPORT TIM5_IRQHandler [WEAK] 291 | EXPORT SPI3_IRQHandler [WEAK] 292 | EXPORT UART4_IRQHandler [WEAK] 293 | EXPORT UART5_IRQHandler [WEAK] 294 | EXPORT TIM6_DAC_IRQHandler [WEAK] 295 | EXPORT TIM7_IRQHandler [WEAK] 296 | EXPORT DMA2_Stream0_IRQHandler [WEAK] 297 | EXPORT DMA2_Stream1_IRQHandler [WEAK] 298 | EXPORT DMA2_Stream2_IRQHandler [WEAK] 299 | EXPORT DMA2_Stream3_IRQHandler [WEAK] 300 | EXPORT DMA2_Stream4_IRQHandler [WEAK] 301 | EXPORT ETH_IRQHandler [WEAK] 302 | EXPORT ETH_WKUP_IRQHandler [WEAK] 303 | EXPORT CAN2_TX_IRQHandler [WEAK] 304 | EXPORT CAN2_RX0_IRQHandler [WEAK] 305 | EXPORT CAN2_RX1_IRQHandler [WEAK] 306 | EXPORT CAN2_SCE_IRQHandler [WEAK] 307 | EXPORT OTG_FS_IRQHandler [WEAK] 308 | EXPORT DMA2_Stream5_IRQHandler [WEAK] 309 | EXPORT DMA2_Stream6_IRQHandler [WEAK] 310 | EXPORT DMA2_Stream7_IRQHandler [WEAK] 311 | EXPORT USART6_IRQHandler [WEAK] 312 | EXPORT I2C3_EV_IRQHandler [WEAK] 313 | EXPORT I2C3_ER_IRQHandler [WEAK] 314 | EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK] 315 | EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK] 316 | EXPORT OTG_HS_WKUP_IRQHandler [WEAK] 317 | EXPORT OTG_HS_IRQHandler [WEAK] 318 | EXPORT DCMI_IRQHandler [WEAK] 319 | EXPORT HASH_RNG_IRQHandler [WEAK] 320 | EXPORT FPU_IRQHandler [WEAK] 321 | 322 | WWDG_IRQHandler 323 | PVD_IRQHandler 324 | TAMP_STAMP_IRQHandler 325 | RTC_WKUP_IRQHandler 326 | FLASH_IRQHandler 327 | RCC_IRQHandler 328 | EXTI0_IRQHandler 329 | EXTI1_IRQHandler 330 | EXTI2_IRQHandler 331 | EXTI3_IRQHandler 332 | EXTI4_IRQHandler 333 | DMA1_Stream0_IRQHandler 334 | DMA1_Stream1_IRQHandler 335 | DMA1_Stream2_IRQHandler 336 | DMA1_Stream3_IRQHandler 337 | DMA1_Stream4_IRQHandler 338 | DMA1_Stream5_IRQHandler 339 | DMA1_Stream6_IRQHandler 340 | ADC_IRQHandler 341 | CAN1_TX_IRQHandler 342 | CAN1_RX0_IRQHandler 343 | CAN1_RX1_IRQHandler 344 | CAN1_SCE_IRQHandler 345 | EXTI9_5_IRQHandler 346 | TIM1_BRK_TIM9_IRQHandler 347 | TIM1_UP_TIM10_IRQHandler 348 | TIM1_TRG_COM_TIM11_IRQHandler 349 | TIM1_CC_IRQHandler 350 | TIM2_IRQHandler 351 | TIM3_IRQHandler 352 | TIM4_IRQHandler 353 | I2C1_EV_IRQHandler 354 | I2C1_ER_IRQHandler 355 | I2C2_EV_IRQHandler 356 | I2C2_ER_IRQHandler 357 | SPI1_IRQHandler 358 | SPI2_IRQHandler 359 | USART1_IRQHandler 360 | USART2_IRQHandler 361 | USART3_IRQHandler 362 | EXTI15_10_IRQHandler 363 | RTC_Alarm_IRQHandler 364 | OTG_FS_WKUP_IRQHandler 365 | TIM8_BRK_TIM12_IRQHandler 366 | TIM8_UP_TIM13_IRQHandler 367 | TIM8_TRG_COM_TIM14_IRQHandler 368 | TIM8_CC_IRQHandler 369 | DMA1_Stream7_IRQHandler 370 | FMC_IRQHandler 371 | SDIO_IRQHandler 372 | TIM5_IRQHandler 373 | SPI3_IRQHandler 374 | UART4_IRQHandler 375 | UART5_IRQHandler 376 | TIM6_DAC_IRQHandler 377 | TIM7_IRQHandler 378 | DMA2_Stream0_IRQHandler 379 | DMA2_Stream1_IRQHandler 380 | DMA2_Stream2_IRQHandler 381 | DMA2_Stream3_IRQHandler 382 | DMA2_Stream4_IRQHandler 383 | ETH_IRQHandler 384 | ETH_WKUP_IRQHandler 385 | CAN2_TX_IRQHandler 386 | CAN2_RX0_IRQHandler 387 | CAN2_RX1_IRQHandler 388 | CAN2_SCE_IRQHandler 389 | OTG_FS_IRQHandler 390 | DMA2_Stream5_IRQHandler 391 | DMA2_Stream6_IRQHandler 392 | DMA2_Stream7_IRQHandler 393 | USART6_IRQHandler 394 | I2C3_EV_IRQHandler 395 | I2C3_ER_IRQHandler 396 | OTG_HS_EP1_OUT_IRQHandler 397 | OTG_HS_EP1_IN_IRQHandler 398 | OTG_HS_WKUP_IRQHandler 399 | OTG_HS_IRQHandler 400 | DCMI_IRQHandler 401 | HASH_RNG_IRQHandler 402 | FPU_IRQHandler 403 | 404 | B . 405 | 406 | ENDP 407 | 408 | ALIGN 409 | 410 | ;******************************************************************************* 411 | ; User Stack and Heap initialization 412 | ;******************************************************************************* 413 | IF :DEF:__MICROLIB 414 | 415 | EXPORT __initial_sp 416 | EXPORT __heap_base 417 | EXPORT __heap_limit 418 | 419 | ELSE 420 | 421 | IMPORT __use_two_region_memory 422 | EXPORT __user_initial_stackheap 423 | 424 | __user_initial_stackheap 425 | 426 | LDR R0, = Heap_Mem 427 | LDR R1, =(Stack_Mem + Stack_Size) 428 | LDR R2, = (Heap_Mem + Heap_Size) 429 | LDR R3, = Stack_Mem 430 | BX LR 431 | 432 | ALIGN 433 | 434 | ENDIF 435 | 436 | END 437 | 438 | ;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** 439 | -------------------------------------------------------------------------------- /cifar10/RTE/Device/STM32F407VGTx/system_stm32f4xx-backup.c: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file system_stm32f4xx.c 4 | * @author MCD Application Team 5 | * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File. 6 | * 7 | * This file provides two functions and one global variable to be called from 8 | * user application: 9 | * - SystemInit(): This function is called at startup just after reset and 10 | * before branch to main program. This call is made inside 11 | * the "startup_stm32f4xx.s" file. 12 | * 13 | * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used 14 | * by the user application to setup the SysTick 15 | * timer or configure other parameters. 16 | * 17 | * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must 18 | * be called whenever the core clock is changed 19 | * during program execution. 20 | * 21 | * 22 | ****************************************************************************** 23 | * @attention 24 | * 25 | *

© COPYRIGHT 2017 STMicroelectronics

26 | * 27 | * Redistribution and use in source and binary forms, with or without modification, 28 | * are permitted provided that the following conditions are met: 29 | * 1. Redistributions of source code must retain the above copyright notice, 30 | * this list of conditions and the following disclaimer. 31 | * 2. Redistributions in binary form must reproduce the above copyright notice, 32 | * this list of conditions and the following disclaimer in the documentation 33 | * and/or other materials provided with the distribution. 34 | * 3. Neither the name of STMicroelectronics nor the names of its contributors 35 | * may be used to endorse or promote products derived from this software 36 | * without specific prior written permission. 37 | * 38 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 39 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 40 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 41 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 42 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 43 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 44 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 45 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 46 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 47 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 48 | * 49 | ****************************************************************************** 50 | */ 51 | 52 | /** @addtogroup CMSIS 53 | * @{ 54 | */ 55 | 56 | /** @addtogroup stm32f4xx_system 57 | * @{ 58 | */ 59 | 60 | /** @addtogroup STM32F4xx_System_Private_Includes 61 | * @{ 62 | */ 63 | 64 | 65 | #include "stm32f4xx.h" 66 | 67 | #if !defined (HSE_VALUE) 68 | #define HSE_VALUE ((uint32_t)25000000) /*!< Default value of the External oscillator in Hz */ 69 | #endif /* HSE_VALUE */ 70 | 71 | #if !defined (HSI_VALUE) 72 | #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/ 73 | #endif /* HSI_VALUE */ 74 | 75 | /** 76 | * @} 77 | */ 78 | 79 | /** @addtogroup STM32F4xx_System_Private_TypesDefinitions 80 | * @{ 81 | */ 82 | 83 | /** 84 | * @} 85 | */ 86 | 87 | /** @addtogroup STM32F4xx_System_Private_Defines 88 | * @{ 89 | */ 90 | 91 | /************************* Miscellaneous Configuration ************************/ 92 | /*!< Uncomment the following line if you need to use external SRAM or SDRAM as data memory */ 93 | #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\ 94 | || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ 95 | || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) 96 | /* #define DATA_IN_ExtSRAM */ 97 | #endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx || STM32F469xx || STM32F479xx ||\ 98 | STM32F412Zx || STM32F412Vx */ 99 | 100 | #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ 101 | || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) 102 | /* #define DATA_IN_ExtSDRAM */ 103 | #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx ||\ 104 | STM32F479xx */ 105 | 106 | /*!< Uncomment the following line if you need to relocate your vector Table in 107 | Internal SRAM. */ 108 | /* #define VECT_TAB_SRAM */ 109 | #define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. 110 | This value must be a multiple of 0x200. */ 111 | /******************************************************************************/ 112 | 113 | /** 114 | * @} 115 | */ 116 | 117 | /** @addtogroup STM32F4xx_System_Private_Macros 118 | * @{ 119 | */ 120 | 121 | /** 122 | * @} 123 | */ 124 | 125 | /** @addtogroup STM32F4xx_System_Private_Variables 126 | * @{ 127 | */ 128 | /* This variable is updated in three ways: 129 | 1) by calling CMSIS function SystemCoreClockUpdate() 130 | 2) by calling HAL API function HAL_RCC_GetHCLKFreq() 131 | 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency 132 | Note: If you use this function to configure the system clock; then there 133 | is no need to call the 2 first functions listed above, since SystemCoreClock 134 | variable is updated automatically. 135 | */ 136 | uint32_t SystemCoreClock = 16000000; 137 | const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; 138 | const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4}; 139 | /** 140 | * @} 141 | */ 142 | 143 | /** @addtogroup STM32F4xx_System_Private_FunctionPrototypes 144 | * @{ 145 | */ 146 | 147 | #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) 148 | static void SystemInit_ExtMemCtl(void); 149 | #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ 150 | 151 | /** 152 | * @} 153 | */ 154 | 155 | /** @addtogroup STM32F4xx_System_Private_Functions 156 | * @{ 157 | */ 158 | 159 | /** 160 | * @brief Setup the microcontroller system 161 | * Initialize the FPU setting, vector table location and External memory 162 | * configuration. 163 | * @param None 164 | * @retval None 165 | */ 166 | void SystemInit(void) 167 | { 168 | /* FPU settings ------------------------------------------------------------*/ 169 | #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) 170 | SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ 171 | #endif 172 | /* Reset the RCC clock configuration to the default reset state ------------*/ 173 | /* Set HSION bit */ 174 | RCC->CR |= (uint32_t)0x00000001; 175 | 176 | /* Reset CFGR register */ 177 | RCC->CFGR = 0x00000000; 178 | 179 | /* Reset HSEON, CSSON and PLLON bits */ 180 | RCC->CR &= (uint32_t)0xFEF6FFFF; 181 | 182 | /* Reset PLLCFGR register */ 183 | RCC->PLLCFGR = 0x24003010; 184 | 185 | /* Reset HSEBYP bit */ 186 | RCC->CR &= (uint32_t)0xFFFBFFFF; 187 | 188 | /* Disable all interrupts */ 189 | RCC->CIR = 0x00000000; 190 | 191 | #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) 192 | SystemInit_ExtMemCtl(); 193 | #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ 194 | 195 | /* Configure the Vector Table location add offset address ------------------*/ 196 | #ifdef VECT_TAB_SRAM 197 | SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ 198 | #else 199 | SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ 200 | #endif 201 | } 202 | 203 | /** 204 | * @brief Update SystemCoreClock variable according to Clock Register Values. 205 | * The SystemCoreClock variable contains the core clock (HCLK), it can 206 | * be used by the user application to setup the SysTick timer or configure 207 | * other parameters. 208 | * 209 | * @note Each time the core clock (HCLK) changes, this function must be called 210 | * to update SystemCoreClock variable value. Otherwise, any configuration 211 | * based on this variable will be incorrect. 212 | * 213 | * @note - The system frequency computed by this function is not the real 214 | * frequency in the chip. It is calculated based on the predefined 215 | * constant and the selected clock source: 216 | * 217 | * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) 218 | * 219 | * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) 220 | * 221 | * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 222 | * or HSI_VALUE(*) multiplied/divided by the PLL factors. 223 | * 224 | * (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value 225 | * 16 MHz) but the real value may vary depending on the variations 226 | * in voltage and temperature. 227 | * 228 | * (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (its value 229 | * depends on the application requirements), user has to ensure that HSE_VALUE 230 | * is same as the real frequency of the crystal used. Otherwise, this function 231 | * may have wrong result. 232 | * 233 | * - The result of this function could be not correct when using fractional 234 | * value for HSE crystal. 235 | * 236 | * @param None 237 | * @retval None 238 | */ 239 | void SystemCoreClockUpdate(void) 240 | { 241 | uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; 242 | 243 | /* Get SYSCLK source -------------------------------------------------------*/ 244 | tmp = RCC->CFGR & RCC_CFGR_SWS; 245 | 246 | switch (tmp) 247 | { 248 | case 0x00: /* HSI used as system clock source */ 249 | SystemCoreClock = HSI_VALUE; 250 | break; 251 | case 0x04: /* HSE used as system clock source */ 252 | SystemCoreClock = HSE_VALUE; 253 | break; 254 | case 0x08: /* PLL used as system clock source */ 255 | 256 | /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N 257 | SYSCLK = PLL_VCO / PLL_P 258 | */ 259 | pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; 260 | pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; 261 | 262 | if (pllsource != 0) 263 | { 264 | /* HSE used as PLL clock source */ 265 | pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); 266 | } 267 | else 268 | { 269 | /* HSI used as PLL clock source */ 270 | pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); 271 | } 272 | 273 | pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; 274 | SystemCoreClock = pllvco/pllp; 275 | break; 276 | default: 277 | SystemCoreClock = HSI_VALUE; 278 | break; 279 | } 280 | /* Compute HCLK frequency --------------------------------------------------*/ 281 | /* Get HCLK prescaler */ 282 | tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; 283 | /* HCLK frequency */ 284 | SystemCoreClock >>= tmp; 285 | } 286 | 287 | #if defined (DATA_IN_ExtSRAM) && defined (DATA_IN_ExtSDRAM) 288 | #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ 289 | || defined(STM32F469xx) || defined(STM32F479xx) 290 | /** 291 | * @brief Setup the external memory controller. 292 | * Called in startup_stm32f4xx.s before jump to main. 293 | * This function configures the external memories (SRAM/SDRAM) 294 | * This SRAM/SDRAM will be used as program data memory (including heap and stack). 295 | * @param None 296 | * @retval None 297 | */ 298 | void SystemInit_ExtMemCtl(void) 299 | { 300 | __IO uint32_t tmp = 0x00; 301 | 302 | register uint32_t tmpreg = 0, timeout = 0xFFFF; 303 | register __IO uint32_t index; 304 | 305 | /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface clock */ 306 | RCC->AHB1ENR |= 0x000001F8; 307 | 308 | /* Delay after an RCC peripheral clock enabling */ 309 | tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN); 310 | 311 | /* Connect PDx pins to FMC Alternate function */ 312 | GPIOD->AFR[0] = 0x00CCC0CC; 313 | GPIOD->AFR[1] = 0xCCCCCCCC; 314 | /* Configure PDx pins in Alternate function mode */ 315 | GPIOD->MODER = 0xAAAA0A8A; 316 | /* Configure PDx pins speed to 100 MHz */ 317 | GPIOD->OSPEEDR = 0xFFFF0FCF; 318 | /* Configure PDx pins Output type to push-pull */ 319 | GPIOD->OTYPER = 0x00000000; 320 | /* No pull-up, pull-down for PDx pins */ 321 | GPIOD->PUPDR = 0x00000000; 322 | 323 | /* Connect PEx pins to FMC Alternate function */ 324 | GPIOE->AFR[0] = 0xC00CC0CC; 325 | GPIOE->AFR[1] = 0xCCCCCCCC; 326 | /* Configure PEx pins in Alternate function mode */ 327 | GPIOE->MODER = 0xAAAA828A; 328 | /* Configure PEx pins speed to 100 MHz */ 329 | GPIOE->OSPEEDR = 0xFFFFC3CF; 330 | /* Configure PEx pins Output type to push-pull */ 331 | GPIOE->OTYPER = 0x00000000; 332 | /* No pull-up, pull-down for PEx pins */ 333 | GPIOE->PUPDR = 0x00000000; 334 | 335 | /* Connect PFx pins to FMC Alternate function */ 336 | GPIOF->AFR[0] = 0xCCCCCCCC; 337 | GPIOF->AFR[1] = 0xCCCCCCCC; 338 | /* Configure PFx pins in Alternate function mode */ 339 | GPIOF->MODER = 0xAA800AAA; 340 | /* Configure PFx pins speed to 50 MHz */ 341 | GPIOF->OSPEEDR = 0xAA800AAA; 342 | /* Configure PFx pins Output type to push-pull */ 343 | GPIOF->OTYPER = 0x00000000; 344 | /* No pull-up, pull-down for PFx pins */ 345 | GPIOF->PUPDR = 0x00000000; 346 | 347 | /* Connect PGx pins to FMC Alternate function */ 348 | GPIOG->AFR[0] = 0xCCCCCCCC; 349 | GPIOG->AFR[1] = 0xCCCCCCCC; 350 | /* Configure PGx pins in Alternate function mode */ 351 | GPIOG->MODER = 0xAAAAAAAA; 352 | /* Configure PGx pins speed to 50 MHz */ 353 | GPIOG->OSPEEDR = 0xAAAAAAAA; 354 | /* Configure PGx pins Output type to push-pull */ 355 | GPIOG->OTYPER = 0x00000000; 356 | /* No pull-up, pull-down for PGx pins */ 357 | GPIOG->PUPDR = 0x00000000; 358 | 359 | /* Connect PHx pins to FMC Alternate function */ 360 | GPIOH->AFR[0] = 0x00C0CC00; 361 | GPIOH->AFR[1] = 0xCCCCCCCC; 362 | /* Configure PHx pins in Alternate function mode */ 363 | GPIOH->MODER = 0xAAAA08A0; 364 | /* Configure PHx pins speed to 50 MHz */ 365 | GPIOH->OSPEEDR = 0xAAAA08A0; 366 | /* Configure PHx pins Output type to push-pull */ 367 | GPIOH->OTYPER = 0x00000000; 368 | /* No pull-up, pull-down for PHx pins */ 369 | GPIOH->PUPDR = 0x00000000; 370 | 371 | /* Connect PIx pins to FMC Alternate function */ 372 | GPIOI->AFR[0] = 0xCCCCCCCC; 373 | GPIOI->AFR[1] = 0x00000CC0; 374 | /* Configure PIx pins in Alternate function mode */ 375 | GPIOI->MODER = 0x0028AAAA; 376 | /* Configure PIx pins speed to 50 MHz */ 377 | GPIOI->OSPEEDR = 0x0028AAAA; 378 | /* Configure PIx pins Output type to push-pull */ 379 | GPIOI->OTYPER = 0x00000000; 380 | /* No pull-up, pull-down for PIx pins */ 381 | GPIOI->PUPDR = 0x00000000; 382 | 383 | /*-- FMC Configuration -------------------------------------------------------*/ 384 | /* Enable the FMC interface clock */ 385 | RCC->AHB3ENR |= 0x00000001; 386 | /* Delay after an RCC peripheral clock enabling */ 387 | tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); 388 | 389 | FMC_Bank5_6->SDCR[0] = 0x000019E4; 390 | FMC_Bank5_6->SDTR[0] = 0x01115351; 391 | 392 | /* SDRAM initialization sequence */ 393 | /* Clock enable command */ 394 | FMC_Bank5_6->SDCMR = 0x00000011; 395 | tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 396 | while((tmpreg != 0) && (timeout-- > 0)) 397 | { 398 | tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 399 | } 400 | 401 | /* Delay */ 402 | for (index = 0; index<1000; index++); 403 | 404 | /* PALL command */ 405 | FMC_Bank5_6->SDCMR = 0x00000012; 406 | timeout = 0xFFFF; 407 | while((tmpreg != 0) && (timeout-- > 0)) 408 | { 409 | tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 410 | } 411 | 412 | /* Auto refresh command */ 413 | FMC_Bank5_6->SDCMR = 0x00000073; 414 | timeout = 0xFFFF; 415 | while((tmpreg != 0) && (timeout-- > 0)) 416 | { 417 | tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 418 | } 419 | 420 | /* MRD register program */ 421 | FMC_Bank5_6->SDCMR = 0x00046014; 422 | timeout = 0xFFFF; 423 | while((tmpreg != 0) && (timeout-- > 0)) 424 | { 425 | tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 426 | } 427 | 428 | /* Set refresh count */ 429 | tmpreg = FMC_Bank5_6->SDRTR; 430 | FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1)); 431 | 432 | /* Disable write protection */ 433 | tmpreg = FMC_Bank5_6->SDCR[0]; 434 | FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF); 435 | 436 | #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) 437 | /* Configure and enable Bank1_SRAM2 */ 438 | FMC_Bank1->BTCR[2] = 0x00001011; 439 | FMC_Bank1->BTCR[3] = 0x00000201; 440 | FMC_Bank1E->BWTR[2] = 0x0fffffff; 441 | #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ 442 | #if defined(STM32F469xx) || defined(STM32F479xx) 443 | /* Configure and enable Bank1_SRAM2 */ 444 | FMC_Bank1->BTCR[2] = 0x00001091; 445 | FMC_Bank1->BTCR[3] = 0x00110212; 446 | FMC_Bank1E->BWTR[2] = 0x0fffffff; 447 | #endif /* STM32F469xx || STM32F479xx */ 448 | 449 | (void)(tmp); 450 | } 451 | #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ 452 | #elif defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) 453 | /** 454 | * @brief Setup the external memory controller. 455 | * Called in startup_stm32f4xx.s before jump to main. 456 | * This function configures the external memories (SRAM/SDRAM) 457 | * This SRAM/SDRAM will be used as program data memory (including heap and stack). 458 | * @param None 459 | * @retval None 460 | */ 461 | void SystemInit_ExtMemCtl(void) 462 | { 463 | __IO uint32_t tmp = 0x00; 464 | #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ 465 | || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) 466 | #if defined (DATA_IN_ExtSDRAM) 467 | register uint32_t tmpreg = 0, timeout = 0xFFFF; 468 | register __IO uint32_t index; 469 | 470 | #if defined(STM32F446xx) 471 | /* Enable GPIOA, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG interface 472 | clock */ 473 | RCC->AHB1ENR |= 0x0000007D; 474 | #else 475 | /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface 476 | clock */ 477 | RCC->AHB1ENR |= 0x000001F8; 478 | #endif /* STM32F446xx */ 479 | /* Delay after an RCC peripheral clock enabling */ 480 | tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN); 481 | 482 | #if defined(STM32F446xx) 483 | /* Connect PAx pins to FMC Alternate function */ 484 | GPIOA->AFR[0] |= 0xC0000000; 485 | GPIOA->AFR[1] |= 0x00000000; 486 | /* Configure PDx pins in Alternate function mode */ 487 | GPIOA->MODER |= 0x00008000; 488 | /* Configure PDx pins speed to 50 MHz */ 489 | GPIOA->OSPEEDR |= 0x00008000; 490 | /* Configure PDx pins Output type to push-pull */ 491 | GPIOA->OTYPER |= 0x00000000; 492 | /* No pull-up, pull-down for PDx pins */ 493 | GPIOA->PUPDR |= 0x00000000; 494 | 495 | /* Connect PCx pins to FMC Alternate function */ 496 | GPIOC->AFR[0] |= 0x00CC0000; 497 | GPIOC->AFR[1] |= 0x00000000; 498 | /* Configure PDx pins in Alternate function mode */ 499 | GPIOC->MODER |= 0x00000A00; 500 | /* Configure PDx pins speed to 50 MHz */ 501 | GPIOC->OSPEEDR |= 0x00000A00; 502 | /* Configure PDx pins Output type to push-pull */ 503 | GPIOC->OTYPER |= 0x00000000; 504 | /* No pull-up, pull-down for PDx pins */ 505 | GPIOC->PUPDR |= 0x00000000; 506 | #endif /* STM32F446xx */ 507 | 508 | /* Connect PDx pins to FMC Alternate function */ 509 | GPIOD->AFR[0] = 0x000000CC; 510 | GPIOD->AFR[1] = 0xCC000CCC; 511 | /* Configure PDx pins in Alternate function mode */ 512 | GPIOD->MODER = 0xA02A000A; 513 | /* Configure PDx pins speed to 50 MHz */ 514 | GPIOD->OSPEEDR = 0xA02A000A; 515 | /* Configure PDx pins Output type to push-pull */ 516 | GPIOD->OTYPER = 0x00000000; 517 | /* No pull-up, pull-down for PDx pins */ 518 | GPIOD->PUPDR = 0x00000000; 519 | 520 | /* Connect PEx pins to FMC Alternate function */ 521 | GPIOE->AFR[0] = 0xC00000CC; 522 | GPIOE->AFR[1] = 0xCCCCCCCC; 523 | /* Configure PEx pins in Alternate function mode */ 524 | GPIOE->MODER = 0xAAAA800A; 525 | /* Configure PEx pins speed to 50 MHz */ 526 | GPIOE->OSPEEDR = 0xAAAA800A; 527 | /* Configure PEx pins Output type to push-pull */ 528 | GPIOE->OTYPER = 0x00000000; 529 | /* No pull-up, pull-down for PEx pins */ 530 | GPIOE->PUPDR = 0x00000000; 531 | 532 | /* Connect PFx pins to FMC Alternate function */ 533 | GPIOF->AFR[0] = 0xCCCCCCCC; 534 | GPIOF->AFR[1] = 0xCCCCCCCC; 535 | /* Configure PFx pins in Alternate function mode */ 536 | GPIOF->MODER = 0xAA800AAA; 537 | /* Configure PFx pins speed to 50 MHz */ 538 | GPIOF->OSPEEDR = 0xAA800AAA; 539 | /* Configure PFx pins Output type to push-pull */ 540 | GPIOF->OTYPER = 0x00000000; 541 | /* No pull-up, pull-down for PFx pins */ 542 | GPIOF->PUPDR = 0x00000000; 543 | 544 | /* Connect PGx pins to FMC Alternate function */ 545 | GPIOG->AFR[0] = 0xCCCCCCCC; 546 | GPIOG->AFR[1] = 0xCCCCCCCC; 547 | /* Configure PGx pins in Alternate function mode */ 548 | GPIOG->MODER = 0xAAAAAAAA; 549 | /* Configure PGx pins speed to 50 MHz */ 550 | GPIOG->OSPEEDR = 0xAAAAAAAA; 551 | /* Configure PGx pins Output type to push-pull */ 552 | GPIOG->OTYPER = 0x00000000; 553 | /* No pull-up, pull-down for PGx pins */ 554 | GPIOG->PUPDR = 0x00000000; 555 | 556 | #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ 557 | || defined(STM32F469xx) || defined(STM32F479xx) 558 | /* Connect PHx pins to FMC Alternate function */ 559 | GPIOH->AFR[0] = 0x00C0CC00; 560 | GPIOH->AFR[1] = 0xCCCCCCCC; 561 | /* Configure PHx pins in Alternate function mode */ 562 | GPIOH->MODER = 0xAAAA08A0; 563 | /* Configure PHx pins speed to 50 MHz */ 564 | GPIOH->OSPEEDR = 0xAAAA08A0; 565 | /* Configure PHx pins Output type to push-pull */ 566 | GPIOH->OTYPER = 0x00000000; 567 | /* No pull-up, pull-down for PHx pins */ 568 | GPIOH->PUPDR = 0x00000000; 569 | 570 | /* Connect PIx pins to FMC Alternate function */ 571 | GPIOI->AFR[0] = 0xCCCCCCCC; 572 | GPIOI->AFR[1] = 0x00000CC0; 573 | /* Configure PIx pins in Alternate function mode */ 574 | GPIOI->MODER = 0x0028AAAA; 575 | /* Configure PIx pins speed to 50 MHz */ 576 | GPIOI->OSPEEDR = 0x0028AAAA; 577 | /* Configure PIx pins Output type to push-pull */ 578 | GPIOI->OTYPER = 0x00000000; 579 | /* No pull-up, pull-down for PIx pins */ 580 | GPIOI->PUPDR = 0x00000000; 581 | #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ 582 | 583 | /*-- FMC Configuration -------------------------------------------------------*/ 584 | /* Enable the FMC interface clock */ 585 | RCC->AHB3ENR |= 0x00000001; 586 | /* Delay after an RCC peripheral clock enabling */ 587 | tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); 588 | 589 | /* Configure and enable SDRAM bank1 */ 590 | #if defined(STM32F446xx) 591 | FMC_Bank5_6->SDCR[0] = 0x00001954; 592 | #else 593 | FMC_Bank5_6->SDCR[0] = 0x000019E4; 594 | #endif /* STM32F446xx */ 595 | FMC_Bank5_6->SDTR[0] = 0x01115351; 596 | 597 | /* SDRAM initialization sequence */ 598 | /* Clock enable command */ 599 | FMC_Bank5_6->SDCMR = 0x00000011; 600 | tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 601 | while((tmpreg != 0) && (timeout-- > 0)) 602 | { 603 | tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 604 | } 605 | 606 | /* Delay */ 607 | for (index = 0; index<1000; index++); 608 | 609 | /* PALL command */ 610 | FMC_Bank5_6->SDCMR = 0x00000012; 611 | timeout = 0xFFFF; 612 | while((tmpreg != 0) && (timeout-- > 0)) 613 | { 614 | tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 615 | } 616 | 617 | /* Auto refresh command */ 618 | #if defined(STM32F446xx) 619 | FMC_Bank5_6->SDCMR = 0x000000F3; 620 | #else 621 | FMC_Bank5_6->SDCMR = 0x00000073; 622 | #endif /* STM32F446xx */ 623 | timeout = 0xFFFF; 624 | while((tmpreg != 0) && (timeout-- > 0)) 625 | { 626 | tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 627 | } 628 | 629 | /* MRD register program */ 630 | #if defined(STM32F446xx) 631 | FMC_Bank5_6->SDCMR = 0x00044014; 632 | #else 633 | FMC_Bank5_6->SDCMR = 0x00046014; 634 | #endif /* STM32F446xx */ 635 | timeout = 0xFFFF; 636 | while((tmpreg != 0) && (timeout-- > 0)) 637 | { 638 | tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 639 | } 640 | 641 | /* Set refresh count */ 642 | tmpreg = FMC_Bank5_6->SDRTR; 643 | #if defined(STM32F446xx) 644 | FMC_Bank5_6->SDRTR = (tmpreg | (0x0000050C<<1)); 645 | #else 646 | FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1)); 647 | #endif /* STM32F446xx */ 648 | 649 | /* Disable write protection */ 650 | tmpreg = FMC_Bank5_6->SDCR[0]; 651 | FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF); 652 | #endif /* DATA_IN_ExtSDRAM */ 653 | #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ 654 | 655 | #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\ 656 | || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ 657 | || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) 658 | 659 | #if defined(DATA_IN_ExtSRAM) 660 | /*-- GPIOs Configuration -----------------------------------------------------*/ 661 | /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ 662 | RCC->AHB1ENR |= 0x00000078; 663 | /* Delay after an RCC peripheral clock enabling */ 664 | tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN); 665 | 666 | /* Connect PDx pins to FMC Alternate function */ 667 | GPIOD->AFR[0] = 0x00CCC0CC; 668 | GPIOD->AFR[1] = 0xCCCCCCCC; 669 | /* Configure PDx pins in Alternate function mode */ 670 | GPIOD->MODER = 0xAAAA0A8A; 671 | /* Configure PDx pins speed to 100 MHz */ 672 | GPIOD->OSPEEDR = 0xFFFF0FCF; 673 | /* Configure PDx pins Output type to push-pull */ 674 | GPIOD->OTYPER = 0x00000000; 675 | /* No pull-up, pull-down for PDx pins */ 676 | GPIOD->PUPDR = 0x00000000; 677 | 678 | /* Connect PEx pins to FMC Alternate function */ 679 | GPIOE->AFR[0] = 0xC00CC0CC; 680 | GPIOE->AFR[1] = 0xCCCCCCCC; 681 | /* Configure PEx pins in Alternate function mode */ 682 | GPIOE->MODER = 0xAAAA828A; 683 | /* Configure PEx pins speed to 100 MHz */ 684 | GPIOE->OSPEEDR = 0xFFFFC3CF; 685 | /* Configure PEx pins Output type to push-pull */ 686 | GPIOE->OTYPER = 0x00000000; 687 | /* No pull-up, pull-down for PEx pins */ 688 | GPIOE->PUPDR = 0x00000000; 689 | 690 | /* Connect PFx pins to FMC Alternate function */ 691 | GPIOF->AFR[0] = 0x00CCCCCC; 692 | GPIOF->AFR[1] = 0xCCCC0000; 693 | /* Configure PFx pins in Alternate function mode */ 694 | GPIOF->MODER = 0xAA000AAA; 695 | /* Configure PFx pins speed to 100 MHz */ 696 | GPIOF->OSPEEDR = 0xFF000FFF; 697 | /* Configure PFx pins Output type to push-pull */ 698 | GPIOF->OTYPER = 0x00000000; 699 | /* No pull-up, pull-down for PFx pins */ 700 | GPIOF->PUPDR = 0x00000000; 701 | 702 | /* Connect PGx pins to FMC Alternate function */ 703 | GPIOG->AFR[0] = 0x00CCCCCC; 704 | GPIOG->AFR[1] = 0x000000C0; 705 | /* Configure PGx pins in Alternate function mode */ 706 | GPIOG->MODER = 0x00085AAA; 707 | /* Configure PGx pins speed to 100 MHz */ 708 | GPIOG->OSPEEDR = 0x000CAFFF; 709 | /* Configure PGx pins Output type to push-pull */ 710 | GPIOG->OTYPER = 0x00000000; 711 | /* No pull-up, pull-down for PGx pins */ 712 | GPIOG->PUPDR = 0x00000000; 713 | 714 | /*-- FMC/FSMC Configuration --------------------------------------------------*/ 715 | /* Enable the FMC/FSMC interface clock */ 716 | RCC->AHB3ENR |= 0x00000001; 717 | 718 | #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) 719 | /* Delay after an RCC peripheral clock enabling */ 720 | tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); 721 | /* Configure and enable Bank1_SRAM2 */ 722 | FMC_Bank1->BTCR[2] = 0x00001011; 723 | FMC_Bank1->BTCR[3] = 0x00000201; 724 | FMC_Bank1E->BWTR[2] = 0x0fffffff; 725 | #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ 726 | #if defined(STM32F469xx) || defined(STM32F479xx) 727 | /* Delay after an RCC peripheral clock enabling */ 728 | tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); 729 | /* Configure and enable Bank1_SRAM2 */ 730 | FMC_Bank1->BTCR[2] = 0x00001091; 731 | FMC_Bank1->BTCR[3] = 0x00110212; 732 | FMC_Bank1E->BWTR[2] = 0x0fffffff; 733 | #endif /* STM32F469xx || STM32F479xx */ 734 | #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)\ 735 | || defined(STM32F412Zx) || defined(STM32F412Vx) 736 | /* Delay after an RCC peripheral clock enabling */ 737 | tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN); 738 | /* Configure and enable Bank1_SRAM2 */ 739 | FSMC_Bank1->BTCR[2] = 0x00001011; 740 | FSMC_Bank1->BTCR[3] = 0x00000201; 741 | FSMC_Bank1E->BWTR[2] = 0x0FFFFFFF; 742 | #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F412Zx || STM32F412Vx */ 743 | 744 | #endif /* DATA_IN_ExtSRAM */ 745 | #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\ 746 | STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx */ 747 | (void)(tmp); 748 | } 749 | #endif /* DATA_IN_ExtSRAM && DATA_IN_ExtSDRAM */ 750 | /** 751 | * @} 752 | */ 753 | 754 | /** 755 | * @} 756 | */ 757 | 758 | /** 759 | * @} 760 | */ 761 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 762 | -------------------------------------------------------------------------------- /cifar10/RTE/Device/STM32F407VGTx/system_stm32f4xx.c: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file system_stm32f4xx.c 4 | * @author MCD Application Team 5 | * @version V1.0.0 6 | * @date 30-September-2011 7 | * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File. 8 | * This file contains the system clock configuration for STM32F4xx devices, 9 | * and is generated by the clock configuration tool 10 | * stm32f4xx_Clock_Configuration_V1.0.0.xls 11 | * 12 | * 1. This file provides two functions and one global variable to be called from 13 | * user application: 14 | * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier 15 | * and Divider factors, AHB/APBx prescalers and Flash settings), 16 | * depending on the configuration made in the clock xls tool. 17 | * This function is called at startup just after reset and 18 | * before branch to main program. This call is made inside 19 | * the "startup_stm32f4xx.s" file. 20 | * 21 | * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used 22 | * by the user application to setup the SysTick 23 | * timer or configure other parameters. 24 | * 25 | * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must 26 | * be called whenever the core clock is changed 27 | * during program execution. 28 | * 29 | * 2. After each device reset the HSI (16 MHz) is used as system clock source. 30 | * Then SystemInit() function is called, in "startup_stm32f4xx.s" file, to 31 | * configure the system clock before to branch to main program. 32 | * 33 | * 3. If the system clock source selected by user fails to startup, the SystemInit() 34 | * function will do nothing and HSI still used as system clock source. User can 35 | * add some code to deal with this issue inside the SetSysClock() function. 36 | * 37 | * 4. The default value of HSE crystal is set to 8MHz, refer to "HSE_VALUE" define 38 | * in "stm32f4xx.h" file. When HSE is used as system clock source, directly or 39 | * through PLL, and you are using different crystal you have to adapt the HSE 40 | * value to your own configuration. 41 | * 42 | * 5. This file configures the system clock as follows: 43 | *============================================================================= 44 | *============================================================================= 45 | * Supported STM32F4xx device revision | Rev A 46 | *----------------------------------------------------------------------------- 47 | * System Clock source | PLL (HSE) 48 | *----------------------------------------------------------------------------- 49 | * SYSCLK(Hz) | 168000000 50 | *----------------------------------------------------------------------------- 51 | * HCLK(Hz) | 168000000 52 | *----------------------------------------------------------------------------- 53 | * AHB Prescaler | 1 54 | *----------------------------------------------------------------------------- 55 | * APB1 Prescaler | 4 56 | *----------------------------------------------------------------------------- 57 | * APB2 Prescaler | 2 58 | *----------------------------------------------------------------------------- 59 | * HSE Frequency(Hz) | 8000000 60 | *----------------------------------------------------------------------------- 61 | * PLL_M | 8 62 | *----------------------------------------------------------------------------- 63 | * PLL_N | 336 64 | *----------------------------------------------------------------------------- 65 | * PLL_P | 2 66 | *----------------------------------------------------------------------------- 67 | * PLL_Q | 7 68 | *----------------------------------------------------------------------------- 69 | * PLLI2S_N | NA 70 | *----------------------------------------------------------------------------- 71 | * PLLI2S_R | NA 72 | *----------------------------------------------------------------------------- 73 | * I2S input clock | NA 74 | *----------------------------------------------------------------------------- 75 | * VDD(V) | 3.3 76 | *----------------------------------------------------------------------------- 77 | * Main regulator output voltage | Scale1 mode 78 | *----------------------------------------------------------------------------- 79 | * Flash Latency(WS) | 5 80 | *----------------------------------------------------------------------------- 81 | * Prefetch Buffer | OFF 82 | *----------------------------------------------------------------------------- 83 | * Instruction cache | ON 84 | *----------------------------------------------------------------------------- 85 | * Data cache | ON 86 | *----------------------------------------------------------------------------- 87 | * Require 48MHz for USB OTG FS, | Enabled 88 | * SDIO and RNG clock | 89 | *----------------------------------------------------------------------------- 90 | *============================================================================= 91 | ****************************************************************************** 92 | * @attention 93 | * 94 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 95 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE 96 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY 97 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING 98 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE 99 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 100 | * 101 | *

© COPYRIGHT 2011 STMicroelectronics

102 | ****************************************************************************** 103 | */ 104 | 105 | /** @addtogroup CMSIS 106 | * @{ 107 | */ 108 | 109 | /** @addtogroup stm32f4xx_system 110 | * @{ 111 | */ 112 | 113 | /** @addtogroup STM32F4xx_System_Private_Includes 114 | * @{ 115 | */ 116 | 117 | #include "stm32f4xx.h" 118 | 119 | /** 120 | * @} 121 | */ 122 | 123 | /** @addtogroup STM32F4xx_System_Private_TypesDefinitions 124 | * @{ 125 | */ 126 | 127 | /** 128 | * @} 129 | */ 130 | 131 | /** @addtogroup STM32F4xx_System_Private_Defines 132 | * @{ 133 | */ 134 | #if !defined (HSE_VALUE) 135 | #define HSE_VALUE ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz */ 136 | #endif /* HSE_VALUE */ 137 | 138 | #if !defined (HSI_VALUE) 139 | #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/ 140 | #endif /* HSI_VALUE */ 141 | //External High Speed oscillator (HSE) Startup Timeout value. 142 | #if !defined (HSE_STARTUP_TIMEOUT) 143 | #define HSE_STARTUP_TIMEOUT ((uint16_t)0x0500) 144 | #endif /* HSE_STARTUP_TIMEOUT */ 145 | /************************* Miscellaneous Configuration ************************/ 146 | /*!< Uncomment the following line if you need to use external SRAM mounted 147 | on STM324xG_EVAL board as data memory */ 148 | /* #define DATA_IN_ExtSRAM */ 149 | 150 | /*!< Uncomment the following line if you need to relocate your vector Table in 151 | Internal SRAM. */ 152 | /* #define VECT_TAB_SRAM */ 153 | #define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. 154 | This value must be a multiple of 0x200. */ 155 | /******************************************************************************/ 156 | 157 | /************************* PLL Parameters *************************************/ 158 | /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */ 159 | #define PLL_M 8 160 | #define PLL_N 336 161 | 162 | /* SYSCLK = PLL_VCO / PLL_P */ 163 | #define PLL_P 2 164 | 165 | /* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */ 166 | #define PLL_Q 7 167 | 168 | /******************************************************************************/ 169 | 170 | /** 171 | * @} 172 | */ 173 | 174 | /** @addtogroup STM32F4xx_System_Private_Macros 175 | * @{ 176 | */ 177 | 178 | /** 179 | * @} 180 | */ 181 | 182 | /** @addtogroup STM32F4xx_System_Private_Variables 183 | * @{ 184 | */ 185 | 186 | uint32_t SystemCoreClock = 168000000; 187 | 188 | //__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; 189 | const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; 190 | /** 191 | * @} 192 | */ 193 | 194 | /** @addtogroup STM32F4xx_System_Private_FunctionPrototypes 195 | * @{ 196 | */ 197 | 198 | static void SetSysClock(void); 199 | #ifdef DATA_IN_ExtSRAM 200 | static void SystemInit_ExtMemCtl(void); 201 | #endif /* DATA_IN_ExtSRAM */ 202 | 203 | /** 204 | * @} 205 | */ 206 | 207 | /** @addtogroup STM32F4xx_System_Private_Functions 208 | * @{ 209 | */ 210 | 211 | /** 212 | * @brief Setup the microcontroller system 213 | * Initialize the Embedded Flash Interface, the PLL and update the 214 | * SystemFrequency variable. 215 | * @param None 216 | * @retval None 217 | */ 218 | void SystemInit(void) 219 | { 220 | /* FPU settings ------------------------------------------------------------*/ 221 | #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) 222 | SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ 223 | #endif 224 | 225 | /* Reset the RCC clock configuration to the default reset state ------------*/ 226 | /* Set HSION bit */ 227 | RCC->CR |= (uint32_t)0x00000001; 228 | 229 | /* Reset CFGR register */ 230 | RCC->CFGR = 0x00000000; 231 | 232 | /* Reset HSEON, CSSON and PLLON bits */ 233 | RCC->CR &= (uint32_t)0xFEF6FFFF; 234 | 235 | /* Reset PLLCFGR register */ 236 | RCC->PLLCFGR = 0x24003010; 237 | 238 | /* Reset HSEBYP bit */ 239 | RCC->CR &= (uint32_t)0xFFFBFFFF; 240 | 241 | /* Disable all interrupts */ 242 | RCC->CIR = 0x00000000; 243 | 244 | #ifdef DATA_IN_ExtSRAM 245 | SystemInit_ExtMemCtl(); 246 | #endif /* DATA_IN_ExtSRAM */ 247 | 248 | /* Configure the System clock source, PLL Multiplier and Divider factors, 249 | AHB/APBx prescalers and Flash settings ----------------------------------*/ 250 | SetSysClock(); 251 | 252 | /* Configure the Vector Table location add offset address ------------------*/ 253 | #ifdef VECT_TAB_SRAM 254 | SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ 255 | #else 256 | SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ 257 | #endif 258 | } 259 | 260 | /** 261 | * @brief Update SystemCoreClock variable according to Clock Register Values. 262 | * The SystemCoreClock variable contains the core clock (HCLK), it can 263 | * be used by the user application to setup the SysTick timer or configure 264 | * other parameters. 265 | * 266 | * @note Each time the core clock (HCLK) changes, this function must be called 267 | * to update SystemCoreClock variable value. Otherwise, any configuration 268 | * based on this variable will be incorrect. 269 | * 270 | * @note - The system frequency computed by this function is not the real 271 | * frequency in the chip. It is calculated based on the predefined 272 | * constant and the selected clock source: 273 | * 274 | * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) 275 | * 276 | * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) 277 | * 278 | * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 279 | * or HSI_VALUE(*) multiplied/divided by the PLL factors. 280 | * 281 | * (*) HSI_VALUE is a constant defined in stm32f4xx.h file (default value 282 | * 16 MHz) but the real value may vary depending on the variations 283 | * in voltage and temperature. 284 | * 285 | * (**) HSE_VALUE is a constant defined in stm32f4xx.h file (default value 286 | * 25 MHz), user has to ensure that HSE_VALUE is same as the real 287 | * frequency of the crystal used. Otherwise, this function may 288 | * have wrong result. 289 | * 290 | * - The result of this function could be not correct when using fractional 291 | * value for HSE crystal. 292 | * 293 | * @param None 294 | * @retval None 295 | */ 296 | void SystemCoreClockUpdate(void) 297 | { 298 | uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; 299 | 300 | /* Get SYSCLK source -------------------------------------------------------*/ 301 | tmp = RCC->CFGR & RCC_CFGR_SWS; 302 | 303 | switch (tmp) 304 | { 305 | case 0x00: /* HSI used as system clock source */ 306 | SystemCoreClock = HSI_VALUE; 307 | break; 308 | case 0x04: /* HSE used as system clock source */ 309 | SystemCoreClock = HSE_VALUE; 310 | break; 311 | case 0x08: /* PLL used as system clock source */ 312 | 313 | /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N 314 | SYSCLK = PLL_VCO / PLL_P 315 | */ 316 | pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; 317 | pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; 318 | 319 | if (pllsource != 0) 320 | { 321 | /* HSE used as PLL clock source */ 322 | pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); 323 | } 324 | else 325 | { 326 | /* HSI used as PLL clock source */ 327 | pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); 328 | } 329 | 330 | pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; 331 | SystemCoreClock = pllvco/pllp; 332 | break; 333 | default: 334 | SystemCoreClock = HSI_VALUE; 335 | break; 336 | } 337 | /* Compute HCLK frequency --------------------------------------------------*/ 338 | /* Get HCLK prescaler */ 339 | tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; 340 | /* HCLK frequency */ 341 | SystemCoreClock >>= tmp; 342 | } 343 | 344 | /** 345 | * @brief Configures the System clock source, PLL Multiplier and Divider factors, 346 | * AHB/APBx prescalers and Flash settings 347 | * @Note This function should be called only once the RCC clock configuration 348 | * is reset to the default reset state (done in SystemInit() function). 349 | * @param None 350 | * @retval None 351 | */ 352 | static void SetSysClock(void) 353 | { 354 | /******************************************************************************/ 355 | /* PLL (clocked by HSE) used as System clock source */ 356 | /******************************************************************************/ 357 | __IO uint32_t StartUpCounter = 0, HSEStatus = 0; 358 | 359 | /* Enable HSE */ 360 | RCC->CR |= ((uint32_t)RCC_CR_HSEON); 361 | 362 | /* Wait till HSE is ready and if Time out is reached exit */ 363 | do 364 | { 365 | HSEStatus = RCC->CR & RCC_CR_HSERDY; 366 | StartUpCounter++; 367 | } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); 368 | 369 | if ((RCC->CR & RCC_CR_HSERDY) != RESET) 370 | { 371 | HSEStatus = (uint32_t)0x01; 372 | } 373 | else 374 | { 375 | HSEStatus = (uint32_t)0x00; 376 | } 377 | 378 | if (HSEStatus == (uint32_t)0x01) 379 | { 380 | /* Select regulator voltage output Scale 1 mode, System frequency up to 168 MHz */ 381 | RCC->APB1ENR |= RCC_APB1ENR_PWREN; 382 | PWR->CR |= PWR_CR_VOS; 383 | 384 | /* HCLK = SYSCLK / 1*/ 385 | RCC->CFGR |= RCC_CFGR_HPRE_DIV1; 386 | 387 | /* PCLK2 = HCLK / 2*/ 388 | RCC->CFGR |= RCC_CFGR_PPRE2_DIV2; 389 | 390 | /* PCLK1 = HCLK / 4*/ 391 | RCC->CFGR |= RCC_CFGR_PPRE1_DIV4; 392 | 393 | /* Configure the main PLL */ 394 | RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) | 395 | (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24); 396 | 397 | /* Enable the main PLL */ 398 | RCC->CR |= RCC_CR_PLLON; 399 | 400 | /* Wait till the main PLL is ready */ 401 | while((RCC->CR & RCC_CR_PLLRDY) == 0) 402 | { 403 | } 404 | 405 | /* Configure Flash prefetch, Instruction cache, Data cache and wait state */ 406 | FLASH->ACR = FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_5WS; 407 | 408 | /* Select the main PLL as system clock source */ 409 | RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); 410 | RCC->CFGR |= RCC_CFGR_SW_PLL; 411 | 412 | /* Wait till the main PLL is used as system clock source */ 413 | while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL); 414 | { 415 | } 416 | } 417 | else 418 | { /* If HSE fails to start-up, the application will have wrong clock 419 | configuration. User can add here some code to deal with this error */ 420 | } 421 | 422 | } 423 | 424 | /** 425 | * @brief Setup the external memory controller. Called in startup_stm32f4xx.s 426 | * before jump to __main 427 | * @param None 428 | * @retval None 429 | */ 430 | #ifdef DATA_IN_ExtSRAM 431 | /** 432 | * @brief Setup the external memory controller. 433 | * Called in startup_stm32f4xx.s before jump to main. 434 | * This function configures the external SRAM mounted on STM324xG_EVAL board 435 | * This SRAM will be used as program data memory (including heap and stack). 436 | * @param None 437 | * @retval None 438 | */ 439 | void SystemInit_ExtMemCtl(void) 440 | { 441 | /*-- GPIOs Configuration -----------------------------------------------------*/ 442 | /* 443 | +-------------------+--------------------+------------------+------------------+ 444 | + SRAM pins assignment + 445 | +-------------------+--------------------+------------------+------------------+ 446 | | PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 | 447 | | PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 | 448 | | PD4 <-> FSMC_NOE | PE3 <-> FSMC_A19 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 | 449 | | PD5 <-> FSMC_NWE | PE4 <-> FSMC_A20 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 | 450 | | PD8 <-> FSMC_D13 | PE7 <-> FSMC_D4 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 | 451 | | PD9 <-> FSMC_D14 | PE8 <-> FSMC_D5 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 | 452 | | PD10 <-> FSMC_D15 | PE9 <-> FSMC_D6 | PF12 <-> FSMC_A6 | PG9 <-> FSMC_NE2 | 453 | | PD11 <-> FSMC_A16 | PE10 <-> FSMC_D7 | PF13 <-> FSMC_A7 |------------------+ 454 | | PD12 <-> FSMC_A17 | PE11 <-> FSMC_D8 | PF14 <-> FSMC_A8 | 455 | | PD13 <-> FSMC_A18 | PE12 <-> FSMC_D9 | PF15 <-> FSMC_A9 | 456 | | PD14 <-> FSMC_D0 | PE13 <-> FSMC_D10 |------------------+ 457 | | PD15 <-> FSMC_D1 | PE14 <-> FSMC_D11 | 458 | | | PE15 <-> FSMC_D12 | 459 | +-------------------+--------------------+ 460 | */ 461 | /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ 462 | RCC->AHB1ENR = 0x00000078; 463 | 464 | /* Connect PDx pins to FSMC Alternate function */ 465 | GPIOD->AFR[0] = 0x00cc00cc; 466 | GPIOD->AFR[1] = 0xcc0ccccc; 467 | /* Configure PDx pins in Alternate function mode */ 468 | GPIOD->MODER = 0xaaaa0a0a; 469 | /* Configure PDx pins speed to 100 MHz */ 470 | GPIOD->OSPEEDR = 0xffff0f0f; 471 | /* Configure PDx pins Output type to push-pull */ 472 | GPIOD->OTYPER = 0x00000000; 473 | /* No pull-up, pull-down for PDx pins */ 474 | GPIOD->PUPDR = 0x00000000; 475 | 476 | /* Connect PEx pins to FSMC Alternate function */ 477 | GPIOE->AFR[0] = 0xc00cc0cc; 478 | GPIOE->AFR[1] = 0xcccccccc; 479 | /* Configure PEx pins in Alternate function mode */ 480 | GPIOE->MODER = 0xaaaa828a; 481 | /* Configure PEx pins speed to 100 MHz */ 482 | GPIOE->OSPEEDR = 0xffffc3cf; 483 | /* Configure PEx pins Output type to push-pull */ 484 | GPIOE->OTYPER = 0x00000000; 485 | /* No pull-up, pull-down for PEx pins */ 486 | GPIOE->PUPDR = 0x00000000; 487 | 488 | /* Connect PFx pins to FSMC Alternate function */ 489 | GPIOF->AFR[0] = 0x00cccccc; 490 | GPIOF->AFR[1] = 0xcccc0000; 491 | /* Configure PFx pins in Alternate function mode */ 492 | GPIOF->MODER = 0xaa000aaa; 493 | /* Configure PFx pins speed to 100 MHz */ 494 | GPIOF->OSPEEDR = 0xff000fff; 495 | /* Configure PFx pins Output type to push-pull */ 496 | GPIOF->OTYPER = 0x00000000; 497 | /* No pull-up, pull-down for PFx pins */ 498 | GPIOF->PUPDR = 0x00000000; 499 | 500 | /* Connect PGx pins to FSMC Alternate function */ 501 | GPIOG->AFR[0] = 0x00cccccc; 502 | GPIOG->AFR[1] = 0x000000c0; 503 | /* Configure PGx pins in Alternate function mode */ 504 | GPIOG->MODER = 0x00080aaa; 505 | /* Configure PGx pins speed to 100 MHz */ 506 | GPIOG->OSPEEDR = 0x000c0fff; 507 | /* Configure PGx pins Output type to push-pull */ 508 | GPIOG->OTYPER = 0x00000000; 509 | /* No pull-up, pull-down for PGx pins */ 510 | GPIOG->PUPDR = 0x00000000; 511 | 512 | /*-- FSMC Configuration ------------------------------------------------------*/ 513 | /* Enable the FSMC interface clock */ 514 | RCC->AHB3ENR = 0x00000001; 515 | 516 | /* Configure and enable Bank1_SRAM2 */ 517 | FSMC_Bank1->BTCR[2] = 0x00001015; 518 | FSMC_Bank1->BTCR[3] = 0x00010603; 519 | FSMC_Bank1E->BWTR[2] = 0x0fffffff; 520 | /* 521 | Bank1_SRAM2 is configured as follow: 522 | 523 | p.FSMC_AddressSetupTime = 3; 524 | p.FSMC_AddressHoldTime = 0; 525 | p.FSMC_DataSetupTime = 6; 526 | p.FSMC_BusTurnAroundDuration = 1; 527 | p.FSMC_CLKDivision = 0; 528 | p.FSMC_DataLatency = 0; 529 | p.FSMC_AccessMode = FSMC_AccessMode_A; 530 | 531 | FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2; 532 | FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable; 533 | FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_PSRAM; 534 | FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b; 535 | FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; 536 | FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; 537 | FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; 538 | FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable; 539 | FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; 540 | FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable; 541 | FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable; 542 | FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; 543 | FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable; 544 | FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p; 545 | FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p; 546 | */ 547 | 548 | } 549 | #endif /* DATA_IN_ExtSRAM */ 550 | 551 | 552 | /** 553 | * @} 554 | */ 555 | 556 | /** 557 | * @} 558 | */ 559 | 560 | /** 561 | * @} 562 | */ 563 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ 564 | -------------------------------------------------------------------------------- /cifar10/RTE/_ARMCM0/RTE_Components.h: -------------------------------------------------------------------------------- 1 | 2 | /* 3 | * Auto generated Run-Time-Environment Component Configuration File 4 | * *** Do not modify ! *** 5 | * 6 | * Project: 'arm_nnexamples_cifar10' 7 | * Target: 'ARMCM0' 8 | */ 9 | 10 | #ifndef RTE_COMPONENTS_H 11 | #define RTE_COMPONENTS_H 12 | 13 | 14 | /* 15 | * Define the Device Header File: 16 | */ 17 | #define CMSIS_device_header "ARMCM0.h" 18 | 19 | #define RTE_Compiler_EventRecorder 20 | #define RTE_Compiler_EventRecorder_DAP 21 | #define RTE_Compiler_IO_STDOUT /* Compiler I/O: STDOUT */ 22 | #define RTE_Compiler_IO_STDOUT_EVR /* Compiler I/O: STDOUT EVR */ 23 | 24 | #endif /* RTE_COMPONENTS_H */ 25 | -------------------------------------------------------------------------------- /cifar10/RTE/_ARMCM3/RTE_Components.h: -------------------------------------------------------------------------------- 1 | 2 | /* 3 | * Auto generated Run-Time-Environment Component Configuration File 4 | * *** Do not modify ! *** 5 | * 6 | * Project: 'arm_nnexamples_cifar10' 7 | * Target: 'ARMCM3' 8 | */ 9 | 10 | #ifndef RTE_COMPONENTS_H 11 | #define RTE_COMPONENTS_H 12 | 13 | 14 | /* 15 | * Define the Device Header File: 16 | */ 17 | #define CMSIS_device_header "ARMCM3.h" 18 | 19 | #define RTE_Compiler_IO_STDOUT /* Compiler I/O: STDOUT */ 20 | #define RTE_Compiler_IO_STDOUT_ITM /* Compiler I/O: STDOUT ITM */ 21 | 22 | #endif /* RTE_COMPONENTS_H */ 23 | -------------------------------------------------------------------------------- /cifar10/RTE/_ARMCM4_FP/RTE_Components.h: -------------------------------------------------------------------------------- 1 | 2 | /* 3 | * Auto generated Run-Time-Environment Component Configuration File 4 | * *** Do not modify ! *** 5 | * 6 | * Project: 'arm_nnexamples_cifar10' 7 | * Target: 'ARMCM4_FP' 8 | */ 9 | 10 | #ifndef RTE_COMPONENTS_H 11 | #define RTE_COMPONENTS_H 12 | 13 | 14 | /* 15 | * Define the Device Header File: 16 | */ 17 | #define CMSIS_device_header "stm32f4xx.h" 18 | 19 | #define RTE_Compiler_IO_STDOUT /* Compiler I/O: STDOUT */ 20 | #define RTE_Compiler_IO_STDOUT_ITM /* Compiler I/O: STDOUT ITM */ 21 | #define RTE_DEVICE_STARTUP_STM32F4XX /* Device Startup for STM32F4 */ 22 | 23 | #endif /* RTE_COMPONENTS_H */ 24 | -------------------------------------------------------------------------------- /cifar10/RTE/_ARMCM7_SP/RTE_Components.h: -------------------------------------------------------------------------------- 1 | 2 | /* 3 | * Auto generated Run-Time-Environment Component Configuration File 4 | * *** Do not modify ! *** 5 | * 6 | * Project: 'arm_nnexamples_cifar10' 7 | * Target: 'ARMCM7_SP' 8 | */ 9 | 10 | #ifndef RTE_COMPONENTS_H 11 | #define RTE_COMPONENTS_H 12 | 13 | 14 | /* 15 | * Define the Device Header File: 16 | */ 17 | #define CMSIS_device_header "ARMCM7_SP.h" 18 | 19 | #define RTE_Compiler_IO_STDOUT /* Compiler I/O: STDOUT */ 20 | #define RTE_Compiler_IO_STDOUT_ITM /* Compiler I/O: STDOUT ITM */ 21 | 22 | #endif /* RTE_COMPONENTS_H */ 23 | -------------------------------------------------------------------------------- /cifar10/RTE/_STM32F407DISCO/RTE_Components.h: -------------------------------------------------------------------------------- 1 | 2 | /* 3 | * Auto generated Run-Time-Environment Component Configuration File 4 | * *** Do not modify ! *** 5 | * 6 | * Project: 'arm_nnexamples_cifar10' 7 | * Target: 'STM32F407DISCO' 8 | */ 9 | 10 | #ifndef RTE_COMPONENTS_H 11 | #define RTE_COMPONENTS_H 12 | 13 | 14 | /* 15 | * Define the Device Header File: 16 | */ 17 | #define CMSIS_device_header "stm32f4xx.h" 18 | 19 | #define RTE_Compiler_IO_STDOUT /* Compiler I/O: STDOUT */ 20 | #define RTE_Compiler_IO_STDOUT_ITM /* Compiler I/O: STDOUT ITM */ 21 | #define RTE_DEVICE_STARTUP_STM32F4XX /* Device Startup for STM32F4 */ 22 | 23 | #endif /* RTE_COMPONENTS_H */ 24 | -------------------------------------------------------------------------------- /cifar10/arm_nnexamples_cifar10.cpp: -------------------------------------------------------------------------------- 1 | /* ---------------------------------------------------------------------- 2 | * Copyright (C) 2010-2018 Arm Limited. All rights reserved. 3 | * 4 | * 5 | * Project: CMSIS NN Library 6 | * Title: arm_nnexamples_cifar10.cpp 7 | * 8 | * Description: Convolutional Neural Network Example 9 | * 10 | * Target Processor: Cortex-M4/Cortex-M7 11 | * 12 | * Redistribution and use in source and binary forms, with or without 13 | * modification, are permitted provided that the following conditions 14 | * are met: 15 | * - Redistributions of source code must retain the above copyright 16 | * notice, this list of conditions and the following disclaimer. 17 | * - Redistributions in binary form must reproduce the above copyright 18 | * notice, this list of conditions and the following disclaimer in 19 | * the documentation and/or other materials provided with the 20 | * distribution. 21 | * - Neither the name of Arm LIMITED nor the names of its contributors 22 | * may be used to endorse or promote products derived from this 23 | * software without specific prior written permission. 24 | * 25 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 26 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 27 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 28 | * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 29 | * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 30 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 31 | * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 32 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 33 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 35 | * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 | * POSSIBILITY OF SUCH DAMAGE. 37 | * -------------------------------------------------------------------- */ 38 | 39 | /** 40 | * @ingroup groupExamples 41 | */ 42 | 43 | /** 44 | * @defgroup CNNExample Convolutional Neural Network Example 45 | * 46 | * \par Description: 47 | * \par 48 | * Demonstrates a convolutional neural network (CNN) example with the use of convolution, 49 | * ReLU activation, pooling and fully-connected functions. 50 | * 51 | * \par Model definition: 52 | * \par 53 | * The CNN used in this example is based on CIFAR-10 example from Caffe [1]. 54 | * The neural network consists 55 | * of 3 convolution layers interspersed by ReLU activation and max pooling layers, followed by a 56 | * fully-connected layer at the end. The input to the network is a 32x32 pixel color image, which will 57 | * be classified into one of the 10 output classes. 58 | * This example model implementation needs 32.3 KB to store weights, 40 KB for activations and 59 | * 3.1 KB for storing the \c im2col data. 60 | * 61 | * \image html CIFAR10_CNN.gif "Neural Network model definition" 62 | * 63 | * \par Variables Description: 64 | * \par 65 | * \li \c conv1_wt, \c conv2_wt, \c conv3_wt are convolution layer weight matrices 66 | * \li \c conv1_bias, \c conv2_bias, \c conv3_bias are convolution layer bias arrays 67 | * \li \c ip1_wt, ip1_bias point to fully-connected layer weights and biases 68 | * \li \c image_data points to the input image data 69 | * \li \c output_data points to the classification output 70 | * \li \c col_buffer is a buffer to store the \c im2col output 71 | * \li \c scratch_buffer is used to store the activation data (intermediate layer outputs) 72 | * 73 | * \par CMSIS DSP Software Library Functions Used: 74 | * \par 75 | * - arm_convolve_HWC_q7_RGB() 76 | * - arm_convolve_HWC_q7_fast() 77 | * - arm_relu_q7() 78 | * - arm_maxpool_q7_HWC() 79 | * - arm_avepool_q7_HWC() 80 | * - arm_fully_connected_q7_opt() 81 | * - arm_fully_connected_q7() 82 | * 83 | * Refer 84 | * \link arm_nnexamples_cifar10.cpp \endlink 85 | * 86 | * \par [1] https://github.com/BVLC/caffe 87 | */ 88 | 89 | #include 90 | #include 91 | #include "arm_math.h" 92 | #include "arm_nnexamples_cifar10_parameter.h" 93 | #include "arm_nnexamples_cifar10_weights.h" 94 | 95 | #include "arm_nnfunctions.h" 96 | #include "arm_nnexamples_cifar10_inputs.h" 97 | 98 | #ifdef _RTE_ 99 | #include "RTE_Components.h" 100 | #ifdef RTE_Compiler_EventRecorder 101 | #include "EventRecorder.h" 102 | #endif 103 | #endif 104 | 105 | // include the input and weights 106 | 107 | static q7_t conv1_wt[CONV1_IM_CH * CONV1_KER_DIM * CONV1_KER_DIM * CONV1_OUT_CH] = CONV1_WT; 108 | static q7_t conv1_bias[CONV1_OUT_CH] = CONV1_BIAS; 109 | 110 | static q7_t conv2_wt[CONV2_IM_CH * CONV2_KER_DIM * CONV2_KER_DIM * CONV2_OUT_CH] = CONV2_WT; 111 | static q7_t conv2_bias[CONV2_OUT_CH] = CONV2_BIAS; 112 | 113 | static q7_t conv3_wt[CONV3_IM_CH * CONV3_KER_DIM * CONV3_KER_DIM * CONV3_OUT_CH] = CONV3_WT; 114 | static q7_t conv3_bias[CONV3_OUT_CH] = CONV3_BIAS; 115 | 116 | static q7_t ip1_wt[IP1_DIM * IP1_OUT] = IP1_WT; 117 | static q7_t ip1_bias[IP1_OUT] = IP1_BIAS; 118 | 119 | /* Here the image_data should be the raw uint8 type RGB image in [RGB, RGB, RGB ... RGB] format */ 120 | uint8_t image_data[CONV1_IM_CH * CONV1_IM_DIM * CONV1_IM_DIM] = IMG_DATA; 121 | q7_t output_data[IP1_OUT]; 122 | 123 | //vector buffer: max(im2col buffer,average pool buffer, fully connected buffer) 124 | q7_t col_buffer[2 * 5 * 5 * 32 * 2]; 125 | 126 | q7_t scratch_buffer[32 * 32 * 10 * 4]; 127 | 128 | int main() 129 | { 130 | #ifdef RTE_Compiler_EventRecorder 131 | EventRecorderInitialize (EventRecordAll, 1); // initialize and start Event Recorder 132 | #endif 133 | 134 | printf("start execution\n"); 135 | /* start the execution */ 136 | 137 | q7_t *img_buffer1 = scratch_buffer; 138 | q7_t *img_buffer2 = img_buffer1 + 32 * 32 * 32; 139 | 140 | /* input pre-processing */ 141 | int mean_data[3] = INPUT_MEAN_SHIFT; 142 | unsigned int scale_data[3] = INPUT_RIGHT_SHIFT; 143 | for (int i=0;i<32*32*3; i+=3) { 144 | img_buffer2[i] = (q7_t)__SSAT( ((((int)image_data[i] - mean_data[0])<<7) + (0x1<<(scale_data[0]-1))) 145 | >> scale_data[0], 8); 146 | img_buffer2[i+1] = (q7_t)__SSAT( ((((int)image_data[i+1] - mean_data[1])<<7) + (0x1<<(scale_data[1]-1))) 147 | >> scale_data[1], 8); 148 | img_buffer2[i+2] = (q7_t)__SSAT( ((((int)image_data[i+2] - mean_data[2])<<7) + (0x1<<(scale_data[2]-1))) 149 | >> scale_data[2], 8); 150 | } 151 | 152 | // conv1 img_buffer2 -> img_buffer1 153 | arm_convolve_HWC_q7_RGB(img_buffer2, CONV1_IM_DIM, CONV1_IM_CH, conv1_wt, CONV1_OUT_CH, CONV1_KER_DIM, CONV1_PADDING, 154 | CONV1_STRIDE, conv1_bias, CONV1_BIAS_LSHIFT, CONV1_OUT_RSHIFT, img_buffer1, CONV1_OUT_DIM, 155 | (q15_t *) col_buffer, NULL); 156 | 157 | arm_relu_q7(img_buffer1, CONV1_OUT_DIM * CONV1_OUT_DIM * CONV1_OUT_CH); 158 | 159 | // pool1 img_buffer1 -> img_buffer2 160 | arm_maxpool_q7_HWC(img_buffer1, CONV1_OUT_DIM, CONV1_OUT_CH, POOL1_KER_DIM, 161 | POOL1_PADDING, POOL1_STRIDE, POOL1_OUT_DIM, NULL, img_buffer2); 162 | 163 | // conv2 img_buffer2 -> img_buffer1 164 | arm_convolve_HWC_q7_fast(img_buffer2, CONV2_IM_DIM, CONV2_IM_CH, conv2_wt, CONV2_OUT_CH, CONV2_KER_DIM, 165 | CONV2_PADDING, CONV2_STRIDE, conv2_bias, CONV2_BIAS_LSHIFT, CONV2_OUT_RSHIFT, img_buffer1, 166 | CONV2_OUT_DIM, (q15_t *) col_buffer, NULL); 167 | 168 | arm_relu_q7(img_buffer1, CONV2_OUT_DIM * CONV2_OUT_DIM * CONV2_OUT_CH); 169 | 170 | // pool2 img_buffer1 -> img_buffer2 171 | arm_maxpool_q7_HWC(img_buffer1, CONV2_OUT_DIM, CONV2_OUT_CH, POOL2_KER_DIM, 172 | POOL2_PADDING, POOL2_STRIDE, POOL2_OUT_DIM, col_buffer, img_buffer2); 173 | 174 | // conv3 img_buffer2 -> img_buffer1 175 | arm_convolve_HWC_q7_fast(img_buffer2, CONV3_IM_DIM, CONV3_IM_CH, conv3_wt, CONV3_OUT_CH, CONV3_KER_DIM, 176 | CONV3_PADDING, CONV3_STRIDE, conv3_bias, CONV3_BIAS_LSHIFT, CONV3_OUT_RSHIFT, img_buffer1, 177 | CONV3_OUT_DIM, (q15_t *) col_buffer, NULL); 178 | 179 | arm_relu_q7(img_buffer1, CONV3_OUT_DIM * CONV3_OUT_DIM * CONV3_OUT_CH); 180 | 181 | // pool3 img_buffer-> img_buffer2 182 | arm_maxpool_q7_HWC(img_buffer1, CONV3_OUT_DIM, CONV3_OUT_CH, POOL3_KER_DIM, 183 | POOL3_PADDING, POOL3_STRIDE, POOL3_OUT_DIM, col_buffer, img_buffer2); 184 | 185 | arm_fully_connected_q7_opt(img_buffer2, ip1_wt, IP1_DIM, IP1_OUT, IP1_BIAS_LSHIFT, IP1_OUT_RSHIFT, ip1_bias, 186 | output_data, (q15_t *) img_buffer1); 187 | 188 | arm_softmax_q7(output_data, 10, output_data); 189 | 190 | for (int i = 0; i < 10; i++) 191 | { 192 | printf("%d: %d\n", i, output_data[i]); 193 | } 194 | 195 | return 0; 196 | } 197 | -------------------------------------------------------------------------------- /cifar10/arm_nnexamples_cifar10_inputs.h: -------------------------------------------------------------------------------- 1 | /* Here are two different test images */ 2 | //#define IMG_DATA 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3 | //#define IMG_DATA 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4 | 5 | /* A CIFAR10 test set image - a dog, label 5 */ 6 | //#define IMG_DATA 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12,103,92,50,52,57,20,30,51,20,35,56,22,36,53,21,36,58,22,37,60,24,38,61,21,36,59,21,34,57,36,47,61,37,50,55,22,30,51,136,121,106,131,115,100,133,114,100,134,113,99,130,108,91,129,113,97,126,117,104,118,109,92,126,109,89,145,115,100,142,108,94,141,108,95,150,117,104,147,113,101,143,108,98,144,111,102,140,112,104,141,118,110,137,119,112,74,69,67,30,36,45,23,37,56,23,37,60,26,38,60,24,39,61,25,40,63,25,40,62,23,38,61,24,39,59,80,84,92,78,72,76,28,31,50} 7 | 8 | /* Custom image - a cat, label 3 */ 9 | #define IMG_DATA {231,227,224,220,214,212,212,205,204,229,222,223,241,238,239,244,243,244,243,244,244,243,244,244,243,244,244,243,243,244,199,188,182,156,141,133,162,144,129,151,126,108,81,55,45,92,66,49,90,69,58,107,88,77,121,108,100,162,152,151,191,182,184,223,220,222,238,233,235,247,244,245,253,252,252,244,243,243,240,239,240,239,237,239,239,237,237,238,232,232,233,227,227,233,227,227,225,220,217,212,206,204,175,167,164,162,153,147,187,181,179,214,210,209,231,229,228,239,236,235,237,234,233,235,232,231,210,200,194,172,156,151,159,145,140,174,153,135,120,94,74,80,54,40,81,59,48,92,73,61,103,89,77,121,112,103,103,93,92,91,84,86,107,100,102,145,138,140,191,185,187,225,219,221,238,235,235,234,230,230,232,227,228,230,224,224,226,220,220,226,220,220,221,216,213,215,210,207,190,185,181,141,135,127,122,117,108,135,130,122,164,158,152,191,183,177,201,192,189,201,193,189,187,178,168,180,167,156,161,150,141,155,142,128,161,138,112,102,70,48,86,63,49,93,79,69,108,99,92,117,111,100,81,74,70,74,68,67,63,58,60,59,56,58,67,64,65,111,105,107,191,184,185,220,214,215,231,225,224,227,220,220,220,214,214,218,212,212,216,212,209,214,209,206,197,192,189,157,153,147,122,115,107,113,106,98,111,104,96,114,110,100,119,113,105,140,132,122,166,153,138,164,150,136,150,137,126,130,117,104,159,138,113,123,94,71,80,63,49,101,90,82,116,105,99,103,92,86,89,81,76,84,78,73,80,74,73,79,73,74,75,69,68,76,70,69,100,93,91,129,122,121,159,153,152,189,184,185,206,201,201,212,207,207,207,206,204,210,207,204,198,193,190,162,157,154,121,116,108,105,100,91,105,101,92,105,101,92,103,98,88,127,118,107,161,144,127,143,125,115,144,131,119,137,123,108,144,122,98,122,100,78,76,64,50,78,68,62,98,87,81,86,78,77,85,80,76,97,87,82,90,85,83,88,83,80,105,95,91,105,94,89,122,108,97,126,110,95,126,110,96,125,111,103,128,116,116,161,157,158,197,196,194,198,196,193,193,190,186,169,164,161,126,121,115,100,96,88,102,98,89,102,98,89,103,97,88,107,98,89,124,111,98,154,140,123,158,142,120,143,126,101,120,99,76,111,94,74,99,87,71,77,66,60,76,67,61,69,63,62,72,67,67,93,82,79,85,79,74,79,76,71,96,86,77,129,110,91,149,126,103,161,143,123,162,145,126,150,133,116,140,123,104,117,101,92,188,187,185,186,185,182,176,174,170,152,147,144,114,109,104,93,89,81,94,90,81,95,92,83,99,94,84,95,87,77,87,77,70,136,123,104,151,135,110,121,105,82,85,69,52,86,72,59,72,63,52,50,43,40,63,54,50,44,41,41,94,83,77,89,79,71,98,85,73,114,98,81,132,112,93,142,122,104,144,128,113,160,145,135,167,151,142,146,129,122,137,120,111,150,132,112,181,180,178,182,181,179,174,173,171,145,144,140,105,101,93,90,86,77,89,85,76,91,88,79,91,85,77,94,82,70,115,99,85,127,112,93,131,116,97,110,96,78,94,81,65,59,49,42,54,46,42,54,49,45,59,52,46,66,59,53,71,62,55,87,74,63,124,105,89,149,127,101,130,112,99,142,126,115,151,135,124,178,162,154,199,182,174,163,139,134,129,103,99,144,123,112,178,177,175,180,179,177,175,174,171,147,145,141,104,100,94,87,83,76,90,86,77,90,86,77,81,76,68,98,83,67,152,134,114,138,124,100,129,113,92,129,113,91,107,92,74,63,53,45,69,60,51,75,62,55,59,53,48,65,55,50,88,75,61,120,101,80,143,122,97,126,107,89,122,104,95,150,136,126,167,151,142,184,168,158,205,186,179,188,160,154,135,106,99,143,119,107,173,172,170,173,172,170,169,169,167,143,143,140,108,104,98,93,85,75,73,68,60,67,62,56,70,65,57,123,109,89,140,123,99,116,100,80,131,116,92,124,107,84,71,59,49,58,49,43,57,49,43,88,79,67,88,75,64,69,60,54,87,76,63,104,90,72,105,88,69,123,101,86,130,106,94,150,135,121,181,166,157,187,167,158,171,144,130,166,139,127,140,112,103,141,112,95,172,171,170,168,167,165,143,144,142,101,97,92,88,79,70,67,60,50,35,33,29,34,31,29,51,46,40,129,113,92,125,107,86,107,95,79,140,126,105,97,81,64,50,42,39,70,60,51,90,79,69,109,99,85,83,70,61,123,106,87,84,74,61,99,86,73,128,110,92,149,124,109,160,134,119,148,127,117,175,158,150,189,173,165,175,149,133,154,118,101,158,128,113,160,132,116,118,112,110,111,106,98,91,85,75,78,68,59,70,62,52,64,58,48,40,39,33,36,36,31,45,40,35,113,100,83,142,127,112,154,140,118,94,82,71,103,88,74,90,80,67,83,74,63,104,93,78,79,68,58,95,81,67,130,113,93,116,101,83,109,92,76,140,119,105,149,125,112,160,137,123,158,133,122,171,153,141,161,141,127,189,162,149,165,131,120,135,108,94,158,138,123,76,66,57,88,78,67,95,86,75,88,80,71,74,66,58,73,64,55,39,35,31,32,30,29,84,73,63,164,143,123,135,113,88,159,140,118,121,104,86,112,97,80,73,63,55,61,54,47,101,87,73,135,117,97,118,100,80,124,108,92,125,108,91,129,108,89,140,117,103,139,115,98,142,118,101,155,132,117,161,142,122,173,147,134,170,135,123,131,101,86,144,120,100,162,143,120,98,88,78,102,91,80,93,83,73,84,77,66,65,60,54,49,44,42,36,35,31,41,38,32,86,75,59,180,153,124,165,130,79,54,58,58,126,114,92,112,96,78,95,84,70,79,68,61,139,124,104,113,98,85,91,78,70,146,129,111,118,100,86,138,116,97,152,125,106,143,117,98,132,107,88,133,111,94,144,121,108,157,133,121,127,102,90,109,89,73,148,128,105,127,109,87,92,82,73,90,80,73,77,68,62,64,56,50,60,53,45,67,60,50,59,53,46,47,41,35,75,64,48,152,129,104,168,131,80,115,94,54,125,111,82,132,116,99,138,120,99,124,109,92,146,129,105,91,73,66,122,107,96,109,91,80,101,81,70,136,110,93,154,129,109,147,121,100,140,115,93,141,119,96,128,105,87,119,99,80,114,97,77,118,102,82,134,118,96,126,109,90,88,80,71,54,49,45,50,46,39,79,69,60,83,73,63,98,89,76,87,79,65,57,49,38,62,52,43,108,92,75,167,137,111,144,110,72,129,112,88,142,126,102,155,136,113,148,131,111,185,164,137,171,144,121,154,131,110,131,113,97,136,117,101,130,105,83,149,122,97,146,119,94,140,116,90,143,123,95,139,117,90,129,107,83,132,113,88,127,110,85,129,112,89,123,108,94,67,60,51,64,57,50,68,61,53,100,90,77,107,96,82,120,107,93,128,113,97,72,59,44,65,53,40,111,94,76,161,137,111,151,123,105,132,113,95,154,135,110,154,136,114,191,172,148,218,198,175,157,127,90,116,100,76,127,119,117,165,148,125,168,143,117,163,134,107,156,131,104,153,129,104,158,136,110,142,116,88,136,110,83,130,108,82,122,100,79,110,90,72,103,93,83,93,80,71,98,86,76,106,93,82,130,115,100,132,117,104,138,122,108,150,133,117,79,65,52,74,61,49,141,122,98,151,126,102,131,103,77,138,114,87,165,144,117,175,152,128,229,207,181,146,121,115,105,79,47,113,106,77,71,77,69,143,116,71,153,125,104,140,115,92,110,92,74,118,101,83,142,121,99,125,103,81,127,103,77,142,120,93,132,109,88,100,84,72,125,120,115,120,106,96,91,81,72,119,106,93,139,122,106,147,130,112,137,121,100,148,131,108,99,83,68,61,51,39,127,110,89,144,118,93,139,106,75,184,153,121,176,151,126,195,167,137,190,163,139,136,104,95,144,114,99,145,117,75,150,119,71,156,124,95,202,177,154,140,118,91,80,66,52,78,67,61,59,49,46,113,96,80,137,115,94,140,118,98,125,105,86,106,94,83,148,139,132,125,110,98,116,105,94,127,114,99,139,123,107,136,120,97,119,101,80,136,118,94,112,92,72,55,39,26,164,142,116,165,126,95,159,114,73,199,162,124,189,153,117,167,132,95,112,86,69,166,135,110,218,190,161,178,152,125,168,138,115,175,153,129,138,118,96,113,93,73,145,127,102,164,142,118,114,97,83,62,52,46,105,92,76,102,87,76,103,88,77,124,109,101,174,160,153,106,94,82,113,101,87,127,112,95,132,116,98,144,124,101,115,96,77,138,121,100,137,111,87,75,55,43,137,122,108,174,144,117,166,126,90,193,149,108,161,115,74,118,86,59,131,107,85,165,143,119,159,140,118,155,136,114,148,128,107,116,98,82,107,91,74,134,116,96,165,143,121,166,144,121,151,129,106,120,100,87,115,100,85,101,86,73,120,106,98,170,157,150,190,177,169,107,93,78,119,105,91,119,100,82,113,96,78,148,126,101,110,92,75,142,125,103,147,122,94,108,92,81,94,82,77,144,121,108,150,115,91,149,113,89,120,79,52,155,114,80,179,146,118,148,123,99,160,139,117,145,126,109,128,111,94,128,111,95,127,109,95,144,125,108,139,120,107,157,138,118,134,111,93,123,103,86,132,112,93,136,119,106,165,152,142,186,173,165,192,177,169,111,95,81,137,123,105,129,109,92,103,85,72,143,127,105,120,102,82,106,93,74,145,124,103,140,124,108,110,100,92,101,86,77,147,119,102,149,125,115,189,163,139,212,179,145,181,152,127,139,115,94,149,127,105,175,153,131,177,157,140,172,153,137,178,158,141,173,149,130,150,126,107,141,118,98,139,117,96,140,121,101,137,121,102,162,146,136,194,176,170,196,181,174,190,176,167,120,106,90,129,117,101,142,124,104,117,97,82,108,91,75,115,99,82,121,106,94,140,124,111,151,135,119,149,134,121,70,61,57,97,86,80,188,175,163,219,208,193,219,201,182,203,178,156,188,163,140,177,151,127,167,144,127,165,148,137,168,149,138,162,137,121,160,132,109,175,150,128,167,144,123,159,139,122,170,151,137,188,171,165,205,191,184,210,192,185,211,194,187,205,190,181,120,105,94,135,123,115,144,129,118,135,121,109,153,136,126,155,139,131,182,166,154,180,162,151,180,165,154,179,166,154,160,142,132,139,120,113,178,158,147,198,179,167,195,177,163,193,170,154,171,148,131,173,152,142,196,177,168,202,185,176,206,190,182,192,172,161,169,148,135,178,155,138,189,168,153,205,188,178,206,189,179,212,195,186,211,193,186,213,198,189,214,196,187,197,180,171,176,161,153,207,192,186,208,190,182,200,183,174,219,202,195,215,195,185,208,187,173,215,196,183,200,178,163,189,170,158,207,189,177,211,193,181,223,204,193,220,201,189,212,192,179,203,179,168,192,167,155,202,181,169,216,199,187,217,198,186,213,193,181,209,189,176,207,187,179,196,171,158,204,184,173,214,198,190,214,196,189,210,191,183,219,202,194,211,194,186,208,192,186,203,187,179,211,194,183,213,195,184,209,190,178,206,184,171,207,184,171,207,183,171,208,179,165,211,186,172,197,168,150,197,168,151,210,185,172,218,198,187,218,196,186,223,202,189,223,196,183,221,194,180,221,198,186,210,182,169,215,190,177,211,183,169,211,185,170,212,185,172,205,181,168,191,165,150,188,161,148,209,187,177,205,187,175,210,191,180,213,195,184,218,201,193,208,191,184,188,167,161,200,182,167,207,189,177,206,180,169,204,177,164,218,193,181,211,185,170,198,168,149,200,168,150,207,174,155,202,168,147,191,160,140,191,161,144,206,178,163,205,176,160,218,192,176,223,197,182,218,190,176,217,191,178,207,178,164,199,169,151,202,175,156,202,173,158,205,180,164,202,177,162,198,173,161,213,195,186,209,191,182,216,197,186,216,198,187,219,201,194,209,190,183,187,168,160,188,157,144,201,172,158,216,189,179,214,188,178,202,172,157,204,171,152,197,162,146,214,188,171,213,183,16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10 | 11 | -------------------------------------------------------------------------------- /cifar10/arm_nnexamples_cifar10_parameter.h: -------------------------------------------------------------------------------- 1 | #define CONV1_IM_DIM 32 2 | #define CONV1_IM_CH 3 3 | #define CONV1_KER_DIM 5 4 | #define CONV1_PADDING 2 5 | #define CONV1_STRIDE 1 6 | #define CONV1_OUT_CH 32 7 | #define CONV1_OUT_DIM 32 8 | 9 | #define POOL1_KER_DIM 3 10 | #define POOL1_STRIDE 2 11 | #define POOL1_PADDING 0 12 | #define POOL1_OUT_DIM 16 13 | 14 | #define CONV2_IM_DIM 16 15 | #define CONV2_IM_CH 32 16 | #define CONV2_KER_DIM 5 17 | #define CONV2_PADDING 2 18 | #define CONV2_STRIDE 1 19 | #define CONV2_OUT_CH 16 20 | #define CONV2_OUT_DIM 16 21 | 22 | #define POOL2_KER_DIM 3 23 | #define POOL2_STRIDE 2 24 | #define POOL2_PADDING 0 25 | #define POOL2_OUT_DIM 8 26 | 27 | #define CONV3_IM_DIM 8 28 | #define CONV3_IM_CH 16 29 | #define CONV3_KER_DIM 5 30 | #define CONV3_PADDING 2 31 | #define CONV3_STRIDE 1 32 | #define CONV3_OUT_CH 32 33 | #define CONV3_OUT_DIM 8 34 | 35 | #define POOL3_KER_DIM 3 36 | #define POOL3_STRIDE 2 37 | #define POOL3_PADDING 0 38 | #define POOL3_OUT_DIM 4 39 | 40 | #define IP1_DIM 4*4*32 41 | #define IP1_IM_DIM 4 42 | #define IP1_IM_CH 32 43 | #define IP1_OUT 10 44 | -------------------------------------------------------------------------------- /cifar10/readme.txt: -------------------------------------------------------------------------------- 1 | CMSIS NN Lib example arm_nnexample_cifar10 for 2 | Cortex-M4 and Cortex-M7. 3 | 4 | The example is configured for uVision Simulator as well as the STM32F407 DISCOVERY board. 5 | For more information, please read the following tutorial 6 | [How to run deep learning model on microcontroller with CMSIS-NN](https://www.dlology.com/blog/how-to-run-deep-learning-model-on-microcontroller-with-cmsis-nn/) 7 | -------------------------------------------------------------------------------- /readme.md: -------------------------------------------------------------------------------- 1 | ## [How to run deep learning model on microcontroller with CMSIS-NN](https://www.dlology.com/blog/how-to-run-deep-learning-model-on-microcontroller-with-cmsis-nn/) Blog 2 | 3 | ## `cifar10` folder 4 | 5 | CMSIS NN Lib example arm_nnexample_cifar10 for 6 | Cortex-M4 and Cortex-M7. 7 | 8 | The example is configured for uVision Simulator as well as the STM32F407 DISCOVERY board. 9 | 10 | 11 | ## `script` folder 12 | It contains a Python Jupyter notebook to generate `#define IMG_DATA {...}` data with a new custom image. 13 | 14 | For more information, please read the tutorial. 15 | 16 | Please noted that the microcontroller project is built with Keil MDK-ARM run on Windows, if you don't have the IDE installed yet, you can find a copy and instruction to install [here](https://pan.baidu.com/s/1EYw5TofPFaihKQG1vCu0kQ). -------------------------------------------------------------------------------- /scripts/.gitignore: -------------------------------------------------------------------------------- 1 | images 2 | *.tar.gz 3 | *.pyc 4 | *.hdf5 5 | *.ipynb_checkpoints 6 | *.p 7 | *.h5 8 | *.HDF5 9 | __pycache__ 10 | *.jpg -------------------------------------------------------------------------------- /scripts/README.md: -------------------------------------------------------------------------------- 1 | To generate a header file with the correct `IMG_DATA` format, look for the following example in the jupyter notebook. 2 | ```python 3 | srcfile = 'cat.jpg' 4 | newImg2File(srcfile, show=True) 5 | ``` -------------------------------------------------------------------------------- /scripts/model.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Tony607/arm_nn_examples/27fc63294fe18653402546f20f86e6d2afff791a/scripts/model.png -------------------------------------------------------------------------------- /scripts/requirements.txt: -------------------------------------------------------------------------------- 1 | numpy 2 | keras 3 | numpy 4 | matplotlib 5 | pillow --------------------------------------------------------------------------------