├── .gitignore ├── DSP ├── DSP.vhd ├── dsp56k.zip └── src │ ├── adgen_stage.vhd │ ├── constants_pkg.vhd │ ├── decode_stage.vhd │ ├── exec_stage_alu.vhd │ ├── exec_stage_bit_modify.vhd │ ├── exec_stage_branch.vhd │ ├── exec_stage_cc_flag_calc.vhd │ ├── exec_stage_cr_mod.vhd │ ├── exec_stage_loops.vhd │ ├── fetch_stage.vhd │ ├── mem_control.vhd │ ├── memory_management.vhd │ ├── parameter_pkg.vhd │ ├── pipeline.vhd │ ├── reg_file.vhd │ └── types_pkg.vhd ├── FalconIO_SDCard_IDE_CF ├── FalconIO_SDCard_IDE_CF.vhd ├── FalconIO_SDCard_IDE_CF_pgk.vhd ├── WF5380 │ ├── wf5380_control.vhd │ ├── wf5380_pkg.vhd │ ├── wf5380_registers.vhd │ ├── wf5380_soc_top.vhd │ └── wf5380_top.vhd ├── WF_FDC1772_IP │ ├── wf1772ip_am_detector.vhd │ ├── wf1772ip_control.vhd │ ├── wf1772ip_crc_logic.vhd │ ├── wf1772ip_digital_pll.vhd │ ├── wf1772ip_pkg.vhd │ ├── wf1772ip_registers.vhd │ ├── wf1772ip_top.vhd │ ├── wf1772ip_top_soc.vhd │ └── wf1772ip_transceiver.vhd ├── WF_MFP68901_IP │ ├── wf68901ip_gpio.vhd │ ├── wf68901ip_interrupts.vhd │ ├── wf68901ip_pkg.vhd │ ├── wf68901ip_timers.vhd │ ├── wf68901ip_top.vhd │ ├── wf68901ip_top_soc.vhd │ ├── wf68901ip_usart_ctrl.vhd │ ├── wf68901ip_usart_rx.vhd │ ├── wf68901ip_usart_top.vhd │ └── wf68901ip_usart_tx.vhd ├── WF_SDC_IF │ ├── sd-card-interface.vhd │ └── sd-card-interface_soc.vhd ├── WF_SND2149_IP │ ├── wf2149ip_pkg.vhd │ ├── wf2149ip_top.vhd │ ├── wf2149ip_top_soc.vhd │ └── wf2149ip_wave.vhd └── WF_UART6850_IP │ ├── wf6850ip_ctrl_status.vhd │ ├── wf6850ip_receive.vhd │ ├── wf6850ip_top.vhd │ ├── wf6850ip_top_soc.vhd │ └── wf6850ip_transmit.vhd ├── Interrupt_Handler ├── interrupt_handler.tdf └── interrupt_handler.v ├── PLLJ_PLLSPE_INFO.txt ├── Video ├── BLITTER │ └── BLITTER.vhd ├── DDR_CTR.tdf ├── DDR_CTR.v ├── VIDEO_MOD_MUX_CLUTCTR.tdf ├── VIDEO_MOD_MUX_CLUTCTR.v ├── Video.bdf ├── video.v └── video.vhd ├── ahdl2v ├── DDR_CTR.tdf ├── DDR_CTR.v ├── VIDEO_MOD_MUX_CLUTCTR.tdf ├── VIDEO_MOD_MUX_CLUTCTR.v ├── interrupt_handler.tdf ├── interrupt_handler.v ├── lpm_bustri.tdf ├── lpm_bustri_BYT.inc ├── lpm_bustri_BYT.tdf ├── lpm_bustri_BYT.v ├── lpm_bustri_LONG.inc ├── lpm_bustri_LONG.tdf ├── lpm_bustri_LONG.v ├── lpm_bustri_WORD.inc ├── lpm_bustri_WORD.tdf ├── lpm_bustri_WORD.v └── xport.exe ├── altdpram0.qip ├── altip ├── altddio_bidir0.ppf ├── altddio_bidir0.qip ├── altddio_bidir0.v ├── altddio_out0.ppf ├── altddio_out0.qip ├── altddio_out0.v ├── altddio_out1.ppf ├── altddio_out1.qip ├── altddio_out1.v ├── altddio_out2.ppf ├── altddio_out2.qip ├── altddio_out2.v ├── altddio_out3.ppf ├── altddio_out3.qip ├── altddio_out3.v ├── altdpram0.qip ├── altdpram0.v ├── altdpram1.qip ├── altdpram1.v ├── altdpram2.qip ├── altdpram2.v ├── altpll0.ppf ├── altpll0.qip ├── altpll0.v ├── altpll1.ppf ├── altpll1.qip ├── altpll1.v ├── altpll2.ppf ├── altpll2.qip ├── altpll2.v ├── altpll3.ppf ├── altpll3.qip ├── altpll3.v ├── altpll4.mif ├── altpll4.ppf ├── altpll4.qip ├── altpll4.v ├── altpll_reconfig1.qip ├── altpll_reconfig1.v ├── dcfifo0.qip ├── dcfifo0.v ├── dcfifo1.qip ├── dcfifo1.v ├── lpm_compare1.qip ├── lpm_compare1.v ├── lpm_constant0.qip ├── lpm_constant0.v ├── lpm_constant1.qip ├── lpm_constant1.v ├── lpm_constant2.qip ├── lpm_constant2.v ├── lpm_constant3.qip ├── lpm_constant3.v ├── lpm_constant4.qip ├── lpm_constant4.v ├── lpm_counter0.qip ├── lpm_counter0.v ├── lpm_fifoDZ.qip ├── lpm_fifoDZ.v ├── lpm_fifo_dc0.qip ├── lpm_fifo_dc0.v ├── lpm_mux0.qip ├── lpm_mux0.v ├── lpm_mux1.qip ├── lpm_mux1.v ├── lpm_mux2.qip ├── lpm_mux2.v ├── lpm_mux3.qip ├── lpm_mux3.v ├── lpm_mux4.qip ├── lpm_mux4.v ├── lpm_mux5.qip ├── lpm_mux5.v ├── lpm_mux6.qip ├── lpm_mux6.v ├── lpm_muxDZ.qip ├── lpm_muxDZ.v ├── lpm_muxDZ2.qip ├── lpm_muxDZ2.v ├── lpm_muxVDM.qip ├── lpm_muxVDM.v ├── lpm_shiftreg0.qip ├── lpm_shiftreg0.v ├── lpm_shiftreg1.qip ├── lpm_shiftreg1.v ├── lpm_shiftreg2.qip ├── lpm_shiftreg2.v ├── lpm_shiftreg3.qip ├── lpm_shiftreg3.v ├── lpm_shiftreg4.qip ├── lpm_shiftreg4.v ├── lpm_shiftreg5.qip ├── lpm_shiftreg5.v ├── lpm_shiftreg6.qip └── lpm_shiftreg6.v ├── altip_orig ├── altddio_bidir0.bsf ├── altddio_bidir0.inc ├── altddio_bidir0.ppf ├── altddio_bidir0.qip ├── altddio_bidir0.vhd ├── altddio_out0.bsf ├── altddio_out0.inc ├── altddio_out0.ppf ├── altddio_out0.qip ├── altddio_out0.vhd ├── altddio_out1.bsf ├── altddio_out1.inc ├── altddio_out1.ppf ├── altddio_out1.qip ├── altddio_out1.vhd ├── altddio_out2.bsf ├── altddio_out2.inc ├── altddio_out2.ppf ├── altddio_out2.qip ├── altddio_out2.vhd ├── altddio_out3.bsf ├── altddio_out3.inc ├── altddio_out3.ppf ├── altddio_out3.qip ├── altddio_out3.vhd ├── altdpram0.bsf ├── altdpram0.inc ├── altdpram0.qip ├── altdpram0.vhd ├── altdpram1.bsf ├── altdpram1.inc ├── altdpram1.qip ├── altdpram1.vhd ├── altdpram2.bsf ├── altdpram2.inc ├── altdpram2.qip ├── altdpram2.vhd ├── altpll0.bsf ├── altpll0.inc ├── altpll0.ppf ├── altpll0.qip ├── altpll0.vhd ├── altpll1.bsf ├── altpll1.inc ├── altpll1.ppf ├── altpll1.qip ├── altpll1.vhd ├── altpll2.bsf ├── altpll2.inc ├── altpll2.ppf ├── altpll2.qip ├── altpll2.vhd ├── altpll3.bsf ├── altpll3.inc ├── altpll3.ppf ├── altpll3.qip ├── altpll3.vhd ├── altpll4.bsf ├── altpll4.inc ├── altpll4.mif ├── altpll4.ppf ├── altpll4.qip ├── altpll4.tdf ├── altpll_reconfig0.bsf ├── altpll_reconfig0.qip ├── altpll_reconfig1.bsf ├── altpll_reconfig1.inc ├── altpll_reconfig1.qip ├── altpll_reconfig1.tdf ├── altpll_reconfig1_pllrcfg_bju.tdf ├── altpll_reconfig1_pllrcfg_t4q.tdf ├── dcfifo0.bsf ├── dcfifo0.cmp ├── dcfifo0.qip ├── dcfifo0.vhd ├── dcfifo1.bsf ├── dcfifo1.cmp ├── dcfifo1.qip ├── dcfifo1.vhd ├── lpm_bustri0.bsf ├── lpm_bustri0.inc ├── lpm_bustri0.qip ├── lpm_bustri0.vhd ├── lpm_bustri1.bsf ├── lpm_bustri1.qip ├── lpm_bustri1.vhd ├── lpm_bustri2.bsf ├── lpm_bustri2.qip ├── lpm_bustri2.vhd ├── lpm_bustri3.bsf ├── lpm_bustri3.qip ├── lpm_bustri3.vhd ├── lpm_bustri4.bsf ├── lpm_bustri4.qip ├── lpm_bustri4.vhd ├── lpm_bustri5.bsf ├── lpm_bustri5.inc ├── lpm_bustri5.qip ├── lpm_bustri5.vhd ├── lpm_bustri6.bsf ├── lpm_bustri6.qip ├── lpm_bustri6.vhd ├── lpm_bustri7.bsf ├── lpm_bustri7.qip ├── lpm_bustri7.vhd ├── lpm_bustri_BYT.bsf ├── lpm_bustri_BYT.inc ├── lpm_bustri_BYT.qip ├── lpm_bustri_BYT.vhd ├── lpm_bustri_LONG.bsf ├── lpm_bustri_LONG.inc ├── lpm_bustri_LONG.qip ├── lpm_bustri_LONG.tdf ├── lpm_bustri_LONG.vhd ├── lpm_bustri_WORD.bsf ├── lpm_bustri_WORD.inc ├── lpm_bustri_WORD.qip ├── lpm_bustri_WORD.vhd ├── lpm_compare1.bsf ├── lpm_compare1.inc ├── lpm_compare1.qip ├── lpm_compare1.vhd ├── lpm_constant0.bsf ├── lpm_constant0.qip ├── lpm_constant0.vhd ├── lpm_constant1.bsf ├── lpm_constant1.inc ├── lpm_constant1.qip ├── lpm_constant1.vhd ├── lpm_constant2.bsf ├── lpm_constant2.qip ├── lpm_constant2.vhd ├── lpm_constant3.bsf ├── lpm_constant3.qip ├── lpm_constant3.vhd ├── lpm_constant4.bsf ├── lpm_constant4.inc ├── lpm_constant4.qip ├── lpm_constant4.vhd ├── lpm_counter0.bsf ├── lpm_counter0.qip ├── lpm_counter0.vhd ├── lpm_ff0.bsf ├── lpm_ff0.qip ├── lpm_ff0.vhd ├── lpm_ff1.bsf ├── lpm_ff1.qip ├── lpm_ff1.vhd ├── lpm_ff2.bsf ├── lpm_ff2.qip ├── lpm_ff2.vhd ├── lpm_ff3.bsf ├── lpm_ff3.qip ├── lpm_ff3.vhd ├── lpm_ff4.bsf ├── lpm_ff4.inc ├── lpm_ff4.qip ├── lpm_ff4.vhd ├── lpm_ff5.bsf ├── lpm_ff5.inc ├── lpm_ff5.qip ├── lpm_ff5.vhd ├── lpm_ff6.bsf ├── lpm_ff6.inc ├── lpm_ff6.qip ├── lpm_ff6.vhd ├── lpm_fifoDZ.bsf ├── lpm_fifoDZ.qip ├── lpm_fifoDZ.vhd ├── lpm_fifo_dc0.bsf ├── lpm_fifo_dc0.inc ├── lpm_fifo_dc0.qip ├── lpm_fifo_dc0.vhd ├── lpm_latch0.bsf ├── lpm_latch0.qip ├── lpm_latch0.vhd ├── lpm_latch1.bsf ├── lpm_latch1.qip ├── lpm_latch1.vhd ├── lpm_mux0.bsf ├── lpm_mux0.inc ├── lpm_mux0.qip ├── lpm_mux0.vhd ├── lpm_mux1.bsf ├── lpm_mux1.inc ├── lpm_mux1.qip ├── lpm_mux1.vhd ├── lpm_mux2.bsf ├── lpm_mux2.inc ├── lpm_mux2.qip ├── lpm_mux2.vhd ├── lpm_mux3.bsf ├── lpm_mux3.qip ├── lpm_mux3.vhd ├── lpm_mux4.bsf ├── lpm_mux4.qip ├── lpm_mux4.vhd ├── lpm_mux5.bsf ├── lpm_mux5.inc ├── lpm_mux5.qip ├── lpm_mux5.vhd ├── lpm_mux6.bsf ├── lpm_mux6.inc ├── lpm_mux6.qip ├── lpm_mux6.vhd ├── lpm_muxDZ.bsf ├── lpm_muxDZ.qip ├── lpm_muxDZ.vhd ├── lpm_muxDZ2.bsf ├── lpm_muxDZ2.qip ├── lpm_muxDZ2.vhd ├── lpm_muxVDM.bsf ├── lpm_muxVDM.qip ├── lpm_muxVDM.vhd ├── lpm_shiftreg0.bsf ├── lpm_shiftreg0.inc ├── lpm_shiftreg0.qip ├── lpm_shiftreg0.vhd ├── lpm_shiftreg1.bsf ├── lpm_shiftreg1.qip ├── lpm_shiftreg1.vhd ├── lpm_shiftreg2.bsf ├── lpm_shiftreg2.qip ├── lpm_shiftreg2.vhd ├── lpm_shiftreg3.bsf ├── lpm_shiftreg3.inc ├── lpm_shiftreg3.qip ├── lpm_shiftreg3.vhd ├── lpm_shiftreg4.bsf ├── lpm_shiftreg4.inc ├── lpm_shiftreg4.qip ├── lpm_shiftreg4.vhd ├── lpm_shiftreg5.bsf ├── lpm_shiftreg5.inc ├── lpm_shiftreg5.qip ├── lpm_shiftreg5.vhd ├── lpm_shiftreg6.bsf ├── lpm_shiftreg6.inc ├── lpm_shiftreg6.qip ├── lpm_shiftreg6.vhd └── root │ ├── altddio_out0.bsf │ ├── altddio_out0.inc │ ├── altddio_out0.ppf │ ├── altddio_out0.qip │ └── altddio_out0.vhd ├── altpll1.qip ├── altpll4.mif ├── altpll4.qip ├── dcfifo0.qip ├── firebee1.bdf ├── firebee1.qpf ├── firebee1.qsf ├── firebee1.rbf ├── firebee1.sdc ├── firebee1.sof ├── firebee1.v ├── firebee1.vhd ├── firebee1_assignment_defaults.qdf ├── fpga.s19 ├── lpm_bustri2.bsf ├── lpm_ffs.v ├── mkS19.bat ├── mux41.v ├── mux41.vhd └── objcopy.exe /.gitignore: -------------------------------------------------------------------------------- 1 | db 2 | incremental_db 3 | greybox_tmp 4 | *.done 5 | *.map* 6 | *.qws 7 | *.asm* 8 | *.fit* 9 | *.flow* 10 | *.pin 11 | *.jdi 12 | *.sta* 13 | *.rpt 14 | -------------------------------------------------------------------------------- /DSP/dsp56k.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Torlus/firebee-fpga/d07ee9b14405b2e00bd1d6589a1991cc32c86d0b/DSP/dsp56k.zip -------------------------------------------------------------------------------- /DSP/src/exec_stage_cr_mod.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use ieee.numeric_std.all; 4 | library work; 5 | use work.parameter_pkg.all; 6 | use work.types_pkg.all; 7 | use work.constants_pkg.all; 8 | 9 | entity exec_stage_cr_mod is port ( 10 | activate_exec_cr_mod : in std_logic; 11 | instr_word : in std_logic_vector(23 downto 0); 12 | instr_array : in instructions_type; 13 | register_file : in register_file_type; 14 | modify_sr : out std_logic; 15 | modified_sr : out std_logic_vector(15 downto 0); 16 | modify_omr : out std_logic; 17 | modified_omr : out std_logic_vector(7 downto 0) 18 | ); 19 | end exec_stage_cr_mod; 20 | 21 | 22 | architecture rtl of exec_stage_cr_mod is 23 | 24 | begin 25 | 26 | process(activate_exec_cr_mod, instr_word, instr_array, register_file) is 27 | variable imm8 : std_logic_vector(7 downto 0); 28 | variable op8 : std_logic_vector(7 downto 0); 29 | variable res8 : std_logic_vector(7 downto 0); 30 | begin 31 | modify_sr <= '0'; 32 | modify_omr <= '0'; 33 | modified_sr <= (others => '0'); 34 | modified_omr <= (others => '0'); 35 | 36 | imm8 := instr_word(15 downto 8); 37 | if instr_word(1 downto 0) = "00" then 38 | -- read MR 39 | op8 := register_file.mr; 40 | elsif instr_word(1 downto 0) = "01" then 41 | -- read CCR 42 | op8 := register_file.ccr; 43 | else -- instr_word(1 downto 0) = "10" 44 | -- read OMR 45 | op8 := register_file.omr; 46 | end if; 47 | 48 | if instr_array = INSTR_ANDI then 49 | res8 := imm8 and op8; 50 | else -- instr_array = INSTR_ORI 51 | res8 := imm8 or op8; 52 | end if; 53 | 54 | -- only write the result when activated 55 | if activate_exec_cr_mod = '1' then 56 | if instr_word(1 downto 0) = "00" then 57 | -- update MR 58 | modify_sr <= '1'; 59 | modified_sr <= res8 & register_file.ccr; 60 | elsif instr_word(1 downto 0) = "01" then 61 | -- update CCR 62 | modify_sr <= '1'; 63 | modified_sr <= register_file.mr & res8; 64 | elsif instr_word(1 downto 0) = "10" then 65 | -- update OMR 66 | modify_omr <= '1'; 67 | modified_omr <= res8; 68 | end if; 69 | end if; 70 | end process; 71 | 72 | end architecture; 73 | -------------------------------------------------------------------------------- /DSP/src/fetch_stage.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use ieee.numeric_std.all; 4 | library work; 5 | use work.parameter_pkg.all; 6 | use work.types_pkg.all; 7 | 8 | 9 | entity fetch_stage is port( 10 | 11 | pc_old : in unsigned(BW_ADDRESS-1 downto 0); 12 | pc_new : out unsigned(BW_ADDRESS-1 downto 0); 13 | modify_pc : in std_logic; 14 | modified_pc : in unsigned(BW_ADDRESS-1 downto 0); 15 | register_file : in register_file_type; 16 | decrement_lc : out std_logic; 17 | perform_enddo : out std_logic 18 | 19 | ); 20 | end fetch_stage; 21 | 22 | 23 | architecture rtl of fetch_stage is 24 | 25 | 26 | begin 27 | 28 | pc_calculation: process(pc_old, modify_pc, modified_pc, register_file) is 29 | begin 30 | decrement_lc <= '0'; 31 | perform_enddo <= '0'; 32 | 33 | -- by default increment pc by one 34 | pc_new <= pc_old + 1; 35 | if modify_pc = '1' then 36 | pc_new <= modified_pc; 37 | end if; 38 | -- Loop Flag set? 39 | if register_file.sr(15) = '1' then 40 | if register_file.la = pc_old then 41 | -- Loop not finished? 42 | -- => start from the beginning if necessary 43 | if register_file.lc /= 1 then 44 | -- if the last address was LA and the loop is not finished yet, we have to 45 | -- read now from the beginning of the loop again 46 | pc_new <= unsigned(register_file.current_ssh(BW_ADDRESS-1 downto 0)); 47 | -- decrement loop counter 48 | decrement_lc <= '1'; 49 | else 50 | -- loop done! 51 | -- => tell the loop controller in the exec stage to perform the enddo operation 52 | -- (without flushing of the pipeline!) 53 | perform_enddo <= '1'; 54 | end if; 55 | end if; 56 | end if; 57 | end process pc_calculation; 58 | 59 | end architecture rtl; 60 | 61 | -------------------------------------------------------------------------------- /DSP/src/parameter_pkg.vhd: -------------------------------------------------------------------------------- 1 | 2 | package parameter_pkg is 3 | 4 | constant BW_ADDRESS : natural := 16; 5 | 6 | constant PIPELINE_DEPTH : natural := 5; 7 | 8 | constant NUM_ACT_SIGNALS : natural := 26; 9 | 10 | end package; 11 | -------------------------------------------------------------------------------- /Interrupt_Handler/interrupt_handler.tdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Torlus/firebee-fpga/d07ee9b14405b2e00bd1d6589a1991cc32c86d0b/Interrupt_Handler/interrupt_handler.tdf -------------------------------------------------------------------------------- /Interrupt_Handler/interrupt_handler.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Torlus/firebee-fpga/d07ee9b14405b2e00bd1d6589a1991cc32c86d0b/Interrupt_Handler/interrupt_handler.v -------------------------------------------------------------------------------- /PLLJ_PLLSPE_INFO.txt: -------------------------------------------------------------------------------- 1 | PLL_Name altpll1:b2v_inst|altpll:altpll_component|altpll_8tp2:auto_generated|pll1 2 | PLLJITTER 33 3 | PLLSPEmax 84 4 | PLLSPEmin -53 5 | 6 | PLL_Name altpll2:b2v_inst12|altpll:altpll_component|altpll_1r33:auto_generated|pll1 7 | PLLJITTER 43 8 | PLLSPEmax 84 9 | PLLSPEmin -53 10 | 11 | PLL_Name altpll3:b2v_inst13|altpll:altpll_component|altpll_jvs2:auto_generated|pll1 12 | PLLJITTER NA 13 | PLLSPEmax 84 14 | PLLSPEmin -53 15 | 16 | PLL_Name altpll4:b2v_inst22|altpll:altpll_component|altpll_qfk2:auto_generated|pll1 17 | PLLJITTER 31 18 | PLLSPEmax 84 19 | PLLSPEmin -53 20 | 21 | -------------------------------------------------------------------------------- /Video/DDR_CTR.tdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Torlus/firebee-fpga/d07ee9b14405b2e00bd1d6589a1991cc32c86d0b/Video/DDR_CTR.tdf -------------------------------------------------------------------------------- /Video/DDR_CTR.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Torlus/firebee-fpga/d07ee9b14405b2e00bd1d6589a1991cc32c86d0b/Video/DDR_CTR.v -------------------------------------------------------------------------------- /Video/VIDEO_MOD_MUX_CLUTCTR.tdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Torlus/firebee-fpga/d07ee9b14405b2e00bd1d6589a1991cc32c86d0b/Video/VIDEO_MOD_MUX_CLUTCTR.tdf -------------------------------------------------------------------------------- /Video/VIDEO_MOD_MUX_CLUTCTR.v: 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https://raw.githubusercontent.com/Torlus/firebee-fpga/d07ee9b14405b2e00bd1d6589a1991cc32c86d0b/ahdl2v/VIDEO_MOD_MUX_CLUTCTR.tdf -------------------------------------------------------------------------------- /ahdl2v/VIDEO_MOD_MUX_CLUTCTR.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Torlus/firebee-fpga/d07ee9b14405b2e00bd1d6589a1991cc32c86d0b/ahdl2v/VIDEO_MOD_MUX_CLUTCTR.v -------------------------------------------------------------------------------- /ahdl2v/interrupt_handler.tdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Torlus/firebee-fpga/d07ee9b14405b2e00bd1d6589a1991cc32c86d0b/ahdl2v/interrupt_handler.tdf -------------------------------------------------------------------------------- /ahdl2v/interrupt_handler.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Torlus/firebee-fpga/d07ee9b14405b2e00bd1d6589a1991cc32c86d0b/ahdl2v/interrupt_handler.v -------------------------------------------------------------------------------- /ahdl2v/lpm_bustri.tdf: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------- 2 | -- 3 | -- LPM_BUSTRI Parameterized Megafunction 4 | -- 5 | -- Copyright (C) 1991-2013 Altera Corporation 6 | -- Your use of Altera Corporation's design tools, logic functions 7 | -- and other software and tools, and its AMPP partner logic 8 | -- functions, and any output files from any of the foregoing 9 | -- (including device programming or simulation files), and any 10 | -- associated documentation or information are expressly subject 11 | -- to the terms and conditions of the Altera Program License 12 | -- Subscription Agreement, Altera MegaCore Function License 13 | -- Agreement, or other applicable license agreement, including, 14 | -- without limitation, that your use is for the sole purpose of 15 | -- programming logic devices manufactured by Altera and sold by 16 | -- Altera or its authorized distributors. Please refer to the 17 | -- applicable agreement for further details. 18 | -- 19 | -- Quartus II 13.1.0 Build 162 10/23/2013 20 | -- 21 | -- Version 2.0 22 | -- 23 | -------------------------------------------------------------------- 24 | 25 | 26 | PARAMETERS 27 | ( 28 | LPM_WIDTH 29 | ); 30 | 31 | SUBDESIGN lpm_bustri 32 | ( 33 | tridata[LPM_WIDTH-1..0] : BIDIR; 34 | data[LPM_WIDTH-1..0] : INPUT = VCC; 35 | enabletr : INPUT = VCC; 36 | enabledt : INPUT = VCC; 37 | result[LPM_WIDTH-1..0] : OUTPUT; 38 | ) 39 | 40 | VARIABLE 41 | % Are the enable inputs used? % 42 | IF (USED(enabledt)) GENERATE 43 | dout[LPM_WIDTH-1..0] : TRI; 44 | END GENERATE; 45 | IF (USED(enabletr)) GENERATE 46 | din[LPM_WIDTH-1..0] : TRI; 47 | END GENERATE; 48 | 49 | BEGIN 50 | 51 | ASSERT (LPM_WIDTH > 0) 52 | REPORT "Value of LPM_WIDTH parameter value must be greater than 0" 53 | SEVERITY ERROR 54 | HELP_ID LPM_BUSTRI_WIDTH; 55 | 56 | ASSERT (USED(enabledt) & USED(data)) 57 | REPORT "lpm_bustri function requires data[] port -- Altera recommends using the TRI primitive instead" 58 | SEVERITY ERROR 59 | HELP_ID LPM_BUSTRI_DATA; 60 | 61 | % Connect buffers if they are used % 62 | IF (USED(enabledt)) GENERATE 63 | dout[].oe = enabledt; 64 | dout[] = data[]; 65 | tridata[] = dout[]; 66 | END GENERATE; 67 | 68 | IF (USED(enabletr)) GENERATE 69 | din[].oe = enabletr; 70 | din[] = tridata[]; 71 | result[] = din[]; 72 | ELSE GENERATE 73 | result[] = tridata[]; 74 | END GENERATE; 75 | IF !USED(result) GENERATE 76 | result[] = GND; 77 | END GENERATE; 78 | END; 79 | -------------------------------------------------------------------------------- /ahdl2v/lpm_bustri_BYT.inc: -------------------------------------------------------------------------------- 1 | --Copyright (C) 1991-2008 Altera Corporation 2 | --Your use of Altera Corporation's design tools, logic functions 3 | --and other software and tools, and its AMPP partner logic 4 | --functions, and any output files from any of the foregoing 5 | --(including device programming or simulation files), and any 6 | --associated documentation or information are expressly subject 7 | --to the terms and conditions of the Altera Program License 8 | --Subscription Agreement, Altera MegaCore Function License 9 | --Agreement, or other applicable license agreement, including, 10 | --without limitation, that your use is for the sole purpose of 11 | --programming logic devices manufactured by Altera and sold by 12 | --Altera or its authorized distributors. Please refer to the 13 | --applicable agreement for further details. 14 | 15 | 16 | FUNCTION lpm_bustri_BYT 17 | ( 18 | data[7..0], 19 | enabledt 20 | ) 21 | 22 | RETURNS ( 23 | tridata[7..0] 24 | ); 25 | -------------------------------------------------------------------------------- /ahdl2v/lpm_bustri_BYT.tdf: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------- 2 | -- 3 | -- LPM_BUSTRI Parameterized Megafunction 4 | -- 5 | -- Copyright (C) 1991-2013 Altera Corporation 6 | -- Your use of Altera Corporation's design tools, logic functions 7 | -- and other software and tools, and its AMPP partner logic 8 | -- functions, and any output files from any of the foregoing 9 | -- (including device programming or simulation files), and any 10 | -- associated documentation or information are expressly subject 11 | -- to the terms and conditions of the Altera Program License 12 | -- Subscription Agreement, Altera MegaCore Function License 13 | -- Agreement, or other applicable license agreement, including, 14 | -- without limitation, that your use is for the sole purpose of 15 | -- programming logic devices manufactured by Altera and sold by 16 | -- Altera or its authorized distributors. Please refer to the 17 | -- applicable agreement for further details. 18 | -- 19 | -- Quartus II 13.1.0 Build 162 10/23/2013 20 | -- 21 | -- Version 2.0 22 | -- 23 | -------------------------------------------------------------------- 24 | 25 | SUBDESIGN lpm_bustri_BYT 26 | ( 27 | tridata[8-1..0] : BIDIR; 28 | data[8-1..0] : INPUT = VCC; 29 | enabletr : INPUT = VCC; 30 | enabledt : INPUT = VCC; 31 | result[8-1..0] : OUTPUT; 32 | ) 33 | 34 | VARIABLE 35 | % Are the enable inputs used? % 36 | IF (USED(enabledt)) GENERATE 37 | dout[8-1..0] : TRI; 38 | END GENERATE; 39 | IF (USED(enabletr)) GENERATE 40 | din[8-1..0] : TRI; 41 | END GENERATE; 42 | 43 | BEGIN 44 | 45 | ASSERT (8 > 0) 46 | REPORT "Value of 8 parameter value must be greater than 0" 47 | SEVERITY ERROR 48 | HELP_ID LPM_BUSTRI_WIDTH; 49 | 50 | ASSERT (USED(enabledt) & USED(data)) 51 | REPORT "lpm_bustri function requires data[] port -- Altera recommends using the TRI primitive instead" 52 | SEVERITY ERROR 53 | HELP_ID LPM_BUSTRI_DATA; 54 | 55 | % Connect buffers if they are used % 56 | IF (USED(enabledt)) GENERATE 57 | dout[].oe = enabledt; 58 | dout[] = data[]; 59 | tridata[] = dout[]; 60 | END GENERATE; 61 | 62 | IF (USED(enabletr)) GENERATE 63 | din[].oe = enabletr; 64 | din[] = tridata[]; 65 | result[] = din[]; 66 | ELSE GENERATE 67 | result[] = tridata[]; 68 | END GENERATE; 69 | IF !USED(result) GENERATE 70 | result[] = GND; 71 | END GENERATE; 72 | END; 73 | -------------------------------------------------------------------------------- /ahdl2v/lpm_bustri_LONG.inc: -------------------------------------------------------------------------------- 1 | --Copyright (C) 1991-2008 Altera Corporation 2 | --Your use of Altera Corporation's design tools, logic functions 3 | --and other software and tools, and its AMPP partner logic 4 | --functions, and any output files from any of the foregoing 5 | --(including device programming or simulation files), and any 6 | --associated documentation or information are expressly subject 7 | --to the terms and conditions of the Altera Program License 8 | --Subscription Agreement, Altera MegaCore Function License 9 | --Agreement, or other applicable license agreement, including, 10 | --without limitation, that your use is for the sole purpose of 11 | --programming logic devices manufactured by Altera and sold by 12 | --Altera or its authorized distributors. Please refer to the 13 | --applicable agreement for further details. 14 | 15 | 16 | FUNCTION lpm_bustri_LONG 17 | ( 18 | data[31..0], 19 | enabledt 20 | ) 21 | 22 | RETURNS ( 23 | tridata[31..0] 24 | ); 25 | -------------------------------------------------------------------------------- /ahdl2v/lpm_bustri_LONG.tdf: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------- 2 | -- 3 | -- LPM_BUSTRI Parameterized Megafunction 4 | -- 5 | -- Copyright (C) 1991-2013 Altera Corporation 6 | -- Your use of Altera Corporation's design tools, logic functions 7 | -- and other software and tools, and its AMPP partner logic 8 | -- functions, and any output files from any of the foregoing 9 | -- (including device programming or simulation files), and any 10 | -- associated documentation or information are expressly subject 11 | -- to the terms and conditions of the Altera Program License 12 | -- Subscription Agreement, Altera MegaCore Function License 13 | -- Agreement, or other applicable license agreement, including, 14 | -- without limitation, that your use is for the sole purpose of 15 | -- programming logic devices manufactured by Altera and sold by 16 | -- Altera or its authorized distributors. Please refer to the 17 | -- applicable agreement for further details. 18 | -- 19 | -- Quartus II 13.1.0 Build 162 10/23/2013 20 | -- 21 | -- Version 2.0 22 | -- 23 | -------------------------------------------------------------------- 24 | 25 | SUBDESIGN lpm_bustri_LONG 26 | ( 27 | tridata[32-1..0] : BIDIR; 28 | data[32-1..0] : INPUT = VCC; 29 | enabletr : INPUT = VCC; 30 | enabledt : INPUT = VCC; 31 | result[32-1..0] : OUTPUT; 32 | ) 33 | 34 | VARIABLE 35 | % Are the enable inputs used? % 36 | IF (USED(enabledt)) GENERATE 37 | dout[32-1..0] : TRI; 38 | END GENERATE; 39 | IF (USED(enabletr)) GENERATE 40 | din[32-1..0] : TRI; 41 | END GENERATE; 42 | 43 | BEGIN 44 | 45 | ASSERT (32 > 0) 46 | REPORT "Value of 32 parameter value must be greater than 0" 47 | SEVERITY ERROR 48 | HELP_ID LPM_BUSTRI_WIDTH; 49 | 50 | ASSERT (USED(enabledt) & USED(data)) 51 | REPORT "lpm_bustri function requires data[] port -- Altera recommends using the TRI primitive instead" 52 | SEVERITY ERROR 53 | HELP_ID LPM_BUSTRI_DATA; 54 | 55 | % Connect buffers if they are used % 56 | IF (USED(enabledt)) GENERATE 57 | dout[].oe = enabledt; 58 | dout[] = data[]; 59 | tridata[] = dout[]; 60 | END GENERATE; 61 | 62 | IF (USED(enabletr)) GENERATE 63 | din[].oe = enabletr; 64 | din[] = tridata[]; 65 | result[] = din[]; 66 | ELSE GENERATE 67 | result[] = tridata[]; 68 | END GENERATE; 69 | IF !USED(result) GENERATE 70 | result[] = GND; 71 | END GENERATE; 72 | END; 73 | -------------------------------------------------------------------------------- /ahdl2v/lpm_bustri_LONG.v: -------------------------------------------------------------------------------- 1 | // Xilinx XPort Language Converter, Version 4.1 (110) 2 | // 3 | // AHDL Design Source: lpm_bustri_LONG.tdf 4 | // Verilog Design Output: lpm_bustri_LONG.v 5 | // Created 05-Mar-2014 12:37 AM 6 | // 7 | // Copyright (c) 2014, Xilinx, Inc. All Rights Reserved. 8 | // Xilinx Inc makes no warranty, expressed or implied, with respect to 9 | // the operation and/or functionality of the converted output files. 10 | // 11 | 12 | // 13 | // 14 | // *** this module FAILED during conversion 15 | //Look at error messages. 16 | // 17 | -------------------------------------------------------------------------------- /ahdl2v/lpm_bustri_WORD.inc: -------------------------------------------------------------------------------- 1 | --Copyright (C) 1991-2008 Altera Corporation 2 | --Your use of Altera Corporation's design tools, logic functions 3 | --and other software and tools, and its AMPP partner logic 4 | --functions, and any output files from any of the foregoing 5 | --(including device programming or simulation files), and any 6 | --associated documentation or information are expressly subject 7 | --to the terms and conditions of the Altera Program License 8 | --Subscription Agreement, Altera MegaCore Function License 9 | --Agreement, or other applicable license agreement, including, 10 | --without limitation, that your use is for the sole purpose of 11 | --programming logic devices manufactured by Altera and sold by 12 | --Altera or its authorized distributors. Please refer to the 13 | --applicable agreement for further details. 14 | 15 | 16 | FUNCTION lpm_bustri_WORD 17 | ( 18 | data[15..0], 19 | enabledt 20 | ) 21 | 22 | RETURNS ( 23 | tridata[15..0] 24 | ); 25 | -------------------------------------------------------------------------------- /ahdl2v/lpm_bustri_WORD.tdf: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------- 2 | -- 3 | -- LPM_BUSTRI Parameterized Megafunction 4 | -- 5 | -- Copyright (C) 1991-2013 Altera Corporation 6 | -- Your use of Altera Corporation's design tools, logic functions 7 | -- and other software and tools, and its AMPP partner logic 8 | -- functions, and any output files from any of the foregoing 9 | -- (including device programming or simulation files), and any 10 | -- associated documentation or information are expressly subject 11 | -- to the terms and conditions of the Altera Program License 12 | -- Subscription Agreement, Altera MegaCore Function License 13 | -- Agreement, or other applicable license agreement, including, 14 | -- without limitation, that your use is for the sole purpose of 15 | -- programming logic devices manufactured by Altera and sold by 16 | -- Altera or its authorized distributors. Please refer to the 17 | -- applicable agreement for further details. 18 | -- 19 | -- Quartus II 13.1.0 Build 162 10/23/2013 20 | -- 21 | -- Version 2.0 22 | -- 23 | -------------------------------------------------------------------- 24 | 25 | SUBDESIGN lpm_bustri_WORD 26 | ( 27 | tridata[16-1..0] : BIDIR; 28 | data[16-1..0] : INPUT = VCC; 29 | enabletr : INPUT = VCC; 30 | enabledt : INPUT = VCC; 31 | result[16-1..0] : OUTPUT; 32 | ) 33 | 34 | VARIABLE 35 | % Are the enable inputs used? % 36 | IF (USED(enabledt)) GENERATE 37 | dout[16-1..0] : TRI; 38 | END GENERATE; 39 | IF (USED(enabletr)) GENERATE 40 | din[16-1..0] : TRI; 41 | END GENERATE; 42 | 43 | BEGIN 44 | 45 | ASSERT (16 > 0) 46 | REPORT "Value of 16 parameter value must be greater than 0" 47 | SEVERITY ERROR 48 | HELP_ID LPM_BUSTRI_WIDTH; 49 | 50 | ASSERT (USED(enabledt) & USED(data)) 51 | REPORT "lpm_bustri function requires data[] port -- Altera recommends using the TRI primitive instead" 52 | SEVERITY ERROR 53 | HELP_ID LPM_BUSTRI_DATA; 54 | 55 | % Connect buffers if they are used % 56 | IF (USED(enabledt)) GENERATE 57 | dout[].oe = enabledt; 58 | dout[] = data[]; 59 | tridata[] = dout[]; 60 | END GENERATE; 61 | 62 | IF (USED(enabletr)) GENERATE 63 | din[].oe = enabletr; 64 | din[] = tridata[]; 65 | result[] = din[]; 66 | ELSE GENERATE 67 | result[] = tridata[]; 68 | END GENERATE; 69 | IF !USED(result) GENERATE 70 | result[] = GND; 71 | END GENERATE; 72 | END; 73 | -------------------------------------------------------------------------------- /ahdl2v/xport.exe: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Torlus/firebee-fpga/d07ee9b14405b2e00bd1d6589a1991cc32c86d0b/ahdl2v/xport.exe -------------------------------------------------------------------------------- /altdpram0.qip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Torlus/firebee-fpga/d07ee9b14405b2e00bd1d6589a1991cc32c86d0b/altdpram0.qip -------------------------------------------------------------------------------- /altip/altddio_bidir0.ppf: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | -------------------------------------------------------------------------------- /altip/altddio_bidir0.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "ALTDDIO_BIDIR" 2 | set_global_assignment -name IP_TOOL_VERSION "13.1" 3 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "altddio_bidir0.v"] 4 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_bidir0.ppf"] 5 | -------------------------------------------------------------------------------- /altip/altddio_out0.ppf: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | -------------------------------------------------------------------------------- /altip/altddio_out0.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "ALTDDIO_OUT" 2 | set_global_assignment -name IP_TOOL_VERSION "13.1" 3 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "altddio_out0.v"] 4 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out0.ppf"] 5 | -------------------------------------------------------------------------------- /altip/altddio_out1.ppf: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | -------------------------------------------------------------------------------- /altip/altddio_out1.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "ALTDDIO_OUT" 2 | set_global_assignment -name IP_TOOL_VERSION "13.1" 3 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "altddio_out1.v"] 4 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out1.ppf"] 5 | -------------------------------------------------------------------------------- /altip/altddio_out2.ppf: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | -------------------------------------------------------------------------------- /altip/altddio_out2.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "ALTDDIO_OUT" 2 | set_global_assignment -name IP_TOOL_VERSION "13.1" 3 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "altddio_out2.v"] 4 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out2.ppf"] 5 | -------------------------------------------------------------------------------- /altip/altddio_out3.ppf: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | -------------------------------------------------------------------------------- /altip/altddio_out3.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "ALTDDIO_OUT" 2 | set_global_assignment -name IP_TOOL_VERSION "13.1" 3 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "altddio_out3.v"] 4 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out3.ppf"] 5 | -------------------------------------------------------------------------------- /altip/altdpram0.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "RAM: 2-PORT" 2 | set_global_assignment -name IP_TOOL_VERSION "13.1" 3 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "altdpram0.v"] 4 | -------------------------------------------------------------------------------- /altip/altdpram1.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "RAM: 2-PORT" 2 | set_global_assignment -name IP_TOOL_VERSION "13.1" 3 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "altdpram1.v"] 4 | -------------------------------------------------------------------------------- /altip/altdpram2.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "RAM: 2-PORT" 2 | set_global_assignment -name IP_TOOL_VERSION "13.1" 3 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "altdpram2.v"] 4 | -------------------------------------------------------------------------------- /altip/altpll0.ppf: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | -------------------------------------------------------------------------------- /altip/altpll0.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "ALTPLL" 2 | set_global_assignment -name IP_TOOL_VERSION "13.1" 3 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "altpll0.v"] 4 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll0.ppf"] 5 | -------------------------------------------------------------------------------- /altip/altpll1.ppf: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | -------------------------------------------------------------------------------- /altip/altpll1.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "ALTPLL" 2 | set_global_assignment -name IP_TOOL_VERSION "13.1" 3 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "altpll1.v"] 4 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll1.ppf"] 5 | -------------------------------------------------------------------------------- /altip/altpll2.ppf: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | -------------------------------------------------------------------------------- /altip/altpll2.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "ALTPLL" 2 | set_global_assignment -name IP_TOOL_VERSION "13.1" 3 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "altpll2.v"] 4 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll2.ppf"] 5 | -------------------------------------------------------------------------------- /altip/altpll3.ppf: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | -------------------------------------------------------------------------------- /altip/altpll3.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "ALTPLL" 2 | set_global_assignment -name IP_TOOL_VERSION "13.1" 3 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "altpll3.v"] 4 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll3.ppf"] 5 | -------------------------------------------------------------------------------- /altip/altpll4.ppf: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | -------------------------------------------------------------------------------- /altip/altpll4.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "ALTPLL" 2 | set_global_assignment -name IP_TOOL_VERSION "13.1" 3 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "altpll4.v"] 4 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll4.ppf"] 5 | -------------------------------------------------------------------------------- /altip/altpll_reconfig1.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "ALTPLL_RECONFIG" 2 | set_global_assignment -name IP_TOOL_VERSION "13.1" 3 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "altpll_reconfig1.v"] 4 | -------------------------------------------------------------------------------- /altip/dcfifo0.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "FIFO" 2 | set_global_assignment -name IP_TOOL_VERSION "13.1" 3 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "dcfifo0.v"] 4 | -------------------------------------------------------------------------------- /altip/dcfifo1.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "FIFO" 2 | set_global_assignment -name IP_TOOL_VERSION "13.1" 3 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "dcfifo1.v"] 4 | -------------------------------------------------------------------------------- /altip/lpm_compare1.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "LPM_COMPARE" 2 | set_global_assignment -name IP_TOOL_VERSION "13.1" 3 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "lpm_compare1.v"] 4 | -------------------------------------------------------------------------------- /altip/lpm_constant0.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "LPM_CONSTANT" 2 | set_global_assignment -name IP_TOOL_VERSION "13.1" 3 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "lpm_constant0.v"] 4 | -------------------------------------------------------------------------------- /altip/lpm_constant1.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "LPM_CONSTANT" 2 | set_global_assignment -name IP_TOOL_VERSION "13.1" 3 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "lpm_constant1.v"] 4 | -------------------------------------------------------------------------------- /altip/lpm_constant2.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "LPM_CONSTANT" 2 | set_global_assignment -name IP_TOOL_VERSION "13.1" 3 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "lpm_constant2.v"] 4 | -------------------------------------------------------------------------------- /altip/lpm_constant3.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "LPM_CONSTANT" 2 | set_global_assignment -name IP_TOOL_VERSION "13.1" 3 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "lpm_constant3.v"] 4 | -------------------------------------------------------------------------------- /altip/lpm_constant4.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "LPM_CONSTANT" 2 | set_global_assignment -name IP_TOOL_VERSION "13.1" 3 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "lpm_constant4.v"] 4 | -------------------------------------------------------------------------------- /altip/lpm_counter0.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "LPM_COUNTER" 2 | set_global_assignment -name IP_TOOL_VERSION "13.1" 3 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "lpm_counter0.v"] 4 | -------------------------------------------------------------------------------- /altip/lpm_fifoDZ.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "FIFO" 2 | set_global_assignment -name IP_TOOL_VERSION "13.1" 3 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "lpm_fifoDZ.v"] 4 | -------------------------------------------------------------------------------- /altip/lpm_fifo_dc0.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "FIFO" 2 | set_global_assignment -name IP_TOOL_VERSION "13.1" 3 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "lpm_fifo_dc0.v"] 4 | -------------------------------------------------------------------------------- /altip/lpm_mux0.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "LPM_MUX" 2 | set_global_assignment -name IP_TOOL_VERSION "13.1" 3 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "lpm_mux0.v"] 4 | -------------------------------------------------------------------------------- /altip/lpm_mux1.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "LPM_MUX" 2 | set_global_assignment -name IP_TOOL_VERSION "13.1" 3 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "lpm_mux1.v"] 4 | -------------------------------------------------------------------------------- /altip/lpm_mux2.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "LPM_MUX" 2 | set_global_assignment -name IP_TOOL_VERSION "13.1" 3 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "lpm_mux2.v"] 4 | -------------------------------------------------------------------------------- /altip/lpm_mux3.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "LPM_MUX" 2 | set_global_assignment -name IP_TOOL_VERSION "13.1" 3 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "lpm_mux3.v"] 4 | -------------------------------------------------------------------------------- /altip/lpm_mux4.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "LPM_MUX" 2 | set_global_assignment -name IP_TOOL_VERSION "13.1" 3 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "lpm_mux4.v"] 4 | -------------------------------------------------------------------------------- /altip/lpm_mux5.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "LPM_MUX" 2 | set_global_assignment -name IP_TOOL_VERSION "13.1" 3 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "lpm_mux5.v"] 4 | -------------------------------------------------------------------------------- /altip/lpm_mux6.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "LPM_MUX" 2 | set_global_assignment -name IP_TOOL_VERSION "13.1" 3 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "lpm_mux6.v"] 4 | -------------------------------------------------------------------------------- /altip/lpm_muxDZ.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "LPM_MUX" 2 | set_global_assignment -name IP_TOOL_VERSION "13.1" 3 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "lpm_muxDZ.v"] 4 | -------------------------------------------------------------------------------- /altip/lpm_muxDZ2.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "LPM_MUX" 2 | set_global_assignment -name IP_TOOL_VERSION "13.1" 3 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "lpm_muxDZ2.v"] 4 | -------------------------------------------------------------------------------- /altip/lpm_muxVDM.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "LPM_MUX" 2 | set_global_assignment -name IP_TOOL_VERSION "13.1" 3 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "lpm_muxVDM.v"] 4 | -------------------------------------------------------------------------------- /altip/lpm_shiftreg0.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "LPM_SHIFTREG" 2 | set_global_assignment -name IP_TOOL_VERSION "13.1" 3 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "lpm_shiftreg0.v"] 4 | -------------------------------------------------------------------------------- /altip/lpm_shiftreg1.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "LPM_SHIFTREG" 2 | set_global_assignment -name IP_TOOL_VERSION "13.1" 3 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "lpm_shiftreg1.v"] 4 | -------------------------------------------------------------------------------- /altip/lpm_shiftreg2.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "LPM_SHIFTREG" 2 | set_global_assignment -name IP_TOOL_VERSION "13.1" 3 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "lpm_shiftreg2.v"] 4 | -------------------------------------------------------------------------------- /altip/lpm_shiftreg3.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "LPM_SHIFTREG" 2 | set_global_assignment -name IP_TOOL_VERSION "13.1" 3 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "lpm_shiftreg3.v"] 4 | -------------------------------------------------------------------------------- /altip/lpm_shiftreg4.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "LPM_SHIFTREG" 2 | set_global_assignment -name IP_TOOL_VERSION "13.1" 3 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "lpm_shiftreg4.v"] 4 | -------------------------------------------------------------------------------- /altip/lpm_shiftreg5.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "LPM_SHIFTREG" 2 | set_global_assignment -name IP_TOOL_VERSION "13.1" 3 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "lpm_shiftreg5.v"] 4 | -------------------------------------------------------------------------------- /altip/lpm_shiftreg6.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "LPM_SHIFTREG" 2 | set_global_assignment -name IP_TOOL_VERSION "13.1" 3 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "lpm_shiftreg6.v"] 4 | -------------------------------------------------------------------------------- /altip_orig/altddio_bidir0.inc: -------------------------------------------------------------------------------- 1 | --Copyright (C) 1991-2008 Altera Corporation 2 | --Your use of Altera Corporation's design tools, logic functions 3 | --and other software and tools, and its AMPP partner logic 4 | --functions, and any output files from any of the foregoing 5 | --(including device programming or simulation files), and any 6 | --associated documentation or information are expressly subject 7 | --to the terms and conditions of the Altera Program License 8 | --Subscription Agreement, Altera MegaCore Function License 9 | --Agreement, or other applicable license agreement, including, 10 | --without limitation, that your use is for the sole purpose of 11 | --programming logic devices manufactured by Altera and sold by 12 | --Altera or its authorized distributors. Please refer to the 13 | --applicable agreement for further details. 14 | 15 | 16 | FUNCTION altddio_bidir0 17 | ( 18 | datain_h[31..0], 19 | datain_l[31..0], 20 | inclock, 21 | oe, 22 | outclock 23 | ) 24 | 25 | RETURNS ( 26 | combout[31..0], 27 | dataout_h[31..0], 28 | dataout_l[31..0], 29 | padio[31..0] 30 | ); 31 | -------------------------------------------------------------------------------- /altip_orig/altddio_bidir0.ppf: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | -------------------------------------------------------------------------------- /altip_orig/altddio_bidir0.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "ALTDDIO_BIDIR" 2 | set_global_assignment -name IP_TOOL_VERSION "8.1" 3 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altddio_bidir0.vhd"] 4 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_bidir0.bsf"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_bidir0.inc"] 6 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_bidir0.cmp"] 7 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_bidir0.ppf"] 8 | -------------------------------------------------------------------------------- /altip_orig/altddio_out0.inc: -------------------------------------------------------------------------------- 1 | --Copyright (C) 1991-2008 Altera Corporation 2 | --Your use of Altera Corporation's design tools, logic functions 3 | --and other software and tools, and its AMPP partner logic 4 | --functions, and any output files from any of the foregoing 5 | --(including device programming or simulation files), and any 6 | --associated documentation or information are expressly subject 7 | --to the terms and conditions of the Altera Program License 8 | --Subscription Agreement, Altera MegaCore Function License 9 | --Agreement, or other applicable license agreement, including, 10 | --without limitation, that your use is for the sole purpose of 11 | --programming logic devices manufactured by Altera and sold by 12 | --Altera or its authorized distributors. Please refer to the 13 | --applicable agreement for further details. 14 | 15 | 16 | FUNCTION altddio_out0 17 | ( 18 | datain_h, 19 | datain_l, 20 | outclock 21 | ) 22 | 23 | RETURNS ( 24 | dataout 25 | ); 26 | -------------------------------------------------------------------------------- /altip_orig/altddio_out0.ppf: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | -------------------------------------------------------------------------------- /altip_orig/altddio_out0.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "ALTDDIO_OUT" 2 | set_global_assignment -name IP_TOOL_VERSION "13.1" 3 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "altddio_out0.v"] 4 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out0_bb.v"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out0.ppf"] 6 | -------------------------------------------------------------------------------- /altip_orig/altddio_out1.inc: -------------------------------------------------------------------------------- 1 | --Copyright (C) 1991-2008 Altera Corporation 2 | --Your use of Altera Corporation's design tools, logic functions 3 | --and other software and tools, and its AMPP partner logic 4 | --functions, and any output files from any of the foregoing 5 | --(including device programming or simulation files), and any 6 | --associated documentation or information are expressly subject 7 | --to the terms and conditions of the Altera Program License 8 | --Subscription Agreement, Altera MegaCore Function License 9 | --Agreement, or other applicable license agreement, including, 10 | --without limitation, that your use is for the sole purpose of 11 | --programming logic devices manufactured by Altera and sold by 12 | --Altera or its authorized distributors. Please refer to the 13 | --applicable agreement for further details. 14 | 15 | 16 | FUNCTION altddio_out1 17 | ( 18 | datain_h, 19 | datain_l, 20 | outclock 21 | ) 22 | 23 | RETURNS ( 24 | dataout 25 | ); 26 | -------------------------------------------------------------------------------- /altip_orig/altddio_out1.ppf: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | -------------------------------------------------------------------------------- /altip_orig/altddio_out1.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "ALTDDIO_OUT" 2 | set_global_assignment -name IP_TOOL_VERSION "8.1" 3 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altddio_out1.vhd"] 4 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out1.bsf"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out1.inc"] 6 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out1.cmp"] 7 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out1.ppf"] 8 | -------------------------------------------------------------------------------- /altip_orig/altddio_out2.inc: -------------------------------------------------------------------------------- 1 | --Copyright (C) 1991-2008 Altera Corporation 2 | --Your use of Altera Corporation's design tools, logic functions 3 | --and other software and tools, and its AMPP partner logic 4 | --functions, and any output files from any of the foregoing 5 | --(including device programming or simulation files), and any 6 | --associated documentation or information are expressly subject 7 | --to the terms and conditions of the Altera Program License 8 | --Subscription Agreement, Altera MegaCore Function License 9 | --Agreement, or other applicable license agreement, including, 10 | --without limitation, that your use is for the sole purpose of 11 | --programming logic devices manufactured by Altera and sold by 12 | --Altera or its authorized distributors. Please refer to the 13 | --applicable agreement for further details. 14 | 15 | 16 | FUNCTION altddio_out2 17 | ( 18 | datain_h[23..0], 19 | datain_l[23..0], 20 | outclock 21 | ) 22 | 23 | RETURNS ( 24 | dataout[23..0] 25 | ); 26 | -------------------------------------------------------------------------------- /altip_orig/altddio_out2.ppf: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | -------------------------------------------------------------------------------- /altip_orig/altddio_out2.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "ALTDDIO_OUT" 2 | set_global_assignment -name IP_TOOL_VERSION "8.1" 3 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altddio_out2.vhd"] 4 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out2.bsf"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out2.inc"] 6 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out2.cmp"] 7 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out2.ppf"] 8 | -------------------------------------------------------------------------------- /altip_orig/altddio_out3.inc: -------------------------------------------------------------------------------- 1 | --Copyright (C) 1991-2008 Altera Corporation 2 | --Your use of Altera Corporation's design tools, logic functions 3 | --and other software and tools, and its AMPP partner logic 4 | --functions, and any output files from any of the foregoing 5 | --(including device programming or simulation files), and any 6 | --associated documentation or information are expressly subject 7 | --to the terms and conditions of the Altera Program License 8 | --Subscription Agreement, Altera MegaCore Function License 9 | --Agreement, or other applicable license agreement, including, 10 | --without limitation, that your use is for the sole purpose of 11 | --programming logic devices manufactured by Altera and sold by 12 | --Altera or its authorized distributors. Please refer to the 13 | --applicable agreement for further details. 14 | 15 | 16 | FUNCTION altddio_out3 17 | ( 18 | datain_h, 19 | datain_l, 20 | outclock 21 | ) 22 | 23 | RETURNS ( 24 | dataout 25 | ); 26 | -------------------------------------------------------------------------------- /altip_orig/altddio_out3.ppf: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | -------------------------------------------------------------------------------- /altip_orig/altddio_out3.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "ALTDDIO_OUT" 2 | set_global_assignment -name IP_TOOL_VERSION "13.1" 3 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "altddio_out3.v"] 4 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out3.ppf"] 5 | -------------------------------------------------------------------------------- /altip_orig/altdpram0.inc: -------------------------------------------------------------------------------- 1 | --Copyright (C) 1991-2008 Altera Corporation 2 | --Your use of Altera Corporation's design tools, logic functions 3 | --and other software and tools, and its AMPP partner logic 4 | --functions, and any output files from any of the foregoing 5 | --(including device programming or simulation files), and any 6 | --associated documentation or information are expressly subject 7 | --to the terms and conditions of the Altera Program License 8 | --Subscription Agreement, Altera MegaCore Function License 9 | --Agreement, or other applicable license agreement, including, 10 | --without limitation, that your use is for the sole purpose of 11 | --programming logic devices manufactured by Altera and sold by 12 | --Altera or its authorized distributors. Please refer to the 13 | --applicable agreement for further details. 14 | 15 | 16 | FUNCTION altdpram0 17 | ( 18 | address_a[3..0], 19 | address_b[3..0], 20 | clock_a, 21 | clock_b, 22 | data_a[2..0], 23 | data_b[2..0], 24 | wren_a, 25 | wren_b 26 | ) 27 | 28 | RETURNS ( 29 | q_a[2..0], 30 | q_b[2..0] 31 | ); 32 | -------------------------------------------------------------------------------- /altip_orig/altdpram0.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "LPM_RAM_DP+" 2 | set_global_assignment -name IP_TOOL_VERSION "8.1" 3 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altdpram0.vhd"] 4 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altdpram0.bsf"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altdpram0.inc"] 6 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altdpram0.cmp"] 7 | -------------------------------------------------------------------------------- /altip_orig/altdpram1.inc: -------------------------------------------------------------------------------- 1 | --Copyright (C) 1991-2008 Altera Corporation 2 | --Your use of Altera Corporation's design tools, logic functions 3 | --and other software and tools, and its AMPP partner logic 4 | --functions, and any output files from any of the foregoing 5 | --(including device programming or simulation files), and any 6 | --associated documentation or information are expressly subject 7 | --to the terms and conditions of the Altera Program License 8 | --Subscription Agreement, Altera MegaCore Function License 9 | --Agreement, or other applicable license agreement, including, 10 | --without limitation, that your use is for the sole purpose of 11 | --programming logic devices manufactured by Altera and sold by 12 | --Altera or its authorized distributors. Please refer to the 13 | --applicable agreement for further details. 14 | 15 | 16 | FUNCTION altdpram1 17 | ( 18 | address_a[7..0], 19 | address_b[7..0], 20 | clock_a, 21 | clock_b, 22 | data_a[5..0], 23 | data_b[5..0], 24 | wren_a, 25 | wren_b 26 | ) 27 | 28 | RETURNS ( 29 | q_a[5..0], 30 | q_b[5..0] 31 | ); 32 | -------------------------------------------------------------------------------- /altip_orig/altdpram1.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "LPM_RAM_DP+" 2 | set_global_assignment -name IP_TOOL_VERSION "8.1" 3 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altdpram1.vhd"] 4 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altdpram1.bsf"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altdpram1.inc"] 6 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altdpram1.cmp"] 7 | -------------------------------------------------------------------------------- /altip_orig/altdpram2.inc: -------------------------------------------------------------------------------- 1 | --Copyright (C) 1991-2008 Altera Corporation 2 | --Your use of Altera Corporation's design tools, logic functions 3 | --and other software and tools, and its AMPP partner logic 4 | --functions, and any output files from any of the foregoing 5 | --(including device programming or simulation files), and any 6 | --associated documentation or information are expressly subject 7 | --to the terms and conditions of the Altera Program License 8 | --Subscription Agreement, Altera MegaCore Function License 9 | --Agreement, or other applicable license agreement, including, 10 | --without limitation, that your use is for the sole purpose of 11 | --programming logic devices manufactured by Altera and sold by 12 | --Altera or its authorized distributors. Please refer to the 13 | --applicable agreement for further details. 14 | 15 | 16 | FUNCTION altdpram2 17 | ( 18 | address_a[7..0], 19 | address_b[7..0], 20 | clock_a, 21 | clock_b, 22 | data_a[7..0], 23 | data_b[7..0], 24 | wren_a, 25 | wren_b 26 | ) 27 | 28 | RETURNS ( 29 | q_a[7..0], 30 | q_b[7..0] 31 | ); 32 | -------------------------------------------------------------------------------- /altip_orig/altdpram2.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "LPM_RAM_DP+" 2 | set_global_assignment -name IP_TOOL_VERSION "8.1" 3 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altdpram2.vhd"] 4 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altdpram2.bsf"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altdpram2.inc"] 6 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altdpram2.cmp"] 7 | -------------------------------------------------------------------------------- /altip_orig/altpll0.inc: -------------------------------------------------------------------------------- 1 | --Copyright (C) 1991-2010 Altera Corporation 2 | --Your use of Altera Corporation's design tools, logic functions 3 | --and other software and tools, and its AMPP partner logic 4 | --functions, and any output files from any of the foregoing 5 | --(including device programming or simulation files), and any 6 | --associated documentation or information are expressly subject 7 | --to the terms and conditions of the Altera Program License 8 | --Subscription Agreement, Altera MegaCore Function License 9 | --Agreement, or other applicable license agreement, including, 10 | --without limitation, that your use is for the sole purpose of 11 | --programming logic devices manufactured by Altera and sold by 12 | --Altera or its authorized distributors. Please refer to the 13 | --applicable agreement for further details. 14 | 15 | 16 | FUNCTION altpll0 17 | ( 18 | inclk0 19 | ) 20 | 21 | RETURNS ( 22 | c0, 23 | c1, 24 | c2, 25 | c3, 26 | c4 27 | ); 28 | -------------------------------------------------------------------------------- /altip_orig/altpll0.ppf: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | -------------------------------------------------------------------------------- /altip_orig/altpll0.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "ALTPLL" 2 | set_global_assignment -name IP_TOOL_VERSION "9.1" 3 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altpll0.vhd"] 4 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll0.bsf"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll0.inc"] 6 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll0.cmp"] 7 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll0.ppf"] 8 | -------------------------------------------------------------------------------- /altip_orig/altpll1.inc: -------------------------------------------------------------------------------- 1 | --Copyright (C) 1991-2010 Altera Corporation 2 | --Your use of Altera Corporation's design tools, logic functions 3 | --and other software and tools, and its AMPP partner logic 4 | --functions, and any output files from any of the foregoing 5 | --(including device programming or simulation files), and any 6 | --associated documentation or information are expressly subject 7 | --to the terms and conditions of the Altera Program License 8 | --Subscription Agreement, Altera MegaCore Function License 9 | --Agreement, or other applicable license agreement, including, 10 | --without limitation, that your use is for the sole purpose of 11 | --programming logic devices manufactured by Altera and sold by 12 | --Altera or its authorized distributors. Please refer to the 13 | --applicable agreement for further details. 14 | 15 | 16 | FUNCTION altpll1 17 | ( 18 | inclk0 19 | ) 20 | 21 | RETURNS ( 22 | c0, 23 | c1, 24 | c2, 25 | locked 26 | ); 27 | -------------------------------------------------------------------------------- /altip_orig/altpll1.ppf: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | -------------------------------------------------------------------------------- /altip_orig/altpll1.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "ALTPLL" 2 | set_global_assignment -name IP_TOOL_VERSION "9.1" 3 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altpll1.vhd"] 4 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll1.bsf"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll1.inc"] 6 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll1.cmp"] 7 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll1.ppf"] 8 | -------------------------------------------------------------------------------- /altip_orig/altpll2.inc: -------------------------------------------------------------------------------- 1 | --Copyright (C) 1991-2010 Altera Corporation 2 | --Your use of Altera Corporation's design tools, logic functions 3 | --and other software and tools, and its AMPP partner logic 4 | --functions, and any output files from any of the foregoing 5 | --(including device programming or simulation files), and any 6 | --associated documentation or information are expressly subject 7 | --to the terms and conditions of the Altera Program License 8 | --Subscription Agreement, Altera MegaCore Function License 9 | --Agreement, or other applicable license agreement, including, 10 | --without limitation, that your use is for the sole purpose of 11 | --programming logic devices manufactured by Altera and sold by 12 | --Altera or its authorized distributors. Please refer to the 13 | --applicable agreement for further details. 14 | 15 | 16 | FUNCTION altpll2 17 | ( 18 | inclk0 19 | ) 20 | 21 | RETURNS ( 22 | c0, 23 | c1, 24 | c2, 25 | c3, 26 | c4 27 | ); 28 | -------------------------------------------------------------------------------- /altip_orig/altpll2.ppf: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | -------------------------------------------------------------------------------- /altip_orig/altpll2.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "ALTPLL" 2 | set_global_assignment -name IP_TOOL_VERSION "9.1" 3 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altpll2.vhd"] 4 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll2.bsf"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll2.inc"] 6 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll2.cmp"] 7 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll2.ppf"] 8 | -------------------------------------------------------------------------------- /altip_orig/altpll3.inc: -------------------------------------------------------------------------------- 1 | --Copyright (C) 1991-2010 Altera Corporation 2 | --Your use of Altera Corporation's design tools, logic functions 3 | --and other software and tools, and its AMPP partner logic 4 | --functions, and any output files from any of the foregoing 5 | --(including device programming or simulation files), and any 6 | --associated documentation or information are expressly subject 7 | --to the terms and conditions of the Altera Program License 8 | --Subscription Agreement, Altera MegaCore Function License 9 | --Agreement, or other applicable license agreement, including, 10 | --without limitation, that your use is for the sole purpose of 11 | --programming logic devices manufactured by Altera and sold by 12 | --Altera or its authorized distributors. Please refer to the 13 | --applicable agreement for further details. 14 | 15 | 16 | FUNCTION altpll3 17 | ( 18 | inclk0 19 | ) 20 | 21 | RETURNS ( 22 | c0, 23 | c1, 24 | c2, 25 | c3 26 | ); 27 | -------------------------------------------------------------------------------- /altip_orig/altpll3.ppf: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | -------------------------------------------------------------------------------- /altip_orig/altpll3.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "ALTPLL" 2 | set_global_assignment -name IP_TOOL_VERSION "9.1" 3 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altpll3.vhd"] 4 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll3.bsf"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll3.inc"] 6 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll3.cmp"] 7 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll3.ppf"] 8 | -------------------------------------------------------------------------------- /altip_orig/altpll4.inc: -------------------------------------------------------------------------------- 1 | --Copyright (C) 1991-2010 Altera Corporation 2 | --Your use of Altera Corporation's design tools, logic functions 3 | --and other software and tools, and its AMPP partner logic 4 | --functions, and any output files from any of the foregoing 5 | --(including device programming or simulation files), and any 6 | --associated documentation or information are expressly subject 7 | --to the terms and conditions of the Altera Program License 8 | --Subscription Agreement, Altera MegaCore Function License 9 | --Agreement, or other applicable license agreement, including, 10 | --without limitation, that your use is for the sole purpose of 11 | --programming logic devices manufactured by Altera and sold by 12 | --Altera or its authorized distributors. Please refer to the 13 | --applicable agreement for further details. 14 | 15 | 16 | FUNCTION altpll4 17 | ( 18 | areset, 19 | configupdate, 20 | inclk0, 21 | scanclk, 22 | scanclkena, 23 | scandata 24 | ) 25 | 26 | RETURNS ( 27 | c0, 28 | locked, 29 | scandataout, 30 | scandone 31 | ); 32 | -------------------------------------------------------------------------------- /altip_orig/altpll4.ppf: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | -------------------------------------------------------------------------------- /altip_orig/altpll4.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "ALTPLL" 2 | set_global_assignment -name IP_TOOL_VERSION "9.1" 3 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll4.tdf"] 4 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll4.bsf"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll4.inc"] 6 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll4.cmp"] 7 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll4.ppf"] 8 | -------------------------------------------------------------------------------- /altip_orig/altpll_reconfig0.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "ALTPLL_RECONFIG" 2 | set_global_assignment -name IP_TOOL_VERSION "9.1" 3 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll_reconfig0.tdf"] 4 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll_reconfig0.bsf"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll_reconfig0.cmp"] 6 | -------------------------------------------------------------------------------- /altip_orig/altpll_reconfig1.inc: -------------------------------------------------------------------------------- 1 | --Copyright (C) 1991-2010 Altera Corporation 2 | --Your use of Altera Corporation's design tools, logic functions 3 | --and other software and tools, and its AMPP partner logic 4 | --functions, and any output files from any of the foregoing 5 | --(including device programming or simulation files), and any 6 | --associated documentation or information are expressly subject 7 | --to the terms and conditions of the Altera Program License 8 | --Subscription Agreement, Altera MegaCore Function License 9 | --Agreement, or other applicable license agreement, including, 10 | --without limitation, that your use is for the sole purpose of 11 | --programming logic devices manufactured by Altera and sold by 12 | --Altera or its authorized distributors. Please refer to the 13 | --applicable agreement for further details. 14 | 15 | 16 | FUNCTION altpll_reconfig1 17 | ( 18 | clock, 19 | counter_param[2..0], 20 | counter_type[3..0], 21 | data_in[8..0], 22 | pll_areset_in, 23 | pll_scandataout, 24 | pll_scandone, 25 | read_param, 26 | reconfig, 27 | reset, 28 | write_param 29 | ) 30 | 31 | RETURNS ( 32 | busy, 33 | data_out[8..0], 34 | pll_areset, 35 | pll_configupdate, 36 | pll_scanclk, 37 | pll_scanclkena, 38 | pll_scandata 39 | ); 40 | -------------------------------------------------------------------------------- /altip_orig/altpll_reconfig1.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "ALTPLL_RECONFIG" 2 | set_global_assignment -name IP_TOOL_VERSION "9.1" 3 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll_reconfig1.tdf"] 4 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll_reconfig1.bsf"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll_reconfig1.inc"] 6 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll_reconfig1.cmp"] 7 | -------------------------------------------------------------------------------- /altip_orig/dcfifo0.cmp: -------------------------------------------------------------------------------- 1 | --Copyright (C) 1991-2009 Altera Corporation 2 | --Your use of Altera Corporation's design tools, logic functions 3 | --and other software and tools, and its AMPP partner logic 4 | --functions, and any output files from any of the foregoing 5 | --(including device programming or simulation files), and any 6 | --associated documentation or information are expressly subject 7 | --to the terms and conditions of the Altera Program License 8 | --Subscription Agreement, Altera MegaCore Function License 9 | --Agreement, or other applicable license agreement, including, 10 | --without limitation, that your use is for the sole purpose of 11 | --programming logic devices manufactured by Altera and sold by 12 | --Altera or its authorized distributors. Please refer to the 13 | --applicable agreement for further details. 14 | 15 | 16 | component dcfifo0 17 | PORT 18 | ( 19 | aclr : IN STD_LOGIC := '0'; 20 | data : IN STD_LOGIC_VECTOR (7 DOWNTO 0); 21 | rdclk : IN STD_LOGIC ; 22 | rdreq : IN STD_LOGIC ; 23 | wrclk : IN STD_LOGIC ; 24 | wrreq : IN STD_LOGIC ; 25 | q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0); 26 | wrusedw : OUT STD_LOGIC_VECTOR (9 DOWNTO 0) 27 | ); 28 | end component; 29 | -------------------------------------------------------------------------------- /altip_orig/dcfifo0.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "LPM_FIFO+" 2 | set_global_assignment -name IP_TOOL_VERSION "9.1" 3 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "dcfifo0.vhd"] 4 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "dcfifo0.bsf"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "dcfifo0.cmp"] 6 | -------------------------------------------------------------------------------- /altip_orig/dcfifo1.cmp: -------------------------------------------------------------------------------- 1 | --Copyright (C) 1991-2009 Altera Corporation 2 | --Your use of Altera Corporation's design tools, logic functions 3 | --and other software and tools, and its AMPP partner logic 4 | --functions, and any output files from any of the foregoing 5 | --(including device programming or simulation files), and any 6 | --associated documentation or information are expressly subject 7 | --to the terms and conditions of the Altera Program License 8 | --Subscription Agreement, Altera MegaCore Function License 9 | --Agreement, or other applicable license agreement, including, 10 | --without limitation, that your use is for the sole purpose of 11 | --programming logic devices manufactured by Altera and sold by 12 | --Altera or its authorized distributors. Please refer to the 13 | --applicable agreement for further details. 14 | 15 | 16 | component dcfifo1 17 | PORT 18 | ( 19 | aclr : IN STD_LOGIC := '0'; 20 | data : IN STD_LOGIC_VECTOR (31 DOWNTO 0); 21 | rdclk : IN STD_LOGIC ; 22 | rdreq : IN STD_LOGIC ; 23 | wrclk : IN STD_LOGIC ; 24 | wrreq : IN STD_LOGIC ; 25 | q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); 26 | rdusedw : OUT STD_LOGIC_VECTOR (9 DOWNTO 0) 27 | ); 28 | end component; 29 | -------------------------------------------------------------------------------- /altip_orig/dcfifo1.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "LPM_FIFO+" 2 | set_global_assignment -name IP_TOOL_VERSION "9.1" 3 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "dcfifo1.vhd"] 4 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "dcfifo1.bsf"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "dcfifo1.cmp"] 6 | -------------------------------------------------------------------------------- /altip_orig/lpm_bustri0.bsf: -------------------------------------------------------------------------------- 1 | /* 2 | WARNING: Do NOT edit the input and output ports in this file in a text 3 | editor if you plan to continue editing the block that represents it in 4 | the Block Editor! File corruption is VERY likely to occur. 5 | */ 6 | /* 7 | Copyright (C) 1991-2008 Altera Corporation 8 | Your use of Altera Corporation's design tools, logic functions 9 | and other software and tools, and its AMPP partner logic 10 | functions, and any output files from any of the foregoing 11 | (including device programming or simulation files), and any 12 | associated documentation or information are expressly subject 13 | to the terms and conditions of the Altera Program License 14 | Subscription Agreement, Altera MegaCore Function License 15 | Agreement, or other applicable license agreement, including, 16 | without limitation, that your use is for the sole purpose of 17 | programming logic devices manufactured by Altera and sold by 18 | Altera or its authorized distributors. Please refer to the 19 | applicable agreement for further details. 20 | */ 21 | (header "symbol" (version "1.1")) 22 | (symbol 23 | (rect 0 0 80 40) 24 | (text "lpm_bustri0" (rect 7 1 86 17)(font "Arial" (font_size 10))) 25 | (text "inst" (rect 8 24 25 36)(font "Arial" )) 26 | (port 27 | (pt 40 40) 28 | (input) 29 | (text "enabledt" (rect 0 0 48 14)(font "Arial" (font_size 8))) 30 | (text "enabledt" (rect 40 -6 53 36)(font "Arial" (font_size 8))(invisible)) 31 | (line (pt 40 40)(pt 40 28)(line_width 1)) 32 | ) 33 | (port 34 | (pt 0 24) 35 | (input) 36 | (text "data[31..0]" (rect 0 0 60 14)(font "Arial" (font_size 8))) 37 | (text "data[31..0]" (rect -3 -27 10 24)(font "Arial" (font_size 8))(invisible)) 38 | (line (pt 0 24)(pt 32 24)(line_width 3)) 39 | ) 40 | (port 41 | (pt 80 24) 42 | (bidir) 43 | (text "tridata[31..0]" (rect 0 0 70 14)(font "Arial" (font_size 8))) 44 | (text "tridata[31..0]" (rect 84 -36 97 24)(font "Arial" (font_size 8))(invisible)) 45 | (line (pt 80 24)(pt 48 24)(line_width 3)) 46 | ) 47 | (drawing 48 | (text "32" (rect 61 25 71 37)(font "Arial" )) 49 | (text "32" (rect 13 25 23 37)(font "Arial" )) 50 | (line (pt 32 16)(pt 48 24)(line_width 1)) 51 | (line (pt 48 24)(pt 32 32)(line_width 1)) 52 | (line (pt 32 32)(pt 32 16)(line_width 1)) 53 | (line (pt 56 28)(pt 64 20)(line_width 1)) 54 | (line (pt 8 28)(pt 16 20)(line_width 1)) 55 | ) 56 | ) 57 | -------------------------------------------------------------------------------- /altip_orig/lpm_bustri0.inc: -------------------------------------------------------------------------------- 1 | --Copyright (C) 1991-2008 Altera Corporation 2 | --Your use of Altera Corporation's design tools, logic functions 3 | --and other software and tools, and its AMPP partner logic 4 | --functions, and any output files from any of the foregoing 5 | --(including device programming or simulation files), and any 6 | --associated documentation or information are expressly subject 7 | --to the terms and conditions of the Altera Program License 8 | --Subscription Agreement, Altera MegaCore Function License 9 | --Agreement, or other applicable license agreement, including, 10 | --without limitation, that your use is for the sole purpose of 11 | --programming logic devices manufactured by Altera and sold by 12 | --Altera or its authorized distributors. Please refer to the 13 | --applicable agreement for further details. 14 | 15 | 16 | FUNCTION lpm_bustri0 17 | ( 18 | data[31..0], 19 | enabledt 20 | ) 21 | 22 | RETURNS ( 23 | tridata[31..0] 24 | ); 25 | -------------------------------------------------------------------------------- /altip_orig/lpm_bustri0.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "LPM_BUSTRI" 2 | set_global_assignment -name IP_TOOL_VERSION "8.1" 3 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_bustri0.vhd"] 4 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri0.bsf"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri0.inc"] 6 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri0.cmp"] 7 | -------------------------------------------------------------------------------- /altip_orig/lpm_bustri1.bsf: -------------------------------------------------------------------------------- 1 | /* 2 | WARNING: Do NOT edit the input and output ports in this file in a text 3 | editor if you plan to continue editing the block that represents it in 4 | the Block Editor! File corruption is VERY likely to occur. 5 | */ 6 | /* 7 | Copyright (C) 1991-2008 Altera Corporation 8 | Your use of Altera Corporation's design tools, logic functions 9 | and other software and tools, and its AMPP partner logic 10 | functions, and any output files from any of the foregoing 11 | (including device programming or simulation files), and any 12 | associated documentation or information are expressly subject 13 | to the terms and conditions of the Altera Program License 14 | Subscription Agreement, Altera MegaCore Function License 15 | Agreement, or other applicable license agreement, including, 16 | without limitation, that your use is for the sole purpose of 17 | programming logic devices manufactured by Altera and sold by 18 | Altera or its authorized distributors. Please refer to the 19 | applicable agreement for further details. 20 | */ 21 | (header "symbol" (version "1.1")) 22 | (symbol 23 | (rect 0 0 80 40) 24 | (text "lpm_bustri1" (rect 7 1 86 17)(font "Arial" (font_size 10))) 25 | (text "inst" (rect 8 24 25 36)(font "Arial" )) 26 | (port 27 | (pt 40 40) 28 | (input) 29 | (text "enabledt" (rect 0 0 48 14)(font "Arial" (font_size 8))) 30 | (text "enabledt" (rect 40 -6 53 36)(font "Arial" (font_size 8))(invisible)) 31 | (line (pt 40 40)(pt 40 28)(line_width 1)) 32 | ) 33 | (port 34 | (pt 0 24) 35 | (input) 36 | (text "data[2..0]" (rect 0 0 53 14)(font "Arial" (font_size 8))) 37 | (text "data[2..0]" (rect -3 -21 10 24)(font "Arial" (font_size 8))(invisible)) 38 | (line (pt 0 24)(pt 32 24)(line_width 3)) 39 | ) 40 | (port 41 | (pt 80 24) 42 | (bidir) 43 | (text "tridata[2..0]" (rect 0 0 63 14)(font "Arial" (font_size 8))) 44 | (text "tridata[2..0]" (rect 84 -30 97 24)(font "Arial" (font_size 8))(invisible)) 45 | (line (pt 80 24)(pt 48 24)(line_width 3)) 46 | ) 47 | (drawing 48 | (text "3" (rect 63 25 68 37)(font "Arial" )) 49 | (text "3" (rect 15 25 20 37)(font "Arial" )) 50 | (line (pt 32 16)(pt 48 24)(line_width 1)) 51 | (line (pt 48 24)(pt 32 32)(line_width 1)) 52 | (line (pt 32 32)(pt 32 16)(line_width 1)) 53 | (line (pt 58 28)(pt 66 20)(line_width 1)) 54 | (line (pt 10 28)(pt 18 20)(line_width 1)) 55 | ) 56 | ) 57 | -------------------------------------------------------------------------------- /altip_orig/lpm_bustri1.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "LPM_BUSTRI" 2 | set_global_assignment -name IP_TOOL_VERSION "8.1" 3 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_bustri1.vhd"] 4 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri1.bsf"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri1.cmp"] 6 | -------------------------------------------------------------------------------- /altip_orig/lpm_bustri2.bsf: -------------------------------------------------------------------------------- 1 | /* 2 | WARNING: Do NOT edit the input and output ports in this file in a text 3 | editor if you plan to continue editing the block that represents it in 4 | the Block Editor! File corruption is VERY likely to occur. 5 | */ 6 | /* 7 | Copyright (C) 1991-2008 Altera Corporation 8 | Your use of Altera Corporation's design tools, logic functions 9 | and other software and tools, and its AMPP partner logic 10 | functions, and any output files from any of the foregoing 11 | (including device programming or simulation files), and any 12 | associated documentation or information are expressly subject 13 | to the terms and conditions of the Altera Program License 14 | Subscription Agreement, Altera MegaCore Function License 15 | Agreement, or other applicable license agreement, including, 16 | without limitation, that your use is for the sole purpose of 17 | programming logic devices manufactured by Altera and sold by 18 | Altera or its authorized distributors. Please refer to the 19 | applicable agreement for further details. 20 | */ 21 | (header "symbol" (version "1.1")) 22 | (symbol 23 | (rect 0 0 80 40) 24 | (text "lpm_bustri2" (rect 7 1 86 17)(font "Arial" (font_size 10))) 25 | (text "inst" (rect 8 24 25 36)(font "Arial" )) 26 | (port 27 | (pt 40 40) 28 | (input) 29 | (text "enabledt" (rect 0 0 48 14)(font "Arial" (font_size 8))) 30 | (text "enabledt" (rect 40 -6 53 36)(font "Arial" (font_size 8))(invisible)) 31 | (line (pt 40 40)(pt 40 28)(line_width 1)) 32 | ) 33 | (port 34 | (pt 0 24) 35 | (input) 36 | (text "data[17..0]" (rect 0 0 60 14)(font "Arial" (font_size 8))) 37 | (text "data[17..0]" (rect -3 -27 10 24)(font "Arial" (font_size 8))(invisible)) 38 | (line (pt 0 24)(pt 32 24)(line_width 3)) 39 | ) 40 | (port 41 | (pt 80 24) 42 | (bidir) 43 | (text "tridata[17..0]" (rect 0 0 70 14)(font "Arial" (font_size 8))) 44 | (text "tridata[17..0]" (rect 84 -36 97 24)(font "Arial" (font_size 8))(invisible)) 45 | (line (pt 80 24)(pt 48 24)(line_width 3)) 46 | ) 47 | (drawing 48 | (text "18" (rect 61 25 71 37)(font "Arial" )) 49 | (text "18" (rect 13 25 23 37)(font "Arial" )) 50 | (line (pt 32 16)(pt 48 24)(line_width 1)) 51 | (line (pt 48 24)(pt 32 32)(line_width 1)) 52 | (line (pt 32 32)(pt 32 16)(line_width 1)) 53 | (line (pt 56 28)(pt 64 20)(line_width 1)) 54 | (line (pt 8 28)(pt 16 20)(line_width 1)) 55 | ) 56 | ) 57 | -------------------------------------------------------------------------------- /altip_orig/lpm_bustri2.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "LPM_BUSTRI" 2 | set_global_assignment -name IP_TOOL_VERSION "8.1" 3 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_bustri2.vhd"] 4 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri2.bsf"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri2.cmp"] 6 | -------------------------------------------------------------------------------- /altip_orig/lpm_bustri3.bsf: -------------------------------------------------------------------------------- 1 | /* 2 | WARNING: Do NOT edit the input and output ports in this file in a text 3 | editor if you plan to continue editing the block that represents it in 4 | the Block Editor! File corruption is VERY likely to occur. 5 | */ 6 | /* 7 | Copyright (C) 1991-2008 Altera Corporation 8 | Your use of Altera Corporation's design tools, logic functions 9 | and other software and tools, and its AMPP partner logic 10 | functions, and any output files from any of the foregoing 11 | (including device programming or simulation files), and any 12 | associated documentation or information are expressly subject 13 | to the terms and conditions of the Altera Program License 14 | Subscription Agreement, Altera MegaCore Function License 15 | Agreement, or other applicable license agreement, including, 16 | without limitation, that your use is for the sole purpose of 17 | programming logic devices manufactured by Altera and sold by 18 | Altera or its authorized distributors. Please refer to the 19 | applicable agreement for further details. 20 | */ 21 | (header "symbol" (version "1.1")) 22 | (symbol 23 | (rect 0 0 80 40) 24 | (text "lpm_bustri3" (rect 7 1 86 17)(font "Arial" (font_size 10))) 25 | (text "inst" (rect 8 24 25 36)(font "Arial" )) 26 | (port 27 | (pt 40 40) 28 | (input) 29 | (text "enabledt" (rect 0 0 48 14)(font "Arial" (font_size 8))) 30 | (text "enabledt" (rect 40 -6 53 36)(font "Arial" (font_size 8))(invisible)) 31 | (line (pt 40 40)(pt 40 28)(line_width 1)) 32 | ) 33 | (port 34 | (pt 0 24) 35 | (input) 36 | (text "data[5..0]" (rect 0 0 53 14)(font "Arial" (font_size 8))) 37 | (text "data[5..0]" (rect -3 -21 10 24)(font "Arial" (font_size 8))(invisible)) 38 | (line (pt 0 24)(pt 32 24)(line_width 3)) 39 | ) 40 | (port 41 | (pt 80 24) 42 | (bidir) 43 | (text "tridata[5..0]" (rect 0 0 63 14)(font "Arial" (font_size 8))) 44 | (text "tridata[5..0]" (rect 84 -30 97 24)(font "Arial" (font_size 8))(invisible)) 45 | (line (pt 80 24)(pt 48 24)(line_width 3)) 46 | ) 47 | (drawing 48 | (text "6" (rect 63 25 68 37)(font "Arial" )) 49 | (text "6" (rect 15 25 20 37)(font "Arial" )) 50 | (line (pt 32 16)(pt 48 24)(line_width 1)) 51 | (line (pt 48 24)(pt 32 32)(line_width 1)) 52 | (line (pt 32 32)(pt 32 16)(line_width 1)) 53 | (line (pt 58 28)(pt 66 20)(line_width 1)) 54 | (line (pt 10 28)(pt 18 20)(line_width 1)) 55 | ) 56 | ) 57 | -------------------------------------------------------------------------------- /altip_orig/lpm_bustri3.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "LPM_BUSTRI" 2 | set_global_assignment -name IP_TOOL_VERSION "8.1" 3 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_bustri3.vhd"] 4 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri3.bsf"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri3.cmp"] 6 | -------------------------------------------------------------------------------- /altip_orig/lpm_bustri4.bsf: -------------------------------------------------------------------------------- 1 | /* 2 | WARNING: Do NOT edit the input and output ports in this file in a text 3 | editor if you plan to continue editing the block that represents it in 4 | the Block Editor! File corruption is VERY likely to occur. 5 | */ 6 | /* 7 | Copyright (C) 1991-2008 Altera Corporation 8 | Your use of Altera Corporation's design tools, logic functions 9 | and other software and tools, and its AMPP partner logic 10 | functions, and any output files from any of the foregoing 11 | (including device programming or simulation files), and any 12 | associated documentation or information are expressly subject 13 | to the terms and conditions of the Altera Program License 14 | Subscription Agreement, Altera MegaCore Function License 15 | Agreement, or other applicable license agreement, including, 16 | without limitation, that your use is for the sole purpose of 17 | programming logic devices manufactured by Altera and sold by 18 | Altera or its authorized distributors. Please refer to the 19 | applicable agreement for further details. 20 | */ 21 | (header "symbol" (version "1.1")) 22 | (symbol 23 | (rect 0 0 80 40) 24 | (text "lpm_bustri4" (rect 7 1 86 17)(font "Arial" (font_size 10))) 25 | (text "inst" (rect 8 24 25 36)(font "Arial" )) 26 | (port 27 | (pt 40 40) 28 | (input) 29 | (text "enabledt" (rect 0 0 48 14)(font "Arial" (font_size 8))) 30 | (text "enabledt" (rect 40 -6 53 36)(font "Arial" (font_size 8))(invisible)) 31 | (line (pt 40 40)(pt 40 28)(line_width 1)) 32 | ) 33 | (port 34 | (pt 0 24) 35 | (input) 36 | (text "data[4..0]" (rect 0 0 53 14)(font "Arial" (font_size 8))) 37 | (text "data[4..0]" (rect -3 -21 10 24)(font "Arial" (font_size 8))(invisible)) 38 | (line (pt 0 24)(pt 32 24)(line_width 3)) 39 | ) 40 | (port 41 | (pt 80 24) 42 | (bidir) 43 | (text "tridata[4..0]" (rect 0 0 63 14)(font "Arial" (font_size 8))) 44 | (text "tridata[4..0]" (rect 84 -30 97 24)(font "Arial" (font_size 8))(invisible)) 45 | (line (pt 80 24)(pt 48 24)(line_width 3)) 46 | ) 47 | (drawing 48 | (text "5" (rect 63 25 68 37)(font "Arial" )) 49 | (text "5" (rect 15 25 20 37)(font "Arial" )) 50 | (line (pt 32 16)(pt 48 24)(line_width 1)) 51 | (line (pt 48 24)(pt 32 32)(line_width 1)) 52 | (line (pt 32 32)(pt 32 16)(line_width 1)) 53 | (line (pt 58 28)(pt 66 20)(line_width 1)) 54 | (line (pt 10 28)(pt 18 20)(line_width 1)) 55 | ) 56 | ) 57 | -------------------------------------------------------------------------------- /altip_orig/lpm_bustri4.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "LPM_BUSTRI" 2 | set_global_assignment -name IP_TOOL_VERSION "8.1" 3 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_bustri4.vhd"] 4 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri4.bsf"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri4.cmp"] 6 | -------------------------------------------------------------------------------- /altip_orig/lpm_bustri5.bsf: -------------------------------------------------------------------------------- 1 | /* 2 | WARNING: Do NOT edit the input and output ports in this file in a text 3 | editor if you plan to continue editing the block that represents it in 4 | the Block Editor! File corruption is VERY likely to occur. 5 | */ 6 | /* 7 | Copyright (C) 1991-2008 Altera Corporation 8 | Your use of Altera Corporation's design tools, logic functions 9 | and other software and tools, and its AMPP partner logic 10 | functions, and any output files from any of the foregoing 11 | (including device programming or simulation files), and any 12 | associated documentation or information are expressly subject 13 | to the terms and conditions of the Altera Program License 14 | Subscription Agreement, Altera MegaCore Function License 15 | Agreement, or other applicable license agreement, including, 16 | without limitation, that your use is for the sole purpose of 17 | programming logic devices manufactured by Altera and sold by 18 | Altera or its authorized distributors. Please refer to the 19 | applicable agreement for further details. 20 | */ 21 | (header "symbol" (version "1.1")) 22 | (symbol 23 | (rect 0 0 80 40) 24 | (text "lpm_bustri5" (rect 7 1 86 17)(font "Arial" (font_size 10))) 25 | (text "inst" (rect 8 24 25 36)(font "Arial" )) 26 | (port 27 | (pt 40 40) 28 | (input) 29 | (text "enabledt" (rect 0 0 48 14)(font "Arial" (font_size 8))) 30 | (text "enabledt" (rect 40 -6 53 36)(font "Arial" (font_size 8))(invisible)) 31 | (line (pt 40 40)(pt 40 28)(line_width 1)) 32 | ) 33 | (port 34 | (pt 0 24) 35 | (input) 36 | (text "data[7..0]" (rect 0 0 53 14)(font "Arial" (font_size 8))) 37 | (text "data[7..0]" (rect -3 -21 10 24)(font "Arial" (font_size 8))(invisible)) 38 | (line (pt 0 24)(pt 32 24)(line_width 3)) 39 | ) 40 | (port 41 | (pt 80 24) 42 | (bidir) 43 | (text "tridata[7..0]" (rect 0 0 63 14)(font "Arial" (font_size 8))) 44 | (text "tridata[7..0]" (rect 84 -30 97 24)(font "Arial" (font_size 8))(invisible)) 45 | (line (pt 80 24)(pt 48 24)(line_width 3)) 46 | ) 47 | (drawing 48 | (text "8" (rect 63 25 68 37)(font "Arial" )) 49 | (text "8" (rect 15 25 20 37)(font "Arial" )) 50 | (line (pt 32 16)(pt 48 24)(line_width 1)) 51 | (line (pt 48 24)(pt 32 32)(line_width 1)) 52 | (line (pt 32 32)(pt 32 16)(line_width 1)) 53 | (line (pt 58 28)(pt 66 20)(line_width 1)) 54 | (line (pt 10 28)(pt 18 20)(line_width 1)) 55 | ) 56 | ) 57 | -------------------------------------------------------------------------------- /altip_orig/lpm_bustri5.inc: -------------------------------------------------------------------------------- 1 | --Copyright (C) 1991-2008 Altera Corporation 2 | --Your use of Altera Corporation's design tools, logic functions 3 | --and other software and tools, and its AMPP partner logic 4 | --functions, and any output files from any of the foregoing 5 | --(including device programming or simulation files), and any 6 | --associated documentation or information are expressly subject 7 | --to the terms and conditions of the Altera Program License 8 | --Subscription Agreement, Altera MegaCore Function License 9 | --Agreement, or other applicable license agreement, including, 10 | --without limitation, that your use is for the sole purpose of 11 | --programming logic devices manufactured by Altera and sold by 12 | --Altera or its authorized distributors. Please refer to the 13 | --applicable agreement for further details. 14 | 15 | 16 | FUNCTION lpm_bustri5 17 | ( 18 | data[7..0], 19 | enabledt 20 | ) 21 | 22 | RETURNS ( 23 | tridata[7..0] 24 | ); 25 | -------------------------------------------------------------------------------- /altip_orig/lpm_bustri5.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "LPM_BUSTRI" 2 | set_global_assignment -name IP_TOOL_VERSION "8.1" 3 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_bustri5.vhd"] 4 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri5.bsf"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri5.inc"] 6 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri5.cmp"] 7 | -------------------------------------------------------------------------------- /altip_orig/lpm_bustri6.bsf: -------------------------------------------------------------------------------- 1 | /* 2 | WARNING: Do NOT edit the input and output ports in this file in a text 3 | editor if you plan to continue editing the block that represents it in 4 | the Block Editor! File corruption is VERY likely to occur. 5 | */ 6 | /* 7 | Copyright (C) 1991-2008 Altera Corporation 8 | Your use of Altera Corporation's design tools, logic functions 9 | and other software and tools, and its AMPP partner logic 10 | functions, and any output files from any of the foregoing 11 | (including device programming or simulation files), and any 12 | associated documentation or information are expressly subject 13 | to the terms and conditions of the Altera Program License 14 | Subscription Agreement, Altera MegaCore Function License 15 | Agreement, or other applicable license agreement, including, 16 | without limitation, that your use is for the sole purpose of 17 | programming logic devices manufactured by Altera and sold by 18 | Altera or its authorized distributors. Please refer to the 19 | applicable agreement for further details. 20 | */ 21 | (header "symbol" (version "1.1")) 22 | (symbol 23 | (rect 0 0 80 40) 24 | (text "lpm_bustri6" (rect 7 1 86 17)(font "Arial" (font_size 10))) 25 | (text "inst" (rect 8 24 25 36)(font "Arial" )) 26 | (port 27 | (pt 40 40) 28 | (input) 29 | (text "enabledt" (rect 0 0 48 14)(font "Arial" (font_size 8))) 30 | (text "enabledt" (rect 40 -6 53 36)(font "Arial" (font_size 8))(invisible)) 31 | (line (pt 40 40)(pt 40 28)(line_width 1)) 32 | ) 33 | (port 34 | (pt 0 24) 35 | (input) 36 | (text "data[23..0]" (rect 0 0 60 14)(font "Arial" (font_size 8))) 37 | (text "data[23..0]" (rect -3 -27 10 24)(font "Arial" (font_size 8))(invisible)) 38 | (line (pt 0 24)(pt 32 24)(line_width 3)) 39 | ) 40 | (port 41 | (pt 80 24) 42 | (bidir) 43 | (text "tridata[23..0]" (rect 0 0 70 14)(font "Arial" (font_size 8))) 44 | (text "tridata[23..0]" (rect 84 -36 97 24)(font "Arial" (font_size 8))(invisible)) 45 | (line (pt 80 24)(pt 48 24)(line_width 3)) 46 | ) 47 | (drawing 48 | (text "24" (rect 61 25 71 37)(font "Arial" )) 49 | (text "24" (rect 13 25 23 37)(font "Arial" )) 50 | (line (pt 32 16)(pt 48 24)(line_width 1)) 51 | (line (pt 48 24)(pt 32 32)(line_width 1)) 52 | (line (pt 32 32)(pt 32 16)(line_width 1)) 53 | (line (pt 56 28)(pt 64 20)(line_width 1)) 54 | (line (pt 8 28)(pt 16 20)(line_width 1)) 55 | ) 56 | ) 57 | -------------------------------------------------------------------------------- /altip_orig/lpm_bustri6.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "LPM_BUSTRI" 2 | set_global_assignment -name IP_TOOL_VERSION "8.1" 3 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_bustri6.vhd"] 4 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri6.bsf"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri6.cmp"] 6 | -------------------------------------------------------------------------------- /altip_orig/lpm_bustri7.bsf: -------------------------------------------------------------------------------- 1 | /* 2 | WARNING: Do NOT edit the input and output ports in this file in a text 3 | editor if you plan to continue editing the block that represents it in 4 | the Block Editor! File corruption is VERY likely to occur. 5 | */ 6 | /* 7 | Copyright (C) 1991-2008 Altera Corporation 8 | Your use of Altera Corporation's design tools, logic functions 9 | and other software and tools, and its AMPP partner logic 10 | functions, and any output files from any of the foregoing 11 | (including device programming or simulation files), and any 12 | associated documentation or information are expressly subject 13 | to the terms and conditions of the Altera Program License 14 | Subscription Agreement, Altera MegaCore Function License 15 | Agreement, or other applicable license agreement, including, 16 | without limitation, that your use is for the sole purpose of 17 | programming logic devices manufactured by Altera and sold by 18 | Altera or its authorized distributors. Please refer to the 19 | applicable agreement for further details. 20 | */ 21 | (header "symbol" (version "1.1")) 22 | (symbol 23 | (rect 0 0 80 40) 24 | (text "lpm_bustri7" (rect 7 1 86 17)(font "Arial" (font_size 10))) 25 | (text "inst" (rect 8 24 25 36)(font "Arial" )) 26 | (port 27 | (pt 40 40) 28 | (input) 29 | (text "enabledt" (rect 0 0 48 14)(font "Arial" (font_size 8))) 30 | (text "enabledt" (rect 40 -6 53 36)(font "Arial" (font_size 8))(invisible)) 31 | (line (pt 40 40)(pt 40 28)(line_width 1)) 32 | ) 33 | (port 34 | (pt 0 24) 35 | (input) 36 | (text "data[3..0]" (rect 0 0 53 14)(font "Arial" (font_size 8))) 37 | (text "data[3..0]" (rect -3 -21 10 24)(font "Arial" (font_size 8))(invisible)) 38 | (line (pt 0 24)(pt 32 24)(line_width 3)) 39 | ) 40 | (port 41 | (pt 80 24) 42 | (bidir) 43 | (text "tridata[3..0]" (rect 0 0 63 14)(font "Arial" (font_size 8))) 44 | (text "tridata[3..0]" (rect 84 -30 97 24)(font "Arial" (font_size 8))(invisible)) 45 | (line (pt 80 24)(pt 48 24)(line_width 3)) 46 | ) 47 | (drawing 48 | (text "4" (rect 63 25 68 37)(font "Arial" )) 49 | (text "4" (rect 15 25 20 37)(font "Arial" )) 50 | (line (pt 32 16)(pt 48 24)(line_width 1)) 51 | (line (pt 48 24)(pt 32 32)(line_width 1)) 52 | (line (pt 32 32)(pt 32 16)(line_width 1)) 53 | (line (pt 58 28)(pt 66 20)(line_width 1)) 54 | (line (pt 10 28)(pt 18 20)(line_width 1)) 55 | ) 56 | ) 57 | -------------------------------------------------------------------------------- /altip_orig/lpm_bustri7.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "LPM_BUSTRI" 2 | set_global_assignment -name IP_TOOL_VERSION "8.1" 3 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_bustri7.vhd"] 4 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri7.bsf"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri7.cmp"] 6 | -------------------------------------------------------------------------------- /altip_orig/lpm_bustri_BYT.bsf: -------------------------------------------------------------------------------- 1 | /* 2 | WARNING: Do NOT edit the input and output ports in this file in a text 3 | editor if you plan to continue editing the block that represents it in 4 | the Block Editor! File corruption is VERY likely to occur. 5 | */ 6 | /* 7 | Copyright (C) 1991-2008 Altera Corporation 8 | Your use of Altera Corporation's design tools, logic functions 9 | and other software and tools, and its AMPP partner logic 10 | functions, and any output files from any of the foregoing 11 | (including device programming or simulation files), and any 12 | associated documentation or information are expressly subject 13 | to the terms and conditions of the Altera Program License 14 | Subscription Agreement, Altera MegaCore Function License 15 | Agreement, or other applicable license agreement, including, 16 | without limitation, that your use is for the sole purpose of 17 | programming logic devices manufactured by Altera and sold by 18 | Altera or its authorized distributors. Please refer to the 19 | applicable agreement for further details. 20 | */ 21 | (header "symbol" (version "1.1")) 22 | (symbol 23 | (rect 0 0 96 40) 24 | (text "lpm_bustri_BYT" (rect 2 1 110 17)(font "Arial" (font_size 10))) 25 | (text "inst" (rect 8 24 25 36)(font "Arial" )) 26 | (port 27 | (pt 40 40) 28 | (input) 29 | (text "enabledt" (rect 0 0 48 14)(font "Arial" (font_size 8))) 30 | (text "enabledt" (rect 40 -6 53 36)(font "Arial" (font_size 8))(invisible)) 31 | (line (pt 40 40)(pt 40 28)(line_width 1)) 32 | ) 33 | (port 34 | (pt 0 24) 35 | (input) 36 | (text "data[7..0]" (rect 0 0 53 14)(font "Arial" (font_size 8))) 37 | (text "data[7..0]" (rect -3 -21 10 24)(font "Arial" (font_size 8))(invisible)) 38 | (line (pt 0 24)(pt 32 24)(line_width 3)) 39 | ) 40 | (port 41 | (pt 96 24) 42 | (bidir) 43 | (text "tridata[7..0]" (rect 0 0 63 14)(font "Arial" (font_size 8))) 44 | (text "tridata[7..0]" (rect 100 -30 113 24)(font "Arial" (font_size 8))(invisible)) 45 | (line (pt 96 24)(pt 48 24)(line_width 3)) 46 | ) 47 | (drawing 48 | (text "8" (rect 71 25 76 37)(font "Arial" )) 49 | (text "8" (rect 15 25 20 37)(font "Arial" )) 50 | (line (pt 32 16)(pt 48 24)(line_width 1)) 51 | (line (pt 48 24)(pt 32 32)(line_width 1)) 52 | (line (pt 32 32)(pt 32 16)(line_width 1)) 53 | (line (pt 66 28)(pt 74 20)(line_width 1)) 54 | (line (pt 10 28)(pt 18 20)(line_width 1)) 55 | ) 56 | ) 57 | -------------------------------------------------------------------------------- /altip_orig/lpm_bustri_BYT.inc: -------------------------------------------------------------------------------- 1 | --Copyright (C) 1991-2008 Altera Corporation 2 | --Your use of Altera Corporation's design tools, logic functions 3 | --and other software and tools, and its AMPP partner logic 4 | --functions, and any output files from any of the foregoing 5 | --(including device programming or simulation files), and any 6 | --associated documentation or information are expressly subject 7 | --to the terms and conditions of the Altera Program License 8 | --Subscription Agreement, Altera MegaCore Function License 9 | --Agreement, or other applicable license agreement, including, 10 | --without limitation, that your use is for the sole purpose of 11 | --programming logic devices manufactured by Altera and sold by 12 | --Altera or its authorized distributors. Please refer to the 13 | --applicable agreement for further details. 14 | 15 | 16 | FUNCTION lpm_bustri_BYT 17 | ( 18 | data[7..0], 19 | enabledt 20 | ) 21 | 22 | RETURNS ( 23 | tridata[7..0] 24 | ); 25 | -------------------------------------------------------------------------------- /altip_orig/lpm_bustri_BYT.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "LPM_BUSTRI" 2 | set_global_assignment -name IP_TOOL_VERSION "8.1" 3 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_bustri_BYT.vhd"] 4 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri_BYT.bsf"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri_BYT.inc"] 6 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri_BYT.cmp"] 7 | -------------------------------------------------------------------------------- /altip_orig/lpm_bustri_LONG.bsf: -------------------------------------------------------------------------------- 1 | /* 2 | WARNING: Do NOT edit the input and output ports in this file in a text 3 | editor if you plan to continue editing the block that represents it in 4 | the Block Editor! File corruption is VERY likely to occur. 5 | */ 6 | /* 7 | Copyright (C) 1991-2008 Altera Corporation 8 | Your use of Altera Corporation's design tools, logic functions 9 | and other software and tools, and its AMPP partner logic 10 | functions, and any output files from any of the foregoing 11 | (including device programming or simulation files), and any 12 | associated documentation or information are expressly subject 13 | to the terms and conditions of the Altera Program License 14 | Subscription Agreement, Altera MegaCore Function License 15 | Agreement, or other applicable license agreement, including, 16 | without limitation, that your use is for the sole purpose of 17 | programming logic devices manufactured by Altera and sold by 18 | Altera or its authorized distributors. Please refer to the 19 | applicable agreement for further details. 20 | */ 21 | (header "symbol" (version "1.1")) 22 | (symbol 23 | (rect 0 0 112 40) 24 | (text "lpm_bustri_LONG" (rect 5 1 126 17)(font "Arial" (font_size 10))) 25 | (text "inst" (rect 8 24 25 36)(font "Arial" )) 26 | (port 27 | (pt 40 40) 28 | (input) 29 | (text "enabledt" (rect 0 0 48 14)(font "Arial" (font_size 8))) 30 | (text "enabledt" (rect 40 -6 53 36)(font "Arial" (font_size 8))(invisible)) 31 | (line (pt 40 40)(pt 40 28)(line_width 1)) 32 | ) 33 | (port 34 | (pt 0 24) 35 | (input) 36 | (text "data[31..0]" (rect 0 0 60 14)(font "Arial" (font_size 8))) 37 | (text "data[31..0]" (rect -3 -27 10 24)(font "Arial" (font_size 8))(invisible)) 38 | (line (pt 0 24)(pt 32 24)(line_width 3)) 39 | ) 40 | (port 41 | (pt 112 24) 42 | (bidir) 43 | (text "tridata[31..0]" (rect 0 0 70 14)(font "Arial" (font_size 8))) 44 | (text "tridata[31..0]" (rect 116 -36 129 24)(font "Arial" (font_size 8))(invisible)) 45 | (line (pt 112 24)(pt 48 24)(line_width 3)) 46 | ) 47 | (drawing 48 | (text "32" (rect 77 25 87 37)(font "Arial" )) 49 | (text "32" (rect 13 25 23 37)(font "Arial" )) 50 | (line (pt 32 16)(pt 48 24)(line_width 1)) 51 | (line (pt 48 24)(pt 32 32)(line_width 1)) 52 | (line (pt 32 32)(pt 32 16)(line_width 1)) 53 | (line (pt 72 28)(pt 80 20)(line_width 1)) 54 | (line (pt 8 28)(pt 16 20)(line_width 1)) 55 | ) 56 | ) 57 | -------------------------------------------------------------------------------- /altip_orig/lpm_bustri_LONG.inc: -------------------------------------------------------------------------------- 1 | --Copyright (C) 1991-2008 Altera Corporation 2 | --Your use of Altera Corporation's design tools, logic functions 3 | --and other software and tools, and its AMPP partner logic 4 | --functions, and any output files from any of the foregoing 5 | --(including device programming or simulation files), and any 6 | --associated documentation or information are expressly subject 7 | --to the terms and conditions of the Altera Program License 8 | --Subscription Agreement, Altera MegaCore Function License 9 | --Agreement, or other applicable license agreement, including, 10 | --without limitation, that your use is for the sole purpose of 11 | --programming logic devices manufactured by Altera and sold by 12 | --Altera or its authorized distributors. Please refer to the 13 | --applicable agreement for further details. 14 | 15 | 16 | FUNCTION lpm_bustri_LONG 17 | ( 18 | data[31..0], 19 | enabledt 20 | ) 21 | 22 | RETURNS ( 23 | tridata[31..0] 24 | ); 25 | -------------------------------------------------------------------------------- /altip_orig/lpm_bustri_LONG.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "LPM_BUSTRI" 2 | set_global_assignment -name IP_TOOL_VERSION "8.1" 3 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_bustri_LONG.vhd"] 4 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri_LONG.bsf"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri_LONG.inc"] 6 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri_LONG.cmp"] 7 | -------------------------------------------------------------------------------- /altip_orig/lpm_bustri_LONG.tdf: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------- 2 | -- 3 | -- LPM_BUSTRI Parameterized Megafunction 4 | -- 5 | -- Copyright (C) 1991-2013 Altera Corporation 6 | -- Your use of Altera Corporation's design tools, logic functions 7 | -- and other software and tools, and its AMPP partner logic 8 | -- functions, and any output files from any of the foregoing 9 | -- (including device programming or simulation files), and any 10 | -- associated documentation or information are expressly subject 11 | -- to the terms and conditions of the Altera Program License 12 | -- Subscription Agreement, Altera MegaCore Function License 13 | -- Agreement, or other applicable license agreement, including, 14 | -- without limitation, that your use is for the sole purpose of 15 | -- programming logic devices manufactured by Altera and sold by 16 | -- Altera or its authorized distributors. Please refer to the 17 | -- applicable agreement for further details. 18 | -- 19 | -- Quartus II 13.1.0 Build 162 10/23/2013 20 | -- 21 | -- Version 2.0 22 | -- 23 | -------------------------------------------------------------------- 24 | 25 | SUBDESIGN lpm_bustri_LONG 26 | ( 27 | tridata[32-1..0] : BIDIR; 28 | data[32-1..0] : INPUT = VCC; 29 | enabletr : INPUT = VCC; 30 | enabledt : INPUT = VCC; 31 | result[32-1..0] : OUTPUT; 32 | ) 33 | 34 | VARIABLE 35 | % Are the enable inputs used? % 36 | IF (USED(enabledt)) GENERATE 37 | dout[32-1..0] : TRI; 38 | END GENERATE; 39 | IF (USED(enabletr)) GENERATE 40 | din[32-1..0] : TRI; 41 | END GENERATE; 42 | 43 | BEGIN 44 | 45 | ASSERT (32 > 0) 46 | REPORT "Value of 32 parameter value must be greater than 0" 47 | SEVERITY ERROR 48 | HELP_ID LPM_BUSTRI_WIDTH; 49 | 50 | ASSERT (USED(enabledt) & USED(data)) 51 | REPORT "lpm_bustri function requires data[] port -- Altera recommends using the TRI primitive instead" 52 | SEVERITY ERROR 53 | HELP_ID LPM_BUSTRI_DATA; 54 | 55 | % Connect buffers if they are used % 56 | IF (USED(enabledt)) GENERATE 57 | dout[].oe = enabledt; 58 | dout[] = data[]; 59 | tridata[] = dout[]; 60 | END GENERATE; 61 | 62 | IF (USED(enabletr)) GENERATE 63 | din[].oe = enabletr; 64 | din[] = tridata[]; 65 | result[] = din[]; 66 | ELSE GENERATE 67 | result[] = tridata[]; 68 | END GENERATE; 69 | IF !USED(result) GENERATE 70 | result[] = GND; 71 | END GENERATE; 72 | END; 73 | -------------------------------------------------------------------------------- /altip_orig/lpm_bustri_WORD.bsf: -------------------------------------------------------------------------------- 1 | /* 2 | WARNING: Do NOT edit the input and output ports in this file in a text 3 | editor if you plan to continue editing the block that represents it in 4 | the Block Editor! File corruption is VERY likely to occur. 5 | */ 6 | /* 7 | Copyright (C) 1991-2008 Altera Corporation 8 | Your use of Altera Corporation's design tools, logic functions 9 | and other software and tools, and its AMPP partner logic 10 | functions, and any output files from any of the foregoing 11 | (including device programming or simulation files), and any 12 | associated documentation or information are expressly subject 13 | to the terms and conditions of the Altera Program License 14 | Subscription Agreement, Altera MegaCore Function License 15 | Agreement, or other applicable license agreement, including, 16 | without limitation, that your use is for the sole purpose of 17 | programming logic devices manufactured by Altera and sold by 18 | Altera or its authorized distributors. Please refer to the 19 | applicable agreement for further details. 20 | */ 21 | (header "symbol" (version "1.1")) 22 | (symbol 23 | (rect 0 0 112 40) 24 | (text "lpm_bustri_WORD" (rect 2 1 129 17)(font "Arial" (font_size 10))) 25 | (text "inst" (rect 8 24 25 36)(font "Arial" )) 26 | (port 27 | (pt 40 40) 28 | (input) 29 | (text "enabledt" (rect 0 0 48 14)(font "Arial" (font_size 8))) 30 | (text "enabledt" (rect 40 -6 53 36)(font "Arial" (font_size 8))(invisible)) 31 | (line (pt 40 40)(pt 40 28)(line_width 1)) 32 | ) 33 | (port 34 | (pt 0 24) 35 | (input) 36 | (text "data[15..0]" (rect 0 0 60 14)(font "Arial" (font_size 8))) 37 | (text "data[15..0]" (rect -3 -27 10 24)(font "Arial" (font_size 8))(invisible)) 38 | (line (pt 0 24)(pt 32 24)(line_width 3)) 39 | ) 40 | (port 41 | (pt 112 24) 42 | (bidir) 43 | (text "tridata[15..0]" (rect 0 0 70 14)(font "Arial" (font_size 8))) 44 | (text "tridata[15..0]" (rect 116 -36 129 24)(font "Arial" (font_size 8))(invisible)) 45 | (line (pt 112 24)(pt 48 24)(line_width 3)) 46 | ) 47 | (drawing 48 | (text "16" (rect 77 25 87 37)(font "Arial" )) 49 | (text "16" (rect 13 25 23 37)(font "Arial" )) 50 | (line (pt 32 16)(pt 48 24)(line_width 1)) 51 | (line (pt 48 24)(pt 32 32)(line_width 1)) 52 | (line (pt 32 32)(pt 32 16)(line_width 1)) 53 | (line (pt 72 28)(pt 80 20)(line_width 1)) 54 | (line (pt 8 28)(pt 16 20)(line_width 1)) 55 | ) 56 | ) 57 | -------------------------------------------------------------------------------- /altip_orig/lpm_bustri_WORD.inc: -------------------------------------------------------------------------------- 1 | --Copyright (C) 1991-2008 Altera Corporation 2 | --Your use of Altera Corporation's design tools, logic functions 3 | --and other software and tools, and its AMPP partner logic 4 | --functions, and any output files from any of the foregoing 5 | --(including device programming or simulation files), and any 6 | --associated documentation or information are expressly subject 7 | --to the terms and conditions of the Altera Program License 8 | --Subscription Agreement, Altera MegaCore Function License 9 | --Agreement, or other applicable license agreement, including, 10 | --without limitation, that your use is for the sole purpose of 11 | --programming logic devices manufactured by Altera and sold by 12 | --Altera or its authorized distributors. Please refer to the 13 | --applicable agreement for further details. 14 | 15 | 16 | FUNCTION lpm_bustri_WORD 17 | ( 18 | data[15..0], 19 | enabledt 20 | ) 21 | 22 | RETURNS ( 23 | tridata[15..0] 24 | ); 25 | -------------------------------------------------------------------------------- /altip_orig/lpm_bustri_WORD.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "LPM_BUSTRI" 2 | set_global_assignment -name IP_TOOL_VERSION "8.1" 3 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_bustri_WORD.vhd"] 4 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri_WORD.bsf"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri_WORD.inc"] 6 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri_WORD.cmp"] 7 | -------------------------------------------------------------------------------- /altip_orig/lpm_compare1.bsf: -------------------------------------------------------------------------------- 1 | /* 2 | WARNING: Do NOT edit the input and output ports in this file in a text 3 | editor if you plan to continue editing the block that represents it in 4 | the Block Editor! File corruption is VERY likely to occur. 5 | */ 6 | /* 7 | Copyright (C) 1991-2008 Altera Corporation 8 | Your use of Altera Corporation's design tools, logic functions 9 | and other software and tools, and its AMPP partner logic 10 | functions, and any output files from any of the foregoing 11 | (including device programming or simulation files), and any 12 | associated documentation or information are expressly subject 13 | to the terms and conditions of the Altera Program License 14 | Subscription Agreement, Altera MegaCore Function License 15 | Agreement, or other applicable license agreement, including, 16 | without limitation, that your use is for the sole purpose of 17 | programming logic devices manufactured by Altera and sold by 18 | Altera or its authorized distributors. Please refer to the 19 | applicable agreement for further details. 20 | */ 21 | (header "symbol" (version "1.1")) 22 | (symbol 23 | (rect 0 0 128 96) 24 | (text "lpm_compare1" (rect 22 1 122 17)(font "Arial" (font_size 10))) 25 | (text "inst" (rect 8 80 25 92)(font "Arial" )) 26 | (port 27 | (pt 0 48) 28 | (input) 29 | (text "dataa[10..0]" (rect 0 0 67 14)(font "Arial" (font_size 8))) 30 | (text "dataa[10..0]" (rect 20 42 77 55)(font "Arial" (font_size 8))) 31 | (line (pt 0 48)(pt 16 48)(line_width 3)) 32 | ) 33 | (port 34 | (pt 0 64) 35 | (input) 36 | (text "datab[10..0]" (rect 0 0 67 14)(font "Arial" (font_size 8))) 37 | (text "datab[10..0]" (rect 20 58 77 71)(font "Arial" (font_size 8))) 38 | (line (pt 0 64)(pt 16 64)(line_width 3)) 39 | ) 40 | (port 41 | (pt 128 56) 42 | (output) 43 | (text "agb" (rect 0 0 21 14)(font "Arial" (font_size 8))) 44 | (text "agb" (rect 91 50 109 63)(font "Arial" (font_size 8))) 45 | (line (pt 128 56)(pt 112 56)(line_width 1)) 46 | ) 47 | (drawing 48 | (text "unsigned compare" (rect 36 17 112 29)(font "Arial" )) 49 | (line (pt 16 16)(pt 112 16)(line_width 1)) 50 | (line (pt 112 16)(pt 112 80)(line_width 1)) 51 | (line (pt 112 80)(pt 16 80)(line_width 1)) 52 | (line (pt 16 80)(pt 16 16)(line_width 1)) 53 | ) 54 | ) 55 | -------------------------------------------------------------------------------- /altip_orig/lpm_compare1.inc: -------------------------------------------------------------------------------- 1 | --Copyright (C) 1991-2008 Altera Corporation 2 | --Your use of Altera Corporation's design tools, logic functions 3 | --and other software and tools, and its AMPP partner logic 4 | --functions, and any output files from any of the foregoing 5 | --(including device programming or simulation files), and any 6 | --associated documentation or information are expressly subject 7 | --to the terms and conditions of the Altera Program License 8 | --Subscription Agreement, Altera MegaCore Function License 9 | --Agreement, or other applicable license agreement, including, 10 | --without limitation, that your use is for the sole purpose of 11 | --programming logic devices manufactured by Altera and sold by 12 | --Altera or its authorized distributors. Please refer to the 13 | --applicable agreement for further details. 14 | 15 | 16 | FUNCTION lpm_compare1 17 | ( 18 | dataa[10..0], 19 | datab[10..0] 20 | ) 21 | 22 | RETURNS ( 23 | AgB 24 | ); 25 | -------------------------------------------------------------------------------- /altip_orig/lpm_compare1.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "LPM_COMPARE" 2 | set_global_assignment -name IP_TOOL_VERSION "8.1" 3 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_compare1.vhd"] 4 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_compare1.bsf"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_compare1.inc"] 6 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_compare1.cmp"] 7 | -------------------------------------------------------------------------------- /altip_orig/lpm_constant0.bsf: -------------------------------------------------------------------------------- 1 | /* 2 | WARNING: Do NOT edit the input and output ports in this file in a text 3 | editor if you plan to continue editing the block that represents it in 4 | the Block Editor! File corruption is VERY likely to occur. 5 | */ 6 | /* 7 | Copyright (C) 1991-2008 Altera Corporation 8 | Your use of Altera Corporation's design tools, logic functions 9 | and other software and tools, and its AMPP partner logic 10 | functions, and any output files from any of the foregoing 11 | (including device programming or simulation files), and any 12 | associated documentation or information are expressly subject 13 | to the terms and conditions of the Altera Program License 14 | Subscription Agreement, Altera MegaCore Function License 15 | Agreement, or other applicable license agreement, including, 16 | without limitation, that your use is for the sole purpose of 17 | programming logic devices manufactured by Altera and sold by 18 | Altera or its authorized distributors. Please refer to the 19 | applicable agreement for further details. 20 | */ 21 | (header "symbol" (version "1.1")) 22 | (symbol 23 | (rect 0 0 96 48) 24 | (text "lpm_constant0" (rect 6 1 106 17)(font "Arial" (font_size 10))) 25 | (text "inst" (rect 8 32 25 44)(font "Arial" )) 26 | (port 27 | (pt 96 24) 28 | (output) 29 | (text "result[4..0]" (rect 0 0 60 14)(font "Arial" (font_size 8))) 30 | (text "result[4..0]" (rect 93 -25 106 24)(font "Arial" (font_size 8))(invisible)) 31 | (line (pt 96 24)(pt 80 24)(line_width 3)) 32 | ) 33 | (drawing 34 | (text "0" (rect 75 18 80 30)(font "Arial" )) 35 | (text "5" (rect 87 25 92 37)(font "Arial" )) 36 | (line (pt 16 16)(pt 80 16)(line_width 1)) 37 | (line (pt 80 16)(pt 80 32)(line_width 1)) 38 | (line (pt 80 32)(pt 16 32)(line_width 1)) 39 | (line (pt 16 32)(pt 16 16)(line_width 1)) 40 | (line (pt 82 28)(pt 90 20)(line_width 1)) 41 | ) 42 | ) 43 | -------------------------------------------------------------------------------- /altip_orig/lpm_constant0.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "LPM_CONSTANT" 2 | set_global_assignment -name IP_TOOL_VERSION "8.1" 3 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_constant0.vhd"] 4 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_constant0.bsf"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_constant0.cmp"] 6 | -------------------------------------------------------------------------------- /altip_orig/lpm_constant1.bsf: -------------------------------------------------------------------------------- 1 | /* 2 | WARNING: Do NOT edit the input and output ports in this file in a text 3 | editor if you plan to continue editing the block that represents it in 4 | the Block Editor! File corruption is VERY likely to occur. 5 | */ 6 | /* 7 | Copyright (C) 1991-2008 Altera Corporation 8 | Your use of Altera Corporation's design tools, logic functions 9 | and other software and tools, and its AMPP partner logic 10 | functions, and any output files from any of the foregoing 11 | (including device programming or simulation files), and any 12 | associated documentation or information are expressly subject 13 | to the terms and conditions of the Altera Program License 14 | Subscription Agreement, Altera MegaCore Function License 15 | Agreement, or other applicable license agreement, including, 16 | without limitation, that your use is for the sole purpose of 17 | programming logic devices manufactured by Altera and sold by 18 | Altera or its authorized distributors. Please refer to the 19 | applicable agreement for further details. 20 | */ 21 | (header "symbol" (version "1.1")) 22 | (symbol 23 | (rect 0 0 96 48) 24 | (text "lpm_constant1" (rect 6 1 106 17)(font "Arial" (font_size 10))) 25 | (text "inst" (rect 8 32 25 44)(font "Arial" )) 26 | (port 27 | (pt 96 24) 28 | (output) 29 | (text "result[1..0]" (rect 0 0 60 14)(font "Arial" (font_size 8))) 30 | (text "result[1..0]" (rect 93 -25 106 24)(font "Arial" (font_size 8))(invisible)) 31 | (line (pt 96 24)(pt 80 24)(line_width 3)) 32 | ) 33 | (drawing 34 | (text "0" (rect 75 18 80 30)(font "Arial" )) 35 | (text "2" (rect 87 25 92 37)(font "Arial" )) 36 | (line (pt 16 16)(pt 80 16)(line_width 1)) 37 | (line (pt 80 16)(pt 80 32)(line_width 1)) 38 | (line (pt 80 32)(pt 16 32)(line_width 1)) 39 | (line (pt 16 32)(pt 16 16)(line_width 1)) 40 | (line (pt 82 28)(pt 90 20)(line_width 1)) 41 | ) 42 | ) 43 | -------------------------------------------------------------------------------- /altip_orig/lpm_constant1.inc: -------------------------------------------------------------------------------- 1 | --Copyright (C) 1991-2008 Altera Corporation 2 | --Your use of Altera Corporation's design tools, logic functions 3 | --and other software and tools, and its AMPP partner logic 4 | --functions, and any output files from any of the foregoing 5 | --(including device programming or simulation files), and any 6 | --associated documentation or information are expressly subject 7 | --to the terms and conditions of the Altera Program License 8 | --Subscription Agreement, Altera MegaCore Function License 9 | --Agreement, or other applicable license agreement, including, 10 | --without limitation, that your use is for the sole purpose of 11 | --programming logic devices manufactured by Altera and sold by 12 | --Altera or its authorized distributors. Please refer to the 13 | --applicable agreement for further details. 14 | 15 | 16 | FUNCTION lpm_constant1 17 | ( 18 | 19 | ) 20 | 21 | RETURNS ( 22 | result[1..0] 23 | ); 24 | -------------------------------------------------------------------------------- /altip_orig/lpm_constant1.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "LPM_CONSTANT" 2 | set_global_assignment -name IP_TOOL_VERSION "8.1" 3 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_constant1.vhd"] 4 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_constant1.bsf"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_constant1.inc"] 6 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_constant1.cmp"] 7 | -------------------------------------------------------------------------------- /altip_orig/lpm_constant2.bsf: -------------------------------------------------------------------------------- 1 | /* 2 | WARNING: Do NOT edit the input and output ports in this file in a text 3 | editor if you plan to continue editing the block that represents it in 4 | the Block Editor! File corruption is VERY likely to occur. 5 | */ 6 | /* 7 | Copyright (C) 1991-2008 Altera Corporation 8 | Your use of Altera Corporation's design tools, logic functions 9 | and other software and tools, and its AMPP partner logic 10 | functions, and any output files from any of the foregoing 11 | (including device programming or simulation files), and any 12 | associated documentation or information are expressly subject 13 | to the terms and conditions of the Altera Program License 14 | Subscription Agreement, Altera MegaCore Function License 15 | Agreement, or other applicable license agreement, including, 16 | without limitation, that your use is for the sole purpose of 17 | programming logic devices manufactured by Altera and sold by 18 | Altera or its authorized distributors. Please refer to the 19 | applicable agreement for further details. 20 | */ 21 | (header "symbol" (version "1.1")) 22 | (symbol 23 | (rect 0 0 96 48) 24 | (text "lpm_constant2" (rect 6 1 106 17)(font "Arial" (font_size 10))) 25 | (text "inst" (rect 8 32 25 44)(font "Arial" )) 26 | (port 27 | (pt 96 24) 28 | (output) 29 | (text "result[7..0]" (rect 0 0 60 14)(font "Arial" (font_size 8))) 30 | (text "result[7..0]" (rect 93 -25 106 24)(font "Arial" (font_size 8))(invisible)) 31 | (line (pt 96 24)(pt 80 24)(line_width 3)) 32 | ) 33 | (drawing 34 | (text "0" (rect 75 18 80 30)(font "Arial" )) 35 | (text "8" (rect 87 25 92 37)(font "Arial" )) 36 | (line (pt 16 16)(pt 80 16)(line_width 1)) 37 | (line (pt 80 16)(pt 80 32)(line_width 1)) 38 | (line (pt 80 32)(pt 16 32)(line_width 1)) 39 | (line (pt 16 32)(pt 16 16)(line_width 1)) 40 | (line (pt 82 28)(pt 90 20)(line_width 1)) 41 | ) 42 | ) 43 | -------------------------------------------------------------------------------- /altip_orig/lpm_constant2.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "LPM_CONSTANT" 2 | set_global_assignment -name IP_TOOL_VERSION "8.1" 3 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_constant2.vhd"] 4 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_constant2.bsf"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_constant2.cmp"] 6 | -------------------------------------------------------------------------------- /altip_orig/lpm_constant3.bsf: -------------------------------------------------------------------------------- 1 | /* 2 | WARNING: Do NOT edit the input and output ports in this file in a text 3 | editor if you plan to continue editing the block that represents it in 4 | the Block Editor! File corruption is VERY likely to occur. 5 | */ 6 | /* 7 | Copyright (C) 1991-2008 Altera Corporation 8 | Your use of Altera Corporation's design tools, logic functions 9 | and other software and tools, and its AMPP partner logic 10 | functions, and any output files from any of the foregoing 11 | (including device programming or simulation files), and any 12 | associated documentation or information are expressly subject 13 | to the terms and conditions of the Altera Program License 14 | Subscription Agreement, Altera MegaCore Function License 15 | Agreement, or other applicable license agreement, including, 16 | without limitation, that your use is for the sole purpose of 17 | programming logic devices manufactured by Altera and sold by 18 | Altera or its authorized distributors. Please refer to the 19 | applicable agreement for further details. 20 | */ 21 | (header "symbol" (version "1.1")) 22 | (symbol 23 | (rect 0 0 96 48) 24 | (text "lpm_constant3" (rect 6 1 106 17)(font "Arial" (font_size 10))) 25 | (text "inst" (rect 8 32 25 44)(font "Arial" )) 26 | (port 27 | (pt 96 24) 28 | (output) 29 | (text "result[6..0]" (rect 0 0 60 14)(font "Arial" (font_size 8))) 30 | (text "result[6..0]" (rect 93 -25 106 24)(font "Arial" (font_size 8))(invisible)) 31 | (line (pt 96 24)(pt 80 24)(line_width 3)) 32 | ) 33 | (drawing 34 | (text "0" (rect 75 18 80 30)(font "Arial" )) 35 | (text "7" (rect 87 25 92 37)(font "Arial" )) 36 | (line (pt 16 16)(pt 80 16)(line_width 1)) 37 | (line (pt 80 16)(pt 80 32)(line_width 1)) 38 | (line (pt 80 32)(pt 16 32)(line_width 1)) 39 | (line (pt 16 32)(pt 16 16)(line_width 1)) 40 | (line (pt 82 28)(pt 90 20)(line_width 1)) 41 | ) 42 | ) 43 | -------------------------------------------------------------------------------- /altip_orig/lpm_constant3.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "LPM_CONSTANT" 2 | set_global_assignment -name IP_TOOL_VERSION "8.1" 3 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_constant3.vhd"] 4 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_constant3.bsf"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_constant3.cmp"] 6 | -------------------------------------------------------------------------------- /altip_orig/lpm_constant4.bsf: -------------------------------------------------------------------------------- 1 | /* 2 | WARNING: Do NOT edit the input and output ports in this file in a text 3 | editor if you plan to continue editing the block that represents it in 4 | the Block Editor! File corruption is VERY likely to occur. 5 | */ 6 | /* 7 | Copyright (C) 1991-2008 Altera Corporation 8 | Your use of Altera Corporation's design tools, logic functions 9 | and other software and tools, and its AMPP partner logic 10 | functions, and any output files from any of the foregoing 11 | (including device programming or simulation files), and any 12 | associated documentation or information are expressly subject 13 | to the terms and conditions of the Altera Program License 14 | Subscription Agreement, Altera MegaCore Function License 15 | Agreement, or other applicable license agreement, including, 16 | without limitation, that your use is for the sole purpose of 17 | programming logic devices manufactured by Altera and sold by 18 | Altera or its authorized distributors. Please refer to the 19 | applicable agreement for further details. 20 | */ 21 | (header "symbol" (version "1.1")) 22 | (symbol 23 | (rect 0 0 96 48) 24 | (text "lpm_constant4" (rect 6 1 106 17)(font "Arial" (font_size 10))) 25 | (text "inst" (rect 8 32 25 44)(font "Arial" )) 26 | (port 27 | (pt 96 24) 28 | (output) 29 | (text "result[10..0]" (rect 0 0 67 14)(font "Arial" (font_size 8))) 30 | (text "result[10..0]" (rect 93 -31 106 24)(font "Arial" (font_size 8))(invisible)) 31 | (line (pt 96 24)(pt 80 24)(line_width 3)) 32 | ) 33 | (drawing 34 | (text "2040" (rect 60 18 80 30)(font "Arial" )) 35 | (text "11" (rect 85 25 95 37)(font "Arial" )) 36 | (line (pt 16 16)(pt 80 16)(line_width 1)) 37 | (line (pt 80 16)(pt 80 32)(line_width 1)) 38 | (line (pt 80 32)(pt 16 32)(line_width 1)) 39 | (line (pt 16 32)(pt 16 16)(line_width 1)) 40 | (line (pt 80 28)(pt 88 20)(line_width 1)) 41 | ) 42 | ) 43 | -------------------------------------------------------------------------------- /altip_orig/lpm_constant4.inc: -------------------------------------------------------------------------------- 1 | --Copyright (C) 1991-2008 Altera Corporation 2 | --Your use of Altera Corporation's design tools, logic functions 3 | --and other software and tools, and its AMPP partner logic 4 | --functions, and any output files from any of the foregoing 5 | --(including device programming or simulation files), and any 6 | --associated documentation or information are expressly subject 7 | --to the terms and conditions of the Altera Program License 8 | --Subscription Agreement, Altera MegaCore Function License 9 | --Agreement, or other applicable license agreement, including, 10 | --without limitation, that your use is for the sole purpose of 11 | --programming logic devices manufactured by Altera and sold by 12 | --Altera or its authorized distributors. Please refer to the 13 | --applicable agreement for further details. 14 | 15 | 16 | FUNCTION lpm_constant4 17 | ( 18 | 19 | ) 20 | 21 | RETURNS ( 22 | result[10..0] 23 | ); 24 | -------------------------------------------------------------------------------- /altip_orig/lpm_constant4.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "LPM_CONSTANT" 2 | set_global_assignment -name IP_TOOL_VERSION "8.1" 3 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_constant4.vhd"] 4 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_constant4.bsf"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_constant4.inc"] 6 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_constant4.cmp"] 7 | -------------------------------------------------------------------------------- /altip_orig/lpm_counter0.bsf: -------------------------------------------------------------------------------- 1 | /* 2 | WARNING: Do NOT edit the input and output ports in this file in a text 3 | editor if you plan to continue editing the block that represents it in 4 | the Block Editor! File corruption is VERY likely to occur. 5 | */ 6 | /* 7 | Copyright (C) 1991-2008 Altera Corporation 8 | Your use of Altera Corporation's design tools, logic functions 9 | and other software and tools, and its AMPP partner logic 10 | functions, and any output files from any of the foregoing 11 | (including device programming or simulation files), and any 12 | associated documentation or information are expressly subject 13 | to the terms and conditions of the Altera Program License 14 | Subscription Agreement, Altera MegaCore Function License 15 | Agreement, or other applicable license agreement, including, 16 | without limitation, that your use is for the sole purpose of 17 | programming logic devices manufactured by Altera and sold by 18 | Altera or its authorized distributors. Please refer to the 19 | applicable agreement for further details. 20 | */ 21 | (header "symbol" (version "1.1")) 22 | (symbol 23 | (rect 0 0 144 64) 24 | (text "lpm_counter0" (rect 33 1 125 17)(font "Arial" (font_size 10))) 25 | (text "inst" (rect 8 48 25 60)(font "Arial" )) 26 | (port 27 | (pt 0 32) 28 | (input) 29 | (text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8))) 30 | (text "clock" (rect 26 26 49 39)(font "Arial" (font_size 8))) 31 | (line (pt 0 32)(pt 16 32)(line_width 1)) 32 | ) 33 | (port 34 | (pt 144 40) 35 | (output) 36 | (text "q[17..0]" (rect 0 0 42 14)(font "Arial" (font_size 8))) 37 | (text "q[17..0]" (rect 89 34 125 47)(font "Arial" (font_size 8))) 38 | (line (pt 144 40)(pt 128 40)(line_width 3)) 39 | ) 40 | (drawing 41 | (text "up counter" (rect 84 17 128 29)(font "Arial" )) 42 | (line (pt 16 16)(pt 128 16)(line_width 1)) 43 | (line (pt 128 16)(pt 128 48)(line_width 1)) 44 | (line (pt 128 48)(pt 16 48)(line_width 1)) 45 | (line (pt 16 48)(pt 16 16)(line_width 1)) 46 | (line (pt 16 26)(pt 22 32)(line_width 1)) 47 | (line (pt 22 32)(pt 16 38)(line_width 1)) 48 | ) 49 | ) 50 | -------------------------------------------------------------------------------- /altip_orig/lpm_counter0.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "LPM_COUNTER" 2 | set_global_assignment -name IP_TOOL_VERSION "8.1" 3 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_counter0.vhd"] 4 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_counter0.bsf"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_counter0.cmp"] 6 | -------------------------------------------------------------------------------- /altip_orig/lpm_ff0.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "LPM_FF" 2 | set_global_assignment -name IP_TOOL_VERSION "8.1" 3 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_ff0.vhd"] 4 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_ff0.bsf"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_ff0.cmp"] 6 | -------------------------------------------------------------------------------- /altip_orig/lpm_ff1.bsf: -------------------------------------------------------------------------------- 1 | /* 2 | WARNING: Do NOT edit the input and output ports in this file in a text 3 | editor if you plan to continue editing the block that represents it in 4 | the Block Editor! File corruption is VERY likely to occur. 5 | */ 6 | /* 7 | Copyright (C) 1991-2008 Altera Corporation 8 | Your use of Altera Corporation's design tools, logic functions 9 | and other software and tools, and its AMPP partner logic 10 | functions, and any output files from any of the foregoing 11 | (including device programming or simulation files), and any 12 | associated documentation or information are expressly subject 13 | to the terms and conditions of the Altera Program License 14 | Subscription Agreement, Altera MegaCore Function License 15 | Agreement, or other applicable license agreement, including, 16 | without limitation, that your use is for the sole purpose of 17 | programming logic devices manufactured by Altera and sold by 18 | Altera or its authorized distributors. Please refer to the 19 | applicable agreement for further details. 20 | */ 21 | (header "symbol" (version "1.1")) 22 | (symbol 23 | (rect 0 0 144 80) 24 | (text "lpm_ff1" (rect 52 1 100 17)(font "Arial" (font_size 10))) 25 | (text "inst" (rect 8 64 25 76)(font "Arial" )) 26 | (port 27 | (pt 0 32) 28 | (input) 29 | (text "data[31..0]" (rect 0 0 60 14)(font "Arial" (font_size 8))) 30 | (text "data[31..0]" (rect 20 26 71 39)(font "Arial" (font_size 8))) 31 | (line (pt 0 32)(pt 16 32)(line_width 3)) 32 | ) 33 | (port 34 | (pt 0 48) 35 | (input) 36 | (text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8))) 37 | (text "clock" (rect 26 42 49 55)(font "Arial" (font_size 8))) 38 | (line (pt 0 48)(pt 16 48)(line_width 1)) 39 | ) 40 | (port 41 | (pt 144 48) 42 | (output) 43 | (text "q[31..0]" (rect 0 0 42 14)(font "Arial" (font_size 8))) 44 | (text "q[31..0]" (rect 89 42 125 55)(font "Arial" (font_size 8))) 45 | (line (pt 144 48)(pt 128 48)(line_width 3)) 46 | ) 47 | (drawing 48 | (text "DFF" (rect 109 17 128 29)(font "Arial" )) 49 | (line (pt 16 16)(pt 128 16)(line_width 1)) 50 | (line (pt 128 16)(pt 128 64)(line_width 1)) 51 | (line (pt 128 64)(pt 16 64)(line_width 1)) 52 | (line (pt 16 64)(pt 16 16)(line_width 1)) 53 | (line (pt 16 42)(pt 22 48)(line_width 1)) 54 | (line (pt 22 48)(pt 16 54)(line_width 1)) 55 | ) 56 | ) 57 | -------------------------------------------------------------------------------- /altip_orig/lpm_ff1.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "LPM_FF" 2 | set_global_assignment -name IP_TOOL_VERSION "8.1" 3 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_ff1.vhd"] 4 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_ff1.bsf"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_ff1.cmp"] 6 | -------------------------------------------------------------------------------- /altip_orig/lpm_ff2.bsf: -------------------------------------------------------------------------------- 1 | /* 2 | WARNING: Do NOT edit the input and output ports in this file in a text 3 | editor if you plan to continue editing the block that represents it in 4 | the Block Editor! File corruption is VERY likely to occur. 5 | */ 6 | /* 7 | Copyright (C) 1991-2008 Altera Corporation 8 | Your use of Altera Corporation's design tools, logic functions 9 | and other software and tools, and its AMPP partner logic 10 | functions, and any output files from any of the foregoing 11 | (including device programming or simulation files), and any 12 | associated documentation or information are expressly subject 13 | to the terms and conditions of the Altera Program License 14 | Subscription Agreement, Altera MegaCore Function License 15 | Agreement, or other applicable license agreement, including, 16 | without limitation, that your use is for the sole purpose of 17 | programming logic devices manufactured by Altera and sold by 18 | Altera or its authorized distributors. Please refer to the 19 | applicable agreement for further details. 20 | */ 21 | (header "symbol" (version "1.1")) 22 | (symbol 23 | (rect 0 0 144 80) 24 | (text "lpm_ff2" (rect 52 1 100 17)(font "Arial" (font_size 10))) 25 | (text "inst" (rect 8 64 25 76)(font "Arial" )) 26 | (port 27 | (pt 0 32) 28 | (input) 29 | (text "data[127..0]" (rect 0 0 67 14)(font "Arial" (font_size 8))) 30 | (text "data[127..0]" (rect 20 26 77 39)(font "Arial" (font_size 8))) 31 | (line (pt 0 32)(pt 16 32)(line_width 3)) 32 | ) 33 | (port 34 | (pt 0 48) 35 | (input) 36 | (text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8))) 37 | (text "clock" (rect 26 42 49 55)(font "Arial" (font_size 8))) 38 | (line (pt 0 48)(pt 16 48)(line_width 1)) 39 | ) 40 | (port 41 | (pt 144 48) 42 | (output) 43 | (text "q[127..0]" (rect 0 0 49 14)(font "Arial" (font_size 8))) 44 | (text "q[127..0]" (rect 83 42 125 55)(font "Arial" (font_size 8))) 45 | (line (pt 144 48)(pt 128 48)(line_width 3)) 46 | ) 47 | (drawing 48 | (text "DFF" (rect 109 17 128 29)(font "Arial" )) 49 | (line (pt 16 16)(pt 128 16)(line_width 1)) 50 | (line (pt 128 16)(pt 128 64)(line_width 1)) 51 | (line (pt 128 64)(pt 16 64)(line_width 1)) 52 | (line (pt 16 64)(pt 16 16)(line_width 1)) 53 | (line (pt 16 42)(pt 22 48)(line_width 1)) 54 | (line (pt 22 48)(pt 16 54)(line_width 1)) 55 | ) 56 | ) 57 | -------------------------------------------------------------------------------- /altip_orig/lpm_ff2.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "LPM_FF" 2 | set_global_assignment -name IP_TOOL_VERSION "8.1" 3 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_ff2.vhd"] 4 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_ff2.bsf"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_ff2.cmp"] 6 | -------------------------------------------------------------------------------- /altip_orig/lpm_ff3.bsf: -------------------------------------------------------------------------------- 1 | /* 2 | WARNING: Do NOT edit the input and output ports in this file in a text 3 | editor if you plan to continue editing the block that represents it in 4 | the Block Editor! File corruption is VERY likely to occur. 5 | */ 6 | /* 7 | Copyright (C) 1991-2008 Altera Corporation 8 | Your use of Altera Corporation's design tools, logic functions 9 | and other software and tools, and its AMPP partner logic 10 | functions, and any output files from any of the foregoing 11 | (including device programming or simulation files), and any 12 | associated documentation or information are expressly subject 13 | to the terms and conditions of the Altera Program License 14 | Subscription Agreement, Altera MegaCore Function License 15 | Agreement, or other applicable license agreement, including, 16 | without limitation, that your use is for the sole purpose of 17 | programming logic devices manufactured by Altera and sold by 18 | Altera or its authorized distributors. Please refer to the 19 | applicable agreement for further details. 20 | */ 21 | (header "symbol" (version "1.1")) 22 | (symbol 23 | (rect 0 0 144 80) 24 | (text "lpm_ff3" (rect 52 1 100 17)(font "Arial" (font_size 10))) 25 | (text "inst" (rect 8 64 25 76)(font "Arial" )) 26 | (port 27 | (pt 0 32) 28 | (input) 29 | (text "data[23..0]" (rect 0 0 60 14)(font "Arial" (font_size 8))) 30 | (text "data[23..0]" (rect 20 26 71 39)(font "Arial" (font_size 8))) 31 | (line (pt 0 32)(pt 16 32)(line_width 3)) 32 | ) 33 | (port 34 | (pt 0 48) 35 | (input) 36 | (text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8))) 37 | (text "clock" (rect 26 42 49 55)(font "Arial" (font_size 8))) 38 | (line (pt 0 48)(pt 16 48)(line_width 1)) 39 | ) 40 | (port 41 | (pt 144 48) 42 | (output) 43 | (text "q[23..0]" (rect 0 0 42 14)(font "Arial" (font_size 8))) 44 | (text "q[23..0]" (rect 89 42 125 55)(font "Arial" (font_size 8))) 45 | (line (pt 144 48)(pt 128 48)(line_width 3)) 46 | ) 47 | (drawing 48 | (text "DFF" (rect 109 17 128 29)(font "Arial" )) 49 | (line (pt 16 16)(pt 128 16)(line_width 1)) 50 | (line (pt 128 16)(pt 128 64)(line_width 1)) 51 | (line (pt 128 64)(pt 16 64)(line_width 1)) 52 | (line (pt 16 64)(pt 16 16)(line_width 1)) 53 | (line (pt 16 42)(pt 22 48)(line_width 1)) 54 | (line (pt 22 48)(pt 16 54)(line_width 1)) 55 | ) 56 | ) 57 | -------------------------------------------------------------------------------- /altip_orig/lpm_ff3.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "LPM_FF" 2 | set_global_assignment -name IP_TOOL_VERSION "8.1" 3 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_ff3.vhd"] 4 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_ff3.bsf"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_ff3.cmp"] 6 | -------------------------------------------------------------------------------- /altip_orig/lpm_ff4.bsf: -------------------------------------------------------------------------------- 1 | /* 2 | WARNING: Do NOT edit the input and output ports in this file in a text 3 | editor if you plan to continue editing the block that represents it in 4 | the Block Editor! File corruption is VERY likely to occur. 5 | */ 6 | /* 7 | Copyright (C) 1991-2008 Altera Corporation 8 | Your use of Altera Corporation's design tools, logic functions 9 | and other software and tools, and its AMPP partner logic 10 | functions, and any output files from any of the foregoing 11 | (including device programming or simulation files), and any 12 | associated documentation or information are expressly subject 13 | to the terms and conditions of the Altera Program License 14 | Subscription Agreement, Altera MegaCore Function License 15 | Agreement, or other applicable license agreement, including, 16 | without limitation, that your use is for the sole purpose of 17 | programming logic devices manufactured by Altera and sold by 18 | Altera or its authorized distributors. Please refer to the 19 | applicable agreement for further details. 20 | */ 21 | (header "symbol" (version "1.1")) 22 | (symbol 23 | (rect 0 0 144 80) 24 | (text "lpm_ff4" (rect 52 1 100 17)(font "Arial" (font_size 10))) 25 | (text "inst" (rect 8 64 25 76)(font "Arial" )) 26 | (port 27 | (pt 0 32) 28 | (input) 29 | (text "data[15..0]" (rect 0 0 60 14)(font "Arial" (font_size 8))) 30 | (text "data[15..0]" (rect 20 26 71 39)(font "Arial" (font_size 8))) 31 | (line (pt 0 32)(pt 16 32)(line_width 3)) 32 | ) 33 | (port 34 | (pt 0 48) 35 | (input) 36 | (text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8))) 37 | (text "clock" (rect 26 42 49 55)(font "Arial" (font_size 8))) 38 | (line (pt 0 48)(pt 16 48)(line_width 1)) 39 | ) 40 | (port 41 | (pt 144 48) 42 | (output) 43 | (text "q[15..0]" (rect 0 0 42 14)(font "Arial" (font_size 8))) 44 | (text "q[15..0]" (rect 89 42 125 55)(font "Arial" (font_size 8))) 45 | (line (pt 144 48)(pt 128 48)(line_width 3)) 46 | ) 47 | (drawing 48 | (text "DFF" (rect 109 17 128 29)(font "Arial" )) 49 | (line (pt 16 16)(pt 128 16)(line_width 1)) 50 | (line (pt 128 16)(pt 128 64)(line_width 1)) 51 | (line (pt 128 64)(pt 16 64)(line_width 1)) 52 | (line (pt 16 64)(pt 16 16)(line_width 1)) 53 | (line (pt 16 42)(pt 22 48)(line_width 1)) 54 | (line (pt 22 48)(pt 16 54)(line_width 1)) 55 | ) 56 | ) 57 | -------------------------------------------------------------------------------- /altip_orig/lpm_ff4.inc: -------------------------------------------------------------------------------- 1 | --Copyright (C) 1991-2008 Altera Corporation 2 | --Your use of Altera Corporation's design tools, logic functions 3 | --and other software and tools, and its AMPP partner logic 4 | --functions, and any output files from any of the foregoing 5 | --(including device programming or simulation files), and any 6 | --associated documentation or information are expressly subject 7 | --to the terms and conditions of the Altera Program License 8 | --Subscription Agreement, Altera MegaCore Function License 9 | --Agreement, or other applicable license agreement, including, 10 | --without limitation, that your use is for the sole purpose of 11 | --programming logic devices manufactured by Altera and sold by 12 | --Altera or its authorized distributors. Please refer to the 13 | --applicable agreement for further details. 14 | 15 | 16 | FUNCTION lpm_ff4 17 | ( 18 | clock, 19 | data[15..0] 20 | ) 21 | 22 | RETURNS ( 23 | q[15..0] 24 | ); 25 | -------------------------------------------------------------------------------- /altip_orig/lpm_ff4.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "LPM_FF" 2 | set_global_assignment -name IP_TOOL_VERSION "8.1" 3 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_ff4.vhd"] 4 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_ff4.bsf"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_ff4.inc"] 6 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_ff4.cmp"] 7 | -------------------------------------------------------------------------------- /altip_orig/lpm_ff5.bsf: -------------------------------------------------------------------------------- 1 | /* 2 | WARNING: Do NOT edit the input and output ports in this file in a text 3 | editor if you plan to continue editing the block that represents it in 4 | the Block Editor! File corruption is VERY likely to occur. 5 | */ 6 | /* 7 | Copyright (C) 1991-2008 Altera Corporation 8 | Your use of Altera Corporation's design tools, logic functions 9 | and other software and tools, and its AMPP partner logic 10 | functions, and any output files from any of the foregoing 11 | (including device programming or simulation files), and any 12 | associated documentation or information are expressly subject 13 | to the terms and conditions of the Altera Program License 14 | Subscription Agreement, Altera MegaCore Function License 15 | Agreement, or other applicable license agreement, including, 16 | without limitation, that your use is for the sole purpose of 17 | programming logic devices manufactured by Altera and sold by 18 | Altera or its authorized distributors. Please refer to the 19 | applicable agreement for further details. 20 | */ 21 | (header "symbol" (version "1.1")) 22 | (symbol 23 | (rect 0 0 144 80) 24 | (text "lpm_ff5" (rect 52 1 100 17)(font "Arial" (font_size 10))) 25 | (text "inst" (rect 8 64 25 76)(font "Arial" )) 26 | (port 27 | (pt 0 32) 28 | (input) 29 | (text "data[7..0]" (rect 0 0 53 14)(font "Arial" (font_size 8))) 30 | (text "data[7..0]" (rect 20 26 65 39)(font "Arial" (font_size 8))) 31 | (line (pt 0 32)(pt 16 32)(line_width 3)) 32 | ) 33 | (port 34 | (pt 0 48) 35 | (input) 36 | (text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8))) 37 | (text "clock" (rect 26 42 49 55)(font "Arial" (font_size 8))) 38 | (line (pt 0 48)(pt 16 48)(line_width 1)) 39 | ) 40 | (port 41 | (pt 144 48) 42 | (output) 43 | (text "q[7..0]" (rect 0 0 35 14)(font "Arial" (font_size 8))) 44 | (text "q[7..0]" (rect 95 42 125 55)(font "Arial" (font_size 8))) 45 | (line (pt 144 48)(pt 128 48)(line_width 3)) 46 | ) 47 | (drawing 48 | (text "DFF" (rect 109 17 128 29)(font "Arial" )) 49 | (line (pt 16 16)(pt 128 16)(line_width 1)) 50 | (line (pt 128 16)(pt 128 64)(line_width 1)) 51 | (line (pt 128 64)(pt 16 64)(line_width 1)) 52 | (line (pt 16 64)(pt 16 16)(line_width 1)) 53 | (line (pt 16 42)(pt 22 48)(line_width 1)) 54 | (line (pt 22 48)(pt 16 54)(line_width 1)) 55 | ) 56 | ) 57 | -------------------------------------------------------------------------------- /altip_orig/lpm_ff5.inc: -------------------------------------------------------------------------------- 1 | --Copyright (C) 1991-2008 Altera Corporation 2 | --Your use of Altera Corporation's design tools, logic functions 3 | --and other software and tools, and its AMPP partner logic 4 | --functions, and any output files from any of the foregoing 5 | --(including device programming or simulation files), and any 6 | --associated documentation or information are expressly subject 7 | --to the terms and conditions of the Altera Program License 8 | --Subscription Agreement, Altera MegaCore Function License 9 | --Agreement, or other applicable license agreement, including, 10 | --without limitation, that your use is for the sole purpose of 11 | --programming logic devices manufactured by Altera and sold by 12 | --Altera or its authorized distributors. Please refer to the 13 | --applicable agreement for further details. 14 | 15 | 16 | FUNCTION lpm_ff5 17 | ( 18 | clock, 19 | data[7..0] 20 | ) 21 | 22 | RETURNS ( 23 | q[7..0] 24 | ); 25 | -------------------------------------------------------------------------------- /altip_orig/lpm_ff5.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "LPM_FF" 2 | set_global_assignment -name IP_TOOL_VERSION "8.1" 3 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_ff5.vhd"] 4 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_ff5.bsf"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_ff5.inc"] 6 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_ff5.cmp"] 7 | -------------------------------------------------------------------------------- /altip_orig/lpm_ff6.inc: -------------------------------------------------------------------------------- 1 | --Copyright (C) 1991-2008 Altera Corporation 2 | --Your use of Altera Corporation's design tools, logic functions 3 | --and other software and tools, and its AMPP partner logic 4 | --functions, and any output files from any of the foregoing 5 | --(including device programming or simulation files), and any 6 | --associated documentation or information are expressly subject 7 | --to the terms and conditions of the Altera Program License 8 | --Subscription Agreement, Altera MegaCore Function License 9 | --Agreement, or other applicable license agreement, including, 10 | --without limitation, that your use is for the sole purpose of 11 | --programming logic devices manufactured by Altera and sold by 12 | --Altera or its authorized distributors. Please refer to the 13 | --applicable agreement for further details. 14 | 15 | 16 | FUNCTION lpm_ff6 17 | ( 18 | clock, 19 | data[127..0], 20 | enable 21 | ) 22 | 23 | RETURNS ( 24 | q[127..0] 25 | ); 26 | -------------------------------------------------------------------------------- /altip_orig/lpm_ff6.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "LPM_FF" 2 | set_global_assignment -name IP_TOOL_VERSION "8.1" 3 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_ff6.vhd"] 4 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_ff6.bsf"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_ff6.inc"] 6 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_ff6.cmp"] 7 | -------------------------------------------------------------------------------- /altip_orig/lpm_fifoDZ.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "LPM_FIFO+" 2 | set_global_assignment -name IP_TOOL_VERSION "9.1" 3 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_fifoDZ.vhd"] 4 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_fifoDZ.bsf"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_fifoDZ.cmp"] 6 | -------------------------------------------------------------------------------- /altip_orig/lpm_fifo_dc0.inc: -------------------------------------------------------------------------------- 1 | --Copyright (C) 1991-2008 Altera Corporation 2 | --Your use of Altera Corporation's design tools, logic functions 3 | --and other software and tools, and its AMPP partner logic 4 | --functions, and any output files from any of the foregoing 5 | --(including device programming or simulation files), and any 6 | --associated documentation or information are expressly subject 7 | --to the terms and conditions of the Altera Program License 8 | --Subscription Agreement, Altera MegaCore Function License 9 | --Agreement, or other applicable license agreement, including, 10 | --without limitation, that your use is for the sole purpose of 11 | --programming logic devices manufactured by Altera and sold by 12 | --Altera or its authorized distributors. Please refer to the 13 | --applicable agreement for further details. 14 | 15 | 16 | FUNCTION lpm_fifo_dc0 17 | ( 18 | aclr, 19 | data[127..0], 20 | rdclk, 21 | rdreq, 22 | wrclk, 23 | wrreq 24 | ) 25 | 26 | RETURNS ( 27 | q[127..0], 28 | rdempty, 29 | wrusedw[8..0] 30 | ); 31 | -------------------------------------------------------------------------------- /altip_orig/lpm_fifo_dc0.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "LPM_FIFO+" 2 | set_global_assignment -name IP_TOOL_VERSION "8.1" 3 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_fifo_dc0.vhd"] 4 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_fifo_dc0.bsf"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_fifo_dc0.inc"] 6 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_fifo_dc0.cmp"] 7 | -------------------------------------------------------------------------------- /altip_orig/lpm_latch0.bsf: -------------------------------------------------------------------------------- 1 | /* 2 | WARNING: Do NOT edit the input and output ports in this file in a text 3 | editor if you plan to continue editing the block that represents it in 4 | the Block Editor! File corruption is VERY likely to occur. 5 | */ 6 | /* 7 | Copyright (C) 1991-2008 Altera Corporation 8 | Your use of Altera Corporation's design tools, logic functions 9 | and other software and tools, and its AMPP partner logic 10 | functions, and any output files from any of the foregoing 11 | (including device programming or simulation files), and any 12 | associated documentation or information are expressly subject 13 | to the terms and conditions of the Altera Program License 14 | Subscription Agreement, Altera MegaCore Function License 15 | Agreement, or other applicable license agreement, including, 16 | without limitation, that your use is for the sole purpose of 17 | programming logic devices manufactured by Altera and sold by 18 | Altera or its authorized distributors. Please refer to the 19 | applicable agreement for further details. 20 | */ 21 | (header "symbol" (version "1.1")) 22 | (symbol 23 | (rect 0 0 160 80) 24 | (text "lpm_latch0" (rect 49 1 123 17)(font "Arial" (font_size 10))) 25 | (text "inst" (rect 8 64 25 76)(font "Arial" )) 26 | (port 27 | (pt 0 32) 28 | (input) 29 | (text "data[31..0]" (rect 0 0 60 14)(font "Arial" (font_size 8))) 30 | (text "data[31..0]" (rect 20 26 71 39)(font "Arial" (font_size 8))) 31 | (line (pt 0 32)(pt 16 32)(line_width 3)) 32 | ) 33 | (port 34 | (pt 0 48) 35 | (input) 36 | (text "gate" (rect 0 0 24 14)(font "Arial" (font_size 8))) 37 | (text "gate" (rect 20 42 41 55)(font "Arial" (font_size 8))) 38 | (line (pt 0 48)(pt 16 48)(line_width 1)) 39 | ) 40 | (port 41 | (pt 160 32) 42 | (output) 43 | (text "q[31..0]" (rect 0 0 42 14)(font "Arial" (font_size 8))) 44 | (text "q[31..0]" (rect 105 26 141 39)(font "Arial" (font_size 8))) 45 | (line (pt 160 32)(pt 144 32)(line_width 3)) 46 | ) 47 | (drawing 48 | (line (pt 16 16)(pt 144 16)(line_width 1)) 49 | (line (pt 144 16)(pt 144 64)(line_width 1)) 50 | (line (pt 144 64)(pt 16 64)(line_width 1)) 51 | (line (pt 16 64)(pt 16 16)(line_width 1)) 52 | ) 53 | ) 54 | -------------------------------------------------------------------------------- /altip_orig/lpm_latch0.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "LPM_LATCH" 2 | set_global_assignment -name IP_TOOL_VERSION "8.1" 3 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_latch0.vhd"] 4 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_latch0.bsf"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_latch0.cmp"] 6 | -------------------------------------------------------------------------------- /altip_orig/lpm_latch1.bsf: -------------------------------------------------------------------------------- 1 | /* 2 | WARNING: Do NOT edit the input and output ports in this file in a text 3 | editor if you plan to continue editing the block that represents it in 4 | the Block Editor! File corruption is VERY likely to occur. 5 | */ 6 | /* 7 | Copyright (C) 1991-2008 Altera Corporation 8 | Your use of Altera Corporation's design tools, logic functions 9 | and other software and tools, and its AMPP partner logic 10 | functions, and any output files from any of the foregoing 11 | (including device programming or simulation files), and any 12 | associated documentation or information are expressly subject 13 | to the terms and conditions of the Altera Program License 14 | Subscription Agreement, Altera MegaCore Function License 15 | Agreement, or other applicable license agreement, including, 16 | without limitation, that your use is for the sole purpose of 17 | programming logic devices manufactured by Altera and sold by 18 | Altera or its authorized distributors. Please refer to the 19 | applicable agreement for further details. 20 | */ 21 | (header "symbol" (version "1.1")) 22 | (symbol 23 | (rect 0 0 160 80) 24 | (text "lpm_latch1" (rect 49 1 123 17)(font "Arial" (font_size 10))) 25 | (text "inst" (rect 8 64 25 76)(font "Arial" )) 26 | (port 27 | (pt 0 32) 28 | (input) 29 | (text "data[31..0]" (rect 0 0 60 14)(font "Arial" (font_size 8))) 30 | (text "data[31..0]" (rect 20 26 71 39)(font "Arial" (font_size 8))) 31 | (line (pt 0 32)(pt 16 32)(line_width 3)) 32 | ) 33 | (port 34 | (pt 0 48) 35 | (input) 36 | (text "gate" (rect 0 0 24 14)(font "Arial" (font_size 8))) 37 | (text "gate" (rect 20 42 41 55)(font "Arial" (font_size 8))) 38 | (line (pt 0 48)(pt 16 48)(line_width 1)) 39 | ) 40 | (port 41 | (pt 160 32) 42 | (output) 43 | (text "q[31..0]" (rect 0 0 42 14)(font "Arial" (font_size 8))) 44 | (text "q[31..0]" (rect 105 26 141 39)(font "Arial" (font_size 8))) 45 | (line (pt 160 32)(pt 144 32)(line_width 3)) 46 | ) 47 | (drawing 48 | (line (pt 16 16)(pt 144 16)(line_width 1)) 49 | (line (pt 144 16)(pt 144 64)(line_width 1)) 50 | (line (pt 144 64)(pt 16 64)(line_width 1)) 51 | (line (pt 16 64)(pt 16 16)(line_width 1)) 52 | ) 53 | ) 54 | -------------------------------------------------------------------------------- /altip_orig/lpm_latch1.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "LPM_LATCH" 2 | set_global_assignment -name IP_TOOL_VERSION "8.1" 3 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_latch1.vhd"] 4 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_latch1.bsf"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_latch1.cmp"] 6 | -------------------------------------------------------------------------------- /altip_orig/lpm_mux0.inc: -------------------------------------------------------------------------------- 1 | --Copyright (C) 1991-2008 Altera Corporation 2 | --Your use of Altera Corporation's design tools, logic functions 3 | --and other software and tools, and its AMPP partner logic 4 | --functions, and any output files from any of the foregoing 5 | --(including device programming or simulation files), and any 6 | --associated documentation or information are expressly subject 7 | --to the terms and conditions of the Altera Program License 8 | --Subscription Agreement, Altera MegaCore Function License 9 | --Agreement, or other applicable license agreement, including, 10 | --without limitation, that your use is for the sole purpose of 11 | --programming logic devices manufactured by Altera and sold by 12 | --Altera or its authorized distributors. Please refer to the 13 | --applicable agreement for further details. 14 | 15 | 16 | FUNCTION lpm_mux0 17 | ( 18 | clock, 19 | data0x[31..0], 20 | data1x[31..0], 21 | data2x[31..0], 22 | data3x[31..0], 23 | sel[1..0] 24 | ) 25 | 26 | RETURNS ( 27 | result[31..0] 28 | ); 29 | -------------------------------------------------------------------------------- /altip_orig/lpm_mux0.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "LPM_MUX" 2 | set_global_assignment -name IP_TOOL_VERSION "8.1" 3 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_mux0.vhd"] 4 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux0.bsf"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux0.inc"] 6 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux0.cmp"] 7 | -------------------------------------------------------------------------------- /altip_orig/lpm_mux1.inc: -------------------------------------------------------------------------------- 1 | --Copyright (C) 1991-2008 Altera Corporation 2 | --Your use of Altera Corporation's design tools, logic functions 3 | --and other software and tools, and its AMPP partner logic 4 | --functions, and any output files from any of the foregoing 5 | --(including device programming or simulation files), and any 6 | --associated documentation or information are expressly subject 7 | --to the terms and conditions of the Altera Program License 8 | --Subscription Agreement, Altera MegaCore Function License 9 | --Agreement, or other applicable license agreement, including, 10 | --without limitation, that your use is for the sole purpose of 11 | --programming logic devices manufactured by Altera and sold by 12 | --Altera or its authorized distributors. Please refer to the 13 | --applicable agreement for further details. 14 | 15 | 16 | FUNCTION lpm_mux1 17 | ( 18 | clock, 19 | data0x[15..0], 20 | data1x[15..0], 21 | data2x[15..0], 22 | data3x[15..0], 23 | data4x[15..0], 24 | data5x[15..0], 25 | data6x[15..0], 26 | data7x[15..0], 27 | sel[2..0] 28 | ) 29 | 30 | RETURNS ( 31 | result[15..0] 32 | ); 33 | -------------------------------------------------------------------------------- /altip_orig/lpm_mux1.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "LPM_MUX" 2 | set_global_assignment -name IP_TOOL_VERSION "8.1" 3 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_mux1.vhd"] 4 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux1.bsf"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux1.inc"] 6 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux1.cmp"] 7 | -------------------------------------------------------------------------------- /altip_orig/lpm_mux2.inc: -------------------------------------------------------------------------------- 1 | --Copyright (C) 1991-2008 Altera Corporation 2 | --Your use of Altera Corporation's design tools, logic functions 3 | --and other software and tools, and its AMPP partner logic 4 | --functions, and any output files from any of the foregoing 5 | --(including device programming or simulation files), and any 6 | --associated documentation or information are expressly subject 7 | --to the terms and conditions of the Altera Program License 8 | --Subscription Agreement, Altera MegaCore Function License 9 | --Agreement, or other applicable license agreement, including, 10 | --without limitation, that your use is for the sole purpose of 11 | --programming logic devices manufactured by Altera and sold by 12 | --Altera or its authorized distributors. Please refer to the 13 | --applicable agreement for further details. 14 | 15 | 16 | FUNCTION lpm_mux2 17 | ( 18 | clock, 19 | data0x[7..0], 20 | data10x[7..0], 21 | data11x[7..0], 22 | data12x[7..0], 23 | data13x[7..0], 24 | data14x[7..0], 25 | data15x[7..0], 26 | data1x[7..0], 27 | data2x[7..0], 28 | data3x[7..0], 29 | data4x[7..0], 30 | data5x[7..0], 31 | data6x[7..0], 32 | data7x[7..0], 33 | data8x[7..0], 34 | data9x[7..0], 35 | sel[3..0] 36 | ) 37 | 38 | RETURNS ( 39 | result[7..0] 40 | ); 41 | -------------------------------------------------------------------------------- /altip_orig/lpm_mux2.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "LPM_MUX" 2 | set_global_assignment -name IP_TOOL_VERSION "8.1" 3 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_mux2.vhd"] 4 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux2.bsf"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux2.inc"] 6 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux2.cmp"] 7 | -------------------------------------------------------------------------------- /altip_orig/lpm_mux3.bsf: -------------------------------------------------------------------------------- 1 | /* 2 | WARNING: Do NOT edit the input and output ports in this file in a text 3 | editor if you plan to continue editing the block that represents it in 4 | the Block Editor! File corruption is VERY likely to occur. 5 | */ 6 | /* 7 | Copyright (C) 1991-2008 Altera Corporation 8 | Your use of Altera Corporation's design tools, logic functions 9 | and other software and tools, and its AMPP partner logic 10 | functions, and any output files from any of the foregoing 11 | (including device programming or simulation files), and any 12 | associated documentation or information are expressly subject 13 | to the terms and conditions of the Altera Program License 14 | Subscription Agreement, Altera MegaCore Function License 15 | Agreement, or other applicable license agreement, including, 16 | without limitation, that your use is for the sole purpose of 17 | programming logic devices manufactured by Altera and sold by 18 | Altera or its authorized distributors. Please refer to the 19 | applicable agreement for further details. 20 | */ 21 | (header "symbol" (version "1.1")) 22 | (symbol 23 | (rect 0 0 80 80) 24 | (text "lpm_mux3" (rect 10 2 80 18)(font "Arial" (font_size 10))) 25 | (text "inst" (rect 8 64 25 76)(font "Arial" )) 26 | (port 27 | (pt 0 40) 28 | (input) 29 | (text "data1" (rect 0 0 31 14)(font "Arial" (font_size 8))) 30 | (text "data1" (rect 4 27 31 40)(font "Arial" (font_size 8))) 31 | (line (pt 0 40)(pt 32 40)(line_width 1)) 32 | ) 33 | (port 34 | (pt 0 56) 35 | (input) 36 | (text "data0" (rect 0 0 31 14)(font "Arial" (font_size 8))) 37 | (text "data0" (rect 4 43 31 56)(font "Arial" (font_size 8))) 38 | (line (pt 0 56)(pt 32 56)(line_width 1)) 39 | ) 40 | (port 41 | (pt 40 80) 42 | (input) 43 | (text "sel" (rect 0 0 16 14)(font "Arial" (font_size 8))) 44 | (text "sel" (rect 44 67 57 80)(font "Arial" (font_size 8))) 45 | (line (pt 40 80)(pt 40 68)(line_width 1)) 46 | ) 47 | (port 48 | (pt 80 48) 49 | (output) 50 | (text "result" (rect 0 0 31 14)(font "Arial" (font_size 8))) 51 | (text "result" (rect 50 35 75 48)(font "Arial" (font_size 8))) 52 | (line (pt 80 48)(pt 48 48)(line_width 1)) 53 | ) 54 | (drawing 55 | (line (pt 32 24)(pt 32 72)(line_width 1)) 56 | (line (pt 48 32)(pt 48 64)(line_width 1)) 57 | (line (pt 32 24)(pt 48 32)(line_width 1)) 58 | (line (pt 32 72)(pt 48 64)(line_width 1)) 59 | ) 60 | ) 61 | -------------------------------------------------------------------------------- /altip_orig/lpm_mux3.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "LPM_MUX" 2 | set_global_assignment -name IP_TOOL_VERSION "8.1" 3 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_mux3.vhd"] 4 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux3.bsf"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux3.cmp"] 6 | -------------------------------------------------------------------------------- /altip_orig/lpm_mux4.bsf: -------------------------------------------------------------------------------- 1 | /* 2 | WARNING: Do NOT edit the input and output ports in this file in a text 3 | editor if you plan to continue editing the block that represents it in 4 | the Block Editor! File corruption is VERY likely to occur. 5 | */ 6 | /* 7 | Copyright (C) 1991-2008 Altera Corporation 8 | Your use of Altera Corporation's design tools, logic functions 9 | and other software and tools, and its AMPP partner logic 10 | functions, and any output files from any of the foregoing 11 | (including device programming or simulation files), and any 12 | associated documentation or information are expressly subject 13 | to the terms and conditions of the Altera Program License 14 | Subscription Agreement, Altera MegaCore Function License 15 | Agreement, or other applicable license agreement, including, 16 | without limitation, that your use is for the sole purpose of 17 | programming logic devices manufactured by Altera and sold by 18 | Altera or its authorized distributors. Please refer to the 19 | applicable agreement for further details. 20 | */ 21 | (header "symbol" (version "1.1")) 22 | (symbol 23 | (rect 0 0 136 80) 24 | (text "lpm_mux4" (rect 42 2 112 18)(font "Arial" (font_size 10))) 25 | (text "inst" (rect 8 64 25 76)(font "Arial" )) 26 | (port 27 | (pt 0 40) 28 | (input) 29 | (text "data1x[6..0]" (rect 0 0 67 14)(font "Arial" (font_size 8))) 30 | (text "data1x[6..0]" (rect 4 27 60 40)(font "Arial" (font_size 8))) 31 | (line (pt 0 40)(pt 64 40)(line_width 3)) 32 | ) 33 | (port 34 | (pt 0 56) 35 | (input) 36 | (text "data0x[6..0]" (rect 0 0 67 14)(font "Arial" (font_size 8))) 37 | (text "data0x[6..0]" (rect 4 43 60 56)(font "Arial" (font_size 8))) 38 | (line (pt 0 56)(pt 64 56)(line_width 3)) 39 | ) 40 | (port 41 | (pt 72 80) 42 | (input) 43 | (text "sel" (rect 0 0 16 14)(font "Arial" (font_size 8))) 44 | (text "sel" (rect 76 67 89 80)(font "Arial" (font_size 8))) 45 | (line (pt 72 80)(pt 72 68)(line_width 1)) 46 | ) 47 | (port 48 | (pt 136 48) 49 | (output) 50 | (text "result[6..0]" (rect 0 0 60 14)(font "Arial" (font_size 8))) 51 | (text "result[6..0]" (rect 82 35 131 48)(font "Arial" (font_size 8))) 52 | (line (pt 136 48)(pt 80 48)(line_width 3)) 53 | ) 54 | (drawing 55 | (line (pt 64 24)(pt 64 72)(line_width 1)) 56 | (line (pt 80 32)(pt 80 64)(line_width 1)) 57 | (line (pt 64 24)(pt 80 32)(line_width 1)) 58 | (line (pt 64 72)(pt 80 64)(line_width 1)) 59 | ) 60 | ) 61 | -------------------------------------------------------------------------------- /altip_orig/lpm_mux4.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "LPM_MUX" 2 | set_global_assignment -name IP_TOOL_VERSION "8.1" 3 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_mux4.vhd"] 4 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux4.bsf"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux4.cmp"] 6 | -------------------------------------------------------------------------------- /altip_orig/lpm_mux5.inc: -------------------------------------------------------------------------------- 1 | --Copyright (C) 1991-2008 Altera Corporation 2 | --Your use of Altera Corporation's design tools, logic functions 3 | --and other software and tools, and its AMPP partner logic 4 | --functions, and any output files from any of the foregoing 5 | --(including device programming or simulation files), and any 6 | --associated documentation or information are expressly subject 7 | --to the terms and conditions of the Altera Program License 8 | --Subscription Agreement, Altera MegaCore Function License 9 | --Agreement, or other applicable license agreement, including, 10 | --without limitation, that your use is for the sole purpose of 11 | --programming logic devices manufactured by Altera and sold by 12 | --Altera or its authorized distributors. Please refer to the 13 | --applicable agreement for further details. 14 | 15 | 16 | FUNCTION lpm_mux5 17 | ( 18 | data0x[63..0], 19 | data1x[63..0], 20 | data2x[63..0], 21 | data3x[63..0], 22 | sel[1..0] 23 | ) 24 | 25 | RETURNS ( 26 | result[63..0] 27 | ); 28 | -------------------------------------------------------------------------------- /altip_orig/lpm_mux5.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "LPM_MUX" 2 | set_global_assignment -name IP_TOOL_VERSION "8.1" 3 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_mux5.vhd"] 4 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux5.bsf"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux5.inc"] 6 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux5.cmp"] 7 | -------------------------------------------------------------------------------- /altip_orig/lpm_mux6.inc: -------------------------------------------------------------------------------- 1 | --Copyright (C) 1991-2008 Altera Corporation 2 | --Your use of Altera Corporation's design tools, logic functions 3 | --and other software and tools, and its AMPP partner logic 4 | --functions, and any output files from any of the foregoing 5 | --(including device programming or simulation files), and any 6 | --associated documentation or information are expressly subject 7 | --to the terms and conditions of the Altera Program License 8 | --Subscription Agreement, Altera MegaCore Function License 9 | --Agreement, or other applicable license agreement, including, 10 | --without limitation, that your use is for the sole purpose of 11 | --programming logic devices manufactured by Altera and sold by 12 | --Altera or its authorized distributors. Please refer to the 13 | --applicable agreement for further details. 14 | 15 | 16 | FUNCTION lpm_mux6 17 | ( 18 | clock, 19 | data0x[23..0], 20 | data1x[23..0], 21 | data2x[23..0], 22 | data3x[23..0], 23 | data4x[23..0], 24 | data5x[23..0], 25 | data6x[23..0], 26 | data7x[23..0], 27 | sel[2..0] 28 | ) 29 | 30 | RETURNS ( 31 | result[23..0] 32 | ); 33 | -------------------------------------------------------------------------------- /altip_orig/lpm_mux6.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "LPM_MUX" 2 | set_global_assignment -name IP_TOOL_VERSION "8.1" 3 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_mux6.vhd"] 4 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux6.bsf"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux6.inc"] 6 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux6.cmp"] 7 | -------------------------------------------------------------------------------- /altip_orig/lpm_muxDZ.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "LPM_MUX" 2 | set_global_assignment -name IP_TOOL_VERSION "9.1" 3 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_muxDZ.vhd"] 4 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_muxDZ.bsf"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_muxDZ.cmp"] 6 | -------------------------------------------------------------------------------- /altip_orig/lpm_muxDZ2.bsf: -------------------------------------------------------------------------------- 1 | /* 2 | WARNING: Do NOT edit the input and output ports in this file in a text 3 | editor if you plan to continue editing the block that represents it in 4 | the Block Editor! File corruption is VERY likely to occur. 5 | */ 6 | /* 7 | Copyright (C) 1991-2009 Altera Corporation 8 | Your use of Altera Corporation's design tools, logic functions 9 | and other software and tools, and its AMPP partner logic 10 | functions, and any output files from any of the foregoing 11 | (including device programming or simulation files), and any 12 | associated documentation or information are expressly subject 13 | to the terms and conditions of the Altera Program License 14 | Subscription Agreement, Altera MegaCore Function License 15 | Agreement, or other applicable license agreement, including, 16 | without limitation, that your use is for the sole purpose of 17 | programming logic devices manufactured by Altera and sold by 18 | Altera or its authorized distributors. Please refer to the 19 | applicable agreement for further details. 20 | */ 21 | (header "symbol" (version "1.1")) 22 | (symbol 23 | (rect 0 0 96 80) 24 | (text "lpm_muxDZ2" (rect 10 2 99 18)(font "Arial" (font_size 10))) 25 | (text "inst" (rect 8 64 25 76)(font "Arial" )) 26 | (port 27 | (pt 0 40) 28 | (input) 29 | (text "data1" (rect 0 0 31 14)(font "Arial" (font_size 8))) 30 | (text "data1" (rect 4 27 31 40)(font "Arial" (font_size 8))) 31 | (line (pt 0 40)(pt 40 40)(line_width 1)) 32 | ) 33 | (port 34 | (pt 0 56) 35 | (input) 36 | (text "data0" (rect 0 0 31 14)(font "Arial" (font_size 8))) 37 | (text "data0" (rect 4 43 31 56)(font "Arial" (font_size 8))) 38 | (line (pt 0 56)(pt 40 56)(line_width 1)) 39 | ) 40 | (port 41 | (pt 48 80) 42 | (input) 43 | (text "sel" (rect 0 0 16 14)(font "Arial" (font_size 8))) 44 | (text "sel" (rect 52 67 65 80)(font "Arial" (font_size 8))) 45 | (line (pt 48 80)(pt 48 68)(line_width 1)) 46 | ) 47 | (port 48 | (pt 96 48) 49 | (output) 50 | (text "result" (rect 0 0 31 14)(font "Arial" (font_size 8))) 51 | (text "result" (rect 66 35 91 48)(font "Arial" (font_size 8))) 52 | (line (pt 96 48)(pt 56 48)(line_width 1)) 53 | ) 54 | (drawing 55 | (line (pt 40 24)(pt 40 72)(line_width 1)) 56 | (line (pt 56 32)(pt 56 64)(line_width 1)) 57 | (line (pt 40 24)(pt 56 32)(line_width 1)) 58 | (line (pt 40 72)(pt 56 64)(line_width 1)) 59 | ) 60 | ) 61 | -------------------------------------------------------------------------------- /altip_orig/lpm_muxDZ2.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "LPM_MUX" 2 | set_global_assignment -name IP_TOOL_VERSION "9.1" 3 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_muxDZ2.vhd"] 4 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_muxDZ2.bsf"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_muxDZ2.cmp"] 6 | -------------------------------------------------------------------------------- /altip_orig/lpm_muxVDM.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "LPM_MUX" 2 | set_global_assignment -name IP_TOOL_VERSION "9.1" 3 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_muxVDM.vhd"] 4 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_muxVDM.bsf"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_muxVDM.cmp"] 6 | -------------------------------------------------------------------------------- /altip_orig/lpm_shiftreg0.inc: -------------------------------------------------------------------------------- 1 | --Copyright (C) 1991-2008 Altera Corporation 2 | --Your use of Altera Corporation's design tools, logic functions 3 | --and other software and tools, and its AMPP partner logic 4 | --functions, and any output files from any of the foregoing 5 | --(including device programming or simulation files), and any 6 | --associated documentation or information are expressly subject 7 | --to the terms and conditions of the Altera Program License 8 | --Subscription Agreement, Altera MegaCore Function License 9 | --Agreement, or other applicable license agreement, including, 10 | --without limitation, that your use is for the sole purpose of 11 | --programming logic devices manufactured by Altera and sold by 12 | --Altera or its authorized distributors. Please refer to the 13 | --applicable agreement for further details. 14 | 15 | 16 | FUNCTION lpm_shiftreg0 17 | ( 18 | clock, 19 | data[15..0], 20 | load, 21 | shiftin 22 | ) 23 | 24 | RETURNS ( 25 | shiftout 26 | ); 27 | -------------------------------------------------------------------------------- /altip_orig/lpm_shiftreg0.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "LPM_SHIFTREG" 2 | set_global_assignment -name IP_TOOL_VERSION "8.1" 3 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_shiftreg0.vhd"] 4 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg0.bsf"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg0.inc"] 6 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg0.cmp"] 7 | -------------------------------------------------------------------------------- /altip_orig/lpm_shiftreg1.bsf: -------------------------------------------------------------------------------- 1 | /* 2 | WARNING: Do NOT edit the input and output ports in this file in a text 3 | editor if you plan to continue editing the block that represents it in 4 | the Block Editor! File corruption is VERY likely to occur. 5 | */ 6 | /* 7 | Copyright (C) 1991-2008 Altera Corporation 8 | Your use of Altera Corporation's design tools, logic functions 9 | and other software and tools, and its AMPP partner logic 10 | functions, and any output files from any of the foregoing 11 | (including device programming or simulation files), and any 12 | associated documentation or information are expressly subject 13 | to the terms and conditions of the Altera Program License 14 | Subscription Agreement, Altera MegaCore Function License 15 | Agreement, or other applicable license agreement, including, 16 | without limitation, that your use is for the sole purpose of 17 | programming logic devices manufactured by Altera and sold by 18 | Altera or its authorized distributors. Please refer to the 19 | applicable agreement for further details. 20 | */ 21 | (header "symbol" (version "1.1")) 22 | (symbol 23 | (rect 0 0 144 80) 24 | (text "lpm_shiftreg1" (rect 34 1 124 17)(font "Arial" (font_size 10))) 25 | (text "inst" (rect 8 64 25 76)(font "Arial" )) 26 | (port 27 | (pt 0 32) 28 | (input) 29 | (text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8))) 30 | (text "clock" (rect 26 26 49 39)(font "Arial" (font_size 8))) 31 | (line (pt 0 32)(pt 16 32)(line_width 1)) 32 | ) 33 | (port 34 | (pt 0 48) 35 | (input) 36 | (text "shiftin" (rect 0 0 34 14)(font "Arial" (font_size 8))) 37 | (text "shiftin" (rect 20 42 48 55)(font "Arial" (font_size 8))) 38 | (line (pt 0 48)(pt 16 48)(line_width 1)) 39 | ) 40 | (port 41 | (pt 144 48) 42 | (output) 43 | (text "q[1..0]" (rect 0 0 35 14)(font "Arial" (font_size 8))) 44 | (text "q[1..0]" (rect 95 42 125 55)(font "Arial" (font_size 8))) 45 | (line (pt 144 48)(pt 128 48)(line_width 3)) 46 | ) 47 | (drawing 48 | (text "left shift" (rect 92 17 128 29)(font "Arial" )) 49 | (line (pt 16 16)(pt 128 16)(line_width 1)) 50 | (line (pt 128 16)(pt 128 64)(line_width 1)) 51 | (line (pt 128 64)(pt 16 64)(line_width 1)) 52 | (line (pt 16 64)(pt 16 16)(line_width 1)) 53 | (line (pt 16 26)(pt 22 32)(line_width 1)) 54 | (line (pt 22 32)(pt 16 38)(line_width 1)) 55 | ) 56 | ) 57 | -------------------------------------------------------------------------------- /altip_orig/lpm_shiftreg1.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "LPM_SHIFTREG" 2 | set_global_assignment -name IP_TOOL_VERSION "8.1" 3 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_shiftreg1.vhd"] 4 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg1.bsf"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg1.cmp"] 6 | -------------------------------------------------------------------------------- /altip_orig/lpm_shiftreg2.bsf: -------------------------------------------------------------------------------- 1 | /* 2 | WARNING: Do NOT edit the input and output ports in this file in a text 3 | editor if you plan to continue editing the block that represents it in 4 | the Block Editor! File corruption is VERY likely to occur. 5 | */ 6 | /* 7 | Copyright (C) 1991-2008 Altera Corporation 8 | Your use of Altera Corporation's design tools, logic functions 9 | and other software and tools, and its AMPP partner logic 10 | functions, and any output files from any of the foregoing 11 | (including device programming or simulation files), and any 12 | associated documentation or information are expressly subject 13 | to the terms and conditions of the Altera Program License 14 | Subscription Agreement, Altera MegaCore Function License 15 | Agreement, or other applicable license agreement, including, 16 | without limitation, that your use is for the sole purpose of 17 | programming logic devices manufactured by Altera and sold by 18 | Altera or its authorized distributors. Please refer to the 19 | applicable agreement for further details. 20 | */ 21 | (header "symbol" (version "1.1")) 22 | (symbol 23 | (rect 0 0 144 80) 24 | (text "lpm_shiftreg2" (rect 34 1 124 17)(font "Arial" (font_size 10))) 25 | (text "inst" (rect 8 64 25 76)(font "Arial" )) 26 | (port 27 | (pt 0 32) 28 | (input) 29 | (text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8))) 30 | (text "clock" (rect 26 26 49 39)(font "Arial" (font_size 8))) 31 | (line (pt 0 32)(pt 16 32)(line_width 1)) 32 | ) 33 | (port 34 | (pt 0 48) 35 | (input) 36 | (text "shiftin" (rect 0 0 34 14)(font "Arial" (font_size 8))) 37 | (text "shiftin" (rect 20 42 48 55)(font "Arial" (font_size 8))) 38 | (line (pt 0 48)(pt 16 48)(line_width 1)) 39 | ) 40 | (port 41 | (pt 144 48) 42 | (output) 43 | (text "shiftout" (rect 0 0 42 14)(font "Arial" (font_size 8))) 44 | (text "shiftout" (rect 89 42 123 55)(font "Arial" (font_size 8))) 45 | (line (pt 144 48)(pt 128 48)(line_width 1)) 46 | ) 47 | (drawing 48 | (text "right shift" (rect 88 17 128 29)(font "Arial" )) 49 | (line (pt 16 16)(pt 128 16)(line_width 1)) 50 | (line (pt 128 16)(pt 128 64)(line_width 1)) 51 | (line (pt 128 64)(pt 16 64)(line_width 1)) 52 | (line (pt 16 64)(pt 16 16)(line_width 1)) 53 | (line (pt 16 26)(pt 22 32)(line_width 1)) 54 | (line (pt 22 32)(pt 16 38)(line_width 1)) 55 | ) 56 | ) 57 | -------------------------------------------------------------------------------- /altip_orig/lpm_shiftreg2.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "LPM_SHIFTREG" 2 | set_global_assignment -name IP_TOOL_VERSION "8.1" 3 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_shiftreg2.vhd"] 4 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg2.bsf"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg2.cmp"] 6 | -------------------------------------------------------------------------------- /altip_orig/lpm_shiftreg3.bsf: -------------------------------------------------------------------------------- 1 | /* 2 | WARNING: Do NOT edit the input and output ports in this file in a text 3 | editor if you plan to continue editing the block that represents it in 4 | the Block Editor! File corruption is VERY likely to occur. 5 | */ 6 | /* 7 | Copyright (C) 1991-2008 Altera Corporation 8 | Your use of Altera Corporation's design tools, logic functions 9 | and other software and tools, and its AMPP partner logic 10 | functions, and any output files from any of the foregoing 11 | (including device programming or simulation files), and any 12 | associated documentation or information are expressly subject 13 | to the terms and conditions of the Altera Program License 14 | Subscription Agreement, Altera MegaCore Function License 15 | Agreement, or other applicable license agreement, including, 16 | without limitation, that your use is for the sole purpose of 17 | programming logic devices manufactured by Altera and sold by 18 | Altera or its authorized distributors. Please refer to the 19 | applicable agreement for further details. 20 | */ 21 | (header "symbol" (version "1.1")) 22 | (symbol 23 | (rect 0 0 144 80) 24 | (text "lpm_shiftreg3" (rect 34 1 124 17)(font "Arial" (font_size 10))) 25 | (text "inst" (rect 8 64 25 76)(font "Arial" )) 26 | (port 27 | (pt 0 32) 28 | (input) 29 | (text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8))) 30 | (text "clock" (rect 26 26 49 39)(font "Arial" (font_size 8))) 31 | (line (pt 0 32)(pt 16 32)(line_width 1)) 32 | ) 33 | (port 34 | (pt 0 48) 35 | (input) 36 | (text "shiftin" (rect 0 0 34 14)(font "Arial" (font_size 8))) 37 | (text "shiftin" (rect 20 42 48 55)(font "Arial" (font_size 8))) 38 | (line (pt 0 48)(pt 16 48)(line_width 1)) 39 | ) 40 | (port 41 | (pt 144 48) 42 | (output) 43 | (text "shiftout" (rect 0 0 42 14)(font "Arial" (font_size 8))) 44 | (text "shiftout" (rect 89 42 123 55)(font "Arial" (font_size 8))) 45 | (line (pt 144 48)(pt 128 48)(line_width 1)) 46 | ) 47 | (drawing 48 | (text "right shift" (rect 88 17 128 29)(font "Arial" )) 49 | (line (pt 16 16)(pt 128 16)(line_width 1)) 50 | (line (pt 128 16)(pt 128 64)(line_width 1)) 51 | (line (pt 128 64)(pt 16 64)(line_width 1)) 52 | (line (pt 16 64)(pt 16 16)(line_width 1)) 53 | (line (pt 16 26)(pt 22 32)(line_width 1)) 54 | (line (pt 22 32)(pt 16 38)(line_width 1)) 55 | ) 56 | ) 57 | -------------------------------------------------------------------------------- /altip_orig/lpm_shiftreg3.inc: -------------------------------------------------------------------------------- 1 | --Copyright (C) 1991-2008 Altera Corporation 2 | --Your use of Altera Corporation's design tools, logic functions 3 | --and other software and tools, and its AMPP partner logic 4 | --functions, and any output files from any of the foregoing 5 | --(including device programming or simulation files), and any 6 | --associated documentation or information are expressly subject 7 | --to the terms and conditions of the Altera Program License 8 | --Subscription Agreement, Altera MegaCore Function License 9 | --Agreement, or other applicable license agreement, including, 10 | --without limitation, that your use is for the sole purpose of 11 | --programming logic devices manufactured by Altera and sold by 12 | --Altera or its authorized distributors. Please refer to the 13 | --applicable agreement for further details. 14 | 15 | 16 | FUNCTION lpm_shiftreg3 17 | ( 18 | clock, 19 | shiftin 20 | ) 21 | 22 | RETURNS ( 23 | shiftout 24 | ); 25 | -------------------------------------------------------------------------------- /altip_orig/lpm_shiftreg3.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "LPM_SHIFTREG" 2 | set_global_assignment -name IP_TOOL_VERSION "8.1" 3 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_shiftreg3.vhd"] 4 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg3.bsf"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg3.inc"] 6 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg3.cmp"] 7 | -------------------------------------------------------------------------------- /altip_orig/lpm_shiftreg4.bsf: -------------------------------------------------------------------------------- 1 | /* 2 | WARNING: Do NOT edit the input and output ports in this file in a text 3 | editor if you plan to continue editing the block that represents it in 4 | the Block Editor! File corruption is VERY likely to occur. 5 | */ 6 | /* 7 | Copyright (C) 1991-2008 Altera Corporation 8 | Your use of Altera Corporation's design tools, logic functions 9 | and other software and tools, and its AMPP partner logic 10 | functions, and any output files from any of the foregoing 11 | (including device programming or simulation files), and any 12 | associated documentation or information are expressly subject 13 | to the terms and conditions of the Altera Program License 14 | Subscription Agreement, Altera MegaCore Function License 15 | Agreement, or other applicable license agreement, including, 16 | without limitation, that your use is for the sole purpose of 17 | programming logic devices manufactured by Altera and sold by 18 | Altera or its authorized distributors. Please refer to the 19 | applicable agreement for further details. 20 | */ 21 | (header "symbol" (version "1.1")) 22 | (symbol 23 | (rect 0 0 144 80) 24 | (text "lpm_shiftreg4" (rect 34 1 124 17)(font "Arial" (font_size 10))) 25 | (text "inst" (rect 8 64 25 76)(font "Arial" )) 26 | (port 27 | (pt 0 32) 28 | (input) 29 | (text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8))) 30 | (text "clock" (rect 26 26 49 39)(font "Arial" (font_size 8))) 31 | (line (pt 0 32)(pt 16 32)(line_width 1)) 32 | ) 33 | (port 34 | (pt 0 48) 35 | (input) 36 | (text "shiftin" (rect 0 0 34 14)(font "Arial" (font_size 8))) 37 | (text "shiftin" (rect 20 42 48 55)(font "Arial" (font_size 8))) 38 | (line (pt 0 48)(pt 16 48)(line_width 1)) 39 | ) 40 | (port 41 | (pt 144 48) 42 | (output) 43 | (text "shiftout" (rect 0 0 42 14)(font "Arial" (font_size 8))) 44 | (text "shiftout" (rect 89 42 123 55)(font "Arial" (font_size 8))) 45 | (line (pt 144 48)(pt 128 48)(line_width 1)) 46 | ) 47 | (drawing 48 | (text "right shift" (rect 88 17 128 29)(font "Arial" )) 49 | (line (pt 16 16)(pt 128 16)(line_width 1)) 50 | (line (pt 128 16)(pt 128 64)(line_width 1)) 51 | (line (pt 128 64)(pt 16 64)(line_width 1)) 52 | (line (pt 16 64)(pt 16 16)(line_width 1)) 53 | (line (pt 16 26)(pt 22 32)(line_width 1)) 54 | (line (pt 22 32)(pt 16 38)(line_width 1)) 55 | ) 56 | ) 57 | -------------------------------------------------------------------------------- /altip_orig/lpm_shiftreg4.inc: -------------------------------------------------------------------------------- 1 | --Copyright (C) 1991-2008 Altera Corporation 2 | --Your use of Altera Corporation's design tools, logic functions 3 | --and other software and tools, and its AMPP partner logic 4 | --functions, and any output files from any of the foregoing 5 | --(including device programming or simulation files), and any 6 | --associated documentation or information are expressly subject 7 | --to the terms and conditions of the Altera Program License 8 | --Subscription Agreement, Altera MegaCore Function License 9 | --Agreement, or other applicable license agreement, including, 10 | --without limitation, that your use is for the sole purpose of 11 | --programming logic devices manufactured by Altera and sold by 12 | --Altera or its authorized distributors. Please refer to the 13 | --applicable agreement for further details. 14 | 15 | 16 | FUNCTION lpm_shiftreg4 17 | ( 18 | clock, 19 | shiftin 20 | ) 21 | 22 | RETURNS ( 23 | shiftout 24 | ); 25 | -------------------------------------------------------------------------------- /altip_orig/lpm_shiftreg4.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "LPM_SHIFTREG" 2 | set_global_assignment -name IP_TOOL_VERSION "8.1" 3 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_shiftreg4.vhd"] 4 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg4.bsf"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg4.inc"] 6 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg4.cmp"] 7 | -------------------------------------------------------------------------------- /altip_orig/lpm_shiftreg5.bsf: -------------------------------------------------------------------------------- 1 | /* 2 | WARNING: Do NOT edit the input and output ports in this file in a text 3 | editor if you plan to continue editing the block that represents it in 4 | the Block Editor! File corruption is VERY likely to occur. 5 | */ 6 | /* 7 | Copyright (C) 1991-2008 Altera Corporation 8 | Your use of Altera Corporation's design tools, logic functions 9 | and other software and tools, and its AMPP partner logic 10 | functions, and any output files from any of the foregoing 11 | (including device programming or simulation files), and any 12 | associated documentation or information are expressly subject 13 | to the terms and conditions of the Altera Program License 14 | Subscription Agreement, Altera MegaCore Function License 15 | Agreement, or other applicable license agreement, including, 16 | without limitation, that your use is for the sole purpose of 17 | programming logic devices manufactured by Altera and sold by 18 | Altera or its authorized distributors. Please refer to the 19 | applicable agreement for further details. 20 | */ 21 | (header "symbol" (version "1.1")) 22 | (symbol 23 | (rect 0 0 144 80) 24 | (text "lpm_shiftreg5" (rect 34 1 124 17)(font "Arial" (font_size 10))) 25 | (text "inst" (rect 8 64 25 76)(font "Arial" )) 26 | (port 27 | (pt 0 32) 28 | (input) 29 | (text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8))) 30 | (text "clock" (rect 26 26 49 39)(font "Arial" (font_size 8))) 31 | (line (pt 0 32)(pt 16 32)(line_width 1)) 32 | ) 33 | (port 34 | (pt 0 48) 35 | (input) 36 | (text "shiftin" (rect 0 0 34 14)(font "Arial" (font_size 8))) 37 | (text "shiftin" (rect 20 42 48 55)(font "Arial" (font_size 8))) 38 | (line (pt 0 48)(pt 16 48)(line_width 1)) 39 | ) 40 | (port 41 | (pt 144 48) 42 | (output) 43 | (text "q[4..0]" (rect 0 0 35 14)(font "Arial" (font_size 8))) 44 | (text "q[4..0]" (rect 95 42 125 55)(font "Arial" (font_size 8))) 45 | (line (pt 144 48)(pt 128 48)(line_width 3)) 46 | ) 47 | (drawing 48 | (text "right shift" (rect 88 17 128 29)(font "Arial" )) 49 | (line (pt 16 16)(pt 128 16)(line_width 1)) 50 | (line (pt 128 16)(pt 128 64)(line_width 1)) 51 | (line (pt 128 64)(pt 16 64)(line_width 1)) 52 | (line (pt 16 64)(pt 16 16)(line_width 1)) 53 | (line (pt 16 26)(pt 22 32)(line_width 1)) 54 | (line (pt 22 32)(pt 16 38)(line_width 1)) 55 | ) 56 | ) 57 | -------------------------------------------------------------------------------- /altip_orig/lpm_shiftreg5.inc: -------------------------------------------------------------------------------- 1 | --Copyright (C) 1991-2008 Altera Corporation 2 | --Your use of Altera Corporation's design tools, logic functions 3 | --and other software and tools, and its AMPP partner logic 4 | --functions, and any output files from any of the foregoing 5 | --(including device programming or simulation files), and any 6 | --associated documentation or information are expressly subject 7 | --to the terms and conditions of the Altera Program License 8 | --Subscription Agreement, Altera MegaCore Function License 9 | --Agreement, or other applicable license agreement, including, 10 | --without limitation, that your use is for the sole purpose of 11 | --programming logic devices manufactured by Altera and sold by 12 | --Altera or its authorized distributors. Please refer to the 13 | --applicable agreement for further details. 14 | 15 | 16 | FUNCTION lpm_shiftreg5 17 | ( 18 | clock, 19 | shiftin 20 | ) 21 | 22 | RETURNS ( 23 | q[4..0] 24 | ); 25 | -------------------------------------------------------------------------------- /altip_orig/lpm_shiftreg5.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "LPM_SHIFTREG" 2 | set_global_assignment -name IP_TOOL_VERSION "8.1" 3 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_shiftreg5.vhd"] 4 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg5.bsf"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg5.inc"] 6 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg5.cmp"] 7 | -------------------------------------------------------------------------------- /altip_orig/lpm_shiftreg6.bsf: -------------------------------------------------------------------------------- 1 | /* 2 | WARNING: Do NOT edit the input and output ports in this file in a text 3 | editor if you plan to continue editing the block that represents it in 4 | the Block Editor! File corruption is VERY likely to occur. 5 | */ 6 | /* 7 | Copyright (C) 1991-2008 Altera Corporation 8 | Your use of Altera Corporation's design tools, logic functions 9 | and other software and tools, and its AMPP partner logic 10 | functions, and any output files from any of the foregoing 11 | (including device programming or simulation files), and any 12 | associated documentation or information are expressly subject 13 | to the terms and conditions of the Altera Program License 14 | Subscription Agreement, Altera MegaCore Function License 15 | Agreement, or other applicable license agreement, including, 16 | without limitation, that your use is for the sole purpose of 17 | programming logic devices manufactured by Altera and sold by 18 | Altera or its authorized distributors. Please refer to the 19 | applicable agreement for further details. 20 | */ 21 | (header "symbol" (version "1.1")) 22 | (symbol 23 | (rect 0 0 144 80) 24 | (text "lpm_shiftreg6" (rect 34 1 124 17)(font "Arial" (font_size 10))) 25 | (text "inst" (rect 8 64 25 76)(font "Arial" )) 26 | (port 27 | (pt 0 32) 28 | (input) 29 | (text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8))) 30 | (text "clock" (rect 26 26 49 39)(font "Arial" (font_size 8))) 31 | (line (pt 0 32)(pt 16 32)(line_width 1)) 32 | ) 33 | (port 34 | (pt 0 48) 35 | (input) 36 | (text "shiftin" (rect 0 0 34 14)(font "Arial" (font_size 8))) 37 | (text "shiftin" (rect 20 42 48 55)(font "Arial" (font_size 8))) 38 | (line (pt 0 48)(pt 16 48)(line_width 1)) 39 | ) 40 | (port 41 | (pt 144 48) 42 | (output) 43 | (text "q[4..0]" (rect 0 0 35 14)(font "Arial" (font_size 8))) 44 | (text "q[4..0]" (rect 95 42 125 55)(font "Arial" (font_size 8))) 45 | (line (pt 144 48)(pt 128 48)(line_width 3)) 46 | ) 47 | (drawing 48 | (text "right shift" (rect 88 17 128 29)(font "Arial" )) 49 | (line (pt 16 16)(pt 128 16)(line_width 1)) 50 | (line (pt 128 16)(pt 128 64)(line_width 1)) 51 | (line (pt 128 64)(pt 16 64)(line_width 1)) 52 | (line (pt 16 64)(pt 16 16)(line_width 1)) 53 | (line (pt 16 26)(pt 22 32)(line_width 1)) 54 | (line (pt 22 32)(pt 16 38)(line_width 1)) 55 | ) 56 | ) 57 | -------------------------------------------------------------------------------- /altip_orig/lpm_shiftreg6.inc: -------------------------------------------------------------------------------- 1 | --Copyright (C) 1991-2008 Altera Corporation 2 | --Your use of Altera Corporation's design tools, logic functions 3 | --and other software and tools, and its AMPP partner logic 4 | --functions, and any output files from any of the foregoing 5 | --(including device programming or simulation files), and any 6 | --associated documentation or information are expressly subject 7 | --to the terms and conditions of the Altera Program License 8 | --Subscription Agreement, Altera MegaCore Function License 9 | --Agreement, or other applicable license agreement, including, 10 | --without limitation, that your use is for the sole purpose of 11 | --programming logic devices manufactured by Altera and sold by 12 | --Altera or its authorized distributors. Please refer to the 13 | --applicable agreement for further details. 14 | 15 | 16 | FUNCTION lpm_shiftreg6 17 | ( 18 | clock, 19 | shiftin 20 | ) 21 | 22 | RETURNS ( 23 | q[4..0] 24 | ); 25 | -------------------------------------------------------------------------------- /altip_orig/lpm_shiftreg6.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "LPM_SHIFTREG" 2 | set_global_assignment -name IP_TOOL_VERSION "8.1" 3 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_shiftreg6.vhd"] 4 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg6.bsf"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg6.inc"] 6 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg6.cmp"] 7 | -------------------------------------------------------------------------------- /altip_orig/root/altddio_out0.inc: -------------------------------------------------------------------------------- 1 | --Copyright (C) 1991-2008 Altera Corporation 2 | --Your use of Altera Corporation's design tools, logic functions 3 | --and other software and tools, and its AMPP partner logic 4 | --functions, and any output files from any of the foregoing 5 | --(including device programming or simulation files), and any 6 | --associated documentation or information are expressly subject 7 | --to the terms and conditions of the Altera Program License 8 | --Subscription Agreement, Altera MegaCore Function License 9 | --Agreement, or other applicable license agreement, including, 10 | --without limitation, that your use is for the sole purpose of 11 | --programming logic devices manufactured by Altera and sold by 12 | --Altera or its authorized distributors. Please refer to the 13 | --applicable agreement for further details. 14 | 15 | 16 | FUNCTION altddio_out0 17 | ( 18 | datain_h[3..0], 19 | datain_l[3..0], 20 | outclock 21 | ) 22 | 23 | RETURNS ( 24 | dataout[3..0] 25 | ); 26 | -------------------------------------------------------------------------------- /altip_orig/root/altddio_out0.ppf: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | -------------------------------------------------------------------------------- /altip_orig/root/altddio_out0.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "ALTDDIO_OUT" 2 | set_global_assignment -name IP_TOOL_VERSION "8.1" 3 | set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altddio_out0.vhd"] 4 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out0.bsf"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out0.inc"] 6 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out0.cmp"] 7 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out0.ppf"] 8 | -------------------------------------------------------------------------------- /altpll1.qip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Torlus/firebee-fpga/d07ee9b14405b2e00bd1d6589a1991cc32c86d0b/altpll1.qip -------------------------------------------------------------------------------- /altpll4.qip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Torlus/firebee-fpga/d07ee9b14405b2e00bd1d6589a1991cc32c86d0b/altpll4.qip -------------------------------------------------------------------------------- /dcfifo0.qip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Torlus/firebee-fpga/d07ee9b14405b2e00bd1d6589a1991cc32c86d0b/dcfifo0.qip -------------------------------------------------------------------------------- /firebee1.qpf: -------------------------------------------------------------------------------- 1 | # -------------------------------------------------------------------------- # 2 | # 3 | # Copyright (C) 1991-2013 Altera Corporation 4 | # Your use of Altera Corporation's design tools, logic functions 5 | # and other software and tools, and its AMPP partner logic 6 | # functions, and any output files from any of the foregoing 7 | # (including device programming or simulation files), and any 8 | # associated documentation or information are expressly subject 9 | # to the terms and conditions of the Altera Program License 10 | # Subscription Agreement, Altera MegaCore Function License 11 | # Agreement, or other applicable license agreement, including, 12 | # without limitation, that your use is for the sole purpose of 13 | # programming logic devices manufactured by Altera and sold by 14 | # Altera or its authorized distributors. Please refer to the 15 | # applicable agreement for further details. 16 | # 17 | # -------------------------------------------------------------------------- # 18 | # 19 | # Quartus II 32-bit 20 | # Version 13.1.0 Build 162 10/23/2013 SJ Web Edition 21 | # Date created = 01:26:07 March 01, 2014 22 | # 23 | # -------------------------------------------------------------------------- # 24 | 25 | QUARTUS_VERSION = "13.1" 26 | DATE = "01:26:07 March 01, 2014" 27 | 28 | # Revisions 29 | 30 | PROJECT_REVISION = "firebee1" 31 | -------------------------------------------------------------------------------- /firebee1.rbf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Torlus/firebee-fpga/d07ee9b14405b2e00bd1d6589a1991cc32c86d0b/firebee1.rbf -------------------------------------------------------------------------------- /firebee1.sof: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Torlus/firebee-fpga/d07ee9b14405b2e00bd1d6589a1991cc32c86d0b/firebee1.sof -------------------------------------------------------------------------------- /lpm_bustri2.bsf: -------------------------------------------------------------------------------- 1 | /* 2 | WARNING: Do NOT edit the input and output ports in this file in a text 3 | editor if you plan to continue editing the block that represents it in 4 | the Block Editor! File corruption is VERY likely to occur. 5 | */ 6 | /* 7 | Copyright (C) 1991-2008 Altera Corporation 8 | Your use of Altera Corporation's design tools, logic functions 9 | and other software and tools, and its AMPP partner logic 10 | functions, and any output files from any of the foregoing 11 | (including device programming or simulation files), and any 12 | associated documentation or information are expressly subject 13 | to the terms and conditions of the Altera Program License 14 | Subscription Agreement, Altera MegaCore Function License 15 | Agreement, or other applicable license agreement, including, 16 | without limitation, that your use is for the sole purpose of 17 | programming logic devices manufactured by Altera and sold by 18 | Altera or its authorized distributors. Please refer to the 19 | applicable agreement for further details. 20 | */ 21 | (header "symbol" (version "1.1")) 22 | (symbol 23 | (rect 0 0 80 40) 24 | (text "lpm_bustri2" (rect 7 1 86 17)(font "Arial" (font_size 10))) 25 | (text "inst" (rect 8 24 25 36)(font "Arial" )) 26 | (port 27 | (pt 40 40) 28 | (input) 29 | (text "enabledt" (rect 0 0 48 14)(font "Arial" (font_size 8))) 30 | (text "enabledt" (rect 40 -6 53 36)(font "Arial" (font_size 8))(invisible)) 31 | (line (pt 40 40)(pt 40 28)(line_width 1)) 32 | ) 33 | (port 34 | (pt 0 24) 35 | (input) 36 | (text "data[17..0]" (rect 0 0 60 14)(font "Arial" (font_size 8))) 37 | (text "data[17..0]" (rect -3 -27 10 24)(font "Arial" (font_size 8))(invisible)) 38 | (line (pt 0 24)(pt 32 24)(line_width 3)) 39 | ) 40 | (port 41 | (pt 80 24) 42 | (bidir) 43 | (text "tridata[17..0]" (rect 0 0 70 14)(font "Arial" (font_size 8))) 44 | (text "tridata[17..0]" (rect 84 -36 97 24)(font "Arial" (font_size 8))(invisible)) 45 | (line (pt 80 24)(pt 48 24)(line_width 3)) 46 | ) 47 | (drawing 48 | (text "18" (rect 61 25 71 37)(font "Arial" )) 49 | (text "18" (rect 13 25 23 37)(font "Arial" )) 50 | (line (pt 32 16)(pt 48 24)(line_width 1)) 51 | (line (pt 48 24)(pt 32 32)(line_width 1)) 52 | (line (pt 32 32)(pt 32 16)(line_width 1)) 53 | (line (pt 56 28)(pt 64 20)(line_width 1)) 54 | (line (pt 8 28)(pt 16 20)(line_width 1)) 55 | ) 56 | ) 57 | -------------------------------------------------------------------------------- /mkS19.bat: -------------------------------------------------------------------------------- 1 | %QUARTUS_ROOTDIR%\bin\quartus_cpf.exe -c firebee1.sof firebee1.rbf 2 | objcopy -I binary -O srec --change-addresses 0xe0700000 firebee1.rbf fpga.s19 3 | -------------------------------------------------------------------------------- /mux41.v: -------------------------------------------------------------------------------- 1 | // Copyright (C) 1991-2009 Altera Corporation 2 | // Your use of Altera Corporation's design tools, logic functions 3 | // and other software and tools, and its AMPP partner logic 4 | // functions, and any output files from any of the foregoing 5 | // (including device programming or simulation files), and any 6 | // associated documentation or information are expressly subject 7 | // to the terms and conditions of the Altera Program License 8 | // Subscription Agreement, Altera MegaCore Function License 9 | // Agreement, or other applicable license agreement, including, 10 | // without limitation, that your use is for the sole purpose of 11 | // programming logic devices manufactured by Altera and sold by 12 | // Altera or its authorized distributors. Please refer to the 13 | // applicable agreement for further details. 14 | 15 | // PROGRAM "Quartus II 64-Bit" 16 | // VERSION "Version 9.1 Build 222 10/21/2009 SJ Full Version" 17 | // CREATED "Sat Mar 01 09:17:14 2014" 18 | 19 | module mux41( 20 | S0, 21 | D2, 22 | INH, 23 | D0, 24 | D1, 25 | D3, 26 | S1, 27 | Q 28 | ); 29 | 30 | 31 | input S0; 32 | input D2; 33 | input INH; 34 | input D0; 35 | input D1; 36 | input D3; 37 | input S1; 38 | output Q; 39 | 40 | wire SYNTHESIZED_WIRE_18; 41 | wire SYNTHESIZED_WIRE_19; 42 | wire SYNTHESIZED_WIRE_20; 43 | wire SYNTHESIZED_WIRE_21; 44 | wire SYNTHESIZED_WIRE_22; 45 | wire SYNTHESIZED_WIRE_13; 46 | wire SYNTHESIZED_WIRE_14; 47 | wire SYNTHESIZED_WIRE_15; 48 | wire SYNTHESIZED_WIRE_16; 49 | 50 | 51 | 52 | 53 | assign SYNTHESIZED_WIRE_18 = ~S0; 54 | 55 | assign SYNTHESIZED_WIRE_21 = ~SYNTHESIZED_WIRE_18; 56 | 57 | assign SYNTHESIZED_WIRE_13 = SYNTHESIZED_WIRE_19 & SYNTHESIZED_WIRE_20 & SYNTHESIZED_WIRE_18 & D0; 58 | 59 | assign SYNTHESIZED_WIRE_14 = SYNTHESIZED_WIRE_19 & SYNTHESIZED_WIRE_20 & SYNTHESIZED_WIRE_21 & D1; 60 | 61 | assign SYNTHESIZED_WIRE_15 = SYNTHESIZED_WIRE_19 & SYNTHESIZED_WIRE_22 & SYNTHESIZED_WIRE_18 & D2; 62 | 63 | assign SYNTHESIZED_WIRE_16 = SYNTHESIZED_WIRE_19 & SYNTHESIZED_WIRE_22 & SYNTHESIZED_WIRE_21 & D3; 64 | 65 | assign Q = SYNTHESIZED_WIRE_13 | SYNTHESIZED_WIRE_14 | SYNTHESIZED_WIRE_15 | SYNTHESIZED_WIRE_16; 66 | 67 | assign SYNTHESIZED_WIRE_19 = ~INH; 68 | 69 | assign SYNTHESIZED_WIRE_20 = ~S1; 70 | 71 | assign SYNTHESIZED_WIRE_22 = ~SYNTHESIZED_WIRE_20; 72 | 73 | 74 | endmodule 75 | -------------------------------------------------------------------------------- /objcopy.exe: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Torlus/firebee-fpga/d07ee9b14405b2e00bd1d6589a1991cc32c86d0b/objcopy.exe --------------------------------------------------------------------------------