├── .gitignore ├── LICENSE.md ├── Project_1 ├── Appendix.md ├── assemble_code_exp.txt ├── code.txt ├── control │ └── ctrl.v ├── datapath │ ├── alu.v │ ├── dm.v │ ├── ext.v │ ├── im.v │ ├── mux.v │ ├── npc.v │ ├── pc.v │ └── rf.v ├── mips.v └── testbench.v ├── Project_2_OC ├── ALUOnBoard │ ├── ALUOnBoard.gise │ ├── ALUOnBoard.xise │ ├── _ngo │ │ └── netlist.lst │ ├── _xmsgs │ │ ├── bitgen.xmsgs │ │ ├── map.xmsgs │ │ ├── ngdbuild.xmsgs │ │ ├── par.xmsgs │ │ ├── pn_parser.xmsgs │ │ ├── trce.xmsgs │ │ └── xst.xmsgs │ ├── adder.v │ ├── alu.ucf │ ├── alu.v │ ├── alu_display.bgn │ ├── alu_display.bit │ ├── alu_display.bld │ ├── alu_display.cmd_log │ ├── alu_display.drc │ ├── alu_display.lso │ ├── alu_display.ncd │ ├── alu_display.ngc │ ├── alu_display.ngd │ ├── alu_display.ngr │ ├── alu_display.pad │ ├── alu_display.par │ ├── alu_display.pcf │ ├── alu_display.prj │ ├── alu_display.ptwx │ ├── alu_display.stx │ ├── alu_display.syr │ ├── alu_display.twr │ ├── alu_display.twx │ ├── alu_display.unroutes │ ├── alu_display.ut │ ├── alu_display.v │ ├── alu_display.xpi │ ├── alu_display.xst │ ├── alu_display_bitgen.xwbt │ ├── alu_display_envsettings.html │ ├── alu_display_guide.ncd │ ├── alu_display_map.map │ ├── alu_display_map.mrp │ ├── alu_display_map.ncd │ ├── alu_display_map.ngm │ ├── alu_display_map.xrpt │ ├── alu_display_ngdbuild.xrpt │ ├── alu_display_pad.csv │ ├── alu_display_pad.txt │ ├── alu_display_par.xrpt │ ├── alu_display_summary.html │ ├── alu_display_summary.xml │ ├── alu_display_usage.xml │ ├── alu_display_xst.xrpt │ ├── iseconfig │ │ ├── ALUOnBoard.projectmgr │ │ └── alu_display.xreport │ ├── lcd_module.ngc │ ├── lcd_module.v │ ├── lcd_rom.ngc │ ├── par_usage_statistics.html │ ├── webtalk.log │ ├── webtalk_pn.xml │ ├── xlnx_auto_0_xdb │ │ └── cst.xbcd │ └── xst │ │ └── work │ │ ├── work.sdbl │ │ └── work.sdbx ├── MemoryOnBoard │ ├── MemoryOnBoard.gise │ ├── MemoryOnBoard.xise │ ├── _ngo │ │ └── netlist.lst │ ├── _xmsgs │ │ ├── bitgen.xmsgs │ │ ├── map.xmsgs │ │ ├── ngdbuild.xmsgs │ │ ├── par.xmsgs │ │ ├── pn_parser.xmsgs │ │ ├── trce.xmsgs │ │ └── xst.xmsgs │ ├── data_mem.ucf │ ├── data_ram.ngc │ ├── data_ram.sym │ ├── data_ram.v │ ├── data_ram_display.bgn │ ├── data_ram_display.bit │ ├── data_ram_display.bld │ ├── data_ram_display.cmd_log │ ├── data_ram_display.drc │ ├── data_ram_display.lso │ ├── data_ram_display.ncd │ ├── data_ram_display.ngc │ ├── data_ram_display.ngd │ ├── data_ram_display.ngr │ ├── data_ram_display.pad │ ├── data_ram_display.par │ ├── data_ram_display.pcf │ ├── data_ram_display.prj │ ├── data_ram_display.ptwx │ ├── data_ram_display.stx │ ├── data_ram_display.syr │ ├── data_ram_display.twr │ ├── data_ram_display.twx │ ├── data_ram_display.unroutes │ ├── data_ram_display.ut │ ├── data_ram_display.v │ ├── data_ram_display.xpi │ ├── data_ram_display.xst │ ├── data_ram_display_bitgen.xwbt │ ├── data_ram_display_envsettings.html │ ├── data_ram_display_guide.ncd │ ├── data_ram_display_map.map │ ├── data_ram_display_map.mrp │ ├── data_ram_display_map.ncd │ ├── data_ram_display_map.ngm │ ├── data_ram_display_map.xrpt │ ├── data_ram_display_ngdbuild.xrpt │ ├── data_ram_display_pad.csv │ ├── data_ram_display_pad.txt │ ├── data_ram_display_par.xrpt │ ├── data_ram_display_summary.html │ ├── data_ram_display_summary.xml │ ├── data_ram_display_usage.xml │ ├── data_ram_display_xst.xrpt │ ├── data_ram_summary.html │ ├── ipcore_dir │ │ ├── _xmsgs │ │ │ ├── cg.xmsgs │ │ │ └── pn_parser.xmsgs │ │ ├── blk_mem_gen_readme.txt │ │ ├── coregen.cgp │ │ ├── coregen.log │ │ ├── create_data_ram.tcl │ │ ├── data_ram.asy │ │ ├── data_ram.gise │ │ ├── data_ram.ncf │ │ ├── data_ram.ngc │ │ ├── data_ram.sym │ │ ├── data_ram.v │ │ ├── data_ram.veo │ │ ├── data_ram.xco │ │ ├── data_ram.xise │ │ ├── data_ram │ │ │ └── doc │ │ │ │ └── blk_mem_gen_v6_1_vinfo.html │ │ ├── data_ram_flist.txt │ │ ├── data_ram_xmdf.tcl │ │ ├── edit_data_ram.tcl │ │ └── tmp │ │ │ ├── _cg │ │ │ └── _dbg │ │ │ │ ├── xil_996.in │ │ │ │ └── xil_996.out │ │ │ ├── _xmsgs │ │ │ ├── ngcbuild.xmsgs │ │ │ ├── pn_parser.xmsgs │ │ │ └── xst.xmsgs │ │ │ └── data_ram.lso │ ├── iseconfig │ │ ├── MemoryOnBoard.projectmgr │ │ ├── data_ram.xreport │ │ └── data_ram_display.xreport │ ├── lcd_module.ngc │ ├── lcd_module.v │ ├── lcd_rom.ngc │ ├── par_usage_statistics.html │ ├── webtalk.log │ ├── webtalk_pn.xml │ ├── xlnx_auto_0_xdb │ │ └── cst.xbcd │ └── xst │ │ └── work │ │ ├── work.sdbl │ │ └── work.sdbx ├── RegisterFileOnBoard │ ├── RegisterFileOnBoard.gise │ ├── RegisterFileOnBoard.xise │ ├── _ngo │ │ └── netlist.lst │ ├── _xmsgs │ │ ├── bitgen.xmsgs │ │ ├── map.xmsgs │ │ ├── ngdbuild.xmsgs │ │ ├── par.xmsgs │ │ ├── pn_parser.xmsgs │ │ ├── trce.xmsgs │ │ └── xst.xmsgs │ ├── iseconfig │ │ ├── RegisterFileOnBoard.projectmgr │ │ ├── regfile.xreport │ │ └── regfile_display.xreport │ ├── lcd_module.ngc │ ├── lcd_module.v │ ├── lcd_rom.ngc │ ├── par_usage_statistics.html │ ├── regfile.ucf │ ├── regfile.v │ ├── regfile_display.bgn │ ├── regfile_display.bit │ ├── regfile_display.bld │ ├── regfile_display.cmd_log │ ├── regfile_display.cpj │ ├── regfile_display.drc │ ├── regfile_display.lso │ ├── regfile_display.ncd │ ├── regfile_display.ngc │ ├── regfile_display.ngd │ ├── regfile_display.ngr │ ├── regfile_display.pad │ ├── regfile_display.par │ ├── regfile_display.pcf │ ├── regfile_display.prj │ ├── regfile_display.ptwx │ ├── regfile_display.stx │ ├── regfile_display.syr │ ├── regfile_display.twr │ ├── regfile_display.twx │ ├── regfile_display.unroutes │ ├── regfile_display.ut │ ├── regfile_display.v │ ├── regfile_display.xpi │ ├── regfile_display.xst │ ├── regfile_display_bitgen.xwbt │ ├── regfile_display_envsettings.html │ ├── regfile_display_guide.ncd │ ├── regfile_display_map.map │ ├── regfile_display_map.mrp │ ├── regfile_display_map.ncd │ ├── regfile_display_map.ngm │ ├── regfile_display_map.xrpt │ ├── regfile_display_ngdbuild.xrpt │ ├── regfile_display_pad.csv │ ├── regfile_display_pad.txt │ ├── regfile_display_par.xrpt │ ├── regfile_display_summary.html │ ├── regfile_display_summary.xml │ ├── regfile_display_usage.xml │ ├── regfile_display_xst.xrpt │ ├── regfile_summary.html │ ├── webtalk.log │ ├── webtalk_pn.xml │ ├── xlnx_auto_0_xdb │ │ └── cst.xbcd │ └── xst │ │ └── work │ │ ├── work.sdbl │ │ └── work.sdbx ├── SingleCycleCPUOnBoard │ ├── SingleCycleCPUOnBoard.gise │ ├── SingleCycleCPUOnBoard.xise │ ├── _ngo │ │ └── netlist.lst │ ├── _xmsgs │ │ ├── bitgen.xmsgs │ │ ├── map.xmsgs │ │ ├── ngdbuild.xmsgs │ │ ├── par.xmsgs │ │ ├── pn_parser.xmsgs │ │ ├── trce.xmsgs │ │ └── xst.xmsgs │ ├── adder.v │ ├── alu.v │ ├── data_ram.v │ ├── inst_rom.v │ ├── iseconfig │ │ ├── SingleCycleCPUOnBoard.projectmgr │ │ └── single_cycle_cpu_display.xreport │ ├── lcd_module.ngc │ ├── lcd_module.v │ ├── lcd_rom.ngc │ ├── par_usage_statistics.html │ ├── regfile.v │ ├── single_cycle_cpu.ucf │ ├── single_cycle_cpu.v │ ├── single_cycle_cpu_display.bgn │ ├── single_cycle_cpu_display.bit │ ├── single_cycle_cpu_display.bld │ ├── single_cycle_cpu_display.cmd_log │ ├── single_cycle_cpu_display.drc │ ├── single_cycle_cpu_display.lso │ ├── single_cycle_cpu_display.ncd │ ├── single_cycle_cpu_display.ngc │ ├── single_cycle_cpu_display.ngd │ ├── single_cycle_cpu_display.ngr │ ├── single_cycle_cpu_display.pad │ ├── single_cycle_cpu_display.par │ ├── single_cycle_cpu_display.pcf │ ├── single_cycle_cpu_display.prj │ ├── single_cycle_cpu_display.ptwx │ ├── single_cycle_cpu_display.stx │ ├── single_cycle_cpu_display.syr │ ├── single_cycle_cpu_display.twr │ ├── single_cycle_cpu_display.twx │ ├── single_cycle_cpu_display.unroutes │ ├── single_cycle_cpu_display.ut │ ├── single_cycle_cpu_display.v │ ├── single_cycle_cpu_display.xpi │ ├── single_cycle_cpu_display.xst │ ├── single_cycle_cpu_display_bitgen.xwbt │ ├── single_cycle_cpu_display_envsettings.html │ ├── single_cycle_cpu_display_guide.ncd │ ├── single_cycle_cpu_display_map.map │ ├── single_cycle_cpu_display_map.mrp │ ├── single_cycle_cpu_display_map.ncd │ ├── single_cycle_cpu_display_map.ngm │ ├── single_cycle_cpu_display_map.xrpt │ ├── single_cycle_cpu_display_ngdbuild.xrpt │ ├── single_cycle_cpu_display_pad.csv │ ├── single_cycle_cpu_display_pad.txt │ ├── single_cycle_cpu_display_par.xrpt │ ├── single_cycle_cpu_display_summary.html │ ├── single_cycle_cpu_display_summary.xml │ ├── single_cycle_cpu_display_usage.xml │ ├── single_cycle_cpu_display_xst.xrpt │ ├── tb.v │ ├── webtalk.log │ ├── webtalk_pn.xml │ ├── xlnx_auto_0_xdb │ │ └── cst.xbcd │ └── xst │ │ └── work │ │ ├── work.sdbl │ │ └── work.sdbx ├── TestProject │ ├── TestProject.gise │ ├── TestProject.xise │ ├── _ngo │ │ └── netlist.lst │ ├── _xmsgs │ │ ├── bitgen.xmsgs │ │ ├── map.xmsgs │ │ ├── ngdbuild.xmsgs │ │ ├── par.xmsgs │ │ ├── pn_parser.xmsgs │ │ ├── trce.xmsgs │ │ └── xst.xmsgs │ ├── adder.ucf │ ├── adder.v │ ├── adder_display.bgn │ ├── adder_display.bit │ ├── adder_display.bld │ ├── adder_display.cmd_log │ ├── adder_display.cpj │ ├── adder_display.drc │ ├── adder_display.lso │ ├── adder_display.ncd │ ├── adder_display.ngc │ ├── adder_display.ngd │ ├── adder_display.ngr │ ├── adder_display.pad │ ├── adder_display.par │ ├── adder_display.pcf │ ├── adder_display.prj │ ├── adder_display.ptwx │ ├── adder_display.stx │ ├── adder_display.syr │ ├── adder_display.twr │ ├── adder_display.twx │ ├── adder_display.unroutes │ ├── adder_display.ut │ ├── adder_display.v │ ├── adder_display.xpi │ ├── adder_display.xst │ ├── adder_display_bitgen.xwbt │ ├── adder_display_envsettings.html │ ├── adder_display_guide.ncd │ ├── adder_display_map.map │ ├── adder_display_map.mrp │ ├── adder_display_map.ncd │ ├── adder_display_map.ngm │ ├── adder_display_map.xrpt │ ├── adder_display_ngdbuild.xrpt │ ├── adder_display_pad.csv │ ├── adder_display_pad.txt │ ├── adder_display_par.xrpt │ ├── adder_display_summary.html │ ├── adder_display_summary.xml │ ├── adder_display_usage.xml │ ├── adder_display_xst.xrpt │ ├── adder_summary.html │ ├── fuse.log │ ├── fuse.xmsgs │ ├── fuseRelaunch.cmd │ ├── iseconfig │ │ ├── TestProject.projectmgr │ │ ├── adder_display.xreport │ │ └── mux4_1.xreport │ ├── isim.cmd │ ├── isim.log │ ├── isim │ │ ├── isim_usage_statistics.html │ │ ├── pn_info │ │ ├── temp │ │ │ ├── adder.sdb │ │ │ ├── glbl.sdb │ │ │ └── testbench.sdb │ │ ├── testbench_isim_beh.exe.sim │ │ │ ├── ISimEngine-DesignHierarchy.dbg │ │ │ ├── isimcrash.log │ │ │ ├── isimkernel.log │ │ │ ├── libPortability.dll │ │ │ ├── netId.dat │ │ │ ├── testbench_isim_beh.exe │ │ │ ├── tmp_save │ │ │ │ └── _1 │ │ │ └── work │ │ │ │ ├── m_00000000002451488663_1949178628.c │ │ │ │ ├── m_00000000002451488663_1949178628.didat │ │ │ │ ├── m_00000000002451488663_1949178628.nt64.obj │ │ │ │ ├── m_00000000003717066445_0833183191.c │ │ │ │ ├── m_00000000003717066445_0833183191.didat │ │ │ │ ├── m_00000000003717066445_0833183191.nt64.obj │ │ │ │ ├── m_00000000004093713498_2073120511.c │ │ │ │ ├── m_00000000004093713498_2073120511.didat │ │ │ │ ├── m_00000000004093713498_2073120511.nt64.obj │ │ │ │ ├── testbench_isim_beh.exe_main.c │ │ │ │ └── testbench_isim_beh.exe_main.nt64.obj │ │ └── work │ │ │ ├── adder.sdb │ │ │ ├── glbl.sdb │ │ │ └── testbench.sdb │ ├── lcd_module.ngc │ ├── lcd_module.v │ ├── lcd_rom.ngc │ ├── mux4_1.ucf │ ├── mux4_1.v │ ├── mux4_1_summary.html │ ├── par_usage_statistics.html │ ├── testbench.cmd_log │ ├── testbench.lso │ ├── testbench.prj │ ├── testbench.stx │ ├── testbench.tfi │ ├── testbench.v │ ├── testbench.xst │ ├── testbench_beh.prj │ ├── testbench_isim_beh.exe │ ├── testbench_isim_beh.wdb │ ├── testbench_stx_beh.prj │ ├── webtalk.log │ ├── webtalk_pn.xml │ ├── xilinxsim.ini │ ├── xlnx_auto_0_xdb │ │ └── cst.xbcd │ └── xst │ │ └── work │ │ ├── work.sdbl │ │ └── work.sdbx ├── adder.v ├── alu.v └── rf.v ├── Project_Assignment ├── Appendix.md ├── code.txt ├── code_exp.txt ├── control │ └── ctrl.v ├── datapath │ ├── CoProcessor0RF.v │ ├── alu.v │ ├── comp.v │ ├── dm.v │ ├── ext.v │ ├── im.v │ ├── mux.v │ ├── npc.v │ ├── pc.v │ └── rf.v ├── mips.v └── testbench.v ├── Project_Assignment_OnBoard ├── CoProcessor0RF.v ├── _ngo │ └── netlist.lst ├── _xmsgs │ ├── bitgen.xmsgs │ ├── map.xmsgs │ ├── ngdbuild.xmsgs │ ├── par.xmsgs │ ├── pn_parser.xmsgs │ ├── trce.xmsgs │ └── xst.xmsgs ├── adder.v ├── alu.v ├── code.txt ├── comp.v ├── ctrl.v ├── data_ram.v ├── dm.v ├── ext.v ├── im.v ├── inst_rom.v ├── iseconfig │ ├── mips_display.xreport │ ├── single_cycle_cpu.projectmgr │ └── single_cycle_cpu_display.xreport ├── lcd_module.ngc ├── lcd_module.v ├── lcd_rom.ngc ├── mips.v ├── mips_display.bgn ├── mips_display.bit ├── mips_display.bld ├── mips_display.cmd_log ├── mips_display.drc ├── mips_display.lso ├── mips_display.ncd ├── mips_display.ngc ├── mips_display.ngd ├── mips_display.ngr ├── mips_display.pad ├── mips_display.par ├── mips_display.pcf ├── mips_display.prj ├── mips_display.ptwx ├── mips_display.stx ├── mips_display.syr ├── mips_display.twr ├── mips_display.twx ├── mips_display.unroutes ├── mips_display.ut ├── mips_display.xpi ├── mips_display.xst ├── mips_display_bitgen.xwbt ├── mips_display_envsettings.html ├── mips_display_guide.ncd ├── mips_display_map.map ├── mips_display_map.mrp ├── mips_display_map.ncd ├── mips_display_map.ngm ├── mips_display_map.xrpt ├── mips_display_ngdbuild.xrpt ├── mips_display_pad.csv ├── mips_display_pad.txt ├── mips_display_par.xrpt ├── mips_display_summary.html ├── mips_display_summary.xml ├── mips_display_usage.xml ├── mips_display_xst.xrpt ├── mux.v ├── npc.v ├── par_usage_statistics.html ├── pc.v ├── regfile.v ├── rf.v ├── single_cycle_cpu.gise ├── single_cycle_cpu.ucf ├── single_cycle_cpu.v ├── single_cycle_cpu.xise ├── single_cycle_cpu_display.bgn ├── single_cycle_cpu_display.bit ├── single_cycle_cpu_display.bld ├── single_cycle_cpu_display.cmd_log ├── single_cycle_cpu_display.drc ├── single_cycle_cpu_display.lso ├── single_cycle_cpu_display.ncd ├── single_cycle_cpu_display.ngc ├── single_cycle_cpu_display.ngd ├── single_cycle_cpu_display.ngr ├── single_cycle_cpu_display.pad ├── single_cycle_cpu_display.par ├── single_cycle_cpu_display.pcf ├── single_cycle_cpu_display.prj ├── single_cycle_cpu_display.ptwx ├── single_cycle_cpu_display.stx ├── single_cycle_cpu_display.syr ├── single_cycle_cpu_display.twr ├── single_cycle_cpu_display.twx ├── single_cycle_cpu_display.unroutes ├── single_cycle_cpu_display.ut ├── single_cycle_cpu_display.v ├── single_cycle_cpu_display.xpi ├── single_cycle_cpu_display.xst ├── single_cycle_cpu_display_bitgen.xwbt ├── single_cycle_cpu_display_envsettings.html ├── single_cycle_cpu_display_guide.ncd ├── single_cycle_cpu_display_map.map ├── single_cycle_cpu_display_map.mrp ├── single_cycle_cpu_display_map.ncd ├── single_cycle_cpu_display_map.ngm ├── single_cycle_cpu_display_map.xrpt ├── single_cycle_cpu_display_ngdbuild.xrpt ├── single_cycle_cpu_display_pad.csv ├── single_cycle_cpu_display_pad.txt ├── single_cycle_cpu_display_par.xrpt ├── single_cycle_cpu_display_summary.html ├── single_cycle_cpu_display_summary.xml ├── single_cycle_cpu_display_usage.xml ├── single_cycle_cpu_display_xst.xrpt ├── tb.v ├── usage_statistics_webtalk.html ├── webtalk.log ├── webtalk_pn.xml ├── xlnx_auto_0_xdb │ └── cst.xbcd └── xst │ └── work │ ├── work.sdbl │ └── work.sdbx ├── README.md └── _config.yml /.gitignore: -------------------------------------------------------------------------------- 1 | Project_1/work/ 2 | *.mpf 3 | *.mti 4 | *.wlf 5 | *.bak 6 | transcript 7 | .vscode/ 8 | .xmind 9 | ISE/ 10 | *.pdf 11 | Project_Assignment/work/ 12 | -------------------------------------------------------------------------------- /LICENSE.md: -------------------------------------------------------------------------------- 1 | MIT License 2 | 3 | Copyright (c) 2017 [Triple-Z](https://github.com/Triple-Z) 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in all 13 | copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 | SOFTWARE. 22 | -------------------------------------------------------------------------------- /Project_1/assemble_code_exp.txt: -------------------------------------------------------------------------------- 1 | ori $t2, $t5, 10 2 | add $t1, $t1, $t1 3 | addu $t3, $t3, $t3 4 | beq $t0, $zero, H 5 | add $t2, $t2, $t2 6 | H: sub $t3, $t1, $t2 7 | subu $t3, $t4, $t2 8 | and $t5, $t4, $t2 9 | or $t5, $t4, $t2 10 | slt $t1, $t2, $t4 11 | sltu $t1, $t4, $t2 12 | sw $t5, 100($s2) 13 | lw $t1, 100($s2) 14 | j L 15 | add $t2, $t2, $t2 16 | add $t2, $t2, $t2 17 | add $t2, $t2, $t2 18 | L:sub $t3, $t2, $t4 19 | 20 | 21 | $zero | $0 22 | $t0 | $8 23 | $t1 | $9 24 | $t2 | $10 25 | $t3 | $11 26 | $t4 | $12 27 | $t5 | $13 28 | $s2 | $18 -------------------------------------------------------------------------------- /Project_1/code.txt: -------------------------------------------------------------------------------- 1 | 35aa000a 2 | 01294820 3 | 016b5821 4 | 11000001 5 | 014a5020 6 | 012a5822 7 | 018a5823 8 | 018a6824 9 | 018a6825 10 | 014c482a 11 | 018a482b 12 | ae4d0064 13 | 8e490064 14 | 08000c11 15 | 014a5020 16 | 014a5020 17 | 014a5020 18 | 014c5822 19 | -------------------------------------------------------------------------------- /Project_1/control/ctrl.v: -------------------------------------------------------------------------------- 1 | module ctrl (ins, branch, jump, regDst, aluSrc, aluCtr, regWr, memWr, extOp, memtoReg); 2 | input [31:0] ins; 3 | 4 | output reg [3:0] aluCtr; 5 | output reg branch; 6 | output reg jump; 7 | output reg regDst; 8 | output reg aluSrc; 9 | output reg regWr; 10 | output reg memWr; 11 | output reg extOp; 12 | output reg memtoReg; 13 | 14 | wire [5:0] op; 15 | wire [5:0] func; 16 | 17 | assign op = ins[31:26]; 18 | assign func = ins[5:0]; 19 | 20 | // Operation code; 21 | parameter R = 6'b000000, 22 | LW = 6'b100011, 23 | SW = 6'b101011, 24 | BEQ = 6'b000100, 25 | J = 6'b000010, 26 | ORI = 6'b001101; 27 | // Function code; 28 | parameter ADD = 6'b100000, 29 | ADDU = 6'b100001, 30 | SUB = 6'b100010, 31 | SUBU = 6'b100011, 32 | AND = 6'b100100, 33 | OR = 6'b100101, 34 | SLT = 6'b101010, 35 | SLTU = 6'b101011; 36 | 37 | always @ ( * ) begin 38 | case (op) 39 | R: begin// R-Type Instructions; 40 | branch = 0; 41 | jump = 0; 42 | regDst = 1; 43 | aluSrc = 0; 44 | memtoReg = 0; 45 | regWr = 1; 46 | memWr = 0; 47 | case (func) 48 | ADD: aluCtr = 4'b0001; 49 | ADDU: aluCtr = 4'b0000; 50 | SUB: aluCtr = 4'b1001; 51 | SUBU: aluCtr = 4'b1000; 52 | AND: aluCtr = 4'b0010; 53 | OR: aluCtr = 4'b0011; 54 | SLT: aluCtr = 4'b1011; 55 | SLTU: aluCtr = 4'b1010; 56 | endcase 57 | end 58 | 59 | LW: begin// Load word; 60 | branch = 0; 61 | jump = 0; 62 | regDst = 0; 63 | aluSrc = 1; 64 | memtoReg = 1; 65 | regWr = 1; 66 | memWr = 0; 67 | extOp = 1; 68 | aluCtr = 4'b0001;// add; 69 | end 70 | 71 | SW: begin// Store word; 72 | branch = 0; 73 | jump = 0; 74 | aluSrc = 1; 75 | regWr = 0; 76 | memWr = 1; 77 | extOp = 1; 78 | aluCtr = 4'b0001;// add; 79 | end 80 | 81 | BEQ: begin// Branch on equal; 82 | branch = 1; 83 | jump = 0; 84 | aluSrc = 0; 85 | regWr = 0; 86 | memWr = 0; 87 | end 88 | 89 | J: begin// J-Type Instructions； 90 | branch = 0; 91 | jump = 1; 92 | regWr = 0; 93 | memWr = 0; 94 | end 95 | 96 | ORI: begin// Or immediate; 97 | branch = 0; 98 | jump = 0; 99 | regDst = 0; 100 | aluSrc = 1; 101 | memtoReg = 0; 102 | regWr = 1; 103 | memWr = 0; 104 | extOp = 0; 105 | aluCtr = 4'b0011; 106 | end 107 | endcase 108 | end 109 | 110 | endmodule // Control; 111 | -------------------------------------------------------------------------------- /Project_1/datapath/alu.v: -------------------------------------------------------------------------------- 1 | module alu (ALUop, a, b, result, zero); 2 | input [3:0] ALUop; 3 | input [31:0] a, b; 4 | output zero; 5 | output reg [31:0] result; 6 | 7 | assign zero = (result == 0)? 1: 0; 8 | 9 | always @ ( ALUop or a or b ) begin 10 | case (ALUop) 11 | 4'b0000: result = a + b;// addu; 12 | 4'b0001: result = a + b;// add; 13 | 4'b0010: result = a & b;// and; 14 | 4'b0011: result = a | b;// or; 15 | 4'b1000: result = a - b;// subu; 16 | 4'b1001: result = a - b;// sub; 17 | 4'b1010: result = a < b? 1: 0;// sltu; 18 | 4'b1011: result = a < b? 1: 0;// slt; 19 | default: result = 0; 20 | endcase 21 | end 22 | 23 | endmodule // Arithmetic Logic Unit; 24 | -------------------------------------------------------------------------------- /Project_1/datapath/dm.v: -------------------------------------------------------------------------------- 1 | module dm_4k (addr, din, wEn, clk, dout); 2 | input [11:2] addr; 3 | input [31:0] din; 4 | input wEn; 5 | input clk; 6 | output [31:0] dout; 7 | 8 | reg [31:0] dm [1023:0];// 32-bit*1024; 9 | 10 | assign dout = dm[addr[11:2]][31:0]; 11 | 12 | always @ ( posedge clk ) begin// Write; 13 | if (wEn) begin 14 | dm[addr[11:2]][31:0] <= din[31:0]; 15 | end 16 | end 17 | endmodule // 4K Data Memeory; 18 | -------------------------------------------------------------------------------- /Project_1/datapath/ext.v: -------------------------------------------------------------------------------- 1 | module ext (imm16, extOp, dout); 2 | input extOp; 3 | input [15:0] imm16; 4 | output reg [31:0] dout; 5 | 6 | always @ ( * ) begin 7 | case (extOp) 8 | 0: dout = {16'h0000, imm16};// Logical Cal; 9 | 1: dout = {{16{imm16[15]}}, imm16};// Arithmetic Cal;; 10 | endcase 11 | end 12 | endmodule // Extender; 13 | -------------------------------------------------------------------------------- /Project_1/datapath/im.v: -------------------------------------------------------------------------------- 1 | module im_4k (iaddr, ins); 2 | input [11:2] iaddr; 3 | output [31:0] ins; 4 | 5 | reg [31:0] im[1023:0];// 32-bit*1024; 6 | 7 | initial begin 8 | $readmemh("code.txt", im); 9 | end 10 | 11 | assign ins = im[iaddr[11:2]][31:0]; 12 | 13 | 14 | endmodule // 4k Instruction Memeory; 15 | -------------------------------------------------------------------------------- /Project_1/datapath/mux.v: -------------------------------------------------------------------------------- 1 | module mux #(parameter WIDTH = 32) (a, b, ctrl_s, dout); 2 | input [WIDTH - 1:0] a; 3 | input [WIDTH - 1:0] b; 4 | input ctrl_s; 5 | 6 | output [WIDTH - 1:0] dout; 7 | 8 | assign dout = ctrl_s? b: a; 9 | 10 | endmodule // Multiplexer; 11 | -------------------------------------------------------------------------------- /Project_1/datapath/npc.v: -------------------------------------------------------------------------------- 1 | module npc (iaddr, branch, jump, zero, imm16, imm26, niaddr); 2 | input branch, jump, zero; 3 | input [31:0] iaddr;// Instruction Address; 4 | input [15:0] imm16; 5 | input [25:0] imm26; 6 | 7 | output reg [31:0] niaddr;// Next Instruction Address; 8 | 9 | wire [31:0] pc4; 10 | assign pc4 = iaddr + 3'b100; 11 | 12 | always @ ( * ) begin 13 | if (zero && branch) begin// Branch; 14 | niaddr = {{14{imm16[15]}}, imm16[15:0], 2'b00} + pc4; 15 | end else if (jump) begin// Jump; 16 | niaddr = {iaddr[31:28], imm26[25:0], 2'b00}; 17 | end else begin// PC + 4; 18 | niaddr = pc4; 19 | end 20 | end 21 | 22 | endmodule // Next Program Counter; 23 | -------------------------------------------------------------------------------- /Project_1/datapath/pc.v: -------------------------------------------------------------------------------- 1 | module pc (clk, rst, niaddr, iaddr); 2 | input clk; 3 | input rst; 4 | input [31:0] niaddr;// Next Instruction Address; 5 | 6 | output reg [31:0] iaddr;// Instruction Address; 7 | 8 | always @ ( posedge clk ) begin 9 | if (rst) 10 | iaddr <= 32'h0000_3000; 11 | else 12 | iaddr <= niaddr; 13 | end 14 | endmodule // Program Counter; 15 | -------------------------------------------------------------------------------- /Project_1/datapath/rf.v: -------------------------------------------------------------------------------- 1 | module regFile (busW, clk, wE, rW, rA, rB, busA, busB); 2 | input [31:0] busW; 3 | input [4:0] rW, rA, rB; 4 | input clk, wE; 5 | output [31:0] busA, busB; 6 | 7 | reg [31:0] register[0:31]; 8 | 9 | initial begin 10 | register[0] = 0;// $zero; 11 | 12 | register[8] = 0;// $t0; 13 | register[9] = 1;// $t1; 14 | register[10] = 2;// $t2; 15 | register[11] = 3;// $t3; 16 | register[12] = 4;// $t4; 17 | register[13] = 5;// $t5; 18 | register[14] = 6;// $t6; 19 | register[15] = 7;// $t7; 20 | 21 | register[16] = 0;// $s0; 22 | register[17] = 0;// $s0; 23 | register[18] = 0;// $s0; 24 | register[19] = 0;// $s0; 25 | end 26 | 27 | assign busA = (rA != 0)? register[rA]: 0; 28 | assign busB = (rB != 0)? register[rB]: 0; 29 | 30 | always @ ( posedge clk ) begin 31 | if ((wE == 1) && (rW != 0)) begin 32 | register[rW] <= busW; 33 | end 34 | end 35 | endmodule // Register File 36 | -------------------------------------------------------------------------------- /Project_1/mips.v: -------------------------------------------------------------------------------- 1 | `include "datapath/pc.v" 2 | `include "datapath/alu.v" 3 | `include "datapath/dm.v" 4 | `include "datapath/ext.v" 5 | `include "datapath/im.v" 6 | `include "datapath/npc.v" 7 | `include "datapath/rf.v" 8 | `include "datapath/mux.v" 9 | `include "control/ctrl.v" 10 | 11 | module mips (clk, rst); 12 | input clk; 13 | input rst; 14 | 15 | wire [31:0] pc_next; 16 | wire [31:0] pc_cur; 17 | wire [31:0] ins; 18 | wire [31:0] ext_imm; 19 | wire [31:0] routa; 20 | wire [31:0] routb; 21 | wire [31:0] rin; 22 | wire [31:0] aluSrc_mux_out; 23 | wire [31:0] alu_out; 24 | wire [31:0] dm_out; 25 | wire [4:0] rWin; 26 | wire [3:0] aluCtr; 27 | wire branch; 28 | wire jump; 29 | wire regDst; 30 | wire aluSrc; 31 | wire regWr; 32 | wire memWr; 33 | wire extOp; 34 | wire memtoReg; 35 | wire zero; 36 | 37 | 38 | pc pc( 39 | .clk(clk), 40 | .rst(rst), 41 | .niaddr(pc_next), 42 | .iaddr(pc_cur) 43 | ); 44 | 45 | npc npc( 46 | .iaddr(pc_cur), 47 | .branch(branch), 48 | .jump(jump), 49 | .zero(zero), 50 | .imm16(ins[15:0]), 51 | .imm26(ins[25:0]), 52 | .niaddr(pc_next) 53 | ); 54 | 55 | im_4k im( 56 | .iaddr(pc_cur[11:2]), 57 | .ins(ins) 58 | ); 59 | 60 | ext extOp_ext( 61 | .imm16(ins[15:0]), 62 | .extOp(extOp), 63 | .dout(ext_imm) 64 | ); 65 | 66 | 67 | mux #(32) aluSrc_mux( 68 | .a(routb), 69 | .b(ext_imm), 70 | .ctrl_s(aluSrc), 71 | .dout(aluSrc_mux_out) 72 | ); 73 | 74 | mux #(5) regDst_mux( 75 | .a(ins[20:16]), 76 | .b(ins[15:11]), 77 | .ctrl_s(regDst), 78 | .dout(rWin) 79 | ); 80 | 81 | regFile rf( 82 | .busW(rin), 83 | .clk(clk), 84 | .wE(regWr), 85 | .rW(rWin), 86 | .rA(ins[25:21]), 87 | .rB(ins[20:16]), 88 | .busA(routa), 89 | .busB(routb) 90 | ); 91 | 92 | alu alu( 93 | .ALUop(aluCtr), 94 | .a(routa), 95 | .b(aluSrc_mux_out), 96 | .result(alu_out), 97 | .zero(zero) 98 | ); 99 | 100 | dm_4k dm( 101 | .addr(alu_out[11:2]), 102 | .din(routb), 103 | .wEn(memWr), 104 | .clk(clk), 105 | .dout(dm_out) 106 | ); 107 | 108 | mux memtoReg_mux( 109 | .a(alu_out), 110 | .b(dm_out), 111 | .ctrl_s(memtoReg), 112 | .dout(rin) 113 | ); 114 | 115 | ctrl ctrl( 116 | .ins(ins), 117 | .branch(branch), 118 | .jump(jump), 119 | .regDst(regDst), 120 | .aluSrc(aluSrc), 121 | .aluCtr(aluCtr), 122 | .regWr(regWr), 123 | .memWr(memWr), 124 | .extOp(extOp), 125 | .memtoReg(memtoReg) 126 | ); 127 | 128 | endmodule // MIPS main program; 129 | -------------------------------------------------------------------------------- /Project_1/testbench.v: -------------------------------------------------------------------------------- 1 | `include "mips.v" 2 | 3 | module testbench (); 4 | reg clk, rst; 5 | 6 | initial begin 7 | clk = 0; 8 | rst = 1; 9 | #20 rst = 0; 10 | end 11 | 12 | always #10 clk = ~clk; 13 | 14 | mips mips( 15 | .clk(clk), 16 | .rst(rst) 17 | ); 18 | 19 | endmodule // Test Bench; 20 | -------------------------------------------------------------------------------- /Project_2_OC/ALUOnBoard/_ngo/netlist.lst: -------------------------------------------------------------------------------- 1 | F:\Verilog\Project_2_OC\ALUOnBoard\alu_display.ngc 1497525632 2 | F:\Verilog\Project_2_OC\ALUOnBoard/lcd_module.ngc 1462996372 3 | F:\Verilog\Project_2_OC\ALUOnBoard/lcd_rom.ngc 1462996372 4 | OK 5 | -------------------------------------------------------------------------------- /Project_2_OC/ALUOnBoard/_xmsgs/bitgen.xmsgs: -------------------------------------------------------------------------------- 1 | 2 | 7 | 8 | 9 | 10 | -------------------------------------------------------------------------------- /Project_2_OC/ALUOnBoard/_xmsgs/map.xmsgs: -------------------------------------------------------------------------------- 1 | 2 | 7 | 8 | Logical network N210 has no load. 9 | 10 | 11 | The above info message is repeated 2 more times for the following (max. 5 shown): 12 | N211, 13 | lcd_module/touch_module/int_io/O 14 | To see the details of these info messages, please use the -detail switch. 15 | 16 | 17 | No environment variables are currently set. 18 | 19 | 20 | All of the single ended outputs in this design are using slew rate limited output drivers. The delay on speed critical single ended outputs can be dramatically reduced by designating them as fast outputs. 21 | 22 | 23 | Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius) 24 | 25 | 26 | Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts) 27 | 28 | 29 | The Interim Design Summary has been generated in the MAP Report (.mrp). 30 | 31 | 32 | Map created a placed design. 33 | 34 | 35 | 36 | 37 | -------------------------------------------------------------------------------- /Project_2_OC/ALUOnBoard/_xmsgs/ngdbuild.xmsgs: -------------------------------------------------------------------------------- 1 | 2 | 7 | 8 | logical net 'N210' has no driver 9 | 10 | 11 | logical net 'N211' has no driver 12 | 13 | 14 | 15 | 16 | -------------------------------------------------------------------------------- /Project_2_OC/ALUOnBoard/_xmsgs/par.xmsgs: -------------------------------------------------------------------------------- 1 | 2 | 7 | 8 | 9 | 10 | -------------------------------------------------------------------------------- /Project_2_OC/ALUOnBoard/_xmsgs/pn_parser.xmsgs: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | Analyzing Verilog file \"F:/Verilog/Project_2_OC/ALUOnBoard/adder.v\" into library work 12 | 13 | 14 | Analyzing Verilog file \"F:/Verilog/Project_2_OC/ALUOnBoard/alu.v\" into library work 15 | 16 | 17 | Analyzing Verilog file \"F:/Verilog/Project_2_OC/ALUOnBoard/alu_display.v\" into library work 18 | 19 | 20 | Analyzing Verilog file \"F:/Verilog/Project_2_OC/ALUOnBoard/lcd_module.v\" into library work 21 | 22 | 23 | 24 | 25 | -------------------------------------------------------------------------------- /Project_2_OC/ALUOnBoard/_xmsgs/trce.xmsgs: -------------------------------------------------------------------------------- 1 | 2 | 7 | 8 | To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report. 9 | 10 | The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet. 11 | 12 | 13 | 14 | -------------------------------------------------------------------------------- /Project_2_OC/ALUOnBoard/adder.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Triple-Z/COExperiment_Repo/7a0ad4c5d025753d560e8a433fb26ea406268b1b/Project_2_OC/ALUOnBoard/adder.v -------------------------------------------------------------------------------- /Project_2_OC/ALUOnBoard/alu.ucf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Triple-Z/COExperiment_Repo/7a0ad4c5d025753d560e8a433fb26ea406268b1b/Project_2_OC/ALUOnBoard/alu.ucf -------------------------------------------------------------------------------- /Project_2_OC/ALUOnBoard/alu.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Triple-Z/COExperiment_Repo/7a0ad4c5d025753d560e8a433fb26ea406268b1b/Project_2_OC/ALUOnBoard/alu.v -------------------------------------------------------------------------------- /Project_2_OC/ALUOnBoard/alu_display.bit: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Triple-Z/COExperiment_Repo/7a0ad4c5d025753d560e8a433fb26ea406268b1b/Project_2_OC/ALUOnBoard/alu_display.bit -------------------------------------------------------------------------------- /Project_2_OC/ALUOnBoard/alu_display.bld: -------------------------------------------------------------------------------- 1 | Release 13.2 ngdbuild O.61xd (nt64) 2 | Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. 3 | 4 | Command Line: F:\ISE\ISE_DS\ISE\bin\nt64\unwrapped\ngdbuild.exe -intstyle ise 5 | -dd _ngo -nt timestamp -uc alu.ucf -p xc6slx150-fgg484-3 alu_display.ngc 6 | alu_display.ngd 7 | 8 | Reading NGO file "F:/Verilog/Project_2_OC/ALUOnBoard/alu_display.ngc" ... 9 | Loading design module "F:\Verilog\Project_2_OC\ALUOnBoard/lcd_module.ngc"... 10 | Loading design module "F:\Verilog\Project_2_OC\ALUOnBoard/lcd_rom.ngc"... 11 | Gathering constraint information from source properties... 12 | Done. 13 | 14 | Annotating constraints to design from ucf file "alu.ucf" ... 15 | Resolving constraint associations... 16 | Checking Constraint Associations... 17 | Done... 18 | 19 | Checking expanded design ... 20 | WARNING:NgdBuild:452 - logical net 'N210' has no driver 21 | WARNING:NgdBuild:452 - logical net 'N211' has no driver 22 | 23 | Partition Implementation Status 24 | ------------------------------- 25 | 26 | No Partitions were found in this design. 27 | 28 | ------------------------------- 29 | 30 | NGDBUILD Design Results Summary: 31 | Number of errors: 0 32 | Number of warnings: 2 33 | 34 | Total memory usage is 154920 kilobytes 35 | 36 | Writing NGD file "alu_display.ngd" ... 37 | Total REAL time to NGDBUILD completion: 3 sec 38 | Total CPU time to NGDBUILD completion: 2 sec 39 | 40 | Writing NGDBUILD log file "alu_display.bld"... 41 | -------------------------------------------------------------------------------- /Project_2_OC/ALUOnBoard/alu_display.cmd_log: -------------------------------------------------------------------------------- 1 | xst -intstyle ise -ifn "F:/Verilog/Project_2_OC/ALUOnBoard/alu_display.xst" -ofn "F:/Verilog/Project_2_OC/ALUOnBoard/alu_display.syr" 2 | xst -intstyle ise -ifn "F:/Verilog/Project_2_OC/ALUOnBoard/alu_display.xst" -ofn "F:/Verilog/Project_2_OC/ALUOnBoard/alu_display.syr" 3 | ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc alu.ucf -p xc6slx150-fgg484-3 alu_display.ngc alu_display.ngd 4 | map -intstyle ise -p xc6slx150-fgg484-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o alu_display_map.ncd alu_display.ngd alu_display.pcf 5 | par -w -intstyle ise -ol high -mt off alu_display_map.ncd alu_display.ncd alu_display.pcf 6 | trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml alu_display.twx alu_display.ncd -o alu_display.twr alu_display.pcf -ucf alu.ucf 7 | bitgen -intstyle ise -f alu_display.ut alu_display.ncd 8 | -------------------------------------------------------------------------------- /Project_2_OC/ALUOnBoard/alu_display.drc: -------------------------------------------------------------------------------- 1 | Release 13.2 Drc O.61xd (nt64) 2 | Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. 3 | 4 | Thu Jun 15 19:21:39 2017 5 | 6 | drc -z alu_display.ncd alu_display.pcf 7 | 8 | DRC detected 0 errors and 0 warnings. 9 | -------------------------------------------------------------------------------- /Project_2_OC/ALUOnBoard/alu_display.lso: -------------------------------------------------------------------------------- 1 | work 2 | -------------------------------------------------------------------------------- /Project_2_OC/ALUOnBoard/alu_display.prj: -------------------------------------------------------------------------------- 1 | verilog work "adder.v" 2 | verilog work "lcd_module.v" 3 | verilog work "alu.v" 4 | verilog work "alu_display.v" 5 | -------------------------------------------------------------------------------- /Project_2_OC/ALUOnBoard/alu_display.stx: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Triple-Z/COExperiment_Repo/7a0ad4c5d025753d560e8a433fb26ea406268b1b/Project_2_OC/ALUOnBoard/alu_display.stx -------------------------------------------------------------------------------- /Project_2_OC/ALUOnBoard/alu_display.unroutes: -------------------------------------------------------------------------------- 1 | Release 13.2 - par O.61xd (nt64) 2 | Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. 3 | 4 | Thu Jun 15 19:21:26 2017 5 | 6 | All signals are completely routed. 7 | 8 | 9 | 10 | -------------------------------------------------------------------------------- /Project_2_OC/ALUOnBoard/alu_display.ut: -------------------------------------------------------------------------------- 1 | -w 2 | -g DebugBitstream:No 3 | -g Binary:no 4 | -g CRC:Enable 5 | -g Reset_on_err:No 6 | -g ConfigRate:2 7 | -g ProgPin:PullUp 8 | -g TckPin:PullUp 9 | -g TdiPin:PullUp 10 | -g TdoPin:PullUp 11 | -g TmsPin:PullUp 12 | -g UnusedPin:PullDown 13 | -g UserID:0xFFFFFFFF 14 | -g ExtMasterCclk_en:No 15 | -g SPI_buswidth:1 16 | -g TIMER_CFG:0xFFFF 17 | -g multipin_wakeup:No 18 | -g StartUpClk:CClk 19 | -g DONE_cycle:4 20 | -g GTS_cycle:5 21 | -g GWE_cycle:6 22 | -g LCK_cycle:NoWait 23 | -g Security:None 24 | -g DonePipe:No 25 | -g DriveDone:No 26 | -g Encrypt:No 27 | -g en_sw_gsr:No 28 | -g drive_awake:No 29 | -g sw_clk:Startupclk 30 | -g sw_gwe_cycle:5 31 | -g sw_gts_cycle:4 32 | -------------------------------------------------------------------------------- /Project_2_OC/ALUOnBoard/alu_display.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Triple-Z/COExperiment_Repo/7a0ad4c5d025753d560e8a433fb26ea406268b1b/Project_2_OC/ALUOnBoard/alu_display.v -------------------------------------------------------------------------------- /Project_2_OC/ALUOnBoard/alu_display.xpi: -------------------------------------------------------------------------------- 1 | PROGRAM=PAR 2 | STATE=ROUTED 3 | TIMESPECS_MET=YES 4 | -------------------------------------------------------------------------------- /Project_2_OC/ALUOnBoard/alu_display.xst: -------------------------------------------------------------------------------- 1 | set -tmpdir "xst/projnav.tmp" 2 | set -xsthdpdir "xst" 3 | run 4 | -ifn alu_display.prj 5 | -ifmt mixed 6 | -ofn alu_display 7 | -ofmt NGC 8 | -p xc6slx150-3-fgg484 9 | -top alu_display 10 | -opt_mode Speed 11 | -opt_level 1 12 | -power NO 13 | -iuc NO 14 | -keep_hierarchy No 15 | -netlist_hierarchy As_Optimized 16 | -rtlview Yes 17 | -glob_opt AllClockNets 18 | -read_cores YES 19 | -write_timing_constraints NO 20 | -cross_clock_analysis NO 21 | -hierarchy_separator / 22 | -bus_delimiter <> 23 | -case Maintain 24 | -slice_utilization_ratio 100 25 | -bram_utilization_ratio 100 26 | -dsp_utilization_ratio 100 27 | -lc Auto 28 | -reduce_control_sets Auto 29 | -fsm_extract YES -fsm_encoding Auto 30 | -safe_implementation No 31 | -fsm_style LUT 32 | -ram_extract Yes 33 | -ram_style Auto 34 | -rom_extract Yes 35 | -shreg_extract YES 36 | -rom_style Auto 37 | -auto_bram_packing NO 38 | -resource_sharing YES 39 | -async_to_sync NO 40 | -shreg_min_size 2 41 | -use_dsp48 Auto 42 | -iobuf YES 43 | -max_fanout 100000 44 | -bufg 16 45 | -register_duplication YES 46 | -register_balancing No 47 | -optimize_primitives NO 48 | -use_clock_enable Auto 49 | -use_sync_set Auto 50 | -use_sync_reset Auto 51 | -iob Auto 52 | -equivalent_register_removal YES 53 | -slice_utilization_ratio_maxmargin 5 54 | -------------------------------------------------------------------------------- /Project_2_OC/ALUOnBoard/alu_display_bitgen.xwbt: -------------------------------------------------------------------------------- 1 | INTSTYLE=ise 2 | INFILE=F:\Verilog\Project_2_OC\ALUOnBoard\alu_display.ncd 3 | OUTFILE=F:\Verilog\Project_2_OC\ALUOnBoard\alu_display.bit 4 | FAMILY=Spartan6 5 | PART=xc6slx150-3fgg484 6 | WORKINGDIR=F:\Verilog\Project_2_OC\ALUOnBoard 7 | LICENSE=ISE 8 | USER_INFO=135256_15690819_173552794_661 9 | -------------------------------------------------------------------------------- /Project_2_OC/ALUOnBoard/alu_display_summary.html: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Triple-Z/COExperiment_Repo/7a0ad4c5d025753d560e8a433fb26ea406268b1b/Project_2_OC/ALUOnBoard/alu_display_summary.html -------------------------------------------------------------------------------- /Project_2_OC/ALUOnBoard/alu_display_summary.xml: -------------------------------------------------------------------------------- 1 | 2 | 7 | 8 | 9 | 10 | 11 | -------------------------------------------------------------------------------- /Project_2_OC/ALUOnBoard/lcd_module.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Triple-Z/COExperiment_Repo/7a0ad4c5d025753d560e8a433fb26ea406268b1b/Project_2_OC/ALUOnBoard/lcd_module.v -------------------------------------------------------------------------------- /Project_2_OC/ALUOnBoard/webtalk.log: -------------------------------------------------------------------------------- 1 | Release 13.2 - WebTalk (O.61xd) 2 | Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. 3 | 4 | WebTalk Summary 5 | ---------------- 6 | INFO:WebTalk:3 - WebTalk is disabled. 7 | 8 | INFO:WebTalk:9 - WebTalk Install setting is OFF. 9 | INFO:WebTalk:6 - WebTalk User setting is ON. 10 | -------------------------------------------------------------------------------- /Project_2_OC/ALUOnBoard/webtalk_pn.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 6 | 7 |
8 | 9 | 10 | 11 | 12 |
13 |
14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 |
42 | 43 | 44 | -------------------------------------------------------------------------------- /Project_2_OC/ALUOnBoard/xlnx_auto_0_xdb/cst.xbcd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Triple-Z/COExperiment_Repo/7a0ad4c5d025753d560e8a433fb26ea406268b1b/Project_2_OC/ALUOnBoard/xlnx_auto_0_xdb/cst.xbcd -------------------------------------------------------------------------------- /Project_2_OC/ALUOnBoard/xst/work/work.sdbl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Triple-Z/COExperiment_Repo/7a0ad4c5d025753d560e8a433fb26ea406268b1b/Project_2_OC/ALUOnBoard/xst/work/work.sdbl -------------------------------------------------------------------------------- /Project_2_OC/ALUOnBoard/xst/work/work.sdbx: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Triple-Z/COExperiment_Repo/7a0ad4c5d025753d560e8a433fb26ea406268b1b/Project_2_OC/ALUOnBoard/xst/work/work.sdbx -------------------------------------------------------------------------------- /Project_2_OC/MemoryOnBoard/_ngo/netlist.lst: -------------------------------------------------------------------------------- 1 | F:\Verilog\Project_2_OC\MemoryOnBoard\data_ram_display.ngc 1497529902 2 | F:\Verilog\Project_2_OC\MemoryOnBoard/data_ram.ngc 1462996371 3 | F:\Verilog\Project_2_OC\MemoryOnBoard/lcd_module.ngc 1462996372 4 | F:\Verilog\Project_2_OC\MemoryOnBoard/lcd_rom.ngc 1462996372 5 | OK 6 | -------------------------------------------------------------------------------- /Project_2_OC/MemoryOnBoard/_xmsgs/bitgen.xmsgs: -------------------------------------------------------------------------------- 1 | 2 | 7 | 8 | 9 | 10 | -------------------------------------------------------------------------------- /Project_2_OC/MemoryOnBoard/_xmsgs/map.xmsgs: -------------------------------------------------------------------------------- 1 | 2 | 7 | 8 | Logical network N35 has no load. 9 | 10 | 11 | The above info message is repeated 2 more times for the following (max. 5 shown): 12 | N36, 13 | lcd_module/touch_module/int_io/O 14 | To see the details of these info messages, please use the -detail switch. 15 | 16 | 17 | No environment variables are currently set. 18 | 19 | 20 | All of the single ended outputs in this design are using slew rate limited output drivers. The delay on speed critical single ended outputs can be dramatically reduced by designating them as fast outputs. 21 | 22 | 23 | Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius) 24 | 25 | 26 | Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts) 27 | 28 | 29 | The Interim Design Summary has been generated in the MAP Report (.mrp). 30 | 31 | 32 | Map created a placed design. 33 | 34 | 35 | 36 | 37 | -------------------------------------------------------------------------------- /Project_2_OC/MemoryOnBoard/_xmsgs/ngdbuild.xmsgs: -------------------------------------------------------------------------------- 1 | 2 | 7 | 8 | logical net 'N35' has no driver 9 | 10 | 11 | logical net 'N36' has no driver 12 | 13 | 14 | 15 | 16 | -------------------------------------------------------------------------------- /Project_2_OC/MemoryOnBoard/_xmsgs/par.xmsgs: -------------------------------------------------------------------------------- 1 | 2 | 7 | 8 | 9 | 10 | -------------------------------------------------------------------------------- /Project_2_OC/MemoryOnBoard/_xmsgs/pn_parser.xmsgs: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | Analyzing Verilog file \"F:/Verilog/Project_2_OC/MemoryOnBoard/data_ram.v\" into library work 12 | 13 | 14 | Analyzing Verilog file \"F:/Verilog/Project_2_OC/MemoryOnBoard/data_ram_display.v\" into library work 15 | 16 | 17 | Analyzing Verilog file \"F:/Verilog/Project_2_OC/MemoryOnBoard/lcd_module.v\" into library work 18 | 19 | 20 | 21 | 22 | -------------------------------------------------------------------------------- /Project_2_OC/MemoryOnBoard/_xmsgs/trce.xmsgs: -------------------------------------------------------------------------------- 1 | 2 | 7 | 8 | To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report. 9 | 10 | The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet. 11 | 12 | 13 | 14 | -------------------------------------------------------------------------------- /Project_2_OC/MemoryOnBoard/data_mem.ucf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Triple-Z/COExperiment_Repo/7a0ad4c5d025753d560e8a433fb26ea406268b1b/Project_2_OC/MemoryOnBoard/data_mem.ucf -------------------------------------------------------------------------------- /Project_2_OC/MemoryOnBoard/data_ram.sym: -------------------------------------------------------------------------------- 1 | 2 | 3 | BLOCK 4 | 2017-6-15T12:24:36 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | data_ram 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | -------------------------------------------------------------------------------- /Project_2_OC/MemoryOnBoard/data_ram_display.bit: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Triple-Z/COExperiment_Repo/7a0ad4c5d025753d560e8a433fb26ea406268b1b/Project_2_OC/MemoryOnBoard/data_ram_display.bit -------------------------------------------------------------------------------- /Project_2_OC/MemoryOnBoard/data_ram_display.bld: -------------------------------------------------------------------------------- 1 | Release 13.2 ngdbuild O.61xd (nt64) 2 | Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. 3 | 4 | Command Line: F:\ISE\ISE_DS\ISE\bin\nt64\unwrapped\ngdbuild.exe -intstyle ise 5 | -dd _ngo -sd ipcore_dir -nt timestamp -uc data_mem.ucf -p xc6slx150-fgg484-3 6 | data_ram_display.ngc data_ram_display.ngd 7 | 8 | Reading NGO file "F:/Verilog/Project_2_OC/MemoryOnBoard/data_ram_display.ngc" 9 | ... 10 | Loading design module "F:\Verilog\Project_2_OC\MemoryOnBoard/data_ram.ngc"... 11 | Loading design module "F:\Verilog\Project_2_OC\MemoryOnBoard/lcd_module.ngc"... 12 | Loading design module "F:\Verilog\Project_2_OC\MemoryOnBoard/lcd_rom.ngc"... 13 | Gathering constraint information from source properties... 14 | Done. 15 | 16 | Annotating constraints to design from ucf file "data_mem.ucf" ... 17 | Resolving constraint associations... 18 | Checking Constraint Associations... 19 | Done... 20 | 21 | Checking expanded design ... 22 | WARNING:NgdBuild:452 - logical net 'N35' has no driver 23 | WARNING:NgdBuild:452 - logical net 'N36' has no driver 24 | 25 | Partition Implementation Status 26 | ------------------------------- 27 | 28 | No Partitions were found in this design. 29 | 30 | ------------------------------- 31 | 32 | NGDBUILD Design Results Summary: 33 | Number of errors: 0 34 | Number of warnings: 2 35 | 36 | Total memory usage is 154280 kilobytes 37 | 38 | Writing NGD file "data_ram_display.ngd" ... 39 | Total REAL time to NGDBUILD completion: 2 sec 40 | Total CPU time to NGDBUILD completion: 2 sec 41 | 42 | Writing NGDBUILD log file "data_ram_display.bld"... 43 | -------------------------------------------------------------------------------- /Project_2_OC/MemoryOnBoard/data_ram_display.cmd_log: -------------------------------------------------------------------------------- 1 | xst -intstyle ise -ifn "F:/Verilog/Project_2_OC/MemoryOnBoard/data_ram_display.xst" -ofn "F:/Verilog/Project_2_OC/MemoryOnBoard/data_ram_display.syr" 2 | xst -intstyle ise -ifn "F:/Verilog/Project_2_OC/MemoryOnBoard/data_ram_display.xst" -ofn "F:/Verilog/Project_2_OC/MemoryOnBoard/data_ram_display.syr" 3 | ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc data_mem.ucf -p xc6slx150-fgg484-3 data_ram_display.ngc data_ram_display.ngd 4 | map -intstyle ise -p xc6slx150-fgg484-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o data_ram_display_map.ncd data_ram_display.ngd data_ram_display.pcf 5 | par -w -intstyle ise -ol high -mt off data_ram_display_map.ncd data_ram_display.ncd data_ram_display.pcf 6 | trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml data_ram_display.twx data_ram_display.ncd -o data_ram_display.twr data_ram_display.pcf -ucf data_mem.ucf 7 | bitgen -intstyle ise -f data_ram_display.ut data_ram_display.ncd 8 | -------------------------------------------------------------------------------- /Project_2_OC/MemoryOnBoard/data_ram_display.drc: -------------------------------------------------------------------------------- 1 | Release 13.2 Drc O.61xd (nt64) 2 | Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. 3 | 4 | Thu Jun 15 20:32:36 2017 5 | 6 | drc -z data_ram_display.ncd data_ram_display.pcf 7 | 8 | DRC detected 0 errors and 0 warnings. 9 | -------------------------------------------------------------------------------- /Project_2_OC/MemoryOnBoard/data_ram_display.lso: -------------------------------------------------------------------------------- 1 | work 2 | -------------------------------------------------------------------------------- /Project_2_OC/MemoryOnBoard/data_ram_display.prj: -------------------------------------------------------------------------------- 1 | verilog work "lcd_module.v" 2 | verilog work "data_ram.v" 3 | verilog work "data_ram_display.v" 4 | -------------------------------------------------------------------------------- /Project_2_OC/MemoryOnBoard/data_ram_display.stx: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Triple-Z/COExperiment_Repo/7a0ad4c5d025753d560e8a433fb26ea406268b1b/Project_2_OC/MemoryOnBoard/data_ram_display.stx -------------------------------------------------------------------------------- /Project_2_OC/MemoryOnBoard/data_ram_display.unroutes: -------------------------------------------------------------------------------- 1 | Release 13.2 - par O.61xd (nt64) 2 | Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. 3 | 4 | Thu Jun 15 20:32:24 2017 5 | 6 | All signals are completely routed. 7 | 8 | 9 | 10 | -------------------------------------------------------------------------------- /Project_2_OC/MemoryOnBoard/data_ram_display.ut: -------------------------------------------------------------------------------- 1 | -w 2 | -g DebugBitstream:No 3 | -g Binary:no 4 | -g CRC:Enable 5 | -g Reset_on_err:No 6 | -g ConfigRate:2 7 | -g ProgPin:PullUp 8 | -g TckPin:PullUp 9 | -g TdiPin:PullUp 10 | -g TdoPin:PullUp 11 | -g TmsPin:PullUp 12 | -g UnusedPin:PullDown 13 | -g UserID:0xFFFFFFFF 14 | -g ExtMasterCclk_en:No 15 | -g SPI_buswidth:1 16 | -g TIMER_CFG:0xFFFF 17 | -g multipin_wakeup:No 18 | -g StartUpClk:CClk 19 | -g DONE_cycle:4 20 | -g GTS_cycle:5 21 | -g GWE_cycle:6 22 | -g LCK_cycle:NoWait 23 | -g Security:None 24 | -g DonePipe:No 25 | -g DriveDone:No 26 | -g Encrypt:No 27 | -g en_sw_gsr:No 28 | -g drive_awake:No 29 | -g sw_clk:Startupclk 30 | -g sw_gwe_cycle:5 31 | -g sw_gts_cycle:4 32 | -------------------------------------------------------------------------------- /Project_2_OC/MemoryOnBoard/data_ram_display.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Triple-Z/COExperiment_Repo/7a0ad4c5d025753d560e8a433fb26ea406268b1b/Project_2_OC/MemoryOnBoard/data_ram_display.v -------------------------------------------------------------------------------- /Project_2_OC/MemoryOnBoard/data_ram_display.xpi: -------------------------------------------------------------------------------- 1 | PROGRAM=PAR 2 | STATE=ROUTED 3 | TIMESPECS_MET=YES 4 | -------------------------------------------------------------------------------- /Project_2_OC/MemoryOnBoard/data_ram_display.xst: -------------------------------------------------------------------------------- 1 | set -tmpdir "xst/projnav.tmp" 2 | set -xsthdpdir "xst" 3 | run 4 | -ifn data_ram_display.prj 5 | -ifmt mixed 6 | -ofn data_ram_display 7 | -ofmt NGC 8 | -p xc6slx150-3-fgg484 9 | -top data_ram_display 10 | -opt_mode Speed 11 | -opt_level 1 12 | -power NO 13 | -iuc NO 14 | -keep_hierarchy No 15 | -netlist_hierarchy As_Optimized 16 | -rtlview Yes 17 | -glob_opt AllClockNets 18 | -read_cores YES 19 | -sd {"ipcore_dir" } 20 | -write_timing_constraints NO 21 | -cross_clock_analysis NO 22 | -hierarchy_separator / 23 | -bus_delimiter <> 24 | -case Maintain 25 | -slice_utilization_ratio 100 26 | -bram_utilization_ratio 100 27 | -dsp_utilization_ratio 100 28 | -lc Auto 29 | -reduce_control_sets Auto 30 | -fsm_extract YES -fsm_encoding Auto 31 | -safe_implementation No 32 | -fsm_style LUT 33 | -ram_extract Yes 34 | -ram_style Auto 35 | -rom_extract Yes 36 | -shreg_extract YES 37 | -rom_style Auto 38 | -auto_bram_packing NO 39 | -resource_sharing YES 40 | -async_to_sync NO 41 | -shreg_min_size 2 42 | -use_dsp48 Auto 43 | -iobuf YES 44 | -max_fanout 100000 45 | -bufg 16 46 | -register_duplication YES 47 | -register_balancing No 48 | -optimize_primitives NO 49 | -use_clock_enable Auto 50 | -use_sync_set Auto 51 | -use_sync_reset Auto 52 | -iob Auto 53 | -equivalent_register_removal YES 54 | -slice_utilization_ratio_maxmargin 5 55 | -------------------------------------------------------------------------------- /Project_2_OC/MemoryOnBoard/data_ram_display_bitgen.xwbt: -------------------------------------------------------------------------------- 1 | INTSTYLE=ise 2 | INFILE=F:\Verilog\Project_2_OC\MemoryOnBoard\data_ram_display.ncd 3 | OUTFILE=F:\Verilog\Project_2_OC\MemoryOnBoard\data_ram_display.bit 4 | FAMILY=Spartan6 5 | PART=xc6slx150-3fgg484 6 | WORKINGDIR=F:\Verilog\Project_2_OC\MemoryOnBoard 7 | LICENSE=ISE 8 | USER_INFO=135256_15690819_173552794_661 9 | -------------------------------------------------------------------------------- /Project_2_OC/MemoryOnBoard/data_ram_display_summary.html: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Triple-Z/COExperiment_Repo/7a0ad4c5d025753d560e8a433fb26ea406268b1b/Project_2_OC/MemoryOnBoard/data_ram_display_summary.html -------------------------------------------------------------------------------- /Project_2_OC/MemoryOnBoard/data_ram_display_summary.xml: -------------------------------------------------------------------------------- 1 | 2 | 7 | 8 | 9 | 10 | 11 | -------------------------------------------------------------------------------- /Project_2_OC/MemoryOnBoard/ipcore_dir/_xmsgs/cg.xmsgs: -------------------------------------------------------------------------------- 1 | 2 | 7 | 8 | Generating component instance 'data_ram' of 'xilinx.com:ip:blk_mem_gen:6.1' from 'F:\ISE\ISE_DS\ISE\coregen\ip\xilinx\primary\com\xilinx\ip\blk_mem_gen_v6_1\component.xml'. 9 | 10 | 11 | 12 | 13 | -------------------------------------------------------------------------------- /Project_2_OC/MemoryOnBoard/ipcore_dir/_xmsgs/pn_parser.xmsgs: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | Analyzing Verilog file \"F:/Verilog/Project_2_OC/MemoryOnBoard/ipcore_dir/data_ram.v\" into library work 12 | 13 | 14 | 15 | 16 | -------------------------------------------------------------------------------- /Project_2_OC/MemoryOnBoard/ipcore_dir/coregen.cgp: -------------------------------------------------------------------------------- 1 | SET busformat = BusFormatAngleBracketNotRipped 2 | SET designentry = Verilog 3 | SET device = xc6slx150 4 | SET devicefamily = spartan6 5 | SET flowvendor = Other 6 | SET package = fgg484 7 | SET speedgrade = -3 8 | SET verilogsim = true 9 | SET vhdlsim = false 10 | -------------------------------------------------------------------------------- /Project_2_OC/MemoryOnBoard/ipcore_dir/coregen.log: -------------------------------------------------------------------------------- 1 | CoreGen has not been configured with any user repositories. 2 | CoreGen has been configured with the following Xilinx repositories: 3 | - 'F:\ISE\ISE_DS\ISE\coregen\' [reloaded] 4 | INFO:sim - Generating component instance 'data_ram' of 5 | 'xilinx.com:ip:blk_mem_gen:6.1' from 6 | 'F:\ISE\ISE_DS\ISE\coregen\ip\xilinx\primary\com\xilinx\ip\blk_mem_gen_v6_1\c 7 | omponent.xml'. 8 | Applying current project options... 9 | Finished applying current project options. 10 | Cancelled executing Tcl generator. 11 | Wrote CGP file for project 'data_ram'. 12 | -------------------------------------------------------------------------------- /Project_2_OC/MemoryOnBoard/ipcore_dir/create_data_ram.tcl: -------------------------------------------------------------------------------- 1 | ## 2 | ## Core Generator Run Script, generator for Project Navigator create command 3 | ## 4 | 5 | proc findRtfPath { relativePath } { 6 | set xilenv "" 7 | if { [info exists ::env(XILINX) ] } { 8 | if { [info exists ::env(MYXILINX)] } { 9 | set xilenv [join [list $::env(MYXILINX) $::env(XILINX)] $::xilinx::path_sep ] 10 | } else { 11 | set xilenv $::env(XILINX) 12 | } 13 | } 14 | foreach path [ split $xilenv $::xilinx::path_sep ] { 15 | set fullPath [ file join $path $relativePath ] 16 | if { [ file exists $fullPath ] } { 17 | return $fullPath 18 | } 19 | } 20 | return "" 21 | } 22 | 23 | source [ findRtfPath "data/projnav/scripts/dpm_cgUtils.tcl" ] 24 | 25 | set result [ run_cg_create "xilinx.com:ip:blk_mem_gen:6.1" "data_ram" "Block Memory Generator" "Block Memory Generator (xilinx.com:ip:blk_mem_gen:6.1) generated by Project Navigator" xc6slx150-3fgg484 Verilog ] 26 | 27 | if { $result == 0 } { 28 | puts "Core Generator create command completed successfully." 29 | } elseif { $result == 1 } { 30 | puts "Core Generator create command failed." 31 | } elseif { $result == 3 || $result == 4 } { 32 | # convert 'version check' result to real return range, bypassing any messages. 33 | set result [ expr $result - 3 ] 34 | } else { 35 | puts "Core Generator create cancelled." 36 | } 37 | exit $result 38 | -------------------------------------------------------------------------------- /Project_2_OC/MemoryOnBoard/ipcore_dir/data_ram.asy: -------------------------------------------------------------------------------- 1 | Version 4 2 | SymbolType BLOCK 3 | TEXT 32 32 LEFT 4 data_ram 4 | RECTANGLE Normal 32 32 544 1376 5 | LINE Wide 0 80 32 80 6 | PIN 0 80 LEFT 36 7 | PINATTR PinName addra[7:0] 8 | PINATTR Polarity IN 9 | LINE Wide 0 112 32 112 10 | PIN 0 112 LEFT 36 11 | PINATTR PinName dina[31:0] 12 | PINATTR Polarity IN 13 | LINE Wide 0 208 32 208 14 | PIN 0 208 LEFT 36 15 | PINATTR PinName wea[3:0] 16 | PINATTR Polarity IN 17 | LINE Normal 0 272 32 272 18 | PIN 0 272 LEFT 36 19 | PINATTR PinName clka 20 | PINATTR Polarity IN 21 | LINE Wide 0 432 32 432 22 | PIN 0 432 LEFT 36 23 | PINATTR PinName addrb[7:0] 24 | PINATTR Polarity IN 25 | LINE Wide 0 464 32 464 26 | PIN 0 464 LEFT 36 27 | PINATTR PinName dinb[31:0] 28 | PINATTR Polarity IN 29 | LINE Wide 0 560 32 560 30 | PIN 0 560 LEFT 36 31 | PINATTR PinName web[3:0] 32 | PINATTR Polarity IN 33 | LINE Normal 0 624 32 624 34 | PIN 0 624 LEFT 36 35 | PINATTR PinName clkb 36 | PINATTR Polarity IN 37 | LINE Wide 576 80 544 80 38 | PIN 576 80 RIGHT 36 39 | PINATTR PinName douta[31:0] 40 | PINATTR Polarity OUT 41 | LINE Wide 576 368 544 368 42 | PIN 576 368 RIGHT 36 43 | PINATTR PinName doutb[31:0] 44 | PINATTR Polarity OUT 45 | 46 | -------------------------------------------------------------------------------- /Project_2_OC/MemoryOnBoard/ipcore_dir/data_ram.gise: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 11.1 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | -------------------------------------------------------------------------------- /Project_2_OC/MemoryOnBoard/ipcore_dir/data_ram.ncf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Triple-Z/COExperiment_Repo/7a0ad4c5d025753d560e8a433fb26ea406268b1b/Project_2_OC/MemoryOnBoard/ipcore_dir/data_ram.ncf -------------------------------------------------------------------------------- /Project_2_OC/MemoryOnBoard/ipcore_dir/data_ram.sym: -------------------------------------------------------------------------------- 1 | 2 | 3 | BLOCK 4 | 2017-6-15T12:24:36 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | data_ram 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | -------------------------------------------------------------------------------- /Project_2_OC/MemoryOnBoard/ipcore_dir/data_ram_flist.txt: -------------------------------------------------------------------------------- 1 | # Output products list for 2 | blk_mem_gen_ds512.pdf 3 | blk_mem_gen_readme.txt 4 | data_ram.asy 5 | data_ram.gise 6 | data_ram.ngc 7 | data_ram.sym 8 | data_ram.v 9 | data_ram.veo 10 | data_ram.xco 11 | data_ram.xise 12 | data_ram\doc\blk_mem_gen_ds512.pdf 13 | data_ram\doc\blk_mem_gen_v6_1_vinfo.html 14 | data_ram_flist.txt 15 | data_ram_xmdf.tcl 16 | -------------------------------------------------------------------------------- /Project_2_OC/MemoryOnBoard/ipcore_dir/edit_data_ram.tcl: -------------------------------------------------------------------------------- 1 | ## 2 | ## Core Generator Run Script, generator for Project Navigator edit command 3 | ## 4 | 5 | proc findRtfPath { relativePath } { 6 | set xilenv "" 7 | if { [info exists ::env(XILINX) ] } { 8 | if { [info exists ::env(MYXILINX)] } { 9 | set xilenv [join [list $::env(MYXILINX) $::env(XILINX)] $::xilinx::path_sep ] 10 | } else { 11 | set xilenv $::env(XILINX) 12 | } 13 | } 14 | foreach path [ split $xilenv $::xilinx::path_sep ] { 15 | set fullPath [ file join $path $relativePath ] 16 | if { [ file exists $fullPath ] } { 17 | return $fullPath 18 | } 19 | } 20 | return "" 21 | } 22 | 23 | source [ findRtfPath "data/projnav/scripts/dpm_cgUtils.tcl" ] 24 | 25 | set result [ run_cg_edit "data_ram" xc6slx150-3fgg484 Verilog ] 26 | 27 | if { $result == 0 } { 28 | puts "Core Generator edit command completed successfully." 29 | } elseif { $result == 1 } { 30 | puts "Core Generator edit command failed." 31 | } elseif { $result == 3 || $result == 4 } { 32 | # convert 'version check' result to real return range, bypassing any messages. 33 | set result [ expr $result - 3 ] 34 | } else { 35 | puts "Core Generator edit cancelled." 36 | } 37 | exit $result 38 | -------------------------------------------------------------------------------- /Project_2_OC/MemoryOnBoard/ipcore_dir/tmp/_cg/_dbg/xil_996.out: -------------------------------------------------------------------------------- 1 | SET_PARAMETER use_rstb_pin false 2 | SET_PARAMETER pipeline_stages 0 3 | SET_PARAMETER assume_synchronous_clk false 4 | SET_PARAMETER use_regcea_pin false 5 | SET_PARAMETER axi_id_width 4 6 | SET_PARAMETER softecc false 7 | SET_PARAMETER load_init_file false 8 | SET_PARAMETER port_a_write_rate 50 9 | SET_PARAMETER disable_collision_warnings false 10 | SET_PARAMETER use_byte_write_enable true 11 | SET_PARAMETER ecc false 12 | SET_PARAMETER primitive 8kx2 13 | SET_PARAMETER port_b_clock 100 14 | SET_PARAMETER remaining_memory_locations 0 15 | SET_PARAMETER memory_type True_Dual_Port_RAM 16 | SET_PARAMETER register_porta_input_of_softecc false 17 | SET_PARAMETER port_a_clock 100 18 | SET_PARAMETER read_width_a 32 19 | SET_PARAMETER disable_out_of_range_warnings false 20 | SET_PARAMETER read_width_b 32 21 | SET_PARAMETER register_portb_output_of_softecc false 22 | SET_PARAMETER byte_size 8 23 | SET_PARAMETER register_portb_output_of_memory_core false 24 | SET_PARAMETER use_regceb_pin false 25 | SET_PARAMETER register_porta_output_of_memory_core false 26 | SET_PARAMETER reset_memory_latch_a false 27 | SET_PARAMETER reset_memory_latch_b false 28 | SET_PARAMETER register_porta_output_of_memory_primitives false 29 | SET_PARAMETER use_error_injection_pins false 30 | SET_PARAMETER enable_a Always_Enabled 31 | SET_PARAMETER enable_b Always_Enabled 32 | SET_PARAMETER port_a_enable_rate 100 33 | SET_PARAMETER use_axi_id false 34 | SET_PARAMETER write_depth_a 256 35 | SET_PARAMETER algorithm Minimum_Area 36 | SET_PARAMETER output_reset_value_a 0 37 | SET_PARAMETER output_reset_value_b 0 38 | SET_PARAMETER error_injection_type Single_Bit_Error_Injection 39 | SET_PARAMETER port_b_write_rate 50 40 | SET_PARAMETER ecctype No_ECC 41 | SET_PARAMETER write_width_a 32 42 | SET_PARAMETER write_width_b 32 43 | SET_PARAMETER component_name data_ram 44 | SET_PARAMETER reset_priority_a CE 45 | SET_PARAMETER reset_priority_b CE 46 | SET_PARAMETER operating_mode_a WRITE_FIRST 47 | SET_PARAMETER additional_inputs_for_power_estimation false 48 | SET_PARAMETER operating_mode_b READ_FIRST 49 | SET_PARAMETER interface_type Native 50 | SET_PARAMETER reset_type SYNC 51 | SET_PARAMETER register_portb_output_of_memory_primitives false 52 | SET_PARAMETER use_rsta_pin false 53 | SET_PARAMETER port_b_enable_rate 100 54 | SET_PARAMETER coe_file no_coe_file_loaded 55 | SET_PARAMETER fill_remaining_memory_locations false 56 | SET_PARAMETER axi_slave_type Memory_Slave 57 | SET_PARAMETER axi_type AXI4_Full 58 | SET_PARAMETER collision_warnings ALL 59 | SET_ERROR_CODE 2 60 | SET_ERROR_MSG CANCEL: Customization cancelled. 61 | SET_ERROR_TEXT Finished initializing IP model. 62 | -------------------------------------------------------------------------------- /Project_2_OC/MemoryOnBoard/ipcore_dir/tmp/_xmsgs/ngcbuild.xmsgs: -------------------------------------------------------------------------------- 1 | 2 | 7 | 8 | 9 | 10 | -------------------------------------------------------------------------------- /Project_2_OC/MemoryOnBoard/ipcore_dir/tmp/_xmsgs/pn_parser.xmsgs: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | Analyzing Verilog file \"F:/Verilog/Project_2_OC/MemoryOnBoard/ipcore_dir/tmp/_cg/data_ram.v\" into library work 12 | 13 | 14 | 15 | 16 | -------------------------------------------------------------------------------- /Project_2_OC/MemoryOnBoard/ipcore_dir/tmp/data_ram.lso: -------------------------------------------------------------------------------- 1 | work 2 | -------------------------------------------------------------------------------- /Project_2_OC/MemoryOnBoard/lcd_module.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Triple-Z/COExperiment_Repo/7a0ad4c5d025753d560e8a433fb26ea406268b1b/Project_2_OC/MemoryOnBoard/lcd_module.v -------------------------------------------------------------------------------- /Project_2_OC/MemoryOnBoard/webtalk.log: -------------------------------------------------------------------------------- 1 | Release 13.2 - WebTalk (O.61xd) 2 | Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. 3 | 4 | WebTalk Summary 5 | ---------------- 6 | INFO:WebTalk:3 - WebTalk is disabled. 7 | 8 | INFO:WebTalk:9 - WebTalk Install setting is OFF. 9 | INFO:WebTalk:6 - WebTalk User setting is ON. 10 | -------------------------------------------------------------------------------- /Project_2_OC/MemoryOnBoard/webtalk_pn.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 6 | 7 |
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43 | 44 | 45 | -------------------------------------------------------------------------------- /Project_2_OC/MemoryOnBoard/xlnx_auto_0_xdb/cst.xbcd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Triple-Z/COExperiment_Repo/7a0ad4c5d025753d560e8a433fb26ea406268b1b/Project_2_OC/MemoryOnBoard/xlnx_auto_0_xdb/cst.xbcd -------------------------------------------------------------------------------- /Project_2_OC/MemoryOnBoard/xst/work/work.sdbl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Triple-Z/COExperiment_Repo/7a0ad4c5d025753d560e8a433fb26ea406268b1b/Project_2_OC/MemoryOnBoard/xst/work/work.sdbl -------------------------------------------------------------------------------- /Project_2_OC/MemoryOnBoard/xst/work/work.sdbx: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Triple-Z/COExperiment_Repo/7a0ad4c5d025753d560e8a433fb26ea406268b1b/Project_2_OC/MemoryOnBoard/xst/work/work.sdbx -------------------------------------------------------------------------------- /Project_2_OC/RegisterFileOnBoard/_ngo/netlist.lst: -------------------------------------------------------------------------------- 1 | F:\Verilog\Project_2_OC\RegisterFileOnBoard\regfile_display.ngc 1497012082 2 | F:\Verilog\Project_2_OC\RegisterFileOnBoard/lcd_module.ngc 1462996372 3 | F:\Verilog\Project_2_OC\RegisterFileOnBoard/lcd_rom.ngc 1462996372 4 | OK 5 | -------------------------------------------------------------------------------- /Project_2_OC/RegisterFileOnBoard/_xmsgs/bitgen.xmsgs: -------------------------------------------------------------------------------- 1 | 2 | 7 | 8 | 9 | 10 | -------------------------------------------------------------------------------- /Project_2_OC/RegisterFileOnBoard/_xmsgs/map.xmsgs: -------------------------------------------------------------------------------- 1 | 2 | 7 | 8 | Logical network N38 has no load. 9 | 10 | 11 | The above info message is repeated 2 more times for the following (max. 5 shown): 12 | N39, 13 | lcd_module/touch_module/int_io/O 14 | To see the details of these info messages, please use the -detail switch. 15 | 16 | 17 | No environment variables are currently set. 18 | 19 | 20 | All of the single ended outputs in this design are using slew rate limited output drivers. The delay on speed critical single ended outputs can be dramatically reduced by designating them as fast outputs. 21 | 22 | 23 | Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius) 24 | 25 | 26 | Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts) 27 | 28 | 29 | The Interim Design Summary has been generated in the MAP Report (.mrp). 30 | 31 | 32 | Map created a placed design. 33 | 34 | 35 | 36 | 37 | -------------------------------------------------------------------------------- /Project_2_OC/RegisterFileOnBoard/_xmsgs/ngdbuild.xmsgs: -------------------------------------------------------------------------------- 1 | 2 | 7 | 8 | logical net 'N38' has no driver 9 | 10 | 11 | logical net 'N39' has no driver 12 | 13 | 14 | 15 | 16 | -------------------------------------------------------------------------------- /Project_2_OC/RegisterFileOnBoard/_xmsgs/par.xmsgs: -------------------------------------------------------------------------------- 1 | 2 | 7 | 8 | 9 | 10 | -------------------------------------------------------------------------------- /Project_2_OC/RegisterFileOnBoard/_xmsgs/pn_parser.xmsgs: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | Analyzing Verilog file \"F:/Verilog/Project_2_OC/RegisterFileOnBoard/lcd_module.v\" into library work 12 | 13 | 14 | Analyzing Verilog file \"F:/Verilog/Project_2_OC/RegisterFileOnBoard/regfile.v\" into library work 15 | 16 | 17 | Analyzing Verilog file \"F:/Verilog/Project_2_OC/RegisterFileOnBoard/regfile_display.v\" into library work 18 | 19 | 20 | 21 | 22 | -------------------------------------------------------------------------------- /Project_2_OC/RegisterFileOnBoard/_xmsgs/trce.xmsgs: -------------------------------------------------------------------------------- 1 | 2 | 7 | 8 | To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report. 9 | 10 | The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet. 11 | 12 | 13 | 14 | -------------------------------------------------------------------------------- /Project_2_OC/RegisterFileOnBoard/lcd_module.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Triple-Z/COExperiment_Repo/7a0ad4c5d025753d560e8a433fb26ea406268b1b/Project_2_OC/RegisterFileOnBoard/lcd_module.v -------------------------------------------------------------------------------- /Project_2_OC/RegisterFileOnBoard/regfile.ucf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Triple-Z/COExperiment_Repo/7a0ad4c5d025753d560e8a433fb26ea406268b1b/Project_2_OC/RegisterFileOnBoard/regfile.ucf -------------------------------------------------------------------------------- /Project_2_OC/RegisterFileOnBoard/regfile.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Triple-Z/COExperiment_Repo/7a0ad4c5d025753d560e8a433fb26ea406268b1b/Project_2_OC/RegisterFileOnBoard/regfile.v -------------------------------------------------------------------------------- /Project_2_OC/RegisterFileOnBoard/regfile_display.bit: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Triple-Z/COExperiment_Repo/7a0ad4c5d025753d560e8a433fb26ea406268b1b/Project_2_OC/RegisterFileOnBoard/regfile_display.bit -------------------------------------------------------------------------------- /Project_2_OC/RegisterFileOnBoard/regfile_display.bld: -------------------------------------------------------------------------------- 1 | Release 13.2 ngdbuild O.61xd (nt64) 2 | Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. 3 | 4 | Command Line: F:\ISE\ISE_DS\ISE\bin\nt64\unwrapped\ngdbuild.exe -intstyle ise 5 | -dd _ngo -nt timestamp -uc regfile.ucf -p xc6slx150-fgg484-3 regfile_display.ngc 6 | regfile_display.ngd 7 | 8 | Reading NGO file 9 | "F:/Verilog/Project_2_OC/RegisterFileOnBoard/regfile_display.ngc" ... 10 | Loading design module 11 | "F:\Verilog\Project_2_OC\RegisterFileOnBoard/lcd_module.ngc"... 12 | Loading design module 13 | "F:\Verilog\Project_2_OC\RegisterFileOnBoard/lcd_rom.ngc"... 14 | Gathering constraint information from source properties... 15 | Done. 16 | 17 | Annotating constraints to design from ucf file "regfile.ucf" ... 18 | Resolving constraint associations... 19 | Checking Constraint Associations... 20 | Done... 21 | 22 | Checking expanded design ... 23 | WARNING:NgdBuild:452 - logical net 'N38' has no driver 24 | WARNING:NgdBuild:452 - logical net 'N39' has no driver 25 | 26 | Partition Implementation Status 27 | ------------------------------- 28 | 29 | No Partitions were found in this design. 30 | 31 | ------------------------------- 32 | 33 | NGDBUILD Design Results Summary: 34 | Number of errors: 0 35 | Number of warnings: 2 36 | 37 | Total memory usage is 161128 kilobytes 38 | 39 | Writing NGD file "regfile_display.ngd" ... 40 | Total REAL time to NGDBUILD completion: 2 sec 41 | Total CPU time to NGDBUILD completion: 2 sec 42 | 43 | Writing NGDBUILD log file "regfile_display.bld"... 44 | -------------------------------------------------------------------------------- /Project_2_OC/RegisterFileOnBoard/regfile_display.cmd_log: -------------------------------------------------------------------------------- 1 | xst -intstyle ise -ifn "F:/Verilog/Project_2_OC/RegisterFileOnBoard/regfile_display.xst" -ofn "F:/Verilog/Project_2_OC/RegisterFileOnBoard/regfile_display.syr" 2 | ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc regfile.ucf -p xc6slx150-fgg484-3 regfile_display.ngc regfile_display.ngd 3 | map -intstyle ise -p xc6slx150-fgg484-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o regfile_display_map.ncd regfile_display.ngd regfile_display.pcf 4 | par -w -intstyle ise -ol high -mt off regfile_display_map.ncd regfile_display.ncd regfile_display.pcf 5 | trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml regfile_display.twx regfile_display.ncd -o regfile_display.twr regfile_display.pcf -ucf regfile.ucf 6 | bitgen -intstyle ise -f regfile_display.ut regfile_display.ncd 7 | xst -intstyle ise -ifn "F:/Verilog/Project_2_OC/RegisterFileOnBoard/regfile_display.xst" -ofn "F:/Verilog/Project_2_OC/RegisterFileOnBoard/regfile_display.syr" 8 | ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc regfile.ucf -p xc6slx150-fgg484-3 regfile_display.ngc regfile_display.ngd 9 | map -intstyle ise -p xc6slx150-fgg484-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o regfile_display_map.ncd regfile_display.ngd regfile_display.pcf 10 | par -w -intstyle ise -ol high -mt off regfile_display_map.ncd regfile_display.ncd regfile_display.pcf 11 | trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml regfile_display.twx regfile_display.ncd -o regfile_display.twr regfile_display.pcf -ucf regfile.ucf 12 | bitgen -intstyle ise -f regfile_display.ut regfile_display.ncd 13 | -------------------------------------------------------------------------------- /Project_2_OC/RegisterFileOnBoard/regfile_display.cpj: -------------------------------------------------------------------------------- 1 | #ChipScope Pro Analyzer Project File, Version 3.0 2 | #Fri Jun 09 20:47:34 CST 2017 3 | mdiAreaHeight=0.7 4 | mdiAreaHeightLast=0.7 5 | mdiCount=0 6 | navigatorHeight=0.18 7 | navigatorHeightLast=0.18 8 | navigatorWidth=0.18 9 | navigatorWidthLast=0.18 10 | signalDisplayPath=0 11 | unit.-1.-1.username= 12 | -------------------------------------------------------------------------------- /Project_2_OC/RegisterFileOnBoard/regfile_display.drc: -------------------------------------------------------------------------------- 1 | Release 13.2 Drc O.61xd (nt64) 2 | Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. 3 | 4 | Fri Jun 09 20:42:48 2017 5 | 6 | drc -z regfile_display.ncd regfile_display.pcf 7 | 8 | DRC detected 0 errors and 0 warnings. 9 | -------------------------------------------------------------------------------- /Project_2_OC/RegisterFileOnBoard/regfile_display.lso: -------------------------------------------------------------------------------- 1 | work 2 | -------------------------------------------------------------------------------- /Project_2_OC/RegisterFileOnBoard/regfile_display.prj: -------------------------------------------------------------------------------- 1 | verilog work "regfile.v" 2 | verilog work "lcd_module.v" 3 | verilog work "regfile_display.v" 4 | -------------------------------------------------------------------------------- /Project_2_OC/RegisterFileOnBoard/regfile_display.stx: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Triple-Z/COExperiment_Repo/7a0ad4c5d025753d560e8a433fb26ea406268b1b/Project_2_OC/RegisterFileOnBoard/regfile_display.stx -------------------------------------------------------------------------------- /Project_2_OC/RegisterFileOnBoard/regfile_display.unroutes: -------------------------------------------------------------------------------- 1 | Release 13.2 - par O.61xd (nt64) 2 | Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. 3 | 4 | Fri Jun 09 20:42:34 2017 5 | 6 | All signals are completely routed. 7 | 8 | 9 | 10 | -------------------------------------------------------------------------------- /Project_2_OC/RegisterFileOnBoard/regfile_display.ut: -------------------------------------------------------------------------------- 1 | -w 2 | -g DebugBitstream:No 3 | -g Binary:no 4 | -g CRC:Enable 5 | -g Reset_on_err:No 6 | -g ConfigRate:2 7 | -g ProgPin:PullUp 8 | -g TckPin:PullUp 9 | -g TdiPin:PullUp 10 | -g TdoPin:PullUp 11 | -g TmsPin:PullUp 12 | -g UnusedPin:PullDown 13 | -g UserID:0xFFFFFFFF 14 | -g ExtMasterCclk_en:No 15 | -g SPI_buswidth:1 16 | -g TIMER_CFG:0xFFFF 17 | -g multipin_wakeup:No 18 | -g StartUpClk:CClk 19 | -g DONE_cycle:4 20 | -g GTS_cycle:5 21 | -g GWE_cycle:6 22 | -g LCK_cycle:NoWait 23 | -g Security:None 24 | -g DonePipe:No 25 | -g DriveDone:No 26 | -g Encrypt:No 27 | -g en_sw_gsr:No 28 | -g drive_awake:No 29 | -g sw_clk:Startupclk 30 | -g sw_gwe_cycle:5 31 | -g sw_gts_cycle:4 32 | -------------------------------------------------------------------------------- /Project_2_OC/RegisterFileOnBoard/regfile_display.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Triple-Z/COExperiment_Repo/7a0ad4c5d025753d560e8a433fb26ea406268b1b/Project_2_OC/RegisterFileOnBoard/regfile_display.v -------------------------------------------------------------------------------- /Project_2_OC/RegisterFileOnBoard/regfile_display.xpi: -------------------------------------------------------------------------------- 1 | PROGRAM=PAR 2 | STATE=ROUTED 3 | TIMESPECS_MET=YES 4 | -------------------------------------------------------------------------------- /Project_2_OC/RegisterFileOnBoard/regfile_display.xst: -------------------------------------------------------------------------------- 1 | set -tmpdir "xst/projnav.tmp" 2 | set -xsthdpdir "xst" 3 | run 4 | -ifn regfile_display.prj 5 | -ifmt mixed 6 | -ofn regfile_display 7 | -ofmt NGC 8 | -p xc6slx150-3-fgg484 9 | -top regfile_display 10 | -opt_mode Speed 11 | -opt_level 1 12 | -power NO 13 | -iuc NO 14 | -keep_hierarchy No 15 | -netlist_hierarchy As_Optimized 16 | -rtlview Yes 17 | -glob_opt AllClockNets 18 | -read_cores YES 19 | -write_timing_constraints NO 20 | -cross_clock_analysis NO 21 | -hierarchy_separator / 22 | -bus_delimiter <> 23 | -case Maintain 24 | -slice_utilization_ratio 100 25 | -bram_utilization_ratio 100 26 | -dsp_utilization_ratio 100 27 | -lc Auto 28 | -reduce_control_sets Auto 29 | -fsm_extract YES -fsm_encoding Auto 30 | -safe_implementation No 31 | -fsm_style LUT 32 | -ram_extract Yes 33 | -ram_style Auto 34 | -rom_extract Yes 35 | -shreg_extract YES 36 | -rom_style Auto 37 | -auto_bram_packing NO 38 | -resource_sharing YES 39 | -async_to_sync NO 40 | -shreg_min_size 2 41 | -use_dsp48 Auto 42 | -iobuf YES 43 | -max_fanout 100000 44 | -bufg 16 45 | -register_duplication YES 46 | -register_balancing No 47 | -optimize_primitives NO 48 | -use_clock_enable Auto 49 | -use_sync_set Auto 50 | -use_sync_reset Auto 51 | -iob Auto 52 | -equivalent_register_removal YES 53 | -slice_utilization_ratio_maxmargin 5 54 | -------------------------------------------------------------------------------- /Project_2_OC/RegisterFileOnBoard/regfile_display_bitgen.xwbt: -------------------------------------------------------------------------------- 1 | INTSTYLE=ise 2 | INFILE=F:\Verilog\Project_2_OC\RegisterFileOnBoard\regfile_display.ncd 3 | OUTFILE=F:\Verilog\Project_2_OC\RegisterFileOnBoard\regfile_display.bit 4 | FAMILY=Spartan6 5 | PART=xc6slx150-3fgg484 6 | WORKINGDIR=F:\Verilog\Project_2_OC\RegisterFileOnBoard 7 | LICENSE=ISE 8 | USER_INFO=135256_15690819_173552794_661 9 | -------------------------------------------------------------------------------- /Project_2_OC/RegisterFileOnBoard/regfile_display_summary.html: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Triple-Z/COExperiment_Repo/7a0ad4c5d025753d560e8a433fb26ea406268b1b/Project_2_OC/RegisterFileOnBoard/regfile_display_summary.html -------------------------------------------------------------------------------- /Project_2_OC/RegisterFileOnBoard/regfile_display_summary.xml: -------------------------------------------------------------------------------- 1 | 2 | 7 | 8 | 9 | 10 | 11 | -------------------------------------------------------------------------------- /Project_2_OC/RegisterFileOnBoard/regfile_summary.html: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Triple-Z/COExperiment_Repo/7a0ad4c5d025753d560e8a433fb26ea406268b1b/Project_2_OC/RegisterFileOnBoard/regfile_summary.html -------------------------------------------------------------------------------- /Project_2_OC/RegisterFileOnBoard/webtalk.log: -------------------------------------------------------------------------------- 1 | Release 13.2 - WebTalk (O.61xd) 2 | Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. 3 | 4 | WebTalk Summary 5 | ---------------- 6 | INFO:WebTalk:3 - WebTalk is disabled. 7 | 8 | INFO:WebTalk:9 - WebTalk Install setting is OFF. 9 | INFO:WebTalk:6 - WebTalk User setting is ON. 10 | -------------------------------------------------------------------------------- /Project_2_OC/RegisterFileOnBoard/webtalk_pn.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 6 | 7 |
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14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 |
42 | 43 | 44 | -------------------------------------------------------------------------------- /Project_2_OC/RegisterFileOnBoard/xlnx_auto_0_xdb/cst.xbcd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Triple-Z/COExperiment_Repo/7a0ad4c5d025753d560e8a433fb26ea406268b1b/Project_2_OC/RegisterFileOnBoard/xlnx_auto_0_xdb/cst.xbcd -------------------------------------------------------------------------------- /Project_2_OC/RegisterFileOnBoard/xst/work/work.sdbl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Triple-Z/COExperiment_Repo/7a0ad4c5d025753d560e8a433fb26ea406268b1b/Project_2_OC/RegisterFileOnBoard/xst/work/work.sdbl -------------------------------------------------------------------------------- /Project_2_OC/RegisterFileOnBoard/xst/work/work.sdbx: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Triple-Z/COExperiment_Repo/7a0ad4c5d025753d560e8a433fb26ea406268b1b/Project_2_OC/RegisterFileOnBoard/xst/work/work.sdbx -------------------------------------------------------------------------------- /Project_2_OC/SingleCycleCPUOnBoard/_ngo/netlist.lst: -------------------------------------------------------------------------------- 1 | F:\Verilog\Project_2_OC\SingleCycleCPUOnBoard\single_cycle_cpu_display.ngc 1497843574 2 | F:\Verilog\Project_2_OC\SingleCycleCPUOnBoard/lcd_module.ngc 1478764461 3 | F:\Verilog\Project_2_OC\SingleCycleCPUOnBoard/lcd_rom.ngc 1460178844 4 | OK 5 | -------------------------------------------------------------------------------- /Project_2_OC/SingleCycleCPUOnBoard/_xmsgs/bitgen.xmsgs: -------------------------------------------------------------------------------- 1 | 2 | 7 | 8 | The signal <lcd_module/touch_module/int_io/O> is incomplete. The signal does not drive any load pins in the design. 9 | 10 | 11 | 12 | 13 | -------------------------------------------------------------------------------- /Project_2_OC/SingleCycleCPUOnBoard/_xmsgs/ngdbuild.xmsgs: -------------------------------------------------------------------------------- 1 | 2 | 7 | 8 | logical net 'N789' has no driver 9 | 10 | 11 | logical net 'N790' has no driver 12 | 13 | 14 | 15 | 16 | -------------------------------------------------------------------------------- /Project_2_OC/SingleCycleCPUOnBoard/_xmsgs/par.xmsgs: -------------------------------------------------------------------------------- 1 | 2 | 7 | 8 | The signal lcd_module/touch_module/int_io/O has no load. PAR will not attempt to route this signal. 9 | 10 | 11 | Unusually high hold time violation detected among 49 connections. The top 20 such instances are printed below. The router will continue and try to fix it 12 | 13 | 14 | There are 1 loadless signals in this design. This design will cause Bitgen to issue DRC warnings. 15 | 16 | 17 | 18 | There are 1 loadless signals in this design. This design will cause Bitgen to issue DRC warnings. 19 | 20 | 21 | 22 | 23 | 24 | -------------------------------------------------------------------------------- /Project_2_OC/SingleCycleCPUOnBoard/_xmsgs/pn_parser.xmsgs: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | Analyzing Verilog file \"F:/Verilog/Project_2_OC/SingleCycleCPUOnBoard/regfile.v\" into library work 12 | 13 | 14 | 15 | 16 | -------------------------------------------------------------------------------- /Project_2_OC/SingleCycleCPUOnBoard/_xmsgs/trce.xmsgs: -------------------------------------------------------------------------------- 1 | 2 | 7 | 8 | To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report. 9 | 10 | The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet. 11 | 12 | 13 | 14 | -------------------------------------------------------------------------------- /Project_2_OC/SingleCycleCPUOnBoard/adder.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Triple-Z/COExperiment_Repo/7a0ad4c5d025753d560e8a433fb26ea406268b1b/Project_2_OC/SingleCycleCPUOnBoard/adder.v -------------------------------------------------------------------------------- /Project_2_OC/SingleCycleCPUOnBoard/alu.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Triple-Z/COExperiment_Repo/7a0ad4c5d025753d560e8a433fb26ea406268b1b/Project_2_OC/SingleCycleCPUOnBoard/alu.v -------------------------------------------------------------------------------- /Project_2_OC/SingleCycleCPUOnBoard/data_ram.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Triple-Z/COExperiment_Repo/7a0ad4c5d025753d560e8a433fb26ea406268b1b/Project_2_OC/SingleCycleCPUOnBoard/data_ram.v -------------------------------------------------------------------------------- /Project_2_OC/SingleCycleCPUOnBoard/inst_rom.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Triple-Z/COExperiment_Repo/7a0ad4c5d025753d560e8a433fb26ea406268b1b/Project_2_OC/SingleCycleCPUOnBoard/inst_rom.v -------------------------------------------------------------------------------- /Project_2_OC/SingleCycleCPUOnBoard/lcd_module.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Triple-Z/COExperiment_Repo/7a0ad4c5d025753d560e8a433fb26ea406268b1b/Project_2_OC/SingleCycleCPUOnBoard/lcd_module.v -------------------------------------------------------------------------------- /Project_2_OC/SingleCycleCPUOnBoard/regfile.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Triple-Z/COExperiment_Repo/7a0ad4c5d025753d560e8a433fb26ea406268b1b/Project_2_OC/SingleCycleCPUOnBoard/regfile.v -------------------------------------------------------------------------------- /Project_2_OC/SingleCycleCPUOnBoard/single_cycle_cpu.ucf: -------------------------------------------------------------------------------- 1 | ############################################################################ 2 | # VCC AUX VOLTAGE 3 | ############################################################################ 4 | CONFIG VCCAUX=3.3; # Valid values are 2.5 and 3.3 5 | 6 | #时钟信号连接 10Mhz 7 | NET "clk" LOC = T1 | IOSTANDARD = "LVCMOS33"; 8 | NET "clk" TNM_NET = clk; 9 | TIMESPEC TS_clk = PERIOD "clk" 100 ns HIGH 50%; 10 | NET "clk" CLOCK_DEDICATED_ROUTE = FALSE; 11 | 12 | #脉冲开关，用于输入作为单步执行的clk 13 | NET "btn_clk" LOC = W7 | IOSTANDARD = "LVCMOS33"; #btn 14 | 15 | #led灯连接，用于输出 16 | 17 | #拨码开关连接，用于输入作为复位信号，低电平有效 18 | NET "resetn" LOC = AB7 | IOSTANDARD = "LVCMOS33"; #sw0 19 | 20 | #触摸屏引脚连接，不需要更 21 | NET "lcd_rst" LOC = B20 | IOSTANDARD = "LVTTL"; 22 | NET "lcd_cs" LOC = A19 | IOSTANDARD = "LVTTL"; 23 | NET "lcd_rs" LOC = A18 | IOSTANDARD = "LVTTL"; 24 | NET "lcd_wr" LOC = A21 | IOSTANDARD = "LVTTL"; 25 | NET "lcd_rd" LOC = B22 | IOSTANDARD = "LVTTL"; 26 | NET "lcd_bl_ctr" LOC = E19 | IOSTANDARD = "LVTTL"; 27 | NET "lcd_data_io[0]" LOC = A22 | IOSTANDARD = "LVTTL"; 28 | NET "lcd_data_io[1]" LOC = B18 | IOSTANDARD = "LVTTL"; 29 | NET "lcd_data_io[2]" LOC = A20 | IOSTANDARD = "LVTTL"; 30 | NET "lcd_data_io[3]" LOC = E16 | IOSTANDARD = "LVTTL"; 31 | NET "lcd_data_io[4]" LOC = A17 | IOSTANDARD = "LVTTL"; 32 | NET "lcd_data_io[5]" LOC = C16 | IOSTANDARD = "LVTTL"; 33 | NET "lcd_data_io[6]" LOC = D16 | IOSTANDARD = "LVTTL"; 34 | NET "lcd_data_io[7]" LOC = C17 | IOSTANDARD = "LVTTL"; 35 | NET "lcd_data_io[8]" LOC = F16 | IOSTANDARD = "LVTTL"; 36 | NET "lcd_data_io[9]" LOC = F17 | IOSTANDARD = "LVTTL"; 37 | NET "lcd_data_io[10]" LOC = E17 | IOSTANDARD = "LVTTL"; 38 | NET "lcd_data_io[11]" LOC = D18 | IOSTANDARD = "LVTTL"; 39 | NET "lcd_data_io[12]" LOC = C18 | IOSTANDARD = "LVTTL"; 40 | NET "lcd_data_io[13]" LOC = C19 | IOSTANDARD = "LVTTL"; 41 | NET "lcd_data_io[14]" LOC = E18 | IOSTANDARD = "LVTTL"; 42 | NET "lcd_data_io[15]" LOC = D19 | IOSTANDARD = "LVTTL"; 43 | NET "ct_int" LOC = D21 | IOSTANDARD = "LVTTL"; 44 | NET "ct_sda" LOC = C20 | IOSTANDARD = "LVTTL"; 45 | NET "ct_scl" LOC = C21 | IOSTANDARD = "LVTTL"; 46 | NET "ct_rstn"LOC = F18 | IOSTANDARD = "LVTTL"; 47 | -------------------------------------------------------------------------------- /Project_2_OC/SingleCycleCPUOnBoard/single_cycle_cpu.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Triple-Z/COExperiment_Repo/7a0ad4c5d025753d560e8a433fb26ea406268b1b/Project_2_OC/SingleCycleCPUOnBoard/single_cycle_cpu.v -------------------------------------------------------------------------------- /Project_2_OC/SingleCycleCPUOnBoard/single_cycle_cpu_display.bit: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Triple-Z/COExperiment_Repo/7a0ad4c5d025753d560e8a433fb26ea406268b1b/Project_2_OC/SingleCycleCPUOnBoard/single_cycle_cpu_display.bit -------------------------------------------------------------------------------- /Project_2_OC/SingleCycleCPUOnBoard/single_cycle_cpu_display.bld: -------------------------------------------------------------------------------- 1 | Release 13.2 ngdbuild O.61xd (nt64) 2 | Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. 3 | 4 | Command Line: F:\ISE\ISE_DS\ISE\bin\nt64\unwrapped\ngdbuild.exe -intstyle ise 5 | -dd _ngo -nt timestamp -uc single_cycle_cpu.ucf -p xc6slx150-fgg676-3 6 | single_cycle_cpu_display.ngc single_cycle_cpu_display.ngd 7 | 8 | Reading NGO file 9 | "F:/Verilog/Project_2_OC/SingleCycleCPUOnBoard/single_cycle_cpu_display.ngc" ... 10 | Loading design module 11 | "F:\Verilog\Project_2_OC\SingleCycleCPUOnBoard/lcd_module.ngc"... 12 | Loading design module 13 | "F:\Verilog\Project_2_OC\SingleCycleCPUOnBoard/lcd_rom.ngc"... 14 | Gathering constraint information from source properties... 15 | Done. 16 | 17 | Annotating constraints to design from ucf file "single_cycle_cpu.ucf" ... 18 | Resolving constraint associations... 19 | Checking Constraint Associations... 20 | Done... 21 | 22 | Checking expanded design ... 23 | WARNING:NgdBuild:452 - logical net 'N789' has no driver 24 | WARNING:NgdBuild:452 - logical net 'N790' has no driver 25 | 26 | Partition Implementation Status 27 | ------------------------------- 28 | 29 | No Partitions were found in this design. 30 | 31 | ------------------------------- 32 | 33 | NGDBUILD Design Results Summary: 34 | Number of errors: 0 35 | Number of warnings: 2 36 | 37 | Total memory usage is 162344 kilobytes 38 | 39 | Writing NGD file "single_cycle_cpu_display.ngd" ... 40 | Total REAL time to NGDBUILD completion: 2 sec 41 | Total CPU time to NGDBUILD completion: 2 sec 42 | 43 | Writing NGDBUILD log file "single_cycle_cpu_display.bld"... 44 | -------------------------------------------------------------------------------- /Project_2_OC/SingleCycleCPUOnBoard/single_cycle_cpu_display.drc: -------------------------------------------------------------------------------- 1 | Release 13.2 Drc O.61xd (nt64) 2 | Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. 3 | 4 | Mon Jun 19 11:41:13 2017 5 | 6 | drc -z single_cycle_cpu_display.ncd single_cycle_cpu_display.pcf 7 | 8 | WARNING:PhysDesignRules:367 - The signal is 9 | incomplete. The signal does not drive any load pins in the design. 10 | DRC detected 0 errors and 1 warnings. Please see the previously displayed 11 | individual error or warning messages for more details. 12 | -------------------------------------------------------------------------------- /Project_2_OC/SingleCycleCPUOnBoard/single_cycle_cpu_display.lso: -------------------------------------------------------------------------------- 1 | work 2 | -------------------------------------------------------------------------------- /Project_2_OC/SingleCycleCPUOnBoard/single_cycle_cpu_display.prj: -------------------------------------------------------------------------------- 1 | verilog work "adder.v" 2 | verilog work "regfile.v" 3 | verilog work "inst_rom.v" 4 | verilog work "data_ram.v" 5 | verilog work "alu.v" 6 | verilog work "single_cycle_cpu.v" 7 | verilog work "lcd_module.v" 8 | verilog work "single_cycle_cpu_display.v" 9 | -------------------------------------------------------------------------------- /Project_2_OC/SingleCycleCPUOnBoard/single_cycle_cpu_display.stx: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Triple-Z/COExperiment_Repo/7a0ad4c5d025753d560e8a433fb26ea406268b1b/Project_2_OC/SingleCycleCPUOnBoard/single_cycle_cpu_display.stx -------------------------------------------------------------------------------- /Project_2_OC/SingleCycleCPUOnBoard/single_cycle_cpu_display.unroutes: -------------------------------------------------------------------------------- 1 | Release 13.2 - par O.61xd (nt64) 2 | Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. 3 | 4 | Mon Jun 19 11:40:55 2017 5 | 6 | All signals are completely routed. 7 | 8 | WARNING:ParHelpers:361 - There are 1 loadless signals in this design. This design will cause Bitgen to issue DRC 9 | warnings. 10 | 11 | lcd_module/touch_module/int_io/O 12 | 13 | 14 | -------------------------------------------------------------------------------- /Project_2_OC/SingleCycleCPUOnBoard/single_cycle_cpu_display.ut: -------------------------------------------------------------------------------- 1 | -w 2 | -g DebugBitstream:No 3 | -g Binary:no 4 | -g CRC:Enable 5 | -g Reset_on_err:No 6 | -g ConfigRate:2 7 | -g ProgPin:PullUp 8 | -g TckPin:PullUp 9 | -g TdiPin:PullUp 10 | -g TdoPin:PullUp 11 | -g TmsPin:PullUp 12 | -g UnusedPin:PullDown 13 | -g UserID:0xFFFFFFFF 14 | -g ExtMasterCclk_en:No 15 | -g SPI_buswidth:1 16 | -g TIMER_CFG:0xFFFF 17 | -g multipin_wakeup:No 18 | -g StartUpClk:CClk 19 | -g DONE_cycle:4 20 | -g GTS_cycle:5 21 | -g GWE_cycle:6 22 | -g LCK_cycle:NoWait 23 | -g Security:None 24 | -g DonePipe:No 25 | -g DriveDone:No 26 | -g Encrypt:No 27 | -g en_sw_gsr:No 28 | -g drive_awake:No 29 | -g sw_clk:Startupclk 30 | -g sw_gwe_cycle:5 31 | -g sw_gts_cycle:4 32 | -------------------------------------------------------------------------------- /Project_2_OC/SingleCycleCPUOnBoard/single_cycle_cpu_display.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Triple-Z/COExperiment_Repo/7a0ad4c5d025753d560e8a433fb26ea406268b1b/Project_2_OC/SingleCycleCPUOnBoard/single_cycle_cpu_display.v -------------------------------------------------------------------------------- /Project_2_OC/SingleCycleCPUOnBoard/single_cycle_cpu_display.xpi: -------------------------------------------------------------------------------- 1 | PROGRAM=PAR 2 | STATE=ROUTED 3 | TIMESPECS_MET=YES 4 | -------------------------------------------------------------------------------- /Project_2_OC/SingleCycleCPUOnBoard/single_cycle_cpu_display.xst: -------------------------------------------------------------------------------- 1 | set -tmpdir "xst/projnav.tmp" 2 | set -xsthdpdir "xst" 3 | run 4 | -ifn single_cycle_cpu_display.prj 5 | -ifmt mixed 6 | -ofn single_cycle_cpu_display 7 | -ofmt NGC 8 | -p xc6slx150-3-fgg676 9 | -top single_cycle_cpu_display 10 | -opt_mode Speed 11 | -opt_level 1 12 | -power NO 13 | -iuc NO 14 | -keep_hierarchy No 15 | -netlist_hierarchy As_Optimized 16 | -rtlview Yes 17 | -glob_opt AllClockNets 18 | -read_cores YES 19 | -write_timing_constraints NO 20 | -cross_clock_analysis NO 21 | -hierarchy_separator / 22 | -bus_delimiter <> 23 | -case Maintain 24 | -slice_utilization_ratio 100 25 | -bram_utilization_ratio 100 26 | -dsp_utilization_ratio 100 27 | -lc Auto 28 | -reduce_control_sets Auto 29 | -fsm_extract YES -fsm_encoding Auto 30 | -safe_implementation No 31 | -fsm_style LUT 32 | -ram_extract Yes 33 | -ram_style Auto 34 | -rom_extract Yes 35 | -shreg_extract YES 36 | -rom_style Auto 37 | -auto_bram_packing NO 38 | -resource_sharing YES 39 | -async_to_sync NO 40 | -shreg_min_size 2 41 | -use_dsp48 Auto 42 | -iobuf YES 43 | -max_fanout 100000 44 | -bufg 16 45 | -register_duplication YES 46 | -register_balancing No 47 | -optimize_primitives NO 48 | -use_clock_enable Auto 49 | -use_sync_set Auto 50 | -use_sync_reset Auto 51 | -iob Auto 52 | -equivalent_register_removal YES 53 | -slice_utilization_ratio_maxmargin 5 54 | -------------------------------------------------------------------------------- /Project_2_OC/SingleCycleCPUOnBoard/single_cycle_cpu_display_bitgen.xwbt: -------------------------------------------------------------------------------- 1 | INTSTYLE=ise 2 | INFILE=F:\Verilog\Project_2_OC\SingleCycleCPUOnBoard\single_cycle_cpu_display.ncd 3 | OUTFILE=F:\Verilog\Project_2_OC\SingleCycleCPUOnBoard\single_cycle_cpu_display.bit 4 | FAMILY=Spartan6 5 | PART=xc6slx150-3fgg676 6 | WORKINGDIR=F:\Verilog\Project_2_OC\SingleCycleCPUOnBoard 7 | LICENSE=ISE 8 | USER_INFO=135256_15690819_173552794_661 9 | -------------------------------------------------------------------------------- /Project_2_OC/SingleCycleCPUOnBoard/single_cycle_cpu_display_summary.html: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Triple-Z/COExperiment_Repo/7a0ad4c5d025753d560e8a433fb26ea406268b1b/Project_2_OC/SingleCycleCPUOnBoard/single_cycle_cpu_display_summary.html -------------------------------------------------------------------------------- /Project_2_OC/SingleCycleCPUOnBoard/single_cycle_cpu_display_summary.xml: -------------------------------------------------------------------------------- 1 | 2 | 7 | 8 | 9 | 10 | 11 | -------------------------------------------------------------------------------- /Project_2_OC/SingleCycleCPUOnBoard/tb.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | //////////////////////////////////////////////////////////////////////////////// 4 | // Company: 5 | // Engineer: 6 | // 7 | // Create Date: 16:49:44 04/19/2016 8 | // Design Name: single_cycle_cpu 9 | // Module Name: F:/new_lab/6_single_cycle_cpu/tb.v 10 | // Project Name: single_cycle_cpu 11 | // Target Device: 12 | // Tool versions: 13 | // Description: 14 | // 15 | // Verilog Test Fixture created by ISE for module: single_cycle_cpu 16 | // 17 | // Dependencies: 18 | // 19 | // Revision: 20 | // Revision 0.01 - File Created 21 | // Additional Comments: 22 | // 23 | //////////////////////////////////////////////////////////////////////////////// 24 | 25 | module tb; 26 | 27 | // Inputs 28 | reg clk; 29 | reg resetn; 30 | reg [4:0] rf_addr; 31 | reg [31:0] mem_addr; 32 | 33 | // Outputs 34 | wire [31:0] rf_data; 35 | wire [31:0] mem_data; 36 | wire [31:0] cpu_pc; 37 | wire [31:0] cpu_inst; 38 | 39 | // Instantiate the Unit Under Test (UUT) 40 | single_cycle_cpu uut ( 41 | .clk(clk), 42 | .resetn(resetn), 43 | .rf_addr(rf_addr), 44 | .mem_addr(mem_addr), 45 | .rf_data(rf_data), 46 | .mem_data(mem_data), 47 | .cpu_pc(cpu_pc), 48 | .cpu_inst(cpu_inst) 49 | ); 50 | 51 | initial begin 52 | // Initialize Inputs 53 | clk = 0; 54 | resetn = 0; 55 | rf_addr = 0; 56 | mem_addr = 0; 57 | 58 | // Wait 100 ns for global reset to finish 59 | #100; 60 | resetn = 1; 61 | // Add stimulus here 62 | end 63 | always #5 clk=~clk; 64 | endmodule 65 | 66 | -------------------------------------------------------------------------------- /Project_2_OC/SingleCycleCPUOnBoard/webtalk.log: -------------------------------------------------------------------------------- 1 | Release 13.2 - WebTalk (O.61xd) 2 | Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. 3 | 4 | WebTalk Summary 5 | ---------------- 6 | INFO:WebTalk:3 - WebTalk is disabled. 7 | 8 | INFO:WebTalk:9 - WebTalk Install setting is OFF. 9 | INFO:WebTalk:6 - WebTalk User setting is ON. 10 | -------------------------------------------------------------------------------- /Project_2_OC/SingleCycleCPUOnBoard/webtalk_pn.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 6 | 7 |
8 | 9 | 10 | 11 | 12 |
13 |
14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 |
42 | 43 | 44 | -------------------------------------------------------------------------------- /Project_2_OC/SingleCycleCPUOnBoard/xlnx_auto_0_xdb/cst.xbcd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Triple-Z/COExperiment_Repo/7a0ad4c5d025753d560e8a433fb26ea406268b1b/Project_2_OC/SingleCycleCPUOnBoard/xlnx_auto_0_xdb/cst.xbcd -------------------------------------------------------------------------------- /Project_2_OC/SingleCycleCPUOnBoard/xst/work/work.sdbl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Triple-Z/COExperiment_Repo/7a0ad4c5d025753d560e8a433fb26ea406268b1b/Project_2_OC/SingleCycleCPUOnBoard/xst/work/work.sdbl -------------------------------------------------------------------------------- /Project_2_OC/SingleCycleCPUOnBoard/xst/work/work.sdbx: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Triple-Z/COExperiment_Repo/7a0ad4c5d025753d560e8a433fb26ea406268b1b/Project_2_OC/SingleCycleCPUOnBoard/xst/work/work.sdbx -------------------------------------------------------------------------------- /Project_2_OC/TestProject/_ngo/netlist.lst: -------------------------------------------------------------------------------- 1 | F:\Verilog\Project_2_OC\TestProject\adder_display.ngc 1497010035 2 | F:\Verilog\Project_2_OC\TestProject/lcd_module.ngc 1462996372 3 | F:\Verilog\Project_2_OC\TestProject/lcd_rom.ngc 1462996372 4 | OK 5 | -------------------------------------------------------------------------------- /Project_2_OC/TestProject/_xmsgs/bitgen.xmsgs: -------------------------------------------------------------------------------- 1 | 2 | 7 | 8 | 9 | 10 | -------------------------------------------------------------------------------- /Project_2_OC/TestProject/_xmsgs/map.xmsgs: -------------------------------------------------------------------------------- 1 | 2 | 7 | 8 | Logical network N35 has no load. 9 | 10 | 11 | The above info message is repeated 2 more times for the following (max. 5 shown): 12 | N36, 13 | lcd_module/touch_module/int_io/O 14 | To see the details of these info messages, please use the -detail switch. 15 | 16 | 17 | No environment variables are currently set. 18 | 19 | 20 | All of the single ended outputs in this design are using slew rate limited output drivers. The delay on speed critical single ended outputs can be dramatically reduced by designating them as fast outputs. 21 | 22 | 23 | Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius) 24 | 25 | 26 | Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts) 27 | 28 | 29 | The Interim Design Summary has been generated in the MAP Report (.mrp). 30 | 31 | 32 | Map created a placed design. 33 | 34 | 35 | 36 | 37 | -------------------------------------------------------------------------------- /Project_2_OC/TestProject/_xmsgs/ngdbuild.xmsgs: -------------------------------------------------------------------------------- 1 | 2 | 7 | 8 | logical net 'N35' has no driver 9 | 10 | 11 | logical net 'N36' has no driver 12 | 13 | 14 | 15 | 16 | -------------------------------------------------------------------------------- /Project_2_OC/TestProject/_xmsgs/par.xmsgs: -------------------------------------------------------------------------------- 1 | 2 | 7 | 8 | 9 | 10 | -------------------------------------------------------------------------------- /Project_2_OC/TestProject/_xmsgs/pn_parser.xmsgs: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | Analyzing Verilog file \"F:/Verilog/Project_2_OC/TestProject/adder.v\" into library work 12 | 13 | 14 | Analyzing Verilog file \"F:/Verilog/Project_2_OC/TestProject/adder_display.v\" into library work 15 | 16 | 17 | Analyzing Verilog file \"F:/Verilog/Project_2_OC/TestProject/lcd_module.v\" into library work 18 | 19 | 20 | 21 | 22 | -------------------------------------------------------------------------------- /Project_2_OC/TestProject/_xmsgs/trce.xmsgs: -------------------------------------------------------------------------------- 1 | 2 | 7 | 8 | To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report. 9 | 10 | The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet. 11 | 12 | 13 | 14 | -------------------------------------------------------------------------------- /Project_2_OC/TestProject/adder.ucf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Triple-Z/COExperiment_Repo/7a0ad4c5d025753d560e8a433fb26ea406268b1b/Project_2_OC/TestProject/adder.ucf -------------------------------------------------------------------------------- /Project_2_OC/TestProject/adder.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Triple-Z/COExperiment_Repo/7a0ad4c5d025753d560e8a433fb26ea406268b1b/Project_2_OC/TestProject/adder.v -------------------------------------------------------------------------------- /Project_2_OC/TestProject/adder_display.bit: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Triple-Z/COExperiment_Repo/7a0ad4c5d025753d560e8a433fb26ea406268b1b/Project_2_OC/TestProject/adder_display.bit -------------------------------------------------------------------------------- /Project_2_OC/TestProject/adder_display.bld: -------------------------------------------------------------------------------- 1 | Release 13.2 ngdbuild O.61xd (nt64) 2 | Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. 3 | 4 | Command Line: F:\ISE\ISE_DS\ISE\bin\nt64\unwrapped\ngdbuild.exe -intstyle ise 5 | -dd _ngo -nt timestamp -uc adder.ucf -p xc6slx150-fgg484-3 adder_display.ngc 6 | adder_display.ngd 7 | 8 | Reading NGO file "F:/Verilog/Project_2_OC/TestProject/adder_display.ngc" ... 9 | Loading design module "F:\Verilog\Project_2_OC\TestProject/lcd_module.ngc"... 10 | Loading design module "F:\Verilog\Project_2_OC\TestProject/lcd_rom.ngc"... 11 | Gathering constraint information from source properties... 12 | Done. 13 | 14 | Annotating constraints to design from ucf file "adder.ucf" ... 15 | Resolving constraint associations... 16 | Checking Constraint Associations... 17 | Done... 18 | 19 | Checking expanded design ... 20 | WARNING:NgdBuild:452 - logical net 'N35' has no driver 21 | WARNING:NgdBuild:452 - logical net 'N36' has no driver 22 | 23 | Partition Implementation Status 24 | ------------------------------- 25 | 26 | No Partitions were found in this design. 27 | 28 | ------------------------------- 29 | 30 | NGDBUILD Design Results Summary: 31 | Number of errors: 0 32 | Number of warnings: 2 33 | 34 | Total memory usage is 153320 kilobytes 35 | 36 | Writing NGD file "adder_display.ngd" ... 37 | Total REAL time to NGDBUILD completion: 3 sec 38 | Total CPU time to NGDBUILD completion: 2 sec 39 | 40 | Writing NGDBUILD log file "adder_display.bld"... 41 | -------------------------------------------------------------------------------- /Project_2_OC/TestProject/adder_display.cmd_log: -------------------------------------------------------------------------------- 1 | xst -intstyle ise -ifn "F:/Verilog/Project_2_OC/TestProject/adder_display.xst" -ofn "F:/Verilog/Project_2_OC/TestProject/adder_display.syr" 2 | ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc adder.ucf -p xc6slx150-fgg484-3 adder_display.ngc adder_display.ngd 3 | map -intstyle ise -p xc6slx150-fgg484-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o adder_display_map.ncd adder_display.ngd adder_display.pcf 4 | par -w -intstyle ise -ol high -mt off adder_display_map.ncd adder_display.ncd adder_display.pcf 5 | trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml adder_display.twx adder_display.ncd -o adder_display.twr adder_display.pcf -ucf adder.ucf 6 | bitgen -intstyle ise -f adder_display.ut adder_display.ncd 7 | bitgen -intstyle ise -f adder_display.ut adder_display.ncd 8 | -------------------------------------------------------------------------------- /Project_2_OC/TestProject/adder_display.cpj: -------------------------------------------------------------------------------- 1 | #ChipScope Pro Analyzer Project File, Version 3.0 2 | #Fri Jun 09 20:12:54 CST 2017 3 | device.0.configFileDir=F\:\\Verilog\\Project_2_OC\\TestProject 4 | device.0.configFilename=adder_display.bit 5 | device.0.inserterCDCFileDir=F\:\\Verilog\\Project_2_OC\\TestProject 6 | device.0.inserterCDCFilename= 7 | deviceChain.deviceName0=XC6SLX150 8 | deviceChain.iRLength0=6 9 | deviceChain.name0=MyDevice0 10 | deviceIds=4401d093 11 | mdiAreaHeight=0.7 12 | mdiAreaHeightLast=0.7 13 | mdiCount=0 14 | navigatorHeight=0.17875 15 | navigatorHeightLast=0.18 16 | navigatorWidth=0.18 17 | navigatorWidthLast=0.18 18 | signalDisplayPath=0 19 | unit.-1.-1.username= 20 | -------------------------------------------------------------------------------- /Project_2_OC/TestProject/adder_display.drc: -------------------------------------------------------------------------------- 1 | Release 13.2 Drc O.61xd (nt64) 2 | Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. 3 | 4 | Thu Jun 15 18:48:14 2017 5 | 6 | drc -z adder_display.ncd adder_display.pcf 7 | 8 | DRC detected 0 errors and 0 warnings. 9 | -------------------------------------------------------------------------------- /Project_2_OC/TestProject/adder_display.lso: -------------------------------------------------------------------------------- 1 | work 2 | -------------------------------------------------------------------------------- /Project_2_OC/TestProject/adder_display.prj: -------------------------------------------------------------------------------- 1 | verilog work "lcd_module.v" 2 | verilog work "adder.v" 3 | verilog work "adder_display.v" 4 | -------------------------------------------------------------------------------- /Project_2_OC/TestProject/adder_display.stx: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Triple-Z/COExperiment_Repo/7a0ad4c5d025753d560e8a433fb26ea406268b1b/Project_2_OC/TestProject/adder_display.stx -------------------------------------------------------------------------------- /Project_2_OC/TestProject/adder_display.unroutes: -------------------------------------------------------------------------------- 1 | Release 13.2 - par O.61xd (nt64) 2 | Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. 3 | 4 | Fri Jun 09 20:08:07 2017 5 | 6 | All signals are completely routed. 7 | 8 | 9 | 10 | -------------------------------------------------------------------------------- /Project_2_OC/TestProject/adder_display.ut: -------------------------------------------------------------------------------- 1 | -w 2 | -g DebugBitstream:No 3 | -g Binary:no 4 | -g CRC:Enable 5 | -g Reset_on_err:No 6 | -g ConfigRate:2 7 | -g ProgPin:PullUp 8 | -g TckPin:PullUp 9 | -g TdiPin:PullUp 10 | -g TdoPin:PullUp 11 | -g TmsPin:PullUp 12 | -g UnusedPin:PullDown 13 | -g UserID:0xFFFFFFFF 14 | -g ExtMasterCclk_en:No 15 | -g SPI_buswidth:1 16 | -g TIMER_CFG:0xFFFF 17 | -g multipin_wakeup:No 18 | -g StartUpClk:CClk 19 | -g DONE_cycle:4 20 | -g GTS_cycle:5 21 | -g GWE_cycle:6 22 | -g LCK_cycle:NoWait 23 | -g Security:None 24 | -g DonePipe:No 25 | -g DriveDone:No 26 | -g Encrypt:No 27 | -g en_sw_gsr:No 28 | -g drive_awake:No 29 | -g sw_clk:Startupclk 30 | -g sw_gwe_cycle:5 31 | -g sw_gts_cycle:4 32 | -------------------------------------------------------------------------------- /Project_2_OC/TestProject/adder_display.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Triple-Z/COExperiment_Repo/7a0ad4c5d025753d560e8a433fb26ea406268b1b/Project_2_OC/TestProject/adder_display.v -------------------------------------------------------------------------------- /Project_2_OC/TestProject/adder_display.xpi: -------------------------------------------------------------------------------- 1 | PROGRAM=PAR 2 | STATE=ROUTED 3 | TIMESPECS_MET=YES 4 | -------------------------------------------------------------------------------- /Project_2_OC/TestProject/adder_display.xst: -------------------------------------------------------------------------------- 1 | set -tmpdir "xst/projnav.tmp" 2 | set -xsthdpdir "xst" 3 | run 4 | -ifn adder_display.prj 5 | -ifmt mixed 6 | -ofn adder_display 7 | -ofmt NGC 8 | -p xc6slx150-3-fgg484 9 | -top adder_display 10 | -opt_mode Speed 11 | -opt_level 1 12 | -power NO 13 | -iuc NO 14 | -keep_hierarchy No 15 | -netlist_hierarchy As_Optimized 16 | -rtlview Yes 17 | -glob_opt AllClockNets 18 | -read_cores YES 19 | -write_timing_constraints NO 20 | -cross_clock_analysis NO 21 | -hierarchy_separator / 22 | -bus_delimiter <> 23 | -case Maintain 24 | -slice_utilization_ratio 100 25 | -bram_utilization_ratio 100 26 | -dsp_utilization_ratio 100 27 | -lc Auto 28 | -reduce_control_sets Auto 29 | -fsm_extract YES -fsm_encoding Auto 30 | -safe_implementation No 31 | -fsm_style LUT 32 | -ram_extract Yes 33 | -ram_style Auto 34 | -rom_extract Yes 35 | -shreg_extract YES 36 | -rom_style Auto 37 | -auto_bram_packing NO 38 | -resource_sharing YES 39 | -async_to_sync NO 40 | -shreg_min_size 2 41 | -use_dsp48 Auto 42 | -iobuf YES 43 | -max_fanout 100000 44 | -bufg 16 45 | -register_duplication YES 46 | -register_balancing No 47 | -optimize_primitives NO 48 | -use_clock_enable Auto 49 | -use_sync_set Auto 50 | -use_sync_reset Auto 51 | -iob Auto 52 | -equivalent_register_removal YES 53 | -slice_utilization_ratio_maxmargin 5 54 | -------------------------------------------------------------------------------- /Project_2_OC/TestProject/adder_display_bitgen.xwbt: -------------------------------------------------------------------------------- 1 | INTSTYLE=ise 2 | INFILE=F:\Verilog\Project_2_OC\TestProject\adder_display.ncd 3 | OUTFILE=F:\Verilog\Project_2_OC\TestProject\adder_display.bit 4 | FAMILY=Spartan6 5 | PART=xc6slx150-3fgg484 6 | WORKINGDIR=F:\Verilog\Project_2_OC\TestProject 7 | LICENSE=ISE 8 | USER_INFO=135256_15690819_173552794_661 9 | -------------------------------------------------------------------------------- /Project_2_OC/TestProject/adder_display_summary.html: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Triple-Z/COExperiment_Repo/7a0ad4c5d025753d560e8a433fb26ea406268b1b/Project_2_OC/TestProject/adder_display_summary.html -------------------------------------------------------------------------------- /Project_2_OC/TestProject/adder_display_summary.xml: -------------------------------------------------------------------------------- 1 | 2 | 7 | 8 | 9 | 10 | 11 | -------------------------------------------------------------------------------- /Project_2_OC/TestProject/adder_summary.html: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Triple-Z/COExperiment_Repo/7a0ad4c5d025753d560e8a433fb26ea406268b1b/Project_2_OC/TestProject/adder_summary.html -------------------------------------------------------------------------------- /Project_2_OC/TestProject/fuse.log: -------------------------------------------------------------------------------- 1 | Running: F:\ISE\ISE_DS\ISE\bin\nt64\unwrapped\fuse.exe -intstyle ise -incremental -lib unisims_ver -lib unimacro_ver -lib xilinxcorelib_ver -lib secureip -o F:/Verilog/Project_2_OC/TestProject/testbench_isim_beh.exe -prj F:/Verilog/Project_2_OC/TestProject/testbench_beh.prj work.testbench work.glbl 2 | ISim O.61xd (signature 0x1cce1bb2) 3 | Number of CPUs detected in this system: 8 4 | Turning on mult-threading, number of parallel sub-compilation jobs: 16 5 | Determining compilation order of HDL files 6 | Analyzing Verilog file \"F:/Verilog/Project_2_OC/TestProject/adder.v\" into library work 7 | Analyzing Verilog file \"F:/Verilog/Project_2_OC/TestProject/testbench.v\" into library work 8 | Analyzing Verilog file \"F:/ISE/ISE_DS/ISE//verilog/src/glbl.v\" into library work 9 | Starting static elaboration 10 | Completed static elaboration 11 | Compiling module adder 12 | Compiling module testbench 13 | Compiling module glbl 14 | Time Resolution for simulation is 1ps. 15 | Waiting for 1 sub-compilation(s) to finish... 16 | Compiled 3 Verilog Units 17 | Built simulation executable F:/Verilog/Project_2_OC/TestProject/testbench_isim_beh.exe 18 | Fuse Memory Usage: 19188 KB 19 | Fuse CPU Usage: 77 ms 20 | -------------------------------------------------------------------------------- /Project_2_OC/TestProject/fuse.xmsgs: -------------------------------------------------------------------------------- 1 | 2 | 7 | 8 | 9 | 10 | -------------------------------------------------------------------------------- /Project_2_OC/TestProject/fuseRelaunch.cmd: -------------------------------------------------------------------------------- 1 | -intstyle "ise" -incremental -lib "unisims_ver" -lib "unimacro_ver" -lib "xilinxcorelib_ver" -lib "secureip" -o "F:/Verilog/Project_2_OC/TestProject/testbench_isim_beh.exe" -prj "F:/Verilog/Project_2_OC/TestProject/testbench_beh.prj" "work.testbench" "work.glbl" 2 | -------------------------------------------------------------------------------- /Project_2_OC/TestProject/isim.cmd: -------------------------------------------------------------------------------- 1 | onerror {resume} 2 | wave add / 3 | run 1000 ns; 4 | -------------------------------------------------------------------------------- /Project_2_OC/TestProject/isim.log: -------------------------------------------------------------------------------- 1 | ISim log file 2 | Running: F:\Verilog\Project_2_OC\TestProject\testbench_isim_beh.exe -intstyle ise -gui -tclbatch isim.cmd -wdb F:/Verilog/Project_2_OC/TestProject/testbench_isim_beh.wdb 3 | ISim O.61xd (signature 0x1cce1bb2) 4 | ---------------------------------------------------------------------- 5 | INFO:Security:50 - The XILINXD_LICENSE_FILE environment variable is set to 'F:\ISE\ISE_DS\license.lic'. 6 | INFO:Security:52 - The LM_LICENSE_FILE environment variable is set to 'D:\ModelSim\win32\LICENSE.TXT'. 7 | WARNING:Security:43 - No license file was found in the standard Xilinx license directory. 8 | WARNING:Security:44 - No license file was found. 9 | Please run the Xilinx License Configuration Manager 10 | (xlcm or "Manage Xilinx Licenses") 11 | to assist in obtaining a license. 12 | WARNING:Security:42 - Your software subscription period has lapsed. Your current version of Xilinx tools will continue to function, but you no longer qualify for Xilinx software updates or new releases. 13 | 14 | 15 | ---------------------------------------------------------------------- 16 | This is a Full version of ISim. 17 | Time resolution is 1 ps 18 | # onerror resume 19 | # wave add / 20 | # run 1000 ns 21 | Simulator is doing circuit initialization process. 22 | Finished circuit initialization process. 23 | -------------------------------------------------------------------------------- /Project_2_OC/TestProject/isim/isim_usage_statistics.html: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 |
ISim Statistics
Xilinx HDL Libraries Used=
Fuse Resource Usage=77 ms, 19188 KB
Total Signals=19
Total Nets=110
Total Blocks=3
Total Processes=14
Total Simulation Time=1 us
Simulation Resource Usage=0.280801 sec, 478322 KB
Simulation Mode=gui
Hardware CoSim=0
17 | -------------------------------------------------------------------------------- /Project_2_OC/TestProject/isim/pn_info: -------------------------------------------------------------------------------- 1 | 13.2 2 | -------------------------------------------------------------------------------- /Project_2_OC/TestProject/isim/temp/adder.sdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Triple-Z/COExperiment_Repo/7a0ad4c5d025753d560e8a433fb26ea406268b1b/Project_2_OC/TestProject/isim/temp/adder.sdb -------------------------------------------------------------------------------- /Project_2_OC/TestProject/isim/temp/glbl.sdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Triple-Z/COExperiment_Repo/7a0ad4c5d025753d560e8a433fb26ea406268b1b/Project_2_OC/TestProject/isim/temp/glbl.sdb -------------------------------------------------------------------------------- /Project_2_OC/TestProject/isim/temp/testbench.sdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Triple-Z/COExperiment_Repo/7a0ad4c5d025753d560e8a433fb26ea406268b1b/Project_2_OC/TestProject/isim/temp/testbench.sdb -------------------------------------------------------------------------------- /Project_2_OC/TestProject/isim/testbench_isim_beh.exe.sim/ISimEngine-DesignHierarchy.dbg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Triple-Z/COExperiment_Repo/7a0ad4c5d025753d560e8a433fb26ea406268b1b/Project_2_OC/TestProject/isim/testbench_isim_beh.exe.sim/ISimEngine-DesignHierarchy.dbg -------------------------------------------------------------------------------- /Project_2_OC/TestProject/isim/testbench_isim_beh.exe.sim/isimcrash.log: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Triple-Z/COExperiment_Repo/7a0ad4c5d025753d560e8a433fb26ea406268b1b/Project_2_OC/TestProject/isim/testbench_isim_beh.exe.sim/isimcrash.log -------------------------------------------------------------------------------- /Project_2_OC/TestProject/isim/testbench_isim_beh.exe.sim/isimkernel.log: -------------------------------------------------------------------------------- 1 | Command line: 2 | testbench_isim_beh.exe 3 | -simmode gui 4 | -simrunnum 0 5 | -socket 5170 6 | 7 | Fri Jun 09 20:05:07 2017 8 | 9 | 10 | Elaboration Time: 0.280801 sec 11 | 12 | Current Memory Usage: 503.382 Meg 13 | 14 | Total Signals : 19 15 | Total Nets : 110 16 | Total Signal Drivers : 10 17 | Total Blocks : 3 18 | Total Primitive Blocks : 2 19 | Total Processes : 14 20 | Total Traceable Variables : 21 21 | Total Scalar Nets and Variables : 255 22 | 23 | Total Simulation Time: 0.280801 sec 24 | 25 | Current Memory Usage: 503.382 Meg 26 | 27 | Fri Jun 09 20:05:17 2017 28 | 29 | -------------------------------------------------------------------------------- /Project_2_OC/TestProject/isim/testbench_isim_beh.exe.sim/libPortability.dll: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Triple-Z/COExperiment_Repo/7a0ad4c5d025753d560e8a433fb26ea406268b1b/Project_2_OC/TestProject/isim/testbench_isim_beh.exe.sim/libPortability.dll -------------------------------------------------------------------------------- /Project_2_OC/TestProject/isim/testbench_isim_beh.exe.sim/netId.dat: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Triple-Z/COExperiment_Repo/7a0ad4c5d025753d560e8a433fb26ea406268b1b/Project_2_OC/TestProject/isim/testbench_isim_beh.exe.sim/netId.dat -------------------------------------------------------------------------------- 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-------------------------------------------------------------------------------- 1 | /**********************************************************************/ 2 | /* ____ ____ */ 3 | /* / /\/ / */ 4 | /* /___/ \ / */ 5 | /* \ \ \/ */ 6 | /* \ \ Copyright (c) 2003-2009 Xilinx, Inc. */ 7 | /* / / All Right Reserved. */ 8 | /* /---/ /\ */ 9 | /* \ \ / \ */ 10 | /* \___\/\___\ */ 11 | /***********************************************************************/ 12 | 13 | /* This file is designed for use with ISim build 0x1cce1bb2 */ 14 | 15 | #define XSI_HIDE_SYMBOL_SPEC true 16 | #include "xsi.h" 17 | #include 18 | #ifdef __GNUC__ 19 | #include 20 | #else 21 | #include 22 | #define alloca _alloca 23 | #endif 24 | static const char *ng0 = "F:/Verilog/Project_2_OC/TestProject/adder.v"; 25 | 26 | 27 | 28 | static void Cont_15_0(char *t0) 29 | { 30 | char t5[16]; 31 | char t7[16]; 32 | char *t1; 33 | char *t2; 34 | char *t3; 35 | char *t4; 36 | char *t6; 37 | char *t8; 38 | char *t9; 39 | char *t10; 40 | char *t11; 41 | char *t12; 42 | char *t13; 43 | char *t14; 44 | char *t15; 45 | char *t16; 46 | char *t17; 47 | 48 | LAB0: t1 = (t0 + 2848U); 49 | t2 = *((char **)t1); 50 | if (t2 == 0) 51 | goto LAB2; 52 | 53 | LAB3: goto *t2; 54 | 55 | LAB2: xsi_set_current_line(15, ng0); 56 | t2 = (t0 + 1048U); 57 | t3 = *((char **)t2); 58 | t2 = (t0 + 1208U); 59 | t4 = *((char **)t2); 60 | xsi_vlog_unsigned_add(t5, 33, t3, 32, t4, 32); 61 | t2 = (t0 + 1368U); 62 | t6 = *((char **)t2); 63 | xsi_vlog_unsigned_add(t7, 33, t5, 33, t6, 1); 64 | t2 = (t0 + 3312); 65 | t8 = (t2 + 56U); 66 | t9 = *((char **)t8); 67 | t10 = (t9 + 56U); 68 | t11 = *((char **)t10); 69 | xsi_vlog_bit_copy(t11, 0, t7, 0, 32); 70 | xsi_driver_vfirst_trans(t2, 0, 31); 71 | t12 = (t0 + 3248); 72 | t13 = (t12 + 56U); 73 | t14 = *((char **)t13); 74 | t15 = (t14 + 56U); 75 | t16 = *((char **)t15); 76 | xsi_vlog_bit_copy(t16, 0, t7, 32, 1); 77 | xsi_driver_vfirst_trans(t12, 0, 0); 78 | t17 = (t0 + 3168); 79 | *((int *)t17) = 1; 80 | 81 | LAB1: return; 82 | } 83 | 84 | 85 | extern void work_m_00000000003717066445_0833183191_init() 86 | { 87 | static char *pe[] = {(void *)Cont_15_0}; 88 | xsi_register_didat("work_m_00000000003717066445_0833183191", "isim/testbench_isim_beh.exe.sim/work/m_00000000003717066445_0833183191.didat"); 89 | xsi_register_executes(pe); 90 | } 91 | -------------------------------------------------------------------------------- /Project_2_OC/TestProject/isim/testbench_isim_beh.exe.sim/work/m_00000000003717066445_0833183191.didat: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Triple-Z/COExperiment_Repo/7a0ad4c5d025753d560e8a433fb26ea406268b1b/Project_2_OC/TestProject/isim/testbench_isim_beh.exe.sim/work/m_00000000003717066445_0833183191.didat -------------------------------------------------------------------------------- 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/Project_2_OC/TestProject/isim/testbench_isim_beh.exe.sim/work/m_00000000004093713498_2073120511.nt64.obj: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Triple-Z/COExperiment_Repo/7a0ad4c5d025753d560e8a433fb26ea406268b1b/Project_2_OC/TestProject/isim/testbench_isim_beh.exe.sim/work/m_00000000004093713498_2073120511.nt64.obj -------------------------------------------------------------------------------- /Project_2_OC/TestProject/isim/testbench_isim_beh.exe.sim/work/testbench_isim_beh.exe_main.c: -------------------------------------------------------------------------------- 1 | /**********************************************************************/ 2 | /* ____ ____ */ 3 | /* / /\/ / */ 4 | /* /___/ \ / */ 5 | /* \ \ \/ */ 6 | /* \ \ Copyright (c) 2003-2009 Xilinx, Inc. */ 7 | /* / / All Right Reserved. */ 8 | /* /---/ /\ */ 9 | /* \ \ / \ */ 10 | /* \___\/\___\ */ 11 | /***********************************************************************/ 12 | 13 | #include "xsi.h" 14 | 15 | struct XSI_INFO xsi_info; 16 | 17 | 18 | 19 | int main(int argc, char **argv) 20 | { 21 | xsi_init_design(argc, argv); 22 | xsi_register_info(&xsi_info); 23 | 24 | xsi_register_min_prec_unit(-12); 25 | work_m_00000000003717066445_0833183191_init(); 26 | work_m_00000000002451488663_1949178628_init(); 27 | work_m_00000000004093713498_2073120511_init(); 28 | 29 | 30 | xsi_register_tops("work_m_00000000002451488663_1949178628"); 31 | xsi_register_tops("work_m_00000000004093713498_2073120511"); 32 | 33 | 34 | return xsi_run_simulation(argc, argv); 35 | 36 | } 37 | -------------------------------------------------------------------------------- /Project_2_OC/TestProject/isim/testbench_isim_beh.exe.sim/work/testbench_isim_beh.exe_main.nt64.obj: -------------------------------------------------------------------------------- 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-------------------------------------------------------------------------------- /Project_2_OC/TestProject/mux4_1.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 19:45:16 06/09/2017 7 | // Design Name: 8 | // Module Name: mux4_1 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module mux4_1( 22 | input sw6_a1, 23 | input sw5_a0, 24 | input sw4_d4, 25 | input sw3_d3, 26 | input sw2_d2, 27 | input sw1_d1, 28 | output led8_out 29 | ); 30 | 31 | assign led8_out = sw1_d1 & (!sw6_a1) & (!sw5_a0) | sw2_d2 & (!sw6_a1) & (sw5_a0) | sw3_d3 & (sw6_a1) & (!sw5_a0) | sw4_d4 & (sw6_a1) & (sw5_a0); 32 | 33 | 34 | endmodule 35 | -------------------------------------------------------------------------------- /Project_2_OC/TestProject/mux4_1_summary.html: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Triple-Z/COExperiment_Repo/7a0ad4c5d025753d560e8a433fb26ea406268b1b/Project_2_OC/TestProject/mux4_1_summary.html -------------------------------------------------------------------------------- /Project_2_OC/TestProject/testbench.cmd_log: -------------------------------------------------------------------------------- 1 | vhdtdtfi -lang verilog -prj TestProject -o F:/Verilog/Project_2_OC/TestProject/testbench.tfi -lib work F:/Verilog/Project_2_OC/TestProject//testbench.v -module testbench -template F:/ISE/ISE_DS/ISE//data/tfi.tft -deleteonerror 2 | -------------------------------------------------------------------------------- /Project_2_OC/TestProject/testbench.lso: -------------------------------------------------------------------------------- 1 | work 2 | -------------------------------------------------------------------------------- /Project_2_OC/TestProject/testbench.prj: -------------------------------------------------------------------------------- 1 | verilog work "adder.v" 2 | verilog work "testbench.v" 3 | -------------------------------------------------------------------------------- /Project_2_OC/TestProject/testbench.stx: -------------------------------------------------------------------------------- 1 | Release 13.2 - xst O.61xd (nt64) 2 | Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. 3 | --> Parameter TMPDIR set to F:/Verilog/Project_2_OC/TestProject/xst/projnav.tmp 4 | 5 | 6 | Total REAL time to Xst completion: 0.00 secs 7 | Total CPU time to Xst completion: 0.15 secs 8 | 9 | --> Parameter xsthdpdir set to F:/Verilog/Project_2_OC/TestProject/xst 10 | 11 | 12 | Total REAL time to Xst completion: 0.00 secs 13 | Total CPU time to Xst completion: 0.15 secs 14 | 15 | --> Reading design: testbench.prj 16 | 17 | TABLE OF CONTENTS 18 | 1) Synthesis Options Summary 19 | 2) HDL Parsing 20 | 3) HDL Elaboration 21 | 4) HDL Synthesis 22 | 4.1) HDL Synthesis Report 23 | 5) Advanced HDL Synthesis 24 | 5.1) Advanced HDL Synthesis Report 25 | 6) Low Level Synthesis 26 | 7) Partition Report 27 | 8) Design Summary 28 | 8.1) Primitive and Black Box Usage 29 | 8.2) Device utilization summary 30 | 8.3) Partition Resource Summary 31 | 8.4) Timing Report 32 | 8.4.1) Clock Information 33 | 8.4.2) Asynchronous Control Signals Information 34 | 8.4.3) Timing Summary 35 | 8.4.4) Timing Details 36 | 8.4.5) Cross Clock Domains Report 37 | 38 | 39 | ========================================================================= 40 | * HDL Parsing * 41 | ========================================================================= 42 | Analyzing Verilog file \"F:\Verilog\Project_2_OC\TestProject\adder.v\" into library work 43 | Parsing module . 44 | Analyzing Verilog file \"F:\Verilog\Project_2_OC\TestProject\testbench.v\" into library work 45 | Parsing module . 46 | 47 | 48 | Total REAL time to Xst completion: 3.00 secs 49 | Total CPU time to Xst completion: 2.97 secs 50 | 51 | --> 52 | 53 | Total memory usage is 170552 kilobytes 54 | 55 | Number of errors : 0 ( 0 filtered) 56 | Number of warnings : 0 ( 0 filtered) 57 | Number of infos : 0 ( 0 filtered) 58 | 59 | -------------------------------------------------------------------------------- /Project_2_OC/TestProject/testbench.tfi: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | // Instantiate the module 5 | testbench instance_name ( 6 | ); 7 | 8 | 9 | -------------------------------------------------------------------------------- /Project_2_OC/TestProject/testbench.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Triple-Z/COExperiment_Repo/7a0ad4c5d025753d560e8a433fb26ea406268b1b/Project_2_OC/TestProject/testbench.v -------------------------------------------------------------------------------- /Project_2_OC/TestProject/testbench.xst: -------------------------------------------------------------------------------- 1 | set -tmpdir "F:/Verilog/Project_2_OC/TestProject/xst/projnav.tmp" 2 | set -xsthdpdir "F:/Verilog/Project_2_OC/TestProject/xst" 3 | run -compileonly yes 4 | -p xc6slx150-3-fgg484 5 | -top testbench 6 | -opt_mode Speed 7 | -opt_level 1 8 | -power NO 9 | -iuc NO 10 | -keep_hierarchy No 11 | -netlist_hierarchy As_Optimized 12 | -rtlview Yes 13 | -glob_opt AllClockNets 14 | -read_cores YES 15 | -write_timing_constraints NO 16 | -cross_clock_analysis NO 17 | -hierarchy_separator / 18 | -bus_delimiter <> 19 | -case Maintain 20 | -slice_utilization_ratio 100 21 | -bram_utilization_ratio 100 22 | -dsp_utilization_ratio 100 23 | -lc Auto 24 | -reduce_control_sets Auto 25 | -fsm_extract YES -fsm_encoding Auto 26 | -safe_implementation No 27 | -fsm_style LUT 28 | -ram_extract Yes 29 | -ram_style Auto 30 | -rom_extract Yes 31 | -shreg_extract YES 32 | -rom_style Auto 33 | -auto_bram_packing NO 34 | -resource_sharing YES 35 | -async_to_sync NO 36 | -shreg_min_size 2 37 | -use_dsp48 Auto 38 | -iobuf YES 39 | -max_fanout 100000 40 | -bufg 16 41 | -register_duplication YES 42 | -register_balancing No 43 | -optimize_primitives NO 44 | -use_clock_enable Auto 45 | -use_sync_set Auto 46 | -use_sync_reset Auto 47 | -iob Auto 48 | -equivalent_register_removal YES 49 | -slice_utilization_ratio_maxmargin 5 50 | -ifn testbench.prj 51 | -ifmt mixed 52 | -------------------------------------------------------------------------------- /Project_2_OC/TestProject/testbench_beh.prj: -------------------------------------------------------------------------------- 1 | verilog work "adder.v" 2 | verilog work "testbench.v" 3 | verilog work "F:/ISE/ISE_DS/ISE//verilog/src/glbl.v" 4 | -------------------------------------------------------------------------------- /Project_2_OC/TestProject/testbench_isim_beh.exe: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Triple-Z/COExperiment_Repo/7a0ad4c5d025753d560e8a433fb26ea406268b1b/Project_2_OC/TestProject/testbench_isim_beh.exe -------------------------------------------------------------------------------- /Project_2_OC/TestProject/testbench_isim_beh.wdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Triple-Z/COExperiment_Repo/7a0ad4c5d025753d560e8a433fb26ea406268b1b/Project_2_OC/TestProject/testbench_isim_beh.wdb -------------------------------------------------------------------------------- /Project_2_OC/TestProject/testbench_stx_beh.prj: -------------------------------------------------------------------------------- 1 | verilog isim_temp "adder.v" 2 | verilog isim_temp "testbench.v" 3 | verilog isim_temp "F:/ISE/ISE_DS/ISE//verilog/src/glbl.v" 4 | -------------------------------------------------------------------------------- /Project_2_OC/TestProject/webtalk.log: -------------------------------------------------------------------------------- 1 | Release 13.2 - WebTalk (O.61xd) 2 | Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. 3 | 4 | WebTalk Summary 5 | ---------------- 6 | INFO:WebTalk:3 - WebTalk is disabled. 7 | 8 | INFO:WebTalk:9 - WebTalk Install setting is OFF. 9 | INFO:WebTalk:6 - WebTalk User setting is ON. 10 | -------------------------------------------------------------------------------- /Project_2_OC/TestProject/xilinxsim.ini: -------------------------------------------------------------------------------- 1 | work=isim/work 2 | -------------------------------------------------------------------------------- /Project_2_OC/TestProject/xlnx_auto_0_xdb/cst.xbcd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Triple-Z/COExperiment_Repo/7a0ad4c5d025753d560e8a433fb26ea406268b1b/Project_2_OC/TestProject/xlnx_auto_0_xdb/cst.xbcd -------------------------------------------------------------------------------- /Project_2_OC/TestProject/xst/work/work.sdbl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Triple-Z/COExperiment_Repo/7a0ad4c5d025753d560e8a433fb26ea406268b1b/Project_2_OC/TestProject/xst/work/work.sdbl -------------------------------------------------------------------------------- /Project_2_OC/TestProject/xst/work/work.sdbx: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Triple-Z/COExperiment_Repo/7a0ad4c5d025753d560e8a433fb26ea406268b1b/Project_2_OC/TestProject/xst/work/work.sdbx -------------------------------------------------------------------------------- /Project_2_OC/adder.v: -------------------------------------------------------------------------------- 1 | module adder (operand1, operand2, cin, cout, result); 2 | input [31:0] operand1; 3 | input [31:0] operand2; 4 | input cin; 5 | output cout; 6 | output [31:0] result; 7 | 8 | assign {cout, result} = operand1 + operand2 + cin; 9 | 10 | endmodule // Adder; 11 | -------------------------------------------------------------------------------- /Project_2_OC/alu.v: -------------------------------------------------------------------------------- 1 | module alu (a, b, ALUop, result); 2 | input [31:0] a; 3 | input [31:0] b; 4 | input ALUop; 5 | 6 | output reg [31:0] result; 7 | 8 | always @ ( ALUop or a or b ) begin 9 | case (ALUop) 10 | 4'b0000: result = a + b;// add; 11 | 4'b0001: result = a - b;// sub; 12 | 4'b0010: result = ($signed(a) < $signed(b))? 1: 0;// slt; 13 | 4'b0011: result = (a < b)? 1: 0;// sltu; 14 | 4'b0100: result = a & b;// and; 15 | 4'b0101: result = ~(a | b);// nor; 16 | 4'b0110: result = a | b;// or; 17 | 4'b0111: result = a ^ b;// xor; 18 | 4'b1000: result = a << b[4:0];// sll; 19 | 4'b1001: result = a >> b[4:0];// srl; 20 | 4'b1010: result = $signed(a) >> b[4:0];// sra; 21 | 4'b1011: result = a >> 16;// lui; 22 | default: result = 0; 23 | endcase 24 | end 25 | endmodule // Arithmetic Logic Unit; 26 | -------------------------------------------------------------------------------- /Project_2_OC/rf.v: -------------------------------------------------------------------------------- 1 | module rf (busW, rA, rB, rW, clk, wE, busA, busB); 2 | input [31:0] busW; 3 | input [4:0] rA; 4 | input [4:0] rB; 5 | input [4:0] rW; 6 | input clk; 7 | input wE; 8 | 9 | output [31:0] busA; 10 | output [31:0] busB; 11 | 12 | reg [31:0] register[31:0]; 13 | 14 | // Read; 15 | assign busA[31:0] = register[rA]; 16 | assign busB[31:0] = register[rB]; 17 | 18 | // Write; 19 | always @ ( posedge clk ) begin 20 | if (wE) begin 21 | register[rW] <= busW; 22 | end 23 | end 24 | endmodule // Register File; 25 | -------------------------------------------------------------------------------- /Project_Assignment/code.txt: -------------------------------------------------------------------------------- 1 | 014b0018 2 | 00004810 3 | 00005012 4 | -------------------------------------------------------------------------------- /Project_Assignment/code_exp.txt: -------------------------------------------------------------------------------- 1 | # test for sb/lb. 2 | addu $t0, $zero, $t5 3 | sw $t0, 4($s0) 4 | lw $t3, 4($s0) 5 | sb $t5, 1($s0) 6 | lb $t6, 1($s0) 7 | 8 | # test for branch. 9 | beq $t1, $t2, L 10 | addu $t2, $t2, $t2 11 | addu $t2, $t2, $t2 12 | L: addu $t2, $t2, $t2 13 | bne $t1, $t2,L1 14 | addu $t3, $t3, $t3 15 | L2: addu $t3, $t3, $t3 16 | L1: addu $t3, $t3, $t3 17 | bgtz $t1, L2 18 | 19 | # test for extra 9 ins. 20 | mult $t2, $t3 21 | mfhi $t1 22 | mflo $t2 23 | mthi $t4 24 | mtlo $t5 25 | mtc0 $t6, $12 26 | mfc0 $7, $12 27 | syscall 28 | eret 29 | 30 | # test for jump. 31 | -------------------------------------------------------------------------------- /Project_Assignment/datapath/CoProcessor0RF.v: -------------------------------------------------------------------------------- 1 | module CoProcessor0RF(clk, din, wEn, regNum, sel, dout, npc_out, expiaddr, ins); 2 | input clk; 3 | input [1:0] wEn; 4 | input [4:0] regNum; 5 | input [2:0] sel; 6 | input [31:0] din; 7 | input [31:0] ins; 8 | input [31:0] npc_out; 9 | output [31:0] dout; 10 | output reg [31:0] expiaddr; 11 | 12 | reg [31:0] coprf [0:31]; 13 | 14 | wire [5:0] op; 15 | wire [5:0] func; 16 | wire [4:0] mf_tc0_eret; 17 | 18 | assign op = ins[31:26]; 19 | assign mf_tc0_eret = ins[25:21]; 20 | assign func = ins[5:0]; 21 | 22 | // op 23 | parameter R = 6'b000000, 24 | MTC0_MFC0_ERET = 6'b010000; 25 | // Function code. 26 | parameter SYSCALL = 6'b001100; 27 | // MTC0_MFC0_ERET 28 | parameter MTC0 = 5'b00100, 29 | MFC0 = 5'b00000, 30 | ERET = 5'b10000; 31 | 32 | initial begin 33 | coprf[12] = 32'h0000_0000;// Status 34 | coprf[13] = 32'h0000_0000;// Cause 35 | coprf[14] = 32'h0000_3000;// EPC 36 | end 37 | 38 | assign dout = coprf[regNum]; 39 | 40 | always @ (posedge clk) begin 41 | if (wEn) begin 42 | if ((op == R) && (func == SYSCALL)) begin// SYSCALL 43 | coprf[14] <= npc_out - 3'b100; 44 | coprf[13][6:2] <= 5'b01000; 45 | coprf[12][1] <= 1'b1; 46 | expiaddr <= 32'h0000_3000; 47 | end else if ((op == MTC0_MFC0_ERET) && (mf_tc0_eret == ERET)) begin// ERET 48 | coprf[12][1] <= 1'b0; 49 | expiaddr <= coprf[14][31:0]; 50 | end else begin// MTC0 51 | coprf[regNum] <= din; 52 | end 53 | end 54 | end 55 | 56 | endmodule // CoProcessor 0 Register File; 57 | -------------------------------------------------------------------------------- /Project_Assignment/datapath/alu.v: -------------------------------------------------------------------------------- 1 | module alu (ALUop, a, b, result, clk); 2 | input [3:0] ALUop; 3 | input [31:0] a, b; 4 | input clk; 5 | 6 | output reg [31:0] result; 7 | 8 | reg [63:0] tem64; 9 | reg [31:0] HI, LO; 10 | 11 | initial begin 12 | HI <= 32'h0000_0000; 13 | LO <= 32'h0000_0000; 14 | end 15 | 16 | always @ ( ALUop or a or b ) begin 17 | case (ALUop) 18 | 4'b0000: result <= a + b;// add|addu; 19 | 4'b0001: result <= a - b;// sub|subu; 20 | 4'b0010: result <= a & b;// and|andi; 21 | 4'b0011: result <= a | b;// or|ori; 22 | 4'b0100: result <= ~(a | b);// nor; 23 | 4'b0101: result <= a ^ b;// xor|xori; 24 | 4'b0110: result <= b << a[4:0];// sll; 25 | 4'b0111: result <= b >> a[4:0];// srl|srlv; 26 | 4'b1000: result <= $signed(b) >>> a[4:0];// sra|srav; 27 | 28 | 4'b1010: result <= (a < b)? 1: 0;// sltu|sltiu; 29 | 4'b1011: result <= ($signed(a) < $signed(b))? 1: 0;// slt|slti; 30 | 31 | 4'b1100: result = LO[31:0];// mflo; 32 | 4'b1101: result = HI[31:0];// mfhi; 33 | endcase 34 | end 35 | 36 | always @ ( posedge clk ) begin 37 | case (ALUop) 38 | 4'b1001: {HI, LO} = $signed(a) * $signed(b); 39 | 4'b1110: HI = a[31:0];//mthi; 40 | 4'b1111: LO = a[31:0];//mtlo; 41 | endcase 42 | end 43 | 44 | endmodule // Arithmetic Logic Unit; 45 | -------------------------------------------------------------------------------- /Project_Assignment/datapath/comp.v: -------------------------------------------------------------------------------- 1 | module comp(dinA, dinB, ins, compare, branch); 2 | input [31:0] dinA; 3 | input [31:0] dinB; 4 | input [31:0] ins; 5 | input compare; 6 | output reg branch; 7 | 8 | wire [5:0] op; 9 | wire [4:0] sel; 10 | 11 | assign sel = ins[20:16]; 12 | assign op = ins[31:26]; 13 | 14 | // Operation code. 15 | parameter BEQ = 6'b000100, 16 | BNE = 6'b000101, 17 | BGTZ = 6'b000111, 18 | BLEZ = 6'b000110, 19 | BGEZ_BLTZ = 6'b000001; 20 | 21 | // Sel code. 22 | parameter SEL0 = 5'b00000, 23 | SEL1 = 5'b00001; 24 | 25 | always @ ( compare or dinA or dinB ) begin 26 | if (compare) begin 27 | case (op) 28 | BEQ: begin 29 | if (dinA == dinB) begin 30 | branch = 1; 31 | end else branch = 0; 32 | end 33 | BNE: begin 34 | if (dinA != dinB) begin 35 | branch = 1; 36 | end else branch = 0; 37 | end 38 | BGTZ: begin 39 | if ($signed(dinA) > 0) begin 40 | branch = 1; 41 | end else branch = 0; 42 | end 43 | BLEZ: begin 44 | if ($signed(dinA) <= 0) begin 45 | branch = 1; 46 | end else branch = 0; 47 | end 48 | BGEZ_BLTZ: begin 49 | case (sel) 50 | SEL0: if ($signed(dinA) < 0) begin// BLTZ 51 | branch = 1; 52 | end else branch = 0; 53 | SEL1: if ($signed(dinA) >= 0) begin// BGEZ 54 | branch = 1; 55 | end else branch = 0; 56 | endcase 57 | end 58 | default: branch = 0; 59 | endcase 60 | end else branch = 0; 61 | end 62 | 63 | endmodule // Compare; 64 | -------------------------------------------------------------------------------- /Project_Assignment/datapath/dm.v: -------------------------------------------------------------------------------- 1 | `define BigEndianCPU 1 2 | 3 | module dm_4k (addr, din, byteExt, wEn, clk, dout); 4 | input [11:0] addr; 5 | input [31:0] din; 6 | input [1:0] byteExt; 7 | input [1:0] wEn; 8 | input clk; 9 | output reg [31:0] dout; 10 | 11 | reg [31:0] dm [1023:0];// 32-bit*1024; 12 | 13 | wire [1:0] byteSel; 14 | wire [9:0] gpAddr; 15 | 16 | reg [7:0] byteIn; 17 | reg [31:0] tmpReg; 18 | 19 | assign byteSel = addr[1:0] ^ 2'b11;// Big endian. 20 | assign gpAddr = addr[11:2]; 21 | 22 | always @ ( * ) begin 23 | if (byteExt == 2'b01 || byteExt == 2'b00) begin// Load byte. 24 | case (byteSel) 25 | 2'b00: byteIn <= dm[gpAddr][7:0]; 26 | 2'b01: byteIn <= dm[gpAddr][15:8]; 27 | 2'b10: byteIn <= dm[gpAddr][23:16]; 28 | 2'b11: byteIn <= dm[gpAddr][31:24]; 29 | endcase 30 | case (byteExt)// Embedded extender. 31 | 2'b00: dout <= {{24{1'b0}}, byteIn};// Logical Cal; 32 | 2'b01: dout <= {{24{byteIn[7]}}, byteIn};// Arithmetic Cal; 33 | endcase 34 | end else begin 35 | dout = dm[gpAddr][31:0];// Load word. 36 | end 37 | end 38 | 39 | 40 | always @ ( posedge clk ) begin// Write; 41 | if (wEn == 2'b01) begin 42 | if (byteExt == 2'b10) begin// Store byte. 43 | tmpReg = dm[gpAddr][31:0]; 44 | case (byteSel) 45 | 2'b00: tmpReg[7:0] = din[7:0]; 46 | 2'b01: tmpReg[15:8] = din[7:0]; 47 | 2'b10: tmpReg[23:16] = din[7:0]; 48 | 2'b11: tmpReg[31:24] = din[7:0]; 49 | endcase 50 | dm[gpAddr][31:0] = tmpReg[31:0]; 51 | end else begin// Store word. 52 | dm[gpAddr][31:0] = din[31:0]; 53 | end 54 | end 55 | end 56 | endmodule // 4K Data Memeory; 57 | -------------------------------------------------------------------------------- /Project_Assignment/datapath/ext.v: -------------------------------------------------------------------------------- 1 | module ext #(parameter WIDTH = 16)(din, extOp, dout); 2 | input [1:0] extOp; 3 | input [WIDTH - 1:0] din; 4 | output reg [31:0] dout; 5 | 6 | always @ ( * ) begin 7 | case (extOp) 8 | 2'b00: dout = {{(32 - WIDTH){1'b0}}, din};// Logical Cal; 9 | 2'b01: dout = {{(32 - WIDTH){din[WIDTH - 1]}}, din};// Arithmetic Cal; 10 | default: dout = din; 11 | endcase 12 | end 13 | endmodule // Extender; 14 | -------------------------------------------------------------------------------- /Project_Assignment/datapath/im.v: -------------------------------------------------------------------------------- 1 | module im_4k (iaddr, ins); 2 | input [11:2] iaddr; 3 | output [31:0] ins; 4 | 5 | reg [31:0] im [1023:0];// 32-bit*1024; 6 | 7 | initial begin 8 | $readmemh("code.txt", im); 9 | end 10 | 11 | assign ins = im[iaddr[11:2]][31:0]; 12 | 13 | 14 | endmodule // 4k Instruction Memeory; 15 | -------------------------------------------------------------------------------- /Project_Assignment/datapath/mux.v: -------------------------------------------------------------------------------- 1 | module mux #(parameter WIDTH = 32) (a, b, c, d, ctrl_s, dout); 2 | input [WIDTH - 1:0] a; 3 | input [WIDTH - 1:0] b; 4 | input [WIDTH - 1:0] c; 5 | input [WIDTH - 1:0] d; 6 | input [1:0] ctrl_s; 7 | 8 | output reg [WIDTH - 1:0] dout; 9 | 10 | always @ ( * ) begin 11 | case (ctrl_s) 12 | 2'b00: dout = a; 13 | 2'b01: dout = b; 14 | 2'b10: dout = c; 15 | 2'b11: dout = d; 16 | endcase 17 | end 18 | 19 | 20 | endmodule // Multiplexer; 21 | -------------------------------------------------------------------------------- /Project_Assignment/datapath/npc.v: -------------------------------------------------------------------------------- 1 | module npc (iaddr, branch, jump, ins, jiaddr, imm16, imm26, riaddr, niaddr); 2 | input branch, jump; 3 | input [31:0] ins; 4 | input [31:0] jiaddr;// Jump to instruction address. 5 | input [31:0] iaddr;// Instruction Address. 6 | input [15:0] imm16; 7 | input [25:0] imm26; 8 | 9 | output [31:0] riaddr;// Return instruction address; 10 | output reg [31:0] niaddr;// Next Instruction Address; 11 | 12 | wire [5:0] op; 13 | wire [5:0] func; 14 | assign op = ins[31:26]; 15 | assign func = ins[5:0]; 16 | // Operation code. 17 | parameter R = 6'b000000, 18 | J = 6'b000010, 19 | JAL = 6'b000011, 20 | ERET = 6'b010000; 21 | // Function code. 22 | parameter JR = 6'b001000, 23 | JALR = 6'b001001, 24 | SYSCALL = 6'b001100; 25 | 26 | wire [31:0] pc4; 27 | 28 | assign pc4 = iaddr + 3'b100; 29 | assign riaddr = pc4 + 3'b100; 30 | 31 | always @ ( * ) begin 32 | if (branch) begin// Branch; 33 | // Arithmetic extend. 34 | niaddr = {{14{imm16[15]}}, imm16[15:0], 2'b00} + pc4; 35 | 36 | end else if (jump) begin// Jump. 37 | case (op) 38 | J: begin// Jump. 39 | niaddr = {iaddr[31:28], imm26[25:0], 2'b00}; 40 | end 41 | JAL: begin// Jump and link. 42 | // riaddr <= pc4 + 3'b100; 43 | niaddr <= {iaddr[31:28], imm26[25:0], 2'b00}; 44 | end 45 | R: begin 46 | case (func) 47 | JR: begin// Jump register. 48 | niaddr = jiaddr[31:0]; 49 | end 50 | JALR: begin// Jump and link register. 51 | // riaddr <= pc4 + 3'b100; 52 | niaddr <= jiaddr[31:0]; 53 | end 54 | SYSCALL: begin 55 | niaddr <= jiaddr[31:0]; 56 | end 57 | endcase 58 | end 59 | ERET: begin 60 | niaddr <= jiaddr[31:0]; 61 | end 62 | endcase 63 | 64 | end else begin// PC + 4; 65 | niaddr = pc4; 66 | end 67 | end 68 | 69 | endmodule // Next Program Counter; 70 | -------------------------------------------------------------------------------- /Project_Assignment/datapath/pc.v: -------------------------------------------------------------------------------- 1 | module pc (clk, rst, niaddr, iaddr); 2 | input clk; 3 | input rst; 4 | input [31:0] niaddr;// Next Instruction Address; 5 | 6 | output reg [31:0] iaddr;// Instruction Address; 7 | 8 | always @ ( posedge clk ) begin 9 | if (rst) 10 | iaddr <= 32'h0000_3000; 11 | else 12 | iaddr <= niaddr; 13 | end 14 | endmodule // Program Counter; 15 | -------------------------------------------------------------------------------- /Project_Assignment/datapath/rf.v: -------------------------------------------------------------------------------- 1 | module regFile (busW, clk, wE, rW, rA, rB, busA, busB); 2 | input [31:0] busW; 3 | input [4:0] rW, rA, rB; 4 | input clk; 5 | input [1:0] wE; 6 | output [31:0] busA, busB; 7 | 8 | reg [31:0] register[0:31]; 9 | 10 | initial begin 11 | register[0] <= 0;// $zero; 12 | 13 | register[8] <= 0;// $t0; 14 | register[9] <= 1;// $t1; 15 | register[10] <= 2;// $t2; 16 | register[11] <= 3;// $t3; 17 | register[12] <= 4;// $t4; 18 | register[13] <= 5;// $t5; 19 | register[14] <= 6;// $t6; 20 | register[15] <= 7;// $t7; 21 | 22 | register[16] <= 0;// $s0; 23 | register[17] <= 0;// $s1; 24 | register[18] <= 0;// $s2; 25 | register[19] <= 0;// $s3; 26 | end 27 | 28 | assign busA = (rA != 0)? register[rA]: 0; 29 | assign busB = (rB != 0)? register[rB]: 0; 30 | 31 | always @ ( posedge clk ) begin 32 | if ((wE == 2'b01) && (rW != 0)) begin 33 | register[rW] = busW; 34 | end 35 | end 36 | endmodule // Register File 37 | -------------------------------------------------------------------------------- /Project_Assignment/testbench.v: -------------------------------------------------------------------------------- 1 | `include "mips.v" 2 | 3 | module testbench (); 4 | reg clk, rst; 5 | 6 | initial begin 7 | clk = 0; 8 | rst = 1; 9 | #20 rst = 0; 10 | end 11 | 12 | always #10 clk = ~clk; 13 | 14 | mips mips( 15 | .clk(clk), 16 | .rst(rst) 17 | ); 18 | 19 | endmodule // Test Bench; 20 | -------------------------------------------------------------------------------- /Project_Assignment_OnBoard/CoProcessor0RF.v: -------------------------------------------------------------------------------- 1 | module CoProcessor0RF(clk, din, wEn, regNum, sel, dout, npc_out, expiaddr, ins, cop_addr, cop_data); 2 | input clk; 3 | input [1:0] wEn; 4 | input [4:0] regNum; 5 | input [2:0] sel; 6 | input [31:0] din; 7 | input [31:0] ins; 8 | input [31:0] npc_out; 9 | output [31:0] dout; 10 | output reg [31:0] expiaddr; 11 | input [4:0] cop_addr; 12 | output [31:0] cop_data; 13 | 14 | reg [31:0] coprf [0:31]; 15 | 16 | wire [5:0] op; 17 | wire [5:0] func; 18 | wire [4:0] mf_tc0_eret; 19 | 20 | assign op = ins[31:26]; 21 | assign mf_tc0_eret = ins[25:21]; 22 | assign func = ins[5:0]; 23 | 24 | // op 25 | parameter R = 6'b000000, 26 | MTC0_MFC0_ERET = 6'b010000; 27 | // Function code. 28 | parameter SYSCALL = 6'b001100; 29 | // MTC0_MFC0_ERET 30 | parameter MTC0 = 5'b00100, 31 | MFC0 = 5'b00000, 32 | ERET = 5'b10000; 33 | 34 | initial begin 35 | coprf[12] = 32'h0000_0000;// Status 36 | coprf[13] = 32'h0000_0000;// Cause 37 | coprf[14] = 32'h0000_0000;// EPC 38 | end 39 | 40 | assign dout = coprf[regNum]; 41 | 42 | assign cop_data = coprf[cop_addr]; 43 | 44 | always @ (posedge clk) begin 45 | if (wEn) begin 46 | if ((op == R) && (func == SYSCALL)) begin// SYSCALL 47 | coprf[14] <= npc_out - 4'b1000; 48 | coprf[13][6:2] <= 5'b01000; 49 | coprf[12][1] <= 1'b1; 50 | expiaddr <= 32'h0000_0000; 51 | end else if ((op == MTC0_MFC0_ERET) && (mf_tc0_eret == ERET)) begin// ERET 52 | coprf[12][1] <= 1'b0; 53 | expiaddr <= coprf[14][31:0]; 54 | end else begin// MTC0 55 | coprf[regNum] <= din; 56 | end 57 | end 58 | end 59 | 60 | endmodule // CoProcessor 0 Register File; 61 | -------------------------------------------------------------------------------- /Project_Assignment_OnBoard/_ngo/netlist.lst: -------------------------------------------------------------------------------- 1 | F:\Verilog\Project_Assignment_OnBoard\mips_display.ngc 1498284551 2 | F:\Verilog\Project_Assignment_OnBoard/lcd_module.ngc 1478764461 3 | F:\Verilog\Project_Assignment_OnBoard/lcd_rom.ngc 1460178844 4 | OK 5 | -------------------------------------------------------------------------------- /Project_Assignment_OnBoard/_xmsgs/bitgen.xmsgs: -------------------------------------------------------------------------------- 1 | 2 | 7 | 8 | Gated clock. Clock net cpu/ctrl/op[5]_func[5]_Select_144_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. 9 | 10 | 11 | Gated clock. Clock net cpu/ctrl/op[5]_func[5]_Select_129_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. 12 | 13 | 14 | Gated clock. Clock net cpu/ctrl/op[5]_PWR_159_o_Select_112_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. 15 | 16 | 17 | Gated clock. Clock net cpu/ctrl/op[5]_func[5]_Select_151_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. 18 | 19 | 20 | Gated clock. Clock net cpu/ctrl/op[5]_PWR_149_o_Select_102_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. 21 | 22 | 23 | Gated clock. Clock net cpu/ctrl/op[5]_func[5]_Select_134_o is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. 24 | 25 | 26 | The signal <lcd_module/touch_module/int_io/O> is incomplete. The signal does not drive any load pins in the design. 27 | 28 | 29 | 30 | 31 | -------------------------------------------------------------------------------- /Project_Assignment_OnBoard/_xmsgs/ngdbuild.xmsgs: -------------------------------------------------------------------------------- 1 | 2 | 7 | 8 | logical net 'N291' has no driver 9 | 10 | 11 | logical net 'N292' has no driver 12 | 13 | 14 | 15 | 16 | -------------------------------------------------------------------------------- /Project_Assignment_OnBoard/_xmsgs/par.xmsgs: -------------------------------------------------------------------------------- 1 | 2 | 7 | 8 | The signal lcd_module/touch_module/int_io/O has no load. PAR will not attempt to route this signal. 9 | 10 | 11 | Unusually high hold time violation detected among 101 connections. The top 20 such instances are printed below. The router will continue and try to fix it 12 | 13 | 14 | There are 1 loadless signals in this design. This design will cause Bitgen to issue DRC warnings. 15 | 16 | 17 | 18 | There are 1 loadless signals in this design. This design will cause Bitgen to issue DRC warnings. 19 | 20 | 21 | 22 | 23 | 24 | -------------------------------------------------------------------------------- /Project_Assignment_OnBoard/_xmsgs/trce.xmsgs: -------------------------------------------------------------------------------- 1 | 2 | 7 | 8 | To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report. 9 | 10 | The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet. 11 | 12 | 13 | 14 | -------------------------------------------------------------------------------- /Project_Assignment_OnBoard/adder.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Triple-Z/COExperiment_Repo/7a0ad4c5d025753d560e8a433fb26ea406268b1b/Project_Assignment_OnBoard/adder.v -------------------------------------------------------------------------------- /Project_Assignment_OnBoard/alu.v: -------------------------------------------------------------------------------- 1 | module alu (ALUop, a, b, result, clk, hi_data, lo_data); 2 | input [3:0] ALUop; 3 | input [31:0] a, b; 4 | input clk; 5 | 6 | output [31:0] hi_data; 7 | output [31:0] lo_data; 8 | output reg [31:0] result; 9 | 10 | reg [63:0] tem64; 11 | reg [31:0] HI, LO; 12 | 13 | assign hi_data = HI[31:0]; 14 | assign lo_data = LO[31:0]; 15 | 16 | initial begin 17 | HI <= 32'h0000_0000; 18 | LO <= 32'h0000_0000; 19 | end 20 | 21 | always @ ( ALUop or a or b ) begin 22 | case (ALUop) 23 | 4'b0000: result <= a + b;// add|addu; 24 | 4'b0001: result <= a - b;// sub|subu; 25 | 4'b0010: result <= a & b;// and|andi; 26 | 4'b0011: result <= a | b;// or|ori; 27 | 4'b0100: result <= ~(a | b);// nor; 28 | 4'b0101: result <= a ^ b;// xor|xori; 29 | 4'b0110: result <= b << a[4:0];// sll; 30 | 4'b0111: result <= b >> a[4:0];// srl|srlv; 31 | 4'b1000: result <= $signed(b) >>> a[4:0];// sra|srav; 32 | 33 | 4'b1010: result <= (a < b)? 1: 0;// sltu|sltiu; 34 | 4'b1011: result <= ($signed(a) < $signed(b))? 1: 0;// slt|slti; 35 | 36 | 4'b1100: result = LO[31:0];// mflo; 37 | 4'b1101: result = HI[31:0];// mfhi; 38 | endcase 39 | end 40 | 41 | always @ ( posedge clk ) begin 42 | case (ALUop) 43 | 4'b1001: {HI, LO} = $signed(a) * $signed(b); 44 | 4'b1110: HI = a[31:0];//mthi; 45 | 4'b1111: LO = a[31:0];//mtlo; 46 | endcase 47 | end 48 | 49 | endmodule // Arithmetic Logic Unit; 50 | -------------------------------------------------------------------------------- /Project_Assignment_OnBoard/code.txt: -------------------------------------------------------------------------------- 1 | 014b0018 2 | 00004810 3 | 00005012 4 | 01800011 5 | 01a00013 6 | 408e6000 7 | 40076000 8 | 0000000c 9 | 42000018 10 | -------------------------------------------------------------------------------- /Project_Assignment_OnBoard/comp.v: -------------------------------------------------------------------------------- 1 | module comp(dinA, dinB, ins, compare, branch); 2 | input [31:0] dinA; 3 | input [31:0] dinB; 4 | input [31:0] ins; 5 | input compare; 6 | output reg branch; 7 | 8 | wire [5:0] op; 9 | wire [4:0] sel; 10 | 11 | assign sel = ins[20:16]; 12 | assign op = ins[31:26]; 13 | 14 | // Operation code. 15 | parameter BEQ = 6'b000100, 16 | BNE = 6'b000101, 17 | BGTZ = 6'b000111, 18 | BLEZ = 6'b000110, 19 | BGEZ_BLTZ = 6'b000001; 20 | 21 | // Sel code. 22 | parameter SEL0 = 5'b00000, 23 | SEL1 = 5'b00001; 24 | 25 | always @ ( compare or dinA or dinB ) begin 26 | if (compare) begin 27 | case (op) 28 | BEQ: begin 29 | if (dinA == dinB) begin 30 | branch = 1; 31 | end else branch = 0; 32 | end 33 | BNE: begin 34 | if (dinA != dinB) begin 35 | branch = 1; 36 | end else branch = 0; 37 | end 38 | BGTZ: begin 39 | if ($signed(dinA) > 0) begin 40 | branch = 1; 41 | end else branch = 0; 42 | end 43 | BLEZ: begin 44 | if ($signed(dinA) <= 0) begin 45 | branch = 1; 46 | end else branch = 0; 47 | end 48 | BGEZ_BLTZ: begin 49 | case (sel) 50 | SEL0: if ($signed(dinA) < 0) begin// BLTZ 51 | branch = 1; 52 | end else branch = 0; 53 | SEL1: if ($signed(dinA) >= 0) begin// BGEZ 54 | branch = 1; 55 | end else branch = 0; 56 | endcase 57 | end 58 | default: branch = 0; 59 | endcase 60 | end else branch = 0; 61 | end 62 | 63 | endmodule // Compare; 64 | -------------------------------------------------------------------------------- /Project_Assignment_OnBoard/data_ram.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Triple-Z/COExperiment_Repo/7a0ad4c5d025753d560e8a433fb26ea406268b1b/Project_Assignment_OnBoard/data_ram.v -------------------------------------------------------------------------------- /Project_Assignment_OnBoard/dm.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Triple-Z/COExperiment_Repo/7a0ad4c5d025753d560e8a433fb26ea406268b1b/Project_Assignment_OnBoard/dm.v -------------------------------------------------------------------------------- /Project_Assignment_OnBoard/ext.v: -------------------------------------------------------------------------------- 1 | module ext #(parameter WIDTH = 16)(din, extOp, dout); 2 | input [1:0] extOp; 3 | input [WIDTH - 1:0] din; 4 | output reg [31:0] dout; 5 | 6 | always @ ( * ) begin 7 | case (extOp) 8 | 2'b00: dout = {{(32 - WIDTH){1'b0}}, din};// Logical Cal; 9 | 2'b01: dout = {{(32 - WIDTH){din[WIDTH - 1]}}, din};// Arithmetic Cal; 10 | default: dout = din; 11 | endcase 12 | end 13 | endmodule // Extender; 14 | -------------------------------------------------------------------------------- /Project_Assignment_OnBoard/im.v: -------------------------------------------------------------------------------- 1 | module im_4k (iaddr, ins); 2 | input [11:2] iaddr; 3 | output [31:0] ins; 4 | 5 | reg [31:0] im [31:0];// 32-bit*1024; 6 | 7 | initial begin 8 | $readmemh("code.txt", im); 9 | end 10 | 11 | assign ins = im[iaddr[11:2]][31:0]; 12 | 13 | 14 | endmodule // 4k Instruction Memeory; 15 | -------------------------------------------------------------------------------- /Project_Assignment_OnBoard/inst_rom.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Triple-Z/COExperiment_Repo/7a0ad4c5d025753d560e8a433fb26ea406268b1b/Project_Assignment_OnBoard/inst_rom.v -------------------------------------------------------------------------------- /Project_Assignment_OnBoard/lcd_module.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Triple-Z/COExperiment_Repo/7a0ad4c5d025753d560e8a433fb26ea406268b1b/Project_Assignment_OnBoard/lcd_module.v -------------------------------------------------------------------------------- /Project_Assignment_OnBoard/mips_display.bit: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Triple-Z/COExperiment_Repo/7a0ad4c5d025753d560e8a433fb26ea406268b1b/Project_Assignment_OnBoard/mips_display.bit -------------------------------------------------------------------------------- /Project_Assignment_OnBoard/mips_display.bld: -------------------------------------------------------------------------------- 1 | Release 13.2 ngdbuild O.61xd (nt64) 2 | Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. 3 | 4 | Command Line: F:\ISE\ISE_DS\ISE\bin\nt64\unwrapped\ngdbuild.exe -intstyle ise 5 | -dd _ngo -nt timestamp -uc single_cycle_cpu.ucf -p xc6slx150-fgg676-3 6 | mips_display.ngc mips_display.ngd 7 | 8 | Reading NGO file "F:/Verilog/Project_Assignment_OnBoard/mips_display.ngc" ... 9 | Loading design module "F:\Verilog\Project_Assignment_OnBoard/lcd_module.ngc"... 10 | Loading design module "F:\Verilog\Project_Assignment_OnBoard/lcd_rom.ngc"... 11 | Gathering constraint information from source properties... 12 | Done. 13 | 14 | Annotating constraints to design from ucf file "single_cycle_cpu.ucf" ... 15 | Resolving constraint associations... 16 | Checking Constraint Associations... 17 | Done... 18 | 19 | Checking expanded design ... 20 | WARNING:NgdBuild:452 - logical net 'N291' has no driver 21 | WARNING:NgdBuild:452 - logical net 'N292' has no driver 22 | 23 | Partition Implementation Status 24 | ------------------------------- 25 | 26 | No Partitions were found in this design. 27 | 28 | ------------------------------- 29 | 30 | NGDBUILD Design Results Summary: 31 | Number of errors: 0 32 | Number of warnings: 2 33 | 34 | Total memory usage is 161256 kilobytes 35 | 36 | Writing NGD file "mips_display.ngd" ... 37 | Total REAL time to NGDBUILD completion: 2 sec 38 | Total CPU time to NGDBUILD completion: 2 sec 39 | 40 | Writing NGDBUILD log file "mips_display.bld"... 41 | -------------------------------------------------------------------------------- /Project_Assignment_OnBoard/mips_display.drc: -------------------------------------------------------------------------------- 1 | Release 13.2 Drc O.61xd (nt64) 2 | Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. 3 | 4 | Sat Jun 24 14:10:45 2017 5 | 6 | drc -z mips_display.ncd mips_display.pcf 7 | 8 | WARNING:PhysDesignRules:372 - Gated clock. Clock net 9 | cpu/ctrl/op[5]_func[5]_Select_144_o is sourced by a combinatorial pin. This 10 | is not good design practice. Use the CE pin to control the loading of data 11 | into the flip-flop. 12 | WARNING:PhysDesignRules:372 - Gated clock. Clock net 13 | cpu/ctrl/op[5]_func[5]_Select_129_o is sourced by a combinatorial pin. This 14 | is not good design practice. Use the CE pin to control the loading of data 15 | into the flip-flop. 16 | WARNING:PhysDesignRules:372 - Gated clock. Clock net 17 | cpu/ctrl/op[5]_PWR_159_o_Select_112_o is sourced by a combinatorial pin. This 18 | is not good design practice. Use the CE pin to control the loading of data 19 | into the flip-flop. 20 | WARNING:PhysDesignRules:372 - Gated clock. Clock net 21 | cpu/ctrl/op[5]_func[5]_Select_151_o is sourced by a combinatorial pin. This 22 | is not good design practice. Use the CE pin to control the loading of data 23 | into the flip-flop. 24 | WARNING:PhysDesignRules:372 - Gated clock. Clock net 25 | cpu/ctrl/op[5]_PWR_149_o_Select_102_o is sourced by a combinatorial pin. This 26 | is not good design practice. Use the CE pin to control the loading of data 27 | into the flip-flop. 28 | WARNING:PhysDesignRules:372 - Gated clock. Clock net 29 | cpu/ctrl/op[5]_func[5]_Select_134_o is sourced by a combinatorial pin. This 30 | is not good design practice. Use the CE pin to control the loading of data 31 | into the flip-flop. 32 | WARNING:PhysDesignRules:367 - The signal is 33 | incomplete. The signal does not drive any load pins in the design. 34 | DRC detected 0 errors and 7 warnings. Please see the previously displayed 35 | individual error or warning messages for more details. 36 | -------------------------------------------------------------------------------- /Project_Assignment_OnBoard/mips_display.lso: -------------------------------------------------------------------------------- 1 | work 2 | -------------------------------------------------------------------------------- /Project_Assignment_OnBoard/mips_display.prj: -------------------------------------------------------------------------------- 1 | verilog work "rf.v" 2 | verilog work "pc.v" 3 | verilog work "npc.v" 4 | verilog work "mux.v" 5 | verilog work "im.v" 6 | verilog work "ext.v" 7 | verilog work "dm.v" 8 | verilog work "ctrl.v" 9 | verilog work "CoProcessor0RF.v" 10 | verilog work "comp.v" 11 | verilog work "alu.v" 12 | verilog work "mips.v" 13 | verilog work "lcd_module.v" 14 | verilog work "single_cycle_cpu_display.v" 15 | -------------------------------------------------------------------------------- /Project_Assignment_OnBoard/mips_display.stx: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Triple-Z/COExperiment_Repo/7a0ad4c5d025753d560e8a433fb26ea406268b1b/Project_Assignment_OnBoard/mips_display.stx -------------------------------------------------------------------------------- /Project_Assignment_OnBoard/mips_display.unroutes: -------------------------------------------------------------------------------- 1 | Release 13.2 - par O.61xd (nt64) 2 | Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. 3 | 4 | Sat Jun 24 14:10:20 2017 5 | 6 | All signals are completely routed. 7 | 8 | WARNING:ParHelpers:361 - There are 1 loadless signals in this design. This design will cause Bitgen to issue DRC 9 | warnings. 10 | 11 | lcd_module/touch_module/int_io/O 12 | 13 | 14 | -------------------------------------------------------------------------------- /Project_Assignment_OnBoard/mips_display.ut: -------------------------------------------------------------------------------- 1 | -w 2 | -g DebugBitstream:No 3 | -g Binary:no 4 | -g CRC:Enable 5 | -g Reset_on_err:No 6 | -g ConfigRate:2 7 | -g ProgPin:PullUp 8 | -g TckPin:PullUp 9 | -g TdiPin:PullUp 10 | -g TdoPin:PullUp 11 | -g TmsPin:PullUp 12 | -g UnusedPin:PullDown 13 | -g UserID:0xFFFFFFFF 14 | -g ExtMasterCclk_en:No 15 | -g SPI_buswidth:1 16 | -g TIMER_CFG:0xFFFF 17 | -g multipin_wakeup:No 18 | -g StartUpClk:CClk 19 | -g DONE_cycle:4 20 | -g GTS_cycle:5 21 | -g GWE_cycle:6 22 | -g LCK_cycle:NoWait 23 | -g Security:None 24 | -g DonePipe:No 25 | -g DriveDone:No 26 | -g Encrypt:No 27 | -g en_sw_gsr:No 28 | -g drive_awake:No 29 | -g sw_clk:Startupclk 30 | -g sw_gwe_cycle:5 31 | -g sw_gts_cycle:4 32 | -------------------------------------------------------------------------------- /Project_Assignment_OnBoard/mips_display.xpi: -------------------------------------------------------------------------------- 1 | PROGRAM=PAR 2 | STATE=ROUTED 3 | TIMESPECS_MET=YES 4 | -------------------------------------------------------------------------------- /Project_Assignment_OnBoard/mips_display.xst: -------------------------------------------------------------------------------- 1 | set -tmpdir "xst/projnav.tmp" 2 | set -xsthdpdir "xst" 3 | run 4 | -ifn mips_display.prj 5 | -ifmt mixed 6 | -ofn mips_display 7 | -ofmt NGC 8 | -p xc6slx150-3-fgg676 9 | -top mips_display 10 | -opt_mode Speed 11 | -opt_level 1 12 | -power NO 13 | -iuc NO 14 | -keep_hierarchy No 15 | -netlist_hierarchy As_Optimized 16 | -rtlview Yes 17 | -glob_opt AllClockNets 18 | -read_cores YES 19 | -write_timing_constraints NO 20 | -cross_clock_analysis NO 21 | -hierarchy_separator / 22 | -bus_delimiter <> 23 | -case Maintain 24 | -slice_utilization_ratio 100 25 | -bram_utilization_ratio 100 26 | -dsp_utilization_ratio 100 27 | -lc Auto 28 | -reduce_control_sets Auto 29 | -fsm_extract YES -fsm_encoding Auto 30 | -safe_implementation No 31 | -fsm_style LUT 32 | -ram_extract Yes 33 | -ram_style Auto 34 | -rom_extract Yes 35 | -shreg_extract YES 36 | -rom_style Auto 37 | -auto_bram_packing NO 38 | -resource_sharing YES 39 | -async_to_sync NO 40 | -shreg_min_size 2 41 | -use_dsp48 Auto 42 | -iobuf YES 43 | -max_fanout 100000 44 | -bufg 16 45 | -register_duplication YES 46 | -register_balancing No 47 | -optimize_primitives NO 48 | -use_clock_enable Auto 49 | -use_sync_set Auto 50 | -use_sync_reset Auto 51 | -iob Auto 52 | -equivalent_register_removal YES 53 | -slice_utilization_ratio_maxmargin 5 54 | -------------------------------------------------------------------------------- /Project_Assignment_OnBoard/mips_display_bitgen.xwbt: -------------------------------------------------------------------------------- 1 | INTSTYLE=ise 2 | INFILE=F:\Verilog\Project_Assignment_OnBoard\mips_display.ncd 3 | OUTFILE=F:\Verilog\Project_Assignment_OnBoard\mips_display.bit 4 | FAMILY=Spartan6 5 | PART=xc6slx150-3fgg676 6 | WORKINGDIR=F:\Verilog\Project_Assignment_OnBoard 7 | LICENSE=ISE 8 | USER_INFO=135256_15690819_173552794_661 9 | -------------------------------------------------------------------------------- /Project_Assignment_OnBoard/mips_display_summary.html: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Triple-Z/COExperiment_Repo/7a0ad4c5d025753d560e8a433fb26ea406268b1b/Project_Assignment_OnBoard/mips_display_summary.html -------------------------------------------------------------------------------- /Project_Assignment_OnBoard/mips_display_summary.xml: -------------------------------------------------------------------------------- 1 | 2 | 7 | 8 | 9 | 10 | 11 | -------------------------------------------------------------------------------- /Project_Assignment_OnBoard/mux.v: -------------------------------------------------------------------------------- 1 | module mux #(parameter WIDTH = 32) (a, b, c, d, ctrl_s, dout); 2 | input [WIDTH - 1:0] a; 3 | input [WIDTH - 1:0] b; 4 | input [WIDTH - 1:0] c; 5 | input [WIDTH - 1:0] d; 6 | input [1:0] ctrl_s; 7 | 8 | output reg [WIDTH - 1:0] dout; 9 | 10 | always @ ( * ) begin 11 | case (ctrl_s) 12 | 2'b00: dout = a; 13 | 2'b01: dout = b; 14 | 2'b10: dout = c; 15 | 2'b11: dout = d; 16 | endcase 17 | end 18 | 19 | 20 | endmodule // Multiplexer; 21 | -------------------------------------------------------------------------------- /Project_Assignment_OnBoard/npc.v: -------------------------------------------------------------------------------- 1 | module npc (iaddr, branch, jump, ins, jiaddr, imm16, imm26, riaddr, niaddr); 2 | input branch, jump; 3 | input [31:0] ins; 4 | input [31:0] jiaddr;// Jump to instruction address. 5 | input [31:0] iaddr;// Instruction Address. 6 | input [15:0] imm16; 7 | input [25:0] imm26; 8 | 9 | output [31:0] riaddr;// Return instruction address; 10 | output reg [31:0] niaddr;// Next Instruction Address; 11 | 12 | wire [5:0] op; 13 | wire [5:0] func; 14 | assign op = ins[31:26]; 15 | assign func = ins[5:0]; 16 | // Operation code. 17 | parameter R = 6'b000000, 18 | J = 6'b000010, 19 | JAL = 6'b000011, 20 | ERET = 6'b010000; 21 | // Function code. 22 | parameter JR = 6'b001000, 23 | JALR = 6'b001001, 24 | SYSCALL = 6'b001100; 25 | 26 | wire [31:0] pc4; 27 | 28 | assign pc4 = iaddr + 3'b100; 29 | assign riaddr = pc4 + 3'b100; 30 | 31 | always @ ( * ) begin 32 | if (branch) begin// Branch; 33 | // Arithmetic extend. 34 | niaddr = {{14{imm16[15]}}, imm16[15:0], 2'b00} + pc4; 35 | 36 | end else if (jump) begin// Jump. 37 | case (op) 38 | J: begin// Jump. 39 | niaddr = {iaddr[31:28], imm26[25:0], 2'b00}; 40 | end 41 | JAL: begin// Jump and link. 42 | // riaddr <= pc4 + 3'b100; 43 | niaddr <= {iaddr[31:28], imm26[25:0], 2'b00}; 44 | end 45 | R: begin 46 | case (func) 47 | JR: begin// Jump register. 48 | niaddr = jiaddr[31:0]; 49 | end 50 | JALR: begin// Jump and link register. 51 | // riaddr <= pc4 + 3'b100; 52 | niaddr <= jiaddr[31:0]; 53 | end 54 | SYSCALL: begin 55 | niaddr <= jiaddr[31:0]; 56 | end 57 | endcase 58 | end 59 | ERET: begin 60 | niaddr <= jiaddr[31:0]; 61 | end 62 | endcase 63 | 64 | end else begin// PC + 4; 65 | niaddr = pc4; 66 | end 67 | end 68 | 69 | endmodule // Next Program Counter; 70 | -------------------------------------------------------------------------------- /Project_Assignment_OnBoard/pc.v: -------------------------------------------------------------------------------- 1 | module pc (clk, rst, niaddr, iaddr); 2 | input clk; 3 | input rst; 4 | input [31:0] niaddr;// Next Instruction Address; 5 | 6 | output reg [31:0] iaddr;// Instruction Address; 7 | 8 | always @ ( posedge clk ) begin 9 | if (!rst) 10 | iaddr <= 32'h0000_0000; 11 | else 12 | iaddr <= niaddr; 13 | end 14 | endmodule // Program Counter; 15 | -------------------------------------------------------------------------------- /Project_Assignment_OnBoard/regfile.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Triple-Z/COExperiment_Repo/7a0ad4c5d025753d560e8a433fb26ea406268b1b/Project_Assignment_OnBoard/regfile.v -------------------------------------------------------------------------------- /Project_Assignment_OnBoard/rf.v: -------------------------------------------------------------------------------- 1 | module regFile (busW, clk, wE, rW, rA, rB, busA, busB, test_addr, test_data, rst); 2 | input [31:0] busW; 3 | input [4:0] rW, rA, rB; 4 | input clk; 5 | input [1:0] wE; 6 | output [31:0] busA, busB; 7 | input rst; 8 | 9 | input [4 :0] test_addr; 10 | output [31:0] test_data; 11 | 12 | reg [31:0] register[0:31]; 13 | 14 | initial begin 15 | register[0] <= 0;// $zero; 16 | 17 | register[8] <= 0;// $t0; 18 | register[9] <= 1;// $t1; 19 | register[10] <= 2;// $t2; 20 | register[11] <= 3;// $t3; 21 | register[12] <= 4;// $t4; 22 | register[13] <= 5;// $t5; 23 | register[14] <= 6;// $t6; 24 | register[15] <= 7;// $t7; 25 | 26 | register[16] <= 0;// $s0; 27 | register[17] <= 0;// $s1; 28 | register[18] <= 0;// $s2; 29 | register[19] <= 0;// $s3; 30 | end 31 | 32 | assign busA = (rA != 0)? register[rA]: 0; 33 | assign busB = (rB != 0)? register[rB]: 0; 34 | 35 | always @ ( posedge clk ) begin 36 | if ((wE == 2'b01) && (rW != 0)) begin 37 | register[rW] = busW; 38 | end 39 | if (!rst) begin 40 | register[0] <= 0;// $zero; 41 | 42 | register[8] <= 0;// $t0; 43 | register[9] <= 1;// $t1; 44 | register[10] <= 2;// $t2; 45 | register[11] <= 3;// $t3; 46 | register[12] <= 4;// $t4; 47 | register[13] <= 5;// $t5; 48 | register[14] <= 6;// $t6; 49 | register[15] <= 7;// $t7; 50 | 51 | register[16] <= 0;// $s0; 52 | register[17] <= 0;// $s1; 53 | register[18] <= 0;// $s2; 54 | register[19] <= 0;// $s3; 55 | end 56 | end 57 | 58 | assign test_data = register[test_addr]; 59 | 60 | 61 | endmodule // Register File 62 | -------------------------------------------------------------------------------- /Project_Assignment_OnBoard/single_cycle_cpu.ucf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Triple-Z/COExperiment_Repo/7a0ad4c5d025753d560e8a433fb26ea406268b1b/Project_Assignment_OnBoard/single_cycle_cpu.ucf -------------------------------------------------------------------------------- /Project_Assignment_OnBoard/single_cycle_cpu.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Triple-Z/COExperiment_Repo/7a0ad4c5d025753d560e8a433fb26ea406268b1b/Project_Assignment_OnBoard/single_cycle_cpu.v -------------------------------------------------------------------------------- /Project_Assignment_OnBoard/single_cycle_cpu_display.bit: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Triple-Z/COExperiment_Repo/7a0ad4c5d025753d560e8a433fb26ea406268b1b/Project_Assignment_OnBoard/single_cycle_cpu_display.bit -------------------------------------------------------------------------------- /Project_Assignment_OnBoard/single_cycle_cpu_display.bld: -------------------------------------------------------------------------------- 1 | Release 13.2 ngdbuild O.61xd (nt64) 2 | Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. 3 | 4 | Command Line: D:\Xilinx\13.2\ISE_DS\ISE\bin\nt64\unwrapped\ngdbuild.exe 5 | -intstyle ise -dd _ngo -nt timestamp -uc single_cycle_cpu.ucf -p 6 | xc6slx150-fgg676-3 single_cycle_cpu_display.ngc single_cycle_cpu_display.ngd 7 | 8 | Reading NGO file 9 | "E:/loongson/CPU_LAB_greenfpga/LS_CPU_LAB/6_single_cycle_cpu/single_cycle_cpu_di 10 | splay.ngc" ... 11 | Loading design module 12 | "E:\loongson\CPU_LAB_greenfpga\LS_CPU_LAB\6_single_cycle_cpu/lcd_module.ngc"... 13 | Loading design module 14 | "E:\loongson\CPU_LAB_greenfpga\LS_CPU_LAB\6_single_cycle_cpu/lcd_rom.ngc"... 15 | Gathering constraint information from source properties... 16 | Done. 17 | 18 | Annotating constraints to design from ucf file "single_cycle_cpu.ucf" ... 19 | Resolving constraint associations... 20 | Checking Constraint Associations... 21 | Done... 22 | 23 | Checking expanded design ... 24 | WARNING:NgdBuild:452 - logical net 'N779' has no driver 25 | WARNING:NgdBuild:452 - logical net 'N780' has no driver 26 | 27 | Partition Implementation Status 28 | ------------------------------- 29 | 30 | No Partitions were found in this design. 31 | 32 | ------------------------------- 33 | 34 | NGDBUILD Design Results Summary: 35 | Number of errors: 0 36 | Number of warnings: 2 37 | 38 | Total memory usage is 158704 kilobytes 39 | 40 | Writing NGD file "single_cycle_cpu_display.ngd" ... 41 | Total REAL time to NGDBUILD completion: 4 sec 42 | Total CPU time to NGDBUILD completion: 4 sec 43 | 44 | Writing NGDBUILD log file "single_cycle_cpu_display.bld"... 45 | -------------------------------------------------------------------------------- /Project_Assignment_OnBoard/single_cycle_cpu_display.drc: -------------------------------------------------------------------------------- 1 | Release 13.2 Drc O.61xd (nt64) 2 | Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. 3 | 4 | Thu Nov 17 23:16:22 2016 5 | 6 | drc -z single_cycle_cpu_display.ncd single_cycle_cpu_display.pcf 7 | 8 | WARNING:PhysDesignRules:367 - The signal is 9 | incomplete. The signal does not drive any load pins in the design. 10 | DRC detected 0 errors and 1 warnings. Please see the previously displayed 11 | individual error or warning messages for more details. 12 | -------------------------------------------------------------------------------- /Project_Assignment_OnBoard/single_cycle_cpu_display.lso: -------------------------------------------------------------------------------- 1 | work 2 | -------------------------------------------------------------------------------- /Project_Assignment_OnBoard/single_cycle_cpu_display.prj: -------------------------------------------------------------------------------- 1 | verilog work "adder.v" 2 | verilog work "regfile.v" 3 | verilog work "inst_rom.v" 4 | verilog work "data_ram.v" 5 | verilog work "alu.v" 6 | verilog work "single_cycle_cpu.v" 7 | verilog work "lcd_module.v" 8 | verilog work "single_cycle_cpu_display.v" 9 | -------------------------------------------------------------------------------- /Project_Assignment_OnBoard/single_cycle_cpu_display.stx: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Triple-Z/COExperiment_Repo/7a0ad4c5d025753d560e8a433fb26ea406268b1b/Project_Assignment_OnBoard/single_cycle_cpu_display.stx -------------------------------------------------------------------------------- /Project_Assignment_OnBoard/single_cycle_cpu_display.unroutes: -------------------------------------------------------------------------------- 1 | Release 13.2 - par O.61xd (nt64) 2 | Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. 3 | 4 | Thu Nov 17 23:15:39 2016 5 | 6 | All signals are completely routed. 7 | 8 | WARNING:ParHelpers:361 - There are 1 loadless signals in this design. This design will cause Bitgen to issue DRC 9 | warnings. 10 | 11 | lcd_module/touch_module/int_io/O 12 | 13 | 14 | -------------------------------------------------------------------------------- /Project_Assignment_OnBoard/single_cycle_cpu_display.ut: -------------------------------------------------------------------------------- 1 | -w 2 | -g DebugBitstream:No 3 | -g Binary:no 4 | -g CRC:Enable 5 | -g Reset_on_err:No 6 | -g ConfigRate:2 7 | -g ProgPin:PullUp 8 | -g TckPin:PullUp 9 | -g TdiPin:PullUp 10 | -g TdoPin:PullUp 11 | -g TmsPin:PullUp 12 | -g UnusedPin:PullDown 13 | -g UserID:0xFFFFFFFF 14 | -g ExtMasterCclk_en:No 15 | -g SPI_buswidth:1 16 | -g TIMER_CFG:0xFFFF 17 | -g multipin_wakeup:No 18 | -g StartUpClk:CClk 19 | -g DONE_cycle:4 20 | -g GTS_cycle:5 21 | -g GWE_cycle:6 22 | -g LCK_cycle:NoWait 23 | -g Security:None 24 | -g DonePipe:No 25 | -g DriveDone:No 26 | -g Encrypt:No 27 | -g en_sw_gsr:No 28 | -g drive_awake:No 29 | -g sw_clk:Startupclk 30 | -g sw_gwe_cycle:5 31 | -g sw_gts_cycle:4 32 | -------------------------------------------------------------------------------- /Project_Assignment_OnBoard/single_cycle_cpu_display.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Triple-Z/COExperiment_Repo/7a0ad4c5d025753d560e8a433fb26ea406268b1b/Project_Assignment_OnBoard/single_cycle_cpu_display.v -------------------------------------------------------------------------------- /Project_Assignment_OnBoard/single_cycle_cpu_display.xpi: -------------------------------------------------------------------------------- 1 | PROGRAM=PAR 2 | STATE=ROUTED 3 | TIMESPECS_MET=YES 4 | -------------------------------------------------------------------------------- /Project_Assignment_OnBoard/single_cycle_cpu_display.xst: -------------------------------------------------------------------------------- 1 | set -tmpdir "xst/projnav.tmp" 2 | set -xsthdpdir "xst" 3 | run 4 | -ifn single_cycle_cpu_display.prj 5 | -ifmt mixed 6 | -ofn single_cycle_cpu_display 7 | -ofmt NGC 8 | -p xc6slx150-3-fgg676 9 | -top single_cycle_cpu_display 10 | -opt_mode Speed 11 | -opt_level 1 12 | -power NO 13 | -iuc NO 14 | -keep_hierarchy No 15 | -netlist_hierarchy As_Optimized 16 | -rtlview Yes 17 | -glob_opt AllClockNets 18 | -read_cores YES 19 | -write_timing_constraints NO 20 | -cross_clock_analysis NO 21 | -hierarchy_separator / 22 | -bus_delimiter <> 23 | -case Maintain 24 | -slice_utilization_ratio 100 25 | -bram_utilization_ratio 100 26 | -dsp_utilization_ratio 100 27 | -lc Auto 28 | -reduce_control_sets Auto 29 | -fsm_extract YES -fsm_encoding Auto 30 | -safe_implementation No 31 | -fsm_style LUT 32 | -ram_extract Yes 33 | -ram_style Auto 34 | -rom_extract Yes 35 | -shreg_extract YES 36 | -rom_style Auto 37 | -auto_bram_packing NO 38 | -resource_sharing YES 39 | -async_to_sync NO 40 | -shreg_min_size 2 41 | -use_dsp48 Auto 42 | -iobuf YES 43 | -max_fanout 100000 44 | -bufg 16 45 | -register_duplication YES 46 | -register_balancing No 47 | -optimize_primitives NO 48 | -use_clock_enable Auto 49 | -use_sync_set Auto 50 | -use_sync_reset Auto 51 | -iob Auto 52 | -equivalent_register_removal YES 53 | -slice_utilization_ratio_maxmargin 5 54 | -------------------------------------------------------------------------------- /Project_Assignment_OnBoard/single_cycle_cpu_display_bitgen.xwbt: -------------------------------------------------------------------------------- 1 | INTSTYLE=ise 2 | INFILE=E:\loongson\CPU_LAB_greenfpga\LS_CPU_LAB\6_single_cycle_cpu\single_cycle_cpu_display.ncd 3 | OUTFILE=E:\loongson\CPU_LAB_greenfpga\LS_CPU_LAB\6_single_cycle_cpu\single_cycle_cpu_display.bit 4 | FAMILY=Spartan6 5 | PART=xc6slx150-3fgg676 6 | WORKINGDIR=E:\loongson\CPU_LAB_greenfpga\LS_CPU_LAB\6_single_cycle_cpu 7 | LICENSE=ISE 8 | USER_INFO=135256_15690819_173552794_661 9 | -------------------------------------------------------------------------------- /Project_Assignment_OnBoard/single_cycle_cpu_display_summary.html: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Triple-Z/COExperiment_Repo/7a0ad4c5d025753d560e8a433fb26ea406268b1b/Project_Assignment_OnBoard/single_cycle_cpu_display_summary.html -------------------------------------------------------------------------------- /Project_Assignment_OnBoard/single_cycle_cpu_display_summary.xml: -------------------------------------------------------------------------------- 1 | 2 | 7 | 8 | 9 | 10 | 11 | -------------------------------------------------------------------------------- /Project_Assignment_OnBoard/tb.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | //////////////////////////////////////////////////////////////////////////////// 4 | // Company: 5 | // Engineer: 6 | // 7 | // Create Date: 16:49:44 04/19/2016 8 | // Design Name: single_cycle_cpu 9 | // Module Name: F:/new_lab/6_single_cycle_cpu/tb.v 10 | // Project Name: single_cycle_cpu 11 | // Target Device: 12 | // Tool versions: 13 | // Description: 14 | // 15 | // Verilog Test Fixture created by ISE for module: single_cycle_cpu 16 | // 17 | // Dependencies: 18 | // 19 | // Revision: 20 | // Revision 0.01 - File Created 21 | // Additional Comments: 22 | // 23 | //////////////////////////////////////////////////////////////////////////////// 24 | 25 | module tb; 26 | 27 | // Inputs 28 | reg clk; 29 | reg resetn; 30 | reg [4:0] rf_addr; 31 | reg [31:0] mem_addr; 32 | 33 | // Outputs 34 | wire [31:0] rf_data; 35 | wire [31:0] mem_data; 36 | wire [31:0] cpu_pc; 37 | wire [31:0] cpu_inst; 38 | 39 | // Instantiate the Unit Under Test (UUT) 40 | single_cycle_cpu uut ( 41 | .clk(clk), 42 | .resetn(resetn), 43 | .rf_addr(rf_addr), 44 | .mem_addr(mem_addr), 45 | .rf_data(rf_data), 46 | .mem_data(mem_data), 47 | .cpu_pc(cpu_pc), 48 | .cpu_inst(cpu_inst) 49 | ); 50 | 51 | initial begin 52 | // Initialize Inputs 53 | clk = 0; 54 | resetn = 0; 55 | rf_addr = 0; 56 | mem_addr = 0; 57 | 58 | // Wait 100 ns for global reset to finish 59 | #100; 60 | resetn = 1; 61 | // Add stimulus here 62 | end 63 | always #5 clk=~clk; 64 | endmodule 65 | 66 | -------------------------------------------------------------------------------- /Project_Assignment_OnBoard/webtalk.log: -------------------------------------------------------------------------------- 1 | Release 13.2 - WebTalk (O.61xd) 2 | Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. 3 | 4 | Project Information 5 | -------------------- 6 | ProjectID=01C144C58F3D4B039FB82475AAFB0663 7 | ProjectIteration=14 8 | 9 | WebTalk Summary 10 | ---------------- 11 | INFO:WebTalk:3 - WebTalk is disabled. 12 | 13 | INFO:WebTalk:9 - WebTalk Install setting is OFF. 14 | INFO:WebTalk:6 - WebTalk User setting is ON. 15 | -------------------------------------------------------------------------------- /Project_Assignment_OnBoard/xlnx_auto_0_xdb/cst.xbcd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Triple-Z/COExperiment_Repo/7a0ad4c5d025753d560e8a433fb26ea406268b1b/Project_Assignment_OnBoard/xlnx_auto_0_xdb/cst.xbcd -------------------------------------------------------------------------------- /Project_Assignment_OnBoard/xst/work/work.sdbl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Triple-Z/COExperiment_Repo/7a0ad4c5d025753d560e8a433fb26ea406268b1b/Project_Assignment_OnBoard/xst/work/work.sdbl -------------------------------------------------------------------------------- /Project_Assignment_OnBoard/xst/work/work.sdbx: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Triple-Z/COExperiment_Repo/7a0ad4c5d025753d560e8a433fb26ea406268b1b/Project_Assignment_OnBoard/xst/work/work.sdbx -------------------------------------------------------------------------------- /_config.yml: -------------------------------------------------------------------------------- 1 | theme: jekyll-theme-cayman --------------------------------------------------------------------------------