├── db ├── traffic_led.map.logdb ├── traffic_led.map_bb.logdb ├── traffic_led.smart_action.txt ├── traffic_led.hif ├── traffic_led.ipinfo ├── traffic_led.asm.rdb ├── traffic_led.cmp.bpm ├── traffic_led.cmp.cdb ├── traffic_led.cmp.hdb ├── traffic_led.cmp.idb ├── traffic_led.cmp.rdb ├── traffic_led.lpc.rdb ├── traffic_led.map.bpm ├── traffic_led.map.cdb ├── traffic_led.map.hdb ├── traffic_led.map.kpt ├── traffic_led.map.rdb ├── traffic_led.rtlv.hdb ├── traffic_led.sta.rdb ├── traffic_led.(0).cnf.cdb ├── traffic_led.(0).cnf.hdb ├── traffic_led.(1).cnf.cdb ├── traffic_led.(1).cnf.hdb ├── traffic_led.(2).cnf.cdb ├── traffic_led.(2).cnf.hdb ├── traffic_led.(3).cnf.cdb ├── traffic_led.(3).cnf.hdb ├── traffic_led.(4).cnf.cdb ├── traffic_led.(4).cnf.hdb ├── traffic_led.(5).cnf.cdb ├── traffic_led.(5).cnf.hdb ├── traffic_led.(6).cnf.cdb ├── traffic_led.(6).cnf.hdb ├── traffic_led.(7).cnf.cdb ├── traffic_led.(7).cnf.hdb ├── traffic_led.(8).cnf.cdb ├── traffic_led.(8).cnf.hdb ├── traffic_led.(9).cnf.cdb ├── traffic_led.(9).cnf.hdb ├── traffic_led.map.ammdb ├── traffic_led.map_bb.cdb ├── traffic_led.map_bb.hdb ├── traffic_led.pre_map.hdb ├── traffic_led.routing.rdb ├── traffic_led.rtlv_sg.cdb ├── traffic_led.sgdiff.cdb ├── traffic_led.sgdiff.hdb ├── logic_util_heursitic.dat ├── traffic_led.(10).cnf.cdb ├── traffic_led.(10).cnf.hdb ├── traffic_led.(11).cnf.cdb ├── traffic_led.(11).cnf.hdb ├── traffic_led.asm_labs.ddb ├── traffic_led.cmp_merge.kpt ├── traffic_led.pti_db_list.ddb ├── traffic_led.rtlv_sg_swap.cdb ├── traffic_led.sld_design_entry.sci ├── traffic_led.sld_design_entry_dsc.sci ├── traffic_led.tiscmp.fast_1200mv_0c.ddb ├── traffic_led.tiscmp.slow_1200mv_0c.ddb ├── traffic_led.db_info ├── traffic_led.root_partition.map.reg_db.cdb ├── traffic_led.sta_cmp.8_slow_1200mv_85c.tdb ├── traffic_led.tiscmp.fastest_slow_1200mv_0c.ddb ├── traffic_led.tiscmp.fastest_slow_1200mv_85c.ddb ├── traffic_led.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd ├── traffic_led.cycloneive_io_sim_cache.45um_ss_1200mv_0c_slow.hsd ├── traffic_led.cycloneive_io_sim_cache.45um_ss_1200mv_85c_slow.hsd ├── traffic_led.cbx.xml ├── traffic_led.lpc.html ├── add_sub_7pc.tdf ├── traffic_led.lpc.txt ├── add_sub_8pc.tdf ├── lpm_divide_vam.tdf ├── lpm_divide_sim.tdf ├── sign_div_unsign_klh.tdf ├── traffic_led.eda.qmsg ├── traffic_led.asm.qmsg ├── traffic_led.analyze_file.qmsg ├── alt_u_div_s6f.tdf ├── traffic_led.sta.qmsg ├── traffic_led.cmp.logdb └── traffic_led.hier_info ├── output_files ├── traffic_led.done ├── traffic_led.sof ├── traffic_led.fit.rpt ├── traffic_led.jdi ├── traffic_led.map.summary ├── traffic_led.fit.summary ├── traffic_led.fit.smsg ├── traffic_led.sta.summary ├── traffic_led.eda.rpt ├── traffic_led.asm.rpt └── traffic_led.flow.rpt ├── incremental_db ├── compiled_partitions │ ├── traffic_led.root_partition.cmp.logdb │ ├── traffic_led.root_partition.map.hbdb.sig │ ├── traffic_led.db_info │ ├── traffic_led.root_partition.cmp.ammdb │ ├── traffic_led.root_partition.cmp.cdb │ ├── traffic_led.root_partition.cmp.dfp │ ├── traffic_led.root_partition.cmp.hdb │ ├── traffic_led.root_partition.cmp.rcfdb │ ├── traffic_led.root_partition.map.cdb │ ├── traffic_led.root_partition.map.dpi │ ├── traffic_led.root_partition.map.hdb │ ├── traffic_led.root_partition.map.kpt │ ├── traffic_led.root_partition.map.hbdb.cdb │ ├── traffic_led.root_partition.map.hbdb.hdb │ └── traffic_led.root_partition.map.hbdb.hb_info └── README ├── traffic_led └── simulation │ └── qsim │ └── traffic_led.sft ├── traffic_led.qws ├── traffic_led_nativelink_simulation.rpt ├── README.md ├── traffic_led_inst.v ├── traffic_led.qpf ├── traffic_led.v ├── test.v ├── traffic_led.bsf ├── led_module.v ├── state_trans_model.bsf ├── traffic_led.qsf ├── bit_seg_module.v ├── state_trans_model.v └── traffic_led.bdf /db/traffic_led.map.logdb: -------------------------------------------------------------------------------- 1 | v1 2 | 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https://raw.githubusercontent.com/Tristan-SHU/SHU-Computer-Hardware-Major-Assignment/HEAD/incremental_db/compiled_partitions/traffic_led.root_partition.map.hbdb.hb_info -------------------------------------------------------------------------------- /output_files/traffic_led.jdi: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | -------------------------------------------------------------------------------- /output_files/traffic_led.map.summary: -------------------------------------------------------------------------------- 1 | Analysis & Synthesis Status : Successful - Mon Jul 04 19:18:05 2022 2 | Quartus II 64-Bit Version : 13.1.0 Build 162 10/23/2013 SJ Web Edition 3 | Revision Name : traffic_led 4 | Top-level Entity Name : traffic_led 5 | Family : Cyclone IV E 6 | Total logic elements : 779 7 | Total combinational functions : 766 8 | Dedicated logic registers : 124 9 | Total registers : 124 10 | Total pins : 46 11 | Total virtual pins : 0 12 | Total memory bits : 0 13 | Embedded Multiplier 9-bit elements : 0 14 | Total PLLs : 0 15 | -------------------------------------------------------------------------------- /incremental_db/README: -------------------------------------------------------------------------------- 1 | This folder contains data for incremental compilation. 2 | 3 | The compiled_partitions sub-folder contains previous compilation results for each partition. 4 | As long as this folder is preserved, incremental compilation results from earlier compiles 5 | can be re-used. To perform a clean compilation from source files for all partitions, both 6 | the db and incremental_db folder should be removed. 7 | 8 | The imported_partitions sub-folder contains the last imported QXP for each imported partition. 9 | As long as this folder is preserved, imported partitions will be automatically re-imported 10 | when the db or incremental_db/compiled_partitions folders are removed. 11 | 12 | -------------------------------------------------------------------------------- /output_files/traffic_led.fit.summary: -------------------------------------------------------------------------------- 1 | Fitter Status : Successful - Mon Jul 04 19:18:13 2022 2 | Quartus II 64-Bit Version : 13.1.0 Build 162 10/23/2013 SJ Web Edition 3 | Revision Name : traffic_led 4 | Top-level Entity Name : traffic_led 5 | Family : Cyclone IV E 6 | Device : EP4CE6F17C8 7 | Timing Models : Final 8 | Total logic elements : 781 / 6,272 ( 12 % ) 9 | Total combinational functions : 767 / 6,272 ( 12 % ) 10 | Dedicated logic registers : 124 / 6,272 ( 2 % ) 11 | Total registers : 124 12 | Total pins : 46 / 180 ( 26 % ) 13 | Total virtual pins : 0 14 | Total memory bits : 0 / 276,480 ( 0 % ) 15 | Embedded Multiplier 9-bit elements : 0 / 30 ( 0 % ) 16 | Total PLLs : 0 / 2 ( 0 % ) 17 | -------------------------------------------------------------------------------- /output_files/traffic_led.fit.smsg: -------------------------------------------------------------------------------- 1 | Extra Info (176273): Performing register packing on registers with non-logic cell location assignments 2 | Extra Info (176274): Completed register packing on registers with non-logic cell location assignments 3 | Extra Info (176236): Started Fast Input/Output/OE register processing 4 | Extra Info (176237): Finished Fast Input/Output/OE register processing 5 | Extra Info (176238): Start inferring scan chains for DSP blocks 6 | Extra Info (176239): Inferring scan chains for DSP blocks is complete 7 | Extra Info (176248): Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density 8 | Extra Info (176249): Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks 9 | -------------------------------------------------------------------------------- /db/traffic_led.cbx.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | -------------------------------------------------------------------------------- /traffic_led_nativelink_simulation.rpt: -------------------------------------------------------------------------------- 1 | Info: Start Nativelink Simulation process 2 | Info: NativeLink has detected Verilog design -- Verilog simulation models will be used 3 | 4 | ========= EDA Simulation Settings ===================== 5 | 6 | Sim Mode : RTL 7 | Family : cycloneive 8 | Quartus root : d:/altera/13.1/quartus/bin64/ 9 | Quartus sim root : d:/altera/13.1/quartus/eda/sim_lib 10 | Simulation Tool : modelsim-altera 11 | Simulation Language : verilog 12 | Simulation Mode : GUI 13 | Sim Output File : 14 | Sim SDF file : 15 | Sim dir : simulation\modelsim 16 | 17 | ======================================================= 18 | 19 | Info: Starting NativeLink simulation with ModelSim-Altera software 20 | Sourced NativeLink script d:/altera/13.1/quartus/common/tcl/internal/nativelink/modelsim.tcl 21 | Warning: File traffic_led_run_msim_rtl_verilog.do already exists - backing up current file as traffic_led_run_msim_rtl_verilog.do.bak11 22 | Info: Spawning ModelSim-Altera Simulation software 23 | -------------------------------------------------------------------------------- /db/traffic_led.lpc.html: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | 45 | 46 | 47 | 48 | 49 | 50 | 51 | 52 | 53 | 54 | 55 | 56 | 57 | 58 | 59 | 60 | 61 | 62 | 63 | 64 | 65 | 66 |
HierarchyInputConstant InputUnused InputFloating InputOutputConstant OutputUnused OutputFloating OutputBidirConstant BidirUnused BidirInput only BidirOutput only Bidir
u2_led_module100102400000000
u1_bit_seg_module431011611100000
u0_state_trans_model20008400000000
67 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # 上海大学 计算机硬件综合大型作业 2 | 3 | ## 项目二 交通灯控制器 4 | 5 | ### 项目要求 6 | 7 | 十字路口，每面3个灯+二位数码管倒计时显示 8 | 9 | ### 快速入门 10 | 11 | 下载文件，安装Quartus，打开项目文件即可食用 12 | 13 | FYI：Quartus安装包可以问通信与信息工程学院的同学要（白嫖），他们的工程教育课程使用此软件。 14 | 15 | ### 目录说明 16 | 17 | ``` 18 | ├─ traffic_led // 项目的ModelSim仿真文件的文件夹，应该转移至与项目工程平行的目录下 19 | ├─ traffic_led.qpf // 项目的工程文件 20 | ├─ traffic_led.bdf // 电路图 21 | ├─ traffic_led.bsf 22 | ├─ traffic_led.v // 顶层模块文件 23 | ├─ state_trans_model.v // 控制器模块 24 | ├─ traffic_led_inst.v // 交通灯模块 25 | ├─ led_module.v // LED灯模块 26 | ├─ bit_seg_module.v // 数码管模块 27 | ├─ test.v // 测试文件 28 | ``` 29 | 30 | ### 主要功能 31 | 32 | - 可设定亮灯时间 33 | - 可设定不同亮灯模式（正常方式、单向绿灯、双向黄灯闪烁、双向红灯） 34 | - 注意倒计时超过100秒情况下数码管的显示 35 | 36 | ### 注意事项 37 | 38 | - 项目基于Quartus 13.1.0 Web Edition，已验收通过 39 | - 加入了左转信号灯。每个路口都采用数码管显示倒计时（只有南北或东西直行方向有，左转则为亮灯提示） 40 | - 通过Key和sys_rst_n的不同输入信号，切换亮灯模式 41 | - 【正常模式】对应的Key为1111，【南北方向绿灯模式】为1110，【东西方向绿灯模式】为1101，【黄灯模式】为1011 42 | - sys_rst_n为0时，为遇到紧急情况进入【红灯模式】，倒计时停止，Key值输入无效，此时交通灯变为全红灯，不受其他输入信号干扰 43 | - 如需要修改倒计时时间，可直接修改state_trans_model.v中的parameter define 44 | 45 | ### 参考资料 46 | 47 | 本项目基于YuanZhaoHui1999的trafficlight-based-on-Verilog，并加以修改以满足课程要求，感谢其共享！ 48 | 49 | 链接：https://github.com/YuanZhaoHui1999/trafficlight-based-on-Verilog 50 | -------------------------------------------------------------------------------- /traffic_led_inst.v: -------------------------------------------------------------------------------- 1 | // Copyright (C) 1991-2013 Altera Corporation 2 | // Your use of Altera Corporation's design tools, logic functions 3 | // and other software and tools, and its AMPP partner logic 4 | // functions, and any output files from any of the foregoing 5 | // (including device programming or simulation files), and any 6 | // associated documentation or information are expressly subject 7 | // to the terms and conditions of the Altera Program License 8 | // Subscription Agreement, Altera MegaCore Function License 9 | // Agreement, or other applicable license agreement, including, 10 | // without limitation, that your use is for the sole purpose of 11 | // programming logic devices manufactured by Altera and sold by 12 | // Altera or its authorized distributors. Please refer to the 13 | // applicable agreement for further details. 14 | 15 | 16 | // Generated by Quartus II 64-Bit Version 13.1 (Build Build 162 10/23/2013) 17 | // Created on Wed Jun 22 14:32:08 2022 18 | 19 | traffic_led traffic_led_inst 20 | ( 21 | .sys_clk(sys_clk_sig) , // input sys_clk_sig 22 | .sys_rst_n(sys_rst_n_sig) , // input sys_rst_n_sig 23 | .key(key_sig) , // input [3:0] key_sig 24 | .bit(bit_sig) , // output [7:0] bit_sig 25 | .segment(segment_sig) , // output [7:0] segment_sig 26 | .led(led_sig) // output [23:0] led_sig 27 | ); 28 | -------------------------------------------------------------------------------- /traffic_led.qpf: -------------------------------------------------------------------------------- 1 | # -------------------------------------------------------------------------- # 2 | # 3 | # Copyright (C) 1991-2015 Altera Corporation. All rights reserved. 4 | # Your use of Altera Corporation's design tools, logic functions 5 | # and other software and tools, and its AMPP partner logic 6 | # functions, and any output files from any of the foregoing 7 | # (including device programming or simulation files), and any 8 | # associated documentation or information are expressly subject 9 | # to the terms and conditions of the Altera Program License 10 | # Subscription Agreement, the Altera Quartus II License Agreement, 11 | # the Altera MegaCore Function License Agreement, or other 12 | # applicable license agreement, including, without limitation, 13 | # that your use is for the sole purpose of programming logic 14 | # devices manufactured by Altera and sold by Altera or its 15 | # authorized distributors. Please refer to the applicable 16 | # agreement for further details. 17 | # 18 | # -------------------------------------------------------------------------- # 19 | # 20 | # Quartus II 64-Bit 21 | # Version 15.0.0 Build 145 04/22/2015 SJ Full Version 22 | # Date created = 22:59:01 June 19, 2020 23 | # 24 | # -------------------------------------------------------------------------- # 25 | 26 | QUARTUS_VERSION = "15.0" 27 | DATE = "22:59:01 June 19, 2020" 28 | 29 | # Revisions 30 | 31 | PROJECT_REVISION = "traffic_led" 32 | -------------------------------------------------------------------------------- /db/add_sub_7pc.tdf: -------------------------------------------------------------------------------- 1 | --lpm_add_sub CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 DEVICE_FAMILY="Cyclone IV E" LPM_DIRECTION="SUB" LPM_WIDTH=1 cout dataa datab result 2 | --VERSION_BEGIN 13.1 cbx_cycloneii 2013:10:23:18:05:48:SJ cbx_lpm_add_sub 2013:10:23:18:05:48:SJ cbx_mgl 2013:10:23:18:06:54:SJ cbx_stratix 2013:10:23:18:05:48:SJ cbx_stratixii 2013:10:23:18:05:48:SJ VERSION_END 3 | 4 | 5 | -- Copyright (C) 1991-2013 Altera Corporation 6 | -- Your use of Altera Corporation's design tools, logic functions 7 | -- and other software and tools, and its AMPP partner logic 8 | -- functions, and any output files from any of the foregoing 9 | -- (including device programming or simulation files), and any 10 | -- associated documentation or information are expressly subject 11 | -- to the terms and conditions of the Altera Program License 12 | -- Subscription Agreement, Altera MegaCore Function License 13 | -- Agreement, or other applicable license agreement, including, 14 | -- without limitation, that your use is for the sole purpose of 15 | -- programming logic devices manufactured by Altera and sold by 16 | -- Altera or its authorized distributors. Please refer to the 17 | -- applicable agreement for further details. 18 | 19 | 20 | 21 | --synthesis_resources = 22 | SUBDESIGN add_sub_7pc 23 | ( 24 | cout : output; 25 | dataa[0..0] : input; 26 | datab[0..0] : input; 27 | result[0..0] : output; 28 | ) 29 | VARIABLE 30 | carry_eqn[0..0] : WIRE; 31 | cin_wire : WIRE; 32 | datab_node[0..0] : WIRE; 33 | sum_eqn[0..0] : WIRE; 34 | 35 | BEGIN 36 | carry_eqn[] = ( ((dataa[0..0] & datab_node[0..0]) # ((dataa[0..0] # datab_node[0..0]) & cin_wire))); 37 | cin_wire = B"1"; 38 | cout = carry_eqn[0..0]; 39 | datab_node[] = (! datab[]); 40 | result[] = sum_eqn[]; 41 | sum_eqn[] = ( ((dataa[0..0] $ datab_node[0..0]) $ cin_wire)); 42 | END; 43 | --VALID FILE 44 | -------------------------------------------------------------------------------- /db/traffic_led.lpc.txt: -------------------------------------------------------------------------------- 1 | +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ 2 | ; Legal Partition Candidates ; 3 | +----------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ 4 | ; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ; 5 | +----------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ 6 | ; u2_led_module ; 10 ; 0 ; 1 ; 0 ; 24 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 7 | ; u1_bit_seg_module ; 43 ; 1 ; 0 ; 1 ; 16 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 8 | ; u0_state_trans_model ; 2 ; 0 ; 0 ; 0 ; 84 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 9 | +----------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ 10 | -------------------------------------------------------------------------------- /db/add_sub_8pc.tdf: -------------------------------------------------------------------------------- 1 | --lpm_add_sub CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 DEVICE_FAMILY="Cyclone IV E" LPM_DIRECTION="SUB" LPM_WIDTH=2 cout dataa datab result 2 | --VERSION_BEGIN 13.1 cbx_cycloneii 2013:10:23:18:05:48:SJ cbx_lpm_add_sub 2013:10:23:18:05:48:SJ cbx_mgl 2013:10:23:18:06:54:SJ cbx_stratix 2013:10:23:18:05:48:SJ cbx_stratixii 2013:10:23:18:05:48:SJ VERSION_END 3 | 4 | 5 | -- Copyright (C) 1991-2013 Altera Corporation 6 | -- Your use of Altera Corporation's design tools, logic functions 7 | -- and other software and tools, and its AMPP partner logic 8 | -- functions, and any output files from any of the foregoing 9 | -- (including device programming or simulation files), and any 10 | -- associated documentation or information are expressly subject 11 | -- to the terms and conditions of the Altera Program License 12 | -- Subscription Agreement, Altera MegaCore Function License 13 | -- Agreement, or other applicable license agreement, including, 14 | -- without limitation, that your use is for the sole purpose of 15 | -- programming logic devices manufactured by Altera and sold by 16 | -- Altera or its authorized distributors. Please refer to the 17 | -- applicable agreement for further details. 18 | 19 | 20 | 21 | --synthesis_resources = 22 | SUBDESIGN add_sub_8pc 23 | ( 24 | cout : output; 25 | dataa[1..0] : input; 26 | datab[1..0] : input; 27 | result[1..0] : output; 28 | ) 29 | VARIABLE 30 | carry_eqn[1..0] : WIRE; 31 | cin_wire : WIRE; 32 | datab_node[1..0] : WIRE; 33 | sum_eqn[1..0] : WIRE; 34 | 35 | BEGIN 36 | carry_eqn[] = ( ((dataa[1..1] & datab_node[1..1]) # ((dataa[1..1] # datab_node[1..1]) & carry_eqn[0..0])), ((dataa[0..0] & datab_node[0..0]) # ((dataa[0..0] # datab_node[0..0]) & cin_wire))); 37 | cin_wire = B"1"; 38 | cout = carry_eqn[1..1]; 39 | datab_node[] = (! datab[]); 40 | result[] = sum_eqn[]; 41 | sum_eqn[] = ( ((dataa[1..1] $ datab_node[1..1]) $ carry_eqn[0..0]), ((dataa[0..0] $ datab_node[0..0]) $ cin_wire)); 42 | END; 43 | --VALID FILE 44 | -------------------------------------------------------------------------------- /db/lpm_divide_vam.tdf: -------------------------------------------------------------------------------- 1 | --lpm_divide DEVICE_FAMILY="Cyclone IV E" LPM_DREPRESENTATION="UNSIGNED" LPM_NREPRESENTATION="UNSIGNED" LPM_WIDTHD=4 LPM_WIDTHN=10 OPTIMIZE_FOR_SPEED=5 denom numer remain CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 IGNORE_CARRY_BUFFERS="OFF" 2 | --VERSION_BEGIN 13.1 cbx_cycloneii 2013:10:23:18:05:48:SJ cbx_lpm_abs 2013:10:23:18:05:48:SJ cbx_lpm_add_sub 2013:10:23:18:05:48:SJ cbx_lpm_divide 2013:10:23:18:05:48:SJ cbx_mgl 2013:10:23:18:06:54:SJ cbx_stratix 2013:10:23:18:05:48:SJ cbx_stratixii 2013:10:23:18:05:48:SJ cbx_util_mgl 2013:10:23:18:05:48:SJ VERSION_END 3 | 4 | 5 | -- Copyright (C) 1991-2013 Altera Corporation 6 | -- Your use of Altera Corporation's design tools, logic functions 7 | -- and other software and tools, and its AMPP partner logic 8 | -- functions, and any output files from any of the foregoing 9 | -- (including device programming or simulation files), and any 10 | -- associated documentation or information are expressly subject 11 | -- to the terms and conditions of the Altera Program License 12 | -- Subscription Agreement, Altera MegaCore Function License 13 | -- Agreement, or other applicable license agreement, including, 14 | -- without limitation, that your use is for the sole purpose of 15 | -- programming logic devices manufactured by Altera and sold by 16 | -- Altera or its authorized distributors. Please refer to the 17 | -- applicable agreement for further details. 18 | 19 | 20 | FUNCTION sign_div_unsign_klh (denominator[3..0], numerator[9..0]) 21 | RETURNS ( quotient[9..0], remainder[3..0]); 22 | 23 | --synthesis_resources = 24 | SUBDESIGN lpm_divide_vam 25 | ( 26 | denom[3..0] : input; 27 | numer[9..0] : input; 28 | quotient[9..0] : output; 29 | remain[3..0] : output; 30 | ) 31 | VARIABLE 32 | divider : sign_div_unsign_klh; 33 | numer_tmp[9..0] : WIRE; 34 | 35 | BEGIN 36 | divider.denominator[] = denom[]; 37 | divider.numerator[] = numer_tmp[]; 38 | numer_tmp[] = numer[]; 39 | quotient[] = divider.quotient[]; 40 | remain[] = divider.remainder[]; 41 | END; 42 | --VALID FILE 43 | -------------------------------------------------------------------------------- /db/lpm_divide_sim.tdf: -------------------------------------------------------------------------------- 1 | --lpm_divide DEVICE_FAMILY="Cyclone IV E" LPM_DREPRESENTATION="UNSIGNED" LPM_NREPRESENTATION="UNSIGNED" LPM_WIDTHD=4 LPM_WIDTHN=10 OPTIMIZE_FOR_SPEED=5 denom numer quotient CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 IGNORE_CARRY_BUFFERS="OFF" 2 | --VERSION_BEGIN 13.1 cbx_cycloneii 2013:10:23:18:05:48:SJ cbx_lpm_abs 2013:10:23:18:05:48:SJ cbx_lpm_add_sub 2013:10:23:18:05:48:SJ cbx_lpm_divide 2013:10:23:18:05:48:SJ cbx_mgl 2013:10:23:18:06:54:SJ cbx_stratix 2013:10:23:18:05:48:SJ cbx_stratixii 2013:10:23:18:05:48:SJ cbx_util_mgl 2013:10:23:18:05:48:SJ VERSION_END 3 | 4 | 5 | -- Copyright (C) 1991-2013 Altera Corporation 6 | -- Your use of Altera Corporation's design tools, logic functions 7 | -- and other software and tools, and its AMPP partner logic 8 | -- functions, and any output files from any of the foregoing 9 | -- (including device programming or simulation files), and any 10 | -- associated documentation or information are expressly subject 11 | -- to the terms and conditions of the Altera Program License 12 | -- Subscription Agreement, Altera MegaCore Function License 13 | -- Agreement, or other applicable license agreement, including, 14 | -- without limitation, that your use is for the sole purpose of 15 | -- programming logic devices manufactured by Altera and sold by 16 | -- Altera or its authorized distributors. Please refer to the 17 | -- applicable agreement for further details. 18 | 19 | 20 | FUNCTION sign_div_unsign_klh (denominator[3..0], numerator[9..0]) 21 | RETURNS ( quotient[9..0], remainder[3..0]); 22 | 23 | --synthesis_resources = lut 45 24 | SUBDESIGN lpm_divide_sim 25 | ( 26 | denom[3..0] : input; 27 | numer[9..0] : input; 28 | quotient[9..0] : output; 29 | remain[3..0] : output; 30 | ) 31 | VARIABLE 32 | divider : sign_div_unsign_klh; 33 | numer_tmp[9..0] : WIRE; 34 | 35 | BEGIN 36 | divider.denominator[] = denom[]; 37 | divider.numerator[] = numer_tmp[]; 38 | numer_tmp[] = numer[]; 39 | quotient[] = divider.quotient[]; 40 | remain[] = divider.remainder[]; 41 | END; 42 | --VALID FILE 43 | -------------------------------------------------------------------------------- /db/sign_div_unsign_klh.tdf: -------------------------------------------------------------------------------- 1 | --sign_div_unsign DEN_REPRESENTATION="UNSIGNED" DEN_WIDTH=4 LPM_PIPELINE=0 MAXIMIZE_SPEED=5 NUM_REPRESENTATION="UNSIGNED" NUM_WIDTH=10 SKIP_BITS=0 denominator numerator quotient remainder 2 | --VERSION_BEGIN 13.1 cbx_cycloneii 2013:10:23:18:05:48:SJ cbx_lpm_abs 2013:10:23:18:05:48:SJ cbx_lpm_add_sub 2013:10:23:18:05:48:SJ cbx_lpm_divide 2013:10:23:18:05:48:SJ cbx_mgl 2013:10:23:18:06:54:SJ cbx_stratix 2013:10:23:18:05:48:SJ cbx_stratixii 2013:10:23:18:05:48:SJ cbx_util_mgl 2013:10:23:18:05:48:SJ VERSION_END 3 | 4 | 5 | -- Copyright (C) 1991-2013 Altera Corporation 6 | -- Your use of Altera Corporation's design tools, logic functions 7 | -- and other software and tools, and its AMPP partner logic 8 | -- functions, and any output files from any of the foregoing 9 | -- (including device programming or simulation files), and any 10 | -- associated documentation or information are expressly subject 11 | -- to the terms and conditions of the Altera Program License 12 | -- Subscription Agreement, Altera MegaCore Function License 13 | -- Agreement, or other applicable license agreement, including, 14 | -- without limitation, that your use is for the sole purpose of 15 | -- programming logic devices manufactured by Altera and sold by 16 | -- Altera or its authorized distributors. Please refer to the 17 | -- applicable agreement for further details. 18 | 19 | 20 | FUNCTION alt_u_div_s6f (denominator[3..0], numerator[9..0]) 21 | RETURNS ( quotient[9..0], remainder[3..0]); 22 | 23 | --synthesis_resources = lut 45 24 | SUBDESIGN sign_div_unsign_klh 25 | ( 26 | denominator[3..0] : input; 27 | numerator[9..0] : input; 28 | quotient[9..0] : output; 29 | remainder[3..0] : output; 30 | ) 31 | VARIABLE 32 | divider : alt_u_div_s6f; 33 | norm_num[9..0] : WIRE; 34 | protect_quotient[9..0] : WIRE; 35 | protect_remainder[3..0] : WIRE; 36 | 37 | BEGIN 38 | divider.denominator[] = denominator[]; 39 | divider.numerator[] = norm_num[]; 40 | norm_num[] = numerator[]; 41 | protect_quotient[] = divider.quotient[]; 42 | protect_remainder[] = divider.remainder[]; 43 | quotient[] = protect_quotient[]; 44 | remainder[] = protect_remainder[]; 45 | END; 46 | --VALID FILE 47 | -------------------------------------------------------------------------------- /traffic_led.v: -------------------------------------------------------------------------------- 1 | module traffic_led( 2 | input sys_clk , //系统时钟信号 3 | input sys_rst_n , //系统复位信号 4 | input [3:0] key , 5 | 6 | output [7:0] bit , //数码管位选信号 7 | output [7:0] segment , //数码管段选信号 8 | output [23:0] led //LED使能信号 9 | ); 10 | 11 | //wire define 12 | wire [9:0] n_time; //北方向状态剩余时间数据 13 | wire [9:0] e_time; //东方向状态剩余时间数据 14 | wire [9:0] s_time; //南方向状态剩余时间数据 15 | wire [9:0] w_time; //西方向状态剩余时间数据 16 | wire [9:0] nl_time; //北方向状态剩余时间数据 17 | wire [9:0] el_time; //东方向状态剩余时间数据 18 | wire [9:0] sl_time; //南方向状态剩余时间数据 19 | wire [9:0] wl_time; //西方向状态剩余时间数据 20 | wire [3:0] state ; //交通灯的状态，用于控制LED灯的点亮 21 | 22 | state_trans_model u0_state_trans_model( 23 | .sys_clk (sys_clk), 24 | .sys_rst_n (sys_rst_n), 25 | .n_time (n_time), 26 | .e_time (e_time), 27 | .s_time (s_time), 28 | .w_time (w_time), 29 | .nl_time (nl_time), 30 | .el_time (el_time), 31 | .sl_time (sl_time), 32 | .wl_time (wl_time), 33 | .state (state) 34 | ); 35 | 36 | //数码管显示模块 37 | bit_seg_module u1_bit_seg_module( 38 | .sys_clk (sys_clk) , 39 | .sys_rst_n (sys_rst_n), 40 | .n_time (n_time), 41 | .e_time (e_time), 42 | .s_time (s_time), 43 | .w_time (w_time), 44 | .en (1'b1), 45 | .bit (bit), 46 | .segment (segment) 47 | ); 48 | 49 | //led灯控制模块 50 | led_module u2_led_module( 51 | .sys_clk (sys_clk ), 52 | .sys_rst_n (sys_rst_n), 53 | .state (state ), 54 | .led (led ), 55 | .key (key ) 56 | ); 57 | 58 | endmodule -------------------------------------------------------------------------------- /db/traffic_led.eda.qmsg: -------------------------------------------------------------------------------- 1 | { "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1656933500106 ""} 2 | { "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus II 64-Bit " "Running Quartus II 64-Bit EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1656933500107 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Jul 04 19:18:20 2022 " "Processing started: Mon Jul 04 19:18:20 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1656933500107 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1656933500107 ""} 3 | { "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off traffic_led -c traffic_led " "Command: quartus_eda --read_settings_files=off --write_settings_files=off traffic_led -c traffic_led" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1656933500107 ""} 4 | { "Info" "IWSC_DONE_HDL_GENERATION" "traffic_led.vo E:/traffic_led/simulation/qsim// simulation " "Generated file traffic_led.vo in folder \"E:/traffic_led/simulation/qsim//\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1656933500634 ""} 5 | { "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit EDA Netlist Writer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4548 " "Peak virtual memory: 4548 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1656933500678 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Jul 04 19:18:20 2022 " "Processing ended: Mon Jul 04 19:18:20 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1656933500678 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1656933500678 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1656933500678 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1656933500678 ""} 6 | -------------------------------------------------------------------------------- /output_files/traffic_led.sta.summary: -------------------------------------------------------------------------------- 1 | ------------------------------------------------------------ 2 | TimeQuest Timing Analyzer Summary 3 | ------------------------------------------------------------ 4 | 5 | Type : Slow 1200mV 85C Model Setup 'sys_clk' 6 | Slack : -19.512 7 | TNS : -270.008 8 | 9 | Type : Slow 1200mV 85C Model Setup 'state_trans_model:u0_state_trans_model|clk_t' 10 | Slack : -5.323 11 | TNS : -147.771 12 | 13 | Type : Slow 1200mV 85C Model Hold 'sys_clk' 14 | Slack : 0.146 15 | TNS : 0.000 16 | 17 | Type : Slow 1200mV 85C Model Hold 'state_trans_model:u0_state_trans_model|clk_t' 18 | Slack : 0.453 19 | TNS : 0.000 20 | 21 | Type : Slow 1200mV 85C Model Minimum Pulse Width 'sys_clk' 22 | Slack : -3.000 23 | TNS : -135.343 24 | 25 | Type : Slow 1200mV 85C Model Minimum Pulse Width 'state_trans_model:u0_state_trans_model|clk_t' 26 | Slack : -1.487 27 | TNS : -52.045 28 | 29 | Type : Slow 1200mV 0C Model Setup 'sys_clk' 30 | Slack : -17.892 31 | TNS : -245.142 32 | 33 | Type : Slow 1200mV 0C Model Setup 'state_trans_model:u0_state_trans_model|clk_t' 34 | Slack : -4.835 35 | TNS : -134.405 36 | 37 | Type : Slow 1200mV 0C Model Hold 'sys_clk' 38 | Slack : 0.229 39 | TNS : 0.000 40 | 41 | Type : Slow 1200mV 0C Model Hold 'state_trans_model:u0_state_trans_model|clk_t' 42 | Slack : 0.402 43 | TNS : 0.000 44 | 45 | Type : Slow 1200mV 0C Model Minimum Pulse Width 'sys_clk' 46 | Slack : -3.000 47 | TNS : -135.343 48 | 49 | Type : Slow 1200mV 0C Model Minimum Pulse Width 'state_trans_model:u0_state_trans_model|clk_t' 50 | Slack : -1.487 51 | TNS : -52.045 52 | 53 | Type : Fast 1200mV 0C Model Setup 'sys_clk' 54 | Slack : -7.730 55 | TNS : -66.383 56 | 57 | Type : Fast 1200mV 0C Model Setup 'state_trans_model:u0_state_trans_model|clk_t' 58 | Slack : -1.741 59 | TNS : -43.775 60 | 61 | Type : Fast 1200mV 0C Model Hold 'sys_clk' 62 | Slack : -0.072 63 | TNS : -0.072 64 | 65 | Type : Fast 1200mV 0C Model Hold 'state_trans_model:u0_state_trans_model|clk_t' 66 | Slack : 0.187 67 | TNS : 0.000 68 | 69 | Type : Fast 1200mV 0C Model Minimum Pulse Width 'sys_clk' 70 | Slack : -3.000 71 | TNS : -98.223 72 | 73 | Type : Fast 1200mV 0C Model Minimum Pulse Width 'state_trans_model:u0_state_trans_model|clk_t' 74 | Slack : -1.000 75 | TNS : -35.000 76 | 77 | ------------------------------------------------------------ 78 | -------------------------------------------------------------------------------- /db/traffic_led.asm.qmsg: -------------------------------------------------------------------------------- 1 | { "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1656933494628 ""} 2 | { "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 64-Bit " "Running Quartus II 64-Bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1656933494629 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Jul 04 19:18:14 2022 " "Processing started: Mon Jul 04 19:18:14 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1656933494629 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1656933494629 ""} 3 | { "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off traffic_led -c traffic_led " "Command: quartus_asm --read_settings_files=off --write_settings_files=off traffic_led -c traffic_led" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1656933494629 ""} 4 | { "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1656933495117 ""} 5 | { "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1656933495131 ""} 6 | { "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4582 " "Peak virtual memory: 4582 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1656933495308 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Jul 04 19:18:15 2022 " "Processing ended: Mon Jul 04 19:18:15 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1656933495308 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1656933495308 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1656933495308 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1656933495308 ""} 7 | -------------------------------------------------------------------------------- /test.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns/1ns // 时延单位为1ms，时延精度为1ns 2 | 3 | module test; 4 | 5 | 6 | //wire define 7 | wire [9:0] n_time; //北方向状态剩余时间数据 8 | wire [9:0] e_time; //东方向状态剩余时间数据 9 | wire [9:0] s_time; //南方向状态剩余时间数据 10 | wire [9:0] w_time; //西方向状态剩余时间数据 11 | wire [9:0] nl_time; //北方向状态剩余时间数据 12 | wire [9:0] el_time; //东方向状态剩余时间数据 13 | wire [9:0] sl_time; //南方向状态剩余时间数据 14 | wire [9:0] wl_time; //西方向状态剩余时间数据 15 | wire [3:0] state ; //交通灯的状态，用于控制LED灯的点亮 16 | 17 | 18 | 19 | // 初始化信号 20 | wire [7:0] bit; 21 | wire [7:0] segment; 22 | wire [23:0] led; 23 | reg sys_clk; 24 | reg sys_rst_n; 25 | reg [3:0] key; 26 | 27 | initial begin 28 | sys_clk=1'b0; 29 | sys_rst_n=1'b0; 30 | #20 sys_rst_n=1'b1; 31 | key=4'b1111; 32 | 33 | #120000 sys_rst_n=1'b1; 34 | 35 | 36 | #80000 key=4'b0000; 37 | #80000 key=4'b1110; 38 | #80000 key=4'b1101; 39 | #80000 key=4'b1011; 40 | 41 | #80000 sys_rst_n=1'b0; 42 | end 43 | 44 | always #10 sys_clk = ~sys_clk; // 系统时钟周期为20ns 45 | 46 | 47 | 48 | state_trans_model #(.WIDTH(25))u0_state_trans_model( 49 | .sys_clk (sys_clk), 50 | .sys_rst_n (sys_rst_n), 51 | .n_time (n_time), 52 | .e_time (e_time), 53 | .s_time (s_time), 54 | .w_time (w_time), 55 | .nl_time (nl_time), 56 | .el_time (el_time), 57 | .sl_time (sl_time), 58 | .wl_time (wl_time), 59 | .state (state) 60 | ); 61 | 62 | //数码管显示模块 63 | bit_seg_module u1_bit_seg_module( 64 | .sys_clk (sys_clk) , 65 | .sys_rst_n (sys_rst_n), 66 | .n_time (n_time), 67 | .e_time (e_time), 68 | .s_time (s_time), 69 | .w_time (w_time), 70 | .en (1'b1), 71 | .bit (bit), 72 | .segment (segment) 73 | ); 74 | 75 | //led灯控制模块 76 | led_module u2_led_module( 77 | .sys_clk (sys_clk ), 78 | .sys_rst_n (sys_rst_n), 79 | .state (state ), 80 | .led (led ), 81 | .key (key ) 82 | ); 83 | 84 | endmodule -------------------------------------------------------------------------------- /db/traffic_led.analyze_file.qmsg: -------------------------------------------------------------------------------- 1 | { "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1656824610945 ""} 2 | { "Info" "IQEXE_START_BANNER_PRODUCT" "Analyze Current File Quartus II 64-Bit " "Running Quartus II 64-Bit Analyze Current File" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1656824610945 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Jul 03 13:03:30 2022 " "Processing started: Sun Jul 03 13:03:30 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1656824610945 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1656824610945 ""} 3 | { "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off traffic_led -c traffic_led --analyze_file=E:/trafficled/db/traffic_led.cmp.rdb " "Command: quartus_map --read_settings_files=on --write_settings_files=off traffic_led -c traffic_led --analyze_file=E:/trafficled/db/traffic_led.cmp.rdb" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1656824610945 ""} 4 | { "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1656824611197 ""} 5 | { "Error" "ESGN_NON_DESIGN_FILE" "E:/trafficled/db/traffic_led.cmp.rdb " "File E:/trafficled/db/traffic_led.cmp.rdb is not a recognized design file type" { } { } 0 12074 "File %1!s! is not a recognized design file type" 0 0 "Quartus II" 0 -1 1656824611231 ""} 6 | { "Error" "EQEXE_ERROR_COUNT" "Analyze Current File 1 1 Quartus II 64-Bit " "Quartus II 64-Bit Analyze Current File was unsuccessful. 1 error, 1 warning" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "4601 " "Peak virtual memory: 4601 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1656824611231 ""} { "Error" "EQEXE_END_BANNER_TIME" "Sun Jul 03 13:03:31 2022 " "Processing ended: Sun Jul 03 13:03:31 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1656824611231 ""} { "Error" "EQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1656824611231 ""} { "Error" "EQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1656824611231 ""} } { } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1656824611231 ""} 7 | -------------------------------------------------------------------------------- /traffic_led.bsf: -------------------------------------------------------------------------------- 1 | /* 2 | WARNING: Do NOT edit the input and output ports in this file in a text 3 | editor if you plan to continue editing the block that represents it in 4 | the Block Editor! File corruption is VERY likely to occur. 5 | */ 6 | /* 7 | Copyright (C) 1991-2013 Altera Corporation 8 | Your use of Altera Corporation's design tools, logic functions 9 | and other software and tools, and its AMPP partner logic 10 | functions, and any output files from any of the foregoing 11 | (including device programming or simulation files), and any 12 | associated documentation or information are expressly subject 13 | to the terms and conditions of the Altera Program License 14 | Subscription Agreement, Altera MegaCore Function License 15 | Agreement, or other applicable license agreement, including, 16 | without limitation, that your use is for the sole purpose of 17 | programming logic devices manufactured by Altera and sold by 18 | Altera or its authorized distributors. Please refer to the 19 | applicable agreement for further details. 20 | */ 21 | (header "symbol" (version "1.1")) 22 | (symbol 23 | (rect 16 16 216 128) 24 | (text "traffic_led" (rect 5 0 45 12)(font "Arial" )) 25 | (text "inst" (rect 8 96 20 108)(font "Arial" )) 26 | (port 27 | (pt 0 32) 28 | (input) 29 | (text "sys_clk" (rect 0 0 31 12)(font "Arial" )) 30 | (text "sys_clk" (rect 21 27 52 39)(font "Arial" )) 31 | (line (pt 0 32)(pt 16 32)(line_width 1)) 32 | ) 33 | (port 34 | (pt 0 48) 35 | (input) 36 | (text "sys_rst_n" (rect 0 0 42 12)(font "Arial" )) 37 | (text "sys_rst_n" (rect 21 43 63 55)(font "Arial" )) 38 | (line (pt 0 48)(pt 16 48)(line_width 1)) 39 | ) 40 | (port 41 | (pt 0 64) 42 | (input) 43 | (text "key[3..0]" (rect 0 0 35 12)(font "Arial" )) 44 | (text "key[3..0]" (rect 21 59 56 71)(font "Arial" )) 45 | (line (pt 0 64)(pt 16 64)(line_width 3)) 46 | ) 47 | (port 48 | (pt 200 32) 49 | (output) 50 | (text "bit[7..0]" (rect 0 0 28 12)(font "Arial" )) 51 | (text "bit[7..0]" (rect 151 27 179 39)(font "Arial" )) 52 | (line (pt 200 32)(pt 184 32)(line_width 3)) 53 | ) 54 | (port 55 | (pt 200 48) 56 | (output) 57 | (text "segment[7..0]" (rect 0 0 54 12)(font "Arial" )) 58 | (text "segment[7..0]" (rect 125 43 179 55)(font "Arial" )) 59 | (line (pt 200 48)(pt 184 48)(line_width 3)) 60 | ) 61 | (port 62 | (pt 200 64) 63 | (output) 64 | (text "led[23..0]" (rect 0 0 35 12)(font "Arial" )) 65 | (text "led[23..0]" (rect 144 59 179 71)(font "Arial" )) 66 | (line (pt 200 64)(pt 184 64)(line_width 3)) 67 | ) 68 | (drawing 69 | (rectangle (rect 16 16 184 96)(line_width 1)) 70 | ) 71 | ) 72 | -------------------------------------------------------------------------------- /led_module.v: -------------------------------------------------------------------------------- 1 | module led_module ( 2 | input sys_clk , //系统时钟 3 | input sys_rst_n , //系统复位 4 | input [3:0] state , //交通灯的状态 5 | input [3:0] key , 6 | output reg [23:0] led //红黄绿LED灯发光使能 7 | ); 8 | 9 | //parameter define 10 | parameter Yellow_Count = 20000; //让黄灯闪烁的计数次数 11 | 12 | //reg define 13 | reg [24:0] count; //让黄灯产生闪烁效果的计数器 14 | 15 | //计数时间为0.4ms的计数器，用于让黄灯闪烁(非固定依据Yellow_Count参数调整) 16 | always @(posedge sys_clk or negedge sys_rst_n)begin 17 | if(!sys_rst_n) 18 | count <= 25'b0; 19 | else if (count < Yellow_Count - 1'b1) 20 | count <= count + 1'b1; 21 | else 22 | count <= 25'b0; 23 | end 24 | 25 | //在交通灯的四个状态里，使相应的led灯发光 26 | always @(posedge sys_clk or negedge sys_rst_n)begin 27 | if(!sys_rst_n) 28 | led <= 24'b100_100_100_100_100_100_100_100; 29 | else if(key[0] == 1'b0) 30 | led <= 24'b010_100_010_100_100_100_100_100; 31 | else if(key[1] == 1'b0) 32 | led <= 24'b100_010_100_010_100_100_100_100; 33 | else if(key[2] == 1'b0) 34 | led <= 24'b001_001_001_001_001_001_001_001; 35 | else begin 36 | case(state) 37 | 4'b0000: led <= 24'b010_100_010_100_100_100_100_100; //led寄存器从高到低分别驱动：北东南西向红绿黄灯以及左转灯 38 | 39 | 4'b0001: led <= 24'b001_100_001_100_100_100_100_100; 40 | 41 | 4'b0010: led <= 24'b100_100_100_100_010_100_010_100; 42 | 43 | 4'b0011: led <= 24'b100_100_100_100_001_100_001_100; 44 | 45 | 4'b0100: led <= 24'b100_010_100_010_100_100_100_100; 46 | 47 | 4'b0101: led <= 24'b100_001_100_001_100_100_100_100; 48 | 49 | 4'b0110: led <= 24'b100_100_100_100_100_010_100_010; 50 | 51 | 4'b0111: led <= 24'b100_100_100_100_100_001_100_001; 52 | 53 | default: led <= 24'b010_100_010_100_100_100_100_100; 54 | endcase 55 | end 56 | end 57 | 58 | endmodule -------------------------------------------------------------------------------- /state_trans_model.bsf: -------------------------------------------------------------------------------- 1 | /* 2 | WARNING: Do NOT edit the input and output ports in this file in a text 3 | editor if you plan to continue editing the block that represents it in 4 | the Block Editor! File corruption is VERY likely to occur. 5 | */ 6 | /* 7 | Copyright (C) 1991-2013 Altera Corporation 8 | Your use of Altera Corporation's design tools, logic functions 9 | and other software and tools, and its AMPP partner logic 10 | functions, and any output files from any of the foregoing 11 | (including device programming or simulation files), and any 12 | associated documentation or information are expressly subject 13 | to the terms and conditions of the Altera Program License 14 | Subscription Agreement, Altera MegaCore Function License 15 | Agreement, or other applicable license agreement, including, 16 | without limitation, that your use is for the sole purpose of 17 | programming logic devices manufactured by Altera and sold by 18 | Altera or its authorized distributors. Please refer to the 19 | applicable agreement for further details. 20 | */ 21 | (header "symbol" (version "1.1")) 22 | (symbol 23 | (rect 16 16 208 224) 24 | (text "state_trans_model" (rect 5 0 79 12)(font "Arial" )) 25 | (text "inst" (rect 8 192 20 204)(font "Arial" )) 26 | (port 27 | (pt 0 32) 28 | (input) 29 | (text "sys_clk" (rect 0 0 31 12)(font "Arial" )) 30 | (text "sys_clk" (rect 21 27 52 39)(font "Arial" )) 31 | (line (pt 0 32)(pt 16 32)(line_width 1)) 32 | ) 33 | (port 34 | (pt 0 48) 35 | (input) 36 | (text "sys_rst_n" (rect 0 0 42 12)(font "Arial" )) 37 | (text "sys_rst_n" (rect 21 43 63 55)(font "Arial" )) 38 | (line (pt 0 48)(pt 16 48)(line_width 1)) 39 | ) 40 | (port 41 | (pt 192 32) 42 | (output) 43 | (text "state[3..0]" (rect 0 0 38 12)(font "Arial" )) 44 | (text "state[3..0]" (rect 133 27 171 39)(font "Arial" )) 45 | (line (pt 192 32)(pt 176 32)(line_width 3)) 46 | ) 47 | (port 48 | (pt 192 48) 49 | (output) 50 | (text "n_time[9..0]" (rect 0 0 47 12)(font "Arial" )) 51 | (text "n_time[9..0]" (rect 124 43 171 55)(font "Arial" )) 52 | (line (pt 192 48)(pt 176 48)(line_width 3)) 53 | ) 54 | (port 55 | (pt 192 64) 56 | (output) 57 | (text "e_time[9..0]" (rect 0 0 47 12)(font "Arial" )) 58 | (text "e_time[9..0]" (rect 124 59 171 71)(font "Arial" )) 59 | (line (pt 192 64)(pt 176 64)(line_width 3)) 60 | ) 61 | (port 62 | (pt 192 80) 63 | (output) 64 | (text "s_time[9..0]" (rect 0 0 47 12)(font "Arial" )) 65 | (text "s_time[9..0]" (rect 124 75 171 87)(font "Arial" )) 66 | (line (pt 192 80)(pt 176 80)(line_width 3)) 67 | ) 68 | (port 69 | (pt 192 96) 70 | (output) 71 | (text "w_time[9..0]" (rect 0 0 48 12)(font "Arial" )) 72 | (text "w_time[9..0]" (rect 123 91 171 103)(font "Arial" )) 73 | (line (pt 192 96)(pt 176 96)(line_width 3)) 74 | ) 75 | (port 76 | (pt 192 112) 77 | (output) 78 | (text "nl_time[9..0]" (rect 0 0 48 12)(font "Arial" )) 79 | (text "nl_time[9..0]" (rect 123 107 171 119)(font "Arial" )) 80 | (line (pt 192 112)(pt 176 112)(line_width 3)) 81 | ) 82 | (port 83 | (pt 192 128) 84 | (output) 85 | (text "el_time[9..0]" (rect 0 0 48 12)(font "Arial" )) 86 | (text "el_time[9..0]" (rect 123 123 171 135)(font "Arial" )) 87 | (line (pt 192 128)(pt 176 128)(line_width 3)) 88 | ) 89 | (port 90 | (pt 192 144) 91 | (output) 92 | (text "sl_time[9..0]" (rect 0 0 48 12)(font "Arial" )) 93 | (text "sl_time[9..0]" (rect 123 139 171 151)(font "Arial" )) 94 | (line (pt 192 144)(pt 176 144)(line_width 3)) 95 | ) 96 | (port 97 | (pt 192 160) 98 | (output) 99 | (text "wl_time[9..0]" (rect 0 0 49 12)(font "Arial" )) 100 | (text "wl_time[9..0]" (rect 122 155 171 167)(font "Arial" )) 101 | (line (pt 192 160)(pt 176 160)(line_width 3)) 102 | ) 103 | (parameter 104 | "TIME_LED_NSY" 105 | "3" 106 | "" 107 | (type "PARAMETER_SIGNED_DEC") ) 108 | (parameter 109 | "TIME_LED_NSR" 110 | "60" 111 | "" 112 | (type "PARAMETER_SIGNED_DEC") ) 113 | (parameter 114 | "TIME_LED_NSG" 115 | "27" 116 | "" 117 | (type "PARAMETER_SIGNED_DEC") ) 118 | (parameter 119 | "TIME_LED_WEY" 120 | "3" 121 | "" 122 | (type "PARAMETER_SIGNED_DEC") ) 123 | (parameter 124 | "TIME_LED_WER" 125 | "60" 126 | "" 127 | (type "PARAMETER_SIGNED_DEC") ) 128 | (parameter 129 | "TIME_LED_WEG" 130 | "27" 131 | "" 132 | (type "PARAMETER_SIGNED_DEC") ) 133 | (parameter 134 | "WIDTH" 135 | "25000000" 136 | "" 137 | (type "PARAMETER_SIGNED_DEC") ) 138 | (drawing 139 | (rectangle (rect 16 16 176 192)(line_width 1)) 140 | ) 141 | (annotation_block (parameter)(rect 208 -64 308 16)) 142 | ) 143 | -------------------------------------------------------------------------------- /traffic_led.qsf: -------------------------------------------------------------------------------- 1 | # -------------------------------------------------------------------------- # 2 | # 3 | # Copyright (C) 1991-2015 Altera Corporation. All rights reserved. 4 | # Your use of Altera Corporation's design tools, logic functions 5 | # and other software and tools, and its AMPP partner logic 6 | # functions, and any output files from any of the foregoing 7 | # (including device programming or simulation files), and any 8 | # associated documentation or information are expressly subject 9 | # to the terms and conditions of the Altera Program License 10 | # Subscription Agreement, the Altera Quartus II License Agreement, 11 | # the Altera MegaCore Function License Agreement, or other 12 | # applicable license agreement, including, without limitation, 13 | # that your use is for the sole purpose of programming logic 14 | # devices manufactured by Altera and sold by Altera or its 15 | # authorized distributors. Please refer to the applicable 16 | # agreement for further details. 17 | # 18 | # -------------------------------------------------------------------------- # 19 | # 20 | # Quartus II 64-Bit 21 | # Version 15.0.0 Build 145 04/22/2015 SJ Full Version 22 | # Date created = 22:59:01 June 19, 2020 23 | # 24 | # -------------------------------------------------------------------------- # 25 | # 26 | # Notes: 27 | # 28 | # 1) The default values for assignments are stored in the file: 29 | # traffic_led_assignment_defaults.qdf 30 | # If this file doesn't exist, see file: 31 | # assignment_defaults.qdf 32 | # 33 | # 2) Altera recommends that you do not modify this file. This 34 | # file is updated automatically by the Quartus II software 35 | # and any changes you make may be lost or overwritten. 36 | # 37 | # -------------------------------------------------------------------------- # 38 | 39 | 40 | set_global_assignment -name FAMILY "Cyclone IV E" 41 | set_global_assignment -name DEVICE EP4CE6F17C8 42 | set_global_assignment -name TOP_LEVEL_ENTITY traffic_led 43 | set_global_assignment -name ORIGINAL_QUARTUS_VERSION 15.0.0 44 | set_global_assignment -name PROJECT_CREATION_TIME_DATE "22:59:01 JUNE 19, 2020" 45 | set_global_assignment -name LAST_QUARTUS_VERSION 13.1 46 | set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files 47 | set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 48 | set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 49 | set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 50 | set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)" 51 | set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation 52 | set_global_assignment -name EDA_NETLIST_WRITER_OUTPUT_DIR "E:/traffic_led/simulation/qsim/" -section_id eda_simulation 53 | set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST ON -section_id eda_simulation 54 | set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation 55 | set_global_assignment -name VERILOG_FILE test.v 56 | set_global_assignment -name VECTOR_WAVEFORM_FILE Waveform.vwf 57 | set_global_assignment -name VECTOR_WAVEFORM_FILE Waveform1.vwf 58 | set_global_assignment -name VERILOG_FILE led_module.v 59 | set_global_assignment -name VERILOG_FILE traffic_led.v 60 | set_global_assignment -name VECTOR_WAVEFORM_FILE Waveform2.vwf 61 | set_global_assignment -name VECTOR_WAVEFORM_FILE Waveform3.vwf 62 | set_global_assignment -name VECTOR_WAVEFORM_FILE Waveform4.vwf 63 | set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top 64 | set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top 65 | set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top 66 | set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS TEST_BENCH_MODE -section_id eda_simulation 67 | set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH test -section_id eda_simulation 68 | set_global_assignment -name EDA_TEST_BENCH_NAME test -section_id eda_simulation 69 | set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id test 70 | set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME test -section_id test 71 | set_global_assignment -name EDA_TEST_BENCH_FILE test.v -section_id test 72 | set_location_assignment PIN_E16 -to key[1] 73 | set_location_assignment PIN_M16 -to key[2] 74 | set_location_assignment PIN_M15 -to key[3] 75 | set_location_assignment PIN_R16 -to segment[7] 76 | set_location_assignment PIN_N15 -to segment[6] 77 | set_location_assignment PIN_N12 -to segment[5] 78 | set_location_assignment PIN_P15 -to segment[4] 79 | set_location_assignment PIN_T15 -to segment[3] 80 | set_location_assignment PIN_P16 -to segment[2] 81 | set_location_assignment PIN_N16 -to segment[1] 82 | set_location_assignment PIN_R14 -to segment[0] 83 | set_location_assignment PIN_M11 -to bit[5] 84 | set_location_assignment PIN_P11 -to bit[4] 85 | set_location_assignment PIN_N11 -to bit[3] 86 | set_location_assignment PIN_M10 -to bit[2] 87 | set_location_assignment PIN_P9 -to bit[1] 88 | set_location_assignment PIN_N9 -to bit[0] 89 | set_location_assignment PIN_E1 -to sys_clk 90 | set_location_assignment PIN_N13 -to sys_rst_n 91 | set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V" 92 | set_global_assignment -name DEVICE_FILTER_PIN_COUNT 256 93 | set_global_assignment -name VECTOR_WAVEFORM_FILE output_files/Waveform.vwf 94 | set_location_assignment PIN_E10 -to led[23] 95 | set_location_assignment PIN_F9 -to led[22] 96 | set_location_assignment PIN_C9 -to led[21] 97 | set_global_assignment -name BDF_FILE traffic_led_new.bdf 98 | set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top -------------------------------------------------------------------------------- /bit_seg_module.v: -------------------------------------------------------------------------------- 1 | module bit_seg_module( 2 | input sys_clk , //系统时钟 3 | input sys_rst_n , //系统复位 4 | input [9:0] n_time , //北方向数码管要显示的数值 5 | input [9:0] e_time , //东方向数码管要显示的数值 6 | input [9:0] s_time , //南方向数码管要显示的数值 7 | input [9:0] w_time , //西方向数码管要显示的数值 8 | input en , //数码管使能信号 9 | output reg [7:0] bit , //数码管位选信号 10 | output reg [7:0] segment //数码管段选信号,包含小数点 11 | ); 12 | //parameter define 13 | parameter state_count = 25000; //计数0.0001ms的计数深度 14 | 15 | //reg define 16 | reg [15:0] count_s; //计数1ms的计数器(仿真可调整) 17 | reg [2:0] count_state; //用于切换要点亮数码管 18 | reg [3:0] num; //数码管要显示的数据 19 | 20 | //wire define 21 | wire [3:0] data_n_0; //北方向数码管的十位 22 | wire [3:0] data_n_1; //北方向数码管的个位 23 | wire [3:0] data_e_0; //东方向数码管的十位 24 | wire [3:0] data_e_1; //东方向数码管的个位 25 | wire [3:0] data_s_0; //南方向数码管的十位 26 | wire [3:0] data_s_1; //南方向数码管的个位 27 | wire [3:0] data_w_0; //西方向数码管的十位 28 | wire [3:0] data_w_1; //西方向数码管的个位 29 | 30 | //主程序 31 | assign data_n_0 = n_time / 10; //取出北向时间数据的十位 32 | assign data_n_1 = n_time % 10; //取出北向时间数据的个位 33 | assign data_e_0 = e_time / 10; //取出东向时间数据的十位 34 | assign data_e_1 = e_time % 10; //取出东向时间数据的个位 35 | assign data_s_0 = s_time / 10; //取出南向时间数据的十位 36 | assign data_s_1 = s_time % 10; //取出南向时间数据的个位 37 | assign data_w_0 = w_time / 10; //取出西向时间数据的十位 38 | assign data_w_1 = w_time % 10; //取出西向时间数据的个位 39 | 40 | //计数0.1ms(非固定依据state_count参数调整) 41 | always @ (posedge sys_clk or negedge sys_rst_n) begin 42 | if (!sys_rst_n) 43 | count_s <= 16'b0; 44 | else if (count_s < state_count - 1'b1) 45 | count_s <= count_s + 1'b1; 46 | else 47 | count_s <= 16'b0; 48 | end 49 | 50 | //计数器，用来切换数码管点亮的8个状态 0.2ms周期(非固定依据state_count参数调整) 51 | always @ (posedge sys_clk or negedge sys_rst_n) begin 52 | if (!sys_rst_n) 53 | count_state <= 2'd0; 54 | else if (count_s == state_count - 1'b1) 55 | count_state <= count_state + 1'b1; 56 | else 57 | count_state <= count_state; 58 | end 59 | 60 | //先显示北方向数码管的十位，然后是个位。再依次显示东南西方向数码管的十位、个位 61 | always @ (posedge sys_clk or negedge sys_rst_n) begin 62 | if(!sys_rst_n) begin 63 | bit <= 8'b11111111; 64 | num <= 4'b0; 65 | end 66 | else if(en) begin 67 | case (count_state) 68 | 3'd0 : begin 69 | bit <= 8'b11111110; //驱动北方向数码管的十位 70 | num <= data_n_0; 71 | end 72 | 3'd1 : begin 73 | bit <= 8'b11111101; //驱动北方向数码管的个位 74 | num <= data_n_1; 75 | end 76 | 3'd2 : begin 77 | bit <= 8'b11111011; //驱动东方向数码管的十位 78 | num <= data_e_0; 79 | end 80 | 3'd3 : begin 81 | bit <= 8'b11110111; //驱动东方向数码管的个位 82 | num <= data_e_1 ; 83 | end 84 | 3'd4 : begin 85 | bit <= 8'b11101111; //驱动南方向数码管的十位 86 | num <= data_s_0; 87 | end 88 | 3'd5 : begin 89 | bit <= 8'b11011111; //驱动南方向数码管的个位 90 | num <= data_s_1; 91 | end 92 | 3'd6 : begin 93 | bit <= 8'b10111111; //驱动西方向数码管的十位 94 | num <= data_w_0; 95 | end 96 | 3'd7 : begin 97 | bit <= 8'b01111111; //驱动西方向数码管的个位 98 | num <= data_w_1 ; 99 | end 100 | default : begin 101 | bit <= 8'b11111111; 102 | num <= 4'b0; 103 | end 104 | endcase 105 | end 106 | else begin 107 | bit <= 8'b11111111; 108 | num <= 4'b0; 109 | end 110 | end 111 | 112 | //数码管要显示的数值所对应的段选信号 113 | always @ (posedge sys_clk or negedge sys_rst_n) begin 114 | if (!sys_rst_n) 115 | segment <= 8'b0; 116 | else begin 117 | case (num) 118 | 4'd0 : segment <= 8'b11000000; 119 | 4'd1 : segment <= 8'b11111001; 120 | 4'd2 : segment <= 8'b10100100; 121 | 4'd3 : segment <= 8'b10110000; 122 | 4'd4 : segment <= 8'b10011001; 123 | 4'd5 : segment <= 8'b10010010; 124 | 4'd6 : segment <= 8'b10000010; 125 | 4'd7 : segment <= 8'b11111000; 126 | 4'd8 : segment <= 8'b10000000; 127 | 4'd9 : segment <= 8'b10010000; 128 | default : segment <= 8'b11000000; 129 | endcase 130 | end 131 | end 132 | 133 | endmodule -------------------------------------------------------------------------------- /output_files/traffic_led.eda.rpt: -------------------------------------------------------------------------------- 1 | EDA Netlist Writer report for traffic_led 2 | Mon Jul 04 19:18:20 2022 3 | Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition 4 | 5 | 6 | --------------------- 7 | ; Table of Contents ; 8 | --------------------- 9 | 1. Legal Notice 10 | 2. EDA Netlist Writer Summary 11 | 3. Simulation Settings 12 | 4. Simulation Generated Files 13 | 5. EDA Netlist Writer Messages 14 | 15 | 16 | 17 | ---------------- 18 | ; Legal Notice ; 19 | ---------------- 20 | Copyright (C) 1991-2013 Altera Corporation 21 | Your use of Altera Corporation's design tools, logic functions 22 | and other software and tools, and its AMPP partner logic 23 | functions, and any output files from any of the foregoing 24 | (including device programming or simulation files), and any 25 | associated documentation or information are expressly subject 26 | to the terms and conditions of the Altera Program License 27 | Subscription Agreement, Altera MegaCore Function License 28 | Agreement, or other applicable license agreement, including, 29 | without limitation, that your use is for the sole purpose of 30 | programming logic devices manufactured by Altera and sold by 31 | Altera or its authorized distributors. Please refer to the 32 | applicable agreement for further details. 33 | 34 | 35 | 36 | +-------------------------------------------------------------------+ 37 | ; EDA Netlist Writer Summary ; 38 | +---------------------------+---------------------------------------+ 39 | ; EDA Netlist Writer Status ; Successful - Mon Jul 04 19:18:20 2022 ; 40 | ; Revision Name ; traffic_led ; 41 | ; Top-level Entity Name ; traffic_led ; 42 | ; Family ; Cyclone IV E ; 43 | ; Simulation Files Creation ; Successful ; 44 | +---------------------------+---------------------------------------+ 45 | 46 | 47 | +-------------------------------------------------------------------------------------------------------------------------------+ 48 | ; Simulation Settings ; 49 | +---------------------------------------------------------------------------------------------------+---------------------------+ 50 | ; Option ; Setting ; 51 | +---------------------------------------------------------------------------------------------------+---------------------------+ 52 | ; Tool Name ; ModelSim-Altera (Verilog) ; 53 | ; Generate netlist for functional simulation only ; On ; 54 | ; Truncate long hierarchy paths ; Off ; 55 | ; Map illegal HDL characters ; Off ; 56 | ; Flatten buses into individual nodes ; Off ; 57 | ; Maintain hierarchy ; Off ; 58 | ; Bring out device-wide set/reset signals as ports ; Off ; 59 | ; Enable glitch filtering ; Off ; 60 | ; Do not write top level VHDL entity ; Off ; 61 | ; Disable detection of setup and hold time violations in the input registers of bi-directional pins ; Off ; 62 | ; Architecture name in VHDL output netlist ; structure ; 63 | ; Generate third-party EDA tool command script for RTL functional simulation ; Off ; 64 | ; Generate third-party EDA tool command script for gate-level simulation ; Off ; 65 | +---------------------------------------------------------------------------------------------------+---------------------------+ 66 | 67 | 68 | +------------------------------------------------+ 69 | ; Simulation Generated Files ; 70 | +------------------------------------------------+ 71 | ; Generated Files ; 72 | +------------------------------------------------+ 73 | ; E:/traffic_led/simulation/qsim//traffic_led.vo ; 74 | +------------------------------------------------+ 75 | 76 | 77 | +-----------------------------+ 78 | ; EDA Netlist Writer Messages ; 79 | +-----------------------------+ 80 | Info: ******************************************************************* 81 | Info: Running Quartus II 64-Bit EDA Netlist Writer 82 | Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition 83 | Info: Processing started: Mon Jul 04 19:18:20 2022 84 | Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off traffic_led -c traffic_led 85 | Info (204019): Generated file traffic_led.vo in folder "E:/traffic_led/simulation/qsim//" for EDA simulation tool 86 | Info: Quartus II 64-Bit EDA Netlist Writer was successful. 0 errors, 0 warnings 87 | Info: Peak virtual memory: 4548 megabytes 88 | Info: Processing ended: Mon Jul 04 19:18:20 2022 89 | Info: Elapsed time: 00:00:00 90 | Info: Total CPU time (on all processors): 00:00:01 91 | 92 | 93 | -------------------------------------------------------------------------------- /output_files/traffic_led.asm.rpt: -------------------------------------------------------------------------------- 1 | Assembler report for traffic_led 2 | Mon Jul 04 19:18:15 2022 3 | Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition 4 | 5 | 6 | --------------------- 7 | ; Table of Contents ; 8 | --------------------- 9 | 1. Legal Notice 10 | 2. Assembler Summary 11 | 3. Assembler Settings 12 | 4. Assembler Generated Files 13 | 5. Assembler Device Options: E:/trafficled/output_files/traffic_led.sof 14 | 6. Assembler Messages 15 | 16 | 17 | 18 | ---------------- 19 | ; Legal Notice ; 20 | ---------------- 21 | Copyright (C) 1991-2013 Altera Corporation 22 | Your use of Altera Corporation's design tools, logic functions 23 | and other software and tools, and its AMPP partner logic 24 | functions, and any output files from any of the foregoing 25 | (including device programming or simulation files), and any 26 | associated documentation or information are expressly subject 27 | to the terms and conditions of the Altera Program License 28 | Subscription Agreement, Altera MegaCore Function License 29 | Agreement, or other applicable license agreement, including, 30 | without limitation, that your use is for the sole purpose of 31 | programming logic devices manufactured by Altera and sold by 32 | Altera or its authorized distributors. Please refer to the 33 | applicable agreement for further details. 34 | 35 | 36 | 37 | +---------------------------------------------------------------+ 38 | ; Assembler Summary ; 39 | +-----------------------+---------------------------------------+ 40 | ; Assembler Status ; Successful - Mon Jul 04 19:18:15 2022 ; 41 | ; Revision Name ; traffic_led ; 42 | ; Top-level Entity Name ; traffic_led ; 43 | ; Family ; Cyclone IV E ; 44 | ; Device ; EP4CE6F17C8 ; 45 | +-----------------------+---------------------------------------+ 46 | 47 | 48 | +--------------------------------------------------------------------------------------------------------+ 49 | ; Assembler Settings ; 50 | +-----------------------------------------------------------------------------+----------+---------------+ 51 | ; Option ; Setting ; Default Value ; 52 | +-----------------------------------------------------------------------------+----------+---------------+ 53 | ; Use smart compilation ; Off ; Off ; 54 | ; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ; 55 | ; Enable compact report table ; Off ; Off ; 56 | ; Generate compressed bitstreams ; On ; On ; 57 | ; Compression mode ; Off ; Off ; 58 | ; Clock source for configuration device ; Internal ; Internal ; 59 | ; Clock frequency of the configuration device ; 10 MHZ ; 10 MHz ; 60 | ; Divide clock frequency by ; 1 ; 1 ; 61 | ; Auto user code ; On ; On ; 62 | ; Use configuration device ; Off ; Off ; 63 | ; Configuration device ; Auto ; Auto ; 64 | ; Configuration device auto user code ; Off ; Off ; 65 | ; Generate Tabular Text File (.ttf) For Target Device ; Off ; Off ; 66 | ; Generate Raw Binary File (.rbf) For Target Device ; Off ; Off ; 67 | ; Generate Hexadecimal (Intel-Format) Output File (.hexout) for Target Device ; Off ; Off ; 68 | ; Hexadecimal Output File start address ; 0 ; 0 ; 69 | ; Hexadecimal Output File count direction ; Up ; Up ; 70 | ; Release clears before tri-states ; Off ; Off ; 71 | ; Auto-restart configuration after error ; On ; On ; 72 | ; Enable OCT_DONE ; Off ; Off ; 73 | ; Generate Serial Vector Format File (.svf) for Target Device ; Off ; Off ; 74 | ; Generate a JEDEC STAPL Format File (.jam) for Target Device ; Off ; Off ; 75 | ; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; Off ; Off ; 76 | ; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; On ; On ; 77 | +-----------------------------------------------------------------------------+----------+---------------+ 78 | 79 | 80 | +--------------------------------------------+ 81 | ; Assembler Generated Files ; 82 | +--------------------------------------------+ 83 | ; File Name ; 84 | +--------------------------------------------+ 85 | ; E:/trafficled/output_files/traffic_led.sof ; 86 | +--------------------------------------------+ 87 | 88 | 89 | +----------------------------------------------------------------------+ 90 | ; Assembler Device Options: E:/trafficled/output_files/traffic_led.sof ; 91 | +----------------+-----------------------------------------------------+ 92 | ; Option ; Setting ; 93 | +----------------+-----------------------------------------------------+ 94 | ; Device ; EP4CE6F17C8 ; 95 | ; JTAG usercode ; 0x000E7ACF ; 96 | ; Checksum ; 0x000E7ACF ; 97 | +----------------+-----------------------------------------------------+ 98 | 99 | 100 | +--------------------+ 101 | ; Assembler Messages ; 102 | +--------------------+ 103 | Info: ******************************************************************* 104 | Info: Running Quartus II 64-Bit Assembler 105 | Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition 106 | Info: Processing started: Mon Jul 04 19:18:14 2022 107 | Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off traffic_led -c traffic_led 108 | Info (115031): Writing out detailed assembly data for power analysis 109 | Info (115030): Assembler is generating device programming files 110 | Info: Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings 111 | Info: Peak virtual memory: 4582 megabytes 112 | Info: Processing ended: Mon Jul 04 19:18:15 2022 113 | Info: Elapsed time: 00:00:01 114 | Info: Total CPU time (on all processors): 00:00:01 115 | 116 | 117 | -------------------------------------------------------------------------------- /output_files/traffic_led.flow.rpt: -------------------------------------------------------------------------------- 1 | Flow report for traffic_led 2 | Mon Jul 04 19:18:20 2022 3 | Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition 4 | 5 | 6 | --------------------- 7 | ; Table of Contents ; 8 | --------------------- 9 | 1. Legal Notice 10 | 2. Flow Summary 11 | 3. Flow Settings 12 | 4. Flow Non-Default Global Settings 13 | 5. Flow Elapsed Time 14 | 6. Flow OS Summary 15 | 7. Flow Log 16 | 8. Flow Messages 17 | 9. Flow Suppressed Messages 18 | 19 | 20 | 21 | ---------------- 22 | ; Legal Notice ; 23 | ---------------- 24 | Copyright (C) 1991-2013 Altera Corporation 25 | Your use of Altera Corporation's design tools, logic functions 26 | and other software and tools, and its AMPP partner logic 27 | functions, and any output files from any of the foregoing 28 | (including device programming or simulation files), and any 29 | associated documentation or information are expressly subject 30 | to the terms and conditions of the Altera Program License 31 | Subscription Agreement, Altera MegaCore Function License 32 | Agreement, or other applicable license agreement, including, 33 | without limitation, that your use is for the sole purpose of 34 | programming logic devices manufactured by Altera and sold by 35 | Altera or its authorized distributors. Please refer to the 36 | applicable agreement for further details. 37 | 38 | 39 | 40 | +---------------------------------------------------------------------------------+ 41 | ; Flow Summary ; 42 | +------------------------------------+--------------------------------------------+ 43 | ; Flow Status ; Successful - Mon Jul 04 19:18:20 2022 ; 44 | ; Quartus II 64-Bit Version ; 13.1.0 Build 162 10/23/2013 SJ Web Edition ; 45 | ; Revision Name ; traffic_led ; 46 | ; Top-level Entity Name ; traffic_led ; 47 | ; Family ; Cyclone IV E ; 48 | ; Device ; EP4CE6F17C8 ; 49 | ; Timing Models ; Final ; 50 | ; Total logic elements ; 781 / 6,272 ( 12 % ) ; 51 | ; Total combinational functions ; 767 / 6,272 ( 12 % ) ; 52 | ; Dedicated logic registers ; 124 / 6,272 ( 2 % ) ; 53 | ; Total registers ; 124 ; 54 | ; Total pins ; 46 / 180 ( 26 % ) ; 55 | ; Total virtual pins ; 0 ; 56 | ; Total memory bits ; 0 / 276,480 ( 0 % ) ; 57 | ; Embedded Multiplier 9-bit elements ; 0 / 30 ( 0 % ) ; 58 | ; Total PLLs ; 0 / 2 ( 0 % ) ; 59 | +------------------------------------+--------------------------------------------+ 60 | 61 | 62 | +-----------------------------------------+ 63 | ; Flow Settings ; 64 | +-------------------+---------------------+ 65 | ; Option ; Setting ; 66 | +-------------------+---------------------+ 67 | ; Start date & time ; 07/04/2022 19:18:03 ; 68 | ; Main task ; Compilation ; 69 | ; Revision Name ; traffic_led ; 70 | +-------------------+---------------------+ 71 | 72 | 73 | +-----------------------------------------------------------------------------------------------------------------------+ 74 | ; Flow Non-Default Global Settings ; 75 | +--------------------------------------+---------------------------------+---------------+-------------+----------------+ 76 | ; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; 77 | +--------------------------------------+---------------------------------+---------------+-------------+----------------+ 78 | ; COMPILER_SIGNATURE_ID ; 268987186603939.165693348316200 ; -- ; -- ; -- ; 79 | ; EDA_DESIGN_INSTANCE_NAME ; NA ; -- ; -- ; test ; 80 | ; EDA_GENERATE_FUNCTIONAL_NETLIST ; On ; -- ; -- ; eda_simulation ; 81 | ; EDA_NATIVELINK_SIMULATION_TEST_BENCH ; test ; -- ; -- ; eda_simulation ; 82 | ; EDA_NETLIST_WRITER_OUTPUT_DIR ; E:/traffic_led/simulation/qsim/ ; -- ; -- ; eda_simulation ; 83 | ; EDA_OUTPUT_DATA_FORMAT ; Verilog Hdl ; -- ; -- ; eda_simulation ; 84 | ; EDA_SIMULATION_TOOL ; ModelSim-Altera (Verilog) ; ; -- ; -- ; 85 | ; EDA_TEST_BENCH_ENABLE_STATUS ; TEST_BENCH_MODE ; -- ; -- ; eda_simulation ; 86 | ; EDA_TEST_BENCH_FILE ; test.v ; -- ; -- ; test ; 87 | ; EDA_TEST_BENCH_MODULE_NAME ; test ; -- ; -- ; test ; 88 | ; EDA_TEST_BENCH_NAME ; test ; -- ; -- ; eda_simulation ; 89 | ; EDA_TIME_SCALE ; 1 ps ; -- ; -- ; eda_simulation ; 90 | ; ENABLE_OCT_DONE ; Off ; On ; -- ; -- ; 91 | ; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ; 92 | ; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ; 93 | ; PARTITION_COLOR ; 16764057 ; -- ; -- ; Top ; 94 | ; PARTITION_FITTER_PRESERVATION_LEVEL ; PLACEMENT_AND_ROUTING ; -- ; -- ; Top ; 95 | ; PARTITION_NETLIST_TYPE ; SOURCE ; -- ; -- ; Top ; 96 | ; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ; 97 | +--------------------------------------+---------------------------------+---------------+-------------+----------------+ 98 | 99 | 100 | +-------------------------------------------------------------------------------------------------------------------------------+ 101 | ; Flow Elapsed Time ; 102 | +---------------------------+--------------+-------------------------+---------------------+------------------------------------+ 103 | ; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; 104 | +---------------------------+--------------+-------------------------+---------------------+------------------------------------+ 105 | ; Analysis & Synthesis ; 00:00:02 ; 1.0 ; 4620 MB ; 00:00:02 ; 106 | ; Fitter ; 00:00:07 ; 1.0 ; 4963 MB ; 00:00:07 ; 107 | ; Assembler ; 00:00:01 ; 1.0 ; 4582 MB ; 00:00:01 ; 108 | ; TimeQuest Timing Analyzer ; 00:00:02 ; 1.0 ; 4628 MB ; 00:00:02 ; 109 | ; EDA Netlist Writer ; 00:00:00 ; 1.0 ; 4537 MB ; 00:00:01 ; 110 | ; Total ; 00:00:12 ; -- ; -- ; 00:00:13 ; 111 | +---------------------------+--------------+-------------------------+---------------------+------------------------------------+ 112 | 113 | 114 | +----------------------------------------------------------------------------------------+ 115 | ; Flow OS Summary ; 116 | +---------------------------+------------------+-----------+------------+----------------+ 117 | ; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ; 118 | +---------------------------+------------------+-----------+------------+----------------+ 119 | ; Analysis & Synthesis ; LAPTOP-CN2MR0VN ; Windows 7 ; 6.2 ; x86_64 ; 120 | ; Fitter ; LAPTOP-CN2MR0VN ; Windows 7 ; 6.2 ; x86_64 ; 121 | ; Assembler ; LAPTOP-CN2MR0VN ; Windows 7 ; 6.2 ; x86_64 ; 122 | ; TimeQuest Timing Analyzer ; LAPTOP-CN2MR0VN ; Windows 7 ; 6.2 ; x86_64 ; 123 | ; EDA Netlist Writer ; LAPTOP-CN2MR0VN ; Windows 7 ; 6.2 ; x86_64 ; 124 | +---------------------------+------------------+-----------+------------+----------------+ 125 | 126 | 127 | ------------ 128 | ; Flow Log ; 129 | ------------ 130 | quartus_map --read_settings_files=on --write_settings_files=off traffic_led -c traffic_led 131 | quartus_fit --read_settings_files=off --write_settings_files=off traffic_led -c traffic_led 132 | quartus_asm --read_settings_files=off --write_settings_files=off traffic_led -c traffic_led 133 | quartus_sta traffic_led -c traffic_led 134 | quartus_eda --read_settings_files=off --write_settings_files=off traffic_led -c traffic_led 135 | 136 | 137 | 138 | -------------------------------------------------------------------------------- /db/alt_u_div_s6f.tdf: -------------------------------------------------------------------------------- 1 | --alt_u_div DEVICE_FAMILY="Cyclone IV E" LPM_PIPELINE=0 MAXIMIZE_SPEED=5 SKIP_BITS=0 WIDTH_D=4 WIDTH_N=10 WIDTH_Q=10 WIDTH_R=4 denominator numerator quotient remainder 2 | --VERSION_BEGIN 13.1 cbx_cycloneii 2013:10:23:18:05:48:SJ cbx_lpm_abs 2013:10:23:18:05:48:SJ cbx_lpm_add_sub 2013:10:23:18:05:48:SJ cbx_lpm_divide 2013:10:23:18:05:48:SJ cbx_mgl 2013:10:23:18:06:54:SJ cbx_stratix 2013:10:23:18:05:48:SJ cbx_stratixii 2013:10:23:18:05:48:SJ cbx_util_mgl 2013:10:23:18:05:48:SJ VERSION_END 3 | 4 | 5 | -- Copyright (C) 1991-2013 Altera Corporation 6 | -- Your use of Altera Corporation's design tools, logic functions 7 | -- and other software and tools, and its AMPP partner logic 8 | -- functions, and any output files from any of the foregoing 9 | -- (including device programming or simulation files), and any 10 | -- associated documentation or information are expressly subject 11 | -- to the terms and conditions of the Altera Program License 12 | -- Subscription Agreement, Altera MegaCore Function License 13 | -- Agreement, or other applicable license agreement, including, 14 | -- without limitation, that your use is for the sole purpose of 15 | -- programming logic devices manufactured by Altera and sold by 16 | -- Altera or its authorized distributors. Please refer to the 17 | -- applicable agreement for further details. 18 | 19 | 20 | FUNCTION add_sub_7pc (dataa[0..0], datab[0..0]) 21 | RETURNS ( cout, result[0..0]); 22 | FUNCTION add_sub_8pc (dataa[1..0], datab[1..0]) 23 | RETURNS ( cout, result[1..0]); 24 | 25 | --synthesis_resources = lut 45 26 | SUBDESIGN alt_u_div_s6f 27 | ( 28 | denominator[3..0] : input; 29 | numerator[9..0] : input; 30 | quotient[9..0] : output; 31 | remainder[3..0] : output; 32 | ) 33 | VARIABLE 34 | add_sub_0 : add_sub_7pc; 35 | add_sub_1 : add_sub_8pc; 36 | add_sub_2_result_int[3..0] : WIRE; 37 | add_sub_2_cout : WIRE; 38 | add_sub_2_dataa[2..0] : WIRE; 39 | add_sub_2_datab[2..0] : WIRE; 40 | add_sub_2_result[2..0] : WIRE; 41 | add_sub_3_result_int[4..0] : WIRE; 42 | add_sub_3_cout : WIRE; 43 | add_sub_3_dataa[3..0] : WIRE; 44 | add_sub_3_datab[3..0] : WIRE; 45 | add_sub_3_result[3..0] : WIRE; 46 | add_sub_4_result_int[5..0] : WIRE; 47 | add_sub_4_cout : WIRE; 48 | add_sub_4_dataa[4..0] : WIRE; 49 | add_sub_4_datab[4..0] : WIRE; 50 | add_sub_4_result[4..0] : WIRE; 51 | add_sub_5_result_int[5..0] : WIRE; 52 | add_sub_5_cout : WIRE; 53 | add_sub_5_dataa[4..0] : WIRE; 54 | add_sub_5_datab[4..0] : WIRE; 55 | add_sub_5_result[4..0] : WIRE; 56 | add_sub_6_result_int[5..0] : WIRE; 57 | add_sub_6_cout : WIRE; 58 | add_sub_6_dataa[4..0] : WIRE; 59 | add_sub_6_datab[4..0] : WIRE; 60 | add_sub_6_result[4..0] : WIRE; 61 | add_sub_7_result_int[5..0] : WIRE; 62 | add_sub_7_cout : WIRE; 63 | add_sub_7_dataa[4..0] : WIRE; 64 | add_sub_7_datab[4..0] : WIRE; 65 | add_sub_7_result[4..0] : WIRE; 66 | add_sub_8_result_int[5..0] : WIRE; 67 | add_sub_8_cout : WIRE; 68 | add_sub_8_dataa[4..0] : WIRE; 69 | add_sub_8_datab[4..0] : WIRE; 70 | add_sub_8_result[4..0] : WIRE; 71 | add_sub_9_result_int[5..0] : WIRE; 72 | add_sub_9_cout : WIRE; 73 | add_sub_9_dataa[4..0] : WIRE; 74 | add_sub_9_datab[4..0] : WIRE; 75 | add_sub_9_result[4..0] : WIRE; 76 | DenominatorIn[54..0] : WIRE; 77 | DenominatorIn_tmp[54..0] : WIRE; 78 | gnd_wire : WIRE; 79 | nose[109..0] : WIRE; 80 | NumeratorIn[109..0] : WIRE; 81 | NumeratorIn_tmp[109..0] : WIRE; 82 | prestg[49..0] : WIRE; 83 | quotient_tmp[9..0] : WIRE; 84 | sel[43..0] : WIRE; 85 | selnose[109..0] : WIRE; 86 | StageIn[54..0] : WIRE; 87 | StageIn_tmp[54..0] : WIRE; 88 | StageOut[49..0] : WIRE; 89 | 90 | BEGIN 91 | add_sub_0.dataa[0..0] = NumeratorIn[9..9]; 92 | add_sub_0.datab[0..0] = DenominatorIn[0..0]; 93 | add_sub_1.dataa[] = ( StageIn[5..5], NumeratorIn[18..18]); 94 | add_sub_1.datab[1..0] = DenominatorIn[6..5]; 95 | add_sub_2_result_int[] = (0, add_sub_2_dataa[]) - (0, add_sub_2_datab[]); 96 | add_sub_2_result[] = add_sub_2_result_int[2..0]; 97 | add_sub_2_cout = !add_sub_2_result_int[3]; 98 | add_sub_2_dataa[] = ( StageIn[11..10], NumeratorIn[27..27]); 99 | add_sub_2_datab[] = DenominatorIn[12..10]; 100 | add_sub_3_result_int[] = (0, add_sub_3_dataa[]) - (0, add_sub_3_datab[]); 101 | add_sub_3_result[] = add_sub_3_result_int[3..0]; 102 | add_sub_3_cout = !add_sub_3_result_int[4]; 103 | add_sub_3_dataa[] = ( StageIn[17..15], NumeratorIn[36..36]); 104 | add_sub_3_datab[] = DenominatorIn[18..15]; 105 | add_sub_4_result_int[] = (0, add_sub_4_dataa[]) - (0, add_sub_4_datab[]); 106 | add_sub_4_result[] = add_sub_4_result_int[4..0]; 107 | add_sub_4_cout = !add_sub_4_result_int[5]; 108 | add_sub_4_dataa[] = ( StageIn[23..20], NumeratorIn[45..45]); 109 | add_sub_4_datab[] = DenominatorIn[24..20]; 110 | add_sub_5_result_int[] = (0, add_sub_5_dataa[]) - (0, add_sub_5_datab[]); 111 | add_sub_5_result[] = add_sub_5_result_int[4..0]; 112 | add_sub_5_cout = !add_sub_5_result_int[5]; 113 | add_sub_5_dataa[] = ( StageIn[28..25], NumeratorIn[54..54]); 114 | add_sub_5_datab[] = DenominatorIn[29..25]; 115 | add_sub_6_result_int[] = (0, add_sub_6_dataa[]) - (0, add_sub_6_datab[]); 116 | add_sub_6_result[] = add_sub_6_result_int[4..0]; 117 | add_sub_6_cout = !add_sub_6_result_int[5]; 118 | add_sub_6_dataa[] = ( StageIn[33..30], NumeratorIn[63..63]); 119 | add_sub_6_datab[] = DenominatorIn[34..30]; 120 | add_sub_7_result_int[] = (0, add_sub_7_dataa[]) - (0, add_sub_7_datab[]); 121 | add_sub_7_result[] = add_sub_7_result_int[4..0]; 122 | add_sub_7_cout = !add_sub_7_result_int[5]; 123 | add_sub_7_dataa[] = ( StageIn[38..35], NumeratorIn[72..72]); 124 | add_sub_7_datab[] = DenominatorIn[39..35]; 125 | add_sub_8_result_int[] = (0, add_sub_8_dataa[]) - (0, add_sub_8_datab[]); 126 | add_sub_8_result[] = add_sub_8_result_int[4..0]; 127 | add_sub_8_cout = !add_sub_8_result_int[5]; 128 | add_sub_8_dataa[] = ( StageIn[43..40], NumeratorIn[81..81]); 129 | add_sub_8_datab[] = DenominatorIn[44..40]; 130 | add_sub_9_result_int[] = (0, add_sub_9_dataa[]) - (0, add_sub_9_datab[]); 131 | add_sub_9_result[] = add_sub_9_result_int[4..0]; 132 | add_sub_9_cout = !add_sub_9_result_int[5]; 133 | add_sub_9_dataa[] = ( StageIn[48..45], NumeratorIn[90..90]); 134 | add_sub_9_datab[] = DenominatorIn[49..45]; 135 | DenominatorIn[] = DenominatorIn_tmp[]; 136 | DenominatorIn_tmp[] = ( DenominatorIn[49..0], ( gnd_wire, denominator[])); 137 | gnd_wire = B"0"; 138 | nose[] = ( B"0000000000", add_sub_9_cout, B"0000000000", add_sub_8_cout, B"0000000000", add_sub_7_cout, B"0000000000", add_sub_6_cout, B"0000000000", add_sub_5_cout, B"0000000000", add_sub_4_cout, B"0000000000", add_sub_3_cout, B"0000000000", add_sub_2_cout, B"0000000000", add_sub_1.cout, B"0000000000", add_sub_0.cout); 139 | NumeratorIn[] = NumeratorIn_tmp[]; 140 | NumeratorIn_tmp[] = ( NumeratorIn[99..0], numerator[]); 141 | prestg[] = ( add_sub_9_result[], add_sub_8_result[], add_sub_7_result[], add_sub_6_result[], add_sub_5_result[], add_sub_4_result[], GND, add_sub_3_result[], B"00", add_sub_2_result[], B"000", add_sub_1.result[], B"0000", add_sub_0.result[]); 142 | quotient[] = quotient_tmp[]; 143 | quotient_tmp[] = ( (! selnose[0..0]), (! selnose[11..11]), (! selnose[22..22]), (! selnose[33..33]), (! selnose[44..44]), (! selnose[55..55]), (! selnose[66..66]), (! selnose[77..77]), (! selnose[88..88]), (! selnose[99..99])); 144 | remainder[3..0] = StageIn[53..50]; 145 | sel[] = ( gnd_wire, (sel[43..43] # DenominatorIn[53..53]), (sel[42..42] # DenominatorIn[52..52]), (sel[41..41] # DenominatorIn[51..51]), gnd_wire, (sel[39..39] # DenominatorIn[48..48]), (sel[38..38] # DenominatorIn[47..47]), (sel[37..37] # DenominatorIn[46..46]), gnd_wire, (sel[35..35] # DenominatorIn[43..43]), (sel[34..34] # DenominatorIn[42..42]), (sel[33..33] # DenominatorIn[41..41]), gnd_wire, (sel[31..31] # DenominatorIn[38..38]), (sel[30..30] # DenominatorIn[37..37]), (sel[29..29] # DenominatorIn[36..36]), gnd_wire, (sel[27..27] # DenominatorIn[33..33]), (sel[26..26] # DenominatorIn[32..32]), (sel[25..25] # DenominatorIn[31..31]), gnd_wire, (sel[23..23] # DenominatorIn[28..28]), (sel[22..22] # DenominatorIn[27..27]), (sel[21..21] # DenominatorIn[26..26]), gnd_wire, (sel[19..19] # DenominatorIn[23..23]), (sel[18..18] # DenominatorIn[22..22]), (sel[17..17] # DenominatorIn[21..21]), gnd_wire, (sel[15..15] # DenominatorIn[18..18]), (sel[14..14] # DenominatorIn[17..17]), (sel[13..13] # DenominatorIn[16..16]), gnd_wire, (sel[11..11] # DenominatorIn[13..13]), (sel[10..10] # DenominatorIn[12..12]), (sel[9..9] # DenominatorIn[11..11]), gnd_wire, (sel[7..7] # DenominatorIn[8..8]), (sel[6..6] # DenominatorIn[7..7]), (sel[5..5] # DenominatorIn[6..6]), gnd_wire, (sel[3..3] # DenominatorIn[3..3]), (sel[2..2] # DenominatorIn[2..2]), (sel[1..1] # DenominatorIn[1..1])); 146 | selnose[] = ( (! nose[109..109]), (! nose[108..108]), (! nose[107..107]), (! nose[106..106]), (! nose[105..105]), (! nose[104..104]), ((! nose[103..103]) # sel[43..43]), ((! nose[102..102]) # sel[42..42]), ((! nose[101..101]) # sel[41..41]), ((! nose[100..100]) # sel[40..40]), (! nose[99..99]), (! nose[98..98]), (! nose[97..97]), (! nose[96..96]), (! nose[95..95]), (! nose[94..94]), ((! nose[93..93]) # sel[39..39]), ((! nose[92..92]) # sel[38..38]), ((! nose[91..91]) # sel[37..37]), ((! nose[90..90]) # sel[36..36]), (! nose[89..89]), (! nose[88..88]), (! nose[87..87]), (! nose[86..86]), (! nose[85..85]), (! nose[84..84]), ((! nose[83..83]) # sel[35..35]), ((! nose[82..82]) # sel[34..34]), ((! nose[81..81]) # sel[33..33]), ((! nose[80..80]) # sel[32..32]), (! nose[79..79]), (! nose[78..78]), (! nose[77..77]), (! nose[76..76]), (! nose[75..75]), (! nose[74..74]), ((! nose[73..73]) # sel[31..31]), ((! nose[72..72]) # sel[30..30]), ((! nose[71..71]) # sel[29..29]), ((! nose[70..70]) # sel[28..28]), (! nose[69..69]), (! nose[68..68]), (! nose[67..67]), (! nose[66..66]), (! nose[65..65]), (! nose[64..64]), ((! nose[63..63]) # sel[27..27]), ((! nose[62..62]) # sel[26..26]), ((! nose[61..61]) # sel[25..25]), ((! nose[60..60]) # sel[24..24]), (! nose[59..59]), (! nose[58..58]), (! nose[57..57]), (! nose[56..56]), (! nose[55..55]), (! nose[54..54]), ((! nose[53..53]) # sel[23..23]), ((! nose[52..52]) # sel[22..22]), ((! nose[51..51]) # sel[21..21]), ((! nose[50..50]) # sel[20..20]), (! nose[49..49]), (! nose[48..48]), (! nose[47..47]), (! nose[46..46]), (! nose[45..45]), (! nose[44..44]), ((! nose[43..43]) # sel[19..19]), ((! nose[42..42]) # sel[18..18]), ((! nose[41..41]) # sel[17..17]), ((! nose[40..40]) # sel[16..16]), (! nose[39..39]), (! nose[38..38]), (! nose[37..37]), (! nose[36..36]), (! nose[35..35]), (! nose[34..34]), ((! nose[33..33]) # sel[15..15]), ((! nose[32..32]) # sel[14..14]), ((! nose[31..31]) # sel[13..13]), ((! nose[30..30]) # sel[12..12]), (! nose[29..29]), (! nose[28..28]), (! nose[27..27]), (! nose[26..26]), (! nose[25..25]), (! nose[24..24]), ((! nose[23..23]) # sel[11..11]), ((! nose[22..22]) # sel[10..10]), ((! nose[21..21]) # sel[9..9]), ((! nose[20..20]) # sel[8..8]), (! nose[19..19]), (! nose[18..18]), (! nose[17..17]), (! nose[16..16]), (! nose[15..15]), (! nose[14..14]), ((! nose[13..13]) # sel[7..7]), ((! nose[12..12]) # sel[6..6]), ((! nose[11..11]) # sel[5..5]), ((! nose[10..10]) # sel[4..4]), (! nose[9..9]), (! nose[8..8]), (! nose[7..7]), (! nose[6..6]), (! nose[5..5]), (! nose[4..4]), ((! nose[3..3]) # sel[3..3]), ((! nose[2..2]) # sel[2..2]), ((! nose[1..1]) # sel[1..1]), ((! nose[0..0]) # sel[0..0])); 147 | StageIn[] = StageIn_tmp[]; 148 | StageIn_tmp[] = ( StageOut[49..0], B"00000"); 149 | StageOut[] = ( ((( StageIn[48..45], NumeratorIn[90..90]) & selnose[99..99]) # (prestg[49..45] & (! selnose[99..99]))), ((( StageIn[43..40], NumeratorIn[81..81]) & selnose[88..88]) # (prestg[44..40] & (! selnose[88..88]))), ((( StageIn[38..35], NumeratorIn[72..72]) & selnose[77..77]) # (prestg[39..35] & (! selnose[77..77]))), ((( StageIn[33..30], NumeratorIn[63..63]) & selnose[66..66]) # (prestg[34..30] & (! selnose[66..66]))), ((( StageIn[28..25], NumeratorIn[54..54]) & selnose[55..55]) # (prestg[29..25] & (! selnose[55..55]))), ((( StageIn[23..20], NumeratorIn[45..45]) & selnose[44..44]) # (prestg[24..20] & (! selnose[44..44]))), ((( StageIn[18..15], NumeratorIn[36..36]) & selnose[33..33]) # (prestg[19..15] & (! selnose[33..33]))), ((( StageIn[13..10], NumeratorIn[27..27]) & selnose[22..22]) # (prestg[14..10] & (! selnose[22..22]))), ((( StageIn[8..5], NumeratorIn[18..18]) & selnose[11..11]) # (prestg[9..5] & (! selnose[11..11]))), ((( StageIn[3..0], NumeratorIn[9..9]) & selnose[0..0]) # (prestg[4..0] & (! selnose[0..0])))); 150 | END; 151 | --VALID FILE 152 | -------------------------------------------------------------------------------- /state_trans_model.v: -------------------------------------------------------------------------------- 1 | module state_trans_model( 2 | //input 3 | input sys_clk , //系统时钟 4 | input sys_rst_n , //系统复位 5 | 6 | output reg [3:0] state , //交通灯的状态，用于控制LED灯的点亮 7 | output reg [9:0] n_time , //交通灯北向数码管要显示的时间数据 8 | output reg [9:0] e_time , //交通灯东向数码管要显示的时间数据 9 | output reg [9:0] s_time , //交通灯南向数码管要显示的时间数据 10 | output reg [9:0] w_time , //交通灯西向数码管要显示的时间数据 11 | output reg [9:0] nl_time , //交通灯北向数码管要显示的时间数据 12 | output reg [9:0] el_time , //交通灯东向数码管要显示的时间数据 13 | output reg [9:0] sl_time , //交通灯南向数码管要显示的时间数据 14 | output reg [9:0] wl_time //交通灯西向数码管要显示的时间数据 15 | ); 16 | 17 | //parameter define 18 | parameter TIME_LED_NSY = 3; //黄灯发光的时间 19 | parameter TIME_LED_NSR = 60; //红灯发光的时间 20 | parameter TIME_LED_NSG = 27; //绿灯发光的时间 21 | parameter TIME_LED_WEY = 3; //黄灯发光的时间 22 | parameter TIME_LED_WER = 60; //红灯发光的时间 23 | parameter TIME_LED_WEG = 27; //绿灯发光的时间 24 | parameter WIDTH = 25000000; 25 | 26 | //reg define 27 | reg [5:0] time_cnt; //产生数码管显示时间的计数器 28 | reg [24:0] t_count; //用于产生clk_1hz的计数器 29 | reg clk_t; //1hz时钟 30 | 31 | always @(posedge sys_clk or negedge sys_rst_n)begin 32 | if(!sys_rst_n)begin 33 | t_count <= 25'b0; 34 | clk_t <= 1'b0; 35 | end 36 | else if (t_count < WIDTH - 1'b1)begin 37 | t_count <= t_count + 1'b1; 38 | clk_t <= clk_t; 39 | end 40 | else begin 41 | t_count <= 25'b0; 42 | clk_t <= ~ clk_t; 43 | end 44 | end 45 | 46 | //切换交通信号灯工作的8个状态，并产生数码管要显示的时间数据 47 | always @(posedge clk_t or negedge sys_rst_n)begin 48 | if(!sys_rst_n)begin 49 | state <= 4'd0; 50 | time_cnt <= TIME_LED_NSG ; //状态1持续的时间 51 | end 52 | else begin 53 | case (state) 54 | 4'b0000: begin //状态1 南北为绿灯，东西为黄灯 55 | n_time <= time_cnt - 1'b1; //绿灯倒计时 56 | e_time <= time_cnt + TIME_LED_NSY*2+TIME_LED_NSG- 1'b1 ; //红灯倒计时60S 57 | s_time <= time_cnt - 1'b1; //绿灯倒计时 58 | w_time <= time_cnt + TIME_LED_NSY*2+TIME_LED_NSG- 1'b1 ; 59 | nl_time <= time_cnt + TIME_LED_NSY- 1'b1; //红灯倒计时30s 60 | el_time <= time_cnt + TIME_LED_NSY*2+TIME_LED_NSG+TIME_LED_WEG+TIME_LED_WEY- 1'b1 ; //红灯倒计时90s 61 | sl_time <= time_cnt + TIME_LED_NSY - 1'b1; 62 | wl_time <= time_cnt + TIME_LED_NSY*2+TIME_LED_NSG+TIME_LED_WEG+TIME_LED_WEY- 1'b1 ; 63 | if (time_cnt > 1)begin //time_cnt等于1的时候切换状态，转换为黄灯 64 | time_cnt <= time_cnt - 1'b1; 65 | state <= state; 66 | end 67 | else begin 68 | time_cnt <= TIME_LED_NSY; //状态2持续的时间 //南北直行变为黄灯 69 | state <= 4'b0001; //切换到状态2 70 | n_time <= TIME_LED_NSY; 71 | e_time <= TIME_LED_WER-TIME_LED_NSG; //等待红灯33s 72 | s_time <= TIME_LED_NSY; 73 | w_time <= TIME_LED_WER-TIME_LED_NSG; //南北黄灯，东西为红灯等待南北左转绿灯与红灯 74 | nl_time <= TIME_LED_NSY; //等待与南北黄灯相同时间的红灯 75 | el_time <= TIME_LED_WER+TIME_LED_NSY; //等待南北左转30s+东西直行30s+南北直行3s黄灯 76 | sl_time <= TIME_LED_NSY; 77 | wl_time <= TIME_LED_WER+TIME_LED_NSY; 78 | end 79 | end 80 | 4'b0001: begin //状态2 南北直行为黄灯，左转为红灯；东西直行左转为红灯 81 | n_time <= time_cnt - 1'b1; 82 | e_time <= TIME_LED_NSG+TIME_LED_NSY*2+time_cnt - 1'b1; //等待33s红灯 83 | s_time <= time_cnt - 1'b1; 84 | w_time <= TIME_LED_NSG+TIME_LED_NSY*2+time_cnt - 1'b1; 85 | nl_time <= time_cnt- 1'b1; //左转等待直行黄灯变绿灯 86 | el_time <= time_cnt + TIME_LED_NSY+TIME_LED_NSG+TIME_LED_WEG+TIME_LED_WEY- 1'b1 ; //等待63s红灯 87 | sl_time <= time_cnt- 1'b1; 88 | wl_time <= time_cnt + TIME_LED_NSY+TIME_LED_NSG+TIME_LED_WEG+TIME_LED_WEY- 1'b1 ; 89 | if (time_cnt > 1)begin 90 | time_cnt <= time_cnt - 1'b1; 91 | state <= state; 92 | end 93 | else begin 94 | time_cnt <= TIME_LED_NSG; //状态3持续的时间 南北左转绿灯 95 | state <= 4'b0010; //切换到状态3 96 | e_time <= TIME_LED_NSY+TIME_LED_NSG ; //等待30s红灯 97 | s_time <= TIME_LED_NSY+TIME_LED_NSG+TIME_LED_NSR; //等待90s红灯 98 | w_time <= TIME_LED_NSY+TIME_LED_NSG ; 99 | n_time <= TIME_LED_NSY+TIME_LED_NSG+TIME_LED_NSR; 100 | nl_time <= TIME_LED_NSG; //绿灯 101 | el_time <= TIME_LED_WER; //等待60s红灯 102 | sl_time <= TIME_LED_NSG; 103 | wl_time <= TIME_LED_WER; 104 | end 105 | end 106 | 4'b0010: begin //状态3 南北直行红灯，左转绿灯；东西都为红灯 107 | e_time <= TIME_LED_NSY+time_cnt - 1'b1; //30S倒计时 108 | s_time <= TIME_LED_WER+time_cnt + TIME_LED_NSY - 1'b1; //90S倒计时 109 | w_time <= TIME_LED_NSY+time_cnt - 1'b1; 110 | n_time <= TIME_LED_WER+time_cnt + TIME_LED_NSY - 1'b1; 111 | nl_time <= time_cnt- 1'b1; //绿灯27s 112 | el_time <= time_cnt+TIME_LED_NSY+TIME_LED_WEY+TIME_LED_WEG- 1'b1 ; //东西左转等60s 113 | sl_time <= time_cnt- 1'b1; 114 | wl_time <= time_cnt+TIME_LED_NSY+TIME_LED_WEY+TIME_LED_WEG- 1'b1 ; 115 | if (time_cnt > 1)begin 116 | time_cnt <= time_cnt - 1'b1; 117 | state <= state; 118 | end 119 | else begin 120 | time_cnt <= TIME_LED_NSY; //状态4持续的时间 南北左转黄灯 121 | state <= 4'b0011; //切换到转态4 122 | e_time <= TIME_LED_NSY; //3S倒计时为绿灯 123 | s_time <= TIME_LED_NSY+TIME_LED_WER; //63S红灯倒计时 124 | w_time <= TIME_LED_NSY; 125 | s_time <= TIME_LED_NSY+TIME_LED_WER; 126 | nl_time <= TIME_LED_NSY; //3S黄灯倒计时 127 | el_time <= TIME_LED_NSY+TIME_LED_WEY+TIME_LED_WEG; //33S红灯倒计时 128 | sl_time <= TIME_LED_NSY; 129 | wl_time <= TIME_LED_NSY+TIME_LED_WEY+TIME_LED_WEG; 130 | end 131 | end 132 | 4'b0011: begin //状态4 南北左转黄灯 133 | e_time <= time_cnt - 1'b1; 134 | s_time <= TIME_LED_NSR+time_cnt - 1'b1; //南北等待63s红灯 135 | w_time <= time_cnt - 1'b1; 136 | n_time <= TIME_LED_NSR+time_cnt - 1'b1; 137 | el_time <= TIME_LED_WEY+ TIME_LED_WEG+time_cnt - 1'b1; //30S倒计时 138 | sl_time <= time_cnt - 1'b1; //3S倒计时 139 | wl_time <= TIME_LED_WEY+ TIME_LED_WEG+time_cnt - 1'b1; 140 | nl_time <= time_cnt - 1'b1; 141 | if (time_cnt > 1)begin 142 | time_cnt <= time_cnt - 1'b1; 143 | state <= state; 144 | end 145 | else begin 146 | time_cnt <= TIME_LED_WEG; 147 | state <= 4'b0100; //切换到状态5 东西直行绿灯 148 | n_time <= TIME_LED_NSR; //南北直行等待60s 149 | e_time <= TIME_LED_WEG; //东西绿灯 150 | s_time <= TIME_LED_NSR; 151 | w_time <= TIME_LED_WEG; 152 | nl_time <= TIME_LED_WER+TIME_LED_NSG+TIME_LED_NSY; //等待90s 153 | el_time <= TIME_LED_WEY+TIME_LED_WEG; //30S红灯倒计时 154 | sl_time <= TIME_LED_WER+TIME_LED_NSG+TIME_LED_NSY; 155 | wl_time <= TIME_LED_WEY+TIME_LED_WEG; 156 | end 157 | end 158 | 4'b0100: begin //状态5 南北都为红灯；东西直行绿灯，左转红灯 159 | e_time <= time_cnt - 1'b1; 160 | s_time <= TIME_LED_WEY+TIME_LED_WEG+TIME_LED_WEY+time_cnt - 1'b1; //南北等待60s红灯 161 | w_time <= time_cnt - 1'b1; 162 | n_time <= TIME_LED_WEY+TIME_LED_WEG+TIME_LED_WEY+time_cnt - 1'b1; 163 | el_time <= TIME_LED_WEY+time_cnt - 1'b1; //30S倒计时 164 | sl_time <= TIME_LED_NSR+TIME_LED_WEY+time_cnt - 1'b1; //90S倒计时 165 | wl_time <= TIME_LED_WEY+time_cnt - 1'b1; 166 | nl_time <= TIME_LED_NSR+TIME_LED_WEY+time_cnt - 1'b1; 167 | if (time_cnt > 1)begin 168 | time_cnt <= time_cnt - 1'b1; 169 | state <= state; 170 | end 171 | else begin 172 | time_cnt <= TIME_LED_WEY; 173 | state <= 4'b0101; //切换到状态6 南北都为红灯；东西直行黄灯，左转红灯 174 | n_time <= TIME_LED_WEG+TIME_LED_WEY*2; //南北直行等待33s 175 | e_time <= TIME_LED_WEY; //东西直行黄灯 176 | s_time <= TIME_LED_NSR; 177 | w_time <= TIME_LED_WEY; 178 | nl_time <= TIME_LED_NSR+TIME_LED_WEY; //等待63s 179 | el_time <= TIME_LED_WEY; //3S红灯倒计时 180 | sl_time <= TIME_LED_NSR+TIME_LED_WEY; 181 | wl_time <= TIME_LED_WEY; 182 | end 183 | end 184 | 4'b0101: begin //状态6 南北都为红灯；东西直行黄灯，左转红灯 185 | e_time <= time_cnt - 1'b1; //直行黄灯3s倒计时 186 | s_time <= TIME_LED_WEG+TIME_LED_WEY+time_cnt - 1'b1; //南北等待33s红灯 187 | w_time <= time_cnt - 1'b1; 188 | n_time <= TIME_LED_WEG+TIME_LED_WEY+time_cnt - 1'b1; 189 | el_time <= time_cnt - 1'b1; //3S倒计时 190 | sl_time <= TIME_LED_NSR+time_cnt - 1'b1; //63S倒计时 191 | wl_time <= time_cnt - 1'b1; 192 | nl_time <= TIME_LED_NSR+time_cnt - 1'b1; 193 | if (time_cnt > 1)begin 194 | time_cnt <= time_cnt - 1'b1; 195 | state <= state; 196 | end 197 | else begin 198 | time_cnt <= TIME_LED_WEG; 199 | state <= 4'b0110; //切换到状态7 东西直行红灯，左转绿灯 200 | n_time <= TIME_LED_WEG+TIME_LED_WEY; //南北直行等待30s 201 | e_time <= TIME_LED_WEG+TIME_LED_WEY+TIME_LED_WER; //红灯90s 202 | s_time <= TIME_LED_WEG+TIME_LED_WEY; 203 | w_time <= TIME_LED_WEG+TIME_LED_WEY+TIME_LED_WER; 204 | nl_time <= TIME_LED_WEG+TIME_LED_WEY+TIME_LED_NSY+TIME_LED_NSG; //等待60s 205 | el_time <= TIME_LED_WEG; //27s绿灯倒计时 206 | sl_time <= TIME_LED_WEG+TIME_LED_WEY+TIME_LED_NSY+TIME_LED_NSG; 207 | wl_time <= TIME_LED_WEG; 208 | end 209 | end 210 | 4'b0110: begin //状态7 东西直行红灯，左转绿灯 211 | e_time <= time_cnt - 1'b1; 212 | s_time <= TIME_LED_WEY+time_cnt - 1'b1; //南北等待30s红灯 213 | w_time <= time_cnt - 1'b1; 214 | n_time <= TIME_LED_WEY+time_cnt - 1'b1; 215 | el_time <= time_cnt - 1'b1; //绿灯倒计时 216 | sl_time <= TIME_LED_WEY+TIME_LED_NSG+TIME_LED_NSY+time_cnt - 1'b1; //60S倒计时 217 | wl_time <= time_cnt - 1'b1; 218 | nl_time <= TIME_LED_WEY+TIME_LED_NSG+TIME_LED_NSY+time_cnt - 1'b1; 219 | if (time_cnt > 1)begin 220 | time_cnt <= time_cnt - 1'b1; 221 | state <= state; 222 | end 223 | else begin 224 | time_cnt <= TIME_LED_WEY; 225 | state <= 4'b0111; //切换到状态8 南北都为红灯；东西直行红灯，左转黄灯 226 | 227 | n_time <= TIME_LED_WEY; //南北直行等待3s 228 | e_time <= TIME_LED_WEG+TIME_LED_WEY; //东西63s红灯 229 | s_time <= TIME_LED_WEY; 230 | w_time <= TIME_LED_WEG+TIME_LED_WEY; 231 | nl_time <= TIME_LED_WEY+TIME_LED_NSG+TIME_LED_NSY; //等待33s 232 | el_time <= TIME_LED_WEY; //3s黄灯 233 | sl_time <= TIME_LED_WEY+TIME_LED_NSG+TIME_LED_NSY; 234 | wl_time <= TIME_LED_WEY; 235 | end 236 | end 237 | 4'b0111: begin //状态8 南北都为红灯；东西直行红灯，左转黄灯 238 | e_time <= TIME_LED_WER+time_cnt - 1'b1; //东西直行等待63s红灯 239 | s_time <= time_cnt - 1'b1; //南北等待3s红灯 240 | w_time <= TIME_LED_WER+time_cnt - 1'b1; 241 | n_time <= time_cnt - 1'b1; 242 | el_time <= time_cnt - 1'b1; //30S倒计时 243 | sl_time <= TIME_LED_NSY+TIME_LED_NSG+time_cnt - 1'b1; //3S倒计时 244 | wl_time <= time_cnt - 1'b1; 245 | nl_time <= TIME_LED_NSY+TIME_LED_NSG+time_cnt - 1'b1; 246 | if (time_cnt > 1)begin 247 | time_cnt <= time_cnt - 1'b1; 248 | state <= state; 249 | end 250 | else begin 251 | time_cnt <= TIME_LED_NSG; 252 | state <= 4'b0000; //切换到状态1 南北直行绿灯，左转红灯；东西都为红灯 253 | n_time <= TIME_LED_NSG; //南北直行 254 | e_time <= TIME_LED_WER; //东西等待60s 255 | s_time <= TIME_LED_NSG; 256 | w_time <= TIME_LED_WER; 257 | nl_time <= TIME_LED_NSG+TIME_LED_NSY; //等待30s 258 | el_time <= TIME_LED_WER+TIME_LED_NSY+TIME_LED_NSG; //90S红灯倒计时 259 | sl_time <= TIME_LED_NSG+TIME_LED_NSY; 260 | wl_time <= TIME_LED_WER+TIME_LED_NSY+TIME_LED_NSG; 261 | end 262 | end 263 | default: begin 264 | state <= 4'b0; 265 | time_cnt <= TIME_LED_NSG; 266 | n_time <= TIME_LED_NSG; 267 | e_time <= TIME_LED_WER; 268 | s_time <= TIME_LED_NSG; 269 | w_time <= TIME_LED_WER; 270 | nl_time <= TIME_LED_NSG+TIME_LED_NSY; 271 | el_time <= TIME_LED_WER+TIME_LED_NSY+TIME_LED_NSG; 272 | sl_time <= TIME_LED_NSG+TIME_LED_NSY; 273 | wl_time <= TIME_LED_WER+TIME_LED_NSY+TIME_LED_NSG; 274 | end 275 | endcase 276 | end 277 | end 278 | 279 | endmodule -------------------------------------------------------------------------------- /db/traffic_led.sta.qmsg: -------------------------------------------------------------------------------- 1 | { "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1656933497007 ""} 2 | { "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 64-Bit " "Running Quartus II 64-Bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1656933497008 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Jul 04 19:18:16 2022 " "Processing started: Mon Jul 04 19:18:16 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1656933497008 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1656933497008 ""} 3 | { "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta traffic_led -c traffic_led " "Command: quartus_sta traffic_led -c traffic_led" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1656933497008 ""} 4 | { "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1656933497115 ""} 5 | { "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1656933497243 ""} 6 | { "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1656933497275 ""} 7 | { "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1656933497275 ""} 8 | { "Critical Warning" "WSTA_SDC_NOT_FOUND" "traffic_led.sdc " "Synopsys Design Constraints File file not found: 'traffic_led.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1656933497489 ""} 9 | { "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1656933497489 ""} 10 | { "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name sys_clk sys_clk " "create_clock -period 1.000 -name sys_clk sys_clk" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1656933497491 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name state_trans_model:u0_state_trans_model\|clk_t state_trans_model:u0_state_trans_model\|clk_t " "create_clock -period 1.000 -name state_trans_model:u0_state_trans_model\|clk_t state_trans_model:u0_state_trans_model\|clk_t" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1656933497491 ""} } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1656933497491 ""} 11 | { "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Quartus II" 0 -1 1656933497560 ""} 12 | { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1656933497561 ""} 13 | { "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1656933497562 ""} 14 | { "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Quartus II" 0 0 1656933497568 ""} 15 | { "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1656933497587 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1656933497587 ""} 16 | { "Info" "ISTA_WORST_CASE_SLACK" "setup -19.512 " "Worst-case setup slack is -19.512" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1656933497589 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1656933497589 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -19.512 -270.008 sys_clk " " -19.512 -270.008 sys_clk " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1656933497589 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -5.323 -147.771 state_trans_model:u0_state_trans_model\|clk_t " " -5.323 -147.771 state_trans_model:u0_state_trans_model\|clk_t " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1656933497589 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1656933497589 ""} 17 | { "Info" "ISTA_WORST_CASE_SLACK" "hold 0.146 " "Worst-case hold slack is 0.146" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1656933497594 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1656933497594 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.146 0.000 sys_clk " " 0.146 0.000 sys_clk " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1656933497594 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.453 0.000 state_trans_model:u0_state_trans_model\|clk_t " " 0.453 0.000 state_trans_model:u0_state_trans_model\|clk_t " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1656933497594 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1656933497594 ""} 18 | { "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1656933497596 ""} 19 | { "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1656933497598 ""} 20 | { "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1656933497600 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1656933497600 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -135.343 sys_clk " " -3.000 -135.343 sys_clk " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1656933497600 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.487 -52.045 state_trans_model:u0_state_trans_model\|clk_t " " -1.487 -52.045 state_trans_model:u0_state_trans_model\|clk_t " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1656933497600 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1656933497600 ""} 21 | { "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Quartus II" 0 0 1656933497691 ""} 22 | { "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1656933497713 ""} 23 | { "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1656933498024 ""} 24 | { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1656933498113 ""} 25 | { "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1656933498119 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1656933498119 ""} 26 | { "Info" "ISTA_WORST_CASE_SLACK" "setup -17.892 " "Worst-case setup slack is -17.892" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1656933498122 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1656933498122 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -17.892 -245.142 sys_clk " " -17.892 -245.142 sys_clk " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1656933498122 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -4.835 -134.405 state_trans_model:u0_state_trans_model\|clk_t " " -4.835 -134.405 state_trans_model:u0_state_trans_model\|clk_t " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1656933498122 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1656933498122 ""} 27 | { "Info" "ISTA_WORST_CASE_SLACK" "hold 0.229 " "Worst-case hold slack is 0.229" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1656933498126 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1656933498126 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.229 0.000 sys_clk " " 0.229 0.000 sys_clk " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1656933498126 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.402 0.000 state_trans_model:u0_state_trans_model\|clk_t " " 0.402 0.000 state_trans_model:u0_state_trans_model\|clk_t " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1656933498126 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1656933498126 ""} 28 | { "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1656933498129 ""} 29 | { "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1656933498133 ""} 30 | { "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1656933498136 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1656933498136 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -135.343 sys_clk " " -3.000 -135.343 sys_clk " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1656933498136 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.487 -52.045 state_trans_model:u0_state_trans_model\|clk_t " " -1.487 -52.045 state_trans_model:u0_state_trans_model\|clk_t " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1656933498136 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1656933498136 ""} 31 | { "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Quartus II" 0 0 1656933498223 ""} 32 | { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1656933498394 ""} 33 | { "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1656933498396 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1656933498396 ""} 34 | { "Info" "ISTA_WORST_CASE_SLACK" "setup -7.730 " "Worst-case setup slack is -7.730" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1656933498401 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1656933498401 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -7.730 -66.383 sys_clk " " -7.730 -66.383 sys_clk " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1656933498401 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.741 -43.775 state_trans_model:u0_state_trans_model\|clk_t " " -1.741 -43.775 state_trans_model:u0_state_trans_model\|clk_t " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1656933498401 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1656933498401 ""} 35 | { "Info" "ISTA_WORST_CASE_SLACK" "hold -0.072 " "Worst-case hold slack is -0.072" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1656933498406 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1656933498406 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.072 -0.072 sys_clk " " -0.072 -0.072 sys_clk " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1656933498406 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.187 0.000 state_trans_model:u0_state_trans_model\|clk_t " " 0.187 0.000 state_trans_model:u0_state_trans_model\|clk_t " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1656933498406 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1656933498406 ""} 36 | { "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1656933498409 ""} 37 | { "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1656933498413 ""} 38 | { "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1656933498417 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1656933498417 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -98.223 sys_clk " " -3.000 -98.223 sys_clk " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1656933498417 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.000 -35.000 state_trans_model:u0_state_trans_model\|clk_t " " -1.000 -35.000 state_trans_model:u0_state_trans_model\|clk_t " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1656933498417 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1656933498417 ""} 39 | { "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1656933498794 ""} 40 | { "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1656933498794 ""} 41 | { "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 5 s Quartus II 64-Bit " "Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4628 " "Peak virtual memory: 4628 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1656933498867 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Jul 04 19:18:18 2022 " "Processing ended: Mon Jul 04 19:18:18 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1656933498867 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1656933498867 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1656933498867 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1656933498867 ""} 42 | -------------------------------------------------------------------------------- /traffic_led.bdf: -------------------------------------------------------------------------------- 1 | /* 2 | WARNING: Do NOT edit the input and output ports in this file in a text 3 | editor if you plan to continue editing the block that represents it in 4 | the Block Editor! File corruption is VERY likely to occur. 5 | */ 6 | /* 7 | Copyright (C) 1991-2013 Altera Corporation 8 | Your use of Altera Corporation's design tools, logic functions 9 | and other software and tools, and its AMPP partner logic 10 | functions, and any output files from any of the foregoing 11 | (including device programming or simulation files), and any 12 | associated documentation or information are expressly subject 13 | to the terms and conditions of the Altera Program License 14 | Subscription Agreement, Altera MegaCore Function License 15 | Agreement, or other applicable license agreement, including, 16 | without limitation, that your use is for the sole purpose of 17 | programming logic devices manufactured by Altera and sold by 18 | Altera or its authorized distributors. Please refer to the 19 | applicable agreement for further details. 20 | */ 21 | (header "graphic" (version "1.4")) 22 | (pin 23 | (input) 24 | (rect 56 128 224 144) 25 | (text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6))) 26 | (text "clk" (rect 5 0 19 12)(font "Arial" )) 27 | (pt 168 8) 28 | (drawing 29 | (line (pt 84 12)(pt 109 12)) 30 | (line (pt 84 4)(pt 109 4)) 31 | (line (pt 113 8)(pt 168 8)) 32 | (line (pt 84 12)(pt 84 4)) 33 | (line (pt 109 4)(pt 113 8)) 34 | (line (pt 109 12)(pt 113 8)) 35 | ) 36 | (text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6))) 37 | ) 38 | (pin 39 | (input) 40 | (rect 56 200 224 216) 41 | (text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6))) 42 | (text "rst" (rect 5 0 17 12)(font "Arial" )) 43 | (pt 168 8) 44 | (drawing 45 | (line (pt 84 12)(pt 109 12)) 46 | (line (pt 84 4)(pt 109 4)) 47 | (line (pt 113 8)(pt 168 8)) 48 | (line (pt 84 12)(pt 84 4)) 49 | (line (pt 109 4)(pt 113 8)) 50 | (line (pt 109 12)(pt 113 8)) 51 | ) 52 | (text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6))) 53 | ) 54 | (pin 55 | (input) 56 | (rect 48 368 216 384) 57 | (text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6))) 58 | (text "key[3..0]" (rect 5 0 49 12)(font "Arial" )) 59 | (pt 168 8) 60 | (drawing 61 | (line (pt 84 12)(pt 109 12)) 62 | (line (pt 84 4)(pt 109 4)) 63 | (line (pt 113 8)(pt 168 8)) 64 | (line (pt 84 12)(pt 84 4)) 65 | (line (pt 109 4)(pt 113 8)) 66 | (line (pt 109 12)(pt 113 8)) 67 | ) 68 | (text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6))) 69 | (annotation_block (location)(rect -16 336 48 384)) 70 | ) 71 | (pin 72 | (output) 73 | (rect 1272 368 1448 384) 74 | (text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6))) 75 | (text "nl time" (rect 90 0 123 12)(font "Arial" )) 76 | (pt 0 8) 77 | (drawing 78 | (line (pt 0 8)(pt 52 8)) 79 | (line (pt 52 4)(pt 78 4)) 80 | (line (pt 52 12)(pt 78 12)) 81 | (line (pt 52 12)(pt 52 4)) 82 | (line (pt 78 4)(pt 82 8)) 83 | (line (pt 82 8)(pt 78 12)) 84 | (line (pt 78 12)(pt 82 8)) 85 | ) 86 | ) 87 | (pin 88 | (output) 89 | (rect 1272 384 1448 400) 90 | (text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6))) 91 | (text "el time" (rect 90 0 123 12)(font "Arial" )) 92 | (pt 0 8) 93 | (drawing 94 | (line (pt 0 8)(pt 52 8)) 95 | (line (pt 52 4)(pt 78 4)) 96 | (line (pt 52 12)(pt 78 12)) 97 | (line (pt 52 12)(pt 52 4)) 98 | (line (pt 78 4)(pt 82 8)) 99 | (line (pt 82 8)(pt 78 12)) 100 | (line (pt 78 12)(pt 82 8)) 101 | ) 102 | ) 103 | (pin 104 | (output) 105 | (rect 1272 400 1448 416) 106 | (text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6))) 107 | (text "sl time" (rect 90 0 123 12)(font "Arial" )) 108 | (pt 0 8) 109 | (drawing 110 | (line (pt 0 8)(pt 52 8)) 111 | (line (pt 52 4)(pt 78 4)) 112 | (line (pt 52 12)(pt 78 12)) 113 | (line (pt 52 12)(pt 52 4)) 114 | (line (pt 78 4)(pt 82 8)) 115 | (line (pt 82 8)(pt 78 12)) 116 | (line (pt 78 12)(pt 82 8)) 117 | ) 118 | ) 119 | (pin 120 | (output) 121 | (rect 1272 416 1448 432) 122 | (text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6))) 123 | (text "wl time" (rect 90 0 124 12)(font "Arial" )) 124 | (pt 0 8) 125 | (drawing 126 | (line (pt 0 8)(pt 52 8)) 127 | (line (pt 52 4)(pt 78 4)) 128 | (line (pt 52 12)(pt 78 12)) 129 | (line (pt 52 12)(pt 52 4)) 130 | (line (pt 78 4)(pt 82 8)) 131 | (line (pt 82 8)(pt 78 12)) 132 | (line (pt 78 12)(pt 82 8)) 133 | ) 134 | ) 135 | (pin 136 | (output) 137 | (rect 1648 -48 1824 -32) 138 | (text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6))) 139 | (text "bit" (rect 90 0 101 12)(font "Arial" )) 140 | (pt 0 8) 141 | (drawing 142 | (line (pt 0 8)(pt 52 8)) 143 | (line (pt 52 4)(pt 78 4)) 144 | (line (pt 52 12)(pt 78 12)) 145 | (line (pt 52 12)(pt 52 4)) 146 | (line (pt 78 4)(pt 82 8)) 147 | (line (pt 82 8)(pt 78 12)) 148 | (line (pt 78 12)(pt 82 8)) 149 | ) 150 | ) 151 | (pin 152 | (output) 153 | (rect 1648 -32 1824 -16) 154 | (text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6))) 155 | (text "segment" (rect 90 0 132 12)(font "Arial" )) 156 | (pt 0 8) 157 | (drawing 158 | (line (pt 0 8)(pt 52 8)) 159 | (line (pt 52 4)(pt 78 4)) 160 | (line (pt 52 12)(pt 78 12)) 161 | (line (pt 52 12)(pt 52 4)) 162 | (line (pt 78 4)(pt 82 8)) 163 | (line (pt 82 8)(pt 78 12)) 164 | (line (pt 78 12)(pt 82 8)) 165 | ) 166 | ) 167 | (pin 168 | (output) 169 | (rect 824 368 1000 384) 170 | (text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6))) 171 | (text "led" (rect 90 0 104 12)(font "Arial" )) 172 | (pt 0 8) 173 | (drawing 174 | (line (pt 0 8)(pt 52 8)) 175 | (line (pt 52 4)(pt 78 4)) 176 | (line (pt 52 12)(pt 78 12)) 177 | (line (pt 52 12)(pt 52 4)) 178 | (line (pt 78 4)(pt 82 8)) 179 | (line (pt 82 8)(pt 78 12)) 180 | (line (pt 78 12)(pt 82 8)) 181 | ) 182 | ) 183 | (symbol 184 | (rect 1360 -72 1568 104) 185 | (text "bit_seg_module" (rect 5 0 81 12)(font "Arial" )) 186 | (text "inst" (rect 8 160 25 172)(font "Arial" )) 187 | (port 188 | (pt 0 32) 189 | (input) 190 | (text "sys_clk" (rect 0 0 38 12)(font "Arial" )) 191 | (text "sys_clk" (rect 21 27 59 39)(font "Arial" )) 192 | (line (pt 0 32)(pt 16 32)) 193 | ) 194 | (port 195 | (pt 0 48) 196 | (input) 197 | (text "sys_rst_n" (rect 0 0 49 12)(font "Arial" )) 198 | (text "sys_rst_n" (rect 21 43 70 55)(font "Arial" )) 199 | (line (pt 0 48)(pt 16 48)) 200 | ) 201 | (port 202 | (pt 0 64) 203 | (input) 204 | (text "n_time[9..0]" (rect 0 0 59 12)(font "Arial" )) 205 | (text "n_time[9..0]" (rect 21 59 80 71)(font "Arial" )) 206 | (line (pt 0 64)(pt 16 64)(line_width 3)) 207 | ) 208 | (port 209 | (pt 0 80) 210 | (input) 211 | (text "e_time[9..0]" (rect 0 0 59 12)(font "Arial" )) 212 | (text "e_time[9..0]" (rect 21 75 80 87)(font "Arial" )) 213 | (line (pt 0 80)(pt 16 80)(line_width 3)) 214 | ) 215 | (port 216 | (pt 0 96) 217 | (input) 218 | (text "s_time[9..0]" (rect 0 0 59 12)(font "Arial" )) 219 | (text "s_time[9..0]" (rect 21 91 80 103)(font "Arial" )) 220 | (line (pt 0 96)(pt 16 96)(line_width 3)) 221 | ) 222 | (port 223 | (pt 0 112) 224 | (input) 225 | (text "w_time[9..0]" (rect 0 0 60 12)(font "Arial" )) 226 | (text "w_time[9..0]" (rect 21 107 81 119)(font "Arial" )) 227 | (line (pt 0 112)(pt 16 112)(line_width 3)) 228 | ) 229 | (port 230 | (pt 0 128) 231 | (input) 232 | (text "en" (rect 0 0 11 12)(font "Arial" )) 233 | (text "en" (rect 21 123 32 135)(font "Arial" )) 234 | (line (pt 0 128)(pt 16 128)) 235 | ) 236 | (port 237 | (pt 208 32) 238 | (output) 239 | (text "bit[7..0]" (rect 0 0 37 12)(font "Arial" )) 240 | (text "bit[7..0]" (rect 149 27 186 39)(font "Arial" )) 241 | (line (pt 208 32)(pt 192 32)(line_width 3)) 242 | ) 243 | (port 244 | (pt 208 48) 245 | (output) 246 | (text "segment[7..0]" (rect 0 0 68 12)(font "Arial" )) 247 | (text "segment[7..0]" (rect 113 43 181 55)(font "Arial" )) 248 | (line (pt 208 48)(pt 192 48)(line_width 3)) 249 | ) 250 | (parameter 251 | "state_count" 252 | "25000" 253 | "" 254 | (type "PARAMETER_SIGNED_DEC") ) 255 | (drawing 256 | (rectangle (rect 16 16 192 160)) 257 | ) 258 | (annotation_block (parameter)(rect 1360 -128 1576 -96)) 259 | ) 260 | (symbol 261 | (rect 528 112 704 224) 262 | (text "led_module" (rect 5 0 60 12)(font "Arial" )) 263 | (text "inst1" (rect 8 96 31 108)(font "Arial" )) 264 | (port 265 | (pt 0 32) 266 | (input) 267 | (text "sys_clk" (rect 0 0 38 12)(font "Arial" )) 268 | (text "sys_clk" (rect 21 27 59 39)(font "Arial" )) 269 | (line (pt 0 32)(pt 16 32)) 270 | ) 271 | (port 272 | (pt 0 48) 273 | (input) 274 | (text "sys_rst_n" (rect 0 0 49 12)(font "Arial" )) 275 | (text "sys_rst_n" (rect 21 43 70 55)(font "Arial" )) 276 | (line (pt 0 48)(pt 16 48)) 277 | ) 278 | (port 279 | (pt 0 64) 280 | (input) 281 | (text "state[3..0]" (rect 0 0 50 12)(font "Arial" )) 282 | (text "state[3..0]" (rect 21 59 71 71)(font "Arial" )) 283 | (line (pt 0 64)(pt 16 64)(line_width 3)) 284 | ) 285 | (port 286 | (pt 0 80) 287 | (input) 288 | (text "key[3..0]" (rect 0 0 44 12)(font "Arial" )) 289 | (text "key[3..0]" (rect 21 75 65 87)(font "Arial" )) 290 | (line (pt 0 80)(pt 16 80)(line_width 3)) 291 | ) 292 | (port 293 | (pt 176 32) 294 | (output) 295 | (text "led[23..0]" (rect 0 0 46 12)(font "Arial" )) 296 | (text "led[23..0]" (rect 106 27 152 39)(font "Arial" )) 297 | (line (pt 176 32)(pt 160 32)(line_width 3)) 298 | ) 299 | (parameter 300 | "Yellow_Count" 301 | "20000" 302 | "" 303 | (type "PARAMETER_SIGNED_DEC") ) 304 | (drawing 305 | (rectangle (rect 16 16 160 96)) 306 | ) 307 | (annotation_block (parameter)(rect 528 56 728 88)) 308 | ) 309 | (symbol 310 | (rect 1000 264 1192 472) 311 | (text "state_trans_model" (rect 5 0 95 12)(font "Arial" )) 312 | (text "inst2" (rect 8 192 31 204)(font "Arial" )) 313 | (port 314 | (pt 0 32) 315 | (input) 316 | (text "sys_clk" (rect 0 0 38 12)(font "Arial" )) 317 | (text "sys_clk" (rect 21 27 59 39)(font "Arial" )) 318 | (line (pt 0 32)(pt 16 32)) 319 | ) 320 | (port 321 | (pt 0 48) 322 | (input) 323 | (text "sys_rst_n" (rect 0 0 49 12)(font "Arial" )) 324 | (text "sys_rst_n" (rect 21 43 70 55)(font "Arial" )) 325 | (line (pt 0 48)(pt 16 48)) 326 | ) 327 | (port 328 | (pt 192 32) 329 | (output) 330 | (text "state[3..0]" (rect 0 0 50 12)(font "Arial" )) 331 | (text "state[3..0]" (rect 119 27 169 39)(font "Arial" )) 332 | (line (pt 192 32)(pt 176 32)(line_width 3)) 333 | ) 334 | (port 335 | (pt 192 48) 336 | (output) 337 | (text "n_time[9..0]" (rect 0 0 59 12)(font "Arial" )) 338 | (text "n_time[9..0]" (rect 108 43 167 55)(font "Arial" )) 339 | (line (pt 192 48)(pt 176 48)(line_width 3)) 340 | ) 341 | (port 342 | (pt 192 64) 343 | (output) 344 | (text "e_time[9..0]" (rect 0 0 59 12)(font "Arial" )) 345 | (text "e_time[9..0]" (rect 108 59 167 71)(font "Arial" )) 346 | (line (pt 192 64)(pt 176 64)(line_width 3)) 347 | ) 348 | (port 349 | (pt 192 80) 350 | (output) 351 | (text "s_time[9..0]" (rect 0 0 59 12)(font "Arial" )) 352 | (text "s_time[9..0]" (rect 108 75 167 87)(font "Arial" )) 353 | (line (pt 192 80)(pt 176 80)(line_width 3)) 354 | ) 355 | (port 356 | (pt 192 96) 357 | (output) 358 | (text "w_time[9..0]" (rect 0 0 60 12)(font "Arial" )) 359 | (text "w_time[9..0]" (rect 106 91 166 103)(font "Arial" )) 360 | (line (pt 192 96)(pt 176 96)(line_width 3)) 361 | ) 362 | (port 363 | (pt 192 112) 364 | (output) 365 | (text "nl_time[9..0]" (rect 0 0 61 12)(font "Arial" )) 366 | (text "nl_time[9..0]" (rect 105 107 166 119)(font "Arial" )) 367 | (line (pt 192 112)(pt 176 112)(line_width 3)) 368 | ) 369 | (port 370 | (pt 192 128) 371 | (output) 372 | (text "el_time[9..0]" (rect 0 0 61 12)(font "Arial" )) 373 | (text "el_time[9..0]" (rect 105 123 166 135)(font "Arial" )) 374 | (line (pt 192 128)(pt 176 128)(line_width 3)) 375 | ) 376 | (port 377 | (pt 192 144) 378 | (output) 379 | (text "sl_time[9..0]" (rect 0 0 61 12)(font "Arial" )) 380 | (text "sl_time[9..0]" (rect 105 139 166 151)(font "Arial" )) 381 | (line (pt 192 144)(pt 176 144)(line_width 3)) 382 | ) 383 | (port 384 | (pt 192 160) 385 | (output) 386 | (text "wl_time[9..0]" (rect 0 0 62 12)(font "Arial" )) 387 | (text "wl_time[9..0]" (rect 103 155 165 167)(font "Arial" )) 388 | (line (pt 192 160)(pt 176 160)(line_width 3)) 389 | ) 390 | (parameter 391 | "TIME_LED_NSY" 392 | "3" 393 | "" 394 | (type "PARAMETER_SIGNED_DEC") ) 395 | (parameter 396 | "TIME_LED_NSR" 397 | "60" 398 | "" 399 | (type "PARAMETER_SIGNED_DEC") ) 400 | (parameter 401 | "TIME_LED_NSG" 402 | "27" 403 | "" 404 | (type "PARAMETER_SIGNED_DEC") ) 405 | (parameter 406 | "TIME_LED_WEY" 407 | "3" 408 | "" 409 | (type "PARAMETER_SIGNED_DEC") ) 410 | (parameter 411 | "TIME_LED_WER" 412 | "60" 413 | "" 414 | (type "PARAMETER_SIGNED_DEC") ) 415 | (parameter 416 | "TIME_LED_WEG" 417 | "27" 418 | "" 419 | (type "PARAMETER_SIGNED_DEC") ) 420 | (parameter 421 | "WIDTH" 422 | "25000000" 423 | "" 424 | (type "PARAMETER_SIGNED_DEC") ) 425 | (drawing 426 | (rectangle (rect 16 16 176 192)) 427 | ) 428 | (annotation_block (parameter)(rect 1000 112 1264 240)) 429 | ) 430 | (symbol 431 | (rect 528 312 728 424) 432 | (text "traffic_led" (rect 5 0 55 12)(font "Arial" )) 433 | (text "inst3" (rect 8 96 31 108)(font "Arial" )) 434 | (port 435 | (pt 0 32) 436 | (input) 437 | (text "sys_clk" (rect 0 0 38 12)(font "Arial" )) 438 | (text "sys_clk" (rect 21 27 59 39)(font "Arial" )) 439 | (line (pt 0 32)(pt 16 32)) 440 | ) 441 | (port 442 | (pt 0 48) 443 | (input) 444 | (text "sys_rst_n" (rect 0 0 49 12)(font "Arial" )) 445 | (text "sys_rst_n" (rect 21 43 70 55)(font "Arial" )) 446 | (line (pt 0 48)(pt 16 48)) 447 | ) 448 | (port 449 | (pt 0 64) 450 | (input) 451 | (text "key[3..0]" (rect 0 0 44 12)(font "Arial" )) 452 | (text "key[3..0]" (rect 21 59 65 71)(font "Arial" )) 453 | (line (pt 0 64)(pt 16 64)(line_width 3)) 454 | ) 455 | (port 456 | (pt 200 32) 457 | (output) 458 | (text "bit[7..0]" (rect 0 0 37 12)(font "Arial" )) 459 | (text "bit[7..0]" (rect 141 27 178 39)(font "Arial" )) 460 | (line (pt 200 32)(pt 184 32)(line_width 3)) 461 | ) 462 | (port 463 | (pt 200 48) 464 | (output) 465 | (text "segment[7..0]" (rect 0 0 68 12)(font "Arial" )) 466 | (text "segment[7..0]" (rect 105 43 173 55)(font "Arial" )) 467 | (line (pt 200 48)(pt 184 48)(line_width 3)) 468 | ) 469 | (port 470 | (pt 200 64) 471 | (output) 472 | (text "led[23..0]" (rect 0 0 46 12)(font "Arial" )) 473 | (text "led[23..0]" (rect 130 59 176 71)(font "Arial" )) 474 | (line (pt 200 64)(pt 184 64)(line_width 3)) 475 | ) 476 | (drawing 477 | (rectangle (rect 16 16 184 96)) 478 | ) 479 | ) 480 | (connector 481 | (pt 224 208) 482 | (pt 280 208) 483 | ) 484 | (connector 485 | (pt 280 160) 486 | (pt 280 208) 487 | ) 488 | (connector 489 | (pt 440 144) 490 | (pt 528 144) 491 | ) 492 | (connector 493 | (pt 280 160) 494 | (pt 528 160) 495 | ) 496 | (connector 497 | (pt 480 176) 498 | (pt 528 176) 499 | (bus) 500 | ) 501 | (connector 502 | (pt 320 192) 503 | (pt 528 192) 504 | (bus) 505 | ) 506 | (connector 507 | (pt 480 176) 508 | (pt 480 232) 509 | (bus) 510 | ) 511 | (connector 512 | (pt 320 192) 513 | (pt 320 376) 514 | (bus) 515 | ) 516 | (connector 517 | (pt 440 344) 518 | (pt 528 344) 519 | ) 520 | (connector 521 | (pt 280 360) 522 | (pt 528 360) 523 | ) 524 | (connector 525 | (pt 216 376) 526 | (pt 320 376) 527 | (bus) 528 | ) 529 | (connector 530 | (pt 320 376) 531 | (pt 528 376) 532 | (bus) 533 | ) 534 | (connector 535 | (pt 280 208) 536 | (pt 280 256) 537 | ) 538 | (connector 539 | (pt 280 256) 540 | (pt 280 360) 541 | ) 542 | (connector 543 | (pt 704 144) 544 | (pt 792 144) 545 | (bus) 546 | ) 547 | (connector 548 | (pt 792 144) 549 | (pt 792 376) 550 | (bus) 551 | ) 552 | (connector 553 | (pt 1616 496) 554 | (pt 760 496) 555 | (bus) 556 | ) 557 | (connector 558 | (pt 760 496) 559 | (pt 760 344) 560 | (bus) 561 | ) 562 | (connector 563 | (pt 760 344) 564 | (pt 728 344) 565 | (bus) 566 | ) 567 | (connector 568 | (pt 728 360) 569 | (pt 776 360) 570 | (bus) 571 | ) 572 | (connector 573 | (pt 776 360) 574 | (pt 776 480) 575 | (bus) 576 | ) 577 | (connector 578 | (pt 776 480) 579 | (pt 1600 480) 580 | (bus) 581 | ) 582 | (connector 583 | (pt 1616 496) 584 | (pt 1616 -40) 585 | (bus) 586 | ) 587 | (connector 588 | (pt 1600 480) 589 | (pt 1600 -24) 590 | (bus) 591 | ) 592 | (connector 593 | (pt 440 -40) 594 | (pt 1360 -40) 595 | ) 596 | (connector 597 | (pt 1224 -8) 598 | (pt 1360 -8) 599 | (bus) 600 | ) 601 | (connector 602 | (pt 1240 8) 603 | (pt 1360 8) 604 | (bus) 605 | ) 606 | (connector 607 | (pt 1256 24) 608 | (pt 1360 24) 609 | (bus) 610 | ) 611 | (connector 612 | (pt 1272 40) 613 | (pt 1360 40) 614 | (bus) 615 | ) 616 | (connector 617 | (pt 480 232) 618 | (pt 1192 232) 619 | (bus) 620 | ) 621 | (connector 622 | (pt 832 256) 623 | (pt 832 312) 624 | ) 625 | (connector 626 | (pt 1192 232) 627 | (pt 1192 296) 628 | (bus) 629 | ) 630 | (connector 631 | (pt 1224 -8) 632 | (pt 1224 312) 633 | (bus) 634 | ) 635 | (connector 636 | (pt 1240 8) 637 | (pt 1240 328) 638 | (bus) 639 | ) 640 | (connector 641 | (pt 1256 24) 642 | (pt 1256 344) 643 | (bus) 644 | ) 645 | (connector 646 | (pt 1272 40) 647 | (pt 1272 360) 648 | (bus) 649 | ) 650 | (connector 651 | (pt 440 296) 652 | (pt 1000 296) 653 | ) 654 | (connector 655 | (pt 832 312) 656 | (pt 1000 312) 657 | ) 658 | (connector 659 | (pt 280 256) 660 | (pt 832 256) 661 | ) 662 | (connector 663 | (pt 832 256) 664 | (pt 920 256) 665 | ) 666 | (connector 667 | (pt 440 296) 668 | (pt 440 344) 669 | ) 670 | (connector 671 | (pt 1192 312) 672 | (pt 1224 312) 673 | (bus) 674 | ) 675 | (connector 676 | (pt 1192 328) 677 | (pt 1240 328) 678 | (bus) 679 | ) 680 | (connector 681 | (pt 1192 344) 682 | (pt 1256 344) 683 | (bus) 684 | ) 685 | (connector 686 | (pt 1192 360) 687 | (pt 1272 360) 688 | (bus) 689 | ) 690 | (connector 691 | (pt 1192 376) 692 | (pt 1272 376) 693 | (bus) 694 | ) 695 | (connector 696 | (pt 1192 392) 697 | (pt 1272 392) 698 | (bus) 699 | ) 700 | (connector 701 | (pt 1192 408) 702 | (pt 1272 408) 703 | (bus) 704 | ) 705 | (connector 706 | (pt 1192 424) 707 | (pt 1272 424) 708 | (bus) 709 | ) 710 | (connector 711 | (pt 1568 -40) 712 | (pt 1616 -40) 713 | (bus) 714 | ) 715 | (connector 716 | (pt 1616 -40) 717 | (pt 1648 -40) 718 | (bus) 719 | ) 720 | (connector 721 | (pt 1568 -24) 722 | (pt 1600 -24) 723 | (bus) 724 | ) 725 | (connector 726 | (pt 1600 -24) 727 | (pt 1648 -24) 728 | (bus) 729 | ) 730 | (connector 731 | (pt 728 376) 732 | (pt 792 376) 733 | (bus) 734 | ) 735 | (connector 736 | (pt 792 376) 737 | (pt 824 376) 738 | (bus) 739 | ) 740 | (connector 741 | (pt 920 256) 742 | (pt 920 -72) 743 | ) 744 | (connector 745 | (pt 1352 -24) 746 | (pt 1352 -72) 747 | ) 748 | (connector 749 | (pt 1360 -24) 750 | (pt 1352 -24) 751 | ) 752 | (connector 753 | (pt 1352 -72) 754 | (pt 920 -72) 755 | ) 756 | (connector 757 | (pt 440 136) 758 | (pt 224 136) 759 | ) 760 | (connector 761 | (pt 440 144) 762 | (pt 440 296) 763 | ) 764 | (connector 765 | (pt 440 -40) 766 | (pt 440 136) 767 | ) 768 | (connector 769 | (pt 440 136) 770 | (pt 440 144) 771 | ) 772 | (junction (pt 440 144)) 773 | (junction (pt 280 208)) 774 | (junction (pt 280 256)) 775 | (junction (pt 832 256)) 776 | (junction (pt 440 296)) 777 | (junction (pt 320 376)) 778 | (junction (pt 792 376)) 779 | (junction (pt 1616 -40)) 780 | (junction (pt 1600 -24)) 781 | (junction (pt 440 136)) 782 | -------------------------------------------------------------------------------- /db/traffic_led.cmp.logdb: -------------------------------------------------------------------------------- 1 | v1 2 | IO_RULES,NUM_PINS_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000001,Capacity Checks,Number of pins in an I/O bank should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,, 3 | IO_RULES,NUM_CLKS_NOT_EXCEED_CLKS_AVAILABLE,INAPPLICABLE,IO_000002,Capacity Checks,Number of clocks in an I/O bank should not exceed the number of clocks available.,Critical,No Global Signal assignments found.,,I/O,, 4 | IO_RULES,NUM_VREF_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000003,Capacity Checks,Number of pins in a Vrefgroup should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,, 5 | IO_RULES,IO_BANK_SUPPORT_VCCIO,INAPPLICABLE,IO_000004,Voltage Compatibility Checks,The I/O bank should support the requested VCCIO.,Critical,No IOBANK_VCCIO assignments found.,,I/O,, 6 | IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VREF,INAPPLICABLE,IO_000005,Voltage Compatibility Checks,The I/O bank should not have competing VREF values.,Critical,No VREF I/O Standard assignments found.,,I/O,, 7 | IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VCCIO,PASS,IO_000006,Voltage Compatibility Checks,The I/O bank should not have competing VCCIO values.,Critical,0 such failures found.,,I/O,, 8 | IO_RULES,CHECK_UNAVAILABLE_LOC,PASS,IO_000007,Valid Location Checks,Checks for unavailable locations.,Critical,0 such failures found.,,I/O,, 9 | IO_RULES,CHECK_RESERVED_LOC,INAPPLICABLE,IO_000008,Valid Location Checks,Checks for reserved locations.,Critical,No reserved LogicLock region found.,,I/O,, 10 | IO_RULES,LOC_SUPPORT_IO_STD,PASS,IO_000009,I/O Properties Checks for One I/O,The location should support the requested I/O standard.,Critical,0 such failures found.,,I/O,, 11 | IO_RULES,LOC_SUPPORT_IO_DIR,PASS,IO_000010,I/O Properties Checks for One I/O,The location should support the requested I/O direction.,Critical,0 such failures found.,,I/O,, 12 | IO_RULES,LOC_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000011,I/O Properties Checks for One I/O,The location should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,, 13 | IO_RULES,LOC_SUPPORT_OCT_VALUE,PASS,IO_000012,I/O Properties Checks for One I/O,The location should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,, 14 | IO_RULES,LOC_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000013,I/O Properties Checks for One I/O,The location should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,, 15 | IO_RULES,LOC_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000014,I/O Properties Checks for One I/O,The location should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,, 16 | IO_RULES,LOC_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000015,I/O Properties Checks for One I/O,The location should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,, 17 | IO_RULES,IO_STD_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000018,I/O Properties Checks for One I/O,The I/O standard should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,, 18 | IO_RULES,IO_STD_SUPPORT_OCT_VALUE,PASS,IO_000019,I/O Properties Checks for One I/O,The I/O standard should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,, 19 | IO_RULES,IO_STD_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000020,I/O Properties Checks for One I/O,The I/O standard should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,, 20 | IO_RULES,IO_STD_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000021,I/O Properties Checks for One I/O,The I/O standard should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,, 21 | IO_RULES,IO_STD_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000022,I/O Properties Checks for One I/O,The I/O standard should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,, 22 | IO_RULES,IO_STD_SUPPORT_OPEN_DRAIN_VALUE,INAPPLICABLE,IO_000023,I/O Properties Checks for One I/O,The I/O standard should support the Open Drain value.,Critical,No open drain assignments found.,,I/O,, 23 | IO_RULES,IO_DIR_SUPPORT_OCT_VALUE,PASS,IO_000024,I/O Properties Checks for One I/O,The I/O direction should support the On Chip Termination value.,Critical,0 such failures found.,,I/O,, 24 | IO_RULES,OCT_AND_CURRENT_STRENGTH_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000026,I/O Properties Checks for One I/O,On Chip Termination and Current Strength should not be used at the same time.,Critical,No Current Strength assignments found.,,I/O,, 25 | IO_RULES,WEAK_PULL_UP_AND_BUS_HOLD_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000027,I/O Properties Checks for One I/O,Weak Pull Up and Bus Hold should not be used at the same time.,Critical,No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found.,,I/O,, 26 | IO_RULES,IO_STD_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000045,I/O Properties Checks for One I/O,The I/O standard should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,, 27 | IO_RULES,LOC_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000046,I/O Properties Checks for One I/O,The location should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,, 28 | IO_RULES,OCT_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000047,I/O Properties Checks for One I/O,On Chip Termination and Slew Rate should not be used at the same time.,Critical,No Slew Rate assignments found.,,I/O,, 29 | IO_RULES,CURRENT_DENSITY_FOR_CONSECUTIVE_IO_NOT_EXCEED_CURRENT_VALUE,PASS,IO_000033,Electromigration Checks,Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os.,Critical,0 such failures found.,,I/O,, 30 | IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 5 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,, 31 | IO_RULES,MAX_20_OUTPUTS_ALLOWED_IN_VREFGROUP,INAPPLICABLE,IO_000042,SI Related SSO Limit Checks,No more than 20 outputs are allowed in a VREF group when VREF is being read from.,High,No VREF I/O Standard assignments found.,,I/O,, 32 | IO_RULES,DEV_IO_RULE_OCT_DISCLAIMER,,,,,,,,,, 33 | IO_RULES_MATRIX,Pin/Rules,IO_000001;IO_000002;IO_000003;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000009;IO_000010;IO_000011;IO_000012;IO_000013;IO_000014;IO_000015;IO_000018;IO_000019;IO_000020;IO_000021;IO_000022;IO_000023;IO_000024;IO_000026;IO_000027;IO_000045;IO_000046;IO_000047;IO_000033;IO_000034;IO_000042, 34 | IO_RULES_MATRIX,Total Pass,22;0;22;0;0;46;22;0;46;46;0;40;0;0;6;0;40;6;0;0;0;40;0;0;0;0;0;46;0;0, 35 | IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0, 36 | IO_RULES_MATRIX,Total Inapplicable,24;46;24;46;46;0;24;46;0;0;46;6;46;46;40;46;6;40;46;46;46;6;46;46;46;46;46;0;46;46, 37 | IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0, 38 | IO_RULES_MATRIX,key[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, 39 | IO_RULES_MATRIX,bit[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, 40 | IO_RULES_MATRIX,bit[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, 41 | IO_RULES_MATRIX,bit[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, 42 | IO_RULES_MATRIX,bit[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, 43 | IO_RULES_MATRIX,bit[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, 44 | IO_RULES_MATRIX,bit[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, 45 | IO_RULES_MATRIX,bit[6],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, 46 | IO_RULES_MATRIX,bit[7],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, 47 | IO_RULES_MATRIX,segment[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, 48 | IO_RULES_MATRIX,segment[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, 49 | IO_RULES_MATRIX,segment[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, 50 | IO_RULES_MATRIX,segment[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, 51 | IO_RULES_MATRIX,segment[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, 52 | IO_RULES_MATRIX,segment[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, 53 | IO_RULES_MATRIX,segment[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, 54 | IO_RULES_MATRIX,segment[7],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, 55 | IO_RULES_MATRIX,led[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, 56 | IO_RULES_MATRIX,led[1],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, 57 | IO_RULES_MATRIX,led[2],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, 58 | IO_RULES_MATRIX,led[3],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, 59 | IO_RULES_MATRIX,led[4],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, 60 | IO_RULES_MATRIX,led[5],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, 61 | IO_RULES_MATRIX,led[6],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, 62 | IO_RULES_MATRIX,led[7],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, 63 | IO_RULES_MATRIX,led[8],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, 64 | IO_RULES_MATRIX,led[9],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, 65 | IO_RULES_MATRIX,led[10],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, 66 | IO_RULES_MATRIX,led[11],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, 67 | IO_RULES_MATRIX,led[12],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, 68 | IO_RULES_MATRIX,led[13],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, 69 | IO_RULES_MATRIX,led[14],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, 70 | IO_RULES_MATRIX,led[15],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, 71 | IO_RULES_MATRIX,led[16],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, 72 | IO_RULES_MATRIX,led[17],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, 73 | IO_RULES_MATRIX,led[18],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, 74 | IO_RULES_MATRIX,led[19],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, 75 | IO_RULES_MATRIX,led[20],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, 76 | IO_RULES_MATRIX,led[21],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, 77 | IO_RULES_MATRIX,led[22],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, 78 | IO_RULES_MATRIX,led[23],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, 79 | IO_RULES_MATRIX,sys_clk,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, 80 | IO_RULES_MATRIX,sys_rst_n,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, 81 | IO_RULES_MATRIX,key[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, 82 | IO_RULES_MATRIX,key[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, 83 | IO_RULES_MATRIX,key[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, 84 | IO_RULES_SUMMARY,Total I/O Rules,30, 85 | IO_RULES_SUMMARY,Number of I/O Rules Passed,12, 86 | IO_RULES_SUMMARY,Number of I/O Rules Failed,0, 87 | IO_RULES_SUMMARY,Number of I/O Rules Unchecked,0, 88 | IO_RULES_SUMMARY,Number of I/O Rules Inapplicable,18, 89 | -------------------------------------------------------------------------------- /db/traffic_led.hier_info: -------------------------------------------------------------------------------- 1 | |traffic_led 2 | sys_clk => sys_clk.IN3 3 | sys_rst_n => sys_rst_n.IN3 4 | key[0] => key[0].IN1 5 | key[1] => key[1].IN1 6 | key[2] => key[2].IN1 7 | key[3] => key[3].IN1 8 | bit[0] << bit_seg_module:u1_bit_seg_module.bit 9 | bit[1] << bit_seg_module:u1_bit_seg_module.bit 10 | bit[2] << bit_seg_module:u1_bit_seg_module.bit 11 | bit[3] << bit_seg_module:u1_bit_seg_module.bit 12 | bit[4] << bit_seg_module:u1_bit_seg_module.bit 13 | bit[5] << bit_seg_module:u1_bit_seg_module.bit 14 | bit[6] << bit_seg_module:u1_bit_seg_module.bit 15 | bit[7] << bit_seg_module:u1_bit_seg_module.bit 16 | segment[0] << bit_seg_module:u1_bit_seg_module.segment 17 | segment[1] << bit_seg_module:u1_bit_seg_module.segment 18 | segment[2] << bit_seg_module:u1_bit_seg_module.segment 19 | segment[3] << bit_seg_module:u1_bit_seg_module.segment 20 | segment[4] << bit_seg_module:u1_bit_seg_module.segment 21 | segment[5] << bit_seg_module:u1_bit_seg_module.segment 22 | segment[6] << bit_seg_module:u1_bit_seg_module.segment 23 | segment[7] << bit_seg_module:u1_bit_seg_module.segment 24 | led[0] << led_module:u2_led_module.led 25 | led[1] << led_module:u2_led_module.led 26 | led[2] << led_module:u2_led_module.led 27 | led[3] << led_module:u2_led_module.led 28 | led[4] << led_module:u2_led_module.led 29 | led[5] << led_module:u2_led_module.led 30 | led[6] << led_module:u2_led_module.led 31 | led[7] << led_module:u2_led_module.led 32 | led[8] << led_module:u2_led_module.led 33 | led[9] << led_module:u2_led_module.led 34 | led[10] << led_module:u2_led_module.led 35 | led[11] << led_module:u2_led_module.led 36 | led[12] << led_module:u2_led_module.led 37 | led[13] << led_module:u2_led_module.led 38 | led[14] << led_module:u2_led_module.led 39 | led[15] << led_module:u2_led_module.led 40 | led[16] << led_module:u2_led_module.led 41 | led[17] << led_module:u2_led_module.led 42 | led[18] << led_module:u2_led_module.led 43 | led[19] << led_module:u2_led_module.led 44 | led[20] << led_module:u2_led_module.led 45 | led[21] << led_module:u2_led_module.led 46 | led[22] << led_module:u2_led_module.led 47 | led[23] << led_module:u2_led_module.led 48 | 49 | 50 | |traffic_led|state_trans_model:u0_state_trans_model 51 | sys_clk => clk_t.CLK 52 | sys_clk => t_count[0].CLK 53 | sys_clk => t_count[1].CLK 54 | sys_clk => t_count[2].CLK 55 | sys_clk => t_count[3].CLK 56 | sys_clk => t_count[4].CLK 57 | sys_clk => t_count[5].CLK 58 | sys_clk => t_count[6].CLK 59 | sys_clk => t_count[7].CLK 60 | sys_clk => t_count[8].CLK 61 | sys_clk => t_count[9].CLK 62 | sys_clk => t_count[10].CLK 63 | sys_clk => t_count[11].CLK 64 | sys_clk => t_count[12].CLK 65 | sys_clk => t_count[13].CLK 66 | sys_clk => t_count[14].CLK 67 | sys_clk => t_count[15].CLK 68 | sys_clk => t_count[16].CLK 69 | sys_clk => t_count[17].CLK 70 | sys_clk => t_count[18].CLK 71 | sys_clk => t_count[19].CLK 72 | sys_clk => t_count[20].CLK 73 | sys_clk => t_count[21].CLK 74 | sys_clk => t_count[22].CLK 75 | sys_clk => t_count[23].CLK 76 | sys_clk => t_count[24].CLK 77 | sys_rst_n => time_cnt[0].PRESET 78 | sys_rst_n => time_cnt[1].PRESET 79 | sys_rst_n => time_cnt[2].ACLR 80 | sys_rst_n => time_cnt[3].PRESET 81 | sys_rst_n => time_cnt[4].PRESET 82 | sys_rst_n => time_cnt[5].ACLR 83 | sys_rst_n => state[0]~reg0.ACLR 84 | sys_rst_n => state[1]~reg0.ACLR 85 | sys_rst_n => state[2]~reg0.ACLR 86 | sys_rst_n => state[3]~reg0.ACLR 87 | sys_rst_n => clk_t.ACLR 88 | sys_rst_n => t_count[0].ACLR 89 | sys_rst_n => t_count[1].ACLR 90 | sys_rst_n => t_count[2].ACLR 91 | sys_rst_n => t_count[3].ACLR 92 | sys_rst_n => t_count[4].ACLR 93 | sys_rst_n => t_count[5].ACLR 94 | sys_rst_n => t_count[6].ACLR 95 | sys_rst_n => t_count[7].ACLR 96 | sys_rst_n => t_count[8].ACLR 97 | sys_rst_n => t_count[9].ACLR 98 | sys_rst_n => t_count[10].ACLR 99 | sys_rst_n => t_count[11].ACLR 100 | sys_rst_n => t_count[12].ACLR 101 | sys_rst_n => t_count[13].ACLR 102 | sys_rst_n => t_count[14].ACLR 103 | sys_rst_n => t_count[15].ACLR 104 | sys_rst_n => t_count[16].ACLR 105 | sys_rst_n => t_count[17].ACLR 106 | sys_rst_n => t_count[18].ACLR 107 | sys_rst_n => t_count[19].ACLR 108 | sys_rst_n => t_count[20].ACLR 109 | sys_rst_n => t_count[21].ACLR 110 | sys_rst_n => t_count[22].ACLR 111 | sys_rst_n => t_count[23].ACLR 112 | sys_rst_n => t_count[24].ACLR 113 | sys_rst_n => wl_time[0]~reg0.ENA 114 | sys_rst_n => n_time[9]~reg0.ENA 115 | sys_rst_n => n_time[8]~reg0.ENA 116 | sys_rst_n => n_time[7]~reg0.ENA 117 | sys_rst_n => n_time[6]~reg0.ENA 118 | sys_rst_n => n_time[5]~reg0.ENA 119 | sys_rst_n => n_time[4]~reg0.ENA 120 | sys_rst_n => n_time[3]~reg0.ENA 121 | sys_rst_n => n_time[2]~reg0.ENA 122 | sys_rst_n => n_time[1]~reg0.ENA 123 | sys_rst_n => n_time[0]~reg0.ENA 124 | sys_rst_n => e_time[9]~reg0.ENA 125 | sys_rst_n => e_time[8]~reg0.ENA 126 | sys_rst_n => e_time[7]~reg0.ENA 127 | sys_rst_n => e_time[6]~reg0.ENA 128 | sys_rst_n => e_time[5]~reg0.ENA 129 | sys_rst_n => e_time[4]~reg0.ENA 130 | sys_rst_n => e_time[3]~reg0.ENA 131 | sys_rst_n => e_time[2]~reg0.ENA 132 | sys_rst_n => e_time[1]~reg0.ENA 133 | sys_rst_n => e_time[0]~reg0.ENA 134 | sys_rst_n => s_time[9]~reg0.ENA 135 | sys_rst_n => s_time[8]~reg0.ENA 136 | sys_rst_n => s_time[7]~reg0.ENA 137 | sys_rst_n => s_time[6]~reg0.ENA 138 | sys_rst_n => s_time[5]~reg0.ENA 139 | sys_rst_n => s_time[4]~reg0.ENA 140 | sys_rst_n => s_time[3]~reg0.ENA 141 | sys_rst_n => s_time[2]~reg0.ENA 142 | sys_rst_n => s_time[1]~reg0.ENA 143 | sys_rst_n => s_time[0]~reg0.ENA 144 | sys_rst_n => w_time[9]~reg0.ENA 145 | sys_rst_n => w_time[8]~reg0.ENA 146 | sys_rst_n => w_time[7]~reg0.ENA 147 | sys_rst_n => w_time[6]~reg0.ENA 148 | sys_rst_n => w_time[5]~reg0.ENA 149 | sys_rst_n => w_time[4]~reg0.ENA 150 | sys_rst_n => w_time[3]~reg0.ENA 151 | sys_rst_n => w_time[2]~reg0.ENA 152 | sys_rst_n => w_time[1]~reg0.ENA 153 | sys_rst_n => w_time[0]~reg0.ENA 154 | sys_rst_n => nl_time[9]~reg0.ENA 155 | sys_rst_n => nl_time[8]~reg0.ENA 156 | sys_rst_n => nl_time[7]~reg0.ENA 157 | sys_rst_n => nl_time[6]~reg0.ENA 158 | sys_rst_n => nl_time[5]~reg0.ENA 159 | sys_rst_n => nl_time[4]~reg0.ENA 160 | sys_rst_n => nl_time[3]~reg0.ENA 161 | sys_rst_n => nl_time[2]~reg0.ENA 162 | sys_rst_n => nl_time[1]~reg0.ENA 163 | sys_rst_n => nl_time[0]~reg0.ENA 164 | sys_rst_n => el_time[9]~reg0.ENA 165 | sys_rst_n => el_time[8]~reg0.ENA 166 | sys_rst_n => el_time[7]~reg0.ENA 167 | sys_rst_n => el_time[6]~reg0.ENA 168 | sys_rst_n => el_time[5]~reg0.ENA 169 | sys_rst_n => el_time[4]~reg0.ENA 170 | sys_rst_n => el_time[3]~reg0.ENA 171 | sys_rst_n => el_time[2]~reg0.ENA 172 | sys_rst_n => el_time[1]~reg0.ENA 173 | sys_rst_n => el_time[0]~reg0.ENA 174 | sys_rst_n => sl_time[9]~reg0.ENA 175 | sys_rst_n => sl_time[8]~reg0.ENA 176 | sys_rst_n => sl_time[7]~reg0.ENA 177 | sys_rst_n => sl_time[6]~reg0.ENA 178 | sys_rst_n => sl_time[5]~reg0.ENA 179 | sys_rst_n => sl_time[4]~reg0.ENA 180 | sys_rst_n => sl_time[3]~reg0.ENA 181 | sys_rst_n => sl_time[2]~reg0.ENA 182 | sys_rst_n => sl_time[1]~reg0.ENA 183 | sys_rst_n => sl_time[0]~reg0.ENA 184 | sys_rst_n => wl_time[9]~reg0.ENA 185 | sys_rst_n => wl_time[8]~reg0.ENA 186 | sys_rst_n => wl_time[7]~reg0.ENA 187 | sys_rst_n => wl_time[6]~reg0.ENA 188 | sys_rst_n => wl_time[5]~reg0.ENA 189 | sys_rst_n => wl_time[4]~reg0.ENA 190 | sys_rst_n => wl_time[3]~reg0.ENA 191 | sys_rst_n => wl_time[2]~reg0.ENA 192 | sys_rst_n => wl_time[1]~reg0.ENA 193 | state[0] <= state[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE 194 | state[1] <= state[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE 195 | state[2] <= state[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE 196 | state[3] <= state[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE 197 | n_time[0] <= n_time[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE 198 | n_time[1] <= n_time[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE 199 | n_time[2] <= n_time[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE 200 | n_time[3] <= n_time[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE 201 | n_time[4] <= n_time[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE 202 | n_time[5] <= n_time[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE 203 | n_time[6] <= n_time[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE 204 | n_time[7] <= n_time[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE 205 | n_time[8] <= n_time[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE 206 | n_time[9] <= n_time[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE 207 | e_time[0] <= e_time[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE 208 | e_time[1] <= e_time[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE 209 | e_time[2] <= e_time[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE 210 | e_time[3] <= e_time[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE 211 | e_time[4] <= e_time[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE 212 | e_time[5] <= e_time[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE 213 | e_time[6] <= e_time[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE 214 | e_time[7] <= e_time[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE 215 | e_time[8] <= e_time[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE 216 | e_time[9] <= e_time[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE 217 | s_time[0] <= s_time[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE 218 | s_time[1] <= s_time[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE 219 | s_time[2] <= s_time[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE 220 | s_time[3] <= s_time[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE 221 | s_time[4] <= s_time[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE 222 | s_time[5] <= s_time[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE 223 | s_time[6] <= s_time[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE 224 | s_time[7] <= s_time[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE 225 | s_time[8] <= s_time[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE 226 | s_time[9] <= s_time[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE 227 | w_time[0] <= w_time[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE 228 | w_time[1] <= w_time[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE 229 | w_time[2] <= w_time[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE 230 | w_time[3] <= w_time[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE 231 | w_time[4] <= w_time[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE 232 | w_time[5] <= w_time[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE 233 | w_time[6] <= w_time[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE 234 | w_time[7] <= w_time[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE 235 | w_time[8] <= w_time[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE 236 | w_time[9] <= w_time[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE 237 | nl_time[0] <= nl_time[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE 238 | nl_time[1] <= nl_time[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE 239 | nl_time[2] <= nl_time[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE 240 | nl_time[3] <= nl_time[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE 241 | nl_time[4] <= nl_time[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE 242 | nl_time[5] <= nl_time[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE 243 | nl_time[6] <= nl_time[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE 244 | nl_time[7] <= nl_time[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE 245 | nl_time[8] <= nl_time[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE 246 | nl_time[9] <= nl_time[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE 247 | el_time[0] <= el_time[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE 248 | el_time[1] <= el_time[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE 249 | el_time[2] <= el_time[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE 250 | el_time[3] <= el_time[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE 251 | el_time[4] <= el_time[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE 252 | el_time[5] <= el_time[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE 253 | el_time[6] <= el_time[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE 254 | el_time[7] <= el_time[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE 255 | el_time[8] <= el_time[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE 256 | el_time[9] <= el_time[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE 257 | sl_time[0] <= sl_time[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE 258 | sl_time[1] <= sl_time[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE 259 | sl_time[2] <= sl_time[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE 260 | sl_time[3] <= sl_time[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE 261 | sl_time[4] <= sl_time[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE 262 | sl_time[5] <= sl_time[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE 263 | sl_time[6] <= sl_time[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE 264 | sl_time[7] <= sl_time[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE 265 | sl_time[8] <= sl_time[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE 266 | sl_time[9] <= sl_time[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE 267 | wl_time[0] <= wl_time[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE 268 | wl_time[1] <= wl_time[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE 269 | wl_time[2] <= wl_time[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE 270 | wl_time[3] <= wl_time[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE 271 | wl_time[4] <= wl_time[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE 272 | wl_time[5] <= wl_time[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE 273 | wl_time[6] <= wl_time[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE 274 | wl_time[7] <= wl_time[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE 275 | wl_time[8] <= wl_time[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE 276 | wl_time[9] <= wl_time[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE 277 | 278 | 279 | |traffic_led|bit_seg_module:u1_bit_seg_module 280 | sys_clk => segment[0]~reg0.CLK 281 | sys_clk => segment[1]~reg0.CLK 282 | sys_clk => segment[2]~reg0.CLK 283 | sys_clk => segment[3]~reg0.CLK 284 | sys_clk => segment[4]~reg0.CLK 285 | sys_clk => segment[5]~reg0.CLK 286 | sys_clk => segment[6]~reg0.CLK 287 | sys_clk => segment[7]~reg0.CLK 288 | sys_clk => num[0].CLK 289 | sys_clk => num[1].CLK 290 | sys_clk => num[2].CLK 291 | sys_clk => num[3].CLK 292 | sys_clk => bit[0]~reg0.CLK 293 | sys_clk => bit[1]~reg0.CLK 294 | sys_clk => bit[2]~reg0.CLK 295 | sys_clk => bit[3]~reg0.CLK 296 | sys_clk => bit[4]~reg0.CLK 297 | sys_clk => bit[5]~reg0.CLK 298 | sys_clk => bit[6]~reg0.CLK 299 | sys_clk => bit[7]~reg0.CLK 300 | sys_clk => count_state[0].CLK 301 | sys_clk => count_state[1].CLK 302 | sys_clk => count_state[2].CLK 303 | sys_clk => count_s[0].CLK 304 | sys_clk => count_s[1].CLK 305 | sys_clk => count_s[2].CLK 306 | sys_clk => count_s[3].CLK 307 | sys_clk => count_s[4].CLK 308 | sys_clk => count_s[5].CLK 309 | sys_clk => count_s[6].CLK 310 | sys_clk => count_s[7].CLK 311 | sys_clk => count_s[8].CLK 312 | sys_clk => count_s[9].CLK 313 | sys_clk => count_s[10].CLK 314 | sys_clk => count_s[11].CLK 315 | sys_clk => count_s[12].CLK 316 | sys_clk => count_s[13].CLK 317 | sys_clk => count_s[14].CLK 318 | sys_clk => count_s[15].CLK 319 | sys_rst_n => num[0].ACLR 320 | sys_rst_n => num[1].ACLR 321 | sys_rst_n => num[2].ACLR 322 | sys_rst_n => num[3].ACLR 323 | sys_rst_n => bit[0]~reg0.PRESET 324 | sys_rst_n => bit[1]~reg0.PRESET 325 | sys_rst_n => bit[2]~reg0.PRESET 326 | sys_rst_n => bit[3]~reg0.PRESET 327 | sys_rst_n => bit[4]~reg0.PRESET 328 | sys_rst_n => bit[5]~reg0.PRESET 329 | sys_rst_n => bit[6]~reg0.PRESET 330 | sys_rst_n => bit[7]~reg0.PRESET 331 | sys_rst_n => segment[0]~reg0.ACLR 332 | sys_rst_n => segment[1]~reg0.ACLR 333 | sys_rst_n => segment[2]~reg0.ACLR 334 | sys_rst_n => segment[3]~reg0.ACLR 335 | sys_rst_n => segment[4]~reg0.ACLR 336 | sys_rst_n => segment[5]~reg0.ACLR 337 | sys_rst_n => segment[6]~reg0.ACLR 338 | sys_rst_n => segment[7]~reg0.ACLR 339 | sys_rst_n => count_s[0].ACLR 340 | sys_rst_n => count_s[1].ACLR 341 | sys_rst_n => count_s[2].ACLR 342 | sys_rst_n => count_s[3].ACLR 343 | sys_rst_n => count_s[4].ACLR 344 | sys_rst_n => count_s[5].ACLR 345 | sys_rst_n => count_s[6].ACLR 346 | sys_rst_n => count_s[7].ACLR 347 | sys_rst_n => count_s[8].ACLR 348 | sys_rst_n => count_s[9].ACLR 349 | sys_rst_n => count_s[10].ACLR 350 | sys_rst_n => count_s[11].ACLR 351 | sys_rst_n => count_s[12].ACLR 352 | sys_rst_n => count_s[13].ACLR 353 | sys_rst_n => count_s[14].ACLR 354 | sys_rst_n => count_s[15].ACLR 355 | sys_rst_n => count_state[0].ACLR 356 | sys_rst_n => count_state[1].ACLR 357 | sys_rst_n => count_state[2].ACLR 358 | n_time[0] => Div0.IN13 359 | n_time[0] => Mod0.IN13 360 | n_time[1] => Div0.IN12 361 | n_time[1] => Mod0.IN12 362 | n_time[2] => Div0.IN11 363 | n_time[2] => Mod0.IN11 364 | n_time[3] => Div0.IN10 365 | n_time[3] => Mod0.IN10 366 | n_time[4] => Div0.IN9 367 | n_time[4] => Mod0.IN9 368 | n_time[5] => Div0.IN8 369 | n_time[5] => Mod0.IN8 370 | n_time[6] => Div0.IN7 371 | n_time[6] => Mod0.IN7 372 | n_time[7] => Div0.IN6 373 | n_time[7] => Mod0.IN6 374 | n_time[8] => Div0.IN5 375 | n_time[8] => Mod0.IN5 376 | n_time[9] => Div0.IN4 377 | n_time[9] => Mod0.IN4 378 | e_time[0] => Div1.IN13 379 | e_time[0] => Mod1.IN13 380 | e_time[1] => Div1.IN12 381 | e_time[1] => Mod1.IN12 382 | e_time[2] => Div1.IN11 383 | e_time[2] => Mod1.IN11 384 | e_time[3] => Div1.IN10 385 | e_time[3] => Mod1.IN10 386 | e_time[4] => Div1.IN9 387 | e_time[4] => Mod1.IN9 388 | e_time[5] => Div1.IN8 389 | e_time[5] => Mod1.IN8 390 | e_time[6] => Div1.IN7 391 | e_time[6] => Mod1.IN7 392 | e_time[7] => Div1.IN6 393 | e_time[7] => Mod1.IN6 394 | e_time[8] => Div1.IN5 395 | e_time[8] => Mod1.IN5 396 | e_time[9] => Div1.IN4 397 | e_time[9] => Mod1.IN4 398 | s_time[0] => Div2.IN13 399 | s_time[0] => Mod2.IN13 400 | s_time[1] => Div2.IN12 401 | s_time[1] => Mod2.IN12 402 | s_time[2] => Div2.IN11 403 | s_time[2] => Mod2.IN11 404 | s_time[3] => Div2.IN10 405 | s_time[3] => Mod2.IN10 406 | s_time[4] => Div2.IN9 407 | s_time[4] => Mod2.IN9 408 | s_time[5] => Div2.IN8 409 | s_time[5] => Mod2.IN8 410 | s_time[6] => Div2.IN7 411 | s_time[6] => Mod2.IN7 412 | s_time[7] => Div2.IN6 413 | s_time[7] => Mod2.IN6 414 | s_time[8] => Div2.IN5 415 | s_time[8] => Mod2.IN5 416 | s_time[9] => Div2.IN4 417 | s_time[9] => Mod2.IN4 418 | w_time[0] => Div3.IN13 419 | w_time[0] => Mod3.IN13 420 | w_time[1] => Div3.IN12 421 | w_time[1] => Mod3.IN12 422 | w_time[2] => Div3.IN11 423 | w_time[2] => Mod3.IN11 424 | w_time[3] => Div3.IN10 425 | w_time[3] => Mod3.IN10 426 | w_time[4] => Div3.IN9 427 | w_time[4] => Mod3.IN9 428 | w_time[5] => Div3.IN8 429 | w_time[5] => Mod3.IN8 430 | w_time[6] => Div3.IN7 431 | w_time[6] => Mod3.IN7 432 | w_time[7] => Div3.IN6 433 | w_time[7] => Mod3.IN6 434 | w_time[8] => Div3.IN5 435 | w_time[8] => Mod3.IN5 436 | w_time[9] => Div3.IN4 437 | w_time[9] => Mod3.IN4 438 | en => bit.OUTPUTSELECT 439 | en => bit.OUTPUTSELECT 440 | en => bit.OUTPUTSELECT 441 | en => bit.OUTPUTSELECT 442 | en => bit.OUTPUTSELECT 443 | en => bit.OUTPUTSELECT 444 | en => bit.OUTPUTSELECT 445 | en => bit.OUTPUTSELECT 446 | en => num.OUTPUTSELECT 447 | en => num.OUTPUTSELECT 448 | en => num.OUTPUTSELECT 449 | en => num.OUTPUTSELECT 450 | bit[0] <= bit[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE 451 | bit[1] <= bit[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE 452 | bit[2] <= bit[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE 453 | bit[3] <= bit[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE 454 | bit[4] <= bit[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE 455 | bit[5] <= bit[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE 456 | bit[6] <= bit[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE 457 | bit[7] <= bit[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE 458 | segment[0] <= segment[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE 459 | segment[1] <= segment[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE 460 | segment[2] <= segment[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE 461 | segment[3] <= segment[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE 462 | segment[4] <= segment[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE 463 | segment[5] <= segment[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE 464 | segment[6] <= segment[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE 465 | segment[7] <= segment[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE 466 | 467 | 468 | |traffic_led|led_module:u2_led_module 469 | sys_clk => led[0]~reg0.CLK 470 | sys_clk => led[1]~reg0.CLK 471 | sys_clk => led[2]~reg0.CLK 472 | sys_clk => led[3]~reg0.CLK 473 | sys_clk => led[4]~reg0.CLK 474 | sys_clk => led[5]~reg0.CLK 475 | sys_clk => led[6]~reg0.CLK 476 | sys_clk => led[7]~reg0.CLK 477 | sys_clk => led[8]~reg0.CLK 478 | sys_clk => led[9]~reg0.CLK 479 | sys_clk => led[10]~reg0.CLK 480 | sys_clk => led[11]~reg0.CLK 481 | sys_clk => led[12]~reg0.CLK 482 | sys_clk => led[13]~reg0.CLK 483 | sys_clk => led[14]~reg0.CLK 484 | sys_clk => led[15]~reg0.CLK 485 | sys_clk => led[16]~reg0.CLK 486 | sys_clk => led[17]~reg0.CLK 487 | sys_clk => led[18]~reg0.CLK 488 | sys_clk => led[19]~reg0.CLK 489 | sys_clk => led[20]~reg0.CLK 490 | sys_clk => led[21]~reg0.CLK 491 | sys_clk => led[22]~reg0.CLK 492 | sys_clk => led[23]~reg0.CLK 493 | sys_rst_n => led[0]~reg0.ACLR 494 | sys_rst_n => led[1]~reg0.ACLR 495 | sys_rst_n => led[2]~reg0.PRESET 496 | sys_rst_n => led[3]~reg0.ACLR 497 | sys_rst_n => led[4]~reg0.ACLR 498 | sys_rst_n => led[5]~reg0.PRESET 499 | sys_rst_n => led[6]~reg0.ACLR 500 | sys_rst_n => led[7]~reg0.ACLR 501 | sys_rst_n => led[8]~reg0.PRESET 502 | sys_rst_n => led[9]~reg0.ACLR 503 | sys_rst_n => led[10]~reg0.ACLR 504 | sys_rst_n => led[11]~reg0.PRESET 505 | sys_rst_n => led[12]~reg0.ACLR 506 | sys_rst_n => led[13]~reg0.ACLR 507 | sys_rst_n => led[14]~reg0.PRESET 508 | sys_rst_n => led[15]~reg0.ACLR 509 | sys_rst_n => led[16]~reg0.ACLR 510 | sys_rst_n => led[17]~reg0.PRESET 511 | sys_rst_n => led[18]~reg0.ACLR 512 | sys_rst_n => led[19]~reg0.ACLR 513 | sys_rst_n => led[20]~reg0.PRESET 514 | sys_rst_n => led[21]~reg0.ACLR 515 | sys_rst_n => led[22]~reg0.ACLR 516 | sys_rst_n => led[23]~reg0.PRESET 517 | state[0] => Decoder1.IN3 518 | state[1] => Decoder0.IN2 519 | state[1] => Decoder1.IN2 520 | state[2] => Decoder0.IN1 521 | state[2] => Decoder1.IN1 522 | state[3] => Decoder0.IN0 523 | state[3] => Decoder1.IN0 524 | key[0] => led.OUTPUTSELECT 525 | key[0] => led.OUTPUTSELECT 526 | key[0] => led.OUTPUTSELECT 527 | key[0] => led.OUTPUTSELECT 528 | key[0] => led.OUTPUTSELECT 529 | key[0] => led.OUTPUTSELECT 530 | key[0] => led.OUTPUTSELECT 531 | key[0] => led.OUTPUTSELECT 532 | key[0] => led.OUTPUTSELECT 533 | key[0] => led.OUTPUTSELECT 534 | key[0] => led.OUTPUTSELECT 535 | key[0] => led.OUTPUTSELECT 536 | key[1] => led.OUTPUTSELECT 537 | key[1] => led.OUTPUTSELECT 538 | key[1] => led.OUTPUTSELECT 539 | key[1] => led.OUTPUTSELECT 540 | key[1] => led.OUTPUTSELECT 541 | key[1] => led.OUTPUTSELECT 542 | key[1] => led.OUTPUTSELECT 543 | key[1] => led.OUTPUTSELECT 544 | key[1] => led.OUTPUTSELECT 545 | key[1] => led.OUTPUTSELECT 546 | key[1] => led.OUTPUTSELECT 547 | key[1] => led.OUTPUTSELECT 548 | key[2] => led.OUTPUTSELECT 549 | key[2] => led.OUTPUTSELECT 550 | key[2] => led.OUTPUTSELECT 551 | key[2] => led.OUTPUTSELECT 552 | key[2] => led.OUTPUTSELECT 553 | key[2] => led.OUTPUTSELECT 554 | key[2] => led.OUTPUTSELECT 555 | key[2] => led.OUTPUTSELECT 556 | key[2] => led.OUTPUTSELECT 557 | key[2] => led.OUTPUTSELECT 558 | key[2] => led.OUTPUTSELECT 559 | key[2] => led.OUTPUTSELECT 560 | key[3] => ~NO_FANOUT~ 561 | led[0] <= led[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE 562 | led[1] <= led[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE 563 | led[2] <= led[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE 564 | led[3] <= led[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE 565 | led[4] <= led[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE 566 | led[5] <= led[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE 567 | led[6] <= led[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE 568 | led[7] <= led[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE 569 | led[8] <= led[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE 570 | led[9] <= led[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE 571 | led[10] <= led[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE 572 | led[11] <= led[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE 573 | led[12] <= led[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE 574 | led[13] <= led[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE 575 | led[14] <= led[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE 576 | led[15] <= led[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE 577 | led[16] <= led[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE 578 | led[17] <= led[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE 579 | led[18] <= led[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE 580 | led[19] <= led[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE 581 | led[20] <= led[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE 582 | led[21] <= led[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE 583 | led[22] <= led[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE 584 | led[23] <= led[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE 585 | 586 | 587 | --------------------------------------------------------------------------------