├── README ├── couplers ├── README ├── coupler_layout.png └── gerbers │ ├── rf_bridge_Bottom.gbl │ ├── rf_bridge_In1.g2l │ ├── rf_bridge_In2.g3l │ ├── rf_bridge_Mask.gts │ ├── rf_bridge_Mask_bottom.gbs │ ├── rf_bridge_Outline.gko │ ├── rf_bridge_Top.gtl │ └── rf_bridge_drill.drl ├── fpga ├── vna │ ├── vna.hw │ │ └── vna.lpr │ ├── vna.srcs │ │ ├── constrs_1 │ │ │ └── new │ │ │ │ └── vna_constraints.xdc │ │ ├── sim_1 │ │ │ └── new │ │ │ │ ├── comm_tb.vhd │ │ │ │ ├── ft2232_behavioral.vhd │ │ │ │ ├── io_bank_tb.vhd │ │ │ │ ├── iq_packer_tb.vhd │ │ │ │ ├── lo_sim.vhd │ │ │ │ ├── mixer_sim.vhd │ │ │ │ ├── receiver_tb.vhd │ │ │ │ ├── spi3_tb.vhd │ │ │ │ ├── spi_write_tb.vhd │ │ │ │ ├── vna_tb.vhd │ │ │ │ └── vna_top_tb.vhd │ │ └── sources_1 │ │ │ ├── imports │ │ │ └── new │ │ │ │ ├── downconvert.vhd │ │ │ │ ├── port_switch.vhd │ │ │ │ ├── sample_packer.vhd │ │ │ │ ├── spi3.vhd │ │ │ │ └── vna_top.vhd │ │ │ └── new │ │ │ ├── acc_control.vhd │ │ │ ├── accumulator.vhd │ │ │ ├── comm.vhd │ │ │ ├── dither.vhd │ │ │ ├── file_adc.vhd │ │ │ ├── io_bank.vhd │ │ │ ├── iq_packer.vhd │ │ │ ├── lfsr.vhd │ │ │ ├── lo.vhd │ │ │ ├── mixer.vhd │ │ │ ├── pwr_sync_gen.vhd │ │ │ ├── receiver.vhd │ │ │ ├── receiver_control.vhd │ │ │ ├── rx_sw_mux.vhd │ │ │ ├── rx_switch.vhd │ │ │ ├── source_agc.vhd │ │ │ ├── spi_write.vhd │ │ │ ├── tx_mux.vhd │ │ │ └── vna_pkg.vhd │ └── vna.xpr └── vna_top.bit ├── hw ├── adc.sch ├── filter_bank.sch ├── fpga.sch ├── fpga_power.sch ├── if_amp.sch ├── lib │ └── vna.lib ├── lmz30602.sch ├── microcontroller.sch ├── port_switch.sch ├── power.sch ├── receiver.sch ├── rx_lna.sch ├── rx_switch.sch ├── transmitter.sch ├── tx_amp.sch ├── usb.sch ├── vna.pretty │ ├── 1748LP18A075.kicad_mod │ ├── 3550LP14A300.kicad_mod │ ├── 5400BL15B050E.kicad_mod │ ├── 5515LP15A730.kicad_mod │ ├── ABMM.kicad_mod │ ├── ASTRX-12.kicad_mod │ ├── CNC-3220-10-0300-00.kicad_mod │ ├── CONSMA003.062.kicad_mod │ ├── CTX520.kicad_mod │ ├── C_0402b.kicad_mod │ ├── C_0603b.kicad_mod │ ├── C_0805b.kicad_mod │ ├── DFN-8-1EP_2x2mm_Pitch0.5mm.kicad_mod │ ├── DFN-8.kicad_mod │ ├── EJ508A.kicad_mod │ ├── EVP-AWBA2A.kicad_mod │ ├── FTG256.kicad_mod │ ├── KT2520K.kicad_mod │ ├── LED_0603.kicad_mod │ ├── LP0603A0902.kicad_mod │ ├── MLPD-10.kicad_mod │ ├── MSOP-8.kicad_mod │ ├── MountingHole_3.2mm_M3_Pad_Via_mod.kicad_mod │ ├── PAT1220.kicad_mod │ ├── RF_via.kicad_mod │ ├── R_0402b.kicad_mod │ ├── R_0603b.kicad_mod │ ├── S2711-46R.kicad_mod │ ├── SC-70-6.kicad_mod │ ├── SG-210STF.kicad_mod │ ├── SOD-123F.kicad_mod │ ├── SOT-23-5.kicad_mod │ ├── SOT-23-5L.kicad_mod │ ├── SOT-23-6.kicad_mod │ ├── SOT-416.kicad_mod │ ├── SRN4018.kicad_mod │ ├── SRR6040A.kicad_mod │ ├── SSOP-16.kicad_mod │ ├── SSOT-6.kicad_mod │ ├── TCM1-63AX+.kicad_mod │ ├── TFBGA-100.kicad_mod │ ├── TFLGA-20.kicad_mod │ ├── TP_1.00.kicad_mod │ ├── TQFN-32.kicad_mod │ ├── TSOT-23.kicad_mod │ ├── USB_MICRO.kicad_mod │ ├── VFQFN-16.kicad_mod │ ├── VFQFN-24.kicad_mod │ ├── VFQFN-32.kicad_mod │ ├── VQFN-16.kicad_mod │ ├── VQFN-24.kicad_mod │ ├── WFBGA-6.kicad_mod │ ├── WFDFN-8.kicad_mod │ ├── XDFN-2.kicad_mod │ ├── XFDFN-6.kicad_mod │ ├── XTAL_3.2x2.5.kicad_mod │ ├── coupler4.kicad_mod │ ├── uwmiter_0.34_0.17_45.kicad_mod │ └── uwmiter_0.34_0.17_90.kicad_mod ├── vna2-cache.lib ├── vna2.kicad_pcb ├── vna2.pdf ├── vna2.pro └── vna2.sch ├── openocd ├── interface.cfg ├── program_flash.cfg ├── program_fpga.cfg └── xc7_bscan_spi.bit └── software ├── cal_kit ├── load.s1p ├── open.s1p └── short.s1p ├── max2871.py ├── monitor_rx.py ├── monitor_sparam.py ├── oneport └── calibrate.py ├── sparam.py ├── twoport └── calibrate.py └── vna.py /README: -------------------------------------------------------------------------------- 1 | Second version of the homemade 30 MHZ - 6 GHz single receiver VNA design files. 2 | 3 | First version: https://github.com/Ttl/vna 4 | 5 | For more information see: http://hforsten.com/improved-homemade-vna.html 6 | 7 | FPGA can be programmed with Openocd (http://openocd.org/). Scripts for programming the FPGA and SPI flash are in the "openocd" folder. Copy the bit file to openocd folder and use the command "openocd -f " to program the board. 8 | 9 | Before communication is possible with the board through USB, FT2232D EEPROM needs to be programmed. Port B needs to be changed in FIFO 245 mode. This can be done using FTDIs "ft-prog" tool. 10 | -------------------------------------------------------------------------------- /couplers/README: -------------------------------------------------------------------------------- 1 | Resistive bridge coupler design files. 2 | 3 | 4 | PCB Stackup: OSH park 4 layer process. 5 | 6 | 7 | BOM: 8 | 3, http://www.mouser.fi/ProductDetail/Linx-Technologies/CONSMA003062/?qs=sGAEpiMZZMsgSGrx0WqTbDECK3OTA0n%2f 9 | 1, http://www.mouser.fi/ProductDetail/EPCOS-TDK/B64290P0687X046/?qs=sGAEpiMZZMs2JV%252bnT%2fvX8Df1W1GtRs01w38yswv%252b9W0%3d 10 | 3, http://www.mouser.fi/ProductDetail/Fair-Rite/5943000911/?qs=sGAEpiMZZMsuct6UGZJC7QQ6ZlEn2BkEKxrVH5WSvu8%3d 11 | 2, http://www.mouser.fi/ProductDetail/Fair-Rite/5977000101/?qs=sGAEpiMZZMs2JV%252bnT%2fvX8PSq2BULPkJLFoDtc8BHtvw%3d 12 | 13 | 14 | Resistors (See coupler_layout.png for positions): 15 | R1: 270 16 | R2: 50 17 | R3, R5: 36 18 | R4, R6: 39 19 | 20 | Mount the resistors upside down to minimize parasitics. 21 | 22 | 23 | Coaxial cable: 24 | RG405 25 | -------------------------------------------------------------------------------- /couplers/coupler_layout.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Ttl/vna2/2cf0efb22da56a168a7f07bf5e2c30631343997b/couplers/coupler_layout.png -------------------------------------------------------------------------------- /couplers/gerbers/rf_bridge_Bottom.gbl: -------------------------------------------------------------------------------- 1 | %FSLAX36Y36*% 2 | %MOMM*% 3 | %SFA1B1*% 4 | %ADD10C,.010*% 5 | 6 | G36* 7 | X-18900000Y-4095000D02* 8 | Y-1900000D01* 9 | X100000D01* 10 | Y-4095000D01* 11 | X3300000D01* 12 | Y-7105000D01* 13 | X100000D01* 14 | Y-9300000D01* 15 | X-18900000D01* 16 | Y-12900000D01* 17 | X10900000D01* 18 | Y1700000D01* 19 | X-28700000D01* 20 | Y-12900000D01* 21 | X-18900000D01* 22 | Y-7105000D01* 23 | X-22100000D01* 24 | Y-4095000D01* 25 | X-18900000D01* 26 | G37* 27 | M02* 28 | G04 End of Data * 29 | -------------------------------------------------------------------------------- /couplers/gerbers/rf_bridge_In1.g2l: -------------------------------------------------------------------------------- 1 | %FSLAX36Y36*% 2 | %MOMM*% 3 | %SFA1B1*% 4 | %ADD10C,.010*% 5 | 6 | G36* 7 | X-18900000Y-4295000D02* 8 | Y-1900000D01* 9 | X100000D01* 10 | Y-4295000D01* 11 | X3300000D01* 12 | Y-6905000D01* 13 | X100000D01* 14 | Y-9300000D01* 15 | X-18900000D01* 16 | Y-12900000D01* 17 | X10900000D01* 18 | Y-7030000D01* 19 | X6800000D01* 20 | Y-4170000D01* 21 | X10900000D01* 22 | Y1700000D01* 23 | X5595000D01* 24 | Y-2332657D01* 25 | X2945000D01* 26 | Y1700000D01* 27 | X-28700000D01* 28 | Y-4275000D01* 29 | X-24667343D01* 30 | Y-6925000D01* 31 | X-28700000D01* 32 | Y-12900000D01* 33 | X-18900000D01* 34 | Y-6905000D01* 35 | X-22100000D01* 36 | Y-4295000D01* 37 | X-18900000D01* 38 | G37* 39 | M02* 40 | G04 End of Data * 41 | -------------------------------------------------------------------------------- /couplers/gerbers/rf_bridge_In2.g3l: -------------------------------------------------------------------------------- 1 | %FSLAX36Y36*% 2 | %MOMM*% 3 | %SFA1B1*% 4 | %ADD10C,.010*% 5 | 6 | G36* 7 | X-18900000Y-4095000D02* 8 | Y-1900000D01* 9 | X100000D01* 10 | Y-4095000D01* 11 | X3300000D01* 12 | Y-7105000D01* 13 | X100000D01* 14 | Y-9300000D01* 15 | X-18900000D01* 16 | Y-12900000D01* 17 | X10900000D01* 18 | Y1700000D01* 19 | X-28700000D01* 20 | Y-12900000D01* 21 | X-18900000D01* 22 | Y-7105000D01* 23 | X-22100000D01* 24 | Y-4095000D01* 25 | X-18900000D01* 26 | G37* 27 | M02* 28 | G04 End of Data * 29 | -------------------------------------------------------------------------------- /couplers/gerbers/rf_bridge_Mask.gts: -------------------------------------------------------------------------------- 1 | %FSLAX36Y36*% 2 | %MOMM*% 3 | %SFA1B1*% 4 | %ADD10C,.010*% 5 | 6 | G36* 7 | X-21900000Y-2500000D02* 8 | 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26 | X-024025Y-002050 27 | X-024025Y-008950 28 | X-023925Y-003850 29 | X-023925Y-007550 30 | X-023225Y-002050 31 | X-023225Y-008950 32 | X-022900Y-003895 33 | X-022900Y-007305 34 | X-021700Y-003695 35 | X-021700Y-007605 36 | X-020900Y-003695 37 | X-020900Y-007605 38 | X-020100Y-003695 39 | X-020100Y-007605 40 | X-019300Y-003695 41 | X-019300Y-007605 42 | X000700Y001200 43 | X000700Y000100 44 | X000700Y-000800 45 | X000700Y-001700 46 | X000700Y-002600 47 | X000700Y-008600 48 | X000700Y-009600 49 | X001300Y-010800 50 | X001300Y-012300 51 | X001500Y001200 52 | X001500Y000100 53 | X001500Y-000800 54 | X001500Y-001700 55 | X001500Y-002600 56 | X001500Y-008600 57 | X001500Y-009600 58 | X002300Y001200 59 | X002300Y000100 60 | X002300Y-000800 61 | X002300Y-001700 62 | X002300Y-002600 63 | X002300Y-008600 64 | X002300Y-009600 65 | X002800Y-010800 66 | X002800Y-012300 67 | X003400Y-008600 68 | X004200Y-009300 69 | X004200Y-010800 70 | X004200Y-012300 71 | X004900Y-007800 72 | X005900Y-007800 73 | X005900Y-009300 74 | X005900Y-010800 75 | X005900Y-012300 76 | X006200Y001100 77 | X006200Y-000400 78 | X006200Y-001900 79 | X006200Y-003400 80 | X007400Y-007800 81 | X007400Y-009300 82 | X007400Y-010800 83 | X007400Y-012300 84 | X007700Y001100 85 | X007700Y-000400 86 | X007700Y-001900 87 | X007700Y-003400 88 | X008900Y-007800 89 | X008900Y-009300 90 | X008900Y-010800 91 | X008900Y-012300 92 | X009100Y001100 93 | X009100Y-000400 94 | X009100Y-001900 95 | X009100Y-003400 96 | X010400Y001100 97 | X010400Y-000400 98 | X010400Y-001900 99 | X010400Y-003400 100 | X010400Y-007800 101 | X010400Y-009300 102 | X010400Y-010800 103 | X010400Y-012300 104 | T00 105 | M30 106 | -------------------------------------------------------------------------------- /fpga/vna/vna.hw/vna.lpr: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | -------------------------------------------------------------------------------- /fpga/vna/vna.srcs/sim_1/new/comm_tb.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Company: 3 | -- Engineer: 4 | -- 5 | -- Create Date: 01.12.2016 19:38:11 6 | -- Design Name: 7 | -- Module Name: comm_tb - Behavioral 8 | -- Project Name: 9 | -- Target Devices: 10 | -- Tool Versions: 11 | -- Description: 12 | -- 13 | -- Dependencies: 14 | -- 15 | -- Revision: 16 | -- Revision 0.01 - File Created 17 | -- Additional Comments: 18 | -- 19 | ---------------------------------------------------------------------------------- 20 | 21 | 22 | library IEEE; 23 | use IEEE.STD_LOGIC_1164.ALL; 24 | 25 | -- Uncomment the following library declaration if using 26 | -- arithmetic functions with Signed or Unsigned values 27 | --use IEEE.NUMERIC_STD.ALL; 28 | 29 | -- Uncomment the following library declaration if instantiating 30 | -- any Xilinx leaf cells in this code. 31 | --library UNISIM; 32 | --use UNISIM.VComponents.all; 33 | 34 | entity comm_tb is 35 | -- Port ( ); 36 | end comm_tb; 37 | 38 | architecture Behavioral of comm_tb is 39 | 40 | signal clk, rst : std_logic := '0'; 41 | -- Clock period definitions 42 | constant clk_period : time := 25 ns; 43 | 44 | signal ft2232_data, data_out, data_in : std_logic_vector(7 downto 0) := (others => '0'); 45 | signal data_in_valid : std_logic := '0'; 46 | signal data_out_valid : std_logic; 47 | signal data_in_ack, data_out_ack : std_logic := '0'; 48 | signal rxf, txe, rd, wr, si_wu : std_logic := '0'; 49 | 50 | signal read_done : std_logic := '0'; 51 | 52 | begin 53 | 54 | comm : entity work.comm 55 | Port map ( clk => clk, 56 | rst => rst, 57 | ft2232_data => ft2232_data, 58 | data_in_valid => data_in_valid, 59 | data_out => data_out, 60 | data_out_valid => data_out_valid, 61 | data_in => data_in, 62 | data_in_ack => data_in_ack, 63 | data_out_ack => data_out_ack, 64 | rxf => rxf, 65 | txe => txe, 66 | rd => rd, 67 | wr => wr, 68 | si_wu => si_wu); 69 | 70 | rst_process : process 71 | begin 72 | rst <= '1'; 73 | wait for clk_period; 74 | rst <= '0'; 75 | wait; 76 | end process; 77 | 78 | -- Clock process definitions 79 | clk_process : process 80 | begin 81 | clk <= '0'; 82 | wait for clk_period/2; 83 | clk <= '1'; 84 | wait for clk_period/2; 85 | end process; 86 | 87 | -- Clock process definitions 88 | read_process : process 89 | begin 90 | rxf <= '1'; 91 | wait for 10*clk_period; 92 | rxf <= '0'; 93 | wait until rd = '0'; 94 | wait for 50 ns; 95 | ft2232_data <= "10101010"; 96 | wait until rd = '1'; 97 | ft2232_data <= "ZZZZZZZZ"; 98 | wait for 25 ns; 99 | rxf <= '1'; 100 | wait for 10*clk_period; 101 | assert data_out = "10101010" severity failure; 102 | data_out_ack <= '1'; 103 | wait for clk_period; 104 | data_out_ack <= '0'; 105 | wait for clk_period; 106 | assert data_out_valid = '0' severity failure; 107 | read_done <= '1'; 108 | report "Read done"; 109 | wait; 110 | end process; 111 | 112 | -- Clock process definitions 113 | write_process : process 114 | begin 115 | wait until read_done = '1'; 116 | data_in <= "11110000"; 117 | data_in_valid <= '1'; 118 | wait until wr = '0'; 119 | wait for 25 ns; 120 | txe <= '1'; 121 | assert ft2232_data = "11110000" severity failure; 122 | wait until data_in_ack = '1'; 123 | data_in_valid <= '0'; 124 | assert ft2232_data = "ZZZZZZZZ" severity failure; 125 | report "Write done"; 126 | wait for 5*clk_period; 127 | txe <= '0'; 128 | wait; 129 | end process; 130 | 131 | end Behavioral; 132 | -------------------------------------------------------------------------------- /fpga/vna/vna.srcs/sim_1/new/ft2232_behavioral.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Company: 3 | -- Engineer: 4 | -- 5 | -- Create Date: 05.12.2016 21:22:37 6 | -- Design Name: 7 | -- Module Name: ft2232_rx - Behavioral 8 | -- Project Name: 9 | -- Target Devices: 10 | -- Tool Versions: 11 | -- Description: 12 | -- 13 | -- Dependencies: 14 | -- 15 | -- Revision: 16 | -- Revision 0.01 - File Created 17 | -- Additional Comments: 18 | -- 19 | ---------------------------------------------------------------------------------- 20 | 21 | 22 | library IEEE; 23 | use IEEE.STD_LOGIC_1164.ALL; 24 | 25 | -- Uncomment the following library declaration if using 26 | -- arithmetic functions with Signed or Unsigned values 27 | --use IEEE.NUMERIC_STD.ALL; 28 | 29 | -- Uncomment the following library declaration if instantiating 30 | -- any Xilinx leaf cells in this code. 31 | --library UNISIM; 32 | --use UNISIM.VComponents.all; 33 | 34 | entity ft2232_rx is 35 | Port ( data : in STD_LOGIC_VECTOR (7 downto 0); 36 | data_out : out STD_LOGIC_VECTOR (7 downto 0); 37 | rxf : out STD_LOGIC; 38 | txe : out STD_LOGIC; 39 | rd : out STD_LOGIC; 40 | wr : in STD_LOGIC; 41 | si_wu : in STD_LOGIC); 42 | end ft2232_rx; 43 | 44 | architecture Behavioral of ft2232_rx is 45 | 46 | begin 47 | 48 | rxf <= '1'; 49 | rd <= '1'; 50 | 51 | write_process : process 52 | begin 53 | txe <= '0'; 54 | wait until wr = '0'; 55 | wait for 25 ns; 56 | txe <= '1'; 57 | data_out <= data; 58 | wait for 200 ns; 59 | end process; 60 | 61 | end Behavioral; 62 | -------------------------------------------------------------------------------- /fpga/vna/vna.srcs/sim_1/new/io_bank_tb.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Company: 3 | -- Engineer: 4 | -- 5 | -- Create Date: 01.12.2016 20:52:12 6 | -- Design Name: 7 | -- Module Name: io_bank_tb - Behavioral 8 | -- Project Name: 9 | -- Target Devices: 10 | -- Tool Versions: 11 | -- Description: 12 | -- 13 | -- Dependencies: 14 | -- 15 | -- Revision: 16 | -- Revision 0.01 - File Created 17 | -- Additional Comments: 18 | -- 19 | ---------------------------------------------------------------------------------- 20 | 21 | 22 | library IEEE; 23 | use IEEE.STD_LOGIC_1164.ALL; 24 | use work.vna_pkg.all; 25 | 26 | -- Uncomment the following library declaration if using 27 | -- arithmetic functions with Signed or Unsigned values 28 | --use IEEE.NUMERIC_STD.ALL; 29 | 30 | -- Uncomment the following library declaration if instantiating 31 | -- any Xilinx leaf cells in this code. 32 | --library UNISIM; 33 | --use UNISIM.VComponents.all; 34 | 35 | entity io_bank_tb is 36 | -- Port ( ); 37 | end io_bank_tb; 38 | 39 | architecture Behavioral of io_bank_tb is 40 | 41 | signal clk, rst : std_logic := '0'; 42 | -- Clock period definitions 43 | constant clk_period : time := 25 ns; 44 | 45 | signal ft2232_data, data_out, data_in : std_logic_vector(7 downto 0) := (others => '0'); 46 | signal data_in_valid : std_logic := '0'; 47 | signal data_out_valid : std_logic; 48 | signal data_in_ack, data_out_ack : std_logic := '0'; 49 | signal rxf, txe, rd, wr, si_wu : std_logic := '0'; 50 | 51 | signal io_data_out : std_logic_vector(7 downto 0); 52 | signal io_data_out_valid, io_data_out_ack : std_logic := '0'; 53 | signal tx_filter, port_sw, rx_sw : std_logic_vector(1 downto 0); 54 | signal port_sw_term, rx_term : std_logic; 55 | 56 | signal lo_spi_data : STD_LOGIC_VECTOR(31 downto 0); 57 | signal lo_spi_write : std_logic; 58 | signal source_spi_data : STD_LOGIC_VECTOR(31 downto 0); 59 | signal source_spi_write : std_logic; 60 | 61 | constant TEST_DATA_LENGTH : integer := 11; 62 | type test_data_type is array(TEST_DATA_LENGTH-1 downto 0) of std_logic_vector(7 downto 0); 63 | signal test_data : test_data_type := ( 64 | 0 => COMM_START, 65 | 1 => "00000001", -- Set switches 66 | 2 => "00000001", 67 | 3 => "11111111", 68 | 4 => COMM_START, 69 | 5 => "00000100", -- Set LO 70 | 6 => "00000011", 71 | 7 => "11111111", 72 | 8 => "10101010", 73 | 9 => "01010101", 74 | 10 => "00000000" 75 | ); 76 | 77 | begin 78 | 79 | comm : entity work.comm 80 | Port map ( clk => clk, 81 | rst => rst, 82 | ft2232_data => ft2232_data, 83 | data_in_valid => data_in_valid, 84 | data_out => data_out, 85 | data_out_valid => data_out_valid, 86 | data_in => data_in, 87 | data_in_ack => data_in_ack, 88 | data_out_ack => data_out_ack, 89 | rxf => rxf, 90 | txe => txe, 91 | rd => rd, 92 | wr => wr, 93 | si_wu => si_wu); 94 | 95 | io_bank : entity work.io_bank 96 | Port map ( clk => clk, 97 | rst => rst, 98 | data_in => data_out, 99 | data_valid => data_out_valid, 100 | data_in_ack => data_out_ack, 101 | data_out => io_data_out, 102 | data_out_valid => io_data_out_valid, 103 | data_out_ack => io_data_out_ack, 104 | tx_filter => tx_filter, 105 | port_sw => port_sw, 106 | rx_sw => rx_sw, 107 | lo_spi_data => lo_spi_data, 108 | lo_spi_write => lo_spi_write, 109 | source_spi_data => source_spi_data, 110 | source_spi_write => source_spi_write, 111 | led => open); 112 | 113 | rst_process : process 114 | begin 115 | rst <= '1'; 116 | wait for clk_period; 117 | rst <= '0'; 118 | wait; 119 | end process; 120 | 121 | -- Clock process definitions 122 | clk_process : process 123 | begin 124 | clk <= '0'; 125 | wait for clk_period/2; 126 | clk <= '1'; 127 | wait for clk_period/2; 128 | end process; 129 | 130 | 131 | read_process : process 132 | variable i : integer := 0; 133 | begin 134 | if i = TEST_DATA_LENGTH then 135 | report "End of data"; 136 | wait; 137 | end if; 138 | rxf <= '1'; 139 | wait for 10*clk_period; 140 | rxf <= '0'; 141 | wait until rd = '0'; 142 | wait for 50 ns; 143 | ft2232_data <= test_data(i); 144 | wait until rd = '1'; 145 | ft2232_data <= "ZZZZZZZZ"; 146 | wait for 25 ns; 147 | rxf <= '1'; 148 | wait for 10*clk_period; 149 | assert data_out = test_data(i) severity failure; 150 | i := i + 1; 151 | end process; 152 | 153 | end Behavioral; 154 | -------------------------------------------------------------------------------- /fpga/vna/vna.srcs/sim_1/new/iq_packer_tb.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Company: 3 | -- Engineer: 4 | -- 5 | -- Create Date: 05.12.2016 20:11:24 6 | -- Design Name: 7 | -- Module Name: iq_packer_tb - Behavioral 8 | -- Project Name: 9 | -- Target Devices: 10 | -- Tool Versions: 11 | -- Description: 12 | -- 13 | -- Dependencies: 14 | -- 15 | -- Revision: 16 | -- Revision 0.01 - File Created 17 | -- Additional Comments: 18 | -- 19 | ---------------------------------------------------------------------------------- 20 | 21 | 22 | library IEEE; 23 | use IEEE.STD_LOGIC_1164.ALL; 24 | use work.vna_pkg.all; 25 | 26 | -- Uncomment the following library declaration if using 27 | -- arithmetic functions with Signed or Unsigned values 28 | --use IEEE.NUMERIC_STD.ALL; 29 | 30 | -- Uncomment the following library declaration if instantiating 31 | -- any Xilinx leaf cells in this code. 32 | --library UNISIM; 33 | --use UNISIM.VComponents.all; 34 | 35 | entity iq_packer_tb is 36 | -- Port ( ); 37 | end iq_packer_tb; 38 | 39 | architecture Behavioral of iq_packer_tb is 40 | 41 | signal clk, rst : std_logic := '0'; 42 | -- Clock period definitions 43 | constant clk_period : time := 25 ns; 44 | 45 | signal ft2232_data, data_out, iq_data : std_logic_vector(7 downto 0) := (others => '0'); 46 | signal data_out_valid : std_logic; 47 | signal data_in_ack, data_out_ack : std_logic := '0'; 48 | signal rxf, txe, rd, wr, si_wu : std_logic := '1'; 49 | 50 | signal start : std_logic := '0'; 51 | signal done : std_logic; 52 | signal iq_data_valid, iq_data_ack : std_logic; 53 | signal i_acc, q_acc, cycles : STD_LOGIC_VECTOR (IQ_ACC_WIDTH-1 downto 0) := (1 => '1', 2 => '1', 4 => '1', others => '0'); 54 | 55 | begin 56 | 57 | iq_packer : entity work.iq_packer 58 | Port map ( clk => clk, 59 | rst => rst, 60 | start => start, 61 | done => done, 62 | i_acc => i_acc, 63 | q_acc => q_acc, 64 | cycles => cycles, 65 | data_out => iq_data, 66 | data_valid => iq_data_valid, 67 | data_ack => iq_data_ack); 68 | 69 | comm : entity work.comm 70 | Port map ( clk => clk, 71 | rst => rst, 72 | ft2232_data => ft2232_data, 73 | data_in_valid => iq_data_valid, 74 | data_out => data_out, 75 | data_out_valid => data_out_valid, 76 | data_in => iq_data, 77 | data_in_ack => iq_data_ack, 78 | data_out_ack => data_out_ack, 79 | rxf => rxf, 80 | txe => txe, 81 | rd => rd, 82 | wr => wr, 83 | si_wu => si_wu); 84 | 85 | 86 | rst_process : process 87 | begin 88 | rst <= '1'; 89 | wait for clk_period; 90 | rst <= '0'; 91 | wait; 92 | end process; 93 | 94 | start_process : process 95 | begin 96 | start <= '0'; 97 | wait for 10*clk_period; 98 | start <= '1'; 99 | wait for clk_period; 100 | start <= '0'; 101 | wait; 102 | end process; 103 | 104 | -- Clock process definitions 105 | clk_process : process 106 | begin 107 | clk <= '0'; 108 | wait for clk_period/2; 109 | clk <= '1'; 110 | wait for clk_period/2; 111 | end process; 112 | 113 | write_process : process 114 | begin 115 | txe <= '0'; 116 | wait until wr = '0'; 117 | wait for 25 ns; 118 | txe <= '1'; 119 | wait for 5*clk_period; 120 | end process; 121 | 122 | end Behavioral; 123 | -------------------------------------------------------------------------------- /fpga/vna/vna.srcs/sim_1/new/lo_sim.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Company: 3 | -- Engineer: 4 | -- 5 | -- Create Date: 27.11.2016 12:35:22 6 | -- Design Name: 7 | -- Module Name: lo_sim - Behavioral 8 | -- Project Name: 9 | -- Target Devices: 10 | -- Tool Versions: 11 | -- Description: 12 | -- 13 | -- Dependencies: 14 | -- 15 | -- Revision: 16 | -- Revision 0.01 - File Created 17 | -- Additional Comments: 18 | -- 19 | ---------------------------------------------------------------------------------- 20 | 21 | 22 | library IEEE; 23 | use IEEE.STD_LOGIC_1164.ALL; 24 | 25 | -- Uncomment the following library declaration if using 26 | -- arithmetic functions with Signed or Unsigned values 27 | --use IEEE.NUMERIC_STD.ALL; 28 | 29 | -- Uncomment the following library declaration if instantiating 30 | -- any Xilinx leaf cells in this code. 31 | --library UNISIM; 32 | --use UNISIM.VComponents.all; 33 | 34 | entity lo_sim is 35 | -- Port ( ); 36 | end lo_sim; 37 | 38 | architecture Behavioral of lo_sim is 39 | 40 | constant BIT_WIDTH : integer := 14; 41 | 42 | signal clk, rst : std_logic := '0'; 43 | 44 | signal lo_out : std_logic_vector(BIT_WIDTH-1 downto 0); 45 | 46 | -- Clock period definitions 47 | constant clk_period : time := 10 ns; 48 | 49 | begin 50 | 51 | lo : entity work.lo 52 | Generic map( 53 | BIT_WIDTH => BIT_WIDTH, 54 | TABLE_SIZE => 5, 55 | TABLE_WIDTH => 3, 56 | COS => false 57 | ) 58 | Port map( 59 | rst => rst, 60 | clk => clk, 61 | lo_out => lo_out 62 | ); 63 | 64 | rst_process :process 65 | begin 66 | rst <= '1'; 67 | wait for clk_period; 68 | rst <= '0'; 69 | wait; 70 | end process; 71 | 72 | -- Clock process definitions 73 | clk_process :process 74 | begin 75 | clk <= '0'; 76 | wait for clk_period/2; 77 | clk <= '1'; 78 | wait for clk_period/2; 79 | end process; 80 | 81 | end Behavioral; 82 | -------------------------------------------------------------------------------- /fpga/vna/vna.srcs/sim_1/new/mixer_sim.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Company: 3 | -- Engineer: 4 | -- 5 | -- Create Date: 27.11.2016 10:10:56 6 | -- Design Name: 7 | -- Module Name: mixer_sim - Behavioral 8 | -- Project Name: 9 | -- Target Devices: 10 | -- Tool Versions: 11 | -- Description: 12 | -- 13 | -- Dependencies: 14 | -- 15 | -- Revision: 16 | -- Revision 0.01 - File Created 17 | -- Additional Comments: 18 | -- 19 | ---------------------------------------------------------------------------------- 20 | 21 | 22 | library IEEE; 23 | use IEEE.STD_LOGIC_1164.ALL; 24 | 25 | -- Uncomment the following library declaration if using 26 | -- arithmetic functions with Signed or Unsigned values 27 | use IEEE.NUMERIC_STD.ALL; 28 | 29 | -- Uncomment the following library declaration if instantiating 30 | -- any Xilinx leaf cells in this code. 31 | --library UNISIM; 32 | --use UNISIM.VComponents.all; 33 | 34 | entity mixer_sim is 35 | -- Port ( ); 36 | end mixer_sim; 37 | 38 | architecture Behavioral of mixer_sim is 39 | 40 | signal clk : std_logic := '0'; 41 | 42 | signal rf : std_logic_vector(13 downto 0) := (others => '0'); 43 | signal lo : std_logic_vector(15 downto 0) := (0 => '1', others => '0'); 44 | signal if_out : std_logic_vector(15 downto 0) := (others => '0'); 45 | 46 | -- Clock period definitions 47 | constant clk_period : time := 10 ns; 48 | 49 | begin 50 | 51 | mixer : entity work.mixer 52 | Generic map( 53 | RF_WIDTH => 14, 54 | LO_WIDTH => 16, 55 | IF_WIDTH => 16 56 | ) 57 | Port map( clk => clk, 58 | rf => rf, 59 | lo => lo, 60 | if_out => if_out 61 | ); 62 | 63 | -- Clock process definitions 64 | clk_process :process 65 | begin 66 | clk <= '0'; 67 | wait for clk_period/2; 68 | clk <= '1'; 69 | wait for clk_period/2; 70 | end process; 71 | 72 | -- Clock process definitions 73 | rf_process :process(clk, rf) 74 | begin 75 | if rising_edge(clk) then 76 | rf <= std_logic_vector(unsigned(rf)+1); 77 | end if; 78 | end process; 79 | 80 | end Behavioral; 81 | -------------------------------------------------------------------------------- /fpga/vna/vna.srcs/sim_1/new/receiver_tb.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Company: 3 | -- Engineer: 4 | -- 5 | -- Create Date: 27.11.2016 20:14:33 6 | -- Design Name: 7 | -- Module Name: receiver_tb - Behavioral 8 | -- Project Name: 9 | -- Target Devices: 10 | -- Tool Versions: 11 | -- Description: 12 | -- 13 | -- Dependencies: 14 | -- 15 | -- Revision: 16 | -- Revision 0.01 - File Created 17 | -- Additional Comments: 18 | -- 19 | ---------------------------------------------------------------------------------- 20 | 21 | 22 | library IEEE; 23 | use IEEE.STD_LOGIC_1164.ALL; 24 | use work.vna_pkg.all; 25 | use std.textio.all; 26 | 27 | -- Uncomment the following library declaration if using 28 | -- arithmetic functions with Signed or Unsigned values 29 | use IEEE.NUMERIC_STD.ALL; 30 | 31 | -- Uncomment the following library declaration if instantiating 32 | -- any Xilinx leaf cells in this code. 33 | --library UNISIM; 34 | --use UNISIM.VComponents.all; 35 | 36 | entity receiver_tb is 37 | -- Port ( ); 38 | end receiver_tb; 39 | 40 | architecture Behavioral of receiver_tb is 41 | 42 | signal clk, rst, rst_adc, start : std_logic := '0'; 43 | signal adc : std_logic_vector(ADC_WIDTH-1 downto 0) := (others => '0'); 44 | signal i_acc, q_acc, cycles : std_logic_vector(IQ_ACC_WIDTH-1 downto 0) := (others => '0'); 45 | 46 | signal sample_time : std_logic_vector(31 downto 0) := (others => '0'); 47 | signal sample_time_valid : std_logic := '0'; 48 | 49 | -- Clock period definitions 50 | constant clk_period : time := 10 ns; 51 | 52 | signal i, q : Real := 0.0; 53 | signal i_int, q_int : integer; 54 | 55 | begin 56 | 57 | --adc_source : entity work.lo 58 | -- Generic map( 59 | -- BIT_WIDTH => ADC_WIDTH, 60 | -- TABLE_SIZE => 5, 61 | -- TABLE_WIDTH => 3, 62 | -- COS => false 63 | -- ) 64 | -- Port map( 65 | -- rst => rst, 66 | -- clk => clk, 67 | -- lo_out => adc 68 | --); 69 | 70 | file_adc : entity work.file_adc 71 | Generic map (in_file => "/home/henrik/koodi/vna2/software/samples_no_signal.txt") 72 | Port map ( clk => clk, 73 | rst => rst, 74 | adc_out => adc); 75 | 76 | rx : entity work.receiver 77 | Port map ( clk => clk, 78 | rst => rst, 79 | adc => adc, 80 | i_acc => i_acc, 81 | q_acc => q_acc, 82 | cycles => cycles, 83 | start => start, 84 | if_output => open, 85 | cic_output => open, 86 | cic_valid => open); 87 | 88 | 89 | rx_control : entity work.receiver_control 90 | Port map( clk => clk, 91 | rst => rst, 92 | start_early => open, 93 | start => start, 94 | sample_time => sample_time, 95 | sample_time_valid => sample_time_valid); 96 | 97 | rst_process :process 98 | begin 99 | -- rst <= '1'; 100 | -- rst_adc <= '1'; 101 | -- wait for 2*clk_period; 102 | -- rst_adc <= '0'; 103 | -- rst <= '0'; 104 | wait for 1000*clk_period; 105 | report "I:" & real'image(i); 106 | report "Q:" & real'image(q); 107 | end process; 108 | 109 | -- Clock process definitions 110 | clk_process :process 111 | begin 112 | clk <= '1'; 113 | wait for clk_period/2; 114 | clk <= '0'; 115 | wait for clk_period/2; 116 | end process; 117 | 118 | iq_divide : process(clk) 119 | begin 120 | if rising_edge(clk) then 121 | i <= Real(to_integer(signed(i_acc)))/(to_integer(unsigned(cycles)))/Real(32768000); 122 | q <= Real(to_integer(signed(q_acc)))/(to_integer(unsigned(cycles)))/Real(32768000); 123 | end if; 124 | end process; 125 | 126 | iq_int : process(clk) 127 | begin 128 | if rising_edge(clk) then 129 | i_int <= integer(i*Real(327680)); 130 | q_int <= integer(q*Real(327680)); 131 | end if; 132 | end process; 133 | 134 | --write process 135 | writing : process 136 | file outfile : text is out "receiver_tb_out.txt"; --declare output file 137 | variable outline : line; --line number declaration 138 | begin 139 | wait until clk = '0' and clk'event; 140 | 141 | --write(linenumber,value(real type),justified(side),field(width),digits(natural)); 142 | write(outline, integer'image(to_integer(signed(i_acc)))&", "&integer'image(to_integer(signed(q_acc)))&", "&integer'image(to_integer(unsigned(cycles)))); 143 | -- write line to external file. 144 | writeline(outfile, outline); 145 | 146 | end process writing; 147 | 148 | end Behavioral; 149 | -------------------------------------------------------------------------------- /fpga/vna/vna.srcs/sim_1/new/spi3_tb.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Company: 3 | -- Engineer: 4 | -- 5 | -- Create Date: 12.02.2017 12:24:22 6 | -- Design Name: 7 | -- Module Name: spi3_tb - Behavioral 8 | -- Project Name: 9 | -- Target Devices: 10 | -- Tool Versions: 11 | -- Description: 12 | -- 13 | -- Dependencies: 14 | -- 15 | -- Revision: 16 | -- Revision 0.01 - File Created 17 | -- Additional Comments: 18 | -- 19 | ---------------------------------------------------------------------------------- 20 | 21 | 22 | library IEEE; 23 | use IEEE.STD_LOGIC_1164.ALL; 24 | 25 | -- Uncomment the following library declaration if using 26 | -- arithmetic functions with Signed or Unsigned values 27 | --use IEEE.NUMERIC_STD.ALL; 28 | 29 | -- Uncomment the following library declaration if instantiating 30 | -- any Xilinx leaf cells in this code. 31 | --library UNISIM; 32 | --use UNISIM.VComponents.all; 33 | 34 | entity spi3_tb is 35 | -- Port ( ); 36 | end spi3_tb; 37 | 38 | architecture Behavioral of spi3_tb is 39 | 40 | signal clk, rst : std_logic := '0'; 41 | -- Clock period definitions 42 | constant clk_period : time := 25 ns; 43 | 44 | signal lo_data_in, source_data_in : std_logic_vector(31 downto 0); 45 | signal att_data_in : std_logic_vector(7 downto 0); 46 | signal lo_write, source_write, att_write : std_logic := '0'; 47 | signal busy : std_logic; 48 | signal spi_clk, spi_data_lo, spi_data_source, spi_data_att : std_logic; 49 | signal spi_le_lo, spi_le_source, spi_le_att : std_logic; 50 | 51 | begin 52 | 53 | spi3 : entity work.spi3 54 | Generic map ( SPI_CLK_DIVIDER => 1) 55 | Port map ( clk => clk, 56 | rst => rst, 57 | lo_data_in => lo_data_in, 58 | source_data_in => source_data_in, 59 | att_data_in => att_data_in, 60 | lo_write => lo_write, 61 | source_write => source_write, 62 | att_write => att_write, 63 | busy => busy, 64 | spi_clk => spi_clk, 65 | spi_data_lo => spi_data_lo, 66 | spi_data_source => spi_data_source, 67 | spi_data_att => spi_data_att, 68 | spi_le_lo => spi_le_lo, 69 | spi_le_source => spi_le_source, 70 | spi_le_att => spi_le_att); 71 | 72 | -- Clock process definitions 73 | clk_process : process 74 | begin 75 | clk <= '0'; 76 | wait for clk_period/2; 77 | clk <= '1'; 78 | wait for clk_period/2; 79 | end process; 80 | 81 | test_process : process 82 | begin 83 | wait for 100 ns; 84 | wait until rising_edge(clk); 85 | lo_data_in <= "10101010101010101010101010101010"; 86 | lo_write <= '1'; 87 | wait for 2*clk_period; 88 | lo_write <= '0'; 89 | wait for 5*clk_period; 90 | att_data_in <= "01010101"; 91 | att_write <= '1'; 92 | wait for 2*clk_period; 93 | att_write <= '0'; 94 | wait for 5*clk_period; 95 | source_data_in <= "01010101010101010101010101010101"; 96 | source_write <= '1'; 97 | wait for 2*clk_period; 98 | source_write <= '0'; 99 | wait; 100 | end process; 101 | 102 | end Behavioral; 103 | -------------------------------------------------------------------------------- /fpga/vna/vna.srcs/sim_1/new/spi_write_tb.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Company: 3 | -- Engineer: 4 | -- 5 | -- Create Date: 01.12.2016 18:23:00 6 | -- Design Name: 7 | -- Module Name: spi_write_tb - Behavioral 8 | -- Project Name: 9 | -- Target Devices: 10 | -- Tool Versions: 11 | -- Description: 12 | -- 13 | -- Dependencies: 14 | -- 15 | -- Revision: 16 | -- Revision 0.01 - File Created 17 | -- Additional Comments: 18 | -- 19 | ---------------------------------------------------------------------------------- 20 | 21 | 22 | library IEEE; 23 | use IEEE.STD_LOGIC_1164.ALL; 24 | 25 | -- Uncomment the following library declaration if using 26 | -- arithmetic functions with Signed or Unsigned values 27 | --use IEEE.NUMERIC_STD.ALL; 28 | 29 | -- Uncomment the following library declaration if instantiating 30 | -- any Xilinx leaf cells in this code. 31 | --library UNISIM; 32 | --use UNISIM.VComponents.all; 33 | 34 | entity spi_write_tb is 35 | -- Port ( ); 36 | end spi_write_tb; 37 | 38 | architecture Behavioral of spi_write_tb is 39 | 40 | constant DATA_LENGTH : integer := 16; 41 | 42 | signal clk, rst : std_logic := '0'; 43 | 44 | signal data : std_logic_vector(DATA_LENGTH-1 downto 0) := "1010110111011110"; 45 | signal spi_clk, spi_data, spi_cs : std_logic; 46 | signal data_ack : std_logic; 47 | signal data_in_valid : std_logic := '0'; 48 | 49 | -- Clock period definitions 50 | constant clk_period : time := 10 ns; 51 | 52 | begin 53 | 54 | spi_write : entity work.spi_write 55 | Generic map (SPI_CLK_DIVIDER => 2, 56 | DATA_LENGTH => DATA_LENGTH) 57 | Port map ( clk => clk, 58 | rst => rst, 59 | spi_clk => spi_clk, 60 | spi_data => spi_data, 61 | spi_cs => spi_cs, 62 | data_in => data, 63 | data_in_valid => data_in_valid, 64 | data_in_ack => data_ack); 65 | 66 | rst_process : process 67 | begin 68 | rst <= '1'; 69 | wait for clk_period; 70 | rst <= '0'; 71 | wait; 72 | end process; 73 | 74 | -- Clock process definitions 75 | clk_process : process 76 | begin 77 | clk <= '0'; 78 | wait for clk_period/2; 79 | clk <= '1'; 80 | wait for clk_period/2; 81 | end process; 82 | 83 | write_process : process 84 | begin 85 | wait for 10*clk_period; 86 | data_in_valid <= '1'; 87 | wait until data_ack = '1'; 88 | data_in_valid <= '0'; 89 | end process; 90 | 91 | assert_process : process(spi_clk) 92 | variable i : integer := DATA_LENGTH-1; 93 | begin 94 | if rising_edge(spi_clk) then 95 | assert spi_data = data(i) severity failure; 96 | i := i - 1; 97 | if i = 0 then 98 | i := DATA_LENGTH-1; 99 | end if; 100 | end if; 101 | end process; 102 | 103 | end Behavioral; 104 | -------------------------------------------------------------------------------- /fpga/vna/vna.srcs/sim_1/new/vna_tb.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Company: 3 | -- Engineer: 4 | -- 5 | -- Create Date: 27.11.2016 13:44:10 6 | -- Design Name: 7 | -- Module Name: vna_tb - Behavioral 8 | -- Project Name: 9 | -- Target Devices: 10 | -- Tool Versions: 11 | -- Description: 12 | -- 13 | -- Dependencies: 14 | -- 15 | -- Revision: 16 | -- Revision 0.01 - File Created 17 | -- Additional Comments: 18 | -- 19 | ---------------------------------------------------------------------------------- 20 | 21 | 22 | library IEEE; 23 | use IEEE.STD_LOGIC_1164.ALL; 24 | use work.vna_pkg.all; 25 | 26 | -- Uncomment the following library declaration if using 27 | -- arithmetic functions with Signed or Unsigned values 28 | use IEEE.NUMERIC_STD.ALL; 29 | 30 | -- Uncomment the following library declaration if instantiating 31 | -- any Xilinx leaf cells in this code. 32 | --library UNISIM; 33 | --use UNISIM.VComponents.all; 34 | 35 | entity vna_tb is 36 | -- Port ( ); 37 | end vna_tb; 38 | 39 | architecture Behavioral of vna_tb is 40 | 41 | component lo is 42 | Generic ( 43 | BIT_WIDTH : integer; 44 | TABLE_SIZE : integer; 45 | TABLE_WIDTH : integer; 46 | COS : boolean 47 | ); 48 | Port ( rst : in std_logic; 49 | clk : in STD_LOGIC; 50 | lo_out : out STD_LOGIC_VECTOR (BIT_WIDTH-1 downto 0)); 51 | end component; 52 | 53 | 54 | constant LO_BIT_WIDTH : integer := 14; 55 | constant ADC_BIT_WIDTH : integer := 14; 56 | 57 | signal clk, rst : std_logic := '0'; 58 | 59 | signal rf : std_logic_vector(ADC_BIT_WIDTH-1 downto 0); 60 | signal if_i_out, if_q_out : std_logic_vector(15 downto 0) := (others => '0'); 61 | 62 | -- Clock period definitions 63 | constant clk_period : time := 10 ns; 64 | 65 | begin 66 | 67 | downconvert : entity work.downconvert 68 | -- Generic map ( 69 | -- ADC_WIDTH => ADC_WIDTH, 70 | -- IF_WIDTH => IF_WIDTH) 71 | Port map ( clk => clk, 72 | rst => rst, 73 | adc => rf, 74 | if_i_out => if_i_out, 75 | if_q_out => if_q_out); 76 | 77 | adc_source : lo 78 | Generic map( 79 | BIT_WIDTH => ADC_BIT_WIDTH, 80 | TABLE_SIZE => 5, 81 | TABLE_WIDTH => 3, 82 | COS => true 83 | ) 84 | Port map( 85 | rst => rst, 86 | clk => clk, 87 | lo_out => rf 88 | ); 89 | 90 | rst_process :process 91 | begin 92 | rst <= '1'; 93 | wait for clk_period; 94 | rst <= '0'; 95 | wait; 96 | end process; 97 | 98 | -- Clock process definitions 99 | clk_process :process 100 | begin 101 | clk <= '0'; 102 | wait for clk_period/2; 103 | clk <= '1'; 104 | wait for clk_period/2; 105 | end process; 106 | 107 | end Behavioral; 108 | -------------------------------------------------------------------------------- /fpga/vna/vna.srcs/sources_1/imports/new/downconvert.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Company: 3 | -- Engineer: 4 | -- 5 | -- Create Date: 27.11.2016 13:58:22 6 | -- Design Name: 7 | -- Module Name: downconvert - Behavioral 8 | -- Project Name: 9 | -- Target Devices: 10 | -- Tool Versions: 11 | -- Description: 12 | -- 13 | -- Dependencies: 14 | -- 15 | -- Revision: 16 | -- Revision 0.01 - File Created 17 | -- Additional Comments: 18 | -- 19 | ---------------------------------------------------------------------------------- 20 | 21 | 22 | library IEEE; 23 | use IEEE.STD_LOGIC_1164.ALL; 24 | use work.vna_pkg.all; 25 | 26 | -- Uncomment the following library declaration if using 27 | -- arithmetic functions with Signed or Unsigned values 28 | use IEEE.NUMERIC_STD.ALL; 29 | 30 | -- Uncomment the following library declaration if instantiating 31 | -- any Xilinx leaf cells in this code. 32 | --library UNISIM; 33 | --use UNISIM.VComponents.all; 34 | 35 | entity downconvert is 36 | Port ( clk : in STD_LOGIC; 37 | rst : in STD_LOGIC; 38 | adc : in STD_LOGIC_VECTOR (ADC_WIDTH-1 downto 0); 39 | if_i_out : out STD_LOGIC_VECTOR (IF_WIDTH-1 downto 0); 40 | if_q_out : out STD_LOGIC_VECTOR (IF_WIDTH-1 downto 0)); 41 | end downconvert; 42 | 43 | architecture Behavioral of downconvert is 44 | 45 | signal lo_i_out, lo_q_out : std_logic_vector(LO_WIDTH-1 downto 0) := (others => '0'); 46 | 47 | begin 48 | 49 | lo_i : entity work.lo 50 | Generic map( 51 | BIT_WIDTH => LO_WIDTH, 52 | TABLE_SIZE => 5, 53 | TABLE_WIDTH => 3, 54 | COS => true 55 | ) 56 | Port map( 57 | rst => rst, 58 | clk => clk, 59 | lo_out => lo_i_out 60 | ); 61 | 62 | lo_q : entity work.lo 63 | Generic map( 64 | BIT_WIDTH => LO_WIDTH, 65 | TABLE_SIZE => 5, 66 | TABLE_WIDTH => 3, 67 | COS => false 68 | ) 69 | Port map( 70 | rst => rst, 71 | clk => clk, 72 | lo_out => lo_q_out 73 | ); 74 | 75 | mixer_i : entity work.mixer 76 | Generic map( 77 | RF_WIDTH => ADC_WIDTH, 78 | LO_WIDTH => LO_WIDTH, 79 | IF_WIDTH => IF_WIDTH 80 | ) 81 | Port map( clk => clk, 82 | rf => adc, 83 | lo => lo_i_out, 84 | if_out => if_i_out 85 | ); 86 | 87 | mixer_q : entity work.mixer 88 | Generic map( 89 | RF_WIDTH => ADC_WIDTH, 90 | LO_WIDTH => LO_WIDTH, 91 | IF_WIDTH => IF_WIDTH 92 | ) 93 | Port map( clk => clk, 94 | rf => adc, 95 | lo => lo_q_out, 96 | if_out => if_q_out 97 | ); 98 | 99 | end Behavioral; 100 | -------------------------------------------------------------------------------- /fpga/vna/vna.srcs/sources_1/imports/new/port_switch.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Company: 3 | -- Engineer: 4 | -- 5 | -- Create Date: 27.11.2016 15:33:21 6 | -- Design Name: 7 | -- Module Name: port_switch - Behavioral 8 | -- Project Name: 9 | -- Target Devices: 10 | -- Tool Versions: 11 | -- Description: 12 | -- 13 | -- Dependencies: 14 | -- 15 | -- Revision: 16 | -- Revision 0.01 - File Created 17 | -- Additional Comments: 18 | -- 19 | ---------------------------------------------------------------------------------- 20 | 21 | 22 | library IEEE; 23 | use IEEE.STD_LOGIC_1164.ALL; 24 | 25 | -- Uncomment the following library declaration if using 26 | -- arithmetic functions with Signed or Unsigned values 27 | --use IEEE.NUMERIC_STD.ALL; 28 | 29 | -- Uncomment the following library declaration if instantiating 30 | -- any Xilinx leaf cells in this code. 31 | --library UNISIM; 32 | --use UNISIM.VComponents.all; 33 | 34 | entity port_switch is 35 | Port ( direction : in STD_LOGIC; 36 | term : in STD_LOGIC; 37 | swa_ctrl : out STD_LOGIC_VECTOR (1 downto 0); 38 | swb_ctrl : out STD_LOGIC_VECTOR (1 downto 0); 39 | swc_ctrl : out STD_LOGIC_VECTOR (1 downto 0)); 40 | end port_switch; 41 | 42 | architecture Behavioral of port_switch is 43 | 44 | begin 45 | 46 | process(direction, term) 47 | begin 48 | 49 | if term = '1' then 50 | swa_ctrl <= "00"; 51 | swb_ctrl <= "00"; 52 | swc_ctrl <= "00"; 53 | else 54 | if direction = '1' then 55 | swa_ctrl <= "10"; 56 | swb_ctrl <= "10"; 57 | swc_ctrl <= "01"; 58 | else 59 | swa_ctrl <= "01"; 60 | swb_ctrl <= "01"; 61 | swc_ctrl <= "10"; 62 | end if; 63 | end if; 64 | 65 | end process; 66 | 67 | end Behavioral; 68 | -------------------------------------------------------------------------------- /fpga/vna/vna.srcs/sources_1/imports/new/sample_packer.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Company: 3 | -- Engineer: 4 | -- 5 | -- Create Date: 12.02.2017 19:54:50 6 | -- Design Name: 7 | -- Module Name: sample_packer - Behavioral 8 | -- Project Name: 9 | -- Target Devices: 10 | -- Tool Versions: 11 | -- Description: 12 | -- 13 | -- Dependencies: 14 | -- 15 | -- Revision: 16 | -- Revision 0.01 - File Created 17 | -- Additional Comments: 18 | -- 19 | ---------------------------------------------------------------------------------- 20 | 21 | 22 | library IEEE; 23 | use IEEE.STD_LOGIC_1164.ALL; 24 | use work.vna_pkg.all; 25 | 26 | -- Uncomment the following library declaration if using 27 | -- arithmetic functions with Signed or Unsigned values 28 | use IEEE.NUMERIC_STD.ALL; 29 | 30 | -- Uncomment the following library declaration if instantiating 31 | -- any Xilinx leaf cells in this code. 32 | --library UNISIM; 33 | --use UNISIM.VComponents.all; 34 | 35 | entity sample_packer is 36 | Port ( clk : in STD_LOGIC; 37 | rst : in STD_LOGIC; 38 | start : in STD_LOGIC; 39 | adc_in : in STD_LOGIC_VECTOR(13 downto 0); 40 | if_output : in STD_LOGIC_VECTOR(IF_WIDTH-1 downto 0); 41 | i_acc : in STD_LOGIC_VECTOR(IQ_ACC_WIDTH-1 downto 0); 42 | data_out : out STD_LOGIC_VECTOR(7 downto 0); 43 | data_valid : out STD_LOGIC; 44 | data_ack : in STD_LOGIC; 45 | sample_mux_ctrl : in STD_LOGIC_VECTOR(1 downto 0)); 46 | end sample_packer; 47 | 48 | architecture Behavioral of sample_packer is 49 | 50 | constant packet_size : integer := 10003; 51 | type memory_type is array (0 to packet_size-1) of std_logic_vector(15 downto 0); 52 | signal packet_memory : memory_type := (0 => COMM_START&std_logic_vector(to_unsigned(packet_size-1, 8)), 1 => "0000001000000000", others => (others => '0')); 53 | signal queue_full : std_logic := '0'; 54 | signal start_delay : std_logic := '0'; 55 | 56 | begin 57 | 58 | process(clk, rst, adc_in, if_output, i_acc, data_ack, sample_mux_ctrl) 59 | variable pointer : unsigned(15 downto 0) := to_unsigned(2, 16); 60 | variable word : std_logic := '0'; 61 | variable sample_buffer : STD_LOGIC_VECTOR (15 downto 0) := (others => '0'); 62 | variable wait_start : std_logic := '0'; 63 | begin 64 | 65 | if rising_edge(clk) then 66 | if wait_start = '1' then 67 | if start = '1' then 68 | wait_start := '0'; 69 | end if; 70 | elsif queue_full = '0' then 71 | data_valid <= '0'; 72 | packet_memory(to_integer(pointer)) <= sample_buffer; 73 | if pointer = packet_size-1 then 74 | queue_full <= '1'; 75 | pointer := to_unsigned(0, 16); 76 | else 77 | pointer := pointer + to_unsigned(1, 16); 78 | end if; 79 | else 80 | if word = '0' then 81 | data_out <= packet_memory(to_integer(pointer))(15 downto 8); 82 | else 83 | data_out <= packet_memory(to_integer(pointer))(7 downto 0); 84 | end if; 85 | 86 | data_valid <= '1'; 87 | 88 | if data_ack = '1' then 89 | if pointer = packet_size-1 then 90 | queue_full <= '0'; 91 | wait_start := '1'; 92 | data_valid <= '0'; 93 | pointer := to_unsigned(2, 16); 94 | else 95 | if word = '0' then 96 | word := '1'; 97 | else 98 | pointer := pointer + to_unsigned(1, 16); 99 | word := '0'; 100 | end if; 101 | end if; 102 | end if; 103 | end if; 104 | 105 | if sample_mux_ctrl = "00" then 106 | sample_buffer := adc_in(13)&adc_in(13)&adc_in; 107 | elsif sample_mux_ctrl = "01" then 108 | sample_buffer := if_output(23 downto 8); 109 | elsif sample_mux_ctrl = "10" then 110 | sample_buffer := i_acc(25 downto 10); 111 | else 112 | sample_buffer := (others => '0'); 113 | end if; 114 | end if; 115 | end process; 116 | 117 | 118 | end Behavioral; 119 | -------------------------------------------------------------------------------- /fpga/vna/vna.srcs/sources_1/new/acc_control.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Company: 3 | -- Engineer: 4 | -- 5 | -- Create Date: 05.12.2016 18:31:48 6 | -- Design Name: 7 | -- Module Name: acc_control - Behavioral 8 | -- Project Name: 9 | -- Target Devices: 10 | -- Tool Versions: 11 | -- Description: 12 | -- 13 | -- Dependencies: 14 | -- 15 | -- Revision: 16 | -- Revision 0.01 - File Created 17 | -- Additional Comments: 18 | -- 19 | ---------------------------------------------------------------------------------- 20 | 21 | 22 | library IEEE; 23 | use IEEE.STD_LOGIC_1164.ALL; 24 | use work.vna_pkg.all; 25 | 26 | -- Uncomment the following library declaration if using 27 | -- arithmetic functions with Signed or Unsigned values 28 | use IEEE.NUMERIC_STD.ALL; 29 | 30 | -- Uncomment the following library declaration if instantiating 31 | -- any Xilinx leaf cells in this code. 32 | --library UNISIM; 33 | --use UNISIM.VComponents.all; 34 | 35 | entity acc_control is 36 | Port ( clk : in STD_LOGIC; 37 | rst : in STD_LOGIC; 38 | acc_reset : out STD_LOGIC; 39 | receiver_hold : in STD_LOGIC); 40 | end acc_control; 41 | 42 | architecture Behavioral of acc_control is 43 | 44 | begin 45 | 46 | 47 | process(clk, rst) 48 | variable i : unsigned(11 downto 0) := to_unsigned(0, 12); 49 | begin 50 | 51 | if rst = '1' then 52 | i := to_unsigned(0, 12); 53 | acc_reset <= '1'; 54 | elsif rising_edge(clk) then 55 | acc_reset <= '1'; 56 | if i = SKIP_SAMPLES then 57 | acc_reset <= receiver_hold; 58 | else 59 | if receiver_hold = '0' then 60 | i := i + 1; 61 | end if; 62 | end if; 63 | end if; 64 | 65 | end process; 66 | 67 | end Behavioral; 68 | -------------------------------------------------------------------------------- /fpga/vna/vna.srcs/sources_1/new/accumulator.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Company: 3 | -- Engineer: 4 | -- 5 | -- Create Date: 27.11.2016 19:47:49 6 | -- Design Name: 7 | -- Module Name: average - Behavioral 8 | -- Project Name: 9 | -- Target Devices: 10 | -- Tool Versions: 11 | -- Description: 12 | -- 13 | -- Dependencies: 14 | -- 15 | -- Revision: 16 | -- Revision 0.01 - File Created 17 | -- Additional Comments: 18 | -- 19 | ---------------------------------------------------------------------------------- 20 | 21 | 22 | library IEEE; 23 | use IEEE.STD_LOGIC_1164.ALL; 24 | 25 | -- Uncomment the following library declaration if using 26 | -- arithmetic functions with Signed or Unsigned values 27 | use IEEE.NUMERIC_STD.ALL; 28 | 29 | -- Uncomment the following library declaration if instantiating 30 | -- any Xilinx leaf cells in this code. 31 | --library UNISIM; 32 | --use UNISIM.VComponents.all; 33 | 34 | entity accumulator is 35 | Generic ( 36 | IN_WIDTH : integer := 14; 37 | OUT_WIDTH : integer := 32 38 | ); 39 | Port ( clk : in STD_LOGIC; 40 | rst : in STD_LOGIC; 41 | valid : in STD_LOGIC; 42 | data : in STD_LOGIC_VECTOR (IN_WIDTH-1 downto 0); 43 | average : out STD_LOGIC_VECTOR (OUT_WIDTH-1 downto 0)); 44 | end accumulator; 45 | 46 | architecture Behavioral of accumulator is 47 | 48 | signal accum : signed(OUT_WIDTH-1 downto 0) := to_signed(0, OUT_WIDTH); 49 | 50 | begin 51 | 52 | process(clk, rst, valid, data) 53 | begin 54 | 55 | if rst = '1' then 56 | accum <= to_signed(0, OUT_WIDTH); 57 | elsif rising_edge(clk) then 58 | average <= std_logic_vector(accum); 59 | if valid = '1' then 60 | accum <= accum + signed(data); 61 | end if; 62 | end if; 63 | 64 | end process; 65 | 66 | end Behavioral; 67 | -------------------------------------------------------------------------------- /fpga/vna/vna.srcs/sources_1/new/comm.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Company: 3 | -- Engineer: 4 | -- 5 | -- Create Date: 28.11.2016 20:21:11 6 | -- Design Name: 7 | -- Module Name: comm - Behavioral 8 | -- Project Name: 9 | -- Target Devices: 10 | -- Tool Versions: 11 | -- Description: 12 | -- 13 | -- Dependencies: 14 | -- 15 | -- Revision: 16 | -- Revision 0.01 - File Created 17 | -- Additional Comments: 18 | -- 19 | ---------------------------------------------------------------------------------- 20 | 21 | 22 | library IEEE; 23 | use IEEE.STD_LOGIC_1164.ALL; 24 | 25 | -- Uncomment the following library declaration if using 26 | -- arithmetic functions with Signed or Unsigned values 27 | use IEEE.NUMERIC_STD.ALL; 28 | 29 | -- Uncomment the following library declaration if instantiating 30 | -- any Xilinx leaf cells in this code. 31 | --library UNISIM; 32 | --use UNISIM.VComponents.all; 33 | 34 | entity comm is 35 | Port ( clk : in STD_LOGIC; 36 | rst : in STD_LOGIC; 37 | ft2232_data : inout STD_LOGIC_VECTOR (7 downto 0); 38 | data_in_valid : in STD_LOGIC; 39 | data_out : out STD_LOGIC_VECTOR (7 downto 0); 40 | data_out_valid : out STD_LOGIC; 41 | data_in : in STD_LOGIC_VECTOR(7 downto 0); 42 | data_in_ack : out STD_LOGIC; 43 | data_out_ack : in STD_LOGIC; 44 | rxf : in STD_LOGIC; 45 | txe : in STD_LOGIC; 46 | rd : out STD_LOGIC; 47 | wr : out STD_LOGIC; 48 | si_wu : out STD_LOGIC; 49 | last_byte : in STD_LOGIC); 50 | end comm; 51 | 52 | architecture Behavioral of comm is 53 | 54 | constant WRITE_WR_LENGTH : integer := 4; -- Clock cycles 55 | constant READ_RD_LENGTH : integer := 4; -- Clock cycles 56 | constant SI_WU_DELAY : integer := 2; -- Clock cycles 57 | constant SI_WU_LENGTH : integer := 4; -- Clock cycles 58 | 59 | signal reading : std_logic := '0'; 60 | 61 | signal ft2232_data_write : STD_LOGIC_VECTOR(7 downto 0) := (others => '1'); 62 | 63 | signal data_out_int : STD_LOGIC_VECTOR(7 downto 0) := (others => '0'); 64 | 65 | signal rxf_sync, txe_sync : std_logic := '1'; 66 | 67 | signal last_byte_int : std_logic := '0'; 68 | signal si_wu_out : std_logic := '1'; 69 | 70 | signal si_wu_pipe : std_logic_vector(SI_WU_DELAY - 1 downto 0) := (others => '1'); 71 | signal si_wu_lengthen : std_logic_vector(SI_WU_LENGTH - 1 downto 0) := (others => '1'); 72 | 73 | begin 74 | 75 | sync_process : process(clk, rxf, txe) 76 | variable rxf_sync2, txe_sync2 : std_logic := '1'; 77 | begin 78 | 79 | if rising_edge(clk) then 80 | txe_sync <= txe_sync2; 81 | rxf_sync <= rxf_sync2; 82 | txe_sync2 := txe; 83 | rxf_sync2 := rxf; 84 | end if; 85 | end process; 86 | 87 | process(clk, rst, data_out_ack, txe_sync, rxf_sync) 88 | type ft_state_type is (S_START, S_TX_WR, S_TX_HOLD, S_RX_RD, S_RX_READ, S_RX_SEND, S_RX_WAIT); 89 | variable state : ft_state_type := S_START; 90 | variable pulse_count : unsigned(4 downto 0) := to_unsigned(0, 5); 91 | begin 92 | 93 | if rst = '1' then 94 | ft2232_data_write <= (others => '1'); 95 | state := S_START; 96 | pulse_count := to_unsigned(0, 5); 97 | wr <= '1'; 98 | data_in_ack <= '0'; 99 | elsif rising_edge(clk) then 100 | -- Default values 101 | wr <= '1'; 102 | rd <= '1'; 103 | si_wu_out <= '1'; 104 | 105 | data_in_ack <= '0'; 106 | 107 | ft2232_data_write <= (others => '1'); 108 | 109 | if (state = S_TX_WR or state = S_TX_HOLD) then 110 | reading <= '0'; 111 | else 112 | reading <= '1'; 113 | end if; 114 | 115 | case state is 116 | 117 | when S_START => 118 | -- Priorize reading 119 | if rxf_sync = '0' then 120 | state := S_RX_RD; 121 | rd <= '0'; 122 | pulse_count := to_unsigned(READ_RD_LENGTH, 5); 123 | elsif data_in_valid = '1' and txe_sync = '0' then 124 | state := S_TX_WR; 125 | wr <= '1'; 126 | ft2232_data_write <= data_in; 127 | last_byte_int <= last_byte; 128 | pulse_count := to_unsigned(WRITE_WR_LENGTH, 5); 129 | end if; 130 | 131 | when S_TX_WR => 132 | -- Holds WR signal high 133 | ft2232_data_write <= data_in; 134 | if pulse_count = to_unsigned(0, 5) then 135 | state := S_TX_HOLD; 136 | wr <= '0'; -- Strobe WR to signal a write 137 | pulse_count := to_unsigned(WRITE_WR_LENGTH, 5); 138 | else 139 | pulse_count := pulse_count - 1; 140 | end if; 141 | 142 | when S_TX_HOLD => 143 | -- Wait for TXE to rise 144 | wr <= '0'; 145 | ft2232_data_write <= data_in; 146 | if txe_sync = '1' then 147 | data_in_ack <= '1'; 148 | state := S_START; 149 | si_wu_out <= not last_byte_int; 150 | end if; 151 | 152 | when S_RX_RD => 153 | -- Holds RD signal low 154 | rd <= '0'; 155 | if pulse_count = to_unsigned(0, 5) then 156 | state := S_RX_READ; 157 | else 158 | pulse_count := pulse_count - 1; 159 | end if; 160 | 161 | when S_RX_READ => 162 | -- Read the data 163 | rd <= '1'; 164 | data_out_int <= ft2232_data; 165 | data_out_valid <= '1'; 166 | state := S_RX_SEND; 167 | 168 | when S_RX_SEND => 169 | rd <= '1'; 170 | data_out_valid <= '1'; 171 | if data_out_ack = '1' then 172 | data_out_valid <= '0'; 173 | state := S_RX_WAIT; 174 | pulse_count := to_unsigned(READ_RD_LENGTH, 5); 175 | end if; 176 | 177 | when S_RX_WAIT => 178 | if rxf_sync = '1' or pulse_count = to_unsigned(0, 5) then 179 | state := S_START; 180 | else 181 | pulse_count := pulse_count - 1; 182 | end if; 183 | 184 | when others => 185 | state := S_START; 186 | 187 | end case; 188 | end if; 189 | 190 | end process; 191 | 192 | si_wu_process : process(clk, si_wu_out) 193 | 194 | variable si_wu_and : std_logic := '1'; 195 | begin 196 | 197 | if rising_edge(clk) then 198 | 199 | si_wu_pipe(0) <= si_wu_out; 200 | si_wu_lengthen(0) <= si_wu_pipe(SI_WU_DELAY - 1); 201 | for i in 1 to SI_WU_DELAY-1 loop 202 | si_wu_pipe(i) <= si_wu_pipe(i-1); 203 | end loop; 204 | 205 | si_wu_and := si_wu_lengthen(0); 206 | for i in 1 to SI_WU_LENGTH-1 loop 207 | si_wu_lengthen(i) <= si_wu_lengthen(i-1); 208 | si_wu_and := si_wu_and and si_wu_lengthen(i); 209 | end loop; 210 | 211 | end if; 212 | 213 | si_wu <= si_wu_and; 214 | 215 | end process; 216 | 217 | data_out <= data_out_int; 218 | 219 | ft2232_data <= (others => 'Z') when reading = '1' else ft2232_data_write; 220 | 221 | end Behavioral; 222 | -------------------------------------------------------------------------------- /fpga/vna/vna.srcs/sources_1/new/dither.vhd: -------------------------------------------------------------------------------- 1 | library IEEE; 2 | use IEEE.STD_LOGIC_1164.ALL; 3 | 4 | -- Uncomment the following library declaration if using 5 | -- arithmetic functions with Signed or Unsigned values 6 | use IEEE.NUMERIC_STD.ALL; 7 | 8 | -- Uncomment the following library declaration if instantiating 9 | -- any Xilinx leaf cells in this code. 10 | --library UNISIM; 11 | --use UNISIM.VComponents.all; 12 | 13 | entity dither is 14 | Port ( clk : in STD_LOGIC; 15 | rst : in STD_LOGIC; 16 | q : out STD_LOGIC); 17 | end dither; 18 | 19 | architecture Behavioral of dither is 20 | 21 | constant OUT_WIDTH : integer := 8; 22 | 23 | component lfsr is 24 | generic ( SEED : STD_LOGIC_VECTOR(30 downto 0); 25 | OUT_WIDTH : integer); 26 | port( 27 | clk : in STD_LOGIC; 28 | q : out STD_LOGIC_VECTOR (OUT_WIDTH-1 downto 0); 29 | rst : in STD_LOGIC); 30 | end component; 31 | 32 | signal uniform1 : std_logic_vector(OUT_WIDTH-1 downto 0); 33 | 34 | begin 35 | 36 | unif1: lfsr 37 | generic map (SEED => std_logic_vector(to_unsigned(697757461,31)), 38 | OUT_WIDTH => OUT_WIDTH) 39 | port map( 40 | clk => clk, 41 | q => uniform1, 42 | rst => rst 43 | ); 44 | 45 | q <= uniform1(0); 46 | 47 | end Behavioral; 48 | -------------------------------------------------------------------------------- /fpga/vna/vna.srcs/sources_1/new/file_adc.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Company: 3 | -- Engineer: 4 | -- 5 | -- Create Date: 14.02.2017 21:18:56 6 | -- Design Name: 7 | -- Module Name: file_adc - Behavioral 8 | -- Project Name: 9 | -- Target Devices: 10 | -- Tool Versions: 11 | -- Description: 12 | -- 13 | -- Dependencies: 14 | -- 15 | -- Revision: 16 | -- Revision 0.01 - File Created 17 | -- Additional Comments: 18 | -- 19 | ---------------------------------------------------------------------------------- 20 | 21 | 22 | library IEEE; 23 | use IEEE.STD_LOGIC_1164.ALL; 24 | use std.textio.all; --include package textio.vhd 25 | use IEEE.NUMERIC_STD.ALL; 26 | 27 | -- Uncomment the following library declaration if instantiating 28 | -- any Xilinx leaf cells in this code. 29 | --library UNISIM; 30 | --use UNISIM.VComponents.all; 31 | 32 | entity file_adc is 33 | Generic (in_file : string := "samples.txt"); 34 | Port ( clk : in STD_LOGIC; 35 | rst : in STD_LOGIC; 36 | adc_out : out STD_LOGIC_VECTOR (13 downto 0)); 37 | end file_adc; 38 | 39 | architecture Behavioral of file_adc is 40 | 41 | constant DEPTH : integer := 5000; 42 | 43 | subtype word_t is std_logic_vector(13 downto 0); 44 | type ram_t is array(0 to DEPTH-1) of word_t; 45 | 46 | -- Read a *.hex file 47 | impure function ocram_ReadMemFile(FileName : STRING) return ram_t is 48 | file infile : text is in FileName; 49 | variable inline : line; --line number declaration 50 | variable dataread1 : integer; 51 | variable Result : ram_t := (others => (others => '0')); 52 | 53 | begin 54 | for i in 0 to DEPTH - 1 loop 55 | exit when endfile(infile); 56 | 57 | readline(infile, inline); 58 | read(inline, dataread1); 59 | Result(i) := std_logic_vector(to_signed(dataread1, 14)); 60 | end loop; 61 | 62 | return Result; 63 | end function; 64 | 65 | signal ram : ram_t := ocram_ReadMemFile(in_file); 66 | signal pointer : integer := 0; 67 | 68 | begin 69 | 70 | process(clk, rst) 71 | 72 | begin 73 | if rst = '1' then 74 | pointer <= 0; 75 | elsif rising_edge(clk) then 76 | if pointer < DEPTH - 1 then 77 | pointer <= pointer + 1; 78 | else 79 | pointer <= 0; 80 | end if; 81 | end if; 82 | end process; 83 | 84 | adc_out <= ram(pointer); 85 | 86 | end Behavioral; 87 | -------------------------------------------------------------------------------- /fpga/vna/vna.srcs/sources_1/new/iq_packer.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Company: 3 | -- Engineer: 4 | -- 5 | -- Create Date: 05.12.2016 19:46:05 6 | -- Design Name: 7 | -- Module Name: iq_packer - Behavioral 8 | -- Project Name: 9 | -- Target Devices: 10 | -- Tool Versions: 11 | -- Description: 12 | -- 13 | -- Dependencies: 14 | -- 15 | -- Revision: 16 | -- Revision 0.01 - File Created 17 | -- Additional Comments: 18 | -- 19 | ---------------------------------------------------------------------------------- 20 | 21 | 22 | library IEEE; 23 | use IEEE.STD_LOGIC_1164.ALL; 24 | use work.vna_pkg.all; 25 | 26 | -- Uncomment the following library declaration if using 27 | -- arithmetic functions with Signed or Unsigned values 28 | use IEEE.NUMERIC_STD.ALL; 29 | 30 | -- Uncomment the following library declaration if instantiating 31 | -- any Xilinx leaf cells in this code. 32 | --library UNISIM; 33 | --use UNISIM.VComponents.all; 34 | 35 | entity iq_packer is 36 | Port ( clk : in STD_LOGIC; 37 | rst : in STD_LOGIC; 38 | start : in STD_LOGIC; 39 | done : out STD_LOGIC; 40 | i_acc : in STD_LOGIC_VECTOR (IQ_ACC_WIDTH-1 downto 0); 41 | q_acc : in STD_LOGIC_VECTOR (IQ_ACC_WIDTH-1 downto 0); 42 | cycles : in STD_LOGIC_VECTOR (IQ_ACC_WIDTH-1 downto 0); 43 | data_out : out STD_LOGIC_VECTOR (7 downto 0); 44 | data_valid : out STD_LOGIC; 45 | data_ack : in STD_LOGIC; 46 | rx_sw : in rx_sw_type; 47 | iq_tag_in : in STD_LOGIC_VECTOR(7 downto 0); 48 | iq_tag_valid : in STD_LOGIC; 49 | last_byte : out STD_LOGIC); 50 | end iq_packer; 51 | 52 | architecture Behavioral of iq_packer is 53 | 54 | -- Start, Length, id = 3 55 | -- I, Q, cycles 7 bytes = 21 56 | -- RX_SW, tag 2 57 | 58 | constant packet_size : integer := 3+3*IQ_BYTES+2; 59 | type memory_type is array (0 to packet_size-1) of std_logic_vector(7 downto 0); 60 | signal packet_memory : memory_type := (0 => COMM_START, 1 => std_logic_vector(to_unsigned(packet_size-1, 8)), 2 => "00000001", others => (others => '0')); 61 | signal queue_full : std_logic := '0'; 62 | signal start_delay : std_logic := '0'; 63 | 64 | signal iq_tag : std_logic_vector(7 downto 0) := (others => '0'); 65 | 66 | begin 67 | 68 | queue_fill_process : process(clk, start, i_acc, q_acc, cycles, queue_full, start_delay) 69 | variable rx_sw_delay : rx_sw_type; 70 | variable rx_sw_write : std_logic_vector(2 downto 0); 71 | variable sent : unsigned(7 downto 0) := to_unsigned(0, 8); 72 | begin 73 | if rising_edge(clk) then 74 | 75 | last_byte <= '0'; 76 | if iq_tag_valid = '1' then 77 | packet_memory(3+3*IQ_BYTES+1) <= iq_tag_in; 78 | end if; 79 | 80 | data_out <= packet_memory(to_integer(sent)); 81 | data_valid <= '0'; 82 | 83 | start_delay <= start; 84 | -- Don't write new values if still sending the old ones 85 | if start = '1' and queue_full = '0' then 86 | for i in 0 to IQ_BYTES-1 loop 87 | packet_memory(3+i) <= i_acc(8*(i+1)-1 downto 8*i); 88 | packet_memory(3+IQ_BYTES+i) <= q_acc(8*(i+1)-1 downto 8*i); 89 | packet_memory(3+2*IQ_BYTES+i) <= cycles(8*(i+1)-1 downto 8*i); 90 | end loop; 91 | case rx_sw_delay is 92 | when SW_RX1 => 93 | rx_sw_write := "001"; 94 | when SW_A => 95 | rx_sw_write := "010"; 96 | when SW_RX2 => 97 | rx_sw_write := "011"; 98 | when SW_B => 99 | rx_sw_write := "100"; 100 | when others => 101 | rx_sw_write := (others => '0'); 102 | end case; 103 | packet_memory(3+3*IQ_BYTES) <= "00000"&rx_sw_write; 104 | end if; 105 | rx_sw_delay := rx_sw; 106 | 107 | if start_delay = '1' or queue_full = '1' then 108 | queue_full <= '1'; 109 | data_valid <= '1'; 110 | 111 | if sent = to_unsigned(packet_size-1, 8) then 112 | last_byte <= '1'; 113 | end if; 114 | if sent = to_unsigned(packet_size-1, 8) and data_ack = '1' then 115 | queue_full <= '0'; 116 | sent := to_unsigned(0, 8); 117 | elsif data_ack = '1' then 118 | sent := sent + 1; 119 | end if; 120 | end if; 121 | 122 | end if; 123 | end process; 124 | 125 | done <= not queue_full; 126 | 127 | end Behavioral; 128 | -------------------------------------------------------------------------------- /fpga/vna/vna.srcs/sources_1/new/lfsr.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Company: 3 | -- Engineer: 4 | -- 5 | -- Create Date: 11.02.2017 15:57:28 6 | -- Design Name: 7 | -- Module Name: lfsr - Behavioral 8 | -- Project Name: 9 | -- Target Devices: 10 | -- Tool Versions: 11 | -- Description: 12 | -- 13 | -- Dependencies: 14 | -- 15 | -- Revision: 16 | -- Revision 0.01 - File Created 17 | -- Additional Comments: 18 | -- 19 | ---------------------------------------------------------------------------------- 20 | 21 | 22 | library IEEE; 23 | use IEEE.STD_LOGIC_1164.ALL; 24 | 25 | -- Uncomment the following library declaration if using 26 | -- arithmetic functions with Signed or Unsigned values 27 | --use IEEE.NUMERIC_STD.ALL; 28 | 29 | -- Uncomment the following library declaration if instantiating 30 | -- any Xilinx leaf cells in this code. 31 | --library UNISIM; 32 | --use UNISIM.VComponents.all; 33 | 34 | entity lfsr is 35 | generic ( SEED : STD_LOGIC_VECTOR(30 downto 0):= (others => '0'); 36 | OUT_WIDTH : integer := 11); 37 | Port ( clk : in STD_LOGIC; 38 | rst : in STD_LOGIC; 39 | q : out STD_LOGIC_VECTOR (OUT_WIDTH-1 downto 0)); 40 | end lfsr; 41 | 42 | architecture Behavioral of lfsr is 43 | 44 | signal rand : std_logic_vector(30 downto 0) := SEED; 45 | signal feedback : std_logic; 46 | 47 | begin 48 | 49 | feedback <= not((rand(0) xor rand(3))); 50 | 51 | process(clk,rst) 52 | begin 53 | if rst = '1' then 54 | rand <= SEED; 55 | elsif rising_edge(clk) then 56 | rand <= feedback&rand(30 downto 1); 57 | end if; 58 | end process; 59 | 60 | q <= rand(OUT_WIDTH-1 downto 0); 61 | 62 | end Behavioral; -------------------------------------------------------------------------------- /fpga/vna/vna.srcs/sources_1/new/lo.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Company: 3 | -- Engineer: 4 | -- 5 | -- Create Date: 27.11.2016 12:23:09 6 | -- Design Name: 7 | -- Module Name: lo - Behavioral 8 | -- Project Name: 9 | -- Target Devices: 10 | -- Tool Versions: 11 | -- Description: 12 | -- 13 | -- Dependencies: 14 | -- 15 | -- Revision: 16 | -- Revision 0.01 - File Created 17 | -- Additional Comments: 18 | -- 19 | ---------------------------------------------------------------------------------- 20 | 21 | 22 | library IEEE; 23 | use IEEE.STD_LOGIC_1164.ALL; 24 | 25 | -- Uncomment the following library declaration if using 26 | -- arithmetic functions with Signed or Unsigned values 27 | use IEEE.NUMERIC_STD.ALL; 28 | 29 | -- Uncomment the following library declaration if instantiating 30 | -- any Xilinx leaf cells in this code. 31 | --library UNISIM; 32 | --use UNISIM.VComponents.all; 33 | 34 | entity lo is 35 | Generic ( 36 | BIT_WIDTH : integer := 14; 37 | TABLE_SIZE : integer := 5; 38 | TABLE_WIDTH : integer := 3; 39 | COS : boolean := false 40 | ); 41 | Port ( rst : in std_logic; 42 | clk : in STD_LOGIC; 43 | lo_out : out STD_LOGIC_VECTOR (BIT_WIDTH-1 downto 0)); 44 | end lo; 45 | 46 | architecture Behavioral of lo is 47 | 48 | type table_type is array (0 to TABLE_SIZE) of std_logic_vector(BIT_WIDTH-1 downto 0); 49 | 50 | signal table : table_type := ( 51 | 0 => std_logic_vector(to_signed(0, BIT_WIDTH)), 52 | 1 => std_logic_vector(to_signed(2531, BIT_WIDTH)), 53 | 2 => std_logic_vector(to_signed(4814, BIT_WIDTH)), 54 | 3 => std_logic_vector(to_signed(6626, BIT_WIDTH)), 55 | 4 => std_logic_vector(to_signed(7790, BIT_WIDTH)), 56 | 5 => std_logic_vector(to_signed(8191, BIT_WIDTH)), 57 | others => (others => '0') 58 | ); 59 | 60 | function init_i(cos : in boolean) return unsigned is 61 | begin 62 | if cos then 63 | return to_unsigned(TABLE_SIZE, TABLE_WIDTH); 64 | end if; 65 | return to_unsigned(0, TABLE_WIDTH); 66 | end function; 67 | 68 | function init_dir(cos : in boolean) return std_logic is 69 | begin 70 | if cos then 71 | return '1'; 72 | end if; 73 | return '0'; 74 | end function; 75 | 76 | signal index : unsigned(TABLE_WIDTH-1 downto 0) := init_i(COS); 77 | signal sign: std_logic := '0'; 78 | 79 | begin 80 | 81 | process(clk, rst) 82 | 83 | 84 | variable direction : std_logic := init_dir(COS); 85 | begin 86 | 87 | if rst = '1' then 88 | if COS then 89 | index <= to_unsigned(TABLE_SIZE, TABLE_WIDTH); 90 | sign <= '0'; 91 | direction := '1'; 92 | else 93 | index <= to_unsigned(0, TABLE_WIDTH); 94 | sign <= '0'; 95 | direction := '0'; 96 | end if; 97 | elsif rising_edge(clk) then 98 | if index = TABLE_SIZE then 99 | direction := '1'; 100 | end if; 101 | if index = 0 then 102 | direction := '0'; 103 | sign <= not sign; 104 | end if; 105 | 106 | if direction = '0' then 107 | index <= index+1; 108 | else 109 | index <= index-1; 110 | end if; 111 | end if; 112 | 113 | end process; 114 | 115 | lo_out <= table(to_integer(index)) when sign = '0' else std_logic_vector(-signed(table(to_integer(index)))); 116 | 117 | end Behavioral; 118 | -------------------------------------------------------------------------------- /fpga/vna/vna.srcs/sources_1/new/mixer.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Company: 3 | -- Engineer: 4 | -- 5 | -- Create Date: 27.11.2016 10:07:32 6 | -- Design Name: 7 | -- Module Name: mixer - Behavioral 8 | -- Project Name: 9 | -- Target Devices: 10 | -- Tool Versions: 11 | -- Description: 12 | -- 13 | -- Dependencies: 14 | -- 15 | -- Revision: 16 | -- Revision 0.01 - File Created 17 | -- Additional Comments: 18 | -- 19 | ---------------------------------------------------------------------------------- 20 | 21 | 22 | library IEEE; 23 | use IEEE.STD_LOGIC_1164.ALL; 24 | 25 | -- Uncomment the following library declaration if using 26 | -- arithmetic functions with Signed or Unsigned values 27 | use IEEE.NUMERIC_STD.ALL; 28 | 29 | -- Uncomment the following library declaration if instantiating 30 | -- any Xilinx leaf cells in this code. 31 | --library UNISIM; 32 | --use UNISIM.VComponents.all; 33 | 34 | entity mixer is 35 | Generic ( 36 | RF_WIDTH : integer := 14; 37 | LO_WIDTH : integer := 16; 38 | IF_WIDTH : integer := 16 39 | ); 40 | Port ( clk : in std_logic; 41 | rf : in STD_LOGIC_VECTOR (RF_WIDTH-1 downto 0); 42 | lo : in STD_LOGIC_VECTOR (LO_WIDTH-1 downto 0); 43 | if_out : out STD_LOGIC_VECTOR (IF_WIDTH-1 downto 0)); 44 | end mixer; 45 | 46 | architecture Behavioral of mixer is 47 | 48 | constant level : integer := 2; 49 | 50 | type pipeline_type is array (level-1 downto 0) of std_logic_vector(RF_WIDTH+LO_WIDTH-1 downto 0); 51 | signal pipe : pipeline_type := (others => (others => '0')); 52 | 53 | signal a : std_logic_vector(RF_WIDTH-1 downto 0) := (others => '0'); 54 | signal b : std_logic_vector(LO_WIDTH-1 downto 0) := (others => '0'); 55 | signal non_rounded, rounded : std_logic_vector(IF_WIDTH-1 downto 0) := (others => '0'); 56 | 57 | begin 58 | 59 | process(clk, rf, lo) 60 | variable m : std_logic_vector(RF_WIDTH+LO_WIDTH-1 downto 0); 61 | begin 62 | if rising_edge(clk) then 63 | a <= rf; 64 | b <= lo; 65 | m := std_logic_vector(signed(a)*signed(b)); 66 | pipe(0) <= m; 67 | for i in 1 to level-1 loop 68 | pipe(i) <= pipe(i-1); 69 | end loop; 70 | end if; 71 | end process; 72 | 73 | round_towards_zero : process(clk, pipe) 74 | variable pipe_if : std_logic_vector(IF_WIDTH-1 downto 0); 75 | begin 76 | if rising_edge(clk) then 77 | pipe_if := pipe(level-1)(RF_WIDTH+LO_WIDTH-1 downto RF_WIDTH+LO_WIDTH-IF_WIDTH); 78 | non_rounded <= pipe_if; 79 | rounded <= std_logic_vector(signed(pipe_if) + 1); 80 | end if; 81 | end process; 82 | 83 | if_out <= rounded when non_rounded(IF_WIDTH-1) = '1' else non_rounded; 84 | 85 | end Behavioral; 86 | -------------------------------------------------------------------------------- /fpga/vna/vna.srcs/sources_1/new/pwr_sync_gen.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Company: 3 | -- Engineer: 4 | -- 5 | -- Create Date: 10.01.2017 21:00:45 6 | -- Design Name: 7 | -- Module Name: pwr_sync_gen - Behavioral 8 | -- Project Name: 9 | -- Target Devices: 10 | -- Tool Versions: 11 | -- Description: 12 | -- 13 | -- Dependencies: 14 | -- 15 | -- Revision: 16 | -- Revision 0.01 - File Created 17 | -- Additional Comments: 18 | -- 19 | ---------------------------------------------------------------------------------- 20 | 21 | 22 | library IEEE; 23 | use IEEE.STD_LOGIC_1164.ALL; 24 | use IEEE.NUMERIC_STD.ALL; 25 | 26 | -- Uncomment the following library declaration if instantiating 27 | -- any Xilinx leaf cells in this code. 28 | --library UNISIM; 29 | --use UNISIM.VComponents.all; 30 | 31 | entity pwr_sync_gen is 32 | Port ( clk : in STD_LOGIC; 33 | rst : in STD_LOGIC; 34 | sync1 : out STD_LOGIC); 35 | end pwr_sync_gen; 36 | 37 | architecture Behavioral of pwr_sync_gen is 38 | 39 | begin 40 | 41 | pwr_sync_process : process(clk) 42 | variable count : unsigned(7 downto 0) := to_unsigned(0, 8); 43 | begin 44 | 45 | end process; 46 | 47 | end Behavioral; 48 | -------------------------------------------------------------------------------- /fpga/vna/vna.srcs/sources_1/new/receiver.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Company: 3 | -- Engineer: 4 | -- 5 | -- Create Date: 27.11.2016 20:03:05 6 | -- Design Name: 7 | -- Module Name: receiver - Behavioral 8 | -- Project Name: 9 | -- Target Devices: 10 | -- Tool Versions: 11 | -- Description: 12 | -- 13 | -- Dependencies: 14 | -- 15 | -- Revision: 16 | -- Revision 0.01 - File Created 17 | -- Additional Comments: 18 | -- 19 | ---------------------------------------------------------------------------------- 20 | 21 | 22 | library IEEE; 23 | use IEEE.STD_LOGIC_1164.ALL; 24 | use work.vna_pkg.all; 25 | 26 | -- Uncomment the following library declaration if using 27 | -- arithmetic functions with Signed or Unsigned values 28 | use IEEE.NUMERIC_STD.ALL; 29 | 30 | -- Uncomment the following library declaration if instantiating 31 | -- any Xilinx leaf cells in this code. 32 | --library UNISIM; 33 | --use UNISIM.VComponents.all; 34 | 35 | entity receiver is 36 | Port ( clk : in STD_LOGIC; 37 | rst : in STD_LOGIC; 38 | adc : in STD_LOGIC_VECTOR (13 downto 0); 39 | i_acc : out STD_LOGIC_VECTOR(IQ_ACC_WIDTH-1 downto 0); 40 | q_acc : out STD_LOGIC_VECTOR(IQ_ACC_WIDTH-1 downto 0); 41 | cycles : out STD_LOGIC_VECTOR(IQ_ACC_WIDTH-1 downto 0); 42 | start : in STD_LOGIC; 43 | if_output : out STD_LOGIC_VECTOR(IF_WIDTH-1 downto 0); 44 | receiver_hold : in STD_LOGIC); 45 | end receiver; 46 | 47 | architecture Behavioral of receiver is 48 | 49 | signal acc_rst : std_logic; 50 | signal if_i, if_q : std_logic_vector(IF_WIDTH-1 downto 0); 51 | 52 | signal acc_control_rst : std_logic; 53 | 54 | begin 55 | 56 | downconverter_0 : entity work.downconvert 57 | Port map( clk => clk, 58 | rst => rst, 59 | adc => adc, 60 | if_i_out => if_i, 61 | if_q_out => if_q); 62 | 63 | accumulator_i : entity work.accumulator 64 | Generic map ( 65 | IN_WIDTH => IF_WIDTH, 66 | OUT_WIDTH => IQ_ACC_WIDTH 67 | ) 68 | Port map ( clk => clk, 69 | rst => acc_rst, 70 | valid => '1', 71 | data => if_i, 72 | average => i_acc 73 | ); 74 | 75 | accumulator_q : entity work.accumulator 76 | Generic map ( 77 | IN_WIDTH => IF_WIDTH, 78 | OUT_WIDTH => IQ_ACC_WIDTH 79 | ) 80 | Port map ( clk => clk, 81 | rst => acc_rst, 82 | valid => '1', 83 | data => if_q, 84 | average => q_acc 85 | ); 86 | 87 | accumulator_cycles : entity work.accumulator 88 | Generic map ( 89 | IN_WIDTH => 2, 90 | OUT_WIDTH => IQ_ACC_WIDTH 91 | ) 92 | Port map ( clk => clk, 93 | rst => acc_rst, 94 | valid => '1', 95 | data => "01", 96 | average => cycles 97 | ); 98 | 99 | acc_control : entity work.acc_control 100 | Port map ( clk => clk, 101 | rst => acc_control_rst, 102 | receiver_hold => receiver_hold, 103 | acc_reset => acc_rst 104 | ); 105 | 106 | acc_control_rst <= start or rst; 107 | if_output <= if_i; 108 | 109 | end Behavioral; 110 | -------------------------------------------------------------------------------- /fpga/vna/vna.srcs/sources_1/new/receiver_control.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Company: 3 | -- Engineer: 4 | -- 5 | -- Create Date: 05.12.2016 20:44:41 6 | -- Design Name: 7 | -- Module Name: receiver_control - Behavioral 8 | -- Project Name: 9 | -- Target Devices: 10 | -- Tool Versions: 11 | -- Description: 12 | -- 13 | -- Dependencies: 14 | -- 15 | -- Revision: 16 | -- Revision 0.01 - File Created 17 | -- Additional Comments: 18 | -- 19 | ---------------------------------------------------------------------------------- 20 | 21 | 22 | library IEEE; 23 | use IEEE.STD_LOGIC_1164.ALL; 24 | use work.vna_pkg.all; 25 | 26 | -- Uncomment the following library declaration if using 27 | -- arithmetic functions with Signed or Unsigned values 28 | use IEEE.NUMERIC_STD.ALL; 29 | 30 | -- Uncomment the following library declaration if instantiating 31 | -- any Xilinx leaf cells in this code. 32 | --library UNISIM; 33 | --use UNISIM.VComponents.all; 34 | 35 | entity receiver_control is 36 | Port ( clk : in STD_LOGIC; 37 | rst : in STD_LOGIC; 38 | start_early : out STD_LOGIC; 39 | start : out STD_LOGIC; 40 | sample_time : in STD_LOGIC_VECTOR (31 downto 0); 41 | sample_time_valid : in STD_LOGIC; 42 | receiver_hold : out STD_LOGIC; 43 | lo_ld : in STD_LOGIC; 44 | source_ld : in STD_LOGIC; 45 | rx_sw : out rx_sw_type; 46 | tx_ready : in STD_LOGIC); 47 | end receiver_control; 48 | 49 | architecture Behavioral of receiver_control is 50 | 51 | signal sample_time_int, sample_time_int_next : STD_LOGIC_VECTOR (31 downto 0) := (15 => '1', others => '0'); 52 | 53 | signal start_int : std_logic := '0'; 54 | 55 | signal rx_sw_int : rx_sw_type := SW_RX1; 56 | 57 | signal lo_ld_sync, source_ld_sync : std_logic := '0'; 58 | 59 | begin 60 | 61 | sample_time_update : process(clk, sample_time, sample_time_valid) 62 | begin 63 | if rising_edge(clk) then 64 | if sample_time_valid = '1' then 65 | sample_time_int_next <= sample_time; 66 | end if; 67 | end if; 68 | end process; 69 | 70 | start_generator : process(clk, rst, sample_time_int, rx_sw_int, lo_ld_sync, source_ld_sync, tx_ready) 71 | variable counter : unsigned(31 downto 0) := to_unsigned(0, 32); 72 | variable locked_cycles : unsigned(15 downto 0) := to_unsigned(0, 16); 73 | begin 74 | if rst = '1' then 75 | counter := to_unsigned(0, 32); 76 | elsif rising_edge(clk) then 77 | start_int <= '0'; 78 | receiver_hold <= '1'; 79 | 80 | if lo_ld_sync = '0' or source_ld_sync = '0' then 81 | -- No lock: reset receiver 82 | locked_cycles := to_unsigned(0, 16); 83 | counter := to_unsigned(0, 32); 84 | end if; 85 | 86 | if locked_cycles = LOCK_CYCLES then 87 | receiver_hold <= '0'; 88 | if std_logic_vector(counter) >= sample_time_int and tx_ready = '1' then 89 | start_int <= '1'; 90 | counter := to_unsigned(0, 32); 91 | sample_time_int <= sample_time_int_next; 92 | 93 | 94 | -- Next receiver channel 95 | case rx_sw_int is 96 | when SW_RX1 => 97 | rx_sw_int <= SW_A; 98 | when SW_A => 99 | rx_sw_int <= SW_RX2; 100 | when SW_RX2 => 101 | rx_sw_int <= SW_B; 102 | when SW_B => 103 | rx_sw_int <= SW_RX1; 104 | when others => 105 | rx_sw_int <= SW_RX1; 106 | end case; 107 | 108 | else 109 | counter := counter + 1; 110 | end if; 111 | else 112 | locked_cycles := locked_cycles + to_unsigned(1, 16); 113 | end if; 114 | 115 | end if; 116 | end process; 117 | 118 | late_start : process(clk, start_int) 119 | begin 120 | if rising_edge(clk) then 121 | start <= start_int; 122 | end if; 123 | end process; 124 | 125 | sync_process : process(clk, lo_ld, source_ld) 126 | variable lo_sync2, source_sync2 : std_logic := '0'; 127 | begin 128 | 129 | if rising_edge(clk) then 130 | lo_ld_sync <= lo_sync2; 131 | source_ld_sync <= source_sync2; 132 | lo_sync2 := lo_ld; 133 | source_sync2 := source_ld; 134 | end if; 135 | end process; 136 | 137 | start_early <= start_int; 138 | rx_sw <= rx_sw_int; 139 | 140 | end Behavioral; 141 | -------------------------------------------------------------------------------- /fpga/vna/vna.srcs/sources_1/new/rx_sw_mux.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Company: 3 | -- Engineer: 4 | -- 5 | -- Create Date: 16.02.2017 19:01:41 6 | -- Design Name: 7 | -- Module Name: rx_sw_mux - Behavioral 8 | -- Project Name: 9 | -- Target Devices: 10 | -- Tool Versions: 11 | -- Description: 12 | -- 13 | -- Dependencies: 14 | -- 15 | -- Revision: 16 | -- Revision 0.01 - File Created 17 | -- Additional Comments: 18 | -- 19 | ---------------------------------------------------------------------------------- 20 | 21 | 22 | library IEEE; 23 | use IEEE.STD_LOGIC_1164.ALL; 24 | use work.vna_pkg.all; 25 | 26 | -- Uncomment the following library declaration if using 27 | -- arithmetic functions with Signed or Unsigned values 28 | --use IEEE.NUMERIC_STD.ALL; 29 | 30 | -- Uncomment the following library declaration if instantiating 31 | -- any Xilinx leaf cells in this code. 32 | --library UNISIM; 33 | --use UNISIM.VComponents.all; 34 | 35 | entity rx_sw_mux is 36 | Port ( rx_sw_receiver : in rx_sw_type; 37 | rx_sw_io : in STD_LOGIC_VECTOR(5 downto 0); 38 | rx_sw : out STD_LOGIC_VECTOR(5 downto 0); 39 | ctrl : in STD_LOGIC); 40 | end rx_sw_mux; 41 | 42 | architecture Behavioral of rx_sw_mux is 43 | 44 | signal rx_sw_receiver_vector : std_logic_vector(5 downto 0); 45 | begin 46 | 47 | rx_sw_receiver_vector <= "100010" when rx_sw_receiver = SW_RX1 else 48 | "100001" when rx_sw_receiver = SW_A else 49 | "011000" when rx_sw_receiver = SW_B else 50 | "010100" when rx_sw_receiver = SW_RX2 else 51 | "000000"; 52 | 53 | rx_sw <= rx_sw_io when ctrl = '1' else rx_sw_receiver_vector; 54 | 55 | end Behavioral; 56 | -------------------------------------------------------------------------------- /fpga/vna/vna.srcs/sources_1/new/rx_switch.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Company: 3 | -- Engineer: 4 | -- 5 | -- Create Date: 27.11.2016 18:43:45 6 | -- Design Name: 7 | -- Module Name: rx_switch - Behavioral 8 | -- Project Name: 9 | -- Target Devices: 10 | -- Tool Versions: 11 | -- Description: 12 | -- 13 | -- Dependencies: 14 | -- 15 | -- Revision: 16 | -- Revision 0.01 - File Created 17 | -- Additional Comments: 18 | -- 19 | ---------------------------------------------------------------------------------- 20 | 21 | 22 | library IEEE; 23 | use IEEE.STD_LOGIC_1164.ALL; 24 | 25 | -- Uncomment the following library declaration if using 26 | -- arithmetic functions with Signed or Unsigned values 27 | --use IEEE.NUMERIC_STD.ALL; 28 | 29 | -- Uncomment the following library declaration if instantiating 30 | -- any Xilinx leaf cells in this code. 31 | --library UNISIM; 32 | --use UNISIM.VComponents.all; 33 | 34 | entity rx_switch is 35 | -- Port ( ); 36 | end rx_switch; 37 | 38 | ---------------------------------------------------------------------------------- 39 | -- Company: 40 | -- Engineer: 41 | -- 42 | -- Create Date: 27.11.2016 15:33:21 43 | -- Design Name: 44 | -- Module Name: port_switch - Behavioral 45 | -- Project Name: 46 | -- Target Devices: 47 | -- Tool Versions: 48 | -- Description: 49 | -- 50 | -- Dependencies: 51 | -- 52 | -- Revision: 53 | -- Revision 0.01 - File Created 54 | -- Additional Comments: 55 | -- 56 | ---------------------------------------------------------------------------------- 57 | 58 | 59 | library IEEE; 60 | use IEEE.STD_LOGIC_1164.ALL; 61 | use work.vna_pkg.all; 62 | 63 | -- Uncomment the following library declaration if using 64 | -- arithmetic functions with Signed or Unsigned values 65 | --use IEEE.NUMERIC_STD.ALL; 66 | 67 | -- Uncomment the following library declaration if instantiating 68 | -- any Xilinx leaf cells in this code. 69 | --library UNISIM; 70 | --use UNISIM.VComponents.all; 71 | 72 | entity rx_switch is 73 | Port ( rx_port : in rx_port_type; 74 | term : in STD_LOGIC; 75 | swa_ctrl : out STD_LOGIC_VECTOR (1 downto 0); 76 | swb_ctrl : out STD_LOGIC_VECTOR (1 downto 0); 77 | swc_ctrl : out STD_LOGIC_VECTOR (1 downto 0)); 78 | end rx_switch; 79 | 80 | architecture Behavioral of rx_switch is 81 | 82 | begin 83 | 84 | process(rx_port, term) 85 | begin 86 | 87 | if term = '1' then 88 | swa_ctrl <= "00"; 89 | swb_ctrl <= "00"; 90 | swc_ctrl <= "00"; 91 | else 92 | if rx_port = P_A then 93 | swa_ctrl <= "10"; 94 | swb_ctrl <= "10"; 95 | swc_ctrl <= "01"; 96 | else 97 | swa_ctrl <= "01"; 98 | swb_ctrl <= "01"; 99 | swc_ctrl <= "10"; 100 | end if; 101 | end if; 102 | 103 | end process; 104 | 105 | end Behavioral; -------------------------------------------------------------------------------- /fpga/vna/vna.srcs/sources_1/new/source_agc.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Company: 3 | -- Engineer: 4 | -- 5 | -- Create Date: 06.12.2016 18:29:18 6 | -- Design Name: 7 | -- Module Name: source_agc - Behavioral 8 | -- Project Name: 9 | -- Target Devices: 10 | -- Tool Versions: 11 | -- Description: 12 | -- 13 | -- Dependencies: 14 | -- 15 | -- Revision: 16 | -- Revision 0.01 - File Created 17 | -- Additional Comments: 18 | -- 19 | ---------------------------------------------------------------------------------- 20 | 21 | 22 | library IEEE; 23 | use IEEE.STD_LOGIC_1164.ALL; 24 | use work.vna_pkg.all; 25 | 26 | -- Uncomment the following library declaration if using 27 | -- arithmetic functions with Signed or Unsigned values 28 | use IEEE.NUMERIC_STD.ALL; 29 | 30 | -- Uncomment the following library declaration if instantiating 31 | -- any Xilinx leaf cells in this code. 32 | --library UNISIM; 33 | --use UNISIM.VComponents.all; 34 | 35 | entity source_agc is 36 | Port ( clk : in STD_LOGIC; 37 | rst : in STD_LOGIC; 38 | locked : in STD_LOGIC; 39 | target : in STD_LOGIC_VECTOR (15 downto 0); 40 | xadc_vp : in STD_LOGIC; 41 | xadc_vn : in STD_LOGIC; 42 | adc_result : out STD_LOGIC_VECTOR (15 downto 0); 43 | att_data : out STD_LOGIC_VECTOR(9 downto 0); 44 | att_write : out STD_LOGIC; 45 | set_target : in STD_LOGIC); 46 | end source_agc; 47 | 48 | architecture Behavioral of source_agc is 49 | 50 | COMPONENT xadc_wiz_0 51 | PORT ( 52 | di_in : IN STD_LOGIC_VECTOR(15 DOWNTO 0); 53 | daddr_in : IN STD_LOGIC_VECTOR(6 DOWNTO 0); 54 | den_in : IN STD_LOGIC; 55 | dwe_in : IN STD_LOGIC; 56 | drdy_out : OUT STD_LOGIC; 57 | do_out : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); 58 | dclk_in : IN STD_LOGIC; 59 | reset_in : IN STD_LOGIC; 60 | vp_in : IN STD_LOGIC; 61 | vn_in : IN STD_LOGIC; 62 | user_temp_alarm_out : OUT STD_LOGIC; 63 | vccint_alarm_out : OUT STD_LOGIC; 64 | vccaux_alarm_out : OUT STD_LOGIC; 65 | ot_out : OUT STD_LOGIC; 66 | channel_out : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); 67 | eoc_out : OUT STD_LOGIC; 68 | alarm_out : OUT STD_LOGIC; 69 | eos_out : OUT STD_LOGIC; 70 | busy_out : OUT STD_LOGIC 71 | ); 72 | END COMPONENT; 73 | 74 | signal di_in, do_out : std_logic_vector(15 downto 0); 75 | signal daddr_in : std_logic_vector(6 downto 0); 76 | signal den_in, dwe_in : std_logic := '0'; 77 | signal drdy_out : std_logic; 78 | signal user_temp_alarm_out, vccint_alarm_out, vccaux_alarm_out, ot_out : std_logic; 79 | signal channel_out : std_logic_vector(4 downto 0); 80 | signal eoc_out, alarm_out, eos_out, busy_out : std_logic; 81 | 82 | 83 | signal target_int : std_logic_vector(15 downto 0) := std_logic_vector(to_unsigned(AGC_TARGET, 16)); 84 | 85 | begin 86 | 87 | xadc : xadc_wiz_0 88 | PORT MAP ( 89 | di_in => di_in, 90 | daddr_in => daddr_in, 91 | den_in => den_in, 92 | dwe_in => dwe_in, 93 | drdy_out => drdy_out, 94 | do_out => do_out, 95 | dclk_in => clk, 96 | reset_in => rst, 97 | vp_in => xadc_vp, 98 | vn_in => xadc_vn, 99 | user_temp_alarm_out => user_temp_alarm_out, 100 | vccint_alarm_out => vccint_alarm_out, 101 | vccaux_alarm_out => vccaux_alarm_out, 102 | ot_out => ot_out, 103 | channel_out => channel_out, 104 | eoc_out => eoc_out, 105 | alarm_out => alarm_out, 106 | eos_out => eos_out, 107 | busy_out => busy_out 108 | ); 109 | 110 | process(clk, rst, target, set_target) 111 | begin 112 | if rst = '1' then 113 | target_int <= std_logic_vector(to_unsigned(AGC_TARGET, 16)); 114 | elsif rising_edge(clk) then 115 | if set_target = '1' then 116 | target_int <= target; 117 | end if; 118 | end if; 119 | end process; 120 | 121 | process(clk, rst) 122 | begin 123 | if rst = '1' then 124 | -- 125 | elsif rising_edge(clk) then 126 | -- TODO: Intelligent calculation 127 | if drdy_out = '1' then 128 | 129 | end if; 130 | end if; 131 | end process; 132 | 133 | adc_result <= do_out; 134 | end Behavioral; 135 | -------------------------------------------------------------------------------- /fpga/vna/vna.srcs/sources_1/new/spi_write.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Company: 3 | -- Engineer: 4 | -- 5 | -- Create Date: 01.12.2016 18:06:25 6 | -- Design Name: 7 | -- Module Name: spi_write - Behavioral 8 | -- Project Name: 9 | -- Target Devices: 10 | -- Tool Versions: 11 | -- Description: 12 | -- 13 | -- Dependencies: 14 | -- 15 | -- Revision: 16 | -- Revision 0.01 - File Created 17 | -- Additional Comments: 18 | -- 19 | ---------------------------------------------------------------------------------- 20 | 21 | 22 | library IEEE; 23 | use IEEE.STD_LOGIC_1164.ALL; 24 | 25 | -- Uncomment the following library declaration if using 26 | -- arithmetic functions with Signed or Unsigned values 27 | use IEEE.NUMERIC_STD.ALL; 28 | 29 | -- Uncomment the following library declaration if instantiating 30 | -- any Xilinx leaf cells in this code. 31 | --library UNISIM; 32 | --use UNISIM.VComponents.all; 33 | 34 | entity spi_write is 35 | Generic (SPI_CLK_DIVIDER : integer := 1; 36 | DATA_LENGTH : integer := 8); 37 | Port ( clk : in STD_LOGIC; 38 | rst : in STD_LOGIC; 39 | spi_clk : out STD_LOGIC; 40 | spi_data : out STD_LOGIC; 41 | spi_cs : out STD_LOGIC; 42 | data_in : in STD_LOGIC_VECTOR (DATA_LENGTH-1 downto 0); 43 | data_in_valid : in STD_LOGIC; 44 | data_in_ack : out STD_LOGIC); 45 | end spi_write; 46 | 47 | architecture Behavioral of spi_write is 48 | 49 | constant SPI_CLOCK : unsigned(7 downto 0) := to_unsigned(SPI_CLK_DIVIDER, 8); 50 | signal spi_clk_int : std_logic := '0'; 51 | 52 | begin 53 | 54 | write_process : process(clk, rst, data_in, data_in_valid) 55 | variable bit_counter : unsigned(7 downto 0) := to_unsigned(DATA_LENGTH-1, 8); 56 | variable clk_counter : unsigned(7 downto 0) := to_unsigned(0, 8); 57 | variable done : std_logic := '0'; 58 | type spi_state is (S_START, S_CS, S_WRITE); 59 | variable state : spi_state := S_START; 60 | variable data_in_valid_prev : std_logic := '0'; 61 | begin 62 | 63 | if rst = '1' then 64 | bit_counter := to_unsigned(DATA_LENGTH-1, 8); 65 | spi_cs <= '1'; 66 | spi_clk_int <= '0'; 67 | data_in_ack <= '0'; 68 | spi_data <= '0'; 69 | done := '0'; 70 | state := S_START; 71 | data_in_valid_prev := '0'; 72 | elsif rising_edge(clk) then 73 | data_in_ack <= '0'; 74 | done := '0'; 75 | 76 | case state is 77 | 78 | when S_START => 79 | bit_counter := to_unsigned(DATA_LENGTH-1, 8); 80 | if data_in_valid = '1' then 81 | spi_cs <= '0'; 82 | state := S_CS; 83 | spi_data <= data_in(to_integer(unsigned(bit_counter))); 84 | end if; 85 | 86 | when S_WRITE => 87 | if data_in_valid = '1' then 88 | spi_cs <= '0'; 89 | spi_data <= data_in(to_integer(unsigned(bit_counter))); 90 | if clk_counter = to_unsigned(SPI_CLK_DIVIDER, 8) then 91 | if spi_clk_int = '0' then 92 | if bit_counter = to_unsigned(0, 8) then 93 | data_in_ack <= '1'; 94 | spi_cs <= '1'; 95 | done := '1'; 96 | state := S_START; 97 | else 98 | bit_counter := bit_counter - 1; 99 | end if; 100 | end if; 101 | if done = '0' then 102 | spi_clk_int <= not spi_clk_int; 103 | end if; 104 | else 105 | clk_counter := clk_counter + 1; 106 | end if; 107 | else 108 | spi_cs <= '1'; 109 | bit_counter := to_unsigned(DATA_LENGTH-1, 8); 110 | end if; 111 | 112 | when S_CS => 113 | -- Hold CS for one clock 114 | spi_cs <= '0'; 115 | spi_data <= data_in(to_integer(unsigned(bit_counter))); 116 | state := S_WRITE; 117 | 118 | when others => 119 | state := S_START; 120 | 121 | end case; 122 | end if; 123 | 124 | end process; 125 | 126 | spi_clk <= spi_clk_int; 127 | end Behavioral; 128 | -------------------------------------------------------------------------------- /fpga/vna/vna.srcs/sources_1/new/tx_mux.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Company: 3 | -- Engineer: 4 | -- 5 | -- Create Date: 12.02.2017 21:13:49 6 | -- Design Name: 7 | -- Module Name: tx_mux - Behavioral 8 | -- Project Name: 9 | -- Target Devices: 10 | -- Tool Versions: 11 | -- Description: 12 | -- 13 | -- Dependencies: 14 | -- 15 | -- Revision: 16 | -- Revision 0.01 - File Created 17 | -- Additional Comments: 18 | -- 19 | ---------------------------------------------------------------------------------- 20 | 21 | 22 | library IEEE; 23 | use IEEE.STD_LOGIC_1164.ALL; 24 | 25 | -- Uncomment the following library declaration if using 26 | -- arithmetic functions with Signed or Unsigned values 27 | --use IEEE.NUMERIC_STD.ALL; 28 | 29 | -- Uncomment the following library declaration if instantiating 30 | -- any Xilinx leaf cells in this code. 31 | --library UNISIM; 32 | --use UNISIM.VComponents.all; 33 | 34 | entity tx_mux is 35 | Port ( mux : in STD_LOGIC_VECTOR(1 downto 0); 36 | data_out : out STD_LOGIC_VECTOR (7 downto 0); 37 | data_valid : out STD_LOGIC; 38 | data_ack : in STD_LOGIC; 39 | samples_data :in STD_LOGIC_VECTOR (7 downto 0); 40 | samples_data_valid : in STD_LOGIC; 41 | samples_data_ack : out STD_LOGIC; 42 | iq_data :in STD_LOGIC_VECTOR (7 downto 0); 43 | iq_data_valid : in STD_LOGIC; 44 | iq_data_ack : out STD_LOGIC; 45 | io_data : in STD_LOGIC_VECTOR(7 downto 0); 46 | io_data_valid : in STD_LOGIC; 47 | io_data_ack : out STD_LOGIC; 48 | last_byte_iq : in STD_LOGIC; 49 | last_byte : out STD_LOGIC); 50 | end tx_mux; 51 | 52 | architecture Behavioral of tx_mux is 53 | 54 | begin 55 | 56 | data_out <= iq_data when mux = "00" else 57 | samples_data when mux = "01" else 58 | io_data; 59 | 60 | data_valid <= iq_data_valid when mux = "00" else 61 | samples_data_valid when mux = "01" else 62 | io_data_valid; 63 | 64 | last_byte <= last_byte_iq when mux = "00" else '0'; 65 | 66 | iq_data_ack <= data_ack when mux = "00" else '0'; 67 | samples_data_ack <= data_ack when mux = "01" else '0'; 68 | io_data_ack <= data_ack when mux = "10" else '0'; 69 | 70 | end Behavioral; 71 | -------------------------------------------------------------------------------- /fpga/vna/vna.srcs/sources_1/new/vna_pkg.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use ieee.numeric_std.all; 4 | 5 | package vna_pkg is 6 | 7 | type rx_sw_type is (SW_NONE, SW_RX1, SW_A, SW_RX2, SW_B); 8 | 9 | subtype byte is std_logic_vector(7 downto 0); 10 | 11 | constant ADC_WIDTH : natural := 14; 12 | constant IF_WIDTH : natural := 24; 13 | constant LO_WIDTH : integer := 14; 14 | constant IQ_ACC_WIDTH : natural := 56; 15 | constant CIC_OUT_WIDTH : natural := 32; 16 | 17 | constant IQ_BYTES : natural := IQ_ACC_WIDTH/8; 18 | 19 | constant COMM_START : std_logic_vector(7 downto 0) := "10101010"; 20 | 21 | -- Number of clock cycles to skip after reset 22 | -- Determined by the switch settling time 23 | constant SKIP_SAMPLES : integer := 30; 24 | 25 | constant AGC_TARGET : integer := 200; 26 | 27 | constant LOCK_CYCLES : integer := 12000; 28 | 29 | end vna_pkg; 30 | 31 | package body vna_pkg is 32 | end vna_pkg; 33 | -------------------------------------------------------------------------------- /fpga/vna_top.bit: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Ttl/vna2/2cf0efb22da56a168a7f07bf5e2c30631343997b/fpga/vna_top.bit -------------------------------------------------------------------------------- /hw/vna.pretty/1748LP18A075.kicad_mod: -------------------------------------------------------------------------------- 1 | (module 1748LP18A075 (layer F.Cu) (tedit 569A8F32) 2 | (fp_text reference REF** (at 1.9 1.9) (layer F.SilkS) 3 | (effects (font (size 0.6 0.6) (thickness 0.15))) 4 | ) 5 | (fp_text value 1748LP18A075 (at 1.8 -1.9) (layer F.Fab) 6 | (effects (font (size 0.6 0.6) (thickness 0.15))) 7 | ) 8 | (fp_line (start 0.2 0.8) (end 0.2 -0.8) (layer F.SilkS) (width 0.15)) 9 | (fp_line (start 0.2 -0.8) (end 3.4 -0.8) (layer F.SilkS) (width 0.15)) 10 | (fp_line (start 3.4 -0.8) (end 3.4 0.8) (layer F.SilkS) (width 0.15)) 11 | (fp_line (start 3.4 0.8) (end 0.2 0.8) (layer F.SilkS) (width 0.15)) 12 | (pad 1 smd rect (at 0 0) (size 0.6 1.15) (layers F.Cu F.Paste F.Mask)) 13 | (pad 2 smd rect (at 3.6 0) (size 0.6 1.15) (layers F.Cu F.Paste F.Mask)) 14 | (pad 3 smd rect (at 1.85 -0.7) (size 0.6 0.8) (layers F.Cu F.Paste F.Mask)) 15 | (pad 4 smd rect (at 1.85 0.7) (size 0.6 0.8) (layers F.Cu F.Paste F.Mask)) 16 | ) 17 | -------------------------------------------------------------------------------- /hw/vna.pretty/3550LP14A300.kicad_mod: -------------------------------------------------------------------------------- 1 | (module 3550LP14A300 (layer F.Cu) (tedit 56AC6C89) 2 | (fp_text reference REF** (at 0.5 2.4) (layer F.SilkS) 3 | (effects (font (size 0.6 0.6) (thickness 0.15))) 4 | ) 5 | (fp_text value 3550LP14A300 (at 0.1 -1.1) (layer F.Fab) 6 | (effects (font (size 0.6 0.6) (thickness 0.15))) 7 | ) 8 | (fp_line (start 0.4 1.6) (end 0.4 1.1) (layer F.SilkS) (width 0.15)) 9 | (fp_line (start 0 1.3) (end 0 -0.3) (layer F.SilkS) (width 0.15)) 10 | (fp_line (start 0 -0.3) (end 0.8 -0.3) (layer F.SilkS) (width 0.15)) 11 | (fp_line (start 0.8 -0.3) (end 0.8 1.3) (layer F.SilkS) (width 0.15)) 12 | (fp_line (start 0.8 1.3) (end 0 1.3) (layer F.SilkS) (width 0.15)) 13 | (pad 1 smd rect (at 0 0) (size 0.55 0.25) (layers F.Cu F.Paste F.Mask) 14 | (zone_connect 2)) 15 | (pad 2 smd rect (at 0 0.5) (size 0.55 0.25) (layers F.Cu F.Paste F.Mask) 16 | (zone_connect 2)) 17 | (pad 3 smd rect (at 0 1) (size 0.55 0.25) (layers F.Cu F.Paste F.Mask) 18 | (zone_connect 2)) 19 | (pad 4 smd rect (at 0.8 1) (size 0.55 0.25) (layers F.Cu F.Paste F.Mask) 20 | (zone_connect 2)) 21 | (pad 5 smd rect (at 0.8 0.5) (size 0.55 0.25) (layers F.Cu F.Paste F.Mask) 22 | (zone_connect 2)) 23 | (pad 6 smd rect (at 0.8 0) (size 0.55 0.25) (layers F.Cu F.Paste F.Mask) 24 | (zone_connect 2)) 25 | ) 26 | -------------------------------------------------------------------------------- /hw/vna.pretty/5400BL15B050E.kicad_mod: -------------------------------------------------------------------------------- 1 | (module 5400BL15B050E (layer F.Cu) (tedit 551F940E) 2 | (fp_text reference REF** (at 0 3.25) (layer F.SilkS) 3 | (effects (font (size 1 1) (thickness 0.15))) 4 | ) 5 | (fp_text value 5400BL15B050E (at 0.05 -4) (layer F.Fab) 6 | (effects (font (size 1 1) (thickness 0.15))) 7 | ) 8 | (fp_line (start -0.4 -0.3) (end -0.4 -1.6) (layer F.SilkS) (width 0.15)) 9 | (fp_line (start -0.4 -1.6) (end 1.6 -1.6) (layer F.SilkS) (width 0.15)) 10 | (fp_line (start 1.6 -1.6) (end 1.6 -0.3) (layer F.SilkS) (width 0.15)) 11 | (fp_line (start 1.6 -0.3) (end -0.4 -0.3) (layer F.SilkS) (width 0.15)) 12 | (fp_circle (center -0.5 -0.9) (end -0.4 -1) (layer F.SilkS) (width 0.15)) 13 | (pad 1 smd rect (at 0 0) (size 0.35 1) (layers F.Cu F.Paste F.Mask)) 14 | (pad 2 smd rect (at 0.65 0) (size 0.35 1) (layers F.Cu F.Paste F.Mask)) 15 | (pad 3 smd rect (at 1.3 0) (size 0.35 1) (layers F.Cu F.Paste F.Mask)) 16 | (pad 4 smd rect (at 1.3 -1.8) (size 0.35 1) (layers F.Cu F.Paste F.Mask)) 17 | (pad 5 smd rect (at 0.65 -1.8) (size 0.35 1) (layers F.Cu F.Paste F.Mask)) 18 | (pad 6 smd rect (at 0 -1.8) (size 0.35 1) (layers F.Cu F.Paste F.Mask)) 19 | ) 20 | -------------------------------------------------------------------------------- /hw/vna.pretty/5515LP15A730.kicad_mod: -------------------------------------------------------------------------------- 1 | (module 5515LP15A730 (layer F.Cu) (tedit 56AC6C5D) 2 | (fp_text reference REF** (at 0.225 1.625) (layer F.SilkS) 3 | (effects (font (size 0.6 0.6) (thickness 0.15))) 4 | ) 5 | (fp_text value 5515LP15A730 (at 0.325 -1.65) (layer F.Fab) 6 | (effects (font (size 0.6 0.6) (thickness 0.15))) 7 | ) 8 | (fp_circle (center 0.5 0) (end 0.55 -0.1) (layer F.SilkS) (width 0.15)) 9 | (fp_line (start -1 0.65) (end -1 -0.6) (layer F.SilkS) (width 0.15)) 10 | (fp_line (start -1 -0.6) (end 1 -0.6) (layer F.SilkS) (width 0.15)) 11 | (fp_line (start 1 -0.6) (end 1 0.65) (layer F.SilkS) (width 0.15)) 12 | (fp_line (start 1 0.65) (end -1 0.65) (layer F.SilkS) (width 0.15)) 13 | (pad 1 smd rect (at 0.65 -0.7) (size 0.35 0.6) (layers F.Cu F.Paste F.Mask) 14 | (zone_connect 2)) 15 | (pad 2 smd rect (at 0 -0.7) (size 0.35 0.6) (layers F.Cu F.Paste F.Mask) 16 | (zone_connect 2)) 17 | (pad 3 smd rect (at -0.65 -0.7) (size 0.35 0.6) (layers F.Cu F.Paste F.Mask) 18 | (zone_connect 2)) 19 | (pad 5 smd rect (at -0.65 0.7) (size 0.35 0.6) (layers F.Cu F.Paste F.Mask) 20 | (zone_connect 2)) 21 | (pad 6 smd rect (at 0 0.7) (size 0.35 0.6) (layers F.Cu F.Paste F.Mask) 22 | (zone_connect 2)) 23 | (pad 7 smd rect (at 0.65 0.7) (size 0.35 0.6) (layers F.Cu F.Paste F.Mask) 24 | (zone_connect 2)) 25 | (pad 4 smd rect (at -1.12 0 90) (size 0.35 0.6) (layers F.Cu F.Paste F.Mask) 26 | (zone_connect 2)) 27 | (pad 8 smd rect (at 1.12 0 90) (size 0.35 0.6) (layers F.Cu F.Paste F.Mask) 28 | (zone_connect 2)) 29 | ) 30 | -------------------------------------------------------------------------------- /hw/vna.pretty/ABMM.kicad_mod: -------------------------------------------------------------------------------- 1 | (module ABMM (layer F.Cu) (tedit 584D6D1A) 2 | (fp_text reference REF** (at 3.3 -1.3 90) (layer F.SilkS) 3 | (effects (font (size 0.7 0.7) (thickness 0.15))) 4 | ) 5 | (fp_text value ABMM (at 3.075 -4.625) (layer F.Fab) 6 | (effects (font (size 1 1) (thickness 0.15))) 7 | ) 8 | (fp_line (start -0.4 -3.9) (end 6.8 -3.9) (layer F.SilkS) (width 0.15)) 9 | (fp_line (start 6.8 -3.9) (end 6.8 1.5) (layer F.SilkS) (width 0.15)) 10 | (fp_line (start 6.8 1.5) (end -0.4 1.5) (layer F.SilkS) (width 0.15)) 11 | (fp_line (start -0.4 1.5) (end -0.4 -3.9) (layer F.SilkS) (width 0.15)) 12 | (pad 1 smd rect (at 0 0) (size 2.2 1.4) (layers F.Cu F.Paste F.Mask)) 13 | (pad 2 smd rect (at 6.3 0) (size 2.2 1.4) (layers F.Cu F.Paste F.Mask)) 14 | (pad 3 smd rect (at 6.3 -2.54) (size 2.2 1.4) (layers F.Cu F.Paste F.Mask)) 15 | (pad 4 smd rect (at 0 -2.54) (size 2.2 1.4) (layers F.Cu F.Paste F.Mask)) 16 | ) 17 | -------------------------------------------------------------------------------- /hw/vna.pretty/ASTRX-12.kicad_mod: -------------------------------------------------------------------------------- 1 | (module ASTRX-12 (layer F.Cu) (tedit 569A81B5) 2 | (fp_text reference REF** (at 0.1 2) (layer F.SilkS) 3 | (effects (font (size 0.7 0.7) (thickness 0.15))) 4 | ) 5 | (fp_text value ASTRX-12 (at -0.1 -1.9) (layer F.Fab) 6 | (effects (font (size 1 1) (thickness 0.15))) 7 | ) 8 | (fp_line (start -1.5 1.3) (end -1.5 0.6) (layer F.SilkS) (width 0.15)) 9 | (fp_line (start -1.5 1.3) (end -0.7 1.3) (layer F.SilkS) (width 0.15)) 10 | (fp_line (start -1.2 1) (end -1.2 -1) (layer F.SilkS) (width 0.15)) 11 | (fp_line (start -1.2 -1) (end 1.3 -1) (layer F.SilkS) (width 0.15)) 12 | (fp_line (start 1.3 -1) (end 1.3 1) (layer F.SilkS) (width 0.15)) 13 | (fp_line (start 1.3 1) (end -1.2 1) (layer F.SilkS) (width 0.15)) 14 | (pad 6 smd rect (at -1 -0.7) (size 0.63 0.84) (layers F.Cu F.Paste F.Mask)) 15 | (pad 1 smd rect (at -1 0.69) (size 0.63 0.84) (layers F.Cu F.Paste F.Mask)) 16 | (pad 3 smd rect (at 1.08 0.69) (size 0.63 0.84) (layers F.Cu F.Paste F.Mask)) 17 | (pad 4 smd rect (at 1.08 -0.7) (size 0.63 0.84) (layers F.Cu F.Paste F.Mask)) 18 | ) 19 | -------------------------------------------------------------------------------- /hw/vna.pretty/CNC-3220-10-0300-00.kicad_mod: -------------------------------------------------------------------------------- 1 | (module CNC-3220-10-0300-00 (layer F.Cu) (tedit 569BC5CA) 2 | (fp_text reference REF** (at 0.3 4.8) (layer F.SilkS) 3 | (effects (font (size 1 1) (thickness 0.15))) 4 | ) 5 | (fp_text value CNC-3220-10-0300-00 (at -1.1 -4.3) (layer F.Fab) 6 | (effects (font (size 1 1) (thickness 0.15))) 7 | ) 8 | (fp_line (start -1.3 -0.9) (end -0.6 -0.9) (layer F.SilkS) (width 0.15)) 9 | (fp_line (start -0.6 -0.9) (end -0.6 1) (layer F.SilkS) (width 0.15)) 10 | (fp_line (start -0.6 1) (end -1.3 1) (layer F.SilkS) (width 0.15)) 11 | (fp_line (start -2.4 -6.35) (end 2.7 -6.35) (layer F.SilkS) (width 0.15)) 12 | (fp_line (start 2.7 -6.35) (end 2.7 6.35) (layer F.SilkS) (width 0.15)) 13 | (fp_line (start 2.7 6.35) (end -2.4 6.35) (layer F.SilkS) (width 0.15)) 14 | (fp_line (start -2.4 6.35) (end -2.4 -6.35) (layer F.SilkS) (width 0.15)) 15 | (pad 1 smd rect (at -2.4 -2.5) (size 1.5 0.76) (layers F.Cu F.Paste F.Mask)) 16 | (pad 2 smd rect (at 2.4 -2.5) (size 1.5 0.76) (layers F.Cu F.Paste F.Mask)) 17 | (pad 3 smd rect (at -2.4 -1.23) (size 1.5 0.76) (layers F.Cu F.Paste F.Mask)) 18 | (pad 4 smd rect (at 2.4 -1.23) (size 1.5 0.76) (layers F.Cu F.Paste F.Mask)) 19 | (pad 5 smd rect (at -2.4 0.04) (size 1.5 0.76) (layers F.Cu F.Paste F.Mask)) 20 | (pad 6 smd rect (at 2.4 0.04) (size 1.5 0.76) (layers F.Cu F.Paste F.Mask)) 21 | (pad 7 smd rect (at -2.4 1.31) (size 1.5 0.76) (layers F.Cu F.Paste F.Mask)) 22 | (pad 8 smd rect (at 2.4 1.31) (size 1.5 0.76) (layers F.Cu F.Paste F.Mask)) 23 | (pad 9 smd rect (at -2.4 2.58) (size 1.5 0.76) (layers F.Cu F.Paste F.Mask)) 24 | (pad 10 smd rect (at 2.4 2.58) (size 1.5 0.76) (layers F.Cu F.Paste F.Mask)) 25 | ) 26 | -------------------------------------------------------------------------------- /hw/vna.pretty/CONSMA003.062.kicad_mod: -------------------------------------------------------------------------------- 1 | (module CONSMA003.062 (layer F.Cu) (tedit 587D0CE3) 2 | (fp_text reference CONSMA003.062 (at 0 7.62) (layer F.SilkS) 3 | (effects (font (size 1.5 1.5) (thickness 0.15))) 4 | ) 5 | (fp_text value VAL** (at 0 -7.62) (layer F.SilkS) hide 6 | (effects (font (size 1.5 1.5) (thickness 0.15))) 7 | ) 8 | (fp_line (start 12.25 4.5) (end 2.25 4.5) (layer Dwgs.User) (width 0.15)) 9 | (fp_line (start 12.25 -4.5) (end 12.25 4.5) (layer Dwgs.User) (width 0.15)) 10 | (fp_line (start 2.25 -4.5) (end 12.25 -4.5) (layer Dwgs.User) (width 0.15)) 11 | (fp_line (start 2.25 4.5) (end 2.25 -4.5) (layer Dwgs.User) (width 0.15)) 12 | (pad 2 thru_hole circle (at -1.75 2.1) (size 0.5 0.5) (drill 0.25) (layers *.Cu *.Mask F.SilkS) 13 | (zone_connect 2)) 14 | (pad 2 thru_hole circle (at -1.25 2.1) (size 0.5 0.5) (drill 0.25) (layers *.Cu *.Mask F.SilkS) 15 | (zone_connect 2)) 16 | (pad 2 thru_hole circle (at -0.75 2.1) (size 0.5 0.5) (drill 0.25) (layers *.Cu *.Mask F.SilkS) 17 | (zone_connect 2)) 18 | (pad 2 thru_hole circle (at -0.25 2.1) (size 0.5 0.5) (drill 0.25) (layers *.Cu *.Mask F.SilkS) 19 | (zone_connect 2)) 20 | (pad 2 thru_hole circle (at 0.25 2.1) (size 0.5 0.5) (drill 0.25) (layers *.Cu *.Mask F.SilkS) 21 | (zone_connect 2)) 22 | (pad 2 thru_hole circle (at 0.75 2.1) (size 0.5 0.5) (drill 0.25) (layers *.Cu *.Mask F.SilkS) 23 | (zone_connect 2)) 24 | (pad 2 thru_hole circle (at 1.25 2.1) (size 0.5 0.5) (drill 0.25) (layers *.Cu *.Mask F.SilkS) 25 | (zone_connect 2)) 26 | (pad 2 thru_hole circle (at 1.75 2.1) (size 0.5 0.5) (drill 0.25) (layers *.Cu *.Mask F.SilkS) 27 | (zone_connect 2)) 28 | (pad 2 thru_hole circle (at -1.75 -2.1) (size 0.5 0.5) (drill 0.25) (layers *.Cu *.Mask F.SilkS) 29 | (zone_connect 2)) 30 | (pad 2 thru_hole circle (at -1.25 -2.1) (size 0.5 0.5) (drill 0.25) (layers *.Cu *.Mask F.SilkS) 31 | (zone_connect 2)) 32 | (pad 2 thru_hole circle (at -0.75 -2.1) (size 0.5 0.5) (drill 0.25) (layers *.Cu *.Mask F.SilkS) 33 | (zone_connect 2)) 34 | (pad 2 thru_hole circle (at -0.25 -2.1) (size 0.5 0.5) (drill 0.25) (layers *.Cu *.Mask F.SilkS) 35 | (zone_connect 2)) 36 | (pad 2 thru_hole circle (at 0.25 -2.1) (size 0.5 0.5) (drill 0.25) (layers *.Cu *.Mask F.SilkS) 37 | (zone_connect 2)) 38 | (pad 2 thru_hole circle (at 0.75 -2.1) (size 0.5 0.5) (drill 0.25) (layers *.Cu *.Mask F.SilkS) 39 | (zone_connect 2)) 40 | (pad 2 thru_hole circle (at 1.25 -2.1) (size 0.5 0.5) (drill 0.25) (layers *.Cu *.Mask F.SilkS) 41 | (zone_connect 2)) 42 | (pad 2 thru_hole circle (at 1.75 -2.1) (size 0.5 0.5) (drill 0.25) (layers *.Cu *.Mask F.SilkS) 43 | (zone_connect 2)) 44 | (pad 2 smd rect (at 0 2.54) (size 4.06 1.52) (layers B.Cu B.Mask) 45 | (zone_connect 2) (thermal_width 4) (thermal_gap 0.3)) 46 | (pad 2 smd rect (at 0 -2.54) (size 4.06 1.52) (layers B.Cu B.Mask) 47 | (zone_connect 2) (thermal_width 4) (thermal_gap 0.3)) 48 | (pad 2 smd rect (at 0 2.54) (size 4.06 1.52) (layers F.Cu F.Mask) 49 | (zone_connect 2) (thermal_width 4) (thermal_gap 0.3)) 50 | (pad 2 smd rect (at 0 -2.54) (size 4.06 1.52) (layers F.Cu F.Mask) 51 | (zone_connect 2) (thermal_width 4) (thermal_gap 0.3)) 52 | (pad 1 smd rect (at 0 0) (size 4.06 1.52) (layers F.Cu F.Mask) 53 | (solder_mask_margin 0.5)) 54 | ) 55 | -------------------------------------------------------------------------------- /hw/vna.pretty/CTX520.kicad_mod: -------------------------------------------------------------------------------- 1 | (module CTX520 (layer F.Cu) (tedit 5648C943) 2 | (fp_text reference REF** (at 0 1.95) (layer F.SilkS) 3 | (effects (font (size 0.6 0.6) (thickness 0.15))) 4 | ) 5 | (fp_text value CTX520 (at -0.1 -1.65) (layer F.Fab) 6 | (effects (font (size 0.6 0.6) (thickness 0.125))) 7 | ) 8 | (fp_line (start -1.3 1) (end -1.3 -1) (layer F.SilkS) (width 0.15)) 9 | (fp_line (start -1.3 -1) (end 1.2 -1) (layer F.SilkS) (width 0.15)) 10 | (fp_line (start 1.2 -1) (end 1.2 1) (layer F.SilkS) (width 0.15)) 11 | (fp_line (start 1.2 1) (end -1.3 1) (layer F.SilkS) (width 0.15)) 12 | (pad 1 smd rect (at -1.05 0.75) (size 0.8 0.9) (layers F.Cu F.Paste F.Mask)) 13 | (pad 2 smd rect (at 0.96 0.75) (size 0.8 0.9) (layers F.Cu F.Paste F.Mask)) 14 | (pad 3 smd rect (at 0.95 -0.7) (size 0.8 0.9) (layers F.Cu F.Paste F.Mask)) 15 | (pad 4 smd rect (at -1.05 -0.7) (size 0.8 0.9) (layers F.Cu F.Paste F.Mask)) 16 | ) 17 | -------------------------------------------------------------------------------- /hw/vna.pretty/C_0402b.kicad_mod: -------------------------------------------------------------------------------- 1 | (module C_0402b (layer F.Cu) (tedit 55A40188) 2 | (descr "Capacitor SMD 0402, reflow soldering, AVX (see smccp.pdf)") 3 | (tags "capacitor 0402") 4 | (attr smd) 5 | (fp_text reference REF** (at 0 -1.7) (layer F.SilkS) 6 | (effects (font (size 0.5 0.5) (thickness 0.125))) 7 | ) 8 | (fp_text value C_0402 (at 0 1.7) (layer F.Fab) 9 | (effects (font (size 1 1) (thickness 0.15))) 10 | ) 11 | (fp_line (start -1.15 -0.6) (end 1.15 -0.6) (layer F.CrtYd) (width 0.05)) 12 | (fp_line (start -1.15 0.6) (end 1.15 0.6) (layer F.CrtYd) (width 0.05)) 13 | (fp_line (start -1.15 -0.6) (end -1.15 0.6) (layer F.CrtYd) (width 0.05)) 14 | (fp_line (start 1.15 -0.6) (end 1.15 0.6) (layer F.CrtYd) (width 0.05)) 15 | (fp_line (start 0.25 -0.475) (end -0.25 -0.475) (layer F.SilkS) (width 0.15)) 16 | (fp_line (start -0.25 0.475) (end 0.25 0.475) (layer F.SilkS) (width 0.15)) 17 | (pad 1 smd rect (at -0.55 0) (size 0.6 0.5) (layers F.Cu F.Paste F.Mask)) 18 | (pad 2 smd rect (at 0.55 0) (size 0.6 0.5) (layers F.Cu F.Paste F.Mask)) 19 | (model Capacitors_SMD.3dshapes/C_0402.wrl 20 | (at (xyz 0 0 0)) 21 | (scale (xyz 1 1 1)) 22 | (rotate (xyz 0 0 0)) 23 | ) 24 | ) 25 | -------------------------------------------------------------------------------- /hw/vna.pretty/C_0603b.kicad_mod: -------------------------------------------------------------------------------- 1 | (module C_0603b (layer F.Cu) (tedit 55A401E5) 2 | (descr "Capacitor SMD 0603, reflow soldering, AVX (see smccp.pdf)") 3 | (tags "capacitor 0603") 4 | (attr smd) 5 | (fp_text reference REF** (at 0 -1.425) (layer F.SilkS) 6 | (effects (font (size 0.5 0.5) (thickness 0.125))) 7 | ) 8 | (fp_text value C_0603 (at 0 1.9) (layer F.Fab) 9 | (effects (font (size 1 1) (thickness 0.15))) 10 | ) 11 | (fp_line (start -1.45 -0.75) (end 1.45 -0.75) (layer F.CrtYd) (width 0.05)) 12 | (fp_line (start -1.45 0.75) (end 1.45 0.75) (layer F.CrtYd) (width 0.05)) 13 | (fp_line (start -1.45 -0.75) (end -1.45 0.75) (layer F.CrtYd) (width 0.05)) 14 | (fp_line (start 1.45 -0.75) (end 1.45 0.75) (layer F.CrtYd) (width 0.05)) 15 | (fp_line (start -0.35 -0.6) (end 0.35 -0.6) (layer F.SilkS) (width 0.15)) 16 | (fp_line (start 0.35 0.6) (end -0.35 0.6) (layer F.SilkS) (width 0.15)) 17 | (pad 1 smd rect (at -0.75 0) (size 0.8 0.75) (layers F.Cu F.Paste F.Mask)) 18 | (pad 2 smd rect (at 0.75 0) (size 0.8 0.75) (layers F.Cu F.Paste F.Mask)) 19 | (model Capacitors_SMD.3dshapes/C_0603.wrl 20 | (at (xyz 0 0 0)) 21 | (scale (xyz 1 1 1)) 22 | (rotate (xyz 0 0 0)) 23 | ) 24 | ) 25 | -------------------------------------------------------------------------------- /hw/vna.pretty/C_0805b.kicad_mod: -------------------------------------------------------------------------------- 1 | (module C_0805b (layer F.Cu) (tedit 55A401FA) 2 | (descr "Capacitor SMD 0805, reflow soldering, AVX (see smccp.pdf)") 3 | (tags "capacitor 0805") 4 | (attr smd) 5 | (fp_text reference REF** (at 0 -1.675) (layer F.SilkS) 6 | (effects (font (size 0.5 0.5) (thickness 0.125))) 7 | ) 8 | (fp_text value C_0805 (at 0 2.1) (layer F.Fab) 9 | (effects (font (size 1 1) (thickness 0.15))) 10 | ) 11 | (fp_line (start -1.8 -1) (end 1.8 -1) (layer F.CrtYd) (width 0.05)) 12 | (fp_line (start -1.8 1) (end 1.8 1) (layer F.CrtYd) (width 0.05)) 13 | (fp_line (start -1.8 -1) (end -1.8 1) (layer F.CrtYd) (width 0.05)) 14 | (fp_line (start 1.8 -1) (end 1.8 1) (layer F.CrtYd) (width 0.05)) 15 | (fp_line (start 0.5 -0.85) (end -0.5 -0.85) (layer F.SilkS) (width 0.15)) 16 | (fp_line (start -0.5 0.85) (end 0.5 0.85) (layer F.SilkS) (width 0.15)) 17 | (pad 1 smd rect (at -1 0) (size 1 1.25) (layers F.Cu F.Paste F.Mask)) 18 | (pad 2 smd rect (at 1 0) (size 1 1.25) (layers F.Cu F.Paste F.Mask)) 19 | (model Capacitors_SMD.3dshapes/C_0805.wrl 20 | (at (xyz 0 0 0)) 21 | (scale (xyz 1 1 1)) 22 | (rotate (xyz 0 0 0)) 23 | ) 24 | ) 25 | -------------------------------------------------------------------------------- /hw/vna.pretty/DFN-8-1EP_2x2mm_Pitch0.5mm.kicad_mod: -------------------------------------------------------------------------------- 1 | (module DFN-8-1EP_2x2mm_Pitch0.5mm (layer F.Cu) (tedit 56A1373B) 2 | (descr "DFN8 2x2, 0.5P; CASE 506CN (see ON Semiconductor 506CN.PDF)") 3 | (tags "DFN 0.5") 4 | (attr smd) 5 | (fp_text reference REF** (at -0.05 -2.075) (layer F.SilkS) 6 | (effects (font (size 1 1) (thickness 0.15))) 7 | ) 8 | (fp_text value DFN-8-1EP_2x2mm_Pitch0.5mm (at -0.05 2.075) (layer F.Fab) 9 | (effects (font (size 1 1) (thickness 0.15))) 10 | ) 11 | (fp_line (start -1.45 -1.35) (end -1.45 1.35) (layer F.CrtYd) (width 0.05)) 12 | (fp_line (start 1.35 -1.35) (end 1.35 1.35) (layer F.CrtYd) (width 0.05)) 13 | (fp_line (start -1.45 -1.35) (end 1.35 -1.35) (layer F.CrtYd) (width 0.05)) 14 | (fp_line (start -1.45 1.35) (end 1.35 1.35) (layer F.CrtYd) (width 0.05)) 15 | (fp_line (start -0.65 1.15) (end 0.65 1.15) (layer F.SilkS) (width 0.15)) 16 | (fp_line (start -1.225 -1.15) (end 0.65 -1.15) (layer F.SilkS) (width 0.15)) 17 | (pad 1 smd rect (at -0.95 -0.75) (size 0.5 0.28) (layers F.Cu F.Paste F.Mask)) 18 | (pad 2 smd rect (at -0.95 -0.25) (size 0.5 0.28) (layers F.Cu F.Paste F.Mask)) 19 | (pad 3 smd rect (at -0.95 0.25) (size 0.5 0.28) (layers F.Cu F.Paste F.Mask)) 20 | (pad 4 smd rect (at -0.95 0.75) (size 0.5 0.28) (layers F.Cu F.Paste F.Mask)) 21 | (pad 5 smd rect (at 0.95 0.75) (size 0.5 0.28) (layers F.Cu F.Paste F.Mask)) 22 | (pad 6 smd rect (at 0.95 0.25) (size 0.5 0.28) (layers F.Cu F.Paste F.Mask)) 23 | (pad 7 smd rect (at 0.95 -0.25) (size 0.5 0.28) (layers F.Cu F.Paste F.Mask)) 24 | (pad 8 smd rect (at 0.95 -0.75) (size 0.5 0.28) (layers F.Cu F.Paste F.Mask)) 25 | (pad 9 smd rect (at 0 0.44) (size 1.06 0.88) (layers F.Cu F.Paste F.Mask) 26 | (solder_paste_margin_ratio -0.2)) 27 | (pad 9 smd rect (at 0 -0.44) (size 1.06 0.88) (layers F.Cu F.Paste F.Mask) 28 | (solder_paste_margin_ratio -0.2)) 29 | (model Housings_DFN_QFN.3dshapes/DFN-8-1EP_2x2mm_Pitch0.5mm.wrl 30 | (at (xyz 0 0 0)) 31 | (scale (xyz 1 1 1)) 32 | (rotate (xyz 0 0 0)) 33 | ) 34 | ) 35 | -------------------------------------------------------------------------------- /hw/vna.pretty/DFN-8.kicad_mod: -------------------------------------------------------------------------------- 1 | (module DFN-8 (layer F.Cu) (tedit 584D633D) 2 | (descr "DFN8 2x2, 0.5P; CASE 506CN (see ON Semiconductor 506CN.PDF)") 3 | (tags "DFN 0.5") 4 | (attr smd) 5 | (fp_text reference REF** (at -0.05 -2.075) (layer F.SilkS) 6 | (effects (font (size 1 1) (thickness 0.15))) 7 | ) 8 | (fp_text value DFN-8-1EP_2x2mm_Pitch0.5mm (at -0.05 2.075) (layer F.Fab) 9 | (effects (font (size 1 1) (thickness 0.15))) 10 | ) 11 | (fp_line (start -1.45 -1.35) (end -1.45 1.35) (layer F.CrtYd) (width 0.05)) 12 | (fp_line (start 1.35 -1.35) (end 1.35 1.35) (layer F.CrtYd) (width 0.05)) 13 | (fp_line (start -1.45 -1.35) (end 1.35 -1.35) (layer F.CrtYd) (width 0.05)) 14 | (fp_line (start -1.45 1.35) (end 1.35 1.35) (layer F.CrtYd) (width 0.05)) 15 | (fp_line (start -0.65 1.15) (end 0.65 1.15) (layer F.SilkS) (width 0.15)) 16 | (fp_line (start -1.225 -1.15) (end 0.65 -1.15) (layer F.SilkS) (width 0.15)) 17 | (pad 1 smd rect (at -0.95 -0.75) (size 0.5 0.28) (layers F.Cu F.Paste F.Mask)) 18 | (pad 2 smd rect (at -0.95 -0.25) (size 0.5 0.28) (layers F.Cu F.Paste F.Mask)) 19 | (pad 3 smd rect (at -0.95 0.25) (size 0.5 0.28) (layers F.Cu F.Paste F.Mask)) 20 | (pad 4 smd rect (at -0.95 0.75) (size 0.5 0.28) (layers F.Cu F.Paste F.Mask)) 21 | (pad 5 smd rect (at 0.95 0.75) (size 0.5 0.28) (layers F.Cu F.Paste F.Mask)) 22 | (pad 6 smd rect (at 0.95 0.25) (size 0.5 0.28) (layers F.Cu F.Paste F.Mask)) 23 | (pad 7 smd rect (at 0.95 -0.25) (size 0.5 0.28) (layers F.Cu F.Paste F.Mask)) 24 | (pad 8 smd rect (at 0.95 -0.75) (size 0.5 0.28) (layers F.Cu F.Paste F.Mask)) 25 | (pad EP smd rect (at 0 0.325) (size 0.9 0.65) (layers F.Cu F.Paste F.Mask) 26 | (solder_paste_margin_ratio -0.2)) 27 | (pad EP smd rect (at 0 -0.325) (size 0.9 0.65) (layers F.Cu F.Paste F.Mask) 28 | (solder_paste_margin_ratio -0.2)) 29 | (model Housings_DFN_QFN.3dshapes/DFN-8-1EP_2x2mm_Pitch0.5mm.wrl 30 | (at (xyz 0 0 0)) 31 | (scale (xyz 1 1 1)) 32 | (rotate (xyz 0 0 0)) 33 | ) 34 | ) 35 | -------------------------------------------------------------------------------- /hw/vna.pretty/EJ508A.kicad_mod: -------------------------------------------------------------------------------- 1 | (module EJ508A (layer F.Cu) (tedit 55787BCC) 2 | (fp_text reference REF** (at -4.4 3.5) (layer F.SilkS) 3 | (effects (font (size 1 1) (thickness 0.15))) 4 | ) 5 | (fp_text value EJ508A (at -0.7 -7.6) (layer F.Fab) 6 | (effects (font (size 1 1) (thickness 0.15))) 7 | ) 8 | (fp_line (start -6.5 7.7) (end -6.5 4.9) (layer F.SilkS) (width 0.15)) 9 | (fp_line (start -6.5 4.9) (end -2.9 4.9) (layer F.SilkS) (width 0.15)) 10 | (fp_line (start -2.9 4.9) (end -2.9 7.7) (layer F.SilkS) (width 0.15)) 11 | (fp_line (start -9 -6.7) (end 0 -6.7) (layer F.SilkS) (width 0.15)) 12 | (fp_line (start 0 7.7) (end -9 7.7) (layer F.SilkS) (width 0.15)) 13 | (fp_line (start -9 7.7) (end -9 -6.7) (layer F.SilkS) (width 0.15)) 14 | (fp_line (start 0 -6.7) (end 0 7.7) (layer F.SilkS) (width 0.15)) 15 | (pad 3 thru_hole circle (at 0 -3) (size 4.2 4.2) (drill 3.05) (layers *.Cu *.Mask F.SilkS)) 16 | (pad 1 thru_hole circle (at -5.9 -6) (size 4.6 4.6) (drill 3.56) (layers *.Cu *.Mask F.SilkS)) 17 | (pad 2 thru_hole circle (at -5.9 0) (size 4.2 4.2) (drill 3.05) (layers *.Cu *.Mask F.SilkS)) 18 | ) 19 | -------------------------------------------------------------------------------- /hw/vna.pretty/EVP-AWBA2A.kicad_mod: -------------------------------------------------------------------------------- 1 | (module EVP-AWBA2A (layer F.Cu) (tedit 5582E39A) 2 | (fp_text reference REF** (at 1.5 2.1) (layer F.SilkS) 3 | (effects (font (size 1 1) (thickness 0.15))) 4 | ) 5 | (fp_text value EVP-AWBA2A (at 1 -1.9) (layer F.Fab) 6 | (effects (font (size 1 1) (thickness 0.15))) 7 | ) 8 | (fp_line (start 0.1 1) (end 0.1 -1) (layer F.SilkS) (width 0.15)) 9 | (fp_line (start 0.1 -1) (end 3.1 -1) (layer F.SilkS) (width 0.15)) 10 | (fp_line (start 3.1 -1) (end 3.1 1) (layer F.SilkS) (width 0.15)) 11 | (fp_line (start 3.1 1) (end 0.1 1) (layer F.SilkS) (width 0.15)) 12 | (pad 1 smd rect (at 0 0) (size 0.55 1.5) (layers F.Cu F.Mask)) 13 | (pad 2 smd rect (at 3.25 0) (size 0.55 1.5) (layers F.Cu F.Mask)) 14 | (pad 2 smd rect (at 3.25 -0.4) (size 0.55 0.5) (layers F.Cu F.Paste F.Mask)) 15 | (pad 2 smd rect (at 3.25 0.5) (size 0.55 0.5) (layers F.Cu F.Paste F.Mask)) 16 | (pad 1 smd rect (at 0 -0.5) (size 0.55 0.5) (layers F.Cu F.Paste F.Mask)) 17 | (pad 1 smd rect (at 0 0.5) (size 0.55 0.5) (layers F.Cu F.Paste F.Mask)) 18 | ) 19 | -------------------------------------------------------------------------------- /hw/vna.pretty/KT2520K.kicad_mod: -------------------------------------------------------------------------------- 1 | (module KT2520K (layer F.Cu) (tedit 584D64F8) 2 | (fp_text reference REF** (at 0 2.35) (layer F.SilkS) 3 | (effects (font (size 0.7 0.7) (thickness 0.15))) 4 | ) 5 | (fp_text value KT2520K (at 0 -2.475) (layer F.Fab) 6 | (effects (font (size 1 1) (thickness 0.15))) 7 | ) 8 | (fp_line (start -1.275 -1.025) (end 1.225 -1.025) (layer F.SilkS) (width 0.15)) 9 | (fp_line (start 1.225 -1.025) (end 1.225 0.975) (layer F.SilkS) (width 0.15)) 10 | (fp_line (start 1.225 0.975) (end -1.275 0.975) (layer F.SilkS) (width 0.15)) 11 | (fp_line (start -1.275 0.975) (end -1.275 -1.025) (layer F.SilkS) (width 0.15)) 12 | (fp_line (start -1.775 0.85) (end -1.775 1.4) (layer F.SilkS) (width 0.15)) 13 | (fp_line (start -1.775 1.45) (end -1.125 1.45) (layer F.SilkS) (width 0.15)) 14 | (pad 1 smd rect (at -1.175 0.7) (size 0.5 0.825) (layers F.Cu F.Paste F.Mask)) 15 | (pad 2 smd rect (at -0.025 0.9) (size 0.7 0.43) (layers F.Cu F.Paste F.Mask)) 16 | (pad 3 smd rect (at 1.125 0.7) (size 0.5 0.825) (layers F.Cu F.Paste F.Mask)) 17 | (pad 4 smd rect (at 1.125 -0.775) (size 0.5 0.825) (layers F.Cu F.Paste F.Mask)) 18 | (pad 5 smd rect (at -0.025 -0.975) (size 0.7 0.43) (layers F.Cu F.Paste F.Mask)) 19 | (pad 6 smd rect (at -1.175 -0.775) (size 0.5 0.825) (layers F.Cu F.Paste F.Mask)) 20 | ) 21 | -------------------------------------------------------------------------------- /hw/vna.pretty/LED_0603.kicad_mod: -------------------------------------------------------------------------------- 1 | (module LED_0603 (layer F.Cu) (tedit 57404998) 2 | (descr "Capacitor SMD 0603, reflow soldering, AVX (see smccp.pdf)") 3 | (tags "capacitor 0603") 4 | (attr smd) 5 | (fp_text reference D4 (at -2.21 0.05) (layer F.SilkS) 6 | (effects (font (size 0.5 0.5) (thickness 0.125))) 7 | ) 8 | (fp_text value LED (at 0 1.9) (layer F.Fab) 9 | (effects (font (size 1 1) (thickness 0.15))) 10 | ) 11 | (fp_line (start 0.35 -0.6) (end -0.25 0) (layer F.SilkS) (width 0.15)) 12 | (fp_line (start -0.25 0) (end 0.35 0.6) (layer F.SilkS) (width 0.15)) 13 | (fp_line (start -1.45 -0.75) (end 1.45 -0.75) (layer F.CrtYd) (width 0.05)) 14 | (fp_line (start -1.45 0.75) (end 1.45 0.75) (layer F.CrtYd) (width 0.05)) 15 | (fp_line (start -1.45 -0.75) (end -1.45 0.75) (layer F.CrtYd) (width 0.05)) 16 | (fp_line (start 1.45 -0.75) (end 1.45 0.75) (layer F.CrtYd) (width 0.05)) 17 | (fp_line (start -0.35 -0.6) (end 0.35 -0.6) (layer F.SilkS) (width 0.15)) 18 | (fp_line (start 0.35 0.6) (end -0.35 0.6) (layer F.SilkS) (width 0.15)) 19 | (pad 1 smd rect (at -0.75 0) (size 0.8 0.75) (layers F.Cu F.Paste F.Mask)) 20 | (pad 2 smd rect (at 0.75 0) (size 0.8 0.75) (layers F.Cu F.Paste F.Mask)) 21 | (model Capacitors_SMD.3dshapes/C_0603.wrl 22 | (at (xyz 0 0 0)) 23 | (scale (xyz 1 1 1)) 24 | (rotate (xyz 0 0 0)) 25 | ) 26 | ) 27 | -------------------------------------------------------------------------------- /hw/vna.pretty/LP0603A0902.kicad_mod: -------------------------------------------------------------------------------- 1 | (module LP0603A0902 (layer F.Cu) (tedit 56AC6C42) 2 | (fp_text reference U17 (at -0.048 1.284) (layer F.SilkS) 3 | (effects (font (size 0.7 0.7) (thickness 0.15))) 4 | ) 5 | (fp_text value LP0603A1880ANTR (at -0.6 -1.375) (layer F.Fab) 6 | (effects (font (size 1 1) (thickness 0.15))) 7 | ) 8 | (fp_line (start -0.775 0.425) (end -0.775 -0.425) (layer F.SilkS) (width 0.15)) 9 | (fp_line (start -0.775 -0.425) (end 0.825 -0.425) (layer F.SilkS) (width 0.15)) 10 | (fp_line (start 0.825 -0.425) (end 0.825 0.425) (layer F.SilkS) (width 0.15)) 11 | (fp_line (start 0.825 0.425) (end -0.775 0.425) (layer F.SilkS) (width 0.15)) 12 | (pad 1 smd rect (at -0.6 0.35) (size 0.5 0.4) (layers F.Cu F.Paste F.Mask) 13 | (zone_connect 2)) 14 | (pad 2 smd rect (at 0.65 0.35) (size 0.5 0.4) (layers F.Cu F.Paste F.Mask) 15 | (zone_connect 2)) 16 | (pad 3 smd rect (at 0.65 -0.35) (size 0.5 0.4) (layers F.Cu F.Paste F.Mask) 17 | (zone_connect 2)) 18 | (pad 4 smd rect (at -0.6 -0.35) (size 0.5 0.4) (layers F.Cu F.Paste F.Mask) 19 | (zone_connect 2)) 20 | ) 21 | -------------------------------------------------------------------------------- /hw/vna.pretty/MLPD-10.kicad_mod: -------------------------------------------------------------------------------- 1 | (module MLPD-10 (layer F.Cu) (tedit 56A3D053) 2 | (fp_text reference REF** (at 0.3 2.1) (layer F.SilkS) 3 | (effects (font (size 0.6 0.6) (thickness 0.15))) 4 | ) 5 | (fp_text value MLPD-10 (at 0.2 -2.1) (layer F.Fab) 6 | (effects (font (size 0.6 0.6) (thickness 0.15))) 7 | ) 8 | (fp_line (start -0.6 -1.7) (end -1.5 -1.7) (layer F.SilkS) (width 0.15)) 9 | (fp_line (start -1 1.5) (end -1 -1.5) (layer F.SilkS) (width 0.15)) 10 | (fp_line (start -1 -1.5) (end 1 -1.5) (layer F.SilkS) (width 0.15)) 11 | (fp_line (start 1 -1.5) (end 1 1.5) (layer F.SilkS) (width 0.15)) 12 | (fp_line (start 1 1.5) (end -1 1.5) (layer F.SilkS) (width 0.15)) 13 | (pad 1 smd rect (at -0.875 -1) (size 0.55 0.25) (layers F.Cu F.Paste F.Mask)) 14 | (pad 2 smd rect (at -0.875 -0.5) (size 0.55 0.25) (layers F.Cu F.Paste F.Mask)) 15 | (pad 3 smd rect (at -0.875 0) (size 0.55 0.25) (layers F.Cu F.Paste F.Mask)) 16 | (pad 4 smd rect (at -0.875 0.5) (size 0.55 0.25) (layers F.Cu F.Paste F.Mask)) 17 | (pad 5 smd rect (at -0.875 1) (size 0.55 0.25) (layers F.Cu F.Paste F.Mask)) 18 | (pad 6 smd rect (at 0.875 1) (size 0.55 0.25) (layers F.Cu F.Paste F.Mask)) 19 | (pad 7 smd rect (at 0.875 0.5) (size 0.55 0.25) (layers F.Cu F.Paste F.Mask)) 20 | (pad 8 smd rect (at 0.875 0) (size 0.55 0.25) (layers F.Cu F.Paste F.Mask)) 21 | (pad 9 smd rect (at 0.875 -0.5) (size 0.55 0.25) (layers F.Cu F.Paste F.Mask)) 22 | (pad 10 smd rect (at 0.875 -1) (size 0.55 0.25) (layers F.Cu F.Paste F.Mask)) 23 | (pad EP smd rect (at 0 0) (size 0.76 2.4) (layers F.Cu F.Paste F.Mask)) 24 | (pad EP thru_hole circle (at 0 0) (size 0.55 0.55) (drill 0.3) (layers *.Cu) 25 | (zone_connect 2)) 26 | (pad EP thru_hole circle (at 0 -0.9) (size 0.55 0.55) (drill 0.3) (layers *.Cu) 27 | (zone_connect 2)) 28 | (pad EP thru_hole circle (at 0 0.9) (size 0.55 0.55) (drill 0.3) (layers *.Cu) 29 | (zone_connect 2)) 30 | ) 31 | -------------------------------------------------------------------------------- /hw/vna.pretty/MSOP-8.kicad_mod: -------------------------------------------------------------------------------- 1 | (module MSOP-8 (layer F.Cu) (tedit 53CEA007) 2 | (fp_text reference MSOP-8 (at -1.95 -2.6 90) (layer F.SilkS) 3 | (effects (font (size 1 1) (thickness 0.15))) 4 | ) 5 | (fp_text value VAL** (at 3.9 -2.6 90) (layer F.SilkS) 6 | (effects (font (size 1 1) (thickness 0.15))) 7 | ) 8 | (fp_circle (center -0.1 -1.3) (end 0.1 -1.4) (layer F.SilkS) (width 0.15)) 9 | (fp_line (start -0.5 -0.85) (end -0.5 -3.85) (layer F.SilkS) (width 0.15)) 10 | (fp_line (start -0.5 -3.85) (end 2.5 -3.85) (layer F.SilkS) (width 0.15)) 11 | (fp_line (start 2.5 -3.85) (end 2.5 -0.85) (layer F.SilkS) (width 0.15)) 12 | (fp_line (start 2.5 -0.85) (end -0.5 -0.85) (layer F.SilkS) (width 0.15)) 13 | (pad 1 smd rect (at 0 0) (size 0.45 1.1) (layers F.Cu F.Paste F.Mask)) 14 | (pad 2 smd rect (at 0.65 0) (size 0.45 1.1) (layers F.Cu F.Paste F.Mask)) 15 | (pad 3 smd rect (at 1.3 0) (size 0.45 1.1) (layers F.Cu F.Paste F.Mask)) 16 | (pad 4 smd rect (at 1.95 0) (size 0.45 1.1) (layers F.Cu F.Paste F.Mask)) 17 | (pad 5 smd rect (at 1.95 -4.66) (size 0.45 1.1) (layers F.Cu F.Paste F.Mask)) 18 | (pad 6 smd rect (at 1.3 -4.66) (size 0.45 1.1) (layers F.Cu F.Paste F.Mask)) 19 | (pad 7 smd rect (at 0.65 -4.66) (size 0.45 1.1) (layers F.Cu F.Paste F.Mask)) 20 | (pad 8 smd rect (at 0 -4.66) (size 0.45 1.1) (layers F.Cu F.Paste F.Mask)) 21 | ) 22 | -------------------------------------------------------------------------------- /hw/vna.pretty/MountingHole_3.2mm_M3_Pad_Via_mod.kicad_mod: -------------------------------------------------------------------------------- 1 | (module MountingHole_3.2mm_M3_Pad_Via_mod (layer F.Cu) (tedit 586E9C4D) 2 | (descr "Mounting Hole 3.2mm, M3") 3 | (tags "mounting hole 3.2mm m3") 4 | (fp_text reference P17 (at 0 -4.2) (layer F.SilkS) 5 | (effects (font (size 1 1) (thickness 0.15))) 6 | ) 7 | (fp_text value CONN_01X01 (at 0 4.2) (layer F.Fab) 8 | (effects (font (size 1 1) (thickness 0.15))) 9 | ) 10 | (fp_circle (center 0 0) (end 3.45 0) (layer F.CrtYd) (width 0.05)) 11 | (fp_circle (center 0 0) (end 3.2 0) (layer Cmts.User) (width 0.15)) 12 | (pad 1 thru_hole circle (at 1.697056 -1.697056) (size 0.6 0.6) (drill 0.5) (layers *.Cu *.Mask) 13 | (zone_connect 2)) 14 | (pad 1 thru_hole circle (at 0 -2.4) (size 0.6 0.6) (drill 0.5) (layers *.Cu *.Mask) 15 | (zone_connect 2)) 16 | (pad 1 thru_hole circle (at -1.697056 -1.697056) (size 0.6 0.6) (drill 0.5) (layers *.Cu *.Mask) 17 | (zone_connect 2)) 18 | (pad 1 thru_hole circle (at -2.4 0) (size 0.6 0.6) (drill 0.5) (layers *.Cu *.Mask) 19 | (zone_connect 2)) 20 | (pad 1 thru_hole circle (at -1.697056 1.697056) (size 0.6 0.6) (drill 0.5) (layers *.Cu *.Mask) 21 | (zone_connect 2)) 22 | (pad 1 thru_hole circle (at 0 2.4) (size 0.6 0.6) (drill 0.5) (layers *.Cu *.Mask) 23 | (zone_connect 2)) 24 | (pad 1 thru_hole circle (at 1.697056 1.697056) (size 0.6 0.6) (drill 0.5) (layers *.Cu *.Mask) 25 | (zone_connect 2)) 26 | (pad 1 thru_hole circle (at 2.4 0) (size 0.6 0.6) (drill 0.5) (layers *.Cu *.Mask) 27 | (zone_connect 2)) 28 | (pad 1 thru_hole circle (at 0 0) (size 6.4 6.4) (drill 3.2) (layers *.Cu *.Mask) 29 | (zone_connect 2)) 30 | ) 31 | -------------------------------------------------------------------------------- /hw/vna.pretty/PAT1220.kicad_mod: -------------------------------------------------------------------------------- 1 | (module PAT1220 (layer F.Cu) (tedit 53D14AD8) 2 | (fp_text reference U7 (at 0.75 -1.75) (layer F.SilkS) 3 | (effects (font (size 1 1) (thickness 0.15))) 4 | ) 5 | (fp_text value PAT1220-6dB (at 0.5 3) (layer F.SilkS) 6 | (effects (font (size 1 1) (thickness 0.15))) 7 | ) 8 | (fp_line (start -0.25 0) (end -0.25 1.25) (layer F.SilkS) (width 0.15)) 9 | (fp_line (start -0.25 1.25) (end 1.75 1.25) (layer F.SilkS) (width 0.15)) 10 | (fp_line (start 1.75 1.25) (end 1.75 0) (layer F.SilkS) (width 0.15)) 11 | (fp_line (start 1.75 0) (end -0.25 0) (layer F.SilkS) (width 0.15)) 12 | (pad 1 smd rect (at 0 0) (size 0.8 0.7) (layers F.Cu F.Paste F.Mask)) 13 | (pad 2 smd rect (at 1.5 0) (size 0.8 0.7) (layers F.Cu F.Paste F.Mask)) 14 | (pad 3 smd rect (at 0.75 1.2) (size 2.3 0.7) (layers F.Cu F.Paste F.Mask)) 15 | ) 16 | -------------------------------------------------------------------------------- /hw/vna.pretty/RF_via.kicad_mod: -------------------------------------------------------------------------------- 1 | (module RF_via (layer F.Cu) (tedit 5883112F) 2 | (fp_text reference REF** (at 0.1 1) (layer F.SilkS) hide 3 | (effects (font (size 0.5 0.5) (thickness 0.125))) 4 | ) 5 | (fp_text value RF_via (at 0 -1.5) (layer F.Fab) 6 | (effects (font (size 1 1) (thickness 0.15))) 7 | ) 8 | (fp_line (start -0.7 0) (end 0.7 0) (layer F.Mask) (width 0.95)) 9 | (pad 1 thru_hole circle (at 0 0) (size 0.55 0.55) (drill 0.26) (layers *.Cu F.Mask)) 10 | (pad 2 thru_hole circle (at 0.75 0) (size 0.55 0.55) (drill 0.26) (layers *.Cu F.Mask) 11 | (zone_connect 2)) 12 | (pad 2 thru_hole circle (at -0.75 0) (size 0.55 0.55) (drill 0.26) (layers *.Cu F.Mask) 13 | (zone_connect 2)) 14 | ) 15 | -------------------------------------------------------------------------------- /hw/vna.pretty/R_0402b.kicad_mod: -------------------------------------------------------------------------------- 1 | (module R_0402b (layer F.Cu) (tedit 55A401B2) 2 | (descr "Resistor SMD 0402, reflow soldering, Vishay (see dcrcw.pdf)") 3 | (tags "resistor 0402") 4 | (attr smd) 5 | (fp_text reference REF** (at 0 -1.4) (layer F.SilkS) 6 | (effects (font (size 0.5 0.5) (thickness 0.125))) 7 | ) 8 | (fp_text value R_0402 (at 0 1.8) (layer F.Fab) 9 | (effects (font (size 1 1) (thickness 0.15))) 10 | ) 11 | (fp_line (start -0.95 -0.65) (end 0.95 -0.65) (layer F.CrtYd) (width 0.05)) 12 | (fp_line (start -0.95 0.65) (end 0.95 0.65) (layer F.CrtYd) (width 0.05)) 13 | (fp_line (start -0.95 -0.65) (end -0.95 0.65) (layer F.CrtYd) (width 0.05)) 14 | (fp_line (start 0.95 -0.65) (end 0.95 0.65) (layer F.CrtYd) (width 0.05)) 15 | (fp_line (start 0.25 -0.525) (end -0.25 -0.525) (layer F.SilkS) (width 0.15)) 16 | (fp_line (start -0.25 0.525) (end 0.25 0.525) (layer F.SilkS) (width 0.15)) 17 | (pad 1 smd rect (at -0.45 0) (size 0.4 0.6) (layers F.Cu F.Paste F.Mask)) 18 | (pad 2 smd rect (at 0.45 0) (size 0.4 0.6) (layers F.Cu F.Paste F.Mask)) 19 | (model Resistors_SMD.3dshapes/R_0402.wrl 20 | (at (xyz 0 0 0)) 21 | (scale (xyz 1 1 1)) 22 | (rotate (xyz 0 0 0)) 23 | ) 24 | ) 25 | -------------------------------------------------------------------------------- /hw/vna.pretty/R_0603b.kicad_mod: -------------------------------------------------------------------------------- 1 | (module R_0603b (layer F.Cu) (tedit 584D7538) 2 | (descr "Resistor SMD 0603, reflow soldering, Vishay (see dcrcw.pdf)") 3 | (tags "resistor 0603") 4 | (attr smd) 5 | (fp_text reference REF** (at 0 -1.4) (layer F.SilkS) 6 | (effects (font (size 0.7 0.7) (thickness 0.15))) 7 | ) 8 | (fp_text value R_0603 (at 0 1.9) (layer F.Fab) 9 | (effects (font (size 1 1) (thickness 0.15))) 10 | ) 11 | (fp_line (start -0.5 -0.675) (end 0.5 -0.675) (layer F.SilkS) (width 0.15)) 12 | (fp_line (start 0.5 0.675) (end -0.5 0.675) (layer F.SilkS) (width 0.15)) 13 | (fp_line (start 1.3 -0.8) (end 1.3 0.8) (layer F.CrtYd) (width 0.05)) 14 | (fp_line (start -1.3 -0.8) (end -1.3 0.8) (layer F.CrtYd) (width 0.05)) 15 | (fp_line (start -1.3 0.8) (end 1.3 0.8) (layer F.CrtYd) (width 0.05)) 16 | (fp_line (start -1.3 -0.8) (end 1.3 -0.8) (layer F.CrtYd) (width 0.05)) 17 | (fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.1)) 18 | (fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.1)) 19 | (fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.1)) 20 | (fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.1)) 21 | (pad 2 smd rect (at 0.75 0) (size 0.5 0.9) (layers F.Cu F.Paste F.Mask)) 22 | (pad 1 smd rect (at -0.75 0) (size 0.5 0.9) (layers F.Cu F.Paste F.Mask)) 23 | (model Resistors_SMD.3dshapes/R_0603.wrl 24 | (at (xyz 0 0 0)) 25 | (scale (xyz 1 1 1)) 26 | (rotate (xyz 0 0 0)) 27 | ) 28 | ) 29 | -------------------------------------------------------------------------------- /hw/vna.pretty/S2711-46R.kicad_mod: -------------------------------------------------------------------------------- 1 | (module S2711-46R (layer F.Cu) (tedit 586FF10A) 2 | (fp_text reference REF** (at 0 2) (layer F.SilkS) 3 | (effects (font (size 0.6 0.6) (thickness 0.15))) 4 | ) 5 | (fp_text value S2711-46R (at 0.1 0) (layer F.Fab) 6 | (effects (font (size 1 1) (thickness 0.15))) 7 | ) 8 | (pad 1 smd rect (at 0 0) (size 9.4 2.3) (layers F.Cu F.Mask)) 9 | ) 10 | -------------------------------------------------------------------------------- /hw/vna.pretty/SC-70-6.kicad_mod: -------------------------------------------------------------------------------- 1 | (module SC-70-6 (layer F.Cu) (tedit 53F4DBEF) 2 | (fp_text reference U12 (at -0.1 -3.65) (layer F.SilkS) 3 | (effects (font (size 1 1) (thickness 0.15))) 4 | ) 5 | (fp_text value MCP4017 (at 0.4 3.9) (layer F.SilkS) hide 6 | (effects (font (size 1 1) (thickness 0.15))) 7 | ) 8 | (fp_line (start 0.1 0.05) (end 0.1 1.3) (layer F.SilkS) (width 0.15)) 9 | (fp_line (start 0.1 1.3) (end 2.1 1.3) (layer F.SilkS) (width 0.15)) 10 | (fp_line (start 2.1 1.3) (end 2.1 0.05) (layer F.SilkS) (width 0.15)) 11 | (fp_line (start 2.1 0.05) (end 0.1 0.05) (layer F.SilkS) (width 0.15)) 12 | (fp_line (start -0.45 -0.55) (end -0.75 -0.55) (layer F.SilkS) (width 0.15)) 13 | (fp_line (start -0.75 -0.55) (end -0.75 -0.3) (layer F.SilkS) (width 0.15)) 14 | (fp_line (start 1.1 1.45) (end 1.1 -0.1) (layer F.SilkS) (width 0.5)) 15 | (pad 1 smd rect (at 0 0) (size 0.9 0.4) (layers F.Cu F.Paste F.Mask)) 16 | (pad 2 smd rect (at 0 0.65) (size 0.9 0.4) (layers F.Cu F.Paste F.Mask)) 17 | (pad 3 smd rect (at 0 1.3) (size 0.9 0.4) (layers F.Cu F.Paste F.Mask)) 18 | (pad 4 smd rect (at 2.2 1.3) (size 0.9 0.4) (layers F.Cu F.Paste F.Mask)) 19 | (pad 5 smd rect (at 2.2 0.65) (size 0.9 0.4) (layers F.Cu F.Paste F.Mask)) 20 | (pad 6 smd rect (at 2.2 0) (size 0.9 0.4) (layers F.Cu F.Paste F.Mask)) 21 | ) 22 | -------------------------------------------------------------------------------- /hw/vna.pretty/SG-210STF.kicad_mod: -------------------------------------------------------------------------------- 1 | (module SG-210STF (layer F.Cu) (tedit 551F92FA) 2 | (fp_text reference REF** (at 0.1 -2) (layer F.SilkS) 3 | (effects (font (size 1 1) (thickness 0.15))) 4 | ) 5 | (fp_text value SG-210STF (at 0.25 2.05) (layer F.Fab) 6 | (effects (font (size 1 1) (thickness 0.15))) 7 | ) 8 | (fp_line (start -1.2 1.35) (end -1.65 1.35) (layer F.SilkS) (width 0.15)) 9 | (fp_line (start -1.65 1.35) (end -1.65 0.9) (layer F.SilkS) (width 0.15)) 10 | (fp_line (start -1.3 1) (end -1.3 -1) (layer F.SilkS) (width 0.15)) 11 | (fp_line (start -1.3 -1) (end 1.2 -1) (layer F.SilkS) (width 0.15)) 12 | (fp_line (start 1.2 -1) (end 1.2 1) (layer F.SilkS) (width 0.15)) 13 | (fp_line (start 1.2 1) (end -1.3 1) (layer F.SilkS) (width 0.15)) 14 | (pad 1 smd rect (at -0.9 0.65) (size 1.1 0.9) (layers F.Cu F.Paste F.Mask)) 15 | (pad 2 smd rect (at 0.8 0.65) (size 1.1 0.9) (layers F.Cu F.Paste F.Mask)) 16 | (pad 3 smd rect (at 0.8 -0.65) (size 1.1 0.9) (layers F.Cu F.Paste F.Mask)) 17 | (pad 4 smd rect (at -0.9 -0.65) (size 1.1 0.9) (layers F.Cu F.Paste F.Mask)) 18 | ) 19 | -------------------------------------------------------------------------------- /hw/vna.pretty/SOD-123F.kicad_mod: -------------------------------------------------------------------------------- 1 | (module SOD-123F (layer F.Cu) (tedit 569A86EC) 2 | (fp_text reference REF** (at 0.1 1.8) (layer F.SilkS) 3 | (effects (font (size 0.7 0.7) (thickness 0.15))) 4 | ) 5 | (fp_text value SOD-123F (at -0.3 -2.1) (layer F.Fab) 6 | (effects (font (size 1 1) (thickness 0.15))) 7 | ) 8 | (fp_line (start -0.8 -0.1) (end 0.5 0.9) (layer F.SilkS) (width 0.15)) 9 | (fp_line (start 0.5 -1.1) (end -0.8 -0.1) (layer F.SilkS) (width 0.15)) 10 | (fp_line (start -1.6 -1.1) (end -1.6 0.9) (layer F.SilkS) (width 0.15)) 11 | (fp_line (start -1.6 0.9) (end 1.4 0.9) (layer F.SilkS) (width 0.15)) 12 | (fp_line (start 1.4 0.9) (end 1.4 -1.1) (layer F.SilkS) (width 0.15)) 13 | (fp_line (start 1.4 -1.1) (end -1.6 -1.1) (layer F.SilkS) (width 0.15)) 14 | (pad 1 smd rect (at -1.5 -0.1) (size 1.34 1.8) (layers F.Cu F.Paste F.Mask)) 15 | (pad 2 smd rect (at 1.36 -0.1) (size 1.34 1.8) (layers F.Cu F.Paste F.Mask)) 16 | ) 17 | -------------------------------------------------------------------------------- /hw/vna.pretty/SOT-23-5.kicad_mod: -------------------------------------------------------------------------------- 1 | (module SOT-23-5 (layer F.Cu) (tedit 55AA3491) 2 | (fp_text reference SOT-23-5 (at 0 1.325) (layer F.SilkS) 3 | (effects (font (size 1 1) (thickness 0.15))) 4 | ) 5 | (fp_text value VAL** (at 0 -4.05) (layer F.SilkS) 6 | (effects (font (size 1 1) (thickness 0.15))) 7 | ) 8 | (fp_line (start -0.55 -2.2) (end -0.55 -0.45) (layer F.SilkS) (width 0.15)) 9 | (fp_line (start -0.55 -0.45) (end 2.45 -0.45) (layer F.SilkS) (width 0.15)) 10 | (fp_line (start 2.45 -0.45) (end 2.45 -2.2) (layer F.SilkS) (width 0.15)) 11 | (fp_line (start 2.45 -2.2) (end -0.55 -2.2) (layer F.SilkS) (width 0.15)) 12 | (pad 1 smd rect (at 0 0) (size 0.6 1.05) (layers F.Cu F.Paste F.Mask)) 13 | (pad 2 smd rect (at 0.95 0) (size 0.6 1.05) (layers F.Cu F.Paste F.Mask)) 14 | (pad 3 smd rect (at 1.9 0) (size 0.6 1.05) (layers F.Cu F.Paste F.Mask)) 15 | (pad 4 smd rect (at 1.9 -2.6) (size 0.6 1.25) (layers F.Cu F.Paste F.Mask)) 16 | (pad 5 smd rect (at 0 -2.6) (size 0.6 1.25) (layers F.Cu F.Paste F.Mask)) 17 | ) 18 | -------------------------------------------------------------------------------- /hw/vna.pretty/SOT-23-5L.kicad_mod: -------------------------------------------------------------------------------- 1 | (module SOT-23-5L (layer F.Cu) (tedit 55840FD3) 2 | (fp_text reference REF** (at 1.1 1.4) (layer F.SilkS) 3 | (effects (font (size 1 1) (thickness 0.15))) 4 | ) 5 | (fp_text value SOT-23-5L (at 0.7 -3.6) (layer F.Fab) 6 | (effects (font (size 1 1) (thickness 0.15))) 7 | ) 8 | (fp_line (start -0.5 -0.4) (end -0.5 -2) (layer F.SilkS) (width 0.15)) 9 | (fp_line (start -0.5 -2) (end 2.5 -2) (layer F.SilkS) (width 0.15)) 10 | (fp_line (start 2.5 -2) (end 2.5 -0.4) (layer F.SilkS) (width 0.15)) 11 | (fp_line (start 2.5 -0.4) (end -0.5 -0.4) (layer F.SilkS) (width 0.15)) 12 | (pad 1 smd rect (at 0 0) (size 0.6 1.2) (layers F.Cu F.Paste F.Mask)) 13 | (pad 2 smd rect (at 0.95 0) (size 0.6 1.2) (layers F.Cu F.Paste F.Mask)) 14 | (pad 3 smd rect (at 1.9 0) (size 0.6 1.2) (layers F.Cu F.Paste F.Mask)) 15 | (pad 4 smd rect (at 1.9 -2.3) (size 0.6 1.2) (layers F.Cu F.Paste F.Mask)) 16 | (pad 5 smd rect (at 0 -2.3) (size 0.6 1.2) (layers F.Cu F.Paste F.Mask)) 17 | ) 18 | -------------------------------------------------------------------------------- /hw/vna.pretty/SOT-23-6.kicad_mod: -------------------------------------------------------------------------------- 1 | (module SOT-23-6 (layer F.Cu) (tedit 53F4C8CF) 2 | (fp_text reference SOT23_6 (at 1.99898 0 90) (layer F.SilkS) 3 | (effects (font (size 0.762 0.762) (thickness 0.0762))) 4 | ) 5 | (fp_text value VAL (at 0.0635 0) (layer F.SilkS) 6 | (effects (font (size 0.50038 0.50038) (thickness 0.0762))) 7 | ) 8 | (fp_circle (center -1.1 0.5) (end -1 0.2) (layer F.SilkS) (width 0.15)) 9 | (fp_line (start -1.5 0.9) (end -1.5 -0.8) (layer F.SilkS) (width 0.15)) 10 | (fp_line (start -1.5 -0.8) (end 1.5 -0.8) (layer F.SilkS) (width 0.15)) 11 | (fp_line (start 1.5 -0.8) (end 1.5 0.9) (layer F.SilkS) (width 0.15)) 12 | (fp_line (start 1.5 0.9) (end -1.5 0.9) (layer F.SilkS) (width 0.15)) 13 | (pad 6 smd rect (at -0.9525 -1.27) (size 0.70104 1.00076) (layers F.Cu F.Paste F.Mask)) 14 | (pad 5 smd rect (at 0 -1.27) (size 0.70104 1.00076) (layers F.Cu F.Paste F.Mask)) 15 | (pad 4 smd rect (at 0.9525 -1.27) (size 0.70104 1.00076) (layers F.Cu F.Paste F.Mask)) 16 | (pad 3 smd rect (at 0.9525 1.27) (size 0.70104 1.00076) (layers F.Cu F.Paste F.Mask)) 17 | (pad 2 smd rect (at 0 1.27) (size 0.70104 1.00076) (layers F.Cu F.Paste F.Mask)) 18 | (pad 1 smd rect (at -0.9525 1.27) (size 0.70104 1.00076) (layers F.Cu F.Paste F.Mask)) 19 | (model smd/SOT23_6.wrl 20 | (at (xyz 0 0 0)) 21 | (scale (xyz 0.11 0.11 0.11)) 22 | (rotate (xyz 0 0 0)) 23 | ) 24 | ) 25 | -------------------------------------------------------------------------------- /hw/vna.pretty/SOT-416.kicad_mod: -------------------------------------------------------------------------------- 1 | (module SOT-416 (layer F.Cu) (tedit 559825CE) 2 | (fp_text reference REF** (at 0.05 1.15) (layer F.SilkS) 3 | (effects (font (size 1 1) (thickness 0.15))) 4 | ) 5 | (fp_text value SOT-416 (at -0.05 -1.9) (layer F.Fab) 6 | (effects (font (size 1 1) (thickness 0.15))) 7 | ) 8 | (fp_line (start -0.4 0.05) (end -0.4 -0.95) (layer F.SilkS) (width 0.15)) 9 | (fp_line (start -0.4 -0.95) (end 1.3 -0.95) (layer F.SilkS) (width 0.15)) 10 | (fp_line (start 1.3 -0.95) (end 1.3 0.05) (layer F.SilkS) (width 0.15)) 11 | (fp_line (start 1.3 0.05) (end -0.4 0.05) (layer F.SilkS) (width 0.15)) 12 | (pad 1 smd rect (at 0 0) (size 0.46 0.65) (layers F.Cu F.Paste F.Mask)) 13 | (pad 2 smd rect (at 1 0) (size 0.46 0.65) (layers F.Cu F.Paste F.Mask)) 14 | (pad 3 smd rect (at 0.5 -1.05) (size 0.46 0.65) (layers F.Cu F.Paste F.Mask)) 15 | ) 16 | -------------------------------------------------------------------------------- /hw/vna.pretty/SRN4018.kicad_mod: -------------------------------------------------------------------------------- 1 | (module SRN4018 (layer F.Cu) (tedit 5585889F) 2 | (fp_text reference REF** (at 1.7 2.8) (layer F.SilkS) 3 | (effects (font (size 1 1) (thickness 0.15))) 4 | ) 5 | (fp_text value SRN4018 (at 1.5 -2.5) (layer F.Fab) 6 | (effects (font (size 1 1) (thickness 0.15))) 7 | ) 8 | (fp_line (start -0.5 2.1) (end -0.5 -1.9) (layer F.SilkS) (width 0.15)) 9 | (fp_line (start -0.5 -1.9) (end 3.5 -1.9) (layer F.SilkS) (width 0.15)) 10 | (fp_line (start 3.5 -1.9) (end 3.5 2.1) (layer F.SilkS) (width 0.15)) 11 | (fp_line (start 3.5 2.1) (end -0.5 2.1) (layer F.SilkS) (width 0.15)) 12 | (pad 1 smd rect (at 0 0) (size 1.5 3.6) (layers F.Cu F.Paste F.Mask)) 13 | (pad 2 smd rect (at 3.05 0) (size 1.5 3.6) (layers F.Cu F.Paste F.Mask)) 14 | ) 15 | -------------------------------------------------------------------------------- /hw/vna.pretty/SRR6040A.kicad_mod: -------------------------------------------------------------------------------- 1 | (module SRR6040A (layer F.Cu) (tedit 566C267B) 2 | (fp_text reference REF** (at -0.25 4.6) (layer F.SilkS) 3 | (effects (font (size 1 1) (thickness 0.15))) 4 | ) 5 | (fp_text value SRR6040A (at -0.25 -4.9) (layer F.Fab) 6 | (effects (font (size 1 1) (thickness 0.15))) 7 | ) 8 | (fp_line (start -3.6 3.3) (end -3.6 -3.4) (layer F.SilkS) (width 0.15)) 9 | (fp_line (start -3.6 -3.4) (end 3.1 -3.4) (layer F.SilkS) (width 0.15)) 10 | (fp_line (start 3.1 -3.4) (end 3.1 3.3) (layer F.SilkS) (width 0.15)) 11 | (fp_line (start 3.1 3.3) (end -3.6 3.3) (layer F.SilkS) (width 0.15)) 12 | (pad 1 smd rect (at -0.25 -2.9) (size 7.3 1.4) (layers F.Cu F.Paste F.Mask)) 13 | (pad 2 smd rect (at -0.25 2.9) (size 7.3 1.4) (layers F.Cu F.Paste F.Mask)) 14 | (pad 1 smd rect (at -3.575 -1.7) (size 0.65 1) (layers F.Cu F.Paste F.Mask)) 15 | (pad 1 smd rect (at 3.075 -1.7) (size 0.65 1) (layers F.Cu F.Paste F.Mask)) 16 | (pad 2 smd rect (at -3.575 1.7) (size 0.65 1) (layers F.Cu F.Paste F.Mask)) 17 | (pad 2 smd rect (at 3.075 1.7) (size 0.65 1) (layers F.Cu F.Paste F.Mask)) 18 | ) 19 | -------------------------------------------------------------------------------- /hw/vna.pretty/SSOP-16.kicad_mod: -------------------------------------------------------------------------------- 1 | (module SSOP-16 (layer F.Cu) (tedit 53F4C63A) 2 | (fp_text reference SSOP-16 (at 1.905 -6.985) (layer F.SilkS) 3 | (effects (font (size 1 1) (thickness 0.15))) 4 | ) 5 | (fp_text value VAL** (at 2.54 1.905) (layer F.SilkS) hide 6 | (effects (font (size 1 1) (thickness 0.15))) 7 | ) 8 | (fp_circle (center 0.3 -1.2) (end 0.5 -1.5) (layer F.SilkS) (width 0.15)) 9 | (fp_line (start -0.2 -0.7) (end -0.2 -4.6) (layer F.SilkS) (width 0.15)) 10 | (fp_line (start -0.2 -4.6) (end 4.7 -4.6) (layer F.SilkS) (width 0.15)) 11 | (fp_line (start 4.7 -4.6) (end 4.7 -0.7) (layer F.SilkS) (width 0.15)) 12 | (fp_line (start 4.7 -0.7) (end -0.2 -0.7) (layer F.SilkS) (width 0.15)) 13 | (pad 1 smd rect (at 0 0) (size 0.4191 1.143) (layers F.Cu F.Paste F.Mask)) 14 | (pad 2 smd rect (at 0.635 0) (size 0.4191 1.143) (layers F.Cu F.Paste F.Mask)) 15 | (pad 3 smd rect (at 1.27 0) (size 0.4191 1.143) (layers F.Cu F.Paste F.Mask)) 16 | (pad 4 smd rect (at 1.905 0) (size 0.4191 1.143) (layers F.Cu F.Paste F.Mask)) 17 | (pad 5 smd rect (at 2.54 0) (size 0.4191 1.143) (layers F.Cu F.Paste F.Mask)) 18 | (pad 6 smd rect (at 3.175 0) (size 0.4191 1.143) (layers F.Cu F.Paste F.Mask)) 19 | (pad 7 smd rect (at 3.81 0) (size 0.4191 1.143) (layers F.Cu F.Paste F.Mask)) 20 | (pad 8 smd rect (at 4.445 0) (size 0.4191 1.143) (layers F.Cu F.Paste F.Mask)) 21 | (pad 9 smd rect (at 4.445 -5.334) (size 0.4191 1.143) (layers F.Cu F.Paste F.Mask)) 22 | (pad 10 smd rect (at 3.81 -5.334) (size 0.4191 1.143) (layers F.Cu F.Paste F.Mask)) 23 | (pad 11 smd rect (at 3.175 -5.334) (size 0.4191 1.143) (layers F.Cu F.Paste F.Mask)) 24 | (pad 12 smd rect (at 2.54 -5.334) (size 0.4191 1.143) (layers F.Cu F.Paste F.Mask)) 25 | (pad 13 smd rect (at 1.905 -5.334) (size 0.4191 1.143) (layers F.Cu F.Paste F.Mask)) 26 | (pad 14 smd rect (at 1.27 -5.334) (size 0.4191 1.143) (layers F.Cu F.Paste F.Mask)) 27 | (pad 15 smd rect (at 0.635 -5.334) (size 0.4191 1.143) (layers F.Cu F.Paste F.Mask)) 28 | (pad 16 smd rect (at 0 -5.334) (size 0.4191 1.143) (layers F.Cu F.Paste F.Mask)) 29 | ) 30 | -------------------------------------------------------------------------------- /hw/vna.pretty/SSOT-6.kicad_mod: -------------------------------------------------------------------------------- 1 | (module SSOT-6 (layer F.Cu) (tedit 559D5666) 2 | (fp_text reference REF** (at -0.4 2.4) (layer F.SilkS) 3 | (effects (font (size 1 1) (thickness 0.15))) 4 | ) 5 | (fp_text value SSOT-6 (at -0.7 -2.7) (layer F.Fab) 6 | (effects (font (size 1 1) (thickness 0.15))) 7 | ) 8 | (fp_circle (center -1.3 0.4) (end -1.1 0.3) (layer F.SilkS) (width 0.15)) 9 | (fp_line (start -1.6 0.7) (end -1.6 -0.9) (layer F.SilkS) (width 0.15)) 10 | (fp_line (start -1.6 -0.9) (end 1.4 -0.9) (layer F.SilkS) (width 0.15)) 11 | (fp_line (start 1.4 -0.9) (end 1.4 0.7) (layer F.SilkS) (width 0.15)) 12 | (fp_line (start 1.4 0.7) (end -1.6 0.7) (layer F.SilkS) (width 0.15)) 13 | (pad 1 smd rect (at -1.1 1.2) (size 0.69 0.99) (layers F.Cu F.Paste F.Mask)) 14 | (pad 2 smd rect (at -0.15 1.2) (size 0.69 0.99) (layers F.Cu F.Paste F.Mask)) 15 | (pad 3 smd rect (at 0.8 1.2) (size 0.69 0.99) (layers F.Cu F.Paste F.Mask)) 16 | (pad 4 smd rect (at 0.8 -1.39) (size 0.69 0.99) (layers F.Cu F.Paste F.Mask)) 17 | (pad 5 smd rect (at -0.15 -1.39) (size 0.69 0.99) (layers F.Cu F.Paste F.Mask)) 18 | (pad 6 smd rect (at -1.1 -1.39) (size 0.69 0.99) (layers F.Cu F.Paste F.Mask)) 19 | ) 20 | -------------------------------------------------------------------------------- /hw/vna.pretty/TCM1-63AX+.kicad_mod: -------------------------------------------------------------------------------- 1 | (module TCM1-63AX+ (layer F.Cu) (tedit 584AEBBE) 2 | (fp_text reference REF** (at 0 3.6) (layer F.SilkS) 3 | (effects (font (size 1 1) (thickness 0.15))) 4 | ) 5 | (fp_text value TCM1-63AX+ (at 0 -3.6) (layer F.Fab) 6 | (effects (font (size 1 1) (thickness 0.15))) 7 | ) 8 | (fp_line (start -1.9 -2.1) (end 1.9 -2.1) (layer F.SilkS) (width 0.15)) 9 | (fp_line (start 1.9 -2.1) (end 1.9 2) (layer F.SilkS) (width 0.15)) 10 | (fp_line (start 1.9 2) (end -1.9 2) (layer F.SilkS) (width 0.15)) 11 | (fp_line (start -1.9 2) (end -1.9 -2.1) (layer F.SilkS) (width 0.15)) 12 | (pad 1 smd rect (at -1.2827 -1.5875) (size 0.76 1.65) (layers F.Cu F.Paste F.Mask)) 13 | (pad 2 smd rect (at -0.0127 -1.5875) (size 0.76 1.65) (layers F.Cu F.Paste F.Mask)) 14 | (pad 3 smd rect (at 1.2573 -1.5875) (size 0.76 1.65) (layers F.Cu F.Paste F.Mask)) 15 | (pad 4 smd rect (at 1.2573 1.5925) (size 0.76 1.65) (layers F.Cu F.Paste F.Mask)) 16 | (pad 5 smd rect (at -0.0127 1.5925) (size 0.76 1.65) (layers F.Cu F.Paste F.Mask)) 17 | (pad 6 smd rect (at -1.2827 1.5925) (size 0.76 1.65) (layers F.Cu F.Paste F.Mask)) 18 | ) 19 | -------------------------------------------------------------------------------- /hw/vna.pretty/TFLGA-20.kicad_mod: -------------------------------------------------------------------------------- 1 | (module TFLGA-20 (layer F.Cu) (tedit 587D08AF) 2 | (solder_mask_margin 0.1) 3 | (fp_text reference REF** (at 0 3.125) (layer F.SilkS) 4 | (effects (font (size 0.7 0.7) (thickness 0.15))) 5 | ) 6 | (fp_text value TFLGA-20 (at 0 -3.75) (layer F.Fab) 7 | (effects (font (size 1 1) (thickness 0.15))) 8 | ) 9 | (fp_line (start -2 -2) (end 2 -2) (layer F.SilkS) (width 0.15)) 10 | (fp_line (start 2 -2) (end 2 2) (layer F.SilkS) (width 0.15)) 11 | (fp_line (start 2 2) (end -2 2) (layer F.SilkS) (width 0.15)) 12 | (fp_line (start -2 2) (end -2 -2) (layer F.SilkS) (width 0.15)) 13 | (pad 1 smd rect (at -1.8 -1) (size 0.6 0.31) (layers F.Cu F.Paste F.Mask)) 14 | (pad 2 smd rect (at -1.8 -0.5) (size 0.6 0.31) (layers F.Cu F.Paste F.Mask)) 15 | (pad 3 smd rect (at -1.8 0) (size 0.6 0.31) (layers F.Cu F.Paste F.Mask)) 16 | (pad 4 smd rect (at -1.8 0.5) (size 0.6 0.31) (layers F.Cu F.Paste F.Mask)) 17 | (pad 5 smd rect (at -1.8 1) (size 0.6 0.31) (layers F.Cu F.Paste F.Mask)) 18 | (pad 6 smd rect (at -1 1.8 90) (size 0.6 0.31) (layers F.Cu F.Paste F.Mask)) 19 | (pad 7 smd rect (at -0.5 1.8 90) (size 0.6 0.31) (layers F.Cu F.Paste F.Mask)) 20 | (pad 8 smd rect (at 0 1.8 90) (size 0.6 0.31) (layers F.Cu F.Paste F.Mask)) 21 | (pad 9 smd rect (at 0.5 1.8 90) (size 0.6 0.31) (layers F.Cu F.Paste F.Mask)) 22 | (pad 10 smd rect (at 1 1.8 90) (size 0.6 0.31) (layers F.Cu F.Paste F.Mask)) 23 | (pad 11 smd rect (at 1.8 1) (size 0.6 0.31) (layers F.Cu F.Paste F.Mask)) 24 | (pad 12 smd rect (at 1.8 0.5) (size 0.6 0.31) (layers F.Cu F.Paste F.Mask)) 25 | (pad 13 smd rect (at 1.8 0) (size 0.6 0.31) (layers F.Cu F.Paste F.Mask)) 26 | (pad 14 smd rect (at 1.8 -0.5) (size 0.6 0.31) (layers F.Cu F.Paste F.Mask)) 27 | (pad 15 smd rect (at 1.8 -1) (size 0.6 0.31) (layers F.Cu F.Paste F.Mask)) 28 | (pad 16 smd rect (at 1 -1.8 90) (size 0.6 0.31) (layers F.Cu F.Paste F.Mask)) 29 | (pad 17 smd rect (at 0.5 -1.8 90) (size 0.6 0.31) (layers F.Cu F.Paste F.Mask)) 30 | (pad 18 smd rect (at 0 -1.8 90) (size 0.6 0.31) (layers F.Cu F.Paste F.Mask)) 31 | (pad 19 smd rect (at -0.5 -1.8 90) (size 0.6 0.31) (layers F.Cu F.Paste F.Mask)) 32 | (pad 20 smd rect (at -1 -1.8 90) (size 0.6 0.31) (layers F.Cu F.Paste F.Mask)) 33 | (pad EP smd rect (at 0 0 90) (size 2.05 2.05) (layers F.Cu F.Paste F.Mask) 34 | (solder_mask_margin 0.1) (solder_paste_margin_ratio -0.2)) 35 | (pad EP thru_hole circle (at -0.7 -0.7 90) (size 0.5 0.5) (drill 0.3) (layers *.Cu *.Mask) 36 | (zone_connect 2)) 37 | (pad EP thru_hole circle (at 0 -0.7 90) (size 0.5 0.5) (drill 0.3) (layers *.Cu *.Mask) 38 | (zone_connect 2)) 39 | (pad EP thru_hole circle (at 0.7 -0.7 90) (size 0.5 0.5) (drill 0.3) (layers *.Cu *.Mask) 40 | (zone_connect 2)) 41 | (pad EP thru_hole circle (at -0.7 0 90) (size 0.5 0.5) (drill 0.3) (layers *.Cu *.Mask) 42 | (zone_connect 2)) 43 | (pad EP thru_hole circle (at 0 0 90) (size 0.5 0.5) (drill 0.3) (layers *.Cu *.Mask) 44 | (zone_connect 2)) 45 | (pad EP thru_hole circle (at 0.7 0 90) (size 0.5 0.5) (drill 0.3) (layers *.Cu *.Mask) 46 | (zone_connect 2)) 47 | (pad EP thru_hole circle (at -0.7 0.7 90) (size 0.5 0.5) (drill 0.3) (layers *.Cu *.Mask) 48 | (zone_connect 2)) 49 | (pad EP thru_hole circle (at 0 0.7 90) (size 0.5 0.5) (drill 0.3) (layers *.Cu *.Mask) 50 | (zone_connect 2)) 51 | (pad EP thru_hole circle (at 0.7 0.7 90) (size 0.5 0.5) (drill 0.3) (layers *.Cu *.Mask) 52 | (zone_connect 2)) 53 | ) 54 | -------------------------------------------------------------------------------- /hw/vna.pretty/TP_1.00.kicad_mod: -------------------------------------------------------------------------------- 1 | (module TP_1.00 (layer F.Cu) (tedit 55A404EB) 2 | (fp_text reference REF** (at 0.125 0.05) (layer F.SilkS) hide 3 | (effects (font (size 0.5 0.5) (thickness 0.125))) 4 | ) 5 | (fp_text value TP_1.00 (at 0 -0.5) (layer F.Fab) 6 | (effects (font (size 1 1) (thickness 0.15))) 7 | ) 8 | (pad 1 smd circle (at 0 0) (size 1 1) (layers F.Cu F.Paste F.Mask)) 9 | ) 10 | -------------------------------------------------------------------------------- /hw/vna.pretty/TQFN-32.kicad_mod: -------------------------------------------------------------------------------- 1 | (module TQFN-32 (layer F.Cu) (tedit 587D0F5C) 2 | (fp_text reference REF** (at 0.115 3.55) (layer F.SilkS) 3 | (effects (font (size 0.6 0.6) (thickness 0.125))) 4 | ) 5 | (fp_text value TQFN-32 (at -0.085 -3.55) (layer F.Fab) 6 | (effects (font (size 0.6 0.6) (thickness 0.15))) 7 | ) 8 | (fp_line (start -2.185 -2.85) (end -2.785 -2.85) (layer F.SilkS) (width 0.15)) 9 | (fp_line (start -2.785 -2.85) (end -2.785 -2.25) (layer F.SilkS) (width 0.15)) 10 | (fp_line (start -2.485 2.45) (end -2.485 -2.55) (layer F.SilkS) (width 0.15)) 11 | (fp_line (start -2.485 -2.55) (end 2.515 -2.55) (layer F.SilkS) (width 0.15)) 12 | (fp_line (start 2.515 -2.55) (end 2.515 2.45) (layer F.SilkS) (width 0.15)) 13 | (fp_line (start 2.515 2.45) (end -2.485 2.45) (layer F.SilkS) (width 0.15)) 14 | (pad 1 smd rect (at -2.415 -1.75) (size 0.75 0.3) (layers F.Cu F.Paste F.Mask)) 15 | (pad 2 smd rect (at -2.415 -1.25) (size 0.8 0.3) (layers F.Cu F.Paste F.Mask)) 16 | (pad 3 smd rect (at -2.415 -0.75) (size 0.8 0.3) (layers F.Cu F.Paste F.Mask)) 17 | (pad 4 smd rect (at -2.415 -0.25) (size 0.8 0.3) (layers F.Cu F.Paste F.Mask)) 18 | (pad 5 smd rect (at -2.415 0.25) (size 0.8 0.3) (layers F.Cu F.Paste F.Mask)) 19 | (pad 6 smd rect (at -2.415 0.75) (size 0.8 0.3) (layers F.Cu F.Paste F.Mask)) 20 | (pad 7 smd rect (at -2.415 1.25) (size 0.8 0.3) (layers F.Cu F.Paste F.Mask)) 21 | (pad 8 smd rect (at -2.415 1.75) (size 0.75 0.3) (layers F.Cu F.Paste F.Mask)) 22 | (pad 17 smd rect (at 2.415 1.75) (size 0.75 0.3) (layers F.Cu F.Paste F.Mask)) 23 | (pad 18 smd rect (at 2.415 1.25) (size 0.8 0.3) (layers F.Cu F.Paste F.Mask)) 24 | (pad 19 smd rect (at 2.415 0.75) (size 0.8 0.3) (layers F.Cu F.Paste F.Mask)) 25 | (pad 20 smd rect (at 2.415 0.25) (size 0.8 0.3) (layers F.Cu F.Paste F.Mask)) 26 | (pad 21 smd rect (at 2.415 -0.25) (size 0.8 0.3) (layers F.Cu F.Paste F.Mask)) 27 | (pad 22 smd rect (at 2.415 -0.75) (size 0.8 0.3) (layers F.Cu F.Paste F.Mask)) 28 | (pad 23 smd rect (at 2.415 -1.25) (size 0.8 0.3) (layers F.Cu F.Paste F.Mask)) 29 | (pad 24 smd rect (at 2.415 -1.75) (size 0.75 0.3) (layers F.Cu F.Paste F.Mask)) 30 | (pad 9 smd rect (at -1.75 2.415 90) (size 0.75 0.3) (layers F.Cu F.Paste F.Mask)) 31 | (pad EP smd rect (at 0 0) (size 3.15 3.15) (layers F.Cu F.Paste F.Mask)) 32 | (pad 10 smd rect (at -1.25 2.415 90) (size 0.8 0.3) (layers F.Cu F.Paste F.Mask)) 33 | (pad 11 smd rect (at -0.75 2.415 90) (size 0.8 0.3) (layers F.Cu F.Paste F.Mask)) 34 | (pad 12 smd rect (at -0.25 2.415 90) (size 0.8 0.3) (layers F.Cu F.Paste F.Mask)) 35 | (pad 13 smd rect (at 0.25 2.415 90) (size 0.8 0.3) (layers F.Cu F.Paste F.Mask)) 36 | (pad 14 smd rect (at 0.75 2.415 90) (size 0.8 0.3) (layers F.Cu F.Paste F.Mask)) 37 | (pad 15 smd rect (at 1.25 2.415 90) (size 0.8 0.3) (layers F.Cu F.Paste F.Mask)) 38 | (pad 16 smd rect (at 1.75 2.415 90) (size 0.75 0.3) (layers F.Cu F.Paste F.Mask)) 39 | (pad 25 smd rect (at 1.75 -2.415 90) (size 0.75 0.3) (layers F.Cu F.Paste F.Mask)) 40 | (pad 26 smd rect (at 1.25 -2.415 90) (size 0.8 0.3) (layers F.Cu F.Paste F.Mask)) 41 | (pad 27 smd rect (at 0.75 -2.415 90) (size 0.8 0.3) (layers F.Cu F.Paste F.Mask)) 42 | (pad 28 smd rect (at 0.25 -2.415 90) (size 0.8 0.3) (layers F.Cu F.Paste F.Mask)) 43 | (pad 29 smd rect (at -0.25 -2.415 90) (size 0.8 0.3) (layers F.Cu F.Paste F.Mask)) 44 | (pad 30 smd rect (at -0.75 -2.415 90) (size 0.8 0.3) (layers F.Cu F.Paste F.Mask)) 45 | (pad 31 smd rect (at -1.25 -2.415 90) (size 0.8 0.3) (layers F.Cu F.Paste F.Mask)) 46 | (pad 32 smd rect (at -1.75 -2.415 90) (size 0.75 0.3) (layers F.Cu F.Paste F.Mask)) 47 | (pad EP thru_hole circle (at 0 0) (size 0.5 0.5) (drill 0.3) (layers *.Cu) 48 | (zone_connect 2)) 49 | (pad EP thru_hole circle (at -1 -1) (size 0.5 0.5) (drill 0.3) (layers *.Cu) 50 | (zone_connect 2)) 51 | (pad EP thru_hole circle (at 1 -1) (size 0.5 0.5) (drill 0.3) (layers *.Cu) 52 | (zone_connect 2)) 53 | (pad EP thru_hole circle (at -1 1) (size 0.5 0.5) (drill 0.3) (layers *.Cu) 54 | (zone_connect 2)) 55 | (pad EP thru_hole circle (at 1 1) (size 0.5 0.5) (drill 0.3) (layers *.Cu) 56 | (zone_connect 2)) 57 | (pad EP thru_hole circle (at 1 0) (size 0.5 0.5) (drill 0.3) (layers *.Cu) 58 | (zone_connect 2)) 59 | (pad EP thru_hole circle (at 0 -1) (size 0.5 0.5) (drill 0.3) (layers *.Cu) 60 | (zone_connect 2)) 61 | (pad EP thru_hole circle (at -1 0) (size 0.5 0.5) (drill 0.3) (layers *.Cu) 62 | (zone_connect 2)) 63 | (pad EP thru_hole circle (at 0 1) (size 0.5 0.5) (drill 0.3) (layers *.Cu) 64 | (zone_connect 2)) 65 | ) 66 | -------------------------------------------------------------------------------- /hw/vna.pretty/TSOT-23.kicad_mod: -------------------------------------------------------------------------------- 1 | (module TSOT-23 (layer F.Cu) (tedit 53F4D02D) 2 | (fp_text reference TSOT-23 (at 0 -4.699) (layer F.SilkS) 3 | (effects (font (size 1 1) (thickness 0.15))) 4 | ) 5 | (fp_text value VAL** (at 0.0635 3.302) (layer F.SilkS) 6 | (effects (font (size 1 1) (thickness 0.15))) 7 | ) 8 | (fp_line (start -0.8 -1) (end -0.8 -0.2) (layer F.SilkS) (width 0.15)) 9 | (fp_line (start -0.8 -0.2) (end -0.5 -0.2) (layer F.SilkS) (width 0.15)) 10 | (fp_line (start -0.5 -0.6) (end -0.5 -2.1) (layer F.SilkS) (width 0.15)) 11 | (fp_line (start -0.5 -2.1) (end 2.4 -2.1) (layer F.SilkS) (width 0.15)) 12 | (fp_line (start 2.4 -2.1) (end 2.4 -0.6) (layer F.SilkS) (width 0.15)) 13 | (fp_line (start 2.4 -0.6) (end -0.5 -0.6) (layer F.SilkS) (width 0.15)) 14 | (pad 1 smd rect (at 0 0) (size 0.62 1.22) (layers F.Cu F.Paste F.Mask)) 15 | (pad 2 smd rect (at 0.95 0) (size 0.62 1.22) (layers F.Cu F.Paste F.Mask)) 16 | (pad 3 smd rect (at 1.9 0) (size 0.62 1.22) (layers F.Cu F.Paste F.Mask)) 17 | (pad 4 smd rect (at 1.9 -2.62) (size 0.62 1.22) (layers F.Cu F.Paste F.Mask)) 18 | (pad 5 smd rect (at 0.95 -2.62) (size 0.62 1.22) (layers F.Cu F.Paste F.Mask)) 19 | (pad 6 smd rect (at 0 -2.62) (size 0.62 1.22) (layers F.Cu F.Paste F.Mask)) 20 | ) 21 | -------------------------------------------------------------------------------- /hw/vna.pretty/USB_MICRO.kicad_mod: -------------------------------------------------------------------------------- 1 | (module USB_MICRO (layer F.Cu) (tedit 53F64203) 2 | (fp_text reference U13 (at 0.1 -1.9) (layer F.SilkS) 3 | (effects (font (size 1 1) (thickness 0.15))) 4 | ) 5 | (fp_text value USB-MICRO (at 0.1 7.3) (layer F.SilkS) hide 6 | (effects (font (size 1 1) (thickness 0.15))) 7 | ) 8 | (fp_line (start -3.6 4.9) (end -3.6 -0.1) (layer F.SilkS) (width 0.15)) 9 | (fp_line (start -3.6 -0.1) (end 3.4 -0.1) (layer F.SilkS) (width 0.15)) 10 | (fp_line (start 3.4 -0.1) (end 3.4 4.9) (layer F.SilkS) (width 0.15)) 11 | (fp_line (start 3.4 4.9) (end -3.6 4.9) (layer F.SilkS) (width 0.15)) 12 | (fp_line (start -4.95 4.125) (end 4.75 4.125) (layer F.SilkS) (width 0.15)) 13 | (pad 1 smd rect (at -1.3 0) (size 0.4 1.35) (layers F.Cu F.Paste F.Mask)) 14 | (pad 5 smd rect (at 1.3 0) (size 0.4 1.35) (layers F.Cu F.Paste F.Mask)) 15 | (pad 3 smd rect (at 0 0) (size 0.4 1.35) (layers F.Cu F.Paste F.Mask)) 16 | (pad 2 smd rect (at -0.65 0) (size 0.4 1.35) (layers F.Cu F.Paste F.Mask)) 17 | (pad 4 smd rect (at 0.65 0) (size 0.4 1.35) (layers F.Cu F.Paste F.Mask)) 18 | (pad ~ smd rect (at -3.1 0.12) (size 2.1 1.6) (layers F.Cu F.Paste F.Mask)) 19 | (pad ~ smd rect (at 3.1 0.12) (size 2.1 1.6) (layers F.Cu F.Paste F.Mask)) 20 | (pad SH smd rect (at 3.8 2.675) (size 1.8 1.9) (layers F.Cu F.Paste F.Mask)) 21 | (pad ~ smd rect (at -3.8 2.675) (size 1.8 1.9) (layers F.Cu F.Paste F.Mask)) 22 | (pad ~ smd rect (at 1.2 2.675) (size 1.9 1.9) (layers F.Cu F.Paste F.Mask)) 23 | (pad ~ smd rect (at -1.2 2.675) (size 1.9 1.9) (layers F.Cu F.Paste F.Mask)) 24 | ) 25 | -------------------------------------------------------------------------------- /hw/vna.pretty/VFQFN-16.kicad_mod: -------------------------------------------------------------------------------- 1 | (module VFQFN-16 (layer F.Cu) (tedit 584D6891) 2 | (fp_text reference REF** (at 0 2.7) (layer F.SilkS) 3 | (effects (font (size 0.7 0.7) (thickness 0.15))) 4 | ) 5 | (fp_text value VFQFN-16 (at 0 -3.3) (layer F.Fab) 6 | (effects (font (size 1 1) (thickness 0.15))) 7 | ) 8 | (fp_line (start -1.5 -1.5) (end 1.5 -1.5) (layer F.SilkS) (width 0.15)) 9 | (fp_line (start 1.5 -1.5) (end 1.5 1.5) (layer F.SilkS) (width 0.15)) 10 | (fp_line (start 1.5 1.5) (end -1.5 1.5) (layer F.SilkS) (width 0.15)) 11 | (fp_line (start -1.5 1.5) (end -1.5 -1.5) (layer F.SilkS) (width 0.15)) 12 | (fp_line (start -1.5 -1.5) (end -1.9 -1.9) (layer F.SilkS) (width 0.15)) 13 | (pad 1 smd oval (at -1.35 -0.75 90) (size 0.3 0.7) (layers F.Cu F.Paste F.Mask)) 14 | (pad 2 smd oval (at -1.35 -0.25 90) (size 0.3 0.7) (layers F.Cu F.Paste F.Mask)) 15 | (pad 3 smd oval (at -1.35 0.25 90) (size 0.3 0.7) (layers F.Cu F.Paste F.Mask)) 16 | (pad 4 smd oval (at -1.35 0.75 90) (size 0.3 0.7) (layers F.Cu F.Paste F.Mask)) 17 | (pad 5 smd oval (at -0.75 1.35) (size 0.3 0.7) (layers F.Cu F.Paste F.Mask)) 18 | (pad 12 smd oval (at 1.35 -0.75 90) (size 0.3 0.7) (layers F.Cu F.Paste F.Mask)) 19 | (pad 11 smd oval (at 1.35 -0.25 90) (size 0.3 0.7) (layers F.Cu F.Paste F.Mask)) 20 | (pad 10 smd oval (at 1.35 0.25 90) (size 0.3 0.7) (layers F.Cu F.Paste F.Mask)) 21 | (pad 9 smd oval (at 1.35 0.75 90) (size 0.3 0.7) (layers F.Cu F.Paste F.Mask)) 22 | (pad 6 smd oval (at -0.25 1.35) (size 0.3 0.7) (layers F.Cu F.Paste F.Mask)) 23 | (pad 7 smd oval (at 0.25 1.35) (size 0.3 0.7) (layers F.Cu F.Paste F.Mask)) 24 | (pad 8 smd oval (at 0.75 1.35) (size 0.3 0.7) (layers F.Cu F.Paste F.Mask)) 25 | (pad 13 smd oval (at 0.75 -1.35) (size 0.3 0.7) (layers F.Cu F.Paste F.Mask)) 26 | (pad 14 smd oval (at 0.25 -1.35) (size 0.3 0.7) (layers F.Cu F.Paste F.Mask)) 27 | (pad 15 smd oval (at -0.25 -1.35) (size 0.3 0.7) (layers F.Cu F.Paste F.Mask)) 28 | (pad 16 smd oval (at -0.75 -1.35) (size 0.3 0.7) (layers F.Cu F.Paste F.Mask)) 29 | (pad EP smd rect (at 0 0) (size 1.6 1.6) (layers F.Cu F.Mask)) 30 | (pad EP thru_hole circle (at -0.4 -0.4) (size 0.5 0.5) (drill 0.3) (layers *.Cu *.Mask) 31 | (zone_connect 2)) 32 | (pad EP thru_hole circle (at 0.4 -0.4) (size 0.5 0.5) (drill 0.3) (layers *.Cu *.Mask) 33 | (zone_connect 2)) 34 | (pad EP thru_hole circle (at -0.4 0.4) (size 0.5 0.5) (drill 0.3) (layers *.Cu *.Mask) 35 | (zone_connect 2)) 36 | (pad EP thru_hole circle (at 0.4 0.4) (size 0.5 0.5) (drill 0.3) (layers *.Cu *.Mask) 37 | (zone_connect 2)) 38 | (pad EP smd rect (at 0 0) (size 1.3 0.5) (layers F.Cu F.Paste F.Mask)) 39 | (pad EP smd rect (at 0 0 90) (size 1.3 0.5) (layers F.Cu F.Paste F.Mask)) 40 | ) 41 | -------------------------------------------------------------------------------- /hw/vna.pretty/VFQFN-24.kicad_mod: -------------------------------------------------------------------------------- 1 | (module VFQFN-24 (layer F.Cu) (tedit 55A67B47) 2 | (fp_text reference U2 (at 0.095 5.025 90) (layer F.SilkS) 3 | (effects (font (size 1 1) (thickness 0.15))) 4 | ) 5 | (fp_text value HMC431LP4 (at 0 -5) (layer F.SilkS) 6 | (effects (font (size 1 1) (thickness 0.15))) 7 | ) 8 | (fp_line (start -2.25 1.75) (end -2.25 2.25) (layer F.SilkS) (width 0.15)) 9 | (fp_line (start -2.25 2.25) (end -1.75 2.25) (layer F.SilkS) (width 0.15)) 10 | (fp_line (start -2 -2) (end 2 -2) (layer F.SilkS) (width 0.15)) 11 | (fp_line (start 2 -2) (end 2 2) (layer F.SilkS) (width 0.15)) 12 | (fp_line (start 2 2) (end -2 2) (layer F.SilkS) (width 0.15)) 13 | (fp_line (start -2 2) (end -2 -2) (layer F.SilkS) (width 0.15)) 14 | (pad 1 smd oval (at -1.25 1.8) (size 0.3 0.7) (layers F.Cu F.Paste F.Mask)) 15 | (pad 2 smd oval (at -0.75 1.8) (size 0.3 0.7) (layers F.Cu F.Paste F.Mask)) 16 | (pad 3 smd oval (at -0.25 1.8) (size 0.3 0.7) (layers F.Cu F.Paste F.Mask)) 17 | (pad 4 smd oval (at 0.25 1.8) (size 0.3 0.7) (layers F.Cu F.Paste F.Mask)) 18 | (pad 5 smd oval (at 0.75 1.8) (size 0.3 0.7) (layers F.Cu F.Paste F.Mask)) 19 | (pad 6 smd oval (at 1.25 1.8) (size 0.3 0.7) (layers F.Cu F.Paste F.Mask)) 20 | (pad 13 smd oval (at 1.25 -1.8) (size 0.3 0.7) (layers F.Cu F.Paste F.Mask)) 21 | (pad 14 smd oval (at 0.75 -1.8) (size 0.3 0.7) (layers F.Cu F.Paste F.Mask)) 22 | (pad 15 smd oval (at 0.25 -1.8) (size 0.3 0.7) (layers F.Cu F.Paste F.Mask)) 23 | (pad 16 smd oval (at -0.25 -1.8) (size 0.3 0.7) (layers F.Cu F.Paste F.Mask)) 24 | (pad 17 smd oval (at -0.75 -1.8) (size 0.3 0.7) (layers F.Cu F.Paste F.Mask)) 25 | (pad 18 smd oval (at -1.25 -1.8) (size 0.3 0.7) (layers F.Cu F.Paste F.Mask)) 26 | (pad 19 smd oval (at -1.8 -1.25 90) (size 0.3 0.7) (layers F.Cu F.Paste F.Mask)) 27 | (pad 20 smd oval (at -1.8 -0.75 90) (size 0.3 0.7) (layers F.Cu F.Paste F.Mask)) 28 | (pad 21 smd oval (at -1.8 -0.25 90) (size 0.3 0.7) (layers F.Cu F.Paste F.Mask)) 29 | (pad 22 smd oval (at -1.8 0.25 90) (size 0.3 0.7) (layers F.Cu F.Paste F.Mask)) 30 | (pad 23 smd oval (at -1.8 0.75 90) (size 0.3 0.7) (layers F.Cu F.Paste F.Mask)) 31 | (pad 7 smd oval (at 1.8 1.25 90) (size 0.3 0.7) (layers F.Cu F.Paste F.Mask)) 32 | (pad 8 smd oval (at 1.8 0.76 90) (size 0.3 0.7) (layers F.Cu F.Paste F.Mask)) 33 | (pad 9 smd oval (at 1.8 0.25 90) (size 0.3 0.7) (layers F.Cu F.Paste F.Mask)) 34 | (pad 10 smd oval (at 1.8 -0.25 90) (size 0.3 0.7) (layers F.Cu F.Paste F.Mask)) 35 | (pad 11 smd oval (at 1.8 -0.75 90) (size 0.3 0.7) (layers F.Cu F.Paste F.Mask)) 36 | (pad 12 smd oval (at 1.8 -1.25 90) (size 0.3 0.7) (layers F.Cu F.Paste F.Mask)) 37 | (pad 24 smd oval (at -1.8 1.25 90) (size 0.3 0.7) (layers F.Cu F.Paste F.Mask)) 38 | (pad PAD smd rect (at 0 0) (size 2.5 2.5) (layers F.Cu F.Paste F.Mask)) 39 | (pad PAD thru_hole circle (at 0 0) (size 0.3 0.3) (drill 0.3) (layers *.Cu F.SilkS F.Mask) 40 | (zone_connect 2)) 41 | (pad PAD thru_hole circle (at 0 -0.65) (size 0.3 0.3) (drill 0.3) (layers *.Cu F.SilkS F.Mask) 42 | (zone_connect 2)) 43 | (pad PAD thru_hole circle (at 0.65 0.65) (size 0.3 0.3) (drill 0.3) (layers *.Cu F.SilkS F.Mask) 44 | (zone_connect 2)) 45 | (pad PAD thru_hole circle (at 0 0.65) (size 0.3 0.3) (drill 0.3) (layers *.Cu F.SilkS F.Mask) 46 | (zone_connect 2)) 47 | (pad PAD thru_hole circle (at 0.65 0) (size 0.3 0.3) (drill 0.3) (layers *.Cu F.SilkS F.Mask) 48 | (zone_connect 2)) 49 | (pad PAD thru_hole circle (at 0.65 -0.65) (size 0.3 0.3) (drill 0.3) (layers *.Cu F.SilkS F.Mask) 50 | (zone_connect 2)) 51 | (pad PAD thru_hole circle (at -0.65 -0.65) (size 0.3 0.3) (drill 0.3) (layers *.Cu F.SilkS F.Mask) 52 | (zone_connect 2)) 53 | (pad PAD thru_hole circle (at -0.65 0) (size 0.3 0.3) (drill 0.3) (layers *.Cu F.SilkS F.Mask) 54 | (zone_connect 2)) 55 | (pad PAD thru_hole circle (at -0.65 0.65) (size 0.3 0.3) (drill 0.3) (layers *.Cu F.SilkS F.Mask) 56 | (zone_connect 2)) 57 | ) 58 | -------------------------------------------------------------------------------- /hw/vna.pretty/VFQFN-32.kicad_mod: -------------------------------------------------------------------------------- 1 | (module VFQFN-32 (layer F.Cu) (tedit 56489F4B) 2 | (fp_text reference REF** (at 0.115 3.55) (layer F.SilkS) 3 | (effects (font (size 0.6 0.6) (thickness 0.125))) 4 | ) 5 | (fp_text value VFQFN-32 (at -0.085 -3.55) (layer F.Fab) 6 | (effects (font (size 0.6 0.6) (thickness 0.15))) 7 | ) 8 | (fp_line (start -2.185 -2.85) (end -2.785 -2.85) (layer F.SilkS) (width 0.15)) 9 | (fp_line (start -2.785 -2.85) (end -2.785 -2.25) (layer F.SilkS) (width 0.15)) 10 | (fp_line (start -2.485 2.45) (end -2.485 -2.55) (layer F.SilkS) (width 0.15)) 11 | (fp_line (start -2.485 -2.55) (end 2.515 -2.55) (layer F.SilkS) (width 0.15)) 12 | (fp_line (start 2.515 -2.55) (end 2.515 2.45) (layer F.SilkS) (width 0.15)) 13 | (fp_line (start 2.515 2.45) (end -2.485 2.45) (layer F.SilkS) (width 0.15)) 14 | (pad 1 smd oval (at -2.315 -1.75) (size 0.8 0.34) (layers F.Cu F.Paste F.Mask)) 15 | (pad 2 smd oval (at -2.315 -1.25) (size 0.8 0.34) (layers F.Cu F.Paste F.Mask)) 16 | (pad 3 smd oval (at -2.315 -0.75) (size 0.8 0.34) (layers F.Cu F.Paste F.Mask)) 17 | (pad 4 smd oval (at -2.315 -0.25) (size 0.8 0.34) (layers F.Cu F.Paste F.Mask)) 18 | (pad 5 smd oval (at -2.315 0.25) (size 0.8 0.34) (layers F.Cu F.Paste F.Mask)) 19 | (pad 6 smd oval (at -2.315 0.75) (size 0.8 0.34) (layers F.Cu F.Paste F.Mask)) 20 | (pad 7 smd oval (at -2.315 1.25) (size 0.8 0.34) (layers F.Cu F.Paste F.Mask)) 21 | (pad 8 smd oval (at -2.315 1.75) (size 0.8 0.34) (layers F.Cu F.Paste F.Mask)) 22 | (pad 17 smd oval (at 2.315 1.75) (size 0.8 0.34) (layers F.Cu F.Paste F.Mask)) 23 | (pad 18 smd oval (at 2.315 1.25) (size 0.8 0.34) (layers F.Cu F.Paste F.Mask)) 24 | (pad 19 smd oval (at 2.315 0.75) (size 0.8 0.34) (layers F.Cu F.Paste F.Mask)) 25 | (pad 20 smd oval (at 2.315 0.25) (size 0.8 0.34) (layers F.Cu F.Paste F.Mask)) 26 | (pad 21 smd oval (at 2.315 -0.25) (size 0.8 0.34) (layers F.Cu F.Paste F.Mask)) 27 | (pad 22 smd oval (at 2.315 -0.75) (size 0.8 0.34) (layers F.Cu F.Paste F.Mask)) 28 | (pad 23 smd oval (at 2.315 -1.25) (size 0.8 0.34) (layers F.Cu F.Paste F.Mask)) 29 | (pad 24 smd oval (at 2.315 -1.75) (size 0.8 0.34) (layers F.Cu F.Paste F.Mask)) 30 | (pad 9 smd oval (at -1.75 2.315 90) (size 0.8 0.34) (layers F.Cu F.Paste F.Mask)) 31 | (pad EP smd rect (at 0 0) (size 3.08 3.08) (layers F.Cu F.Paste F.Mask)) 32 | (pad 10 smd oval (at -1.25 2.315 90) (size 0.8 0.34) (layers F.Cu F.Paste F.Mask)) 33 | (pad 11 smd oval (at -0.75 2.315 90) (size 0.8 0.34) (layers F.Cu F.Paste F.Mask)) 34 | (pad 12 smd oval (at -0.25 2.315 90) (size 0.8 0.34) (layers F.Cu F.Paste F.Mask)) 35 | (pad 13 smd oval (at 0.25 2.315 90) (size 0.8 0.34) (layers F.Cu F.Paste F.Mask)) 36 | (pad 14 smd oval (at 0.75 2.315 90) (size 0.8 0.34) (layers F.Cu F.Paste F.Mask)) 37 | (pad 15 smd oval (at 1.25 2.315 90) (size 0.8 0.34) (layers F.Cu F.Paste F.Mask)) 38 | (pad 16 smd oval (at 1.75 2.315 90) (size 0.8 0.34) (layers F.Cu F.Paste F.Mask)) 39 | (pad 25 smd oval (at 1.75 -2.315 90) (size 0.8 0.34) (layers F.Cu F.Paste F.Mask)) 40 | (pad 26 smd oval (at 1.25 -2.315 90) (size 0.8 0.34) (layers F.Cu F.Paste F.Mask)) 41 | (pad 27 smd oval (at 0.75 -2.315 90) (size 0.8 0.34) (layers F.Cu F.Paste F.Mask)) 42 | (pad 28 smd oval (at 0.25 -2.315 90) (size 0.8 0.34) (layers F.Cu F.Paste F.Mask)) 43 | (pad 29 smd oval (at -0.25 -2.315 90) (size 0.8 0.34) (layers F.Cu F.Paste F.Mask)) 44 | (pad 30 smd oval (at -0.75 -2.315 90) (size 0.8 0.34) (layers F.Cu F.Paste F.Mask)) 45 | (pad 31 smd oval (at -1.25 -2.315 90) (size 0.8 0.3) (layers F.Cu F.Paste F.Mask)) 46 | (pad 32 smd oval (at -1.75 -2.315 90) (size 0.8 0.34) (layers F.Cu F.Paste F.Mask)) 47 | (pad EP thru_hole circle (at 0 0) (size 0.5 0.5) (drill 0.3) (layers *.Cu) 48 | (zone_connect 2)) 49 | (pad EP thru_hole circle (at -1 -1) (size 0.5 0.5) (drill 0.3) (layers *.Cu) 50 | (zone_connect 2)) 51 | (pad EP thru_hole circle (at 1 -1) (size 0.5 0.5) (drill 0.3) (layers *.Cu) 52 | (zone_connect 2)) 53 | (pad EP thru_hole circle (at -1 1) (size 0.5 0.5) (drill 0.3) (layers *.Cu) 54 | (zone_connect 2)) 55 | (pad EP thru_hole circle (at 1 1) (size 0.5 0.5) (drill 0.3) (layers *.Cu) 56 | (zone_connect 2)) 57 | (pad EP thru_hole circle (at 1 0) (size 0.5 0.5) (drill 0.3) (layers *.Cu) 58 | (zone_connect 2)) 59 | (pad EP thru_hole circle (at 0 -1) (size 0.5 0.5) (drill 0.3) (layers *.Cu) 60 | (zone_connect 2)) 61 | (pad EP thru_hole circle (at -1 0) (size 0.5 0.5) (drill 0.3) (layers *.Cu) 62 | (zone_connect 2)) 63 | (pad EP thru_hole circle (at 0 1) (size 0.5 0.5) (drill 0.3) (layers *.Cu) 64 | (zone_connect 2)) 65 | ) 66 | -------------------------------------------------------------------------------- /hw/vna.pretty/VQFN-16.kicad_mod: -------------------------------------------------------------------------------- 1 | (module VQFN-16 (layer F.Cu) (tedit 564A388D) 2 | (fp_text reference VQFN-16 (at 0 -3.3) (layer F.SilkS) 3 | (effects (font (size 1 1) (thickness 0.15))) 4 | ) 5 | (fp_text value VAL** (at 0 3.25) (layer F.SilkS) 6 | (effects (font (size 1 1) (thickness 0.15))) 7 | ) 8 | (fp_line (start -1.25 -1.75) (end -1.75 -1.75) (layer F.SilkS) (width 0.15)) 9 | (fp_line (start -1.75 -1.75) (end -1.75 -1.25) (layer F.SilkS) (width 0.15)) 10 | (fp_line (start -1.5 -1.5) (end 1.5 -1.5) (layer F.SilkS) (width 0.15)) 11 | (fp_line (start 1.5 -1.5) (end 1.5 1.5) (layer F.SilkS) (width 0.15)) 12 | (fp_line (start 1.5 1.5) (end -1.5 1.5) (layer F.SilkS) (width 0.15)) 13 | (fp_line (start -1.5 1.5) (end -1.5 -1.5) (layer F.SilkS) (width 0.15)) 14 | (pad 1 smd rect (at -1.35 -0.75 90) (size 0.25 0.5) (layers F.Cu F.Paste F.Mask)) 15 | (pad 2 smd rect (at -1.35 -0.25 90) (size 0.25 0.5) (layers F.Cu F.Paste F.Mask)) 16 | (pad 3 smd rect (at -1.35 0.25 90) (size 0.25 0.5) (layers F.Cu F.Paste F.Mask)) 17 | (pad 4 smd rect (at -1.35 0.75 90) (size 0.25 0.5) (layers F.Cu F.Paste F.Mask)) 18 | (pad 5 smd rect (at -0.75 1.35) (size 0.25 0.5) (layers F.Cu F.Paste F.Mask)) 19 | (pad 6 smd rect (at -0.25 1.35) (size 0.25 0.5) (layers F.Cu F.Paste F.Mask)) 20 | (pad 7 smd rect (at 0.25 1.35) (size 0.25 0.5) (layers F.Cu F.Paste F.Mask)) 21 | (pad 8 smd rect (at 0.75 1.35) (size 0.25 0.5) (layers F.Cu F.Paste F.Mask)) 22 | (pad 9 smd rect (at 1.35 0.75 90) (size 0.25 0.5) (layers F.Cu F.Paste F.Mask)) 23 | (pad 10 smd rect (at 1.35 0.25 90) (size 0.25 0.5) (layers F.Cu F.Paste F.Mask)) 24 | (pad 11 smd rect (at 1.35 -0.25 90) (size 0.25 0.5) (layers F.Cu F.Paste F.Mask)) 25 | (pad 12 smd rect (at 1.35 -0.75 90) (size 0.25 0.5) (layers F.Cu F.Paste F.Mask)) 26 | (pad 13 smd rect (at 0.75 -1.35) (size 0.25 0.5) (layers F.Cu F.Paste F.Mask)) 27 | (pad 14 smd rect (at 0.25 -1.35) (size 0.25 0.5) (layers F.Cu F.Paste F.Mask)) 28 | (pad 15 smd rect (at -0.25 -1.35) (size 0.25 0.5) (layers F.Cu F.Paste F.Mask)) 29 | (pad 16 smd rect (at -0.75 -1.35) (size 0.25 0.5) (layers F.Cu F.Paste F.Mask)) 30 | (pad EP smd rect (at 0 0) (size 1.8 1.8) (layers F.Cu F.Paste F.Mask)) 31 | (pad EP thru_hole circle (at -0.45 -0.45) (size 0.3 0.3) (drill 0.3) (layers *.Cu F.SilkS F.Mask) 32 | (zone_connect 2)) 33 | (pad EP thru_hole circle (at -0.45 0.45) (size 0.3 0.3) (drill 0.3) (layers *.Cu F.SilkS F.Mask) 34 | (zone_connect 2)) 35 | (pad EP thru_hole circle (at 0.45 -0.45) (size 0.3 0.3) (drill 0.3) (layers *.Cu F.SilkS F.Mask) 36 | (zone_connect 2)) 37 | (pad EP thru_hole circle (at 0.45 0.45) (size 0.3 0.3) (drill 0.3) (layers *.Cu F.SilkS F.Mask) 38 | (zone_connect 2)) 39 | (pad EP thru_hole circle (at 0 0) (size 0.3 0.3) (drill 0.3) (layers *.Cu F.SilkS F.Mask) 40 | (zone_connect 2)) 41 | ) 42 | -------------------------------------------------------------------------------- /hw/vna.pretty/VQFN-24.kicad_mod: -------------------------------------------------------------------------------- 1 | (module VQFN-24 (layer F.Cu) (tedit 5648A4F4) 2 | (fp_text reference VQFN-24 (at 0 -3.3) (layer F.SilkS) 3 | (effects (font (size 1 1) (thickness 0.15))) 4 | ) 5 | (fp_text value VAL** (at 0 3.25) (layer F.SilkS) 6 | (effects (font (size 1 1) (thickness 0.15))) 7 | ) 8 | (fp_line (start -2.25 1.75) (end -2.25 2.25) (layer F.SilkS) (width 0.15)) 9 | (fp_line (start -2.25 2.25) (end -1.75 2.25) (layer F.SilkS) (width 0.15)) 10 | (fp_line (start -2 -2) (end 2 -2) (layer F.SilkS) (width 0.15)) 11 | (fp_line (start 2 -2) (end 2 2) (layer F.SilkS) (width 0.15)) 12 | (fp_line (start 2 2) (end -2 2) (layer F.SilkS) (width 0.15)) 13 | (fp_line (start -2 2) (end -2 -2) (layer F.SilkS) (width 0.15)) 14 | (pad 1 smd rect (at -1.25 1.9) (size 0.25 0.7) (layers F.Cu F.Paste F.Mask)) 15 | (pad 2 smd rect (at -0.75 1.9) (size 0.25 0.7) (layers F.Cu F.Paste F.Mask)) 16 | (pad 3 smd rect (at -0.25 1.9) (size 0.25 0.7) (layers F.Cu F.Paste F.Mask)) 17 | (pad 4 smd rect (at 0.25 1.9) (size 0.25 0.7) (layers F.Cu F.Paste F.Mask)) 18 | (pad 5 smd rect (at 0.75 1.9) (size 0.25 0.7) (layers F.Cu F.Paste F.Mask)) 19 | (pad 6 smd rect (at 1.25 1.9) (size 0.25 0.7) (layers F.Cu F.Paste F.Mask)) 20 | (pad 13 smd rect (at 1.25 -1.9) (size 0.25 0.7) (layers F.Cu F.Paste F.Mask)) 21 | (pad 14 smd rect (at 0.75 -1.9) (size 0.25 0.7) (layers F.Cu F.Paste F.Mask)) 22 | (pad 15 smd rect (at 0.25 -1.9) (size 0.25 0.7) (layers F.Cu F.Paste F.Mask)) 23 | (pad 16 smd rect (at -0.25 -1.9) (size 0.25 0.7) (layers F.Cu F.Paste F.Mask)) 24 | (pad 17 smd rect (at -0.75 -1.9) (size 0.25 0.7) (layers F.Cu F.Paste F.Mask)) 25 | (pad 18 smd rect (at -1.25 -1.9) (size 0.25 0.7) (layers F.Cu F.Paste F.Mask)) 26 | (pad 19 smd rect (at -1.9 -1.25 90) (size 0.25 0.7) (layers F.Cu F.Paste F.Mask)) 27 | (pad 20 smd rect (at -1.9 -0.75 90) (size 0.25 0.7) (layers F.Cu F.Paste F.Mask)) 28 | (pad 21 smd rect (at -1.9 -0.25 90) (size 0.25 0.7) (layers F.Cu F.Paste F.Mask)) 29 | (pad 22 smd rect (at -1.9 0.25 90) (size 0.25 0.7) (layers F.Cu F.Paste F.Mask)) 30 | (pad 23 smd rect (at -1.9 0.75 90) (size 0.25 0.7) (layers F.Cu F.Paste F.Mask)) 31 | (pad 7 smd rect (at 1.9 1.25 90) (size 0.25 0.7) (layers F.Cu F.Paste F.Mask)) 32 | (pad 8 smd rect (at 1.9 0.76 90) (size 0.25 0.7) (layers F.Cu F.Paste F.Mask)) 33 | (pad 9 smd rect (at 1.9 0.25 90) (size 0.25 0.7) (layers F.Cu F.Paste F.Mask)) 34 | (pad 10 smd rect (at 1.9 -0.25 90) (size 0.25 0.7) (layers F.Cu F.Paste F.Mask)) 35 | (pad 11 smd rect (at 1.9 -0.75 90) (size 0.25 0.7) (layers F.Cu F.Paste F.Mask)) 36 | (pad 12 smd rect (at 1.9 -1.25 90) (size 0.25 0.7) (layers F.Cu F.Paste F.Mask)) 37 | (pad 24 smd rect (at -1.9 1.25 90) (size 0.25 0.7) (layers F.Cu F.Paste F.Mask)) 38 | (pad EP smd rect (at 0 0) (size 2.7 2.7) (layers F.Cu F.Paste F.Mask)) 39 | (pad EP thru_hole circle (at 0 0) (size 0.3 0.3) (drill 0.3) (layers *.Cu F.SilkS F.Mask) 40 | (zone_connect 2)) 41 | (pad EP thru_hole circle (at -0.5 -0.5) (size 0.3 0.3) (drill 0.3) (layers *.Cu F.SilkS F.Mask) 42 | (zone_connect 2)) 43 | (pad EP thru_hole circle (at -1 -1) (size 0.3 0.3) (drill 0.3) (layers *.Cu F.SilkS F.Mask) 44 | (zone_connect 2)) 45 | (pad EP thru_hole circle (at 0 -1) (size 0.3 0.3) (drill 0.3) (layers *.Cu F.SilkS F.Mask) 46 | (zone_connect 2)) 47 | (pad EP thru_hole circle (at 1 -1) (size 0.3 0.3) (drill 0.3) (layers *.Cu F.SilkS F.Mask) 48 | (zone_connect 2)) 49 | (pad EP thru_hole circle (at 0.5 -0.5) (size 0.3 0.3) (drill 0.3) (layers *.Cu F.SilkS F.Mask) 50 | (zone_connect 2)) 51 | (pad EP thru_hole circle (at -1 0) (size 0.3 0.3) (drill 0.3) (layers *.Cu F.SilkS F.Mask) 52 | (zone_connect 2)) 53 | (pad EP thru_hole circle (at 1 0) (size 0.3 0.3) (drill 0.3) (layers *.Cu F.SilkS F.Mask) 54 | (zone_connect 2)) 55 | (pad EP thru_hole circle (at -0.5 0.5) (size 0.3 0.3) (drill 0.3) (layers *.Cu F.SilkS F.Mask) 56 | (zone_connect 2)) 57 | (pad EP thru_hole circle (at 0.5 0.5) (size 0.3 0.3) (drill 0.3) (layers *.Cu F.SilkS F.Mask) 58 | (zone_connect 2)) 59 | (pad EP thru_hole circle (at -1 1) (size 0.3 0.3) (drill 0.3) (layers *.Cu F.SilkS F.Mask) 60 | (zone_connect 2)) 61 | (pad EP thru_hole circle (at 0 1) (size 0.3 0.3) (drill 0.3) (layers *.Cu F.SilkS F.Mask) 62 | (zone_connect 2)) 63 | (pad EP thru_hole circle (at 1 1) (size 0.3 0.3) (drill 0.3) (layers *.Cu F.SilkS F.Mask) 64 | (zone_connect 2)) 65 | ) 66 | -------------------------------------------------------------------------------- /hw/vna.pretty/WFBGA-6.kicad_mod: -------------------------------------------------------------------------------- 1 | (module WFBGA-6 (layer F.Cu) (tedit 56AC6684) 2 | (fp_text reference REF** (at 0 1.35) (layer F.SilkS) 3 | (effects (font (size 0.7 0.7) (thickness 0.15))) 4 | ) 5 | (fp_text value WFBGA-6 (at 0 -1.65) (layer F.Fab) 6 | (effects (font (size 1 1) (thickness 0.15))) 7 | ) 8 | (fp_line (start -0.85 -0.85) (end -0.25 -0.85) (layer F.SilkS) (width 0.15)) 9 | (fp_line (start -0.45 -0.65) (end 0.45 -0.65) (layer F.SilkS) (width 0.15)) 10 | (fp_line (start 0.45 -0.65) (end 0.45 0.65) (layer F.SilkS) (width 0.15)) 11 | (fp_line (start 0.45 0.65) (end -0.45 0.65) (layer F.SilkS) (width 0.15)) 12 | (fp_line (start -0.45 0.65) (end -0.45 -0.65) (layer F.SilkS) (width 0.15)) 13 | (pad A1 smd circle (at -0.2 -0.4) (size 0.22 0.22) (layers F.Cu F.Paste F.Mask) 14 | (solder_mask_margin 0.05)) 15 | (pad A2 smd circle (at 0.2 -0.4) (size 0.22 0.22) (layers F.Cu F.Paste F.Mask) 16 | (solder_mask_margin 0.05)) 17 | (pad B1 smd circle (at -0.2 0) (size 0.22 0.22) (layers F.Cu F.Paste F.Mask) 18 | (solder_mask_margin 0.05)) 19 | (pad B2 smd circle (at 0.2 0) (size 0.22 0.22) (layers F.Cu F.Paste F.Mask) 20 | (solder_mask_margin 0.05)) 21 | (pad C1 smd circle (at -0.2 0.4) (size 0.22 0.22) (layers F.Cu F.Paste F.Mask) 22 | (solder_mask_margin 0.05)) 23 | (pad C2 smd circle (at 0.2 0.4) (size 0.22 0.22) (layers F.Cu F.Paste F.Mask) 24 | (solder_mask_margin 0.05)) 25 | ) 26 | -------------------------------------------------------------------------------- /hw/vna.pretty/WFDFN-8.kicad_mod: -------------------------------------------------------------------------------- 1 | (module WFDFN-8 (layer F.Cu) (tedit 55A927D3) 2 | (fp_text reference REF** (at 0.025 1.775) (layer F.SilkS) 3 | (effects (font (size 0.5 0.5) (thickness 0.125))) 4 | ) 5 | (fp_text value WFDFN-8 (at 0.075 -1.875) (layer F.Fab) 6 | (effects (font (size 1 1) (thickness 0.15))) 7 | ) 8 | (fp_line (start -1 1) (end -1 -1) (layer F.SilkS) (width 0.15)) 9 | (fp_line (start -1 -1) (end 1 -1) (layer F.SilkS) (width 0.15)) 10 | (fp_line (start 1 -1) (end 1 1) (layer F.SilkS) (width 0.15)) 11 | (fp_line (start 1 1) (end -1 1) (layer F.SilkS) (width 0.15)) 12 | (pad 9 smd rect (at 0 0) (size 1.5 0.9) (layers F.Cu F.Paste F.Mask)) 13 | (pad 1 smd rect (at -0.75 0.95) (size 0.25 0.5) (layers F.Cu F.Paste F.Mask)) 14 | (pad 2 smd rect (at -0.25 0.95) (size 0.25 0.5) (layers F.Cu F.Paste F.Mask)) 15 | (pad 3 smd rect (at 0.25 0.95) (size 0.25 0.5) (layers F.Cu F.Paste F.Mask)) 16 | (pad 4 smd rect (at 0.75 0.95) (size 0.25 0.5) (layers F.Cu F.Paste F.Mask)) 17 | (pad 5 smd rect (at 0.75 -0.95) (size 0.25 0.5) (layers F.Cu F.Paste F.Mask)) 18 | (pad 6 smd rect (at 0.25 -0.95) (size 0.25 0.5) (layers F.Cu F.Paste F.Mask)) 19 | (pad 7 smd rect (at -0.25 -0.95) (size 0.25 0.5) (layers F.Cu F.Paste F.Mask)) 20 | (pad 8 smd rect (at -0.75 -0.95) (size 0.25 0.5) (layers F.Cu F.Paste F.Mask)) 21 | (model Housings_DFN_QFN.3dshapes/DFN-6-1EP_2x2mm_Pitch0.5mm.wrl 22 | (at (xyz 0 0 0)) 23 | (scale (xyz 1 1 1)) 24 | (rotate (xyz 0 0 90)) 25 | ) 26 | ) 27 | -------------------------------------------------------------------------------- /hw/vna.pretty/XDFN-2.kicad_mod: -------------------------------------------------------------------------------- 1 | (module XDFN-2 (layer F.Cu) (tedit 55A40369) 2 | (fp_text reference REF** (at 0.475 1) (layer F.SilkS) 3 | (effects (font (size 0.5 0.5) (thickness 0.125))) 4 | ) 5 | (fp_text value XDFN-2 (at 0 -1.2) (layer F.Fab) 6 | (effects (font (size 1 1) (thickness 0.15))) 7 | ) 8 | (fp_line (start -0.2 0.4) (end -0.2 -0.4) (layer F.SilkS) (width 0.15)) 9 | (fp_line (start -0.2 -0.4) (end 1.4 -0.4) (layer F.SilkS) (width 0.15)) 10 | (fp_line (start 1.4 -0.4) (end 1.4 0.4) (layer F.SilkS) (width 0.15)) 11 | (fp_line (start 1.4 0.4) (end -0.2 0.4) (layer F.SilkS) (width 0.15)) 12 | (pad 2 smd rect (at 0 0) (size 0.385 0.69) (layers F.Cu F.Paste F.Mask)) 13 | (pad 1 smd rect (at 0.912 0) (size 1.035 0.69) (layers F.Cu F.Paste F.Mask)) 14 | ) 15 | -------------------------------------------------------------------------------- /hw/vna.pretty/XFDFN-6.kicad_mod: -------------------------------------------------------------------------------- 1 | (module XFDFN-6 (layer F.Cu) (tedit 551FA82D) 2 | (fp_text reference XFDFN-6 (at -0.1 -5.4) (layer F.SilkS) 3 | (effects (font (size 1 1) (thickness 0.15))) 4 | ) 5 | (fp_text value VAL** (at 0 5) (layer F.SilkS) 6 | (effects (font (size 1 1) (thickness 0.15))) 7 | ) 8 | (fp_line (start 0.075 -0.5) (end -0.3 -0.5) (layer F.SilkS) (width 0.15)) 9 | (fp_line (start -0.3 -0.5) (end -0.3 -0.275) (layer F.SilkS) (width 0.15)) 10 | (fp_line (start -0.025 1.25) (end -0.025 -0.25) (layer F.SilkS) (width 0.15)) 11 | (fp_line (start -0.025 -0.25) (end 1.475 -0.25) (layer F.SilkS) (width 0.15)) 12 | (fp_line (start 1.475 -0.25) (end 1.475 1.25) (layer F.SilkS) (width 0.15)) 13 | (fp_line (start 1.475 1.25) (end -0.025 1.25) (layer F.SilkS) (width 0.15)) 14 | (pad 1 smd rect (at 0 0) (size 0.35 0.25) (layers F.Cu F.Paste F.Mask)) 15 | (pad 2 smd rect (at 0 0.5) (size 0.35 0.25) (layers F.Cu F.Paste F.Mask)) 16 | (pad 3 smd rect (at 0 1) (size 0.35 0.25) (layers F.Cu F.Paste F.Mask)) 17 | (pad 4 smd rect (at 1.45 1) (size 0.35 0.25) (layers F.Cu F.Paste F.Mask)) 18 | (pad 5 smd rect (at 1.45 0.5) (size 0.35 0.25) (layers F.Cu F.Paste F.Mask)) 19 | (pad 6 smd rect (at 1.45 0) (size 0.35 0.25) (layers F.Cu F.Paste F.Mask)) 20 | (pad PAD smd rect (at 0.725 0.5) (size 0.7 1.2) (layers F.Cu F.Paste F.Mask)) 21 | (pad PAD smd rect (at 0.725 -0.125) (size 0.2 0.05) (layers F.Cu F.Paste F.Mask)) 22 | (pad PAD smd rect (at 0.725 1.125) (size 0.2 0.05) (layers F.Cu F.Paste F.Mask)) 23 | ) 24 | -------------------------------------------------------------------------------- /hw/vna.pretty/XTAL_3.2x2.5.kicad_mod: -------------------------------------------------------------------------------- 1 | (module XTAL_3.2x2.5 (layer F.Cu) (tedit 5579B9EE) 2 | (fp_text reference REF** (at 0 2.4) (layer F.SilkS) 3 | (effects (font (size 1 1) (thickness 0.15))) 4 | ) 5 | (fp_text value XTAL_3.2x2.5 (at 0 -2.5) (layer F.Fab) 6 | (effects (font (size 1 1) (thickness 0.15))) 7 | ) 8 | (fp_line (start -1.6 1.2) (end -1.6 -1.3) (layer F.SilkS) (width 0.15)) 9 | (fp_line (start -1.6 -1.3) (end 1.6 -1.3) (layer F.SilkS) (width 0.15)) 10 | (fp_line (start 1.6 -1.3) (end 1.6 1.2) (layer F.SilkS) (width 0.15)) 11 | (fp_line (start 1.6 1.2) (end -1.6 1.2) (layer F.SilkS) (width 0.15)) 12 | (pad 1 smd rect (at -1.4 0.8) (size 1.4 1.2) (layers F.Cu F.Paste F.Mask)) 13 | (pad 2 smd rect (at 1.2 0.8) (size 1.4 1.2) (layers F.Cu F.Paste F.Mask)) 14 | (pad 3 smd rect (at 1.2 -0.9) (size 1.4 1.2) (layers F.Cu F.Paste F.Mask)) 15 | (pad 4 smd rect (at -1.4 -0.9) (size 1.4 1.2) (layers F.Cu F.Paste F.Mask)) 16 | ) 17 | -------------------------------------------------------------------------------- /hw/vna.pretty/coupler4.kicad_mod: -------------------------------------------------------------------------------- 1 | (module coupler4 (layer F.Cu) (tedit 564B55DF) 2 | (fp_text reference F1 (at 0.1 3) (layer F.SilkS) hide 3 | (effects (font (thickness 0.3))) 4 | ) 5 | (fp_text value COUPLER (at 0.4 -2.5) (layer F.SilkS) hide 6 | (effects (font (thickness 0.3))) 7 | ) 8 | (fp_poly (pts (xy 8.997557 1.365147) (xy -8.997557 1.365147) (xy -8.997557 1.07557) (xy 8.997557 1.07557) 9 | (xy 8.997557 1.365147)) (layer In2.Cu) (width 0)) 10 | (fp_poly (pts (xy -8.025408 0.661889) (xy -0.97215 0.661889) (xy -0.97215 -1.365146) (xy -0.682574 -1.365146) 11 | (xy -0.682574 0.631834) (xy -1.004092 0.951466) (xy -8.016036 0.951466) (xy -8.335668 0.629948) 12 | (xy -8.335668 -1.365146) (xy -8.025408 -1.365146) (xy -8.025408 0.661889)) (layer In2.Cu) (width 0)) 13 | (fp_poly (pts (xy 0.972149 0.661889) (xy 8.025407 0.661889) (xy 8.025407 -1.365146) (xy 8.335667 -1.365146) 14 | (xy 8.335667 0.631834) (xy 8.014149 0.951466) (xy 1.002205 0.951466) (xy 0.682573 0.629948) 15 | (xy 0.682573 -1.365146) (xy 0.972149 -1.365146) (xy 0.972149 0.661889)) (layer In2.Cu) (width 0)) 16 | (pad 1 thru_hole circle (at -9 1.2) (size 0.55 0.55) (drill 0.26) (layers *.Cu *.Mask F.SilkS)) 17 | (pad GND thru_hole circle (at -9 0.3) (size 0.55 0.55) (drill 0.26) (layers *.Cu *.Mask F.SilkS) 18 | (zone_connect 2)) 19 | (pad GND thru_hole circle (at -9 2.1) (size 0.55 0.55) (drill 0.26) (layers *.Cu *.Mask F.SilkS) 20 | (zone_connect 2)) 21 | (pad 2 thru_hole circle (at 9 1.2) (size 0.58 0.58) (drill 0.26) (layers *.Cu *.Mask F.SilkS)) 22 | (pad GND thru_hole circle (at 9 0.3) (size 0.58 0.58) (drill 0.26) (layers *.Cu *.Mask F.SilkS) 23 | (zone_connect 2)) 24 | (pad GND thru_hole circle (at 9 2.1) (size 0.58 0.58) (drill 0.26) (layers *.Cu *.Mask F.SilkS) 25 | (zone_connect 2)) 26 | (pad 3 thru_hole circle (at -8.2 -1.4) (size 0.58 0.58) (drill 0.26) (layers *.Cu *.Mask F.SilkS)) 27 | (pad 4 thru_hole circle (at -0.8 -1.4) (size 0.58 0.58) (drill 0.26) (layers *.Cu *.Mask F.SilkS)) 28 | (pad 5 thru_hole circle (at 0.8 -1.4) (size 0.58 0.58) (drill 0.26) (layers *.Cu *.Mask F.SilkS)) 29 | (pad 6 thru_hole circle (at 8.2 -1.4) (size 0.58 0.58) (drill 0.26) (layers *.Cu *.Mask F.SilkS)) 30 | (pad GND thru_hole circle (at 0 -1.7) (size 0.58 0.58) (drill 0.26) (layers *.Cu *.Mask F.SilkS) 31 | (zone_connect 2)) 32 | (pad GND thru_hole circle (at -1.7 -1.4) (size 0.58 0.58) (drill 0.26) (layers *.Cu *.Mask F.SilkS) 33 | (zone_connect 2)) 34 | (pad GND thru_hole circle (at 1.7 -1.4) (size 0.58 0.58) (drill 0.26) (layers *.Cu *.Mask F.SilkS) 35 | (zone_connect 2)) 36 | (pad GND thru_hole circle (at 9.1 -1.4) (size 0.58 0.58) (drill 0.26) (layers *.Cu *.Mask F.SilkS) 37 | (zone_connect 2)) 38 | (pad GND thru_hole circle (at 7.3 -1.4) (size 0.58 0.58) (drill 0.26) (layers *.Cu *.Mask F.SilkS) 39 | (zone_connect 2)) 40 | (pad GND thru_hole circle (at -7.3 -1.4) (size 0.58 0.58) (drill 0.26) (layers *.Cu *.Mask F.SilkS) 41 | (zone_connect 2)) 42 | (pad GND thru_hole circle (at -9.1 -1.4) (size 0.58 0.58) (drill 0.26) (layers *.Cu *.Mask F.SilkS) 43 | (zone_connect 2)) 44 | ) 45 | -------------------------------------------------------------------------------- /hw/vna.pretty/uwmiter_0.34_0.17_45.kicad_mod: -------------------------------------------------------------------------------- 1 | (module uwmiter_0.34_0.17_45 (layer F.Cu) (tedit 569FDDF6) 2 | (fp_text reference uwmiter_0.34_0.17_45 (at 0 1.34) (layer F.SilkS) hide 3 | (effects (font (size 0.7 0.8) (thickness 0.15))) 4 | ) 5 | (fp_text value Val*** (at 0 2.34) (layer F.SilkS) hide 6 | (effects (font (size 0.7 0.8) (thickness 0.15))) 7 | ) 8 | (fp_poly (pts (xy 0 0) (xy 0.34 0) (xy 0.34 0.17) (xy 0.460208 0.290208) 9 | (xy 0.219791 0.530624) (xy 0.129199 0.440032) (xy 0 0.128116) (xy 0 0)) (layer F.Cu) (width 0)) 10 | (pad 1 smd rect (at 0.17 -0.017) (size 0.34 0.15) (layers F.Cu) 11 | (clearance 0.000001)) 12 | (pad 2 smd rect (at 0.35202 0.422437 315) (size 0.15 0.34) (layers F.Cu) 13 | (clearance 0.000001)) 14 | ) 15 | -------------------------------------------------------------------------------- /hw/vna.pretty/uwmiter_0.34_0.17_90.kicad_mod: -------------------------------------------------------------------------------- 1 | (module uwmiter_0.34_0.17_90 (layer F.Cu) (tedit 0) 2 | (fp_text reference uwmiter_0.34_0.17_90 (at 0 1.34) (layer F.SilkS) hide 3 | (effects (font (size 0.7 0.8) (thickness 0.15))) 4 | ) 5 | (fp_text value Val*** (at 0 2.34) (layer F.SilkS) hide 6 | (effects (font (size 0.7 0.8) (thickness 0.15))) 7 | ) 8 | (fp_poly (pts (xy 0 0) (xy 0.34 0) (xy 0.34 0.17) (xy 0.51 0.17) 9 | (xy 0.509999 0.51) (xy 0.3808 0.51) (xy 0 0.129199) (xy 0 0)) (layer F.Cu) (width 0)) 10 | (pad 1 smd rect (at 0.17 -0.017) (size 0.34 0.034) (layers F.Cu) 11 | (clearance 0.000001)) 12 | (pad 2 smd rect (at 0.526999 0.34) (size 0.034 0.34) (layers F.Cu) 13 | (clearance 0.000001)) 14 | ) 15 | -------------------------------------------------------------------------------- /hw/vna2.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Ttl/vna2/2cf0efb22da56a168a7f07bf5e2c30631343997b/hw/vna2.pdf -------------------------------------------------------------------------------- /hw/vna2.pro: -------------------------------------------------------------------------------- 1 | update=ke 8. maaliskuuta 2017 19.36.10 2 | version=1 3 | last_client=kicad 4 | [pcbnew] 5 | version=1 6 | LastNetListRead= 7 | UseCmpFile=1 8 | PadDrill=0.600000000000 9 | PadDrillOvalY=0.600000000000 10 | PadSizeH=1.500000000000 11 | PadSizeV=1.500000000000 12 | PcbTextSizeV=1.500000000000 13 | PcbTextSizeH=1.500000000000 14 | PcbTextThickness=0.300000000000 15 | ModuleTextSizeV=1.000000000000 16 | ModuleTextSizeH=1.000000000000 17 | ModuleTextSizeThickness=0.150000000000 18 | SolderMaskClearance=0.000000000000 19 | SolderMaskMinWidth=0.000000000000 20 | DrawSegmentWidth=0.200000000000 21 | BoardOutlineThickness=0.100000000000 22 | ModuleOutlineThickness=0.150000000000 23 | [cvpcb] 24 | version=1 25 | NetIExt=net 26 | [general] 27 | version=1 28 | [eeschema] 29 | version=1 30 | LibDir= 31 | [eeschema/libraries] 32 | LibName1=power 33 | LibName2=device 34 | LibName3=transistors 35 | LibName4=conn 36 | LibName5=linear 37 | LibName6=regul 38 | LibName7=74xx 39 | LibName8=cmos4000 40 | LibName9=adc-dac 41 | LibName10=memory 42 | LibName11=xilinx 43 | LibName12=microcontrollers 44 | LibName13=dsp 45 | LibName14=microchip 46 | LibName15=analog_switches 47 | LibName16=motorola 48 | LibName17=texas 49 | LibName18=intel 50 | LibName19=audio 51 | LibName20=interface 52 | LibName21=digital-audio 53 | LibName22=philips 54 | LibName23=display 55 | LibName24=cypress 56 | LibName25=siliconi 57 | LibName26=opto 58 | LibName27=atmel 59 | LibName28=contrib 60 | LibName29=valves 61 | LibName30=lib/vna 62 | [schematic_editor] 63 | version=1 64 | PageLayoutDescrFile= 65 | PlotDirectoryName=vna2.pdf 66 | SubpartIdSeparator=0 67 | SubpartFirstId=65 68 | NetFmtName= 69 | SpiceAjustPassiveValues=0 70 | LabSize=60 71 | ERC_TestSimilarLabels=1 72 | -------------------------------------------------------------------------------- /openocd/interface.cfg: -------------------------------------------------------------------------------- 1 | interface ftdi 2 | ftdi_device_desc "VNA" 3 | ftdi_vid_pid 0x0403 0x6010 4 | ftdi_layout_init 0x0c08 0x0f1b 5 | reset_config none 6 | adapter_khz 3000 7 | 8 | #telnet_port 4444 9 | #gdb_port 3333 10 | transport select jtag 11 | -------------------------------------------------------------------------------- /openocd/program_flash.cfg: -------------------------------------------------------------------------------- 1 | # xilinx series 7 (artix, kintex, virtex) 2 | # http://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf 3 | 4 | if { [info exists CHIPNAME] } { 5 | set _CHIPNAME $CHIPNAME 6 | } else { 7 | set _CHIPNAME xc7 8 | } 9 | 10 | # the 4 top bits (28:31) are the die stepping/revisions. ignore it. 11 | jtag newtap $_CHIPNAME tap -irlen 6 -ignore-version \ 12 | -expected-id 0x0362E093 \ 13 | -expected-id 0x0362D093 \ 14 | -expected-id 0x0362D093 \ 15 | -expected-id 0x0362C093 \ 16 | -expected-id 0x03632093 \ 17 | -expected-id 0x03631093 \ 18 | -expected-id 0x03636093 \ 19 | -expected-id 0x03647093 \ 20 | -expected-id 0x0364C093 \ 21 | -expected-id 0x03651093 \ 22 | -expected-id 0x03747093 \ 23 | -expected-id 0x03656093 \ 24 | -expected-id 0x03752093 \ 25 | -expected-id 0x03751093 \ 26 | -expected-id 0x03671093 \ 27 | -expected-id 0x036B3093 \ 28 | -expected-id 0x036B7093 \ 29 | -expected-id 0x036BB093 \ 30 | -expected-id 0x036BF093 \ 31 | -expected-id 0x03667093 \ 32 | -expected-id 0x03682093 \ 33 | -expected-id 0x03687093 \ 34 | -expected-id 0x03692093 \ 35 | -expected-id 0x03691093 \ 36 | -expected-id 0x03696093 \ 37 | -expected-id 0x036D5093 \ 38 | -expected-id 0x036D9093 \ 39 | -expected-id 0x036DB093 40 | 41 | pld device virtex2 $_CHIPNAME.tap 1 42 | 43 | set XC7_JSHUTDOWN 0x0d 44 | set XC7_JPROGRAM 0x0b 45 | set XC7_JSTART 0x0c 46 | set XC7_BYPASS 0x3f 47 | 48 | proc xc7_program {tap} { 49 | global XC7_JSHUTDOWN XC7_JPROGRAM XC7_JSTART XC7_BYPASS 50 | irscan $tap $XC7_JSHUTDOWN 51 | irscan $tap $XC7_JPROGRAM 52 | runtest 60000 53 | #JSTART prevents this from working... 54 | #irscan $tap $XC7_JSTART 55 | runtest 2000 56 | irscan $tap $XC7_BYPASS 57 | runtest 2000 58 | } 59 | 60 | source [find cpld/jtagspi.cfg] 61 | 62 | init 63 | jtagspi_init 0 xc7_bscan_spi.bit 64 | jtagspi_program vna_top.bin 0 65 | xc7_program xc7.tap 66 | pld load 0 vna_top.bit 67 | exit 68 | -------------------------------------------------------------------------------- /openocd/program_fpga.cfg: -------------------------------------------------------------------------------- 1 | source [find cpld/xilinx-xc7.cfg] 2 | 3 | init 4 | xc7_program xc7.tap 5 | pld load 0 vna_top.bit 6 | exit 7 | -------------------------------------------------------------------------------- /openocd/xc7_bscan_spi.bit: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Ttl/vna2/2cf0efb22da56a168a7f07bf5e2c30631343997b/openocd/xc7_bscan_spi.bit -------------------------------------------------------------------------------- /software/monitor_rx.py: -------------------------------------------------------------------------------- 1 | # -*- coding: utf-8 -*- 2 | 3 | from vna import VNA 4 | import matplotlib.pyplot as plt 5 | import numpy as np 6 | from pyqtgraph.Qt import QtGui, QtCore 7 | import pyqtgraph as pg 8 | 9 | plot_points = 1000 10 | 11 | def init_vna(): 12 | ref_freq = 40e6 13 | 14 | vna = VNA() 15 | 16 | source_freq = 5e9 17 | lo_freq = source_freq - 2e6 18 | 19 | vna.set_tx_mux('iq', sample_input='adc') 20 | 21 | vna.lo.freq_to_regs(lo_freq, ref_freq, apwr=0) 22 | vna.source.freq_to_regs(source_freq, ref_freq, apwr=0) 23 | 24 | #vna.dither_en(1) 25 | #vna.set_tx_mux('samples', sample_input='adc') 26 | 27 | vna.write_sample_time(int(40e6/100+100)) 28 | #vna.write_sample_time(110000) 29 | vna.write_io(pwdn=0, mixer_enable=0, led=1, adc_oe=0, adc_shdn=0) 30 | vna.write_pll_io(lo_ce=1, source_ce=1, lo_rf=1, source_rf=1) 31 | vna.write_att(8.0) 32 | vna.write_switches(tx_filter=source_freq, port=1, rx_sw='rx1', rx_sw_force=False) 33 | vna.write_pll(vna.source) 34 | vna.write_pll(vna.lo) 35 | vna.write_pll(vna.source) 36 | vna.write_pll(vna.lo) 37 | 38 | vna.read_iq() 39 | vna.read_iq() 40 | return vna 41 | 42 | vna = init_vna() 43 | iqs = {'rx1':[], 'rx2':[], 'a':[], 'b':[], 'none':[], 'unknown':[]} 44 | 45 | app = QtGui.QApplication([]) 46 | 47 | win = pg.GraphicsWindow(title="RX channels") 48 | #win.resize(1000,600) 49 | win.setWindowTitle('RX channels') 50 | 51 | # Enable antialiasing for prettier plots 52 | pg.setConfigOptions(antialias=True) 53 | 54 | plot = win.addPlot(title="RX channels", labels={'left':'Channel reading [dBFs]', 'bottom':'Samples'}) 55 | curve1 = plot.plot(pen='y', name='RX1') 56 | curve2 = plot.plot(pen='g', name='A') 57 | curve3 = plot.plot(pen='r', name='B') 58 | curve4 = plot.plot(pen='b', name='RX2') 59 | plot.addLegend() 60 | plot.legend.addItem(curve1, "RX1") 61 | plot.legend.addItem(curve2, "A") 62 | plot.legend.addItem(curve3, "B") 63 | plot.legend.addItem(curve4, "RX2") 64 | plot.enableAutoRange('xy', False) 65 | plot.setXRange(0, plot_points, padding=0) 66 | plot.setYRange(-100, 0, padding=0) 67 | 68 | def update(): 69 | global iqs, vna, curve1, curve2, plot 70 | for i in range(4): 71 | iq,sw,tag = vna.read_iq() 72 | iqs[sw].append(20*np.log10(np.abs(iq))) 73 | #iqs[sw].append(np.angle(iq)) 74 | rx1 = iqs['rx1'][-plot_points:] 75 | rx1 = [-100]*(plot_points-len(rx1)) + rx1 76 | a = iqs['a'][-plot_points:] 77 | a = [-100]*(plot_points-len(a)) + a 78 | b = iqs['b'][-plot_points:] 79 | b = [-100]*(plot_points-len(b)) + b 80 | rx2 = iqs['rx2'][-plot_points:] 81 | rx2 = [-100]*(plot_points-len(rx2)) + rx2 82 | curve1.setData(rx1) 83 | curve2.setData(a) 84 | curve3.setData(b) 85 | curve4.setData(rx2) 86 | timer = QtCore.QTimer() 87 | timer.timeout.connect(update) 88 | timer.start(10) 89 | 90 | ## Start Qt event loop unless running in interactive mode or using pyside. 91 | if __name__ == '__main__': 92 | import sys 93 | if (sys.flags.interactive != 1) or not hasattr(QtCore, 'PYQT_VERSION'): 94 | QtGui.QApplication.instance().exec_() 95 | 96 | -------------------------------------------------------------------------------- /software/monitor_sparam.py: -------------------------------------------------------------------------------- 1 | # -*- coding: utf-8 -*- 2 | 3 | from vna import VNA 4 | import matplotlib.pyplot as plt 5 | import numpy as np 6 | from pyqtgraph.Qt import QtGui, QtCore 7 | import pyqtgraph as pg 8 | 9 | plot_points = 500 10 | 11 | def init_vna(): 12 | ref_freq = 40e6 13 | 14 | vna = VNA() 15 | 16 | source_freq = 3.5e9 17 | lo_freq = source_freq - 2e6 18 | 19 | vna.lo.freq_to_regs(lo_freq, ref_freq, apwr=0) 20 | vna.source.freq_to_regs(source_freq, ref_freq, apwr=0) 21 | 22 | #vna.dither_en(1) 23 | vna.set_tx_mux('iq', sample_input='adc') 24 | #vna.set_tx_mux('samples', sample_input='adc') 25 | 26 | vna.write_sample_time(int(40e6/1000+100)) 27 | #vna.write_sample_time(110000) 28 | vna.write_io(pwdn=0, mixer_enable=0, led=1, adc_oe=0, adc_shdn=0) 29 | vna.write_pll_io(lo_ce=1, source_ce=1, lo_rf=1, source_rf=1) 30 | vna.write_att(3.0) 31 | vna.write_switches(tx_filter=source_freq, port=1, rx_sw='rx2', rx_sw_force=False) 32 | vna.write_pll(vna.source) 33 | vna.write_pll(vna.lo) 34 | vna.write_pll(vna.source) 35 | vna.write_pll(vna.lo) 36 | 37 | vna.read_iq() 38 | vna.read_iq() 39 | return vna 40 | 41 | vna = init_vna() 42 | iqs = {'rx1':[], 'rx2':[], 'a':[], 'b':[], 'none':[], 'unknown':[]} 43 | 44 | app = QtGui.QApplication([]) 45 | 46 | win = pg.GraphicsWindow(title="RX channels") 47 | #win.resize(1000,600) 48 | win.setWindowTitle('RX channels') 49 | 50 | # Enable antialiasing for prettier plots 51 | pg.setConfigOptions(antialias=True) 52 | 53 | plot = win.addPlot(title="S-parameters", labels={'left':'Magnitude [dB]', 'bottom':'Samples'}) 54 | curve1 = plot.plot(pen='y', name='S11') 55 | curve2 = plot.plot(pen='g', name='S12') 56 | plot.addLegend() 57 | plot.legend.addItem(curve1, "S11") 58 | plot.legend.addItem(curve2, "S21") 59 | plot.enableAutoRange('xy', False) 60 | plot.setXRange(0, plot_points, padding=0) 61 | plot.setYRange(-100, 0, padding=0) 62 | 63 | def update(): 64 | global iqs, vna, curve1, curve2, plot 65 | for i in range(4): 66 | iq,sw,tag = vna.read_iq() 67 | iqs[sw].append(iq) 68 | rx1 = iqs['rx1'][-plot_points:] 69 | rx1 = np.array([-100]*(plot_points-len(rx1)) + rx1) 70 | a = iqs['a'][-plot_points:] 71 | a = np.array([-100]*(plot_points-len(a)) + a) 72 | b = iqs['b'][-plot_points:] 73 | b = np.array([-100]*(plot_points-len(b)) + b) 74 | #rx2 = iqs['rx2'][-plot_points:] 75 | #rx2 = [-100]*(plot_points-len(rx2)) + rx2 76 | curve1.setData(20*np.log10(np.abs(a/rx1))) 77 | curve2.setData(20*np.log10(np.abs(b/rx1))) 78 | #curve1.setData(180/np.pi*np.angle(a/rx1)) 79 | #curve2.setData(180/np.pi*np.angle(b/rx1)) 80 | timer = QtCore.QTimer() 81 | timer.timeout.connect(update) 82 | timer.start(10) 83 | 84 | ## Start Qt event loop unless running in interactive mode or using pyside. 85 | if __name__ == '__main__': 86 | import sys 87 | if (sys.flags.interactive != 1) or not hasattr(QtCore, 'PYQT_VERSION'): 88 | QtGui.QApplication.instance().exec_() 89 | 90 | -------------------------------------------------------------------------------- /software/oneport/calibrate.py: -------------------------------------------------------------------------------- 1 | import sys 2 | import skrf 3 | import matplotlib.pyplot as plt 4 | import numpy as np 5 | skrf.stylely() 6 | 7 | def tline_input(zl, z0, t, f): 8 | c = 299792458 9 | w = c/f 10 | b = np.pi*2/w 11 | l = t*c 12 | return z0*(zl+1j*z0*np.tan(b*l))/(z0+1j*zl*np.tan(b*l)) 13 | 14 | def gamma(zl, z0): 15 | return (zl-z0)/(zl+z0) 16 | 17 | def make_open(freqs, c0, c1, c2, c3, offset_t, offset_z0): 18 | c_coefs = [c0*1e-15, c1*1e-27, c2*1e-36, c3*1e-45] 19 | 20 | reactance = [] 21 | for f in freqs: 22 | c = 0 23 | for i in xrange(len(c_coefs)): 24 | c += c_coefs[i]*f**i 25 | xc = (-1.0j/(2*np.pi*f*c)) 26 | reactance.append(xc) 27 | reactance = np.array(reactance) 28 | sparam = gamma(tline_input(reactance, offset_z0, offset_t, freqs), 50) 29 | 30 | return skrf.Network(s=sparam, f=freqs, f_unit='Hz') 31 | 32 | def make_short(freqs, l0, l1, l2, l3, offset_t, offset_z0): 33 | c_coefs = [l0*1e-12, l1*1e-24, l2*1e-34, l3*1e-42] 34 | 35 | reactance = [] 36 | for f in freqs: 37 | c = 0 38 | for i in xrange(len(c_coefs)): 39 | c += c_coefs[i]*f**i 40 | xc = (1.0j*2*np.pi*f*c) 41 | reactance.append(xc) 42 | reactance = np.array(reactance) 43 | sparam = gamma(tline_input(reactance, offset_z0, offset_t, freqs), 50) 44 | 45 | return skrf.Network(s=sparam, f=freqs, f_unit='Hz') 46 | 47 | def make_load(freqs, r0, l0, l1, l2, l3, offset_t, offset_z0): 48 | c_coefs = [l0*1e-12, l1*1e-24, l2*1e-34, l3*1e-42] 49 | 50 | reactance = [] 51 | for f in freqs: 52 | c = 0 53 | for i in xrange(len(c_coefs)): 54 | c += c_coefs[i]*f**i 55 | xc = (1.0j*2*np.pi*f*c) 56 | reactance.append(xc) 57 | reactance = np.array(reactance) 58 | sparam = gamma(tline_input(r0+reactance, offset_z0, offset_t, freqs), 50) 59 | 60 | return skrf.Network(s=sparam, f=freqs, f_unit='Hz') 61 | 62 | 63 | o = skrf.Network('open.s1p') 64 | s = skrf.Network('short.s1p') 65 | l = skrf.Network('load.s1p') 66 | dut = skrf.Network(sys.argv[1]) 67 | 68 | freqs = o.frequency 69 | 70 | o_i = skrf.Network('../cal_kit/open.s1p') 71 | s_i = skrf.Network('../cal_kit/short.s1p') 72 | l_i = skrf.Network('../cal_kit/load.s1p') 73 | 74 | o_i = o_i.interpolate(freqs) 75 | s_i = s_i.interpolate(freqs) 76 | l_i = l_i.interpolate(freqs) 77 | 78 | #o_i = make_open(freqs, 4.46941071, -1353.09191861, 2189.61227292, -143.3687188, 31.1e-12, 50) 79 | #s_i = make_short(freqs, 64.1413939, -11375.46199962, -3975.09654213, -77.69120398, 31.1e-12 ,50) 80 | #l_i = make_load(freqs, 50.0, 95.97419879, -61.62497249, 262.22809906, -881.59180129, 31.1e-12, 50) 81 | 82 | 83 | 84 | cal = skrf.OnePort(\ 85 | measured = [o, s, l], 86 | ideals =[o_i, s_i, l_i] 87 | ) 88 | 89 | coefs = cal.coefs 90 | print coefs.keys() 91 | 92 | for k in coefs.keys(): 93 | plt.figure() 94 | plt.title(k) 95 | plt.plot(20*np.log10(np.abs(coefs[k]))) 96 | 97 | plt.figure() 98 | dut_cal = cal.apply_cal(dut) 99 | dut_cal.plot_s_db() 100 | plt.show(block=True) 101 | 102 | -------------------------------------------------------------------------------- /software/sparam.py: -------------------------------------------------------------------------------- 1 | 2 | from vna import VNA 3 | import matplotlib.pyplot as plt 4 | import numpy as np 5 | import time 6 | import skrf 7 | import pickle 8 | 9 | def iq_to_sparam(iqs, freqs, ports, sw_correction=True): 10 | sparams = [] 11 | 12 | if len(ports) == 1: 13 | for f in range(len(freqs)): 14 | if ports[0] == 1: 15 | s = iqs[f][('a',1)]/iqs[f][('rx1',1)] 16 | else: 17 | s = iqs[f][('b',2)]/iqs[f][('rx2',2)] 18 | sparams.append(s) 19 | elif len(ports) == 2: 20 | for f in range(len(freqs)): 21 | s11 = [] 22 | s12 = [] 23 | s21 = [] 24 | s22 = [] 25 | if sw_correction: 26 | D = 1.0 - (iqs[f][('rx2',1)]/iqs[f][('rx1',1)])*(iqs[f][('rx1',2)]/iqs[f][('rx2',2)]) 27 | sm11 = (1.0/D)*( iqs[f][('a',1)]/iqs[f][('rx1',1)] - (iqs[f][('a',2)]/iqs[f][('rx2',2)])*(iqs[f][('rx2',1)]/iqs[f][('rx1',1)]) ) 28 | sm12 = (1.0/D)*( iqs[f][('a',2)]/iqs[f][('rx2',2)] - (iqs[f][('a',1)]/iqs[f][('rx1',1)])*(iqs[f][('rx1',2)]/iqs[f][('rx2',2)]) ) 29 | sm21 = (1.0/D)*( iqs[f][('b',1)]/iqs[f][('rx1',1)] - (iqs[f][('b',2)]/iqs[f][('rx2',2)])*(iqs[f][('rx2',1)]/iqs[f][('rx1',1)]) ) 30 | sm22 = (1.0/D)*( iqs[f][('b',2)]/iqs[f][('rx2',2)] - (iqs[f][('b',1)]/iqs[f][('rx1',1)])*(iqs[f][('rx1',2)]/iqs[f][('rx2',2)]) ) 31 | else: 32 | sm11 = iqs[f][('a',1)]/iqs[f][('rx1',1)] 33 | sm12 = iqs[f][('a',2)]/iqs[f][('rx2',2)] 34 | sm21 = iqs[f][('b',1)]/iqs[f][('rx1',1)] 35 | sm22 = iqs[f][('b',2)]/iqs[f][('rx2',2)] 36 | s11.append(sm11) 37 | s12.append(sm12) 38 | s21.append(sm21) 39 | s22.append(sm22) 40 | sparams.append( [[np.mean(s11), np.mean(s12)], [np.mean(s21), np.mean(s22)]] ) 41 | 42 | return skrf.Network(s=sparams, f=freqs, f_unit='Hz') 43 | 44 | def sw_terms(iqs, freqs): 45 | """Switch terms from IQ""" 46 | sparams = [] 47 | 48 | for f in range(len(freqs)): 49 | sw_f = iqs[f][('rx2',1)]/iqs[f][('b',1)] 50 | sw_r = iqs[f][('rx1',2)]/iqs[f][('a',2)] 51 | sparams.append( [[sw_f, 0], [0, sw_r]] ) 52 | 53 | return skrf.Network(s=sparams, f=freqs, f_unit='Hz') 54 | 55 | 56 | vna = VNA() 57 | 58 | ports = [1, 2] 59 | sw_correction = True 60 | 61 | freqs = np.linspace(30e6, 8.5e9, 801) 62 | 63 | vna.set_tx_mux('iq', sample_input='adc') 64 | vna.write_att(7.0) 65 | vna.write_sample_time(int(40e6/1000+100)) 66 | vna.write_io(pwdn=0, mixer_enable=0, led=1, adc_oe=0, adc_shdn=0) 67 | vna.write_pll_io(lo_ce=1, source_ce=1, lo_rf=1, source_rf=1) 68 | iqs = [{} for i in range(len(freqs))] 69 | 70 | time.sleep(0.5) 71 | 72 | first = True 73 | for port in ports: 74 | tag = 1 75 | for e,freq in enumerate(freqs): 76 | if freq > 4.5e9: 77 | vna.write_att(0) 78 | vna.write_switches(tx_filter=freq, port=port, rx_sw='rx1') 79 | vna.program_sources(freq, 2e6) 80 | if first: 81 | time.sleep(20e-3) 82 | vna.write_pll(vna.lo) 83 | vna.write_pll(vna.source) 84 | first = False 85 | for i in range(4): 86 | iq, sw, t = vna.read_iq() 87 | time.sleep(1e-3) 88 | vna.write_tag(tag) 89 | i = 0 90 | while True: 91 | iq, sw, t = vna.read_iq() 92 | if t != tag: 93 | continue 94 | i += 1 95 | iqs[e].setdefault((sw,port), iq) 96 | 97 | print(freq, sw, 20*np.log10(np.abs(iq))) 98 | if i == 4: 99 | break 100 | tag = (tag + 1) % 256 101 | 102 | plt.figure() 103 | net = iq_to_sparam(iqs, freqs, ports, sw_correction=sw_correction) 104 | net.plot_s_db() 105 | net.write_touchstone('response.s{}p'.format(net.nports)) 106 | 107 | if not sw_correction and len(ports) == 2: 108 | sw = sw_terms(iqs, freqs) 109 | sw.write_touchstone('sw_terms.s2p') 110 | 111 | pickle.dump( (freqs, iqs), open( "iqs.p", "wb" ) ) 112 | plt.ylim([-100, 0]) 113 | plt.show() 114 | -------------------------------------------------------------------------------- /software/twoport/calibrate.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python 2 | import skrf 3 | import matplotlib.pyplot as plt 4 | import numpy as np 5 | import sys 6 | skrf.stylely() 7 | 8 | # Calibration standards measured as two-port 9 | # Can be one-port and then combined as two-port 10 | # when not using SixteenTerm calibration 11 | oo = skrf.Network('open_open.s2p') 12 | ss = skrf.Network('short_short.s2p') 13 | ll = skrf.Network('load_load.s2p') 14 | through = skrf.Network('through.s2p') 15 | 16 | freqs = through.f 17 | frequency = through.frequency 18 | 19 | o_i = skrf.Network('../cal_kit/open.s1p') 20 | s_i = skrf.Network('../cal_kit/short.s1p') 21 | l_i = skrf.Network('../cal_kit/load.s1p') 22 | 23 | o_i = o_i.interpolate(frequency) 24 | s_i = s_i.interpolate(frequency) 25 | l_i = l_i.interpolate(frequency) 26 | 27 | ll_i = skrf.two_port_reflect(l_i, l_i) 28 | ss_i = skrf.two_port_reflect(s_i, s_i) 29 | oo_i = skrf.two_port_reflect(o_i, o_i) 30 | 31 | #Make ideal through 32 | through_z0 = 46 33 | through_delay = 100e-12 34 | d = 2*np.pi*through_delay 35 | att = np.log(10**(-0.1/20))/6e9 36 | g = d+1j*att 37 | through_s = [[[0,np.exp(-1j*g*f)],[np.exp(-1j*g*f),0]] for f in freqs] 38 | through_i = skrf.Network(s=through_s, f=freqs, f_unit='Hz', z0=through_z0) 39 | through_i.renormalize(50) 40 | 41 | ll_i = skrf.two_port_reflect(l_i, l_i) 42 | ls_i = skrf.two_port_reflect(l_i, s_i) 43 | sl_i = skrf.two_port_reflect(s_i, l_i) 44 | ss_i = skrf.two_port_reflect(s_i, s_i) 45 | oo_i = skrf.two_port_reflect(o_i, o_i) 46 | 47 | if 0: 48 | # Classic VNA calibration 49 | cal = skrf.TwelveTerm(\ 50 | measured = [oo, ss, ll, through], 51 | ideals =[oo_i, ss_i, ll_i, through_i], 52 | isolation=ll, 53 | n_thrus = 1, 54 | ) 55 | cal.run() 56 | elif 1: 57 | # Doesn't require fully known through standard 58 | cal = skrf.UnknownThru(\ 59 | measured = [oo, ss, ll, through], 60 | ideals =[oo_i, ss_i, ll_i, through_i], 61 | n_thrus = 1, 62 | ) 63 | cal.run() 64 | elif 0: 65 | sl = skrf.Network('short_load.s2p') 66 | ls = skrf.Network('load_short.s2p') 67 | # Calibrates leakage terms 68 | cal = skrf.SixteenTerm(\ 69 | measured = [oo, ss, sl, ls, ll, through], 70 | ideals =[oo_i, ss_i, sl_i, ls_i, ll_i, through_i], 71 | n_thrus = 1, 72 | ) 73 | cal.run() 74 | 75 | if 0: 76 | # Plot calibration error terms 77 | coefs = cal.coefs 78 | for k in list(coefs.keys()): 79 | plt.figure() 80 | plt.title(k) 81 | plt.plot(freqs, 20*np.log10(np.abs(coefs[k]))) 82 | 83 | plt.figure(figsize=(8,5)) 84 | for dut in sys.argv[1:]: 85 | dut = skrf.Network(dut) 86 | dut.frequency.unit = "GHz" 87 | dut = cal.apply_cal(dut) 88 | dut.plot_s_db() 89 | 90 | dut.write_touchstone('dut_calibrated.s2p') 91 | plt.show(block=True) 92 | --------------------------------------------------------------------------------